A Low Stress Bond Pad Design for Low Temperature Solder Interconnections on Through Silicon Vias (TSVs

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Xiaowu Zhang, R. Rajoo, C. S. Selvanayagam, C S Premachandran, W. K. Choi, S. W. Ho, S. W. Ong, Ling Xie, D. Pinjala, V. N. Sekhar, D.-L. Kwong Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Singapore Science Park II, Singapore 117685, xiaowu@ime.a-star.edu.sg, Tel: (65) 67705423; Fax: (65) 67745747 Abstract Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design. Introduction 3D chip-stacking technology with TSVs is the next generation integration technology for IC packaging. The benefits of 3D integration with TSV technology for future ICs include reduced interconnection delay due to shorter chip to chip interconnection lengths, smaller die size which is motivated by the portable and hand held applications, and ability to use distinct, even heterogeneous technologies (analog, logic, RF, MEMS, SiGe, III-V) on separate vertically interconnected layers to build complex systems [1-13]. In the new applications (such as Bio, MEMS, Optical, and RF devices), the vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. The current method uses higher temperature of more than 300°C for bonding and interconnecting the different devices or wafers in the vertical fashion [8]. A high bonding temperature degrades the performance and sensitivity of the Bio, MEMS, Optical, and RF devices. Therefore, a low temperature bonding at less than 200°C is a must for vertically integrating the different systems such as multifunctional devices into a system in package. However, low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints that fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above throughsilicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This phenomenon is expected in thin interconnects and microbumps which are placed on TSVs. TSV 200µm D2 D1 (750 µm thickness) Fig 1: Schematic of stacked dies fabricated by low temperature bonding This paper presents a novel pad design to overcome the situation of high stress in the joints. This results in significantly decreased tensile stress. This proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design. Test vehicle description Fig. 1 shows schematic of stacked dies fabricated by low temperature bonding. Table 1 shows the test vehicle specification. The test vehicle had ~600 I/O with 200-300 µm pitch. Die 1 has a size of 10.1 x 10.4 mm without TSV. Die 2 has a size of 9 x 8 mm with TSV. Die 3 has a size of 8 x 5 mm with TSV. The test vehicle for the die stacking was fabricated on 8” Si wafers with SiO2 coating. Thin IMC interconnection (~5µm) D3 200µm

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1657 2010 Electronic Components and Technology Conference

2: Mesh and materials constituting (a) Global model (b) Submodel Mechanical modeling and analysis Mechanical modeling simulations were carried out to determine the effectiveness of the proposed design. the tensile stresses which tend to pry open the joint were compared for two designs – the conventional pad (i. In particular. On the other hand. 3 shows the stress contour in the axial direction in submodel. the submodelling method was used. a large model with a coarse mesh is first modeled as shown in Fig. The tensile stress along the mid-plane of the IMC joint for the two above-mentioned models is shown in Fig. 2(a). a pad design with a cavity at centre that the pad is decouped from the via was proposed.05 μm) (thickness) Passivatio Front side/Back side PECVD SiN/ polymer n (PI) PI materials (InterVia) UBM Sputtered Ti (1KA) /Au (1 μm) Solder Thin film Indium In-based solder based (Evaporated) Die 1 Table 2: material properties used in modeling Material Cu Si Si Bond Ti oxide (IMC) 130 130 70 80 116 Young’s Modulus (GPa) 0. All material properties are shown in Table 2.2 mm TSV (tapered shape) 100 μm / 50 μm RDL Materials Ti (1 kA)/ Cu (1 μm)/ Au (0.28 0.e.1 x 10.Table 1: Test vehicle specification Size 10. usual full pad) and the proposed pad design.38 17 Conductivity -1K-1) (Wm 240 (0) Plastic 250 (0. With this method.34 0. The structures modeled include the TSV.16 0. Tensile stress in IMC joint used to assess effectiveness of ring pad design compared to full pad.008) properties 260 (0. The temperature loading for stress analysis is from 180ºC to 25ºC.3 0.41 8.2 mm TSV (tapered shape) 100 μm /50 μm Die 3 Size 8 x 5 mm Thickness 0. The copper material is modeled as elastic-plastic materials. Fig.9 CTE (10-6/°C) 400 149 1.010) (MPa) (b) silicon Ti pad IMC bond (a) oxide copper via Fig.9 0. Submodel was further simplified into an axi-symmetric model subjected to a temperature change for even quicker analysis of both pad designs. The results from this model are then applied as boundary conditions to a finely-meshed cut-out of the original model.76 mm Die 2 Size 9 x 8 mm Thickness 0. These cut-outs are termed submodels and one such submodel is shown in Fig.. An axi-symmetric model of a single joint was used to simulate the effect of the contracting copper in the via on the interconnect during post formation cool down. 5. There is a stress of about 150MPa in the joint. In order to reduce this stress.4 mm Thickness 0. with the ring pad design the stress at the center decreases to zero because the contraction of the copper in the via no longer pulls the pad 1658 2010 Electronic Components and Technology Conference . It shows that with usual pad design.34 Poisson Ratio 18 2. All materials are modeled as elastic materials except copper material. IMC bonds and the pads.6 11. As the area of concern is the small bond in a large chip-tochip bonded structure. and analysing such a detailed large model would use up a lot of computer time. the joint is in a general state of high stress (150MPa) at the center as copper deforms most in the z-direction. 3: Stress contour S33 in the axial direction in Submodel Fig. 2 (b). Schematic diagrams of the models used for the full pad and ring pad are shown in Figures 4 (a) and (b) respectively.

a sharp curvature is formed at the top. In this etch step. the etched via patterns are mainly subjected to an isotropic etch plasma which is rich in fluorine radical. Support wafer bonding & thinning 5 m joint 35 pads 2. full pad) and ring pad From Fig. The oxygen used helps in sidewall passivation and also controls excessive lateral etch rate. In addition. This general decrease in the stress state of the joint will increase its reliability. 1) A non-BOSCH etch process consisting of a reactive ion etching (RIE) process is used to produce the required tapered sidewall profile. Oxide/barrier/seed deposition & plating 5 m joint ring pad 7-8. There is a comparatively higher stress at the edges of the bond with the ring pad. metallization and UBM 35 m silicon 3. 4: Schematic diagram showing dimensions used in mechanical modelling for (a) full pad and (b) ring pad 200 150 100 Stress (MPa) 50 0 -5 -50 -100 -150 -200 -250 -300 Distance along Path 1 (μm ) Full pad Ring pad 5 15 25 35 5. Back side passivation.. it can be seen that the maximum tensile stress in the joint decreases by 50% with use of the ring pad. As a consequence of this process. De-bonding (a) (b) 4. A proper balance between SF6 and O2 provides the desired taper angle to the via structure.5: Graph of stress (S33) along mid plane of bond for the conventional pad (i. At the end of stage-1 (non-BOSCH process). 6: TSV interposer fabrication process & integration flow Via etching The tapered silicon via has been developed in two stages as follows. The processes involved are silicon tapered via etch. Test vehicle fabrication The TSV fabrication processes using via first approach are achieved for the TSV interposer of 200um thick with daisy chain structure as shown in steps 1-4 of Fig. The wafer is then subjected to a mask-less global isotropic etch process. sidewall dielectric isolation. 2) After completing the stage-1. Via Etch 25 m Cu 200 m 25 m 200 m 5 m 6. the etch mask is fully stripped and cleaned. 5. Front side passivation / pattern Fig. Front side metallization / UBM pattern 10. via Cu plating and Cu chemical mechanical polishing (CMP).e. 1659 2010 Electronic Components and Technology Conference . This is basically a controlled isotropic etch process which uses SF6 + O2 + Ar (Argon) etch chemistry. Back-side solder deposition Fig. As the reaction in this step is mainly chemical in nature and mostly diffusion limited. Cu CMP silicon 9. it reacts more on the rough edges and sharp corners in the top region of the Fig. 1.and the bond upwards. barrier/seed metallization. the required via depth and taper angle is almost achieved except for the sharp curvature at the top. The 50um diameter via is tapered with 83 degree angle. 6. the bond length which experiences maximum stress decreases from 50% in the normal pad to 4% in the ring pad.

Speed of slurry feeding was 185 cc/min. Optical images of top view of front side UBM on TSV wafer is shown in Fig. 8. 9: Final CMP results Cu CMP and annealing A thick layer (~40 μm) of Cu overburden was plated on the wafer surface because of long plating time (~30 hours) required to fill the 200 μm deep via. The speed of pad and chuck was 90 rpm. The wafer bowed due to the thick Cu on the surface. low plating current and pre-treatment (i. 1660 2010 Electronic Components and Technology Conference . 7). Soft polishing pad and strong removal rate slurry from Rohms and Hass were used for the thicker copper removal. 1 μm SiO2 was grown in MFL furnace. The key process parameters are shown in Table 3. The PVD machine used is Tango System AXCECATM.microstructures resulting in a well-rounded smooth sidewalls inside the vias (Fig. The load of polishing was 340g/cm2. H2SO4. Hydrogen and oxygen were mixed in the quartz bulb where they reacted to create a flame and steam water in 1050°C. Okamoto GNX 200 was used for the higher stress Cu CMP.. Conventional photo lithography and electroplating processes were used for RDL fabrication. Under bump metallization (UBM) of Ti/Au was deposited using electroplating. Chemical etching took a long time to remove the thick Cu and resulted in a non-uniform etch. Annealing was carried out after SiN deposition to relieve the internal stresses induced during SiN deposition. and additives including Suppressor. Front side passivation/metallization/UBM processes Front side metallization process starts with SiN deposition and patterning on the planarized Cu filled TSV wafer to isolate the Si surface from the TSV and further metallization. Accelerator and Leveler. RDL materials are Ti/Cu/Au.e. Cl-. Ltd. The typical wafer-level Cu-filled for 200μm deep vias are shown in Fig. The electroplating system used for the via filling is a research system from Rena. Edge of wafer 200µm Barrier (3kA Ti) and Cu seed layer (2μm) has been deposited with help from Tango System. wetting + DI rinsing + pre-absorbing accelerator) are the key contributors to voidfree Cu-filling for the tapered via.. Fig. A suitable method was evaluated for removal of the copper. It should be noted that plating chemistry. Good coverage at via bottom and via side wall has been achieved. 8: X-ray image showing the typical electroplated Cu via Table 3: Key process parameters for barrier/Cu seed layer Process Ti Cu Thickness 3 KA 2 μm DC Power 8 kW 8 kW Coil Power 600 W 600 W Bias Power 1000 W 1000 W Ar Flow / Ch. Pressure 10 / 1. The plating solution is from Shanghai Sinyang Semiconductor Materials Co. Uniformity of SiO2 is within ±5%. 10. Typical composition of an electrolyte includes CuSO4. 7: SEM images of Silicon via after 2nd etching step with well-rounded and smooth sidewall Fig.5 mT 20 / 2 mT Bias Voltage 100 V 150 V Target Voltage 550 V 630 V Dielectric isolation/Barrier/Cu seed layer/Cu via plating The thermal oxidation was used for the isolation in this project. The Cu electroplating solution for the via-filling application can be either copper sulfate or cyanide-based. 9. The oxidation time of Si is three and half hours. Fig. The wafer after final CMP is shown in Fig.

However. to expose the vias at the backside and to bring the interconnects from front side to backside of the TSV wafer. Optical image of TSV after backgrinding and Cu CMP is shown in Fig. As a result. 11. It was observed that 5 µm Cu protrusions were present at the vias which leads litho issues in further dielectric layer process. 12. So. need to thin down to the thickness.10 from Brewer Science was used for thin wafer handling. passivation layer deposition and patterning is required to passivate the Si surface from the backside metallization and to connect the Cu filled TSV to backside metallization respectively. Support wafer bonding was carried out under vacuum of 1 X 10e-4 torr. SiN passivation was replaced with spin-on dielectric InterVia and it was cured at 175ºC for 3 hours to avoid high temperature process. Cu protrusions height was reduced to below 1 µm by introducing CMP process after via exposure and achieved very good Back side passivation/metallization/UBM processes After via exposure. Support wafer de-bonding/Back-side solder deposition After back side metallization process and UBM pattern process. 12: Optical images of back side passivation and opening Fig. 11: Optical images of TSV at the backside of the wafer after via exposer Support wafer bonding & thinning After front side metallization. Electroplate Ti of 1KA thickness/Au of 1µm thickness was used as UBM for low temperature solder bumps on the backside of the wafer. SiN deposition temperature is 250ºC or above. and temporary adhesive material used for support wafer bonding cannot withstand such high temperatures. Optical images of back side passivation with InterVia photodielectric 8023-2 and opening was shown in Fig. Evaluation results showed very good adhesion of InterVia dielectric film to bare Si surface even after critical moisture sensitivity test level 1 (MST L1). final polishing after via exposure was carried out using Si backgrinding and polishing using Si polishing slurry. Finally. and then bonded to the TSV wafer. the wafer with 200 µm deep Cu solid filled vias. Support wafer bonding using temporary adhesive material HT10. Initially. 10: Front side metallization and UBM on TSV wafer Ø 30µm Fig. Generally. Temporary adhesive material of 12 µm thickness was coated on to the support wafer surface and backed at 110ºC for 5 min to remove the solvent from the coated material layer. Cu solid filled TSVs were exposed at the backside of the TSV wafer using Okamoto back grinder/polisher.control on Cu protrusion height by using the Fujimi Cu CMP slurry RDS-10901 with equal etch selectivity for both Si and Cu. optimized support wafer bonding process was successfully achieved to handle 200 µm thick TSV wafer fabrication processes such as via exposer and backside metallization. Table 4: CMP parameters used for Cu protrusions removal Polishing Parameter Units Time 150 sec Load 150 g/cm2 Pad Speed 90 rpm Chuck table speed 80 rpm Slurry feed rate 180 cc/min Fig. at 220ºC with 3500 N force for 5 min using EVG bonder. Backside metallization process was optimized for single RDL of Ti/Cu/Au and InterVia dielectric film of 5 μm as RDL passivation with support wafer. SiN is used for Si isolation from further metallization. support wafer was de-bonded along with dry film layer by sliding the wafer at high temperature of 220-250ºC 1661 2010 Electronic Components and Technology Conference . low cure temperature spin-on dielectric material InterVia was evaluated on bare Si surface in terms of adhesion using peel test. The CMP parameters used for via exposer to reduce the Cu protrusions is tabulated in Table 4. Thin wafer handling system is required to handle 200 µm thick wafer during backside metallization.

0. Results are shown in Fig. C2C process for 3 die stacking is shown in Fig. Finally. In-based low temperature solder metallization was deposited on the Au UBM layer on the 8” TSV wafer with ebeam evaporation chamber. mechanical shear tests were carried out on the bonded samples with two pad designs. After bonding the chips were annealed at 120°C for 12 hours to completely transform the solder into intermetallics (IMC) phase [14].05 µm Au was coated to prevent oxidation of the In-based layer. 1. 13: C2C process for die stacking using low temperature process for comparison of the conventional pad design with the proposed pad design Low temperature bonding process Based on the previous work [14]. 0. C2C bonding process using the low temperature solder The next process was to stack 3 chips using the C2C process. A top view of the proposal pad is shown in Fig. 120°C as an annealing temperature.3 Shear Strength (MPa) 0. 14b: A top view of the proposal pad Mechanical shear tests/drop impact reliability assessment In order to investigate the effect of pad design on the shear strength of the solder joint. the conventional pad design and the new pad design) were used for comparison purpose. A cross-sectional SEM image of the stacked dies fabricated by using the new pad design is shown in Fig. 13. JEDEC drop tests were carried out on the bonded samples with two pad designs. as a bonding time. The bonding temperature was at 180°C and the entire bonding was done at the flip chip bonder. C2C bonding was carried out with the low temperature solder and bonding was done with a highly accurate flip chip bonder. 14b. 15. 1st bonding D2 D1 (750 m thickness) D 2nd bonding Fig. we could manage to bond uniformly with In-based alloy solder at 180°C as the lowest temperature. In short. the bonding temperature was fixed at 180°C. The top two chips were with TSVs while the bottom chip was without TSVs as shown Fig. Results are shown in Fig. In short. The two pad designs (i. 14a: A cross-sectional SEM image of the stacked dies fabricated by using new pad design D3 D1 (750 m thickness) Annealing at 120oC for ~12hrs Fig. 14a.1 0.2 0. 6 MPa as a bonding pressure. In this study. In order to investigate the effect of pad design on the drop impact performance of the solder joint. the optimal condition was obtained as follows: 45 sec. mechanical reliability tests show improvement in reliability with proposed pad design. It is found that the samples with the proposal pad design have a higher shear strength than those with conventional pad design. 16. 15: Influence of pad design on the shear strength of the solder joint 1662 2010 Electronic Components and Technology Conference .e. It is found that the samples with the proposed pad design have a better drop impact performance than those with conventional pad design.25 0.and then followed by dry film stripping and cleaning of adhesive material cleaning on the front side of the wafer using cleaning chemical from brewer Science.05 0 Conventional pad design Proposed pad design Max Min Ave Fig. and the bonding time and the bonding pressure were optimized together with the annealing temperature and time.. test vehicle fabrication for the chip to chip (C2C) stacking with the conventional pad design and the new pad design has been demonstrated 95um 170u Fig.15 0. and 12 hours as an annealing time.

Sunohara. C. May.. 1. “3D chip stacking technology with lowvolume-lead-free interconnections. No. B. T. W. K. Reno. EVG. S. et al. Dang. Nevada. pp. 18-30.. Xiaowu Zhang. 3 A double-sided multilayer metallization process on 200 µm TSV wafer with low temperature and low volume Pbfree solder have been demonstrated. Y. Xie. U. Bang.” Proceedings of the IEEE. P. 52. 7. USA. M. 11. FL. Chartered Semiconductor Manufacturing Ltd. T. S. Patel.. “Development of through silicon via (TSV) interposer technology for large die (21x21mm) fine-pitch Cu/low-k FCBGA package. “Application of piezoresistive stress sensors in ultra thin device handling and characterization. Maria.Project 4 as well as IME staffs who had contributed and made this work possible.. Song. No. USA. L. Y-S. L. 41.. J. H. V.. N. 1193-1198. 538-543. 5.. Sakuma. S. Vol. K. “Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring. STATSChipPAC. Premachandran. 6. Biswas. Manzer. 2008. 4. Physical. of the 59th ECTC.. May. B.. Acknowledgments Part of this work is the result of a project initiated by the 9th IME Electronic Packaging Research Consortium (EPRC9). References 1. Lu. G.” Proc 58th Electronic Components and Technology Conf. D. Some of the important results are summarized below: 1 A novel bond pad (which decouples the interconnect from the TSV) has been designed and simulated to reduce the joint stress by 50%. Chai.. D. Reno. H.g. “Fabrication and characterization of robust through-silicon vias for siliconcarrier applications. Ahmad..” Sensors & Actuators: A. 2008.. Q. C. Ho. San Diego. John H. of the 57th ECTC. Choi.97. Ho. No. Liu. K.. K. Sabuncuoglu. RES. Ong.. E. B. Rao. N. FL. pp725-753. May. Moor. W. pp. 6 (2008). 16: Influence of pad design on the shear strength of the solder joint Conclusions A low stress bond pad design for low temperature solder interconnections on TSVs has made a few significant achievements. V. 2-7. P.” Proc 58th Electronic Components and Technology Conf. barrier/seed metallization. Ruythooren and K. U. Tsang. Ong. T.” Proc 58th Electronic Components and Technology Conf. X. pp. S. T. “Nonlinear thermal stress/strain analyses of copper filled TSV (Through Silicon Via) and their flip-chip microbumps. K.” Proc 57th Electronic Components and Technology Conf. Pham. 13.” IBM J. Vol. 333-338. 627-632.. Selvanayagam. P. S. Kumar. W. pp571-581. No.” Proc. Lake Beuna Vista. Reno. pp. 3. Institute of Microelectronics (IME).. 5 Shear test shows the samples with the proposal pad design have a higher shear strength than those with conventional pad design. J. May 2007. Knickerbocker. Andry.. 4 Drop impact test shows improvement in reliability with proposed pad design. Xiaowu Zhang. the members of which are ASM Technology Singapore Pte Ltd. Knickerbocker. C. 550-555. 12. C. “Sloped through wafer vias for 3D wafer level packaging. S. & DEV. et al. USA. Choi. B.. Kripesh. Y. C. 847-852.. silicon tapered via etch. Lau. et al. Xiaowu Zhang. Seah. Nevada. S. 643-647. Vol. C.” Proc. J. Baert. B. Tsang. Chai. sidewall dielectric isolation. Cho. T. K. pp. S.-Q. Kang. 14. Andry. Webb. May 2009.. Dishing issue on Cu via after Cu CMP has been successfully overcome by using the new pad design. Liao. 8.” Proc. Lau. Majeed. J. The authors are grateful to members of EPRC 9 . Lim. Tokunaga. 49. U. pp. et al. 305-312. 156. Choi. “3-D silicon integration and silicon packaging technology using silicon through-vias. 9.. deep via Cu filling) have been established. J. 2009. 8 (2006).” IEEE Transactions on Advanced Packaging. et al. CA.. Selvanayagam. et al. 4. Vol. Higashi. 32. Sprogis E. Zhang. C. C. E. San Diego. Infineon Technologies Asia Pacific. 2008.” Proc. S. “3-D silicon integration. 720-728.. National Semiconductor. “Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking. J. S. 2 The tapered TSV processes (e. May. Lee. D. K. CA. Nov. USA. C.. Lee. Nov. M. pp.. S. Xiaowu Zhang. NV. S. Knickerbocker. 10. et al. C. pp. “Power delivery network design for 3D SIP integrated over silicon interposer platform. RES. 4/5 (2005). 2. Wright S. Hitachi Cable. C. Khan. H. A.. 2007.14 12 No. Lake Beuna Vista. Vol. Khong.W. “3-D hyperintegration and packaging technologies for micro-nano systems. pp. FL. 1663 2010 Electronic Components and Technology Conference . J. K. Lake Beuna Vista. et al. May 2009. pp... No. V. May 2007.” IBM J. “Development of 3D silicon module with TSV for system in packaging. pp1718-1725. of drops to failure 10 8 6 4 2 0 Conventional pad design Proposed pad design Fig. “Development of nextgeneration system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection.” IEEE Journal of Solid-State Circuits. of the 59th ECTC. of the 57th ECTC. pp. P. S. Institute of High Performance Computing (IHPC) and Institute of Materials Research and Engineering (IMRE) under A*STAR in Singapore. 2009. S. W. Vol. & DEV... Jan 2009. Kurihara.

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