A 77 GHz Controllable Gain Low Noise Amplifier

M. Fahimnia*, M. Mohammad-Taheri**, Y. Wang*** and S., Safavi-Naeini**** *ECE department, University of Waterloo, Waterloo, Ontario, Canada, mfahimni@uwaterloo.ca **ECE department, University of Tehran, Tehran, Iran, mtaheri@ut.ac.ir ***EE department, University of Ontario Institute of Technology, Ontario, Canada, ying.wang@uoit.ca **** ECE department, University of Waterloo, Waterloo, Ontario, Canada, safavi@maxwell.uwaterloo.ca

Abstract: A 77GHz low noise amplifier has been designed using common source topology implemented in low cost CMOS technology for various applications. A new method has been proposed for the design of the amplifier. In this method, input/output matching networks and transistor gate widths have been optimized for maximum gain and minimum noise figure. The design is flexible such that the LNA can operate in both high gain/high power and low gain/low power modes with low noise figure of less than 7dB at 77GHz. Amplifier gain is better than 18dB consuming 60mW of dc power and it is better than 14.5dB consuming 30mW of dc power. The input and output return losses are better than 10 dB in the frequency range of 72 to 82 GHz.

Keywords: CMOS; Microstrip Line (MSL); Low Noise amplifier (LNA); Millimeter-Wave (MMW); Common Source (CS). 1. Introduction Use of CMOS technology in millimeter wave communication systems is expanding due to its increasing cut off frequency and its low cost technology. It also benefits from the ability to integrate with the digital part of the system, efficient manufacturing process and reliable design and performance [1-5]. The above advantages have made CMOS as a suitable choice in various applications such as broadband communication, radiometry, radio astronomy, remote sensing and high resolution imaging. These applications which have been traditionally dominated by expensive, high performance III-V technologies now are open to CMOS designers [69]. However to successfully design a CMOS circuit in mmW, designers face many challenges such as low resistivity substrate, high sheet resistivity of poly-silicon gate and significant parasitic of CMOS circuit elements. To alleviate these disadvantages, the careful modelling of CMOS is a crucial task. Taking into account the above facts, the optimization of a CMOS amplifier is a timeconsuming process. In this paper, using the accurate models for transistor and transmission line implemented

in input/output matching circuit a low noise amplifier has been designed using 4 stage cascaded common source topology. In section II, the CMOS technology and its transistor small signal and transmission line models are presented. Section III, describes the circuit design method and optimization process. In section IV, the simulation results have been presented. The designed amplifier attains 18dB gain, noise figure better than 7dB and consumes 60mW in high power mode. It can also operate in low power mode with 14.5dB gain and same noise figure as obtained in high power mode while consumes less than 30mW. It is shown that using proposed method a common source amplifier can be designed with superior performances compared with those have been already designed using CMOS technology in the literature. 2. CMOS Technology

A 130nm RF-CMOS technology has been used for LNA design. In this technology, 8 metal layers are available in core back stack. 3 thin metal layer made of Copper are used for digital purpose. They are also very suitable for shielding the millimetre wave signal from lossy substrate. 3 thick Copper metal layers provide low resistive path for circuit biasing. 2 RF Aluminium and Copper metal layers are implemented for high performance passive elements. Relatively high Q transmission lines can be realized using these two RF metal layers. This technology provides metal-insulatormetal (MIM) capacitor using oxide inter-metal dielectric. Transmission line and transistor models at millimetre wave range of frequency are investigated. 2.1 Transmission line model Top metal layer has been used for signal and lower metal level for the ground path. This arrangement isolates the millimeter-wave signal from the lossy substrate. Due to its low loss and low dispersion characteristics, microstrip transmission line (MLS) has been implemented in this

2 Transistor model Fig. GHz -0. The input/output matching elements and transistor gate width are obtained based on simultaneous power and noise match conditions.67 pH / μm (1) C = 0. For example. To calculate the inductor. Fig.1)) -12 -13 -14 -15 60 65 70 75 80 85 90 Where Zs is source impedance (see Fig. 2: S-parameters of a 100µm microstrip. dB(S(2. freq. (2) -10 -11 dB(S(1.35 -0.paper to realize inductor. 5) and Zopt=Ropt+jXopt is optimized noise impedance of the transistor. L1 and L2 are used for input matching.02 fF / μm formula. L5 and L6 are used for output matching of the first stage and input matching of the second stage. the whole circuit is optimized at once. L4. 2. 5. R = 0. This ensures the output matching of each stage is implemented for the input matching of the next stage. Based on this minimization.45 In Fig. GHz Fig. Fig.1)) -0. For these conditions to be satisfied we should have the following equations: Re[ Z in ] = 50Ω Im[Z in ] = 0 Re[ Z s ] = Ropt Im[Z s ] = X opt Fig.25 Fig. 5: Designed 4 stages cascaded amplifier. The simulations results for MLS predict an insertion loss of 4dB per mm and an input return loss of better than 10dB at 77GHz.1:Microstrip transmission line model. However in this paper we also obtained the element values versus transistor gate width equations and used them in our optimization algorithm to find optimum gate width and input/output matching elements. 3 shows the widely used small signal model of a MOSFET. 4 One stage amplifier with input/output matching circuits. 60 65 70 75 80 85 90 -0. 4 shows one stage of common source topology used in this paper.55 freq. The intrinsic elements of the model can be easily found using Y-parameters of the transistor. 3: Small Signal Equivalent Circuit of a MOSFET. capacitor and resistor of the transmission line model. Low noise amplifier design Fig. The transmission line is first modeled with π circuit consisting of series combination of inductor and resistor with two shunt capacitors as shown in Fig. 2 depicts the Sparameters of the microstrip transmission line implemented in the design of low noise amplifier. 3. 1 [10]. The measured S-parameters of the active device is first converted to the Y-parameters and using well-known Fig. the difference between measured S-parameter of a microstrip line and model shown in Fig. the values of the model elements are obtained as: L = 0.013Ω / μm In this paper we ignored the capacitors of transmission line as they are small compared to the intrinsic capacitance of the transistor. one can calculate the element values of the intrinsic and extrinsic parameters [11-12]. . 1 was minimized.

gain is better than 18dB in the frequency range of 73GHz to 78GHz. Fig. For example the inductor L14 was realized with a 63µm microstrip line which is the longest required line. From this table it can be seen that the designed amplifier in the low power mode has better noise figure and lower power consumption with same gain as cascode amplifier presented in [10]. It also has an acceptable gain and noise figure compared with similar amplifier designed in the millimeter-wave range of frequency. It should be noted that noise figure is 6. 6 shows the S-parameters of the designed amplifier for Vg=0. Fig. 7 also shows the S-parameters for Vg=0. Input and output return losses are better than 13dB in this frequency range. As can been seen the noise figure is quite close to NFmin which shows a very good noise match for the designed amplifier. . Fig. Fig 7 S-parameters for low power mode. As can be seen from Fig. 6. 9: Stability factor of the designed amplifier. W = 65µm L1 = 33 pH L2 = 40 pH L3 = 10 pH L4 = 40 pH W=67. 6: S-parameters for high gain mode. Fig. Input and output return losses are better than 12dB in this frequency range while consumes 60mW.5 µm L8 = 30 pH L9 = 20 pH L10 = 40 pH W=65 µm L11 = 16 pH L12 = 30 pH L13 = 17 pH L14 = 42 pH All inductors have been replaced by microstrip transmission lines whose lengths were calculated using (1). 9 shows the stability factor of the designed amplifier. gain is better than 14dB in the frequency range of 74GHz to 80GHz. Stage 1 Stage 2 Stage 3 Stage 4 From this figure.5 µm L5 = 35 pH L6 = 29 pH L7 = 40 pH W=67. TABLE I: Optimized designed values for the amplifier.7dB at 78GHz in high gain mode. Fig. Table II compare the performance of the designed amplifier with those have been already reported in the literature using CMOS technology. Fig.13-µm CMOS technology has been analyzed and designed using 4 stages cascaded common source topology.6 V (Low power mode). In order to maximize gain and minimize noise figure of the LNA. Conclusion A 77 GHz controllable gain amplifier using 0. all inductors can be realized using short lines which is an advantage for the design amplifier. Table I shows the optimized values for the designed amplifier.75 V (High gain mode). 8: Noise figure and NFmin for high gain mode. The amplifier consumes 30mW of dc power. 4. Simulation results Standard Vd=1. Fig.9dB at 78GHz in low power mode. Noise figure is 6. As can be seen from table 1. L3 provides simultaneous power and noise match based on equation (2) and also improves the stability of the first stage. From this figure it is clear that the amplifier is highly stable in both modes. 5.In addition. 8 depicts the noise figure and NFmin for high gain mode. This decrease the losses and parasitic of the lines and also miniaturizes the layout of the circuit which are of great important for MMIC design.2V supply is used to bias the amplifier.

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