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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 4, JULY/AUGUST 2004

Harmonic Analysis and Improvement of a New Solid-State Fault Current Limiter
M. M. R. Ahmed, Member, IEEE, Ghanim A. Putrus, Li Ran, Member, IEEE, and Lejun Xiao
Abstract—This paper presents a harmonic study on a newly developed solid-state fault current limiter. Using this device, the supply voltage sag is reduced when a short-circuit fault occurs on a cable feeder in the downstream network, hence improving the power quality. The device will eventually isolate the faulted part from the healthy network. Harmonics caused by the fault current limiter are analyzed and a method is proposed to prevent undesirable harmonic interactions. Analytical and experimental results are compared with existing regulations. It is verified that, with precautions, the operation of the solid-state fault current limiter will not cause problems to either the supply network or the loads. Index Terms—Fault current limiters, harmonics, power quality and switched-mode power supply (SMPS).

Fig. 1.

Construction of FCLID.

I. INTRODUCTION AULT CURRENT limiters are being developed to improve the performance of distribution networks. Advantages of using a fault current limiter include reduced fault level of the supply and smaller voltage sag during a short-circuit fault. These will avoid upgrading switchgears during system expansion and improve the power quality delivered to customers. Previous studies have proposed designs with impedance insertion, switched using semiconductor devices [1], [2]. Superconducting fault current limiters are also being developed [3], [4]. A shortcoming with previous fault current limiters using impedance insertion is that the limited fault current varies with the supply system condition and fault location. In addition, operation time is limited due to power dissipation in the impedance, which is usually very resistive. For such reasons, a new solid-state fault current limiter was proposed [5] and more recently developed. The semiconductor devices in the proposed fault current limiter are controlled in a repetitive switching pattern during operation so that the fault current is always limited to a predetermined level. A side effect
Paper ICPSD-01-D5, presented at the 2001 IEEE Rural Electric Power Conference, Little Rock, AR, April 29–May 2, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Rural Electric Power Committee of the IEEE Industry Applications Society. Manuscript submitted for review May 15, 2001 and released for publication April 12, 2004. The work of M. M. R. Ahmed was supported by Northern Electric Distribution Ltd., U.K., and the Egyptian Government through a scholarship to study at Northumbria University. M. M. R. Ahmed is with the Industrial Education College, Cairo, Egypt (e-mail: mohamedra62@yahoo.co.uk) G. A. Putrus is with the School of Engineering and Technology, Northumbria University, Newcastle upon Tyne NE1 8ST, U.K. (e-mail: ghanim.putrus@unn.ac.uk) L. Ran is with the School of Engineering, University of Durham, Durham DH1 3LE, U.K. (e-mail: li.ran@durham.ac.uk) L. Xiao is with the School of Engineering, University of Salford, Manchester M45 7FN, U.K. (e-mail: l.xiao@salford.ac.uk) Digital Object Identifier 10.1109/TIA.2004.830774

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of the repetitive switching of the semiconductor devices is that harmonics are generated. This paper considers the harmonic characteristics, and the effects on supply system and loads near the fault current limiter. This paper first outlines the construction and operation of the new solid-state fault current limiter. Its features are summarized. The mechanism of harmonic generation is then analyzed and a MATLAB/SIMULINK model proposed to predict the harmonic level. The calculated harmonics are checked against IEEE standard 519–1992 [6] and the U.K. standard G5/3 [7], regarding short-duration harmonics. A control method is proposed to improve the harmonic signature. Laboratory experiments are performed to verify the harmonic calculation and the control method. Tests are also carried out to investigate the risk and solutions regarding harmonic resonance with power factor correction capacitors in the network or cable capacitance. The effect on sensitive loads such as switched-mode power supplies (SMPSs) in the customer loads is also investigated. II. FAULT CURRENT LIMITING AND INTERRUPTING DEVICE (FCLID) The solid-state fault current limiter concerned in this study is actually an FCLID. Fig. 1 shows the configuration of a singlephase FCLID. It consists of a high-speed bidirectional switch realized using power semiconductor devices such as insulated gate bipolar transistor (IGBT), a varistor (nonlinear resistor), and a snubber circuit, all connected in parallel. In operation without a fault, the semiconductor devices are constantly gated on. Alternatively, the whole FCLID can be bypassed using a circuit breaker to avoid losses. The bypass circuit breaker is opened when the FCLID is required to operate. Considering that a short-circuit fault occurs on the load side, a semiconductor device will initially conduct the fault current. The switch is turned off when the fault current reaches a preset which should be within the interrupting capability value of the semi-conductor device. The fault current is, thus, diverted to the varistor. The clamping voltage of the varistor is set to be higher than the peak supply voltage. Therefore, the current in

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the switching rate is not constant even within a half cycle. 4. As will be shown later. and average values of the current are all determined by the controller. Restrictions apply. Referring to Fig. the harmonics in the FCLID voltage are divided between source impedance and the impedance from the PCC to Authorized licensed use limited to: IEEE Xplore. these will affect the switching frequency of semiconductor devices in the FCLID. If the fault persists. The varistor voltage remains almost constant as long as it is conducting. The value changes to 2. The voltage across the FCLID (upper trace) is. Busbar A is the point of common coupling (PCC) with other cable feeders. 4) The varistor presents its clamping voltage when conducting but the supply source voltage is time variant. Load 2. During operation. cally the small leakage current of the varistor) in this case. Without the fault current limiter. is limited by A. and 4 kA if the fault location is at Load 3. Fig. min- imum. Therefore. 2. the FCLID alternatively presents the clamping voltage of the varistor (varistor conducting) and about 0 V (switch turned on) in series in the power circuit. As for the voltage at the PCC. The maximum. It is observed that the harmonics originate from two distinct mechanisms: the harmonics around the average switching frequency of the semiconductor devices in the FCLID. For the case of a fault at Load 4. after a certain time. . 2009 at 10:56 from IEEE Xplore. It is assumed that the pre-fault load current is less than 40 A. Current through FCLID. The latter have similar distribution to the harmonics in a square wave [11]. 2 [9]. While the proposed FCLID provides some very desirable characteristics. the corresponding laboratory model of the FCLID is able to operate for about 1 s. Fig. The features of the proposed FCLID can be summarized as follows. FCLID incorporated in a typical distribution network. and fault location. III. In deriving the spectrum. the faulted circuit starts to decrease. A method was developed to provide equal current sharing between parallel varistors [10]. the current was sampled for one fundamental cycle and Fourier analysis was then applied to the sample. The semiconductor device is turned on again to reestablish the current as it . 2) The current-limiting function is achieved via the insertion of the varistor. Spectrum of FCLID current. Downloaded on April 21. 3. Switching logic is the same reduces to a preset low value for both positive and negative half cycles of the fault current and the operation is maintained for a specified period of time which is useful to collect information about the fault location and to coordinate protection relays [8]. Therefore. and the fault current is completely interrupted. 1) The limited fault current is independent of the supply system condition and fault location. the maximum through current.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER 1013 Fig. 4 shows the frequency spectrum of the current waveform shown in Fig. respectively. therefore. the supply system condition. the semiconductor devices are turned off permanently. very distorted.AHMED et al. the simulated voltage waveforms across the FCLID and at the PCC (A) are shown in Fig. it is also clear from the above that the FCLID will exhibit some special harmonic characteristics which should be carefully analyzed. 3) The rate of change of the current depends on the total series inductance in the circuit. which is potentially 1 kA without the FCLID. Fig. HARMONIC CALCULATION AND IMPROVEMENT Fig. a simulation model is established using MATLAB/SIMULINK for the single-phase 230-V system shown in Fig. and Load 1. Power dissipation in the varistor may be carefully dealt with such that the FCLID can operate for a considerable period of time. 5. To illustrate the above operating principle. the prospective peak short-circuit current at the busbar of Load 4 is 1 kA. 3 shows the curthe fault current limiter to is set to 0 A (practirent through the fault current limiter. and the lower order harmonics due to the constant and modulation control. The simulation is performed for three half cycles only. 3. 2. 3.

5. This will increase switching frequency.” [7]. 2009 at 10:56 from IEEE Xplore. Other feeders connected to the PCC will be subjected to the voltage waveform shown in Fig.1014 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS. the semiconductor devices can be turned on at a higher current level. as long as the FCLID is installed close to a strong supply and the fault location is sufficiently far from the FCLID. 3 must be absorbed by the supply system. the burst duration does not exceed 2 seconds and the interval between bursts is not less than 30 seconds. there should be no risk of damage. and system fault level should be considered. the risk of damage to the FCLID and other equipment must be prevented. Therefore. V. Voltage across FCLID and at PCC. or protective measures are taken in the controller so that the FCLID does not respond when the fault is very near to it. Provided that the fundamental voltage at the metering point does not exceed the nominal supply voltage plus 6 per cent. e. The Fig. IV. Little voltage sag may be present during the fault. the harmonics produced by the fault current limiter may not be a problem. It is. . Restrictions apply. which states that for short-duration harmonics “Devices such as a thyristor-controlled drive applied to a rolling mill generate short duration harmonic currents as the material passes through the mill. waveform with is to reIt is observed that the effect of increasing duce the bandwidth of the limited fault current. device switching loss Authorized licensed use limited to: IEEE Xplore. which states that “short duration transients are tolerable provided the current bursts and related voltage distortions are of an intermittent nature. an extra inductor may be integrated in the fault current limiter. rich harmonics over a quite wide spectrum band are produced. 5. advisable to improve the harmonic characteristics of the fault current limiter. A method to reduce the harmonic content in the current during the operation of the fault current limiter is to modify the switching strategy.. the transformers. STANDARDS REGARDING SHORT-DURATION HARMONICS There are two main recognized standards dealing with the short-duration harmonic as their main goal. the fault. 6. Fig. the harmonic current shown in Fig. it is important to investigate the possibility of harmonic resonance with the supply network and loads connected to the PCC. Additionally. JULY/AUGUST 2004 Fig. the voltage will be more distorted for a fault closer to the fault current limiter.” [6]. therefore. and other apparatus is sometimes more tolerable than the stress caused by the constant generation of harmonics. Therefore. VOL. Its duration is usually less than 2 s.g. Generation of intermittent harmonics and the resulting voltage stress on the capacitors. Spectrum of FCLID current with I min = 50 A. the voltage at the PCC before the fault current limiter will be close to a sine wave. For this reason. The principal concern is to prevent damage to other plant such as capacitors. Instead of turning on the switches when the current reduces to 0 A. However. Its spectrum is shown in Fig. Operation of the fault current limiter is a rare event as compared to a rolling mill drive. FCLID current with I min = 50 A. CONSIDERATION OF HARMONIC RESONANCE It has been shown that during the operation of the FCLID. 6 shows the simulated current A. Engineering Recommendation G5/3. According to the above standards. Fig. These are: IEEE Standard 519–1992. 7. Therefore. Also. NO. 40. 7. Downloaded on April 21. 4. The voltage at the PCC will also be slightly improved. The harmonics in the FCLID current are of higher frequency and can be more easily absorbed using a passive filter at the PCC. This is particularly the case if the harmonics are reduced using the modulation control.

Normally. The supply fault current level is assumed to be 1 kA. It is clear that the switching frequency should avoid the range from 200 to 800 Hz.AHMED et al. It is worth pointing out that this is the worst case where power-factor-correction capacitors are connected directly at the PCC of the FCLID. the harmonics injected into the supply system will be amplified and overvoltage/overcurrent may cause damage to the plant. Fig. (1) (2) where and are the impedances of the supply system and capacitor. where is the harmonic current generated. validated. Both ysis is performed for different values of the capacitance and is plotted in Fig. To analyze the situation. For the 230-V single-phase circuit. 10 shows the relationship between the resonance frequency and cable length. at the frequency examined. If this happens. Good agreement is observed with previous simulation results. 9 for a system fault level. 13. respectively. A simple equivalent circuit of the network is shown in Fig. Resonance frequency versus cable length. 2 has been carried out. 2009 at 10:56 from IEEE Xplore. worst case is that some harmonics could coincide with the natural frequencies of the circuit formed by power factor correction capacitor at the PCC and the supply system impedance in the upstream. the SMPS derives its power from the utility supply via a diode rectifier with a capacitively smoothed dc link. It is clear that for cables shorter than 5 km. there is no risk of resonance as long as the switching frequency of the FCLID is under 2 kHz. VI. The shunt capacitance is varied from 1 to 10 mF and the resonant peak is captured for each capacitance value.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER 1015 Fig. the cable capacitance is about 1 F/km and inductance is about 230 H/km. Harmonic resonance corresponds to the case when the inductive reactance of the supply equals the capacitive reactance of and will be greater than . 11 shows a cycle set to 120 A and set to 50 A. 2. The current at any harmonic frequency divides between the shunt capacitor and supply as Fig. EXPERIMENTAL RESULTS An experiment was set up for the network shown in Fig. Downloaded on April 21. where the FCLID is assumed to be a source of harmonic current . VII. Restrictions apply. harmonic current flow analysis for the distribution network shown in Fig. when capacitors are connected in the distribution network. 8. Then. 2. 8. which is usually the case. Too high a switching frequency should also be avoided from the device point of view to prevent excessive switching losses. Fig. 12. the PCC will be at a higher voltage level. there will be no risk of parallel resonance. where the line current and voltage as well as the current in other load connected at the PCC were recorded. is the harmonic is the harcurrent that flows into the supply system. The ratio system fault level of 1 kA. Analthe capacitor. Resonant peak with different capacitance. therefore. and monic current that flows into the capacitor. The cable capacitance and inductance could also introduce a resonant mode. of the line current with Its spectrum is shown in Fig. Fig. Authorized licensed use limited to: IEEE Xplore. As shown in Fig. point A in Fig. EFFECT OF FCLID ON SMPS Typical loads that are most sensitive to the distorted waveforms produced by the FCLID are domestic and commercial electronic equipment such as a personal computer (PC) and television (TV). 10. If the switching frequency of the and FCLID is increased above 800 Hz by setting proper . Harmonic current flow. Such equipment normally includes SMPS. Earlier analysis and conclusions based on computer simulation are. . 9.

Measured FCLID current waveform (I = 1 kA). Restrictions apply. SMPS. 11. Downloaded on April 21. 14. A main concern is that the FCLID may affect the operation of the SMPS due to the high rate of change of voltage when the semiconductor device in the FCLID is turned off and the clamping voltage of the varistor appears across the FCLID. Fig. For a fault close to the FCLID. . the corresponding waveforms are shown in Figs. Fig. 12. 15 and 16 show the PC Fig. Figs. Fig. 4. It is useful to consider the effects of the proposed FCLID on such load when connected to the PCC in the distribution network. Test has been performed for a case when the short-circuit fault is far from the FCLID. A PC is connected in front of the FCLID. Fig. 2009 at 10:56 from IEEE Xplore. The input current is usually discontinuous as shown in Fig. PC current with a remote fault. 16. 13.1016 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS. 14. NO. PC voltage with a remote fault. Spectrum of measured FCLID current. JULY/AUGUST 2004 Fig. 17 and 18. current and voltage waveforms. Input current to SMPS. 40. Authorized licensed use limited to: IEEE Xplore. The prospective fault current is 1 kA. 15. VOL.

Authorized licensed use limited to: IEEE Xplore. The spikes are higher when the fault is close to the fault current limiter and. 21. 18. The results are given in Figs. Simulated PC voltage. 20. This may affect the operation of equipment that is phase locked to the sinusoidal supply voltage. Referring to the analysis about harmonics in Fig. A simulation model is used to recreate the situation shown in Figs. The rating and the required duration of of the inductor depends on FCLID operation. 17 and 18. As a solution to the above problem. Downloaded on April 21. Similar signatures can be observed between the simulation and experiment if the measured waveforms are zoomed in. Fig. The simulation results for this case are shown in Figs. 17 shows the moment when the PC fuse blew at 220 ms after the fault current limiter started operating. 17. a small inductor of 100 H may be inserted in series with the FCLID. Section III. The second problem which may arise.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER 1017 Fig. 2009 at 10:56 from IEEE Xplore. Fig. it is generally advisable to include a series inductor with the FCLID proposed. . 19 and 20. The current spikes may exceed the fuse rating of the SMPS and cause fuse fatigue. PC voltage with fault close to FCLID. Simulated PC current. particularly when the fault is close to the FCLID. hence. Restrictions apply. PC current with series inductor. It is shown that the high applied at the input of the SMPS will be seen by the dc-link capacitor.AHMED et al. Fig. PC current with fault close to FCLID. causing input current spikes. is that more zero-crossing points are introduced in the voltage waveform. 21 and 22. 19. the PCC. Fig.

A. U. in 1989. A. 4) Provided that a detailed system study is carried out. 8. He received the B. Restrictions apply. Ahmed has reviewed papers for several IEEE conferences. vol.” in Proc. 1) Operation of the proposed FCLID will produce harmonic current into the supply system which can be reduced by . pp. 1995/026.1018 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS. and the Regional Center for Electronic Technology (ReCET). A. D. NO. He is still regularly involved in IEE professional activities such as organizing lectures and refereeing papers. Appl. U. and H. Bodger. G. Newcastle upon Tyne. [9] M. 22. R. after working for six years at UMIST. dc motor drives. He has over 20 years of research experience in electrical power engineering and has authored over 35 publications in journals and conference proceedings. PC voltage with series inductor. and H. M.. The results obtained from simulation and the experimental test show the following. June 1995. pp. Northumbria. “An overview of transmission fault current limiter. M.” IEEE Trans. Newcastle upon Tyne. 1999. Egypt. as a Teacher. B. Remedy actions were recommended. and the supply network inductance.K. Abha. “Solid-state current limiter for power distribution system. New York: Wiley. Putrus was a Member of the 1999–2000 Professional Group P7 of the Institution of Electrical Engineers. Cooper. Smith. M. increasing 2) The short-duration harmonics produced by the FCLID comply with the harmonics standards (IEEE 519–1992 and G5/3). pp. pp. Power System Harmonics. in 1955. Power. in 1994.Sc.K. P. M. Simulation and test were performed regarding the application of the FCLID in a typical 230-V single-phase distribution network. 519–522.” in IEE Colloq. Cairo. in 1967. in 2002. [8] M.K. CONCLUSION This paper has investigated the problems associated with harmonic generation in a new solid-state FCLID. He received the Ph. U. U. Since moving to Northumbria. Technol. 40. Authorized licensed use limited to: IEEE Xplore. degree in electrical engineering from Cairo University. Arita. From 1993 to 1996. June 1995. Dr.” in IEE Colloq. “Investigation into custom power technology. “A static fault current limiting and interrupting device.Sc. Ahmed. N.K. Power Delivery. The voltage waveform at the PCC is also improved. he was with the Abha Technical College. custom power technology. His main research interests are the application of power electronics in power systems. June 1995. 1993. and P. Insertion of a small series inductor will attenuate the undesirable effects on sensitive loads such as SMPS. pp. Fault Current Limiter—A Look at Tomorrow. Putrus. pp. VATECH Reyroll. Dr. This paper describes part of a development work. Cairo. VIII. Pusan. Helowan. he has provided consultancy to several companies.K. Manchester. 2009 at 10:56 from IEEE Xplore.. Egypt.D. REFERENCES [1] R. vol. Power Delivery. Salasoo. 1796–1801.. ANSI/IEEE Std. Jenkins.. Ran. 1324–1327. Arrillaga. Ghanim A. S. M. as a Senior Lecturer in Power System Engineering in January 1995. and power quality.” School Eng. power systems. (IEE). the major problems regarding harmonics in the proposed FCLID are generally solvable. [10] G. 1999. degree from the University of Manchester Institute of Science and Technology (UMIST). “Improving current sharing between parallel varistors. and National Grid Company (NGC). for their support to and advice on this work. Mehta. Industrial Education College. The risk of harmonic resonance and adverse effect on sensitive loads such as SMPSs were assessed.. the results of which have been submitted in a patent application. followed by four years as an Administrate and Teacher at the Industrial Education College. Downloaded on April 21. . Iraq. [11] J. Morita.K. Fault Current Limiter—A Look at Tomorrow.” in Proc.” IEEE Trans. Saudi Arabia. R. He was a Lecturer at the National Civil Aviation Training Institute. Putrus was born in Mosul.” IEEE Trans. 1979. 5/1–5/6.. Ahmed and G. 3) Proper measures can be taken to avoid the risk of harmonic resonance between the cable or power-factor-correction capacitance. U. Egypt. [5] G. the M. Ahmed (M’00) was born in Cairo. Korea. including Northern Electric Distribution Ltd. Ueda. June 2001.E. Putrus. Egypt. and L. Engineering Recommendation G5/3. VOL. July 1993. 519-1992. Ahmed. [4] L. Univ.D. [7] Limits for Harmonics in the United Kingdom Electricity Supply System. He joined Northumbria University. microcomputer control. pp. J. in particular. K. “Report on development of a solid-state FCLID. Putrus. 1995/026. M. R. from 1990 to 1991. Cairo.E. and C.. U. FACTS. Slade. Oct. IEEE ISIE’01. degree from Northumbria University. U. and the Ph. Dig. Newcastle upon Tyne. ACKNOWLEDGMENT The authors would like to thank Northern Electric Distribution Ltd. Superconduct. 5. 1985. Bradley. His research areas are in power electronics. vol. UPEC’99. He is currently a Lecturer with the Faculty of Industrial Education. [2] T. R. “Solid-state distribution current limiter and circuit-breaker application requirements and control strategies.K. 1/1–1/5. [3] A. Dig. 1155–1164. 1079–1082.. degree from Helowan University. Factors affecting the harmonic characteristics were identified. JULY/AUGUST 2004 Fig. and active control of power distribution networks. 8. [6] IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems.. M. Egypt. 4. “Comparison of superconducting fault limiter concepts in electric utility applications.

Edinburgh. He received the B. China. U.. and industrial drives. Chongqing.. in 1963. Downloaded on April 21. U.D. in 2000. U. Durham. Aberdeen.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER 1019 Li Ran (M’98) was born in Sichuan.. He joined the University of Durham.K.. Newcastle upon Tyne. U. in 1983 and 1986.K. where he was involved in research on marine and offshore electrical systems. power systems.AHMED et al. U. Glasgow. U. Bradford. and M.Eng degrees from Xi’an Jiaotong University.K. China..D. Changsha. He is currently a Research Fellow at the University of Salford. China. Between 2000–2001. he was a Research Fellow at the Universities of Aberdeen. and the Ph. His present research interests include the control and grid integration of offshore renewable energy systems.K. Nottingham. His main research interests are in power electronics. He received the Ph.K. he was a Senior Research Assistant at Northumbria University. before joining the University of Strathclyde. and controller design and DSP implementation. Between 1992–1999. he was a Lecturer in Power Electronics at Northumbria University. U. in 2003. Restrictions apply. China. U. in 1963. Lejun Xiao was born in Hunan.Eng. He was an Associate Professor at Hunan University. degree in power engineering from Chongqing University. China. respectively. Authorized licensed use limited to: IEEE Xplore. degree from the University of Bradford.K.K. 2009 at 10:56 from IEEE Xplore. Dr. Between 1999–2003. in 1989. and Heriot-Watt.K. He then became a Lecturer at Chongqing University. Newcastle upon Tyne.K. Ran received a Stanley Gray Award—Offshore Technology from the Institute of Marine Engineers in 1999 for his work on the interconnection of offshore oil platforms. Nottingham. Manchester. as an Academic Visitor in 1995. electromagnetism. Xi’an. room acoustics. U. ..

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