Dolby Pro Logic IIx / Virtual Dolby Surround Decoder
General Description
The NJU26206 processes the stereo matrix-encoded signal(Lt/Rt) or normal stereo signal into spacious sound of 7.1(max) channels by Dolby Pro Logic IIx. The NJU26206 provides not only Dolby Pro Logic IIx but also Virtual Dolby Surround, Bass Management, Multi channel input, 5 Band PEQ, and Lip-Sync Delay function. The NJU26206 is suitable for multi-channel products such as Car Audio, or 2 channel products such as LCD-TV, and Plasma-TV.



-Software Dolby Pro Logic II Dolby Pro Logic IIx (Max 7.1ch Output) Virtual Dolby Surround (algorithm of Dolby Laboratories) Bass Management 5 Band PEQ Lip-Sync Delay function (Digital Audio Delay) Sampling Frequency
32kHz/44.1kHz/48kHz (In Master mode, DSP can’t generate a required system clock 44.1kHz of sampling frequency.)

-Hardware 24bit Fixed-point Digital Signal Processing Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit Digital Audio Interface : 4 Input ports / 4 Output ports Digital Audio Format : I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs Master / Slave Mode - In Master mode, MCK : 256fs @fs=48kHz / 384fs @fs=32kHz Microcomputer Interface - I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps) - 4 -Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data) Operating Voltage : VDD = VDDPLL = 1.8V : VDDIO = 3.3V Input Terminal : 5.0V Input tolerant Package : SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26206 is described in the “ NJU26200 Series Hardware Data Sheet”.



SW LFE Generator WatchDog Output WDC SDO2 C SW Smooth Control SL SR Virtual Dolby Surround proc. (*2) Band4 and Band5 fo should not be set as low frequency. 5bands PEQ3(*2) SDO3 LB RB (*1) When the system is not using the SL/SR and LB/RB output.2008-12-01 . Virtual Dolby Surround Noise generator proc.NJU26206 Block Diagram AD1/SDIN AD2/SSb NJU26206 24bit Fixed-point DSP Core SERIAL AUDIO INTERFACE BCKO PROGRAM CONTROL 24-BIT x 24-BIT MULTIPLIER ALU LB/RB. 4 stereo L/R->SL/SR 6ch stereo SL/SR->LB/RB SL+SR->CS SL-SR->CS Output Delay (C. it can be used as input delay. LB/RB) L/R Input Delay (*1) Input Trimmer Bass Management System SDI0 SDI1 ProLogic II decoder 5bands PEQ1(*2) 5bands PEQ2(*2) L R SDO1 Output Trimmer (Master & Each Channels) Dolby ProLogic IIx proc. 2 NJU26206 Block Diagram -2- Ver. 1 NJU26206 Hardware Block Diagram Function Block Diagram NJU26206 Features Overview ProLogicIIx and Virtual Dolby Surround Decorder Block Diagram 4ch/6ch Stereo proc. 5bands PEQ4(*2) SDO0 Noise Generator Fig. Monitor LRO SDO0 SDI* L/R C/SW SDO1 SDO2 BCKI SL/SR SDO3 LRI SCL/SCK SDA/SDOUT SERIAL HOST INTERFACE RESETb MCK CLK CLKOUT TIMING GENERATOR / PLL ADDRESS GENERATION UNIT DATA RAM FIRMWARE ROM PROC General I/O INTERFACE MUTEb SEL WDC Fig. ProLogic IIx Extended Surround proc. SL/SR.

3 NJU26206 Function Diagram(Multi Channel Input mode. LB/RB) SDI1 SDI2 SDI3 SDI0 L/R C/SW SL/SR LB/RB L/R (*2) Band4 and Band5 fo should not be set as low frequency. SL/SR) SDI1 C 5bands PEQ1(*2) 5bands PEQ2(*2) L R SDO1 Output Trimmer (Master & Each Channels) SDI2 C/SW SL/SR SL/SR SDO2 C SDI3 SW SW SL SR Lo/Ro Downmix Virtualizer Noise generator proc. with Monitor output) Ver. SDI0 Bass Management System C 5bands PEQ1(*2) 5bands PEQ2(*2) L R SDO1 Output Trimmer (Master & Each Channels) SL/SR SDO2 C SW SW LB/RB SL SR Virtualizer (for L/R. SL/SR) Noise generator proc. without Monitor output) Input Trimmer NJU26206 Features Overview Multi Channel Input mode (with Monitor output) (*2) Band4 and Band5 fo should not be set as low frequency. SL/SR. 5bands PEQ3(*2) L/R Delay SDO3 WatchDog Output WDC Noise Generator SDO0 Fig. 5bands PEQ3(*2) SDO3 L/R Delay LB RB 5bands PEQ4(*2) SDO0 Noise Generator L/R L/R Input Trimmer Bass Management System Output Delay (C.NJU26206 NJU26206 Features Overview Multi Channel Input mode (w/o Monitor output) Output Delay (C. C.4 NJU26206 Function Diagram(Multi Channel Input mode. WatchDog Output WDC Fig.2008-12-01 -3- .

5 NJU26206 Pin Configuration -4- Ver.2008-12-01 .NJU26206 Pin Configuration (SSOP44) SDI3 SDI2 SDI1 SDI0 LRI VDDIO BCKI VSS VDD TEST MUTEb WDC PROC VSSIO VDDIO SEL VDDPLL VSSPLL VSS VDD CLKOUT CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NJU26206 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VDD VSS VSSIO VDDIO SDO0 SDO1 SDO2 SDO3 LRO BCKO MCK VDDIO SDA/SDOUT SCL/SCK AD2/SSb AD1/SDIN TEST TEST TEST RESETb VDDIO VSSIO SSOP44 Fig.

Symbol SSOP44 6. ‘0’ : I C-Bus) PLL Analog Power Supply +1. After Reset DSP (“1” : 0dB . ( “1” : Normal . 24.8V for test (connected to VSSIO through 3. 28 TEST 29 AD1/SDIN 30 AD2/SSb 31 SCL/SCK 32 SDA/SDOUT I/O I I I OD I I O I I I I I I I I/O O O O O O O O I I I I I Function I/O Power Supply +3. 19. 41 VDDIO 7 BCKI 14. “0” : Mute) Clock for Watch Dog Timer (Open Drain Output) After Reset DSP.NJU26206 Pin Description Table 1 Pin Description Pin No. 44 VDD 10 TEST 11 MUTEb * 12 WDC * 13 PROC * 16 SEL 17 VDDPLL 18 VSSPLL 21 CLKOUT 22 CLK 25 RESETb 26 TEST 27. 33.8V PLL Analog GND OSC Output X’tal Clock Input (12. Master Clock Output (CLK Terminal Buffer Out) Bit Clock Output LR Clock Output Audio Data Output 3 (SL/SR) Audio Data Output 2 (C/ SW) Audio Data Output 1 (L/R) Audio Data Output 0 (LB/LR) Audio Data Input 3 Audio Data Input 2 Audio Data Input 1 Audio Data Input 0 LR Clock Input 34 MCK 35 BCKO 36 LRO 37 SDO3 38 SDO2 39 SDO1 40 SDO0 1 SDI3 2 SDI2 3 SDI1 4 SDI0 5 LRI I : Input O : Output OD : Open Drain Output I/O : Bi-directional Note: Pins symbol with * : Connect with VDDIO or VSSIO through 3. 4-wire Serial mode : SDOUT does not require a pull-up resistance.3kΩ resistance. 43 VSS 9. 20.288MHz) Reset (RESETb=’0’ : DSP Reset) for Test (Connect to VDDIO) for Test (Connect to VSSIO) 2 I C Address / Serial Input 2 I C Address / Serial Enable 2 I C Clock / Serial Clock 2 I C I/O (Open Drain output) / Serial Output (CMOS output) 2 I C Bus mode : SDA pin requires a pull-up resistance. 15.3kΩ resistance Ver. “0” : Wait from Command ) 2 2 Select I C or Serial bus ( ‘1’ : Serial . 42 VSSIO 8.) Master Volume level. 23.3V Bit Clock Input I/O GND Core GND Core Power Supply +1.2008-12-01 -5- .

SDO1.NJU26206 Audio Interface The NJU26206 audio interface provides industry serial data formats of I2S. only front Lch/Rch outputs are active. C. . SDI2 and SDI3.In Virtual Dolby Surround mode. SDI0. The other channels are muted. 4/6-Stereo) With Monitor Without Monitor With Monitor Without Monitor output output output output Monitor output A LB/RB Monitor output B LB/RB L/R L/R L/R L/R C/SW C/SW C/SW C/SW SL/SR SL/SR SL/SR SL/SR Note: L/R : Front channel LB/RB : Back surround channel C/SW : Center channel and Sub woofer SL/SR: Surround channel Monitor output A: Bypass output of Stereo L/R signals Monitor output B: Downmix output (Lo/Ro) of L/R.2008-12-01 . .There is a channel that is not outputted by Dolby Pro Logic II / Virtual Dolby Surround. 4/6-Stereo) With Monitor Without Monitor With Monitor Without Monitor output output output output Stereo L/R Stereo L/R L/R LB/RB (Pin select) (Pin select) (Pin select) L/R C/SW C/SW No use No use SL/SR SL/SR Table 3 Serial Audio Output Pin Pin No. Table 2 Serial Audio Input Pin Pin No. The input serial data is selected by the firmware command. The NJU26206 audio interface provides four data inputs. MSB-first Left-justified or MSB-first Right-justified. -6- Ver. and four data outputs. SDO2 and SDO3. SDI1. SDO0. SL/SR signals . SSOP44 40 39 38 37 Symbol SDO0 SDO1 SDO2 SDO3 Description Stereo input mode Multi channel input mode (Pro Logic II/IIx. as shown in table 2 and 3.Multi channel input mode does not assume making it operate as a Dolby Digital EX decoder. Symbol SSOP44 4 3 2 1 SDI0 SDI1 SDI2 SDI3 Description Stereo input mode Multi channel input mode (Pro Logic II/IIx.

This pin. The detail I2C bus and 4-Wire Serial bus information are described in the ‘NJU26200 Series Hardware Data Sheet’. Pin No. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers. Data transfers are in 8 bits packets (1 byte) when using either format. Please note the voltage level (Max voltage is VDDIO). Symbol Setting SSOP44 Low 16 SEL High Table 5 Serial Host Interface Pin Description Symbol 2 (I C /Serial) AD1/SDIN AD2/SSb SCL/SCK SDA/SDOUT 2 2 Host Interface I2C Bus Interface 4-Wire Serial Interface I C Address Select Bit1 Serial data input 2 I C Address Select Bit2 Slave select Serial Clock Serial Clock Serial Data Input/Output Serial data output (Open Drain output) (CMOS Output) Note: When 4-Wire Serial bus is selected. The SDOUT pin does not require a pull-up resistance.0V Input tolerant. SSOP44 29 30 31 32 I C bus Interface 4-Wire Serial Interface Ver. requires a pull-up resistance. 2 2 When I C Bus is selected. this pin is a bi-directional Open Drain output.NJU26206 Host Interface The NJU26206 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or 4-Wire serial bus. regardless of the chosen communication protocol. The SDA/SDOUT pin isn’t 5. Table 4 Serial Host Interface Pin Descriptions Pin No. The SHI operates only in a SLAVE fashion. which is assigned for I C Bus.2008-12-01 -7- . The SDA/SDOUT pin is CMOS output.

Moreover. 6 4-Wire Serial Interface Timing Note : When the data-clock is less than 8 clocks. Data is clocked into SDIN on rising transitions of SCK. Sr (repeated "START" condition) is not received but it becomes the waiting for the P ("STOP" condition). please be sure to send P ("STOP" condition). the last 8 bit data becomes valid.2008-12-01 -8- . This pin does not require a pull-up resistance. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. Therefore. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is latched on the falling transitions of SSb. SSb SCK SDIN SDOUT unstable bit7 MSB bit6 bit6 bit5 bit5 bit1 bit1 bit0 LSB bit7 bit0 unstable Fig. Ver. the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb=”High”. SLAVE address is 1 when AD1/2 is “High”. Data transfers are MSB first and are enabled by setting SSb = “Low”. the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=”High” during the Reset Sequence initialization. The SDOUT pin is always CMOS output. After sending LSB data. Note: The serial host interface supports “Standard-Mode (100kbps)” and “Fast-Mode (400kbps)” I2C bus data transfer. SDOUT transmits the MSB data which is received via SDIN until SSb becomes “High”. SDA is an open drain pin requiring a pull-up resistance.NJU26206 I2C Bus When the NJU26206 is configured for I2C bus communication in SEL=”Low”. When the data-clock is more than 8 clocks. (Table 6) Table 6 I C-Bus Interface Slave address AD2 AD1 2 bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 bit2 0 0 1 1 bit1 0 1 0 1 R/W bit0 R/W Start bit Slave Address ( 7bit ) R/W bit ACK * SLAVE address is 0 when AD1/2 is “Low”. after sending S ("START" condition). SHI bus communication is full-duplex. a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin.

The WDC pin is open drain output. Because WDC output inserts in the process of sound processing. when there is no input of BCKI/LRI.3kΩ resistance Connect with VSSIO through 3. It is required to set up a sampling rate correctly. The WDC clock is able to be variable for 10ms to 640ms by command.3kΩ resistance. Default setting of WDC clock is 200ms.3kΩ resistance. Sending start command is required for starting operation. Master volume is set mute after reset. For example. The NJU26206 does not operate after reset. a microcomputer monitors the WDC clock and checks the status of the NJU26206.NJU26206 Pin setting The NJU26206 operates default command setting after resetting the NJU26206.2008-12-01 -9- . the NJU26206 restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. these pins operate as bi-directional pins. The WDC clock is useful to check the status of the NJU26206 operation. Master volume is set 0dB after reset. Do not open WDC pin. WDC pin is not used. WatchDog Clock The NJU26206 outputs clock pulse through WDC during normal operation. Ver. Connect with VDDIO or VSSIO through 3. The WDC pin setting (Table 8) Table 8 WDC pin setting Pin No. the WDC pin can’t output. Symbol SSOP44 13 11 PROC MUTEb Setting “High” “Low” “High” “Low” Function The NJU26206 operates default setting after reset. Then reset the NJU26206 and set up the NJU26206 again. Table 7 Pin setting Pin No. Note: The cycle of WDC output is rough. In addition. SSOP44 12 Symbol WDC Setting WDC pin is used. However. In slave mode. the NJU26206 does not operate correctly. When the WDC clock pulse is lost or not normal clock cycle. Connect with VDDIO through 3.

Please refer to the licensing application manual issued by Dolby Laboratories. and permission of a licenser (Dolby) is required. .2008-12-01 . Command 1 SET_TASK_CMD 2 PRO2MODE_CMD 3 PRO2CDCFG_CMD 4 PRO2FLAGS_CMD 5 VIRTUAL_CMD 6 BM_CFG_CMD 7 SAMPLERATE_CMD 8 PNG_MODE_CMD 9 DELAY_CMD 10 GAIN_CMD 11 SYSTEM_STATE_CMD 12 WATCHDOG_CMD 13 SMOOTH_CMD 14 PEQ_SEL_CMD 15 PEQ_CFG_CMD 16 BM_EXTEND_CMD 17 REINIT_CMD 18 MON_OUT_DISABLE_CMD 19 MON_OUT_ENABLE_CMD 20 START_CMD 21 NOP_CMD Notes : In respect to detail command information. request New Japan Radio Co.NJU26206 Firmware Command Table Table 9 NJU26206 Command No. “Pro Logic” and the double D mark are trademarks of Dolby Laboratories. Ltd.10 - Ver. The NJU26206 can only be delivered to licensees of Dolby Laboratories. License Information The Word “DOLBY”..

05 1.1 5 ±0 .1 0 ∼1 0 ゜ 23 44 5. 1-0 .2 . 5 ±0 .15 .0.1 0 . without any guarantee as regards either mistakes or omissions. Pb Free + 0. 6 ±0 .75 MAX [CAUTION] The specifications on this databook are only given for information . 0 .10 0.10 0.0.11 - .3 11.3 1 0 .1 0. Ver. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.5 22 + 0.1 M + 0.NJU26206 Package Dimensions SSOP44. 6 ±0 .2008-12-01 0. 2 ±0 .2 7.05 0.1 0.

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