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Page 1 Lorenz A new type of chaotic circuit design Xiong Yan, Liu Wenbo, Zhang Jing (College of Automation

Engineering, Nanjing University of Aeronautics and Astronautics Nanjing 210016, China) Abstract: System Generator is a new FPGA-based signal processing modeling and design tools. This paper referred Introduce the main features of the System Generator and the design process, and then the tool gives the Lorenz-based chaotic circuit A new solution and this solution can be achieved on the FPGA, the experimental results show that the method is simple, the design Flexible, high efficiency, and finally experimental results are given in the field of secure communications, an application example. Keywords: chaos; Lorentz; system generator; field programmable gate array; CLC number: TP312 File flag code: B A new method of designing Lorenz circuit Xiongyan , Liu wenbo , Zhangjing (College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, China) Abstract: System Generator is a kind of newtype signal process and modeling tool based on FPGA. This paper has introduced the main characteristic and the designed procedure of System Generator at first, then provides a new based on this tool to implement Lorenz chaotic system and realize this scheme on FPGA, the experimental results indicate that this scheme has the advantages of easy operation, flexible design and high efficiency. Finally an application example in secure communications is provided. Keywords: chaotic; Lorenz; System Generator; FPGA; 1. Introduction Chaos is a deterministic system described by nonlinear equations generated by periodic oscillations and noise between a complex between the vibration Dang, both seemingly random chaotic oscillation spectrum have broadband spectrum, so in the field of secure communications and spread spectrum communication has been Wide attention and application. Lorenz system is a chaotic system, chaotic system than a more complex, three directions are chaotic and Mutual influence, it will be used for secure communication more secure. However, the traditional Lorenz system is composed of analog circuits To achieve, analog circuit components and signal regeneration intrinsic parameters are sensitive to errors and data communications in analog circuits Difficult to achieve simultaneous transmission and reception, so chaotic circuits with digital circuits has become a trend.

Field programmable gate array FPGA, a programmable logic device, which not only convenient programming, high integration, but also The ability of high-speed parallel computing, data processing faster. FPGA-based design of the chaotic signal generator, System Generator is an ideal software tool, which through the establishment of systems of abstract algorithm and then integrated the abstract algorithm Into a reliable hardware system, so it is high-level system design and FPGA implementation "bridge." In this paper System Generator Lorenz chaotic system is designed to avoid the traditional design process of the complex aspects of programming with HDL, significantly reduced Short design cycle. 2. System Generator Introduction System Generator and Xilinx, Mathworks cooperation is the development of a FPGA design tools, the Tools can be represented as a system module is a highly abstract, and the system automatically mapped to a FPGA-based hardware Pieces of programs. Matlab's Simulink provides a dynamic system can create and visual simulation environment, System electronic enthusiasts Electronic Technology Forum Page 2 Generator is embedded in the simulink in matlab to work, it is called a block of packets Xilinx blockset Included in the simulink library, can be seen as a tool simulink package, users simply complete the model in simulink Structures, start the appropriate module, System Generator will define in the simulink system parameters into the corresponding hardware implementation HDL language when the entity, construction, input output, signals and properties. In addition, System Generator automatically For the FPGA integrated, HDL simulation and implementation tools to generate a command file. Therefore, from system specification to hardware implementation Now, users can visualize the environment in the operation. System Generator design flow includes the following steps: (1) with a mathematical description of the algorithm model; (2) System Generator tool to build the algorithm into a hardware executable model of the model; (3) start the appropriate modules to automatically generate HDL code for the project file; (4) in the ISE call resulting file, the system integration, constraints, routing and timing analysis; (5) into the FPGA to achieve. 3 with the System Generator design Lorenz chaotic circuit 3.1 Algorithm Analysis Description Lorenz chaotic secure communication circuit is a set of differential equations of nonlinear circuits (1): (1) x ( ) 205 A yx y Bx y

xz z Cz xy = = + = g Where A, B, C is a constant.. When A = 9, B = 35, C = 1.5, the system is in chaotic state. The time of its hardware implementation, the main problem is not in the System Generator toolbox module integrator, so the benefit With the first-order discrete equation (2), (2) ( 1) () xk xk xdt + = g Continuous Lorenz equations (1) discrete, taking the sampling time dt = 0.009, by the discrete Lorenz system side Process is as follows: (3) ( 1) 9 () (19) () ( 1) 20 () () 35 () (1 ) () ( 1) 5 () () (1 1.5) () xk dty k dt xk yk dtx kzk dtx k dt yk zk dtx kyk dt zk = + + = + +

+ = + + 3.2 System Generator model structures based on Now the discrete Lorenz equation (3) into System Generator's hardware-based implementation model in Figure 1, By using the Xilinx System Generator company ip module designed to ensure the accuracy of hardware implementation, although System Generator is the result of the ip module features the abstract, but for designers who are familiar with FPGA, the module Also has direct access to the ability of the underlying hardware details, so just call the existing ip simulink module, complete the subThe connection between the module, the parameters set, you can meet the design requirements. electronic enthusiasts Electronic Technology Forum Page 3 Figure 1 is based on the lorenz system generator hardware implementation model Shown in blue with the flag of the modules that Xilinx's ip module, the main function of each module are as follows: Cmult: constant multiplication module; Mult: multiplication module; it is the logic of the most resource intensive and most timeconsuming modules. Due to the continuous chaotic system After the digital system will bring the inevitable cycle of the negative impact, so if the data bit width is not big enough computing, computing Results Results will soon be out of the chaotic state, so here, select 64-bit multiplier ip, pipeline operations, Pipeline is four, great Guarantee speed of operation. Addsub: addition and subtraction module. Counter: counter, control Lorenz system, the number of iterations, when the counter = 1, the switch to take initial switch x (0), y (0), z (0) in operation. Gateway In, Gateway Out: simulink in the signal type is double precision floating point, but the current FPGA Does not support floating-point input, and therefore non-Xilinx Xilinx modules and modules into the module interface, Gateway In the module can be double-precision floating-point signal is converted to fixed-point signal, Gateway Out block signals can be converted to double precision fixed-point Degree of floating-point signal, the design of fixed-point format for the integer part of 4, the fractional part of 28. Delay: the number of combinational logic used by the module to achieve, and the multiplier circuit using the timing, delay period is 4, in order to Ensure that the data transmitted to register, must be added to this delay module, and set the delay period is 4. Register: Register module, a linear sample buffer to ensure adequate signal to establish time and hold time, Achieve assembly-line. System Generator: each System Generator design requires a System Generator block, it can

The basic components found in the library, the module responsible for selecting the device type and package, and make the appropriate pin constraints, and test shock Lai file generation, will also control the generation of the hardware implementation of procedures, it does not require other modules. Each Xilinx block can be user-set used, the block by double-clicking the icon to set the block property. Most electronic enthusiasts Electronic Technology Forum Page 4 Points Xilinx module can be inferred based on the input signal format of the output signal format, if the module's precision is defined as all refined parameters Degrees, the module will automatically select the output signal type to ensure no loss of accuracy of the input signal and automatically sign bit extension and Zero-padding operation. Figure 1 of the process is as follows: First, the counter is 1, select the initial sample x (0) = 0,, y (0) = 1, z (0) = 1 after Gateway In block is converted to 32-bit fixed-point, after several multiplication, multiplication and addition operations, through adjustment of Delay Module The appropriate delay period, making data synchronization into the register, the register module samples the linear buffer, and then by Gateway Out block is converted to double-precision floating point, and finally divided into two, one output to the oscilloscope display, and the other Road into the switch input, the next iteration as the initial value, repeat the above process is needed to generate the chaotic sequence Column. 3.3 Experimental results Select simulation-start, start the simulation, the module can be obtained by the oscilloscope as shown in Figure 2, x, y, z the time domain waveforms, And the x-y, x-z, y-z phase diagram: x-t y-t z-t x-y x-z y-z Figure 2 using System Generator design lorenz system results 3.4 Lorenz system FPGA hardware implementation Matlab programming language with the results compared with the results of the digital system after double its effectiveness and Simulation Results Fruit is basically the same, then to design a specific hardware implementation. Figure 1 Double-click the System Generator block to open its Properties dialog box, select the synthesis tool used The synthesis tool, in this case embedded ISE XST, FPGA Xilinx's VIRTEX2 device used to complete specific Model is XC2v1000bg5754, set is complete, click the Properties button to generate lower left corner of the window generated HDL File. In the generated HDL files to find fft_ex_clk_wrapper, np1 file that is System

Generator project files generated by ISE. Seen from the comprehensive report resource consumption as follows: slices of the total consumption of resources 84% of the source, the trigger for 46% of total resources consumed, the four input look-up table takes up 78% of total resources, in general should be The resource consumption that is not small, but considering the design to reduce the quantization error as much as possible to ensure that intensive operations, an increase of Multiplier bit wide, the other to speed up the use of pipeline operations, which will bring the circuit area increases, so this Kind of resource utilization should be also reasonable. And in the ISE environment, add the necessary UCF (user constraint file user constraints file), the corresponding FPGA-good Pin, synthesis, translation, routing, the generating BIT files directly downloaded to the FPGA. In addition, in order to confirm the validity of the file has been generated, System Generator can also generate a test file electronic enthusiasts Electronic Technology Forum Page 5 test bench, including the simulink simulation test vectors was calculated, we are in the System Generator block Select the "creat testbench" it may be in the project file documents directly test environment MODEL SIM Simulation, observation data waveform shown in Figure 3: Figure 3 The figure above three lines represent the waveform x, y, z the time domain waveform with the System Generator under the waveform (Figure 2) Contrast, found good agreement between the two results, it is designed entirely correct, to achieve in the FPGA. 4 Image Encryption Get this design three-dimensional Lorenz system as a result of the digital encryption key, for a 128 * 128 lena Image encryption, encryption, and the results before and encrypted ciphertext, respectively, the histogram in Figure 4 (a), (b), (c) below: Figure 4 (a) (B) (C) Can be seen from the histogram by a three-dimensional lorenz chaotic sequence generated by the system as a key to encrypt the lena Figure 6 with the literature Logistic map with a given chaotic sequence generated by encrypting lena figure compared to the simple one-dimensional Lorenz system The logistic system, a more chaotic (Lorenz system and the Logistic Map LYAPUNOV index were 1.5 And 0.7), so the system generated by the Lorenz chaotic sequences are more random as the encryption key, security is better. 4. Conclusion System Generator tool to achieve this through the FPGA-lorenz-based chaotic system. With this new system System design, users do not even need to know itself and the FPGA hardware description language, so you can avoid the complexity of HDL

Programming, which greatly improves design efficiency. Experimental results show that the design is correct and feasible, which also chaos theory to reality Use of the field opened up a new path. electronic enthusiasts Electronic Technology Forum Page 6 References [1] MISobby, MAAseeri and A. Shehata, "Real time implementation of chaotic models using digital hardware ", AMREM 2002, HPEM 13, June 2002. [2] Xilinx Inc., Virtex platform FPGA Handbook, 2001 [3] Uwe Meyer Baese. FPGA implementation of digital signal processing Beijing Tsinghua University Press 2003.1 [4], cure of the stone, Fair and so on. CPLD / FPGA Advanced Applications Development Guide Beijing Publishing House of Electronics Industry 2003.6 [5] Xin Xu and so on. FPGA-based Embedded System Design Mechanical Industry Press, Beijing 2005.1 [6] Gu Qin Long Yao Minghai Logistic chaotic sequence based on digital image encryption and application of Computer Engineering 2003.23 electronic enthusiasts Electronic Technology Forum

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