This action might not be possible to undo. Are you sure you want to continue?
Assignment Set – 1 1. Convert the following decimal numbers to binary: a. b. c. 2. 3. 4. 5. 6. 7. 8. 9. 10. 1231 673 1998
Give and explain one stage of logic circuit. Explain Von Neumann Architecture. Compare the register organizations of 8085, Z8000 and MC68000. Give the advantages and disadvantages of physical and functional buses. Explain different types of binary codes. Give and explain the block diagram of the bus system with four registers. Explain the System Bus structure. Explain the register organization of 8086. Explain the single bus structure.
1. Convert the following decimal numbers to binary: a. b. c. 1231 673 1998
10011001111 1010100001 11111001110
2. Give and explain one stage of logic circuit. The hardware implementation of logic microoperations requires that logic gates be inserted for each bit or pair of bits in the registers to perform the required logic function. Although there are 16 logic microoperations, most computers use only four – AND, OR, XOR (exclusive-OR), and complement–from which all others can be derived. Fig. 2.10 shows one stage of a circuit that generates the four basic logic microoperations. It consists of four gates and a multiplexer. Each of the four logic operations is generated through a gate that performs the required logic. The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs S1 and S0 choose one of the data inputs of the multiplexer and direct its value to the output. The diagram shows one typical stage with subscript i. For a logic circuit with n bits, the diagram must be repeated n times for I = 0, 1, 2, …, n-1. The selection variables are applied to all stages. The function table in Fig.2.10 (b) lists the logic microoperations obtained for each combination of the selection variables.
Explain Von Neumann Architecture.3. .
. Data and instructions are stored in a single read-write memory. A main memory. The general structure of the IAS computer is as shown in figure.IAS is the first digital computer in which the von Neumann Architecture was employed. Execution occurs in a sequential fashion unless explicitly modified from one instruction to the next. without regard to the type of data contained therein. 3. which stores both instructions and data An arithmetic and logic unit (ALU) capable of operating on binary data A control unit. which interprets the instructions in memory and causes them to be executed Input and Output (I/O) equipment operated by the control unit The von Neumann Architecture is based on three key concepts: 1. 2. The content of this memory is addressable by location.
The CPU consists of various registers as listed in figure. They are .
. · Dedicated: Permanently assigned to either one function or to a physical subset of components. All the sequence of actions is controlled by the control signals generated by the control unit. Thus Accumulator is a special purpose register designated to hold the result of an operation performed by the ALU. 6. Bus Types: Bus lines can be separated into two types. The instruction is decoded and then the data is brought to the ALU either from memory or register etc. Then ALU computes the required operation on the data and stores the result in a special register called Accumulator.1. The instruction is read from a location pointed by PC of the memory. 4. 4. Memory Address Registers (MAR): Contains the address of a location in memory. Program Counter (PC): It contains an address of an instruction to be fetched. Any instruction to be executed must be present in the System Memory. Memory Buffer Register (MBR): It contains a word of data to be written to memory or the word most recently used. 2. Give the advantages and disadvantages of physical and functional buses. 3. Instruction Register (IR): It contains the instruction most recently fetched. I/O Buffer Register (I/O BR): It contains a word of data to be written to I/O device. I/O Address Register (I/O AR): Contains the address of a I/O. 5. and then transferred it to IR through the data bus.
Explain different types of binary codes. and control signals as seen earlier. Example: Three busses identified for carrying address. And this bus is then connected to the main bus through some type of an I/O adapter module. A typical application of the Gray code . Example: I/O buses are used only to interconnect all I/O modules. each of which connects only a subset of components using the bus. The data must be converted into digital form before they can be used by a digital computer. Continuous. -Physical dedication: Refers to the use of multiple buses. Disadvantage of Physical dedication: Increased size and cost of the system 5. information is converted into digital form by means of an analog-to-digital converter. the change from any number to the next in sequence is recognized by a change of only one bit from 0 to 1 or from 1 to 0. Data Bus. or analog. The advantage of the Gray code over straight binary numbers is that the Gray code changes by only one bit as it sequences from one number to the next. Other binary codes for decimal numbers and alphanumeric characters are sometimes used. shown in Table 1. Many physical systems supply continuous output data. They are Address Bus. data. and Control Bus. A few additional binary codes encountered in digital computers are presented below. The reflected binary or Gray code. In other words. Digital computers also employ other binary codes for special applications.-Functional dedication: Bus has a specific function. Gray Code Digital systems can process data in discrete form only.5. is sometimes used for the converted digital data. Advantage of Physical dedication: It offers high throughput because there is less bus contention.
If adjacent segments are made to correspond to adjacent Gray code numbers.occurs when the analog data are represented by the continuous change of a shaft position. The shaft is partitioned into segments with each segment assigned a number. Binary code 0000 0001 0011 0010 0110 0111 0101 0100 Decimal equivalent Binary code 1100 1101 1111 1110 1010 1011 1001 1000 Decimal equivalent 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 Table: 4-Bit Gray Code Gray codes counters are sometimes used to provide the timing sequence that control the operations in a digital system. Numerous different codes can be formulated by arranging four or more bits in 10 distinct possible combinations. Other Decimal Codes Binary codes for decimal digits require a minimum of four bits. A few possibilities are shown in Table Decimal digit 0 1 2 3 BCD 8421 0000 0001 0010 0011 2421 0000 0001 0010 0011 Excess-3 0011 0100 0101 0110 Excess-3 gray 0010 0110 0111 0101 . A Gray code counter is a counter whose flip-flops go through a sequence of states as specified in Table. Gray code counters remove the ambiguity during the change from one state of the counter to the next because only one bit can change during the state transition. ambiguity is reduced when the shaft position is in the line that separates any two segments.
The BCD code can be assigned the weights 8421 and for this reason it is sometimes called the 8421 code. saying that 1001 110 is a decimal number in BCD is like saying that 9H is a decimal number in the conventional symbol designation. The property is useful when arithmetic operations are done in signed-complement representation. The 2421 is an example of a weighted code. It uses a straight assignment of the binary equivalent of the digit.6.4 5 6 7 8 9 Unused bit combinations 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0100 1011 1100 1101 1110 1111 0101 0110 0111 1000 1001 1010 0111 1000 1001 1010 1011 1100 0000 0001 0010 1101 1110 1111 0100 1100 1101 1111 1110 1010 0000 0001 0011 1000 1001 1011 Table: Four Different Binary Codes for the Decimal Digit The BCD (binary-coded decimal) has been introduced before. On the other hand. is easily obtained by changing 1’s to 0’s and 0’s to 1’s. The six unused bit combinations listed have no meaning when BCD is used. gives the decimal equivalent of 2 x 1 + 4 x 1 + 2 x 0 + 1 + 1 = 7. the 9’s complement is easily obtained with the 2421 and the excess-3 codes listed in Table 1. when weighted by the respective digits 2421. One disadvantage of using BCD is the difficulty encountered when the 9’s complement of the number is to be computed. These two codes have a self-complementing property which means that the 9’s complement of a decimal number. For example. . For example. Both cases contain an invalid symbol and therefore designate a meaningless number. the bit combination 1101. In a weighted code. the bits are multiplied by the weights indicated and the sum of the weighted bits gives the decimal digit. just as the letter H has no meaning when decimal digit symbols are written down. when represented in one of these codes.
When alphanumeric characters are used internally in a computer for data processing (not for transmission purpose) it is more convenient to use a 6-bit code to represent 64-characters. . Another alphanumeric (sometimes called alphameric) code used in IBM equipment is the EBCDIC (Extended BCD Interchange Code). Now the transition from 1010 to 0010 involves a change of only one bit. line feed. Twenty-three characters represent format effectors. It uses eight bits for each character (and a ninth bit for parity).and lowercase letters. Other Alphanumeric Codes The ASCII code is the standard code commonly used for the transmission of binary information. it is called the excess-3 Gray. horizontal tabulation. This set of characters is usually sufficient for data-processing purposes. The code consists of 128 characters. Ninety-five characters represent graphic symbols that include upper. we choose the 10 numbers starting from the third entry 0010 up to the twelfth entry 1010. We note that the Gray code is not suited for a decimal code if we were to choose the first 10 entries in the table. which are functional characters for controlling the layout of printing or display devices such as carriage return. numerals zero to nine. A 6bit code can specify the 26 uppercase letters of the alphabet. This is an unweighted code. Its binary code assignment is obtained from the corresponding BCD equivalent binary number after the addition of binary 3 (0011). Give and explain the block diagram of the bus system with four registers. and back space.The excess-3 code is a decimal code that has been used in older computers. This is because the transition from 9 back to 0 involves a change of three bits (from 1101 to 0000). and special symbols. The other 10 characters are used to direct the data communication flow and report its status. Since the code has been shifted up three numbers. numerals zero to nine. punctuation marks. and up to 28 special characters. Each character is represented by a 7-bit code and usually an eighth bit is inserted for parity. 6. To overcome this difficulty. EBCDIC has the same character symbols as ASCII but the bit assignment to characters is different. Using fewer bits to code characters has the advantage of reducing the memory space needed to store large quantities of alphanumeric data.
The construction of a bus system for four registers is shown in Fig. The number of wires will be excessive if separate lines are used between each register and all other registers in the system.2. and similarly for the other two bits. In order not to complicate the diagram with 16 lines crossing each other. MUX 1 multiplexes the four 1 bits of the registers. Thus MUX 0 multiplexes the four 0 bits of the registers. . The bus consists of four 4 x 1 multiplexers each having four data inputs. 0 through 3. S1 and S0. Each register has four bits. Control signals determine which register is selected by the bus during each particular register transfer. one for each bit of a register. we use labels to show the connections from the outputs of the registers to the inputs of the multiplexers. output 1 of register A is connected to input 0 of MUX 1 because this input is labeled A1. and two selection inputs.A typical digital computer has many registers. and paths must be provided to transfer information from one register to another. One way of constructing a common bus system is with multiplexers. numbered 0 through 3. For example.3. A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system. A bus structure consists of a set of common lines. through which binary information is transferred one at a time. The diagram shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to form one line of the bus. The multiplexers select the source register whose binary information is then placed on the bus.
2 shows the register that is selected by the bus for each of the four possible binary values of the selection lines. This causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers. The selection lines choose the four bits of one register and transfer them into the four-line common bus. register B is selected if S1S0 = 01. Table 2.The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers. and so on. Register Selected 1 S0 . the 0 data inputs of all four multiplexers are selected and applied to the outputs that form the bus. When S1S0 = 00. Similarly.
. it may be convenient just to show the direct transfer. Each multiplexer must have eight data input lines and three selection lines to multiplex one significant bit in the eight registers. If the bus is known to exist in the system. a common bus for eight registers of 16 bits each requires 16 multiplexers. R1 C From this statement the designer knows which control signals must be activated to produce the transfer through the bus. 7. When the bus is included in the statement. and the content of the bus is loaded into register R1 by activating its load control input. The number of multiplexers needed to construct the bus is equal to n. a bus system will multiplex k registers of n bits each to produce an nline common bus. The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. The size of each multiplexer must be k x 1 since it multiplexes k data lines. The transfer of information from a bus into one of many destination registers can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register selected. the number of bits in each register. For example. Explain the System Bus structure. one for each line in the bus. BUS The content of register C is placed on the bus. the register transfer is symbolized as follows: BUS R1 C.0 0 1 1 0 1 0 1 A B C D Table: Function Table for Bus In general.
We can refer to individual wires or a group of adjacent wires with subscripts. and the control bus as part of one larger bus. The dash in it is then labeled with the number of wires and the designation of those wires. Also the slant dash is labeled 32 which indicates that the number of wires in that bus is 32 and the dash is also labeled A31-0 which indicates individual 32 wires from A0 to A31.A bus consists of 1 or more wires. For example. There's usually a bus that connects the CPU to memory and to disk and I/O devices. The size of the bus is the number of wires in the bus. the address bus. Real computers usually have several busses. . even though the simple computer we have modeled only has one bus where we consider the data bus. A bus can be drawn as a line with a dash across it to indicate there's more than one wire. It consists of a slant dash on the horizontal line that represents it is a bus that carries more wires. We can then refer to. consider a bus as shown in figure. say A10-0 or A15-9 to refer to some subset of the wires.
There's a 32-bit address bus for the CPU to specify which address to read or write from or to memory. there's a control bus which may consist of a single wire or multiple wires to allow the CPU and memory to communicate For example a control signal is required to indicate when and whether a read or write is to be performed. Unfortunately. . this requires about N2 connections. To support two 32-bit busses. One alternative to using a bus is to connect each pair of devices directly. There are other kinds of busses that are used primarily for I/O devices like USB. Address. Most devices have a fixed number of connections which doesn't permit dedicated connections to other devices. both the CPU and memory require 64 pins or connections 32 for data and 32 for address. Devices connected to the bus must share the bus. 8. Explain the register organization of 8086. There's a 32-bit data bus. Data. Only one device can write to it at a time. and Control Busses There are usually 3 kinds of buses. Earlier there was shortage of pins and hence it was necessary to multiplex the address and data bus. which may be too many. Multiplexing uses the same bus as both address and data bus.A bus allows any number of devices to hook up to the bus. Finally. These are mostly high-speed busses for external devices. for N devices. which is used to write or read 32 bits of data to or from memory. A bus doesn't have this problem.
implicit way to point to the segment of the current instruction. In others registers are used implicitly. This type of structure is useful in branch operations. The four pointer registers each with segment offset are also used in a number of operations implicitly. It also has four 16-bit pointers and index registers. Three of these segment registers are used in a dedicated. The data registers can be used as general purpose registers in some instructions. . Example: A multiply instruction always uses accumulator. There are also four segment registers. The 8086 also includes an instruction pointer and a set of 1 bit status and control flags.Figure: Intel 8086 register organization In this machine every register is a special purpose register. The 8086 machine contains four 16-bit data registers that are accessible on a byte or 16-bit basis. The dedicated and implicit uses provide for compact encoding at the cost of reduced flexibility. a segment containing data and a segment containing a stack. There are some registers that also serve as general purpose registers.
There might be different functional breakdown for different applications. Figure 4. There are two other registers called stack pointers that are necessary for stack module.9. A segmented address space uses 7-bit segment number and a 16-bit offset. Here only purely internal registers structure is given and memory address registers are not shown. general set of registers than to save instruction bits by using special purpose registers. The designers of this machines felt that it was useful to provide a regularized. . It uses two registers to hold a single address. One register used for system mode and one for normal mode. which can be used for data. Compare the register organizations of 8085. The Zilog Z8000 Figure depicts the register organization of Z8000 machine. Further the way the functions are assigned to these registers is the responsibility of the programmer. Z8000 and MC68000. address and indexing.6: Zilog Z8000 register organization Z8000 consists of sixteen 16-bit general purpose registers.
There are some registers that also serve as general purpose registers. Example: A multiply instruction always uses accumulator. a segment containing data and a segment containing a stack. In others registers are used implicitly.Z8000 consists of five other registers that are related to program status. The four pointer registers each with segment offset are also used in a number of operations implicitly. This type of structure is useful in branch operations. implicit way to point to the segment of the current instruction. A 16-bit flag register called Flag control word holds various flags status and control bits. The data registers can be used as general purpose registers in some instructions. Figure: Intel 8086 register organization In this machine every register is a special purpose register. Two registers hold the program counter and two registers hold the address of a program status area in the memory. It also has four 16-bit pointers and index registers. Three of these segment registers are used in a dedicated. There are also four segment registers. The 8086 machine contains four 16-bit data registers that are accessible on a byte or 16-bit basis. The 8086 also includes an instruction pointer and a set of 1 bit status and control flags. The Motorola MC68000 . The dedicated and implicit uses provide for compact encoding at the cost of reduced flexibility. 10.
The address registers contain a 32-bit address. The MC68000 also has program counter and status register as in the other two machines. Both the stack pointers are numbered as seven i. depending upon the current execution mode.. Two of the address registers are used as stack pointers: One for the users and one for the operating system.e. A7 as only one can be used at a time. . For the purpose of code efficiency they divided the registers into functional components. 11. The program counter is 32-bit register and status register is 16-bit. 16-bit and 32-bit data operations depending upon the opcode. Like Zilog the Motorola team also supports a regular instruction set with no special purpose registers. It does not support segmentation. Explain the single bus structure.8 The MC6800 machine partitions the 32-bit registers into eight data registers and nine address registers. saving one bit at each registers.Figure: MC68000 register organization This machine uses a structure that falls between the Zilog Z8000 and Intel 8086. The register organization of MC68000 is as shown in figure 4. The data registers are used in data manipulations and are also used in addressing only as index registers. The width of data register allows 8-bit.
This simplifies programming of I/O units as no special I/O instructions are needed. To illustrate this let us take one example. At this time bus and the processor are no longer needed and can be released for other activities. Figure: Single-Bus Organization The transfer of information over a bus cannot be done at a speed comparable to the operating speed of all the devices connected to the bus. Now the printer starts printing. The processor sends the character to the printer output register over the bus. Hence the information can be transferred only between two units at a time. This allows the processor to switch rapidly from one device to another interweaving its processing activity with data transfer involving several I/O devices. memory and I/O devices. Here the I/O units use the same memory address space. This is one of advantages of single bus organization. Since all the devices must communicate over the bus. Thus buffer register smoothes out the timing differences between the processor. it is necessary to smooth out the differences in timings among all the devices. Since buffer is an electronic register this transfer requires relatively little time. Main memory and processors operate at electronic speeds.In Single Bus System type of inter-connection. . Buffer register is not available for other transfers until the process is completed. the three units share a single bus. A common approach is to include buffer register with the devices to hold the information during transfers. Consider the transfer of an encoded character from the processor to a character printer where it is to be printed. Some electromechanical devices such as keyboards and printers are very slow whereas disks and tapes are considerably faster.
This action might not be possible to undo. Are you sure you want to continue?
We've moved you to where you read on your other device.
Get the full title to continue reading from where you left off, or restart the preview.