Code No: RR320405

Set No. 1

III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) With neat sketches explain the formation of the inversion layer in n-channel enhancement MOSFET. (b) A PMOS Transistor is operated in the triode region with the following parameters. VGS = −4.5V ; Vtp = −1V ; VDS = −2.2V ; W/L = 95; µnCox = 95 µA/V 2 Find its drain current and drain source resistance. [8+8] 2. (a) With neat sketches explain CMOS fabrication using p-well process. (b) With neat sketches explain pMOS fabrication process. 3. Design a stick diagram for the NMOS logic shown below Y = (A + B).C [16] 4. Design a layout diagram for pMOS inverter. [16] [10+6]

5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in Figure 5, If n-channel sheet resistance is 104 Ω per square. [16]

Figure 5 6. With neat sketches explain the architecture of PAL. 7. Explain about the following EDA tools. 1 of 2 [16]

Code No: RR320405 (a) Design Rules verification. (b) Layout vs Schematic verification. (c) RC calculation from layout.

Set No. 1
[5+6+5] [16]

8. With neat sketches explain the electron lithography process. ⋆⋆⋆⋆⋆

2 of 2

Code No: RR320405

Set No. 2

III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Find gm and rds for an n-channel transistor with VGS = 1.2V; Vtn = 0.8V; W/L = 10; µnCox = 92 µA/V2 and VDS = Veff + 0.5V The out put impedance constant. λ = 95.3 × 10−3 V−1 (b) Explain the term Figure of merit of a MOS Transistor. [10+6]

2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] 3. Design a stick diagram for p-MOS Ex-NOR gate. 4. Design a layout diagram for two input CMOS NOR gate. [16] [16]

5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If nchannel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance Rsp = 1.5 × 104 Ω per square. [16]

Figure 5 6. (a) What are the advantages and disadvantages of the reconfiguration. (b) Mention different advantages of Anti fuse Technology. [8+8]

7. What are the different inputs that are provided to the place and route tool and explain the significance of each input. [16] 8. (a) With neat sketches explain automatic diffusion mechanism. (b) Explain clearly about different types of packing methods used in IC fabrication. [8+8] 1 of 2

Code No: RR320405 ⋆⋆⋆⋆⋆

Set No. 2

2 of 2

Code No: RR320405

Set No. 3

III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Find gm and rds for an n-channel transistor with VGS = 1.2V; Vtn = 0.8V; W/L = 10; µnCox = 92µA/V2 and VDS = Veff. The out put impedance constant. λ = 95.3 × 10−3 V −1 (b) Define the term Threshold voltage of MOSFET and explain its significance. [10+6] 2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] 3. Design a stick diagram for two input p-MOS NAND and NOR gates. 4. Design a layout diagram for pMOS inverter. [16] [16]

5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If nchannel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance Rsp = 3.5 × 104 Ω per square. [16]

Figure 5 6. (a) What are the advantages and disadvantages of the reconfiguration. (b) Mention different advantages of Anti fuse Technology. 7. Clearly explain each step of high level design flow of an ASIC. 8. Explain about the following two oxidation methods. (a) High pressure oxidation. (b) Plasma oxidation. ⋆⋆⋆⋆⋆ 1 of 1 [8+8] [8+8] [16]

Code No: RR320405

Set No. 4

III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008 VLSI DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Define threshold voltage of a MOS device and explain its significance. (b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8] 2. (a) With neat sketches explain CMOS fabrication using n-well process. (b) Explain how capacitors are fabricated in CMOS process. [10+6] 3. What is a stick diagram and explain about different symbols used for components in stick diagram. [16] 4. (a) What do you mean by layout of a component. (b) Draw neat layout diagrams for NMOS and PMOS transistor. [6+10] 5. Two nMOS inverters are cascaded to drive a capacitive load CL =14Cg as shown in Figure 5. Calculate the pair delay Vin to Vout in terms of τ for the given data. Inverter -A LP.U = 12λ , WP.U = 4 λ , LP.d = 1 λ , WP.d = 1 λ Inverter -B LP.U = 4λ , WP.U = 4 λ , LP.d = 2 λ , WP.d = 8 λ [16]

Figure 5 6. With neat sketches explain the architecture of PAL. 7. Explain the following process in the ASIC design flow. (a) Functional gate level verification. (b) Static timing analysis. [8+8] 8. Mention different growth technologies of the thin oxides and explain about any one technique. [16] ⋆⋆⋆⋆⋆ 1 of 1 [16]