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Set No. 1

II B.Tech Supplimentary Examinations, Aug/Sep 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain diﬀerent methods used to represent negative numbers in binary system. [6] (b) Perform the subtraction with the following unsigned binary numbers by taking the 2’s complement of the subtrahend. [5 × 2 = 10] i. ii. iii. iv. v. 11010 - 10010 11011 - 1101 100 - 110000 1010100 - 1010100 11 -1011 [8]

2. (a) Simplify the following Boolean expressions to minimum no. of literals. i. ii. iii. iv. i. ii. iii. iv. x’y’+xy+x’y xy’+y’z’+x’z’ x’+xy+xz’+xy’z’ (x + y)(x + y’)

(b) Obtain the complement of the following Boolean expressions. AB+A(B+C)+B’(B+D) A+B+A’B’C A’B+A’BC’+A’BCD+A’BC’D’E ABEF+ABE’F’+A’B’EF

[8]

3. (a) What are dominating rows & dominating columns? (b) Minimize the following function using tabular minimization F (A, B, C, D) = m(1, 2, 3, 5, 9, 12, 14, 15) + d(4, 8, 11)

[4] [12]

4. Implement the following Boolean function by a Hazard free OR-AND network. f = m(3, 4, 5, 7) and explain in detail what are the Hazards encountered in implementing the above function. [16] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabilation and the limitations of threshold gates. 6. (a) Compare synchronous & Asynchronous circuits 1 of 2 [8+8]

Code No: R05220403

Set No. 1

[6+10]

(b) Design a Mod-6 synchronous counter using J-K ﬂip ﬂops.

7. (a) A clock mode sequential circuit has to provide z=1 whenever the input completes the Sequence of pulses 1010 and overlapping is allowed. Draw the state diagram and obtain minimal state using partition method. (b) Draw the state diagram of mod-8 Up - Down counter in Moore model and obtain its state table. [8+8] 8. (a) For the given ASM chart of a controller, obtain its equivalent control state diagram 8a.

Figure 8a (b) Design the circuit using multiplexers for the above ASM chart. ⋆⋆⋆⋆⋆

[8+8]

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Code No: R05220403

Set No. 2

II B.Tech Supplimentary Examinations, Aug/Sep 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Perform subtraction with the following unsigned decimal numbers by taking 10’s complement of the subtrahend. Verify the result. [4 × 3 = 12] i. ii. iii. iv. 5250- 1321 1753 - 8640 20 - 100 1200 - 250 [4] [8]

(b) Convert the given gray code number to equivalent binary 1001001011110010 2. (a) Reduce the following Boolean expressions. i. ii. iii. iv. i. ii. iii. iv. ((AB)’+A’+AB)’ AB+(AC)’+AB’+C(AB+C) ((AB’+ABC)’+ A(B+AB’))’ AB+A(B+C)+B(B+C)

(b) Obtain the Dual of the following Boolean expressions. x’y’+xy+x’y xy’+y’z’+x’z’ x’+xy+xz’+xy’z’ (x+y)(x+y’)

[8]

3. Reduce the following function using six variable K- map F = m(0, 2, 5, 7, 9, 11, 14, 16, 18, 21, 23, 27, 30, 32, 34, 36, 41, 43, 44, 48, 50, 52, 53, 59, 60, 61). [16] 4. (a) Implement the multiple output combinational logic circuit using a 4line to 16 line decoder. f1 = m(1, 2, 4, 7, 8, 11, 12, 13, 14, 15) f2 = m(0, 1, 3, 5, 8, 9, 15) f3 = m(2, 3, 4, 7) f4 = m(0, 1, 3, 4, 7, 9) (b) Write short notes on Decoder and Encoder. 5. Write a brief note on: (a) Architecture of PLDs (b) Capabilation and the limitations of threshold gates. 1 of 2 [8+8] [12+6]

Code No: R05220403 6. (a) Compare synchronous & Asynchronous circuits

Set No. 2

[6+10]

(b) Design a Mod-6 synchronous counter using J-K ﬂip ﬂops.

7. (a) A Clocked sequential circuit is deﬁned by the following state-table: Obtain minimal state - table. (b) Give proper assignment and hence [8+8] Present Next state Z State x=0 x=1 x=0 0 0 4 1 1 0 4 0 2 1 5 0 3 1 5 0 4 2 6 0 5 2 6 0 6 3 7 0 7 3 7 0 design the circuit using T - Flip-Flops.

x=1 0 0 0 0 1 1 1 1

8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

2 of 2

Code No: R05220403

Set No. 3

II B.Tech Supplimentary Examinations, Aug/Sep 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Octal. (a) 25716 (b) 19916 (c) 101100012 (d) 110011002 (e) 34410 (f) 76610 [3+3+3+3+2+2]

2. (a) Draw the logic diagram using only two input NAND gates to implement the following expression. [8] (AB+A’B’)(CD’+C’D) (b) Obtain the complement of the following Boolean expressions. i. B’C’D+(B+C+D)’+B’C’D’E ii. AB+(AC)’+(AB+C) (c) Obtain the dual of the following Boolean expressions. i. A’B’C’+A’BC’+AB’C’+ABC’ ii. AB+(AC)’+AB’C [4] [4]

3. Reduce the following function using six variable K- map F = m(0, 2, 5, 7, 9, 11, 14, 16, 18, 21, 23, 27, 30, 32, 34, 36, 41, 43, 44, 48, 50, 52, 53, 59, 60, 61). [16] 4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers. (b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full adder. [8+8] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabilation and the limitations of threshold gates. 6. (a) Explain the following i. Race-around condition in ﬂip ﬂop 1 of 2 [8+8]

Code No: R05220403 ii. J-K Master slave ﬂip ﬂop iii. Excitation table for ﬂip ﬂops.

Set No. 3

[3×2=6]

(b) Draw the state diagram of modulo-4 up/ down counter. Design its circuit using J-K ﬂip ﬂops. [10] 7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D - ﬂip-ﬂops. [4+4+8] 8. (a) For the given control state diagram 8 obtain its ASM chart. (b) Design the circuit using one ﬂip-ﬂop per each state. [8+8]

Figure 8 ⋆⋆⋆⋆⋆

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Code No: R05220403

Set No. 4

II B.Tech Supplimentary Examinations, Aug/Sep 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electronics & Communication Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Binary. (a) 187616 (b) AB2216 (c) 12128 (d) 15568 (e) 97710 (f) 66410 [3+3+3+3+2+2]

2. (a) Draw the NAND logic diagram that implements the complement of the following function. [8] F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12) (b) Obtain the complement of the following Boolean expressions. i. AB+A(B+C)+B’(B+D) ii. A+B+A’B’C (c) Obtain the dual of the following Boolean expressions. i. A’B+A’BC’+A’BCD+A’BC’D’E ii. ABEF+ABE’F’+A’B’EF 3. Minimise on the map the ﬁve variable function. F= m(0, 1, 4, 5, 6, 13, 14, 15, 22, 24, 25, 28, 29, 30, 31). [4] [16] [4]

4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates. (b) Draw the logic diagram of a single bit comparator. 5. Write a brief note on: (a) Architecture of PLDs (b) Capabilation and the limitations of threshold gates. [8+8] [12+6]

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter. (b) Compare synchronous & Asynchronous. [10+6]

1 of 2

Code No: R05220403

Set No. 4

7. (a) Convert the given Mealy Machine to Moore Machine. Present State Next state and Output Z x=0 x=1 x=2 a c,0 b,1 c,2 b c,1 a,0 a,1 c a,2 b,2 b,0 (b) A clocked sequential circuit with single input and single output is speciﬁed by the following state equation and output equations. Q+ = Q1 x + Q2 x Q+ = Q1 x Z = (Q1 + Q2 )x where Q+ , Q+ are the next 1 1 2 2 states. Q1 , Q2 are the outputs of T - ﬂip-ﬂops. Design the circuit using T ﬂip-ﬂops. [8+8] 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

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