IC Lab

OPERATI ONAL AMPLI FI ER
IC Lab
REAL OP AMP SPECI FI CATI ON
è Low-Frequency Voltage Gain A
VO
& Power Dissipation
è 3-dB Frequency f
3dB
& Unity-Gain Frequency f
0
è Slew Rate & Settling Time
è Input / Output Range & Output Impedance
è Offset Voltage & Noise
è PSRR (Power Supply Rejection Ratio)
è CMRR (Common-Mode Rejection Ratio)
+ -
V
IC
CMRR
+ -
∆V
supply
PSRR
+ -
V
offset
+ -
V
n
2
+
-
v
in
g
m
v
in
V
1
ouput
buffer
C
O
R
O
V
2
v
O
IC Lab
2-STAGE MI LLER OP AMP
M
4
M
3
M
2
M
1
M
5
M
6
M
7
C
C
R
C
V
DD
V
SS
v
in
+
v
in
-
v
out
M
8
I
B
C
L
+
-
v
in
-
v
in
+
C
C
R
C
v
out
-A
V1
-A
V2
differential
amplifier
CS
amplifier
IC Lab
2-STAGE MI LLER OP AMP : A
VO
l DC Voltage Gain
l Power Dissipation
M
2
M
1
M
3
M
4
M
5
M
6
M
7
C
C
R
C
V
DD
V
SS
v
in
+
v
in
-
v
out
M
8
I
B
C
L

,
`

.
|
+
− ⋅

,
`

.
|
+
− · ⋅ ·


− +
7 o 6 o
6 m
3 o 1 o
1 m
2 V 1 V
in
in
out
VO
g g
g
g g
g
A A
v v
v
A
( ) ( )
7 5 SS DD
I I V V Power + ⋅ − ·
IC Lab
2-STAGE MI LLER OP AMP : OPERTI NG POI NT
l
l
l
l
l
M
2
M
1
M
3
M
4
M
5
M
6
M
7
C
C
R
C
V
DD
V
SS
v
in
+
v
in
-
v
out
M
8
I
B
C
L
A B
C
D E
F
G
) GND Analog ( 0 V V
B A
· ·
( )
( ) ( ) 2 2 I V
2 I V
V 0 V
1 5 1 TH
1 1 1 TH
1 SG C
β + ·
β + ·
+ ·
( )
( ) ( ) 2 2 I V
2 I V
V V V V
3 5 3 TH
3 3 3 TH
3 GS SS E D
β + ·
β + ·
+ · ·
) GND Analog ( 0 V
F

( ) [ ] 2 I V VDD
V V V
8 B 8 TH
8 SG DD G
β + − ·
− ·
Ma k e Su r e All Tr a n s is t or s
in Sa t u r a t ion !
IC Lab
2-STAGE MI LLER OP AMP : I NPUT COMMON MODE RANGE
l Upper Range : M
5
in Saturation
l Lower Range : M
1(2)
in Saturation
M
2
M
1
M
3
M
4
M
5
V
DD
V
SS
V
IC
V
IC
1 TH 1 D ICL
1 TH ICL 1 D 1 G 1 D 1 DG
V V V
V V V V V V
− >
< − · − ·
( )
( ) ( ) 2 2 I V V V
2 I V V V
V V V V
1 5 1 TH ) sat ( 5 SD DD
1 1 1 TH ) sat ( 5 SD DD
1 SG ) sat ( 5 SD DD ICU
β + − − ·
β + − − ·
− − ·
( )
( ) ( ) 2 2 I V V
2 I V V
V V V V V
3 5 3 TH SS
3 3 3 TH SS
3 GS SS 4 D 3 D 1 D
β + + ·
β + + ·
+ · · ·
( ) ( )
TH 3 5 3 TH SS ICL
V 2 2 I V V V − β + + ·
IC Lab
FEEDBACK & STABI LI TY
ü Unstable Condition : FA
V
(s) = -1
A
v
(s) +
F
+
-
V
in
(s) V
out
(s)
( )
( )
( )
( )
( ) s A F 1
s A
s V
s V
s A
v
v
in
out
⋅ +
· ≡
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
1/F
-90
o
phase
margin
0
( ) ( ) ° − · ∠ · 180 s A &
F
1
s A
v v
IC Lab
SMALL-SI GNAL 2-STAGE MI LLER OP MODEL
M
2
M
1
M
3
M
4
M
5
M
6
M
7
C
C
R
C
V
DD
V
SS
v
in
+
v
in
-
v
out
M
8
I
B
C
L
g
mI
v
in
R
I
C
I
v
in
+
-
v
x
+
-
g
mII
v
x
R
II
C
II
v
out
+
-
R
C
C
C
IC Lab
2-STAGE MI LLER OP AMP : UNCOMPENSATED
( )
( )

,
`

.
|
− ⋅

,
`

.
|

·
II I
v
v
p
s
1
p
s
1
0 A
s A
I I
I
C R
1
p − ·
g
mI
v
in
R
I
C
I
v
in
+
-
v
x
+
-
g
mII
v
x
R
II
C
II
v
out
+
-
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
-90
o
phase margin
0
ω
0
|p
I
| |p
II
|
II II
II
C R
1
p − ·
IC Lab
2-STAGE MI LLER OP AMP : COMPENSATED
è pole splitting
g
mI
v
in
R
I
C
I
v
in
+
-
v
x
+
-
g
mII
v
x
R
II
C
II
v
out
+
-
C
C
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
-90
o
phase
margin
0
ω
0
|p
I
|
|p
II
| z'
-270
o
I II I mII
I
C R R g
1
p − ≅

II
mII
I C C II II I
C mII
II
C
g
C C C C C C
C g
p − ≈
+ +
− ≅

1
C
C
R g
1
p
p
C
I
II mII I
I
<< ·

1
C C C C 1
R g
p
p
II I C I
II mII
II
II
>>
+ +
·

IC Lab
2-STAGE MI LLER OP AMP : TO GET PHASE MARGI N 1
l For frequency > |p’
I
|
l Phase of A
v
(s) @ ω
0
> |p’
I
|
l For Phase Margin Φ
M
l Unity-Gain Frequency
l 2nd pole Frequency
( )
( )
) p s 1 ( ) p s 1 (
s A
s A
II I
v
v
′ + ⋅ ′ +
·
( )
( )
) p s 1 ( ) p s (
s A
s A
II I
v
v
′ + ⋅ ′

( ) ( )
II 0
1
v
p tan 90 s A ′ ω − ° − · ∠

( ) ( )
II M 0 M II 0
1
p 90 tan 90 p tan ′ ⋅ Φ − ° · ω ⇒ Φ − ° · ′ ω

( )
C mI
C II I mII
II mII I mI
I v 0
C g
C R R g
R g R g
p 0 A · ·

⋅ · ω
II mII II
C g p · ′
( )
mI
C
II
M
mII
g
C
C
90 tan
1
g ⋅ ⋅
Φ − °
· ∴
IC Lab
2-STAGE MI LLER OP AMP : ZERO-PROBLEM
l Parasitic Zero
l Role of R
C
l Remove Zero
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
-90
o
phase
margin
0
ω
0
|p
I
| |p
II
| z'
-270
o
C
mII
C
g
z ·

( )
C C mII
C R g 1
1
z

·
′ ′
mII C
g 1 R z · ⇒ ∞ → ′ ′

,
`

.
|
+ ≅ ⇒ ′ · ′ ′
C
II
mII
C II
C
C
1
g
1
R p z
IC Lab
2-STAGE MI LLER OP AMP : R
C
I MPLEMENTATI ON
M
13
M
12
M
6
M
7
C
C
V
DD
V
SS
v
out
M
14
V
B
V
X
M
11
( )
THn 11 GS 11
C
V V
1
R
− β
·
( )
THn 6 GS 6 6 m mII
V V g g − β · ·
11 GS 6 GS 14 GS 13 GS x
V V V V V + · + ·
( )
THn 6 GS THn 11 GS THn 13 GS 6 GS 14 GS
V V k V V V V V V − · − · − ⇒ ·
k
V V
V V

g
1
R
THn 11 GS
THn 6 GS
mII
C
·


⇒ ∝
7
12
13
6
7
12
13
6
6
13
13
6
6
6
13
13
THn 6 GS
THn 13 GS
I
I
I
I
I 2
I 2
V V
V V
k
β
β
β
β
·
β
β
·
β
β
·
β
β
·


·
7
12
7
12
6
14
6
14
6
6
14
14
6 GS 14 GS
I
I
I
I

I I
V V
β
β
· · ·
β
β

β
·
β
⇒ ·
13
14
k
β
β
· ∴
IC Lab
2-STAGE MI LLER OP AMP : WELL COMPENSATED
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
-90
o
phase
margin
0 ω
0
|p
I
|
|p
II
|
( )
( )
I
v
v
p
s
1
0 A
s A


·
( )
C
mII
I v 0
C
g
p 0 A ·

⋅ · ω
IC Lab
OP AMP : TRANSI ENT RESPONSE
l t
0
< t < t
1
è Slewing : Large Signal Behavior
l t
1
< t < t
2
è Settling : Small Signal Behavior
+
-
v
out
(t)
C
L
v
i n
(t)
t
v
out
(t) v
i n
(t)
0
t
0
t
1
t
2
imum max
out
dt
dV
rate slew ·
o
settle
t t
ε < ε
·
IC Lab
2-STAGE MI LLER OP AMP : LARGE-SI GNAL TRANSI ENT
l When V
in
goes to rise initially, M
2
off & All I
5
flows in M
1
M
3
M
4
l V
out
goes up linearly with the rate of
M
5
V
DD
M
1
M
2
M
3
M
4
V
SS
v
in
V
BP
v
out
C
L
C
C
-A
2
I
5
I
5
C
5 out
C
I
dt
dV
·
IC Lab
OP AMP : SMALL-SI GNAL TRANSI ENT – 1st Or der
l Closed-Loop Transfer Function
l Output Waveform
l Time Constant
l Settling Error
l Settling Time
( )
( )
( ) [ ] 0 FA 1 p
s
1
1
0 FA 1
0 A
) s ( A
v 1
v
v
+
+
+
·
( )
( )
( )
τ −
− ⋅ ⋅
+
·
t
step
v
v
out
e 1 V
0 FA 1
0 A
) t ( V
( ) [ ] ( )
0 v 1 v 1
F
1
0 A p F
1
0 FA 1 p
1
ω ⋅
·


+
≡ τ
( ) ( )
( )
τ −
·

≡ ε
t
out
out in
e
t V
t V t V

,
`

.
|
ε
⋅ τ ≡
o
settle
1
ln t
IC Lab
OP AMP : SMALL-SI GNAL TRANSI ENT – 2nd Or der
l Closed-Loop Transfer Function
l Oscillation Frequency
l Q Factor
l Q < 1/2
l Q = 1/2
l Q > 1/2
( ) [ ] ( )
2 0 2 v 1 v 2 1 N
p F p 0 A p F 0 FA 1 p p ω · ≅ + ≡ ω
( ) [ ] ( )
2 1
2 0
2 1
2 v 1
2 1
v 2 1
p p
p F
p p
p 0 A p F
p p
0 FA 1 p p
Q
+
ω
·
+

+
+

( )
( )
2
N
N 2
2
N
v
v
s
Q
s
0 FA 1
0 A
) s ( A
ω +
,
`

.
| ω
+
ω
+
·
( ) ( )
]
]
]
]

,
`

.
|
γ

γ

ω
+ ⋅ ⋅ ·
γ γ
2
t
2
1
t
1
2
N
step out
e e
4 Q 1
1 V 0 A t V
( ) ( ) ( )
t
N
N
t
N
step out
te e 1 V 0 A t V
ω − ω −
ω − − ⋅ ⋅ ·
( ) ( )
]
]
]
]
]
]

¹
¹
¹
¹
¹
'
¹
¹
¹
¹
¹
¹
'
¹

,
`

.
| ω
− +

,
`

.
| ω

− ⋅ ⋅ ·
ω

t
Q 2
1 Q 4 cos
1 Q 4
t
Q 2
1 Q 4 sin
e 1 V 0 A t V
N 2
2
N 2
t
Q 2
N
step out
IC Lab
OP AMP : SMALL-SI GNAL TRANSI ENT – 2nd Or der (c ont ’ d)

0 2 4 6 8 10
0
0.2
0.4
0.6
0.8
1
1.2
normalized time
n
o
r
m
a
l
i
z
e
d

o
u
t
p
u
t
Q=0.1 Q=0.5
Q=1.0
IC Lab
2-STAGE MI LLER OP AMP : SMALL-SI GNAL TRANSI ENT
l By Substitution of p’
I
& p’
II
l For Phase Margin Φ
M
( ) { ¦
F
g
g
C g
C F g g
C g C 0 A g
C F g g
Q
mII
mI
II mII
II mII mI
II mII II v mI
II mII mI
· ≅
+
·
II
mII mI
N
C
F g g
· ω
( )
mI mI
C
II
M
mII
g g
C
C
90 tan
1
g ⋅ α ≡ ⋅ ⋅
Φ − °
·
0
II
C
II
mI
N
C
C
F
C
g F
ω ⋅ ⋅ ⋅ α ·
⋅ ⋅ α
· ω
α
··
F
Q
IC Lab
2-STAGE MI LLER OP AMP : SMALL-SI GNAL TRANSI ENT (c ont ’ d)
C
C
=C
L
, F=2
Φ
M
80º 40º
α 5.67 0.84
ω
N
1.68 ω
0
0.65 ω
0
Q 0.30 0.77
0 5 10 15 20
-0.5
0
0.5
1
1.5
0 5 10 15 20
10
-6
10
-4
10
-2
10
0
normalized time
n
o
r
m
a
l
i
z
e
d
o
u
t
p
u
t
PM=80
o
r
e
l
a
t
i
v
e
e
r
r
o
r
PM=40
o
PM=80
o
PM=40
o
+
-
v
out
(t)
C
L
v
in
(t)
R
2
= 100kΩ
R
1
= 100kΩ
IC Lab
OP AMP : OFFSET VOLTAGE
l Definition
l For Non-Ideal Differential Pair
è BJT :
è CMOS :
l Random Offset Component Due to Process
l Systematic Offset Component Due to Circuit Design
0
out
V
in OFFSET
V V

∆ ≡
m
OFFSET
g
I
V


e temperatur room @ mV 26
q
kT
g
I
m
· ·
100mV several
2
V V
g
I
TH GS
m


·
IC Lab
2-STAGE MI LLER OP AMP : RANDOM OFFSET VOLTAGE
l Random Characteristics l 1
st
Stage Random Offset
V
offset
#
0
V
OFFSET
M
1
M
2
I
SS
R
L1
R
L2
V
DD
V
O1
V
O2
]
]
]



∆ − −
+ ∆ ·
L W
L W
R
R
2
V V
V V
L
L TH GS
TH OFFSET
IC Lab
2-STAGE MI LLER OP AMP : SYSTEMATI C OFFSET VOLTAGE
M
2
M
1
M
3
M
4
M
5
M
6
M
7
V
DD
V
SS
V
out
=0V
V
DS3
+
-
+
-
V
GS6
V
BP
4
5
THn
4
4
THn 4 GS 4 DS 3 DS
I
V
I 2
V V V V
β
+ ·
β
+ · · ·
6
7
THn
6
6
THn 6 GS
I 2
V
I 2
V V
β
+ ·
β
+ ·
4
7
5
7 6
I
I
2 I
I
4
· ·
β
β

IC Lab
MOSFET NOI SE MODEL
l 1-f Noise
l Thermal Noise
l MOSFET Noise Model
( )
f
1
WL C
K
f V
ox
2
f 1
⋅ ·
( ) ( )
m
2
thrml m
2
thrml
g
1
3
2
kT 4 f V g
3
2
kT 4 f I ⋅ ⋅ · ⇔ ⋅ ⋅ ·
V
1/f
2
(f)
I
thrml
2
(f)
V
1/f
2
(f)
V
t hrml
2
(f)
IC Lab
2-STAGE MI LLER OP AMP : I NPUT-REFERRED NOI SE
M
2
M
1
M
3
M
4
M
5
M
6
M
7
V
DD
V
SS
V
out
V
BP
V
n,5
2
V
n,7
2
V
n,2
2
V
n,1
2
V
n,3
2
V
n,4
2
V
n,6
2
M
2
M
1
M
3
M
4
M
5
M
6
M
7
V
DD
V
SS
V
out
V
BP
V
n,eq
2
( )
2
4 , n
2
3 , n
2
3 m
1 m 2
2 , n
2
1 , n
2
eq , n
V V
g
g
V V V +

,
`

.
|
+ + ·
( )
f
1
L
L
K
K
1
WL C
K 2
f V
2
3
2
1
p p
n n
ox
p
2
eq , f / 1

,
`

.
|
µ
µ
+ ⋅ ·
( )
( )
( )
( )

,
`

.
|
µ
µ
+ ⋅
µ
⋅ ·
1
p
3
n
1
1
ox p
2
thrml
L W
L W
1
I L W C 2
4
kT 4 f V
IC Lab
OP AMP : CMRR
l Definition
l Modeling & Simulation
( )
c
d
in
in
c in
in
d out
A
A
CMRR
2
V V
A V V A V ≡ ⇒

,
`

.
|
+
⋅ + − ⋅ ·
− +
− +
+
-
v
out
+
+
-
-
v
cm
v
cm
v
+
v
-
v
out
+
+
-
-
v
cm
v
cm
v
+
v
-
A
d
(v
+
-v
-
)
+
-
A
c
(v
+
+v
-
)/2
+
-
CMRR
1
A
A
2
A
A 1
A
V
V
d
c
c
d
c
cm
out
· ≅
− +
·
IC Lab
OP AMP : PSRR
l Definition
l Modeling & Simulation
( )


+
+
− + − +
≡ ≡ ⇒
∆ ⋅ + ∆ ⋅ + − ⋅ ·
p
d
p
d
SS p DD p in
in
d out
A
A
RR S P ,
A
A
RR S P
V A V A V V A V
+
+
· ≅

PSRR
1
A
A
V
V
d
p
DD
out
+
-
v
out
v
+
v
-
v
out
+
-
-
V
DD
v
+
v
-
A
d
(v
+
-v
-
)
+
-
A
p
+
∆V
DD
+
-
+
∆V
DD
IC Lab
2-STAGE MI LLER OP AMP : PSRR
M
6
M
2
M
1
M
3
M
4
M
5
M
6
M
7
C
C
V
DD
V
SS
v
i n
+
v
i n
-
v
out
V
BB
v
out
M
7
V
DD
V
SS
r
o7
1/g
m6
IC Lab
2-STAGE MI LLER OP AMP : NUMERI CAL DESI GN
DC Gain A
v
(0) [dB] ¡ Ã66
Unity-Gain Frequency f
0
[MHz] 25 C
L
=10pF
Phase Margin [ ° ] 60
Slew Rate [V/µsec] 25
Power Dissipation [mW] ¡ Â2.5 ¡ ¾2.5V
SNR @ 1kHz [dB] ¡ Ã90 V
IN
=0.5V
RMS
è
è
è
è
è
è
( ) [pF] 0 . 5 C 2 1 C
L C
· ⋅ ·
[A/V] 10 785 . 0 C g C g
3
C 0 1 m C 1 m 0

× · ⋅ ω ≅ ⇒ ≅ ω
[A] 10 125 C SR I C I SR
6
C 5 C 5

× · ⋅ · ⇒ ·
( ) ( ) 85 . 140 L W I L W C I I 2 g
1
5
1
ox p 5 1 1 1 1 m
· ⇒ µ · β · β ·
( ) [ ] ( ) [A/V] 10 719 . 2 g C C 90 tan g
3
1 m C L
1
M 6 m
− −
× · ⋅ ⋅ Φ − ° ·
( ) ( ) [A] 10 375 I V V I I Power
6
7 SS DD 7 5

× · ⇒ − ⋅ + ·
IC Lab
2-STAGE MI LLER OP AMP : NUMERI CAL DESI GN (c ont ’ d)
è
è
è
è
è
( ) ( ) 43 . 246 L W I L W C I 2 I 2 g
6
7
6
ox n 7 6 6 6 6 m
· ⇒ µ · β · β ·
( )
( )
( ) 07 . 41 L W 6
I
I
I
I
L W
L W
3
1
7
3
6
3
6
· ⇒ · · ·
( ) ( ) [ ] ( ) [ ] [dB] 1 . 67 2276 r r g r r g 0 A
7 o 6 o 6 m 3 o 1 o 1 m v
→ · ⋅ ·
[ ] [ ] ( ) [ ] ] [ 10 67 . 106 2 I I g r
3 1
5 p
1
1 p
1
1 o 1 o
Ω × · λ · λ · ·
− − −
[ ] [ ] ( ) [ ] ] [ 10 00 . 320 2 I I g r
3 1
5 n
1
3 n
1
3 o 3 o
Ω × · λ · λ · ·
− − −
[ ] [ ] [ ] ] [ 10 33 . 53 I I g r
3 1
7 n
1
6 n
1
6 o 6 o
Ω × · λ · λ · ·
− − −
[ ] [ ] ] [ 10 78 . 17 I g r
3 1
7 p
1
7 o 7 o
Ω × · λ · ·
− −
( )
( )
( )
] [V 10 183 f
L W
L W
1
I L W C 2
4
kT 4 V
2 15
1
p
3
n
1
1
ox p
2
eq , thermal

× · ∆ ⋅

,
`

.
|
µ
µ
+ ⋅
µ
⋅ ·
[dB] 4 . 107
V
V
log 10 SNR
2
eq , thermal
2
rms IN,
·

,
`

.
|
·
IC Lab
FOLDED-CASCODE OP AMP : CONSTRUCTI ON
l Single Stage Amplifier
l Compensation w/ Load Capacitance è Suitable for SC Circuits
M
0
V
DD
C
L
M
1
M
2
M
3
M
4
M
6
M
8
M
5
M
7
V
SS
v
in
-
v
in
+
V
BN1
V
BN2
v
out
M
0
V
DD
M
1
M
2
M
6
M
8
M
5
M
7
V
SS
v
in
-
v
in
+
V
BN1
V
BP2
v
out
M
9
M
10
M
3
M
4
V
BP1
IC Lab
FOLDED-CASCODE OP AMP : AC CHARACTERI STI CS
l Voltage Gain
l Frequency Response
l Unity-Gain Frequency
( )
( )
]
]
]

+
⋅ · ⋅ ·
10 o 2 o 4 o
4 m
8 o 6 o
6 m
1 m out 1 m v
g g g
g
g g
g
g r g 0 A
( )
( ) ( )
( )
L out
v
I
v
v
C r s 1
0 A
p s 1
0 A
s A
+
·

·
|A
v
(s)| [dB]
ω
ω
-180
o
|A
v
(0)|
<A
v
(s)
-90
o
phase
margin
0
ω
0
|p
I
|
|p
II
|
( )
L
1 m
II v 0
C
g
p 0 A · ⋅ · ω
gs out gs
1 m
gs ernal int
II
C r
1
C
g
C r
1
p >> → ·
IC Lab
FOLDED-CASCODE OP AMP : NUMERI CAL DESI GN
DC Gain A
v
(0) [dB] ¡ Ã60
Unity-Gain Frequency f
0
[MHz] 20 C
L
=10pF
Phase Margin [ ° ] 60
Slew Rate [V/µsec] 10
Power Dissipation [mW] ¡ Â2.5 ¡ ¾2.5V
Output Range [V] -1.0 ~ +1.0
è
è
è
è
è
è
[A/V] 10 256 . 1 C g C g
3
L 0 1 m L 1 m 0

× · ⋅ ω ≅ ⇒ ≅ ω
[A] 10 100 C SR I C I SR
6
L 0 L 0

× · ⋅ · ⇒ ·
( ) ( ) 19 . 197 L W I L W C I I 2 g
1
0
1
ox n 0 1 1 1 1 m
· ⇒ µ · β · β ·
( ) ( ) ( ) [A] 10 250 I V V I 2 V V I I Power
6
9 SS DD 9 SS DD 10 9

× · ⇒ − ⋅ · − ⋅ + ·
[A] 10 200 I I I I I [A] 10 50 2 I I
6
1 9 7 5 3
6
0 1
− −
× · − · · · × · ·
[A] 10 200 I I I I I [A] 10 50 2 I I
6
2 10 8 6 4
6
0 2
− −
× · − · · · × · ·
IC Lab
FOLDED-CASCODE OP AMP : NUMERI CAL DESI GN (c ont ’ d)
è M
5-8
è M
5-8
è M
5-8
è M
3-4
,M
9-10
è M
3-4
è M
5-8
è
è
[V] 425 . 0 V V - -1.0 2V V
DSn(sat) SS DSn(sat) THn
· ⇒ · +
( )( ) ( ) [A/V] 10 215 . 2 V 2 V V 2 I
3
8 5
2
DSn(sat) 8 - 5
2
THn GSn 8 - 5 8 - 5


× · β ⇒ β · − β ·
( ) ( ) 68 . 27 L W L W C
8 5 8 5
ox n 8 5
· ⇒ µ · β
− −

( ) ( ) 98 . 126 L W [A/V], 10 444 . 4 V 2 I
4 3
3
4 3
2
SDp(sat) 4 - 3 4 - 3
· × · β ⇒ β ·



[V] 300 . 0 V 1.0 - V 2V V
SDp(sat) DD SDp(sat) THp
· ⇒ · +
( ) ( ) 73 . 158 L W [A/V], 10 556 . 5 V 2 I
10 9
3
10 9
2
SDp(sat) 10 - 9 10 - 9
· × · β ⇒ β ·



( )
( )
[dB] 61 1122
g g g
g
g g
g
g r g 0 A
10 o 2 o 4 o
4 m
8 o 6 o
6 m
1 m out 1 m v
→ ·
]
]
]

+
⋅ · ⋅ ·
[A/V] 10 941 . 0 I 2 g
3
6 6 6 m

× · β · [A/V] 10 10 I g g
6
6 n 8 o 6 o

× · λ · ·
[A/V] 10 333 . 1 I 2 g
3
4 4 4 m

× · β ·
[A/V] 10 30 I g
6
4 p 4 o

× · λ ·
[A/V] 10 5 . 7 I g
6
2 p 2 o

× · λ · [A/V] 10 5 . 37 I g
6
10 p 10 o

× · λ ·
0 ernal int
4 GS
2 o 10 o 4 o 4 m
min
GS
o m
ernal int
f [GHz] 4 . 1 f
C
g g g g
C
g g
p >> · ⇒
+ + +
·

+
·
IC Lab
FOLDED-CASCODE OP AMP : FULLY-DI FFERENTI AL
l Voltage Gain
l Common-Mode Noise Can Be
Removed
l Common-Mode Feedback
(CMFB) Circuit Needed
C
L
M
0
V
DD
M
1
M
2
M
6
M
8
M
5
M
7
V
SS
v
in
-
v
in
+
V
BN1
V
BN1
v
out
+
M
9
M
10
M
3
M
4
V
BP1
V
CMFB
C
L
v
out
-
V
BP2
V
SS
− +
− +



in
in
out out
v
V V
V V
A
IC Lab
FOLDED-CASCODE OP AMP : FULLY-DI FFERENTI AL (I MPROVED)
C
L
M
0
V
DD
M
1
M
2
M
6
M
8
M
5
M
7
V
SS
v
in
-
v
in
+
V
BN1
V
BN1
v
out
+
M
9
M
10
M
3
M
4
V
BP1
V
CMFB
C
L
v
out
-
V
BP2
V
SS
+
-
+
-
V
BN1
+
-
+
-
V
BP1
( )
( )
]
]
]

+
⋅ ⋅
⋅ · ⋅ ·
10 o 2 o 4 o
4 m
8 o 6 o
6 m
1 m out 1 m v
g g g
g A
g g
g A
g r g 0 A
IC Lab
CMFB EXAMPLE (CONTI NUOUS-TI ME)
l Using Averaging Resistors l Using 2 Differential Pairs
M
1
V
REF
V
SS
M
6
M
5
V
DD
v
out
+
v
out
-
M
3
M
2
M
4
R
P
R
M
C
P
C
M
M
7
M
8
M
9
V
CNTL
V
CM
V
BP
V
BN
V
REF
V
SS
M
2
M
1
V
DD
v
out
+
v
out
-
M
3
V
CNTL
V
BP
I
B
M
4
M
5
M
6
M
7
M
9
M
8
I
B
IC Lab
CMFB EXAMPLE (DI SCRETE-TI ME)
l For Φ
1
l For Φ
2
v
out
+
v
out
-
C
C
V
CNTL
V
B
C
S
C
C
C
S
V
B
φ
1
φ
1
φ
2
φ
2
φ
1
φ
2
φ
1
φ
2
( )
B S 1
V C 2 Q − ⋅ ⋅ · ∑
( )( ) ( )( )
CNTL out C S CNTL out C S 2
V V C C V V C C Q − + + − + · ∑
− +
B
C S
S out out
CNTL
V
C C
C
2
V V
V
+
+
+
· ∴
− +
IC Lab
RAI L-TO-RAI L I NPUT STAGE : SI NGLE DI FFERENTI AL PAI R
l Single-Polarity Differential Pair Limits Input Range
l nMOS Differential Pair
l pMOS Differential Pair
M
2
M
1
M
3
v
in
-
V
BN
V
SS
v
in
+
V
DS3(sat)
V
GS1
V
SS
operating
input range
M
5
M
4
M
6
v
in
-
V
BP
V
DD
v
in
+
V
SD6(sat)
V
SG4
V
DD
operating
input range
( ) DD INPUT GS sat DS SS
V V V V V ≤ ≤ + +
( )
( )
GS sat DS DD INPUT SS
V V V V V + − ≤ ≤
IC Lab
RAI L-TO-RAI L I NPUT STAGE : DOUBLE DI FFERENTI AL PAI R
l For Input ~ V
SS
è nMOS off & pMOS on
è g
mIN
= g
mp
l For Input ~ V
DD
è nMOS on & pMOS off
è g
mIN
= g
mn
l For Input ~ 0
è nMOS on & pMOS of
è g
mIN
= g
mp
+g
mn
C
L
M
3
V
DD
M
1
M
2
M
12
M
14
M
11
M
13
V
SS
v
in
-
v
in
+
V
BN0
V
BN1
v
out
+
M
9
M
10
M
7
M
8
V
BP1
V
CMFB
v
out
-
V
BP2
V
SS
M
5
M
4
V
DD
v
in
+
v
in
-
V
BP0
M
6
C
L
IC Lab
RAI L-TO-RAI L I NPUT STAGE : CONSTANT Gm APPROACH
l For nMOS Differential Pair Off : g
mp
è 2g
mp
by Providing I
SSP
+3I
SSP
l For pMOS Differential Pair Off : g
mn
è 2g
mn
by Providing I
SSN
+3I
SSN
l For Both Differential Pair On : No Additional Current
M
1N
M
2N
V
SS
v
in
-
v
in
+
M
2P
M
1P
V
DD
v
in
+
v
in
-
I
SS
M
3
V
REFN
I
SS
V
REFP
M
4
M
5
M
6
M
7
M
8
IC Lab
CLASS-AB OUTPUT STAGE : CD
l Small Output Impedance Preferable
l Output Range Limited By 2V
GS
+V
DS(sat)
Each
l Quiescent Point
l Distortion Possible Due to Full-Off of M
1
or M
2
M
1
M
2
M
3
M
4
v
out
v
in
V
DD
V
SS
I
1
I
2
I
REF
I
REF
I
OUT
I
OUT
=I
1
-I
2
0 4I
Q
-4I
Q
4I
Q
4I
Q
I
Q
I
Q
I
2
I
1
I
1
I
2
Q REF
3
1
2 1
I 2 I 2 I I ·
β
β
· +
IC Lab
CLASS-AB OUTPUT STAGE : CS
l Output Range Limited By V
DS(sat)
Each
l Quiescent Point
l Negligible Distortion Due to
M
1
M
2
v
out
v
in1
V
DD
V
SS
I
1
I
2
I
OUT
=I
1
-I
2
0 4I
Q
-4I
Q
I
Q
I
Q
I
2
I
1
I
1
I
2
M
3
M
4
M
5
M
7
M
6
M
8
I
B
2I
B
I
B
2I
B
v
in2
I
min
I
min
7 5
B
2
3
1 1
Q
1 1 1
where , I I
β
+
β
·
α

,
`

.
|
β
β

α
β
·
B
2
3
1 1
min
I 2 I ⋅

,
`

.
|
β
β

α
β
·
IC Lab
CLASS-AB OUTPUT STAGE : CS (EXACT CONTROL)
l Exact Control By Feedback Amplifier
l Quiescent Point
l Minimum Current
M
1
M
2
v
out
v
in1
V
DD
V
SS
I
1
I
2
M
3
M
4
M
5
M
7
M
6
M
8
I
B1
2I
B1
2I
B2
v
in2
I
B1
I
B1
2I
B2
M
9
M
10
M
11
M
12
1 B
12
6
2 B Q
I I 2 I
β
β
− ·
( )
1 B
2
9
12
12
8
2 B min
I 1 2 1 I 2 I ⋅

,
`

.
|
β
β
− +
β
β
− ·
IC Lab
VARI OUS OP AMP EXAMPLE (MULTI -LOOP, MULTI-PATH)
l Multi-Stage For Large Gain w/o Using Cascode Stage
l Multi-Loop & Multi-Path Compensation
l Combined High-Freq. Path (A
4
-A
1
) & High-Freq. Path (A
3
-A
2
-A
1
)
to Achieve Pole-Zero Cancellation when
1 IEEE JSSC pp. 1709-1717, 1992.
A
1
V
SS
V
DD
v
out
A
2
A
3
A
4
p
1
p
2
p
3
v
in
C
m1
C
m2
g
m4
g
m3
g
m2
g
m1
|A
v
(s)| [dB]
ω
|A
v
(0)|
0
p'
2
p'
3
p'
1
ω
0dB
1 m 4 m 2 m 3 m
C g C g ·
IC Lab
VARI OUS OP AMP EXAMPLE (REPLI CA AMP)
l w/o Replica Amp
l w/ Replica Amp
1 IEEE ISSCC pp. 116-117, 1993.
v
out
R
o
v
in
Z
F
+
-
Z
S
v'
out
R
o
Z
F
+
-
Z
S
+
-
v
x
v
y
g
m
g
m
g
m
main
amp
replica
amp
( )
o in
out
A 1 1
1
V
V
β + +
β − ·
( )
( )
o
o
1
A 1 1
A 1
β + +
β +
· ε
( )
o
o
in
out
A 1 1
A 1
1
1
V
V
β + +
+ β +
β +
+
β − ·
( )
( )
( ) ( ) β +
ε

β + +
+ β +
β +
· ε
1 A A 1 1
A 1 A
1
o
1
o
o o
2
2
IC Lab
VARI OUS OP AMP EXAMPLE (SWI TCHED)
l Replace the Switch on Signal Path
l Power Saving When Not Used
1 IEEE JSSC pp. 936-942, 1994.
M
2
M
1
M
3
M
4
M
5
M
6
M
7
C
C
R
C
V
DD
V
SS
v
in
+
v
in
-
v
out
M
8
I
B
C
L
M
CP
M
CN
φ
φ

REAL OP AMP SPECIFICATION
VIC V1 CMRR + ∆V supply PSRR + V offset + V n2 + + vin V2 gm vin CO RO ouput buffer vO

è Low-Frequency Voltage Gain AVO & Power Dissipation è 3-dB Frequency f3dB & Unity-Gain Frequency f0 è Slew Rate & Settling Time è Input / Output Range & Output Impedance è Offset Voltage & Noise è PSRR (Power Supply Rejection Ratio) è CMRR (Common-Mode Rejection Ratio)
IC Lab

2-STAGE MILLER OP AMP
VDD M5

M8

M7

vin -

M2

M1

vin + CC RC

vout CL

IB

M4

M3

M6

VSS CC RC

vin+ vin-

+ -A V1 differential amplifier -A V2 CS amplifier

vout

IC Lab

2-STAGE MILLER OP AMP : AVO
VDD M5

M8

M7

v in-

M2

M1

vin+ CC RC

vout CL

IB

M4

M3

M6

VSS

l DC Voltage Gain
A VO ≡  g m1   g m6   ⋅ − = A V1 ⋅ A V 2 =  −  g +g   g +g   + − v in − v in  o1 o3   o6 o7  v out

l Power Dissipation

Power = (VDD − VSS ) ⋅ (I5 + I7 )
IC Lab

2-STAGE MILLER OP AMP : OPERTING POINT VDD M5 G l VA = VB = 0 ( Analog GND ) M7 M8 C vinA D IB M4 M2 l VC = 0 + VSG1 = VTH1 + CL = VTH1 + I1 (β1 2) M1 B v in+ CC RC F vout (I5 2) (β1 2) E M3 M6 l VD = VE = VSS + VGS3 = VTH3 + VSS = VTH3 + I 3 (β3 2 ) (I 5 2) (β3 2 ) Make Sure All Transistors in Saturation ! l VF ⇒ 0 ( Analog GND ) l VG = VDD − VSG8 = VDD − VTH8 + IB (β8 2) [ ] IC Lab .

2-STAGE MILLER OP AMP : INPUT COMMON MODE RANGE l Upper Range : M5 in Saturation VICU = VDD − VSD5(sat ) − VSG1 M5 V DD = VDD − VSD5(sat ) − VTH1 + I1 (β1 2) = VDD − VSD5(sat ) − VTH1 + (I 5 2 ) (β1 2) VIC M2 M1 VIC l Lower Range : M1(2) in Saturation VDG1 = VD1 − VG1 = VD1 − VICL < VTH1 VICL > VD1 − VTH1 M4 M3 VSS VD1 = VD3 = VD4 = VSS + VGS3 = VSS + VTH3 + I3 (β3 2 ) = VSS + VTH3 + (I 5 2) (β3 2) VICL = VSS + VTH3 + (I5 2) (β3 2) − VTH IC Lab .

FEEDBACK & STABILITY Vin(s) + + Av(s) Vout(s) A (s ) ≡ F Vout (s ) A v (s ) = Vin (s ) 1 + F ⋅ A v (s ) ü Unstable Condition : F AV(s) = -1 |A v(s)| [dB] |A v(0)| 1/F 0 ω ω -90 o phase margin -180 o <Av(s) A v (s ) = 1 F & ∠A v (s ) = −180 ° IC Lab .

SMALL-SIGNAL 2-STAGE MILLER OP MODEL VDD M5 M8 M7 vin - M2 M1 vin + CC RC vout CL IB M4 M3 M6 VSS RC + vin gmI vin RI + CI vx - CC + gmII vx RII CII vout - IC Lab .

2-STAGE MILLER OP AMP : UNCOMPENSATED + vin gmI vin RI + CI vx gmII vx RII CII + vout - |A v(s)| [dB] |A v(0)| A v (s ) = 0 ω0 |p I| |p II | ω ω -90o phase margin A v (0 )  s   s  1 −  ⋅ 1 −     pI   p II    1 R ICI 1 R IICII pI = − p II = − -180o <A v(s) IC Lab .

2-STAGE MILLER OP AMP : COMPENSATED CC + vin |A v(s)| [dB] |A v(0)| + gmI vin RI CI vx gmII vx RII CII + vout - p′I ≅ − |p II| |p I| ω0 z' ω ω 1 g mIIR IR IICI g mIICC g ≈ − mII CICII + CIIC C + CC CI C II 0 p′II ≅ − -90 o phase margin -180 o p′I 1 CI = << 1 pI g mIIR II CC p′II g mIIR II = >> 1 p II 1 + C I CC + CI CII -270 o <Av(s) è pole splitting IC Lab .

2-STAGE MILLER OP AMP : TO GET PHASE MARGIN 1 A v (s ) = A v (s ) (1 + s p′ ) ⋅ (1 + s p′II ) I A v (s ) (s p ′I ) ⋅ (1 + s p′II ) −1 l For frequency > |p’I| l Phase of Av(s) @ ω 0 > |p’I| l For Phase Margin ΦM l Unity-Gain Frequency l 2nd pole Frequency A v (s ) ≅ ∠ A v (s ) = − 90 ° − tan −1 (ω 0 p ′II ) tan (ω 0 p ′II )= 90 ° − Φ M ⇒ ω 0 = tan (90 ° − Φ M ) ⋅ p ′II g mI R I g mII R II g mII R I R II C C = g mI C C ω 0 = A v (0 ) ⋅ p ′ = I p ′II = g mII C II ∴ g mII = 1 tan (90 ° − Φ M ) CC ⋅ C II ⋅ g mI IC Lab .

2-STAGE MILLER OP AMP : ZERO-PROBLEM |A v (s)| [dB] |A v(0)| l Parasitic Zero ω0 |p I | z' |p II| ω z′ = ω g mII CC 0 l Role of RC z ′′ = 1 -90 o -180 o phase margin -270 o <A v (s) (1 g mII − R C )C C l Remove Zero z ′′ → ∞ ⇒ R C = 1 g mII z ′′ = p ′II ⇒ RC ≅  C II 1 + g mII  CC  1     IC Lab .

2-STAGE MILLER OP AMP : RC IMPLEMENTATION V DD M12 M7 RC = VB β11(VGS11 − VTHn ) 1 VX M13 M11 M14 M6 CC v out g mII = g m 6 = β6 (VGS6 − VTHn ) RC ∝ 1 g mII ⇒ VGS 6 − VTHn =k VGS11 − VTHn Vx = VGS13 + VGS14 = VGS6 + VGS11 VSS VGS14 = VGS 6 ⇒ VGS13 − VTHn = VGS11 − VTHn = k (VGS6 − VTHn ) k= VGS13 − VTHn = VGS6 − VTHn VGS14 = VGS6 ⇒ 2I13 β6 = β13 2I6 I14 = β14 ∴k = β6 β13 I13 = I6 β6 β13 I12 = I7 β6 β12 β13 β7 I6 I β β I ⇒ 14 = 14 = 12 = 12 β6 β6 I6 I7 β7 β14 β13 IC Lab .

2-STAGE MILLER OP AMP : WELL COMPENSATED |A v(s)| [dB] |A v(0)| |p II| 0 |p I| ω0 ω ω -90o phase margin -180o <A v(s) A v (s ) = A v (0) s 1− p′ I g mII CC IC Lab ω0 = A v (0 ) ⋅ p ′ = I .

OP AMP : TRANSIENT RESPONSE vin(t) + CL vout (t) vin (t) vout (t) t0 t1 0 t2 t l t0 < t < t1 è Slewing : Large Signal Behavior slew rate = dVout dt max imum l t1 < t < t2 è Settling : Small Signal Behavior tsettle = t ε<ε o IC Lab .

2-STAGE MILLER OP AMP : LARGE-SIGNAL TRANSIENT VDD VBP M5 CC M1 I5 M3 VSS M4 -A 2 M2 vin vout I5 CL l When V in goes to rise initially. M2 off & All I 5 flows in M1 M3 M4 l Vout goes up linearly with the rate of dVout I = 5 dt CC IC Lab .

OP AMP : SMALL-SIGNAL TRANSIENT – 1st Order A v (0 ) 1 + FA v (0 ) l Closed-Loop Transfer Function A(s ) = 1 1+ s p1 [1 + FA v (0 )] l Output Waveform Vout (t ) = A v (0 ) ⋅ Vstep ⋅ 1 − e − t τ 1 + FA v (0 ) ( ) l Time Constant τ≡ 1 1 1 ≅ = p1 [1 + FA v (0 )] F ⋅ p1 A v (0 ) F ⋅ ω0 Vin (t ) − Vout (t ) = e− t τ Vout (t ) l Settling Error ε≡ l Settling Time 1  t settle ≡ τ ⋅ ln  ε   o IC Lab .

OP AMP : SMALL-SIGNAL TRANSIENT – 2nd Order l Closed-Loop Transfer Function ω2 A v (0 ) N A(s ) = 1 + FA v (0 ) 2  ωN  s + s + ω2 N  Q  F p1 A v (0 ) p2 = Fω0 p 2 p1 + p 2 Fω0 p 2 l Oscillation Frequency ωN ≡ p1 p 2 [1 + FA v (0 )] ≅ F p1 A v (0 ) p2 p1 + p2 l Q Factor Q≡ p1 p 2 [1 + FA v (0 )] ≅ p1 + p 2 = l Q < 1/2 l Q = 1/2   e γ1t e γ 2t   ωN   Vout (t ) = A (0 ) ⋅ Vstep ⋅ 1 + −  γ 2   1 Q 2 − 4  γ1   Vout (t ) = A (0 ) ⋅ Vstep ⋅ 1 − e −ωN t − ωNte −ωNt ( ) l Q > 1/2   ωN  sin 4Q2 − 1 ω N t     − t  2Q    2 − 1 ωN t   2Q  Vout (t ) = A (0 ) ⋅ Vstep ⋅ 1 − e + cos 4Q   2 −1  2Q    4Q       IC Lab .

4 0.OP AMP : SMALL-SIGNAL TRANSIENT – 2nd Order (cont’d) 1.2 Q=1.2 0 0 2 4 6 8 10 normalized time IC Lab .1 0.5 0.8 Q=0.6 0.0 1 normalized output Q=0.

2-STAGE MILLER OP AMP : SMALL-SIGNAL TRANSIENT l By Substitution of p’I & p’II ωN = Q= g mI g mII F CII g mIg mIIF CII = g mII CII g mI F g mII g mIg mIIF CII ≅ g mI {A v (0 )C II} + g mII CII l For Phase Margin ΦM ωN = α ⋅ F ⋅ g mI = CII g mII = α⋅F ⋅ 1 C ⋅ II ⋅ g mI ≡ α ⋅ g mI tan (90° − Φ M ) CC CC ⋅ ω0 CII Q == F α IC Lab .

5 0 -0.67 1.30 40º 0.84 0.5 normalized output vout(t) 1 0.5 0 10 0 PM=40 o PM=80 o CC=CL. F=2 relative error 5 10 15 20 ΦM α ωN Q 80º 5.2-STAGE MILLER OP AMP : SMALL-SIGNAL TRANSIENT (cont’d) R2 = 100kΩ R1 = 100kΩ vin (t) + CL 1.77 10 -2 PM=40 o 10 -4 PM=80 o -6 10 0 5 10 15 20 normalized time IC Lab .65 ω 0 0.68 ω 0 0.

OP AMP : OFFSET VOLTAGE l Definition VOFFSET ≡ ∆Vin V out ⇒ 0 VOFFSET ∝ ∆I gm l For Non-Ideal Differential Pair è BJT : è CMOS : I gm I gm = = kT = 26 mV @ room temperatur e q VGS − VTH ≈ several 100mV 2 l Random Offset Component Due to Process l Systematic Offset Component Due to Circuit Design IC Lab .

2-STAGE MILLER OP AMP : RANDOM OFFSET VOLTAGE l Random Characteristics # l 1st Stage Random Offset VDD RL1 RL2 VO1 VOFFSET M1 M2 ISS VO2 0 Voffset V − VTH  − ∆R L ∆ W L  VOFFSET = ∆VTH + GS −  R 2 WL   L  IC Lab .

2-STAGE MILLER OP AMP : SYSTEMATIC OFFSET VOLTAGE VDD VBP M5 M7 Vout=0V M2 M1 + M4 M 3 VDS3 VSS + VGS6 - M6 VDS3 = VDS4 = VGS4 = VTHn + VGS6 = VTHn + I 2I 4 = VTHn + 5 β4 β4 2I6 2I7 = VTHn + β6 β6 β I I ∴ 6 = 7 = 7 β4 I5 2 I 4 IC Lab .

MOSFET NOISE MODEL l 1-f Noise V1 f 2 (f ) = K 1 ⋅ CoxWL f 2 2 1 ⋅ g m ⇔ Vthrml 2 (f ) = 4kT ⋅ ⋅ 3 3 gm l Thermal Noise Ithrml 2 (f ) = 4kT ⋅ l MOSFET Noise Model Vthrml 2 (f) Ithrml 2 (f) V1/f 2 (f) V1/f 2 (f) IC Lab .

12 M2 M1 M5 Vn.eq 2 (f ) = 2 ( )  K nµ n L12  1 ⋅ ⋅ 1 + 2 f  Cox WL  K pµ p L 3  2K p  ⋅ 1 + 2µpCox (W L )1I1   4 µ n (W L )3   µ p (W L )1   IC Lab Vthrml2 (f ) = 4kT ⋅ .62 M4 M3 M6 g  Vn.2-STAGE MILLER OP AMP : INPUT-REFERRED NOISE VDD Vn.12 + Vn.eq2 M2 M1 Vout M7 VBP M5 VDD M7 M6 M4 Vn.42 VSS VSS M3 Vn.32 + Vn.72 Vn.eq 2 = Vn.22 +  m1  Vn.42 g   m3  V1/f .52 VBP Vn.22 Vout Vn.32 Vn.

+ vout - vcm + v+ Vout = Vcm A 1 + Ad − c 2 Ac ≅ Ac 1 = A d CMRR IC Lab .+ v- + vcm .OP AMP : CMRR  V + + V−  A in  + − Vout = A d ⋅ Vin − Vin + A c ⋅  in ⇒ CMRR ≡ d   2 Ac   l Definition ( ) l Modeling & Simulation vout v+ vcm + v+ + A d(v+ -v-) A c(v++v-)/2 vcm .

PSRR − ≡ d + Ap A− p ( ) l Modeling & Simulation vout ∆VDD VDD + + v+ v+ vout v+ v+ + A d(v+ -v-) A p+ ∆V DD A+ Vout 1 p ≅ = ∆VDD A d PSRR + IC Lab .OP AMP : PSRR l Definition + − Vout = A d ⋅ Vin − Vin + A + ⋅ ∆VDD + A − ⋅ ∆VSS p p A A ⇒ PSRR + ≡ d .

2-STAGE MILLER OP AMP : PSRR VDD M5 VDD VBB M7 M7 ro7 vin - M2 M1 vin + CC vout vout 1/g m6 M4 M3 M6 M6 VSS VSS IC Lab .

785 × 10 −3 [A/V] è SR = I5 CC ⇒ I5 = SR ⋅ CC = 125 × 10 −6 [A] è g m1 = 2β1I1 = β1I5 = µpCox (W L )1I5 ⇒ (W L )1 = 140.5V VIN=0.0 [pF] è ω0 ≅ g m1 CC ⇒ gm1 ≅ ω0 ⋅ CC = 0.5VRMS CL=10pF è CC = (1 2 ) ⋅ CL = 5.85 è g m6 = [tan(90° − Φ M )]−1 ⋅ (CL CC ) ⋅ g m1 = 2.5 ≥90 ±2.2-STAGE MILLER OP AMP : NUMERICAL DESIGN DC Gain Av(0) [dB] Unity-Gain Frequency f0 [MHz] Phase Margin [ ° ] Slew Rate [V/µsec] Power Dissipation [mW] SNR @ 1kHz [dB] ≥66 25 60 25 ≤2.719 × 10 −3 [A/V] è Power = (I5 + I7 ) ⋅ (VDD − VSS ) ⇒ I7 = 375 × 10 −6 [A] IC Lab .

67 × 103 [ Ω ] ro3 = [g o3 ]−1 = [λ nI3 ]−1 = [λ n (I5 2)]−1 = 320 .4 [dB] è SNR = 10 log  2  Vthermal.33 × 103 [ Ω] ro7 = [g o7 ]−1 = λ pI7 −1 = 17 .43 (W L )6 è (W L ) 3 I = 6 = I3 I7 = 6 ⇒ (W L )3 = 41 .78 × 10 3 [Ω ] 2 è Vthermal.eq  IC Lab .1 [dB] ro1 = [g o1]−1 = λ pI1 −1 = λp (I5 2) −1 = 106 .00 × 10 3 [Ω ] ro6 = [g o6 ]−1 = [λ nI6 ]−1 = [λnI7 ]−1 = 53 .2-STAGE MILLER OP AMP : NUMERICAL DESIGN (cont’d) è g m6 = 2β6I6 = 2β6 I7 = µ n Cox (W L )6 I7 ⇒ (W L )6 = 246 .07 I1 è A v (0 ) = [g m1(ro1 ro3 )] ⋅ [g m6 (ro6 ro7 )] = 2276 → 67.eq = 4kT ⋅ [ ] [ ] [ ]  ⋅ 1 + 2µ pCox (W L )1I1   4 µ n (W L )3   ⋅ ∆f = 183 × 10 −15 [V 2 ] µ p (W L )1   2   V IN.rms   = 107 .

FOLDED-CASCODE OP AMP : CONSTRUCTION VDD M7 M5 M8 M6 vout M3 VBN2 M1 M2 M4 M3 vinvin+ M1 M2 vinM5 VBN1 M0 VSS VBN1 M0 VSS M7 M6 M8 VBP2 M9 VDD M10 VBP1 M4 vout CL vin+ l Single Stage Amplifier l Compensation w/ Load Capacitance è Suitable for SC Circuits IC Lab .

FOLDED-CASCODE OP AMP : AC CHARACTERISTICS l Voltage Gain  g  g m4 A v (0 ) = g m1 ⋅ rout = g m1 ⋅  m6  g o6g o8 g o4 (g o2 + g o10 )  A v (s ) = A v (0 ) A v (0 ) = 1 − s p I 1 + s (routC L ) g l Frequency Response m1 l Unity-Gain Frequency ω0 = A v (0 ) ⋅ p II = C L |A v(s)| [dB] |A v(0)| p II = |p II| |p I| ω0 1 rint ernal Cgs ω ω → g m1 1 >> C gs rout C gs 0 -90o phase margin -180o <A v(s) IC Lab .

256 × 10 −3 [A/V] è SR = I0 CL ⇒ I 0 = SR ⋅ CL = 100 × 10 −6 [A] è g m1 = 2β1I1 = β1I0 = µnCox (W L )1I0 ⇒ (W L )1 = 197.5V CL=10pF è ω0 ≅ g m1 CL ⇒ g m1 ≅ ω0 ⋅ CL = 1.0 ~ +1.FOLDED-CASCODE OP AMP : NUMERICAL DESIGN DC Gain Av(0) [dB] Unity-Gain Frequency f0 [MHz] Phase Margin [ ° ] Slew Rate [V/µsec] Power Dissipation [mW] Output Range [V] ≥60 20 60 10 ≤2.19 è Power = (I9 + I10 ) ⋅ (VDD − VSS) = 2I9 ⋅ (VDD − VSS) ⇒ I9 = 250 × 10 −6 [A] è I1 = I0 2 = 50 × 10 −6 [A] è I2 = I0 2 = 50 × 10 −6 [A] I3 = I5 = I7 = I9 − I1 = 200 × 10 −6 [A] I4 = I6 = I8 = I10 − I2 = 200 × 10 −6 [A] IC Lab .0 ±2.5 -1.

(W L )3 −4 = 126 .M9-10 è M3-4 è M5-8 I3-4 = (β3-4 2 )VSDp(sat)2 ⇒ β3−4 = 4 .VSS ⇒ VDSn(sat) = 0.68 VTHp + 2VSDp(sat) = VDD .0 ⇒ VSDp(sat) = 0 .5 × 10 −6 [A/V] è pint ernal = g m + ∑ g o CGS = min g m4 + g o4 + g o10 + g o2 ⇒f internal= 1.425 [V] I5-8 = (β5-8 2 )(VGSn − VTHn )2 = (β5-8 2)VDSn(sat)2 ⇒ β5−8 = 2.1.98 (W L )9−10 = 158 .556 × 10 −3 [A/V].215 × 10 −3 [A/V] β5−8 = µnCox (W L )5−8 ⇒ (W L )5−8 = 27.FOLDED-CASCODE OP AMP : NUMERICAL DESIGN (cont’d) è M5-8 è M5-8 è M5-8 VTHn + 2VDSn(sat) = -1.333 × 10 −3 [A/V] g o2 = λpI2 = 7.941 × 10 −3 [A/V] g m4 = 2β4I4 = 1 .444 × 10 −3 [A/V].4 [GHz] >> f0 CGS4 IC Lab .73 I9-10 = (β9-10 2)VSDp(sat)2 ⇒ β9−10 = 5 .  g  g m4 A v (0 ) = g m1 ⋅ rout = g m1 ⋅  m6 è  = 1122 → 61 [dB] g o6g o8 g o4 (g o2 + g o10 )  g m6 = 2β6I6 = 0 .0 .300 [V] è M3-4.5 × 10 −6 [A/V] g o6 = g o8 = λ nI6 = 10 × 10 −6 [A/V] g o4 = λ pI4 = 30 × 10 −6 [A/V] g o10 = λpI10 = 37.

FOLDED-CASCODE OP AMP : FULLY-DIFFERENTIAL VDD M9 VBP2 M10 l Voltage Gain + − Vout − Vout Av ≡ + − Vin − Vin M3 VBP1 M4 vin+ voutCL VBN1 M1 M2 vinvout+ l Common-Mode Noise Can Be CL M0 VSS Removed l Common-Mode Feedback (CMFB) Circuit Needed M5 VBN1 M6 M7 VCMFB VSS M8 IC Lab .

FOLDED-CASCODE OP AMP : FULLY-DIFFERENTIAL (IMPROVED) VDD M10 M9 + - VBP2 M3 M4 + - VBP1 VBP1 vin+ voutCL VBN1 VBN1 M1 M2 vinvout+ M0 VSS CL VBN1 + - M5 M6 + - M7 VCMFB VSS M8  A ⋅ g m6  A ⋅ g m4 A v (0 ) = g m1 ⋅ rout = g m1 ⋅    g o6g o8 g o4 (g o2 + g o10 ) IC Lab .

CMFB EXAMPLE (CONTINUOUS-TIME) l Using Averaging Resistors VDD vout+ M1 RP M2 RM VCM CP VBN M3 CM M4 VSS M7 M8 VCNTL M8 M7 VSS M9 M5 M6 VREF vout+ M1 M2 VREF M5 M4 voutvoutM9 VBP IB l Using 2 Differential Pairs VDD M3 VBP M6 IB VCNTL IC Lab .

CMFB EXAMPLE (DISCRETE-TIME) vout + φ1 CS VB φ1 φ2 VCNTL φ2 CC CC φ2 vout φ2 φ1 CS φ1 VB l For Φ1 l For Φ2 ∑ Q1 = 2 ⋅ CS ⋅ (− VB ) + − ∑ Q2 = (CS + C C ) Vout − VCNTL + (CS + C C ) Vout − VCNTL + − Vout + Vout CS ∴ VCNTL = + VB 2 CS + C C ( ) ( ) IC Lab .

RAIL-TO-RAIL INPUT STAGE : SINGLE DIFFERENTIAL PAIR operating input range vinM2 M1 vin + VGS1 vin V BN M3 V SS VDS3(sat) V SS V DD VBP M6 V DD VSD6(sat) VSG4 M5 M4 vin+ operating input range l Single-Polarity Differential Pair Limits Input Range l nMOS Differential Pair l pMOS Differential Pair VSS + VDS(sat ) + VGS ≤ VINPUT ≤ VDD VSS ≤ VINPUT ≤ VDD − VDS(sat ) + VGS ( ) IC Lab .

RAIL-TO-RAIL INPUT STAGE : DOUBLE DIFFERENTIAL PAIR VDD M9 vin + M1 M2 vin M7 VBN0 M3 V SS V DD VBP0 M6 M 11 vin + M4 M5 vin M 13 M14 VBN1 M12 CL voutvout + CL V BP1 M8 V BP2 l For Input ~ VSS M10 è nMOS off & pMOS on è gmIN = gmp l For Input ~ VDD è nMOS on & pMOS off è gmIN = gmn l For Input ~ 0 è nMOS on & pMOS of VCMFB VSS è gmIN = gmp +gmn IC Lab .

RAIL-TO-RAIL INPUT STAGE : CONSTANT Gm APPROACH VDD M4 M5 I SS M3 VREFN vin+ M1N M2N vin+ vin - M 1P M2P vinM6 VREFP I SS M8 VSS M7 l For nMOS Differential Pair Off : gmp è 2gmp by Providing I SSP+3I SSP l For pMOS Differential Pair Off : gmn è 2gmn by Providing I SSN+3I SSN l For Both Differential Pair On : No Additional Current IC Lab .

CLASS-AB OUTPUT STAGE : CD VDD I REF M1 M3 vin IOUT M4 M2 I REF VSS I2 IQ -4IQ 0 I OUT=I 1-I 2 4IQ IQ I1 vout 4IQ 4IQ I2 I2 I1 I1 l Small Output Impedance Preferable l Output Range Limited By 2VGS+VDS(sat) Each l Quiescent Point I1 + I 2 = 2 β1 IREF = 2 I Q β3 l Distortion Possible Due to Full-Off of M1 or M2 IC Lab .

where =  α β3  α   2 2 1 1 + β5 β7 l Negligible Distortion Due to  β β  Imin =  1 − 2 1  ⋅ IB  α β3    IC Lab .CLASS-AB OUTPUT STAGE : CS VDD IB 2IB M5 M7 M1 vin1 M4 M3 vin2 M2 M8 M6 2IB VSS IB I2 I1 vout IQ I min -4IQ 0 IOUT=I 1-I 2 4IQ IQ I min I2 I2 I1 I1 l Output Range Limited By VDS(sat) Each l Quiescent Point  β β  1 IQ =  1 − 1  ⋅ IB .

CLASS-AB OUTPUT STAGE : CS (EXACT CONTROL) VDD I B1 vin1 IB1 I B1 2IB2 2IB2 M3 M1 I1 vout vin2 M10 M9 2IB1 VSS M6 M8 M7 M5 M4 M11 M2 I2 M12 l Exact Control By Feedback Amplifier l Quiescent Point l Minimum Current IQ = 2IB 2 − β6 IB1 β12 β  Imin = 2I B2 − 8 1 + β12   ( β  2 − 1 12  ⋅ IB1 β9   ) 2 IC Lab .

1709-1717. IC Lab . Path (A3-A2-A1) to Achieve Pole-Zero Cancellation when g m 3 Cm 2 = g m 4 C m1 1 IEEE JSSC pp. Path (A4-A1) & High-Freq. MULTI-PATH) p3 V DD p2 p1 |A v (s)| [dB] |A v (0)| Cm2 gm4 gm2 vin gm3 Cm1 gm1 0 p'2 p'3 vout ω0dB p'1 ω V SS A4 A3 A2 A1 l Multi-Stage For Large Gain w/o Using Cascode Stage l Multi-Loop & Multi-Path Compensation l Combined High-Freq. 1992.VARIOUS OP AMP EXAMPLE (MULTI-LOOP.

1993.VARIOUS OP AMP EXAMPLE (REPLICA AMP) l w/o Replica Amp ZF ZS vx gm + main amp Ro vin + gm Vout 1 = −β Vin 1 + (1 + β) A o vout ε1 = (1 + β) A o 1 + (1 + β) A o l w/ Replica Amp ZF ZS vy + gm Ro v' out 1+ β Vout 1 + β + Ao = −β Vin 1 + (1 + β ) A o 1+ replica amp ε2 = (1 + β)2 A o (1 + β + A o ) 1 + (1 + β) A o ≅ ε1 A o (1 + β ) 1 IEEE ISSCC pp. 116-117. IC Lab .

936-942.VARIOUS OP AMP EXAMPLE (SWITCHED) VDD MCP φ M8 M5 M7 vin- M2 M1 vin+ CC RC vout CL M6 IB M4 M3 MCN φ VSS l Replace the Switch on Signal Path l Power Saving When Not Used 1 IEEE JSSC pp. 1994. IC Lab .

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