Code No: 54111/MT M.Tech.

– I Semester Supplementary Examinations, September, 2008 DIGITAL SYSTEM DESIGN (Common to Digital Systems & Computer Electronics/ Digital Electronics & Communication Systems/ VLSI System Design) Time: 3hours Answer any FIVE questions All questions carry equal marks ---


Max. Marks:60

1.a) Draw the ASM chart to detect the overlapping sequence 1010 from the incoming bit stream and output 1 for each detection. Ex: x: 10101010110- - - - - - Z: 00010101000- - - - - - Implement the controller circuit using MUX method. b) What is the difference between melay and moore state machine. 2.a) b) Draw the general structure of an FPGA and explain how a logicfunction can be realized on FPGA with a simple example. Design and implement a BCD counter on PLD (PLA). Draw the complete fuse-map circuit.

3.a) Using the path –sensitization method and Boolean difference method find the test vectors for SAO fault on input line 1 and SA1 Fault on the internal line 2 of the circuit shown below

b) Draw the table giving the set of all possible single struck faults and the faulty and fault-free responses and also construct the fault cover table for the circuit shown in below.


Code No: 54111/MT 4.a)


What is the significance of Kohavi Algorithm? Explain how it detects multiple faults in a two-level networks with a simple example. b) Discuss the different types of faults in digital circuits (fault models).

5.a) Find a preset distinguishing experiment that determine the initial state of the machine shown in table given below. Given that it cannot be initially in state E. b) Can you identify the initial state when the initial uncertainity is (ABCDE)? Table Ps Ns, z x=0 , x=1 A B,1 A,1 B E,0 A,1 C A,0 E,1 D C,1 D,1 E E,0 D,1 c) Classify the fault detection experiments for the sequential circuits. 6.a) Find minimized PLA of the following multiple output Boolean functions on a map. Calculate the area and cross point densities of the un -minimized and minimized PLAS. f1 = Σ(2, 4,5, 6, 7,10,14,15) f 2 = Σ(4,5, 7,11,15) Briefly describe about PLA folding.


7.a) Explain the different types of fault models and fault types in a PLA. b) Plot the following PLA on the map. Identify the undetectable faults. Determine a minimal test set for an detectable faults.

x1 x2 x3 x4
0 2 21 2 1 12 0 1 21 8.a)

Z1 Z 2
1 0 1 1 0 1


The output Z of a fundamental-mode , two input sequential circuit is to change from 0 to 1 only when x2 changes from 0 to 1 while x1 =1. The output is to change from 1 to 0 only when x1 changes from 1 to 0 while x2 =1. (i) Find a minimum- row reduced flow table, the output should be fast and flicker-free. (ii) Show a valid assignment and write a set of (static) hazardfree exitation and output equations. Define the races and cycles in sequential circuits. &_&_&_&

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