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Code No: 54215/MT

NR
M.Tech. – II Semester Regular Examinations, September, 2008

CMOS ANALOG & MIXED SIGNAL DESIGN


(Digital Systems & Computer Electronics)

Time: 3hours Max. Marks:60

Answer any FIVE questions


All questions carry equal marks

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1.a) Using small signal analysis, Derive an expression for the output
resistance of the triple cascode current source.
b) Using the Wilson current mirror shown in figure.1 and the CN 20
process, design a mirror in which I0=150 µA with IREF = 50 µA for
VDD=5V,VSS=0V.

2.a) Explain the behavior of the MOSFET-only voltage divider.


b) Design a MOSFET-MOSFET voltage divider shown in figure-2 so
that the reference voltage, Vref is 2V and the current through each
MOSFET is 10 µA.

Contd…2.,
Code No: 54215/MT ::2::

3.a) Estimate the small signal voltage gain of the common source
amplifier with current source load. Assume that both M1 and M2
are biased in the saturation region.
b) The amplifier shown in figure-3 is during a 10 pF load capacitor.
What is the maximum rate the load capacitance can be charged.
Is there a slew rate limitation for discharging the capacitor?

4. Explain the properties of negative feed back on amplifier design.

Contd…3.,
Code No: 54215/MT ::3::

5.a) For the differential amplifier shown in figure-4. Determine the


drain current of M1 as a function of the input voltage, Vi1-Vi2.

b) Explain the technique to extend the allowable input swing of a


differential amplifier.

6.a) For OTA, derive the expressions for voltage gain output current
and transconductance.
b) Explain the purpose of common mode feed back circuit in
differential input-output op-Amp’s.

7.a) Can the self biased comparator be used as a wide-swing op-Amp?


If so explain how would the op-Amp be compensated.
b) Explain dynamic comparator & dynamic biasing of current mirror
circuits.

8.a) Explain the methods used to prevent aliasing and the advantages
and disadvantages of each.
b) Design a 3-bitflash ADC with its quantization error centered about
zero LSB’s. Determine the worst case DNL and INL if resistor
matching is known to be 5%. Assume that Vref = 5V.

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