1
CHAPTER 1
INTEGRATEDCIRCUIT DEVICES AND MODELLING
1.1 1.2 1.3 1.4 1.5 1.6 Semiconductors and pn Junctions MOS Transistors 16 Advanced MOS Modelling 39 BipolarJunction Transistors 42 Device Model Summary 56 SPICEModelling Parameters 61 1.7 Appendix 65 1.8 References 78 1.9 Problems 78
CHAPTER 2
PROCESSING AND LAYOUT
82 2.1 CMOS Processing 95 2.2 Bipolar Processing 2.3 CMOS Layout and Design Rules ..l 2.4 Analog Layout Considerations 118 2.5 LatchUp 121 2.6 References 121 2.7 Problems
82
96 105
CHAPTER 3
BASIC CURRENT MIRRORS AND SINGLESTAGE AMPLIFIERS
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Simple CMOS Current Mirror 125 CommonSource Amplifier 128 SourceFollower or CommonDrain Amplifier 129 CommonGate Amplifier 132 SourceDegenerated Current Mirrors 135 HighOutputImpedance Current Mirrors 137 Cascade Gain Stage 140 MOS Differential Pair and Gain Stage 142 Bipolar Current Mirrors 146 Bipolar Gain Stages \49
125
Contents
xi
3.11 3.12 3.13 3.14
Frequency Response 154 SPICE Simulation Examples References 176 Problems 176
169
JCHAPTER4
NOISE ANALYSIS AND MODEUING
4.1 4.2 4.3 4.4 4.5 4.6 TimeDomain Analysis 181 FrequencyDomain Analysis 186 Noise Models for Circuit Elements Noise Analysis Examples 204 References 216 Problems 217
181
196
CHAPTER 5
BASIC OPAMP DESIGN AND COMPENSATION
5.1 5.2 5.3 5.4 5.5 TwoStage CMOS Opamp 221 Feedback and Opamp Compensation SPICE Simulation Examples 251 References 252 Problems 253 232
221
.J CHAPTER 6
ADVANCED CURRENT MIRRORS AND OPAMPS
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Advanced Current Mirrors 256 FoldedCascode Opamp 266 CurrentMirror Opamp 273 Linear Settling Time Revisited 278 Fully Differential Opamps 280 CommonMode Feedback Circuits 287 CurrentFeedback Opamps 291 SPICE Simulation Examples 295 References 299 Problems 300
256
v
CHAPTER7
COMPARATORS
7.1 7.2 7.3 7.4 7.5 7.6 7.7 Using an Opamp for a Comparator 304 ChargeInjection Errors 308 Latched Comparators 317 Examples of CMOS and BiCMOS Comparators Examples of Bipolar Comparators 328 References 330 Problems 331
304
321
xii
Contents
CHAPTER 8
SAMPLE AND HOLDS, VOLTAGE REFERENCES, AND TRANSLINEAR CIRCUITS
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 Performance of SampleandHold Circuits 334 MOS SampleandHold Basics 336 Examples of CMOS SIH Circuits 343 Bipolar and BiCMOS Sample and Holds 349 Bandgap Voltage Reference Basics 353 Circuits for Bandgap References 357 Translinear Gain Cell 364 Translinear Multiplier 366 References 368 Problems 370
334
CHAPTER 9
DISCRETETIME SIGNALS
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Overview of Some Signal Spectra 373 Laplace Transforms of DiscreteTime Signals zTransform 377 Downsampling and Upsampling 379 DiscreteTime Filters 382 SampleandHold Response 389 References 391 Problems 391 374
373
CHAPTER 10 SWITCHEDCAPACITOR CIRCUITS
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 Basic Building Blocks 394 Basic Operation and Analysis :398 FirstOrder Filters 409 Biquad Filters 415 Charge Injection 423 SwitchedCapacitor Gain Circuits 427 Correlated DoubleSampling Techniques Other SwitchedCapacitor Circuits 434 References 441 Problems 443
394
433
CHAPTER 11
DATA CONVERTER FUNDAMENTALS
Il.l
445
445 Ideal 01A Converter 447 11.2 Ideal AID Converter 448 11.3 Quantization Noise 452 11.4 Signed Codes
Contents
xiii
11.5 11.6 11.7
Performance Limitations References 461 Problems 461
454
CHAPTER 12 NYQUISTRATE O/A CONVERTERS
12.1 12.2 12.3 12.4 12.5 12.6 DecoderBased Converters 463 BinaryScaled Converters 469 ThermometerCode Converters 475 Hybrid Converters 481 References 484 Problems 484
463
CHAPTER 13 NYQUISTRATE A/O CONVERTERS
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 Integrating Converters 487 SuccessiveApproximation Converters 492 Algorithmic (or Cyclic) NO Converter 504 Flash (or Parallel) Converters 507 TwoStep NO Converters 513 Interpolating NO Converters 516 Folding NO Converters 519 Pipelined NO Converters 523 TimeInterleaved NO Converters  526 References 527 Problems 528
487
CHAPTER 14 OVERSAMPUNG CONVERTERS
531 14.1 Oversampling without Noise Shaping 14.2 Oversampling with Noise Shaping 538 14.3 System Architectures 547 14.4 Digital Decimation Filters 551 14.5 HigherOrder Modulators 555 14.6 Bandpass Oversampling Converters 557 14.7 Practical Considerations 559 14.8 MultiBit Oversampling Converters 565 14.9 ThirdOrder NO Design Example 568 14.10 References 571 14.11 Problems 572
531
CHAPTER 15 CONTINUOUSTIME FILTERS
15.1 15.2 Introduction to GmC Filters 575 Bipolar Transconductors 584
574
xiv
Contents
15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10
~
CMOS Transconductors Using Triode Transistors CMOS Transconductors Using Active Transistors BiCMOS Transconductors 616 MOSFETC Filters 620 Tuning Circuitry 626 Dynamic Range Performance 635 References 643 Problems 645
597 607
CHAPTER 16 PHASELOCKED LOOPS
16.1 16.2 16.3 16.4 16.5 16.6 16.7 Basic Loop Architecture 648 PLLs with ChargePump Phase Comparators VoltageControlled Oscillators 670 Computer Simulation of PLLs 680 Appendix 689 References 692 Problems 693 663
648
INDEX
696
CHAPTER
IntegratedCircuit Devices and Modelling
In this chapter, the operation and modelling of semiconductor devices are described. Although it is possible to do simple integratedcircuit design with a basic knowledge of semiconductor device modelling, for highspeed stateoftheart design, an indepth understanding of the secondorder effects of device operation and their modelling is considered critical. It is assumed that most readers have been introduced to transistors and their basic modelling in a previous course. Thus, fundamental semiconductor concepts are only briefly reviewed. Section 1.1 describes pn junctions (or diodes). This section is important in understanding the parasitic capacitances in many device models, such as junction capacitances. Section 1.2 covers MOS transistors and modelling. It should be noted that this section relies to some degree on the material previously presented in Section 1.1, in which depletion capacitance is covered. Section 1.4 covers bipolarjunction transistors and modelling. A summary of device models and important equations is presented in Section 1.5. This summary is particularly useful for a reader who already has a good background in transistor modelling, in which case the summary can be used to follow the notation used throughout the remainder of this book. In addition, a brief description is given of the most important processrelated parameters used in SPICE modelling. Finally, this chapter concludes with an Appendix containing derivations of the more physically based device equations.
1.1
SEMICONDUCTORS AND pn JUNCTIONS
A semiconductor is a crystal lattice structure that can have free electrons (which are negative carriers) and/or free holes (which are an absence of electrons and are equivalent to positive carriers). The type of semiconductor typically used is silicon (commonly called sand). This material has a valence of four, implying that each atom has four free electrons to share with neighboring atoms when forming the covalent bonds of the crystal lattice. Intrinsic silicon (i.e., undoped silicon) is a very pure crystal structure having equal numbers of free electrons and holes. These free carriers are those electrons or holes that have gained enough energy due to thermal agitation to escape their bonds. 10 At room temperature, there are approximately 1.5 x 10 carriers of each type per crrr', 16 or equivalently 1.5 x 10 carriers/m '. The number of carriers approximately doubles
for every 11°C increase in temperature.
1
2
Chapter 1 • IntegratedCircuit Devices and Modelling
If one dopes silicon with a pentavalent impurity (i.e., atoms of an element having a valence of five, or equivalently five electrons in the outer shell, available when bonding with neighboring atoms), there will be almost one extra free electron for every impurity atom.' These free electrons can be used to conduct current. A pentavalent impurity is said to donate free electrons to the silicon crystal, and thus the impurity is known as a donor. Examples of donor elements are phosphorus, P, and arsenic, As. These impurities are also called ntype dopants since the free carriers resulting from their use have negative charge. When an ntype impurity is used, the total number of negative carriers or electrons is almost the same as the doping concentration, and is much greater than the number of free electrons in intrinsic silicon. In other words,
(Ll)
where n, denotes the freeelectron concentration in ntype material and ND is the doping concentration (with the subscript D denoting donor). On the other hand, the number of free holes in ndoped material will be much less than the number of holes in intrinsic silicon and can be shown [Sze, 1981] to be given by
n~
,
I
p, = N
(1.2)
D
Here, n, is the carrier concentration in intrinsic silicon. Similarly, if one dopes silicon with atoms having a valence of three, for example, boron (8), the concentration of positive carriers oJ holes will be approximately equal to the acceptor concentration, NA '
Pp
= NA
n,2
(1.3)
and the number of negative carriers in the ptype silicon, n p , is given by np = 
NA
(1,4)
EXAMPLE 1.1
Intrinsic silicon is doped with boron at a concentration of 1026 atoms/m'. At room temperature, what are the concentrations of holes and electrons in the resulting doped silicon? Assume that n, = 1.5 x 1O!6 carriersv m''
Solution
The hole concentration, Pp ' will approximately equal the doping concentration (pp 26 NA = 10 holes/m"). The electron concentration is found from (1.4) to be
I. In fact. there will be slightly fewer mobile carriers than the number of impurity atoms since some of the free electrons from the dopants have recombined with holes. However. since the number of holes of intrinsic silicon is much less than typical doping concentrations, this inaccuracy is small.
=
1.1
Semiconductors and pn Junctions
3
n
p
=
(1.5
X
10'·) 2
10'·
= 2.3 X
10· e lectrons/m'
( 1.5)
Such doped silicon is referred to as p type since it has many more free holes tha n free electrons.
Diodes
To realize a diode. or . equivalently. a pn junction. one pan of a semico nductor is doped n type. and a closely adjacent pan is doped p ype. as shown in Fig. 1.1. Here the diode. or junction. is formed between the p" region and the n region . It sho uld be noted that the superscripts indicate the relat ive dop ing levels. For example. the p" bulk region might have an impurity concentration of 5 x JO" carriers/nr', whereas the p" and n" regions wo uld be doped more heavily to a value aro und 1025 to J027 carriers/nr'. Also, note that the metal contacts to the diode (in this case, alumi num) are connected to a heavi ly doped region as opposed to a lightly doped regio n: otherwise a Scho ttky diode wou ld occur. (Sc hottky diodes are discu ssed on page 15.) Thus, in order not 10 make a Schottky diode. the connection to the n region is actually made via the n" region. In the p' side. a large number of free positive carriers are avai labl~~ w hereas in the n side, many free nega tive carriers are available. The holes in the p" side will tend to disperse or diffuse into the n side, whereas the Tree electrons in the n side will tend to diffuse to the p" side. Th is process is very simi lar 10 two gases rando mly diffusing toget her. This diffusion lowers the co ncentration of free car riers in the regio n betwee n the two sides. As the two types of carriers diffuse toget her, they recom bine. Eve ry electron that diffuses from the n side to the p side leaves behind a bound posi tive charge close to the trans ition regio n. Sim ilarly, every hole that diffuses from the p side leaves behind a bound electron ncar the transition regio n. The end result is shown in Fig. 1.2. This diffusion of free carriers creates a de pletion region at the junctio n of the two sides whe re no free carriers exist, and whic h has a net negati ve charge on the p" side and a net positive charge on the n side . The total amo unt of exposed or bound
Anode Si0 2 An od e Ca thode
n+
n
.. ........ . . . .. . . . .
pn junction
Cathode
Bulk
0
Fig. 1.1
A cross section of
pn diode .
4
Chapter 1 • IntegratedCircuit Devices and Modelling Electric field
+++ +++ +++ ++ +++
Immobile
negative
n
Fig. 1.2 A simplified model of a diode.
~
Depletion
region
charge
Immobile positive charge
Note that a depletion region exists ot the junction due to diffusion and extends far
ther into the mare lightly doped side.
charge on the two sides of the junction must be equal for charge neutrality. This requirement causes the depletion region to extend farther into the more lightly doped n side than into the p" side. As these bound charges are exposed, an electric field develops going from the n side to the p side. This electric field is often called the builtin potential of the junction. It opposes the diffusion of free carriers until there is no net movement of charge under opencircuit and steadystate conditions. The builtin voltage of an opencircuit pn junction is given by Sze [1981] as
<\>0 =
where
VTln[N~~ilJ
V
T
(1.6)
= kT q
(1.7)
with T being the temperature in degrees Kelvin ('" 300 "K at room temperature), k 23 I being Boltzmann's constant (1.38 x 10 JK ), and q being the charge of an elec19 tron (1.602 x 10 C). At room temperature, VT is approximately 26 mY.
EXAMPLE 1.2
22 25 3 A pn junction has N A = 10 holes/m and No = 10 etectrons/m" . What is 16 the builtinjunction potential? Assume that n, = 1.5 x 10 carriers/rn".
Solution
Using (1.6), we obtain
22 1025 x 10 <\>0 = 0.026 x In = 0.88 Y [ (1.5 x 10'6)'
J
(1.8)
1.1
Semiconductors and pn Junctions
5
This is a typical value for the builtin potential of a junction with one side 0.9 V for the heavily doped. As an approximation, we will normally use <1>0 builtin potential of a junction having one side heavily doped.
=
ReverseBiased Diodes
A silicon diode having an anodetocathode (i.e., p side to n side) voltage of 0.4 V or less will not be conducting appreciable current. In this case, it is said to be reverse biased. If a diode is reverse biased, current flow is primarily due to thermally generated carriers in the depletion region, and it is extremely small. Although this reversebiased current is only weakly dependent on the applied voltage, the reversebiased current is directly proportional to the area of the diode junction. However, an effect that should not be ignored, particularly at high frequencies, is the junction capacitance of a diode. In reversebiased diodes, this junction capacitance is due to varying charge storage in the depletion regions and is modelled as a depletion capacitance. To determine the depletion capacitance, we first state the relationship between the depletion widths and the applied reverse voltage, VR [Sze, 1981].
x, = [2Ks o(<I>o + V
E
R )
NA
]112
q
xp 
No(N A + No)
( 1.9)
(1.10)
12
Here, Eo is the permittivity of free space (equal to 8.854 x 10 F/m), VR is the reversebias voltage of the diode, and Ks is the relative permittivity of silicon (equal to 11.8). It should be noted that these equations assume that the doping changes abruptly from the n to the p side. From the above equations, we see that if one side of the junction is more heavily doped than the other, the depletion region will extend mostly on the lightly doped side. For example, if NA » No (i.e., if the p region is more heavily doped), we can approximate (1.9) and (1.10) as (1.11) Indeed, for this case
x,
xp

NA No
(1.12)
This special case is called a singlesided diode.
6
Chapter 1 • integratedCircuit Devices and Modelling
EXAMPLE 1.3
For a pn junction having NA = 10 holes/m' and No = 10 electrons/m' , what are the depletionlayer depths for a 5V reversebias voltage?
25 22
Solution
Since NA » No and we already have found in Example 1.2 that cPo = 0.9 V, we can use (l.ll) to find
x, = [2
X
11.8 x 8.854 x 10 x 5.9] 1/2 = 0.88 11 m 1.6 x 10 19 X 1022
= 0.88 nm
12
(1.13)
(1.14)
Note that the depletion width in the lightly doped n region is 1,000 times greater than that in the more heavily doped p region.
The charge stored in the depletion region, per unit crosssectional area, is found by multiplying the depletionregion width by the concentration of the immobile charge (which is approximately equal to q times the impurity doping density). For example, on the n side, we find the charge in the depletion region to be given by multiplying (1.9) by qN o, resulting in N N ]112 Q+= 2qK sE o(cP O+V R ) A 0 [ NA + No (1.15)
This amount of charge must also equal Q on the p side since there is charge equality. In the case of a singlesided diode when NA » ND, we have (1.16) Note that this result is independent of the impurity concentration on the heavily doped side. Thus, we see from the above relation that the charge stored in the depletion region is dependent on the applied reversebias voltage. It is this chargevoltage relationship that is modelled by a nonlinear depletion capacitance. For small changes in the reversebiased junction voltage, about a bias voltage, we can find an equivalent smallsignal capacitance, C j , by differentiating (1.15) with respect to V R' Such a differentiation results in (1.17)
1.1
Semiconductors and pn Junctions
7
where C jO is the depletion capacitance per unit area at V R = 0 and is given by
CjO =
qK,Eo NAN o 2<1>0 N A+ No
(1.18)
In the case of a onesided diode with NA » No, we have
C.
1
= [ qK,EoN o ]112 = =C=,i=O=
2(<1>0 + VR)
HR
<1>0
(1.19)
1+
where now
CiO =
(1.20)
It should be noted that many of the junctions encountered in integrated circuits are onesided junctions with the lightly doped side being the substrate or sometimes what is called the well. The more heavily doped side is often used to form a contact to interconnecting metal. From (1.20), we see that, for these onesided junctions, the depletion capacitance is approximately independent of the doping concentration on the heavily doped side, and is proportional to the square root of the doping concentration of the more lightly doped side. Thus, smaller depletion capacitances are obtained for more lightly doped substratesa strong incen~ve to strive for lightly doped substrates.
Finally, note that by combining (1.15) and (1.18), we can express the equation for the immobile charge on either side of a reversebiased junction as (1.21 ) As seen in Example 1.6, this equation is useful when one is approximating the largesignal charging (or discharging) time for a reversebiased diode.
EXAMPLE 1.4
For a pn junction having N A = 10 holes/m' and No = 10 electrons/m" , what is the total zerobias depletion capacitance for a diode of area 10 urn x 10 urn ? What is its depletion capacitance for a 3V reversebias voltage?
25 22
Solution
Making use of (1.20), we have 1.6 x 10
C jO =
19
x 11.8 x 8.854 x 10
2 xO.9
12 X
1022
= 304.7 /IF/m
2
(1.22)
8
Chapter 1 • IntegratedCircuit Devices and Modelling
Since the diode area is 100 x 10 12 rrr', the total zerobias depletion capacitance is C T. jO = 100 X 10 12 x 304.7
X
106 = 30.5 IF
( 1.23)
At a 3V reversebias voltage, we have from (1.19) C T. j
=
30.5 fF
= 14.7 IF
(1.24)
JI+(039)
As expected, we see a decrease in junction capacitance as the width of the depletion region is increased.
Graded Junctions
All of the above equations assumed an abrupt junction where the doping concentration changes quickly from p to n over a small distance. Although this is a good approximation for many integrated circuits, it is not always true. For example, the collectortobase junction of a bipolar transistor is most commonly realized as a graded junction. In the case of graded junctions, the exponent 1/2 in Eq. (1.15) is inaccurate, and a better value to use is an exponent closer to unity, perhaps 0.6 to 0.7. Thus, for graded junctions, (1.15) is typically written as (I.25) where m is a constant typically around 1/3. Differentiating (1.25) to find the depletion capacitance, we have (1.26) This depletion capacitance can also be written as
Co
(1.27)
where
(1.28)
From (1.27), we see that a graded junction results in a depletion capacitance that is less dependent on V R than the equivalent capacitance in an abrupt junction. In other word" since m is less than 0.5, the depletion capacitance for a graded junction is
1.1
Semiconductors and pn Junctions
9
more linear than that for an abrupt junction. Correspondingly, increasing the reversebias voltage for a graded junction is not as effective in reducing the depletion capacitance as it is for an abrupt junction. Finally, as in the case of an abrupt junction, the depletion charge on either side of the junction can also be written as
VR Q = _10_<1> I + I 
C
I  m
m 0[
<1>0
J
(1.29)
EXAMPLE 1.5
Repeat Example 1.4 for a graded junction with m = 0.4.
Solution
Noting once again that N A » No, we approximate (1.28) as
G,O =
resulting in
(1.30)
GjO = 81.5
~F/m
2
(1.31)
which, when multiplied by the diode's area of 10 urn x 10 urn. results in G r .io = 8.1 fF For a 3V reversebias voltage, we have CT_j (1.32)
= (I + 3/0.9)04 = 4.5 fF
8. ifF
(1.33)
LargeSignal Junction Capacitance
The equations for the junction capacitance given above are only valid for small changes in the reversebias voltage. This limitation is due to the fact that C j depends on the size of the reversebias voltage instead of being a constant. As a result, it is extremely difficult and time consuming to accurately take this nonlinear capacitance into account when calculating the time to charge or discharge a junction over a large voltage change. A commonly used approximation when analyzing the transient response for large voltage changes is to use an average size for the junction capacitance by calculating the junction capacitance at the two extremes of the reversebias voltage. Unfortunately, a problem with this approach is that when the diode is forward biased with V R '" <1>0' Eq. (1.17) "blows up" (i.e., is equal to infinity). To circumvent this
calculate the average capacitance according to C jav = Q(V. one can use C _ C jO [av  2 (1.o<l>o I + <1>0 Therefore.6 For the circuit shown in Fig.V1 (1.56 x 0.2 fF/(llm)2 and that the diode has an area of 20 urn x 5 um .21).02 pF (1. Compare your answer to that obtained using SPICE.56C jo (1.) V2. 1.10 Chapter 1 • IntegratedCircuit Devices and Modelling problem. and V2 are the two voltage extremes [Hodges. For this special case. through a IOkn resistor.38) It will be seen in the following example that (1. as a rough approximation to quickly estimate the charging time of a junction capacitance from 0 V to 5 V (or vice versa).011 pF (lAO) .37).5 V.3. 1988]. EXAMPLE 1. Solution The total smallsignal capacitance of the junction at 0V bias voltage is obtained by multiplying 0. one can instead calculate the charge stored in the junction for the two extreme values of applied voltage (through the use of (1.35) (1. h i (1.21)).34) where V. Assume that C jO = 0. for an abrupt junction with reversebias voltage Vi' we have Q(V i ) = 2C. and using <1>0 = 0. From (1.5 V.36) One special case often encountered is charging a junction from 0 V to 5 V.37) Thus.39) Using (1. and then through the use of Q = CV. we have C jav = 0. calculate the time required to charge the diode from 0 V to 3.2 fF/(). Repeat the question for the case of the diode being discharged from 5 V to 1.2 X 10.lm)' by the junction area to obtain C jO = 0.37) compares well with a SPICE simulation. we find that C jav = 0.)Q(V.15 x 20 x 5 = 0.02 = 0.9 V. where a reversebiased diode is being charged from 0 V to 5 V.
1. For smaller bias voltages it is larger than that * * * . The input data file was as follows: R I 2 10k D02DMOD VIN lOde 2.3(a) was analyzed using SPICE...TRAN O.END The SPICE simulation gave a OV to 3. (b) its RC approximate equivalent.41 ) Thus.11 ns fall) 70 percent of its final value is equal to 1.0 V 00' 20 ~ urn X 5 urn jO = 0.14 ns and a 5V to 1. in this case. (1.5V rise time of 0. 1..MODEL DMOD D(CJO=0. resulting in a time constant of r = Re j _av = 0.02E12) .42) It is not difficult to show that the time it takes for a firstorder circuit to rise (or 170 % = 1.2 t = 0.6.WIDTH OUT=80 ..Oln LOn .PRINT TRAN V(2) .12 ns.13 ns predicted.5 PULSE (0 5 0 lOp lOp 0. (1.13 ns As a check.49n LOn) .OPTIONS NUMDGT=5 ITLI=500 .3 (a) The circuit used in Example 1.2~.2 fF/(~m) 2 C (a) (b) Fig.1 Semiconductors and pn Junctions 11 R = 10 kQ Vi' 0'1/1. 1. These times compare favorably with the 0.5V fall time of 0.. The reason for the different values of the rise and fall times is the nonlinearity of the junction capacitance.. the circuit of Fig.
they recombine with the majority carriers. This current flow is called drift.010 pF (1. l OSf = 0. The majority carriers that recombine with the diffusing minority carriers come from the metal contacts at the junctions because of the forwardbias voltage. It also reduces the width of the depletion region. For germanium and gallium arsenide semiconductor materials.5 I + .37) is not worth the extra complication because one seldom knows the area of CiG to better than 20 percent accuracy. = 0 Y.45) = 0. thereby decreasing their concentration. After the carriers cross the depletion region.9 J (1.012 pF 0. These minority carriers will diffuse away from the junction toward the bulk.. they greatly increase the minority charge at the edge of the depletion region.9 = 0. ForwardBiased Junctions A positive voltage applied from the p side to the n side of a diode reduces the electric field opposing the diffusion of the free carriers across the depletion region. the carriers diffuse across the junction due to the large gradient in the mobile carrier concentrations.5 and V. When the junction potential is sufficiently lowered for conduction to occur.46) in closer agreement with SPICE. Note that there are more carriers diffusing from the heavily doped side to the lightly doped side than from the lightly doped side to the heavily doped side.02 x 0.0. If this forwardbias voltage is large enough.36) instead of (1. we find that C jav = 2 x 0.5 Y.9(FH·5 3.9 Y. As they diffuse.02 x  0. resulting in a current flow from the anode to the cathode.12 Chapter 1 • IntegratedCircuit Devices and Modelling predicted by (1.5 (Hi·5 1+ . due to an electric field applied across the bulk.44) These more accurate approximations result in t.9 RJ I+0.1 = 0. for the fall time. current conduction starts to occur around 0.5 .3 Y and 0.114 ns (1. These majority carriers flow across the bulk. we find C jav = 2 x 0.144 ns and tlUI} (1. For silicon. appreciable diode current starts to occur for a forwardbias voltage around 0. the carriers will start to diffuse across the junction. the extra accuracy that results from using (1. whereas for larger bias voltages it is smaller. from the contacts to the junction. Normally. respectively. If we use the more accurate approximation of (1. It results in .37).36) for the rise time with V2 = 3. This concentration gradient of the minority charge (which decreases the farther one gets from the junction) is responsible for the current flow near the junction.43) Also.9 1.
the distance from the contacts to the junction. implies that the minority charge storage must double. called the diffusion capacitance. especially in the lightly doped side. Junction Capacitance of ForwardBiased Diode When a junction changes from reverse biased (with little current through it) to forward biased (with significant current flow across it).1. Cd' and the depletion capacitance. similar to when the junction is reverse biased. the currentvoltage relationship is exponential and can be shown (see Appendix) to be I D . Thus. This component is modelled by another capacitance. in tum.49) T where is the transit time of the diode.50) 'T 'T For a forwardbiased junction. The total capacitance of the forwardbiased junction is the sum of the diffusion capacitance.48) Is is known as the scale current and is seen to be proportional to the area of the diode junction. Normally is specified for a given technology. and this. An additional change in charge storage is necessary to account for the change of the minority carrier concentration close to the junction required for the diffusion current to exist. and inversely proportional to the doping concentrations. This change in charge is modelled by the depletion capacitance. the total junction capacitance is given by ( 1. Typical values of this voltage drop might be 50 mY to 0.1 Y. Cj . then the slopes of the minority charge storage at the diode junction edges must double.I seVo/V. AD. Part of the change in charge is due to the change in the width of the depletion region and therefore the amount of immobile charge stored in it. The accuracy of this approximation is not critical since the diffusion capacitance is typically much larger than the depletion capacitance. if a forwardbiased diode current is to double. For example. In the forwardbias region. the charge being stored near and across the junction changes. Cj . and the crosssectional area of the junction. depending primarily on the doping concentration of the lightly doped side. .1 Semiconductors and pn Junctions 13 small potential drops across the bulk. C j . the depletion capacitance. where V D is the voltage applied across the diode and (1. can be roughly approximated by 2C jo. so that one can calculate the diffusion capacitance. and denoted Cd' The diffusion capacitance can be shown (see Appendix) to be Cd = D 'TV 1 (1. Note that the diffusion capacitance ofa forwardbiased junction is proportional to the diode current.47) ( 1.
we see that an alternative equation for the diffusion capacitance. it is sometimes necessary to add the series resistance due to the bulk and also the resistance associated with the contacts.models the change in the diode voltage.= T e VO/V T (1. Using (1047). where C j becomes important. for charging or discharging a forwardbiased junction with a current source having an impedance much larger than ro. Cd' is (1. Typical values for the contact resistance (caused by the workfunction/ difference between metal and silicon) might be 200t0400. 2.52) Since for moderate forwardbias currents. A resistor. This behavior does not occur in Schottky diodes since they do not have minority charge storage.V. For very accurate modelling. 1.51) This resistance is called the incremental resistance of the diode. By combining (1049) and (1.14 Chapter 1 • IntegratedCircuit Devices and Modelling Finally.53) Thus. ro.the time constant of the charging is approximately equal to the transit time of the diode and is independent of the diode current. SmallSignal Model of a ForwardBiased Diode A smallsignal equivalent model for a forwardbiased diode is shown in Fig. the total smallsignal capacitance is C T " Cd' and (1.4 The smallsignal model for a forwardbiased junction. V D' that occurs when 1D changes. the charging or discharging time constant of the circuit becomes larger than 'tT' Fig. Cd » C j . we have I = = 15 . For smaller diode currents. . The workfunction of a material is defined as the minimumenergy required to remove an electronat the Fermi level to the outside vacuumregion.51). 104. it should be mentioned that as a diode is turned off for a short period of time a current will flow in the negative direction until the minority charge is removed.
as occurs at the cathode. What are the values of its smallsignal resistance and diffusion capacitance? Assume room temperature. 1. one often used in microcircuit desig n. is realized by contac ting metal to a lightly doped semiconductor region (rather than a heavily doped region) as shown in Fig.4 and 1.8 26 n p F Note that this diffusion capacitance is over 100 times larger than the total depletion capacitance found in Examples 1. its voltage drop when forward . Solution We have = 26 mY = 26 I rnA n and = )00 ps = 3. a diode to occur at the interface between the aluminum anode and the n" silicon region. so that V T = kT / q = 26 mY. 1 Semiconductors ond pn Junctions 15 EXAMPLE 1.region.7 A given diode has a transit time of 100 ps and is biased at I rnA. Schottky Diodes A different type of diode.5. Notice that the alum inum anode is in direct contact with a relatively lightly doped n. First. the workfunction difference between the aluminum contact and the n" silicon is larger than would be the case for aluminum contact ing to an n + region.5. This diode has differe nt characteristics than a normal pn junction diode. This causes a depletion region and. Because the n" regio n is relatively lightly doped.1. correspondingly.
Before CMOS technology became widely available. One type. the minimum channel length is typically between 0. for complementary MOS. bipolar technologies utilizing highspeed vertical pnp transistors. A typical cross section of an nchanncl enhancementtype MOS transistor is shown in Fig. there is no minoritycharge storage in the lightly doped n. The aCIonym MOS stands for metaloxide semiconductor.5 V.substrate. Most BJT technologies can also realize lowspeed lateral pnp transistors. as well as highspeed npn transistors. More importantly. The separation between the drain and the source is called the channel length. it is only necessary to discharge the depletion capacitance through about 0. The other type.6. have become available and are growing in popularity. the n" source and drain regions are separated by the p. Thus. often two different types of nchannel transistors could be realized. Large MOS transistors used for power applications might not be realized with symmetric drain and source junctions.3 11m and 1. insulator. These technologies are called complementary bipolar technologies. respectively. when the diode is forward biased. Recently. most MOS processes made use of only nchannel transistors (NMOS). and channel region materials. Schottky diodes have been used extensively in bipolar logic circuits. conduct current with a gatesource voltage of 0 V. In present MOS technologies. because it is not necessary to remove the minority charge first. 4. While nchannel devices conduct with a positive gate voltage. Moreover. enhancement nchannel transistors. L.16 Chapter I • IntegratedCircuit Devices and Modelling biased is smaller. Normally these would only be used to realize current sources as they have low gains and poor frequency responses. the smallsignal model of a forwardbiased Schottky diode has Cd = 0 (with reference to Fig. particularly those realized in gallium arsenide (GaAs) technologies. They are also used in a number of highspeed analog circuits. Microcircuits containing both nchannel and pchannel transistors are called CMOS circuits. It is particularly faster when turning off. MOS circuits normally use two complementary types of transistorsenchannel and pchannel. 1. depletion transistors. Enhancement transistors require a positive gatetosource voltage to conduct current. Depletion transistors were used to create highimpedance loads in NMOS logic gates. most present CMOS technologies utilize polysilicon gates rather than metal gates.4). However. which make dominant use of only one type of transistor (npn transistors in the case of BJT processes'). 1. The absence of this diffusion capacitance makes the diode much faster. for aluminum it might be around 0. rather than silicon technologies. . which historically denoted the gate.0 11m. electrons are used to conduct current in nchannel transistors. With no voltage applied to the gate.2 MOS TRANSISTORS Presently. is similar to the nchannel transistors realized in CMOS technologies. Unlike most bipolar junction transistor (BJT) technologies. the most popular technology for realizing microcircuits makes use of MOS transistors. It should be noted that there is no physical difference between the drain and the source. 1." The source terminal of an 3. pchannel devices conduct with a negative gate voltage. However. This voltage drop is dependent on the metal used.region.2V. Rather. while holes are used in pchannel transistors.
but in di gita l circuits it is normall y gro und or 0 V . This higher geometric acc uracy results in smaller.0 1 urn to 0. they are conn ected together throu gh some other mean s). For a pchannel tran sistor. In both cases. n chann el transistor is defined as whiche ver of the two terminals has II lower voltage. which is heavily doped noncrystalli ne (or amo rphous) silicon .03 um . The sym bol in Fig . In analog circuits. 1. 1. this might be the negative power supply. but the current directions are different because nchanne l carriers (electrons) are negative. the true carriers travel from the source to drain.7(a) is often used . which electrica lly isolate the transistors and thereby prevent conduction through the substrate between transistors (unless . Symbols for MOS Transistors Many symbo ls have been used to represent MOS transistors. Thi s connection results in all transi stors placed iii the substrate being surrounded by reve rsebiased junctions. Thu s. note that there is nothin g in the symbol to specify . Since the gate is electrica lly iso lated from the channel. faster transistors. However. Figure 1. Norm ally the p substrate (or bulk) is connected to the most negative voltage in a microcircuit. it ne ver conducts de current . Poly silico n gates are used nowadays (instead of meta l) beca use polysilicon allows the dimensions of the transistor to be reali zed much more acc urate ly during the patterning of the transi stor. A typical thick ness for the 5 i02 insulator between the gate and the channel is presently from 0. simi lar to capacitive coupling. The gate is phys icall y separated from the surface of the silicon by a thin insulator made of silicon dioxide (5 i0 2 ) . because of the inherent capacitances in MOS transistors. which involve s what is called a se lfaligned process.1. T he gate is normally realized using poly silicon. of cour se. When a transistor is turned on. Indeed. transient gate currents do exis t when gate voltages are quickly changing. the source wo uld be the terminal with the higher voltage. the exce llent isol ation results in leakage currents being almost undetectable.6 A cross section of a typical nchunnel transistor. the transistor current) on ly through electrostatic coupling.2 Palysilican Metal (AI) Gate MO S Transistors 17 Source Drain Si02 Bulk or substrate Fig.7 shows some of the sym bols that have been used [0 represent nchannel MO S transistors. current flows from the drain to the source in an nchannel transistor and from the so urce to the drain in a p channel tran sistor. the gate is electrically isolated from the channel and affec ts the channel (and hence. whereas pchanne l carri ers (holes) are pos itive.
The last symbol. when in doubt. MOS transistors are actually fourterminal devices. it will never be used to represent MOS transistors in this text.7(c) can be used to show the substrate connection explicitly. The arrow pointing outward on the source indicates that the transistor is nchannel.7(b) is the most commonly used symbol for an nchannel enhancement transistor and is used throughout this text. for CMOS technologies. whereas for pchannel devices. Figure 1. It should be noted that this case is not encountered often in digital circuits and is more common in analog circuits. 1. most of the nwell substrates would be cosnected to the most positive power supply. This simple notation is more common for digital circuits in which a large number of transistors are present. the n substrate is normally connected to the most positive voltage. 1. with the substrate being the fourth terminal. In these cases. .8(a) will be most often used. whether the transistor is nchannel or pchannel.1. the symbol shown in Fig. denotes an nchannel depletion transistor.8(c) is (a) (b) (c) (d) (e) Fig. 1.8 shows some commonly used symbols for pchannel transistors. A common rule is to assume. and indicates the direction of hole current. Figure 1.18 Chapter 1 • IntegratedCircuit Devices and Modelling (a) Fig. shown in Fig. In these cases the substrate connection is normally not shown in the symbol. For example. Depletion transistors were used in older NMOS technologies but are not typically available in CMOS processes. an nwell process would form nchannel transistors in a p. the isolation of the gate is not explicitly shown.substrate encompassing the entire microcircuit. 1. that the transistor is an nchannel enhancement transistor. while some might be connected to other nodes in the circuit (often the well is connected to the source of a transistor that is not connected to the power supply). 1.7 (b) (c) (cf) (e) Commonly used symbols for nchannel transistors.8 Commonly used symbols for pchonnsl transistors. the symbol of Fig. the p" substrate is normally connected to the most negative voltage in the microcircuit. In nchannel devices. similar to the convention used for npn transistors. as is the case of the symbol of Fig. in the interest of simplicity. Sometimes. However.7(d). In this case. at least one of the two types of transistors will be formed in a well substrate that need not be connected to one of the power supply nodes. while the pchannel transistors would be formed in many nwell substrates. 1.7(e). The symbol in Fig. In this text. Since this symbol is also used for JFET transistors. The extra line is used to indicate that a physical channel exists for a 0V gatesource voltage.
1. thi s negati ve ga te vo ltage has the effec t of sim ply incr easing the c ha nne l doping to p'. I (b) .9(a ).8(e ) mig ht be used in larger c ircuits where man y transistors a re present. TIley w ill not be used in this text. consider the simplified cross sections shown in Fig . as op pose d to a high voltage for an nchannel tran sistor (F ig.substrate n" ..1. Basic Operation The basic operation of MOS transistors wi ll be described with respect 10 a n n chann el transistor..J . resulting in an accumulated channel (no current H ow]: (bl VG » 0 . Fig. 1.. 1. a nd the surface of the silicon. Th e ga te ac ts as o ne plate of the ca pacito r./ Drain ///// ///'. S ource S i02 . and the channel is present [curre nt Row possible from dra in to source). The symbols of Fig.. . If the ga te vol tage is very negat ive.1.sub strate I (a) Source Drain "1////////11/1'""". \ n" Depletion region ~ Channel p. ju st und er the thin insul at ing 8i0 2 • act s as the othe r plate./" / /. dr ain.. positi ve charge will be attrac ted to the c ha nne l regi on...8(d ) or Fig. the MOS transistor ope rates si mi larly to a ca paci tor.9 . a nd subs tra te are all connected to ground . 1. Firs t. S ince the subs tra te was orig ina lly doped p".'//  Depletion region i Accumulation region p... where the circle indicates that a low voltage o n the gate turns the tran sistor on. to sim plify the drawing so mewhat. 1. In th is case.9 A n nchannel MOS transistor. whe re the so urce. 10) V o « 0 ....2 MO S Transistors 19 some times used in di git al circuits. as show n in Fig.7(a » .
For gatesource voltages less than Vtm it is normally assumed that the transistor is off and no current flows between the drain and the source.Vtn ) = CoxVelf (1. and for gatesource voltages slightly less than Vto . . and conduction between the drain and the source can occur.9) and t ox is the thickness of the thin oxide under the gate. 5. When the gatesource voltage.54) The charge density of electrons is then given by o. is commonly referred to as the transistor threshold voltage and denoted Vto (for nchannel transistors). define (1. it should be noted that this assumption of zero drainsource current for a transistor that is off is only an approximation. as shown in Fig. resulting in the equivalent circuit of two backtohack diodes. for gate voltages around Vto' there is no abrupt current change. The drain and source regions are sometimes called diffusion regions or junctions for historical reasons. and therefore the charge density. A point to note here is that (1.20 Chapter 1 • IntegratedCircuit Devices and Modelling resulting in what is called an accumulated channel. However. the positive carriers in the channel under the gate are initially repulsed and the channel changes from a p" doping level to a depletion region. the carrier density. Indeed. Specifically. the density of electrons in the channel increases.56) where Kox is the relative permittivity of Si02 (approximately 3. as discussed in Section 1. which is often called the effective gatesource voltage and denoted Velf. for which the concentration of electrons under the gate is equal to the concentration of holes in the p: substrate far from the gate. the gate attracts negative charge from the source and drain regions.55) Here. the channel is present. This use of the word junction is not synonymous with our previous use. Thus. As a more positive gate voltage is applied.Vtn. small amounts of subthreshold current can flow.' In short. and the channel is said to be inverted. the opposite situation occurs. only leakage current will flow even if one of the source or drain voltages becomes large (unless the drain voltage becomes so large as to cause the transistor to break down). In fact. Cox is the gate capacitance per unit area and is given by . For small positive gate voltages.55) is only accurate when both the drain and the source voltages are zero. is proportional to VGS . In the case of a positive voltage being applied to the gate. = Cox(V GS . Cox KoxE o = t ox (1.3. VGS ' is larger than Vto. in which it designated a pn interface of a diode. 1. For gatesource voltages larger than Vto' there is an ntype channel present. The gatesource voltage. a sufficiently large positive gatesource voltage changes the channel beneath the gate to an n region. As VGS is increased.9(b). and the channel becomes an n region with mobile electrons connecting the drain and source regions. The n' source and drain regions are separated from the p+channel region by depletion regions.
which occurs when aMOS tran sistor is being turned off because the channel charge. ( 1.57) and the tota l charge 01 the channel. Note that as the channel length increases. The current h actually conductedh) negative carriers (elec tro ns) flowing from m source 10 me drain. and O n is the charge co ncentration of the channel per unit area (loo king from the lOP down ).10 The important dimensions of a MOS transistor.58) and ( 1." The relationship between Vos and the drainso urce current . This difference results in curre nt flowing from the drain to the source. 198 1) by 10 W = IlnOn'L Vos ( 1.06 m' / Vs is the mobi lity 01 elec tro ns nearthe silico n surface.10. is the same as for a resistor.59) where Iln . Next.2 MOS Trcnsistors 21 To ob tain the total gate capa citance. (1. the drainsource c urre nt decreases. 0 T_ must flow from unde r the gate out through the terminals to n' other places in the circuit. whereas this current increases as either the charge density or the transistor width increases. e Nega tive carriers flowi ng from source 10 drain re. C g s ' is one of the major load capacitances that circuits must be capable of driving.58) The gate capacitance.60) Gate SiD2 ~' n channel Fig. loa  . This relationship is given [Sze.56) sho uld be multiplied by the e ffec tive gale area. 0 T_n' is given by ( 1.1.ults in a positive curre nt from drain 10 source. where W is the gale width and L is the effective gate length . 1. Using (1 . assuming Vos is small. WL. Gate capacitances are also important when one is calculating charge injection . if the drain voltage is increased abov e 0 V. 10 . 6.: 0. Cgs' is give n by C g s = WLC o . TI1USthe total gate capaci tance. 1.  ( 1..59) results in . a drainsource poten tial difference exists. These dimensions arc shown in Fig.
Vos much smaller than Velf). the charge density also decreases. As the drainsource voltage increases. there is an increasing voltage gradient from the source to the drain. the 10 versus linear. and the charge density decreases near the drain.V'n' as VG .11 The channel charge density for Vos > 0 .Vch(X) decreases. we saw from (1.. . VG. Vs = 0 Depletion region Increasing x Qn(L) = C0' (VGD.61) For small Vos.12.11. as Vos increases. we have (1. 1. the linear relationship for 10 versus Vos flattens for larger Vos. 1.12 For Vas nat close to zero.' This effect is illustrated in Fig. This decrease is due to the smaller gatetochannel voltage difference across the thin gate oxide as one moves closer to the drain.Vch(X) . resulting in a smaller gatetochannel voltage near the drain.60) that 10 was linearly related to Vos' However. the channel charge concentration decreases at the drain end.V) tn Fig.e. the relationship becomes nonlinear. as shown in Fig. 1. VDS relationship is no longer 7. Since the charge density at a distance X from the source end of the channel is proportional to VG . In other words.VCH(X) is the gatetochannel voltage dropat distance x from the source end. In fact. with VG being the same everywhere in the gate. Fig.22 Chapter 1 • IntegratedCircuit Devices and Modelling where it should be emphasized that this relationship is only valid for drainsource voltages near zero (i. Note that at the drain end of the channel. since the drain voltage is assumed to be at a higher voltage than the source. 1. since the gate material is highly conductive.
When they are used in digital logic gates. 8. Thus. the active region was called the saturation region. In the region of operation where V DS > V Ds.14 for a given gatesource voltage. v« = 0 Depletion region n' Pinchoff for VGD<V t n Fig. 1. resulting in the true value of VOS_sal being slightly lower than Veft . but this led to confusion because in the case of bipolar transistors. If the draingate voltage rises above this critical pinchoff voltage of V'n' the charge concentration in the channel remains constant (to a firstorder approximation) and the drain current no longer increases with increasing VDS' The result is the currentvoltage relationship shown in Fig. . since the channel voltage at the drain end is simply equal to VD' Thus. Because of the body effect. 9.2 MOS Transistors 23 As the drain voltage is increased. similar to a gas under pressure travelling through a very small tube.63) where V OSsat is given'' by VDssat = VGSV tn = v« (1.l3. the saturation region occurs for small VCE ' whereas for MOS transistors it occurs for large Vos.1.62) and find an equivalent pinchoff expression V DS > V OSsat (1.64) The electron carriers travelling through the pinchedoff drain region are velocity saturated. they almost always are biased in the active region. they often operate in both regions.sa" the drain current is independent of V os and is called the active region. the channel becomes pinched off. we can substitute V DG = V DS . Historically.V GS into (1.62) Denoting Vossat as the drainsource voltage when the channel becomes pinched off. When MOS transistors are used in analog amplifiers.the minimum gatetochannel voltage needed for n carriers in the channel to exist. at some point the gatetochannel voltage at the drain end will decrease to the threshold value Vtn . 1.n• the channel becomes pinched off at the drain end.' The region where 10 changes with Vns is called the triode region. as shown in Fig. 1. the threshold voltage at the drainend of the transistor is increased. pinchoff occurs for (\ . This pinchoff occurs at VGO = Vtn. at the drain end.13 When VDS is increased so that VGD < V. The renamingof the saturation region to the active region is becoming widely accepted.
Thus. As just discussed. it is worth discussing the terms weak. It can be shown (see Appendix) that this relationship is given by (1.65) As VDS increases. For Vos > V DSsat' 10 is approximately constant.L_ V Triode region GS constant Active region Fig. as the gatesource voltage is increased. However. Before proceeding.3. Weak inversion occurs when VGS is approximately 100 mV or more below V" and is discussed as subthreshold operation in Section 1.CO'W(V 2 L _ V )2 GS In _~__J. strong inversion occurs when the channel is strongly inverted. and strong inversion.65) and the drain current in the active region (which..14 The I D versus V DS curve for on ideal MOS transistor. and drainsource current can flow. the drain current resulting from (1. with Veff > 100 mV (many prudent circuit designers use a minimum value of 200 m"). but rather gradually.66) Right at the edge of pinchoff. noncutoff MOSFET transistors are operated in strong inversion. moderate. This pinchoff occurs for VDG V". nregion) suddenly. I D increases until the drain end of the channel becomes pinched off.e. It should be noted that all the equation models in this section assume strong inversion operation. Finally. or approximately. and then I D no longer increases. moderate inversion is the region between weak and strong inversion. As the name suggests. 1. largeSignal Modelling The triode region equation for a MaS transistor relates the drain current to the gatesource and drainsource voltages. to a firstorder approximation. a gatesource voltage greater than V" results in an inverted channel. it is useful to define three regions of channel inversion with respect to the gatesource voltage. (1. the channel does not become inverted (i.24 Chapter 1 • IntegratedCircuit Devices and Modelling ~. is constant with . In most circuit applications.
. (1. The major source of error is due to the channel length shrinking as Vos increases. This independence is only true to a firstorder approximation. 1.65). ignoring secondorder effects such as the finite output impedance of the transistor. 1. The voltage difference between the drain and the near end of the channel lies across a short depletion region often called the pinchoff region. we first make use of (1. In turn.67) implies that the drain current..67) For Vos > Veff .2 MOS Transistors 25 respect to Vas) must have the same value. this depletion region surrounding the drain junction increases its width in a squareroot relationship with respect to Vos' This increase in the width of the depletion region surrounding the drain junction decreases the effective channel length. As just mentioned. Therefore. The voltage at the end of the channel closest to the drain is fixed at VGS .15 Channel length shortening for V DS > V elf· . A pinchedoff region with very little charge exists between the drain and the channel.66) into (1. . To see this effect. This equation is perhaps the most important one that describes the largesignal operation of aMOS transistor.11) and denote the width of the depletion region by xd.67). .Vl n = Veff . which shows a cross section of a transistor in the active region. resulting in xd where  kd s JV Dcch + <1>0 (1..15. the active region equation can be found by substituting (1. consider Fig. an exponential currentvoltage relationship exists in the active region.. is independent of the drainsource voltage. Depletion region l>L = JV DS  V elf + <Po Pinchoft region Fig.69) VG S > v. resulting in what is commonly referred toas channellength modulation. To derive an equation to account for channellength modulation. the current stays constant at the value given by (1. As Vos becomes larger than Veff .67) represents a squared currentvoltage relationship for a MOS transistor in the active region.68) (1. resulting in (1.1.. In the case of a BJT transistor. this decrease in effective channel length increases the drain current. It should be noted here that (1. ro..
10 increases more than is predicted by (1..e. Note that NA is used here since the ntype drain region is more heavily doped than the ptype channel (i. 1.70) 2LJV oo + V'n + <1>0 (1. inqreasing the electric field no longer increases the carrier speed).)=) _ Dvsat (1.71) assumes that current flow down the channel is not velocitysaturated (i.71) "Ie = = (1.Vic) Triode region :. (1. Note that in the active region. the transistor will eventually break down.16 10 versus Vas for different values of VGs .=V:::::os==V=et:=./ Active region Shortchannel effects i Increasing VGS Fig.I (I + :kd:. we find 10 to be given by = .71).e. If Vos becomes large enough so shortchannel effects occur. Of course.26 Chapter 1 • IntegratedCircuit Devices and Modelling and has units of rnfJV. . 1. By writing a Taylor approximation for 10 around its operating value of Vos = VGS . For example. Velocity saturation commonly occurs in new technologies that have very short channel lengths and therefore large electric fields. for quite large values of Vos.16.72) Equation (1.. often called shortchannel effects. A plot of 10 versus Vos for different values of VGS is shown in Fig.Vln = Veff .::s(. the small (but nonzero) slope indicates the small dependence of loon Vos' Vos = (V GS . No» NA) .71) is accurate until Vos is large enough to cause secondorder effects.
2 MOS Transistors 27 EXAMPLE 1. NA = 10". lt should be noted that the body effect is often important in analog circuit designs and should not be ignored without consideration.4 V.2 V.. bulk) voltage.'5) = 77. typically called the body effect. However. Assuming A remains constant. sourcetosubstrate voltage). we find for Vos = Velf = 0.6 ~Ax(l +AXO. This effect. Vtn. we have ~~ 12 2 x 11. we have 102 = 73.as the sourcetosubstrate reversebias voltage increases.9 JD.9 V.1 ~A Note that this example shows almost a 5 percent increase in drain current for a 0.4) (I) = 73.72) to find A as A= '''==6 2 x 2 X 10X 362 X 10.6 X 10 19 = 362 x 10.8 V.mljV 9 x 10" which is used in (1.71).6 ~A F'Z 2 In the case where Vos = Velf + 0. often the source and substrate can be at different voltage potentials.73) where V. is more important for transistors in a well of a CMOS process where the substrate doping is higher.5 V increase in drainsource voltage. a secondorder effect exists that is modelled as an increase in the threshold voltage. 10 1 =( 92 X 10 6 2 \r20} 0.69). 25 Solution From (1. V'n = 0.e. .8 Find 10 for an nchannel transistor that has doping concentrations of No = 10 . and Vos = Velf. ~nCox = 92 ~A/V2.8 x 8.nO is the threshold voltage with zero VS B (i. VG S = 1. To account for the body effect. it can be shown (see Appendix at the end of this chapter) that the threshold voltage of an nchannel transistor is now given by (1. estimate the new value of 10 if Vos is increased by 0.. W/L = 20 ~m/2 urn .1.e.5 V = 0.3 X 103 VI Using (1.854 x 10 1. In these situations. Body Effect The largesignal equations in the preceding section were based on the assumption that the source voltage was the same as the substrate (i.9 = 95.5 V.
replaced by open circuits). For nchannel depletion transistors. Thus. .28 Chapter 1 • IntegratedCircuit Devices and Modelling and y= J2qN AK.. these equations can also be used if a negative sign is placed in front of every voltage variable. 1. resulting in positive hole current flow from the source to the drain in pchannel transistors. y is proportional to Noll. We first consider the de parameters in which all the capacitors are ignored (i. A typical value might be V'd = 2 V. 10 so the body effect is larger for transistors in a well where typically the doping is higher than the substrate of the microcircuit.p. For an nchannel transistor. Notice that y is proportional to IN.76) lO. smallsignal model shown in Fig. especially if they were in a well. The condition required for conduction is now V SG > Vip. SmallSignal Madelling in the Active Regian The most commonly used smallsignal model for a MOS transistor operating in the active region is shown in Fig. in both regions. but these areof little value andseldom worththe extraprocessing involved. Fora pchannel transistor.74) Cox The factor y is often called the bodyeffect constant and has units of JV. where Vtp is now a negative quantity for an enhancement pchannel transistor.. 9m v 9" is the most important component of the model. It is possible to realizedepletion pchannel transistors. This leads to the lowfrequency. remain unchanged.. In the case of pchannel transistors. (1. because all voltage variables are squared.17. pChannel Transistars All of the preceding equations have been presented for nchannel enhancement transistors. although they might be worth the extra processing involved in some applications.18.. 11 The requirement on the sourcedrain voltage for a pchannel transistor to be in the active region is Vso> VSG + V. VGS becomes VSG' VOS becomes Vs o. with the transistor transconductance 9 m defined as 9m In the active region.E o (1. which is repeated here for convenience. the only difference is that V'd < 0 V.75) ro = Iln Cox(W\v 2 L! GS _ V )' tn (1. Depletion nchannel transistors are also seldom encountered in CMOSmicrocircuits.67).e. V'n becomes V. The voltagecontrolled current source. and so on.p' The equations for ro. we use (1. 1.
2 MOS Transistors 29 C gd Vg ~I"'_"""'_O Cgs _ V Vd gs 9m Vgs C'b I r<~<~o Vd Fig. Sometimes it is desirable to express 9m in terms of I D rather than V GS _ From (1.= Iln C oxL (VGS GS aID W Y. Veff . Veff .78) where the effective gatesource voltage.n+ 21D (1. smallsignal model for an active MOS transistor. L W (1. we have VGS = V.79) The second term in (1.V. we see that the transconductance of a MOS transistor is directly proportional to Veff .79) is the effective gatesource voltage.80) . 1.n) = (1. is defined as Veff '" VGS .1. n Thus.76). where 21D (1..75) to obtain 9m = av. Fig. _ v gs v. 1. and we apply the derivative shown in (1. 9m = Iln C ox v.77) or equivalently.17 The smallsignal model for a MOS transistor in the active region.18 The lawfrequency.
using (1. if the source happens to be biased at the same potential as the bulk but is not .86).82) Note that this expression is independent of ~nCox and W /L.81) Thus. ~ V58 is zero. Thus. the transistor transconductance is proportional to ~ for a MOS transistor.84) 2 IV'n = V'no + y( JV 58 + 1t1>F we have JI 2t1>F I) (1.83) aID aV'n Using (1. if the source is connected to the bulk. id. which gives Vln as = gm (1. and it relates the transconductance to the ratio of drain current to effective gatesource voltage. gm V9" as shown in Fig. or when its voltage does not change appreciably.73). 1.87) Note that although g. and so the effect of g.30 Chapter 1 • IntegratedCircuit Devices and Modelling Substituting (1. When the body effect cannot be ignored.86) The negative sign of (1. is nonzero for V58 = 0. then this current source can be ignored..84) is eliminated by subtracting the current gsv.84) and (1. The second voltagecontrolled currentsource in Fig. from the major component of the drain current. whereas it is proportional to Ie for a BIT. From (1. However.78) results in an alternate expression for gm' gm = J2~nCox~ 10 (1. This simple relationship can be quite useful during an initial circuit design.8]) and then using (1. When the source is connected to smallsignal ground.18.85) (1.76) we have = =  aID sv. does not need to be taken into account.80) in (1. A third expression for gm is found by rearranging (1. we have (1.v" models the body effect on the smallsignal drain current. shown as g.18.80) to obtain gm = 210 Veft (1. we have g. 1. aV'n av 5 8 (1.
and VDS = Velf . . (1.91) (1. Assume y = 0.8 V. VGS = 1.9 Derive the lowfrequency model parameters for an nchannel transistor that has 22 2 doping concentrations of ND = 10"..lnCox 2 L trJ VGS .89) where the approximation assumes A is small.e.lA/V .V. repeated here for convenience.. Thus.5 V.2 x 73.88) we have I rds = gds = . aID aVDS (J. The resistor. such that we can approximate the drain bias current as being the same as I D.y.V eff 0.5 .shown in Fig. NA = 10 .= A .92) It should be noted here that (1. accounts for the finite output impedance (i.87). EXAMPLE 1.18.IV and VSB = 0.Using (1. W/L = 20 J. it models the channellength modulation and its effect on the drain current due to changes in Vosl.8. V'n = 0.2. (1.2 MOS Transistors 31 directly connected to it. What is the new value of rdsifthedrainsourcevoltage is increased by 0.D . we have .lA = 0.368 mA/V .90) is often empirically adjusted to take into account secondorder effects. 1. rds.lnCox = 92 J. we have 2I g m .71). J.sa .6 J.1. then the effect of gs should be taken into account since '" VSB is not necessarily zero.lm/2 urn .5 V? Solution Since these parameters are the same as in Example 1.4 V and from (1.90) where kds 2LJV DS + (V elf ) + <1>0 and (1.n) = AIDsal 2 = AID (1.
5 + 1. 1. known as a T model. it might appear that this model allows for nonzero gate current. 0. elled].19 an active The smallsignal. therefore. 76.6 is much smaller than the corresponding singletransistor gain in a bipolar transistor. is shown in Fig. one assumes from the beginning that the gate current is zero.061 mA/V Note that this sourcebulk transconductance value is about 1/6 that of the gatesource transconductance. At first glance. the gate current must always be zero. if V DS is increased to 0. This T model can often result in simpler equations and is most often used by experienced designers for a quick analysis. 0.9 V. 170 kQ ~A An alternate lowfrequency model.368 X 10 2J0.32 Chapter 1 • IntegratedCircuit Devices and Modelling 3 9s . but a quick check confirms that the drain current must always equal the source current.19.1. Vgo_+ Fig. x 73. this gain of 52.9 1O6 )JjA resulting in a new value of rds given by r ds  I AID' .90) to find r ds I 95.3 X 10 .8 X .6. 362 2(2 X X 10. and.4 x 10' xTLl 3 . For this reason.6 x 10 _1 6 . . lowfrequency T model for MOS transistor (the body effect is not mod v. 0_5 0. the new value for A is A. it is interesting to calculate the gain 9m rds . For rd s ' we use (1. which is the largest voltage gain this single transistor can achieve for these operating bias conditions. when using the T model. Recalling that V eff . 52. As we will see. 143 kQ At this point.4 V.
Solution The value of rs is simply the inverse of 9m resultingin . ? ( 1. The largest capacitor in Fig.L.substrate .~ c' 0.93) When accu racy is import ant.20 is a cross section of a MOS transistor.. an additional term should be added to (1.20 A cross section of an nchcnne l MOS transistor show ing the small..: ~ W L C o. 1987J that C gs is approximately given by C gs . 103 = 2. 1.2 MOS Transistors 33 EXAMPLE 1. I ['+'( T t Fig. Most of the capacitors in the smallsignal model are related to the physical tran sistor...1 0 Find the T model parameter.72 kQ rs =  I = I 9m 0. where the parasitic capacitances are shown at the appropriale locations. r s • for the transistor in Example 1.1. 1.94) Palysilicon AI Si0 2 '/"////////'/n' P' field implant c. T his addi tion al component is gi ven by ( 1.368 X The value of rd s remains the same. T p. . wh ich sho uld inclu de the /rillgillg capacitance (fringi ng capaci tance is due to boundary effects) .93) 10 take into account the ove rla p bet ween the gate and source j unc tion.signal capacitances. either 143 ill or 170 kQ. 1. Shown in Fig. depending o n the drainsource voltage.9.20 is C gs ' This ca pacitance is primarily due 10 the change in cha nnel charge as a result of a cha nge in VGS' It can be shown [Tsividis.
C s_sw and C dsw.99) OB 1+<Do and Ad is the area of the drain junction. Its value is given by (1. The capacitance C gd . Two other capacitors are often important in integrated circuits.the capacitor between the source and the substrate. The major reason these regions exist is to ensure there is no leakage current between transistors. is important when the transistor is being used in circuits with large voltage gain. This capacitor is due to the depletion capacitance of the reversebiased source junction. Here. Its size is given by ( 1.20 is C' sb. C gd is primarily due to the overlap between the gate and the drain and fringing capacitance. Lov is usually empirically derived. Because they are highly doped and they lie beside the highly doped source and drain junctions. (1. 1.97) Note that the total area of the effective source includes the original area of the junction (when no channel is present) plus the effective area of the channel. once again. sometimes called the Millercapacitor. The depletion capacitance of the drain is smaller because it does not include the channel area. the sidewall capacitances can result in large additional capacitances that must be taken into account in determining C sb and C db . The sidewall capacitances are especially important in modem technologies as dimensions .98) where H (1.95) when higher accuracy is needed. These are the source and drain sidewall capacitances. and it includes the channeltobulk capacitance (assuming the transistor is on). The next largest capacitor in Fig. we have ( 1. Thus. These capacitances can be large because of some highly doped p + regions under the thick field oxide called field implants.34 Chapter I • IntegratedCircuit Devices and Modelling where Lov is the overlap distance and is usually empirically derived.100) where.
105) EXAMPLE 1. given by Cdb = C'db + C dsw (1. and Cj_Sw =: C j swO (1. C jsw = 2.ov = 2.sw where Pd is the drain perimeter excluding the portion adjacent to the gate.02 pF C Sb pF = Cj(As + WL) + (C j_ swx P s) = 0_17 pF Cdb = (CjxAd)+(Cj_SWxPd) = 0_12 pF Note that the sourcebulk and drainbulk capacitances are significant compared to the gatesource capacitance.9 x 103 pF/(!tm). = G)wLC ox + C gsov x W = 0.2 shrink.1. excluding the side adjacent to the channel. C dsw = P dCj.11 An nchannel transistor is modelled as having the following capacitance parameters: 2 2 C J = 2..104) with the drainbulk capacitance. For the source. C db. C dsw. for highspeed circuits.101) where Psis the length of the perimeter of the source junction. Solution We calculate the various capacitances as follows: c.0 X 10'4 pF/!tm_ Find the capacitances C gs' Cgd' Cdb' and C sb for a transistor having W = lOO!tm and L = 2 um . Finally..27 C gd = Cgdov X W = 0. C sb' is given by (1. The situation is similar for the drain sidewall capacitance. it is important to .4 x 104 pF/(!tm). C ox = 1.102) )1 + V <Po SB It should be noted that C jswO' the sidewall capacitance per unit length at 0V bias voltage. Thus. C gsov = C gd. the sidewall capacitance is given by MOS Transistors 35 Cssw = p sCjSW (1. can be quite large because the field implants are heavily doped. so that the source and drain areas are As = Ad = 400 (!tm)' and the perimeter of each is P s = P d = 108 urn . the sourcebulk capacitance.103) C sb = C' sb + C ssw (1.0 x 10'4 pF/!tm. Assume the source and drain junctions extend 4 urn beyond the gate.
12 For the transistor of Example 1. where the gatetochannel capacitance .60). as seen in the next chapter).4 = 0.36 Chapter 1 • IntegratedCircuil Devices and Modelling keep the areas and perimeters of drain and source junctions as small as possible (possibly by sharing junctions between transistors. Using (1. The accurate modelling of the highfrequency operation ofa transistor in the triode region is nontrivial (even with the use of a computer simulation). A moderately accurate model is shown in Fig. we have 6 9ds = 92 X 10.72 kQ.21. smallsignal model of a MOS transistor in the triode region (which is sometimes referred to as the linear region) is a resistor.65). The resistance. 1.l08). Solution From (\. 9m' in the active region. SmallSignal Modelling in the Triode and Cutoff Regions The lowfrequency.368 mA/V Note that this conductance value is the same as the transconductance of the transistor. we have 9ds = ':s = ~nCo{~}VGsVtn) ~ ~nCo{~}eff (1. the largesignal equation for 10 in the triode region.9. 'ds' is simply 1/9ds ' resulting in 'ds = 2.x C20) x 0.108) which is similar to the IoversusVos relationship given earlier in (1.107) where 'ds is the smallsignal drainsource resistance (and 9ds is the conductance). find the triode model parameters when V DS is near zero. (1. EXAMPLE 1. For the common case of Vos near zero.106) results in ~ = 9ds = 'ds dID dVos = ~nCox(W)VGsVtnVos) L (1.
the IV relationships of the distributed RC elements are highly nonlinear because the junction capacitances of the source and drain are nonlinear depletion capacitances. The channeltosubstrate capacitance has also been divided in half and shared between the source and drain junctions. = (1.2 MOS Transistors 37 V g Gatetochannel capacitance . which should be taken into account when accuracy is very important. Also.1. the gatetochannel capacitance has been evenly divided between the source and drain nodes. This model is much too complicated for use in hand analysis. as given by (1.108).. rds ' is given by (1. c. then the channel resistance per unit length should increase as one moves closer to the drain. However.21 region. Here..22 A simplified trioderegion model valid for small Vas. 1. A distributed RC model for a transistor in the active and the channeltosubstrate capacitance are modelled as distributed elements. 1. A simplified model often used for small Vos is shown in Fig. where the resistance.109) Note that this equation ignores the gatetojunction overlap capacitances. as is the channeltosubstrate capacitance. .94)./ Channeltosubstrate capacitance Fig. Each of these capacitors should be added to the junctiontosubstrate capacitance and the junctionsidewall capacitance at the appropriate V g C gs 1 r 1 Cgd Vs ot"Vvto Vd Fig.22. 1. if Vos is not small.
23. c. 1. Since the channel has disappeared.. Thus.113) Sb H 1+<1>0 It might be noted that CSb is often comparable in size to C gS due to its larger area and the sidewall capacitance. we have (1. C gb . Another major difference is that C gs and C gd are now much smaller. Thus. A reasonable model is shown in Fig.111) Also. Perhaps the biggest difference is that rds is now infinite. We now have a "new" capacitor. the model changes considerably.110) and (1.114) However. which is the gate Fig. these capacitors are now due to only overlap and fringing capacitance. When the transistor turns off.112) CdbO (1. 1.23 A smallsignal model for aMOSFET that is turned off. we have (1.38 Chapter 1 • IntegratedCircuit Devices and Modelling node. . the reduction of C gs and C gd does not mean that the total gate capacitance is necessarily smaller. and = (1.
This large lateral field causes the effective channel depth to change and also causes more electron collisions.115) is usually used for hand analysis as a worstcase estimate. which might be on 6 the order of 1.117) 1. and leakage currents. then we have C gb = AchC o. and hotcarrier effects (such as oxide trapping and substrate currents). For more detailed modelling of shortchannel effects. We now have (1. due to large electric fields. This capacitor is highly nonlinear and dependent on the gate voltage. Transistors that have short channel lengths and large electric fields experience a degradation in the effective mobility of their carriers due to several factors. see [Wolf. These effects include mobility degradation. then C gb is equal 10 Cox in series with the channeltobulk depletion capacitance and is considerably smaller. One of these factors is the large lateral electric field (which has a vector in a direction perpendicular from the gate into the silicon) caused by large gate voltages and short channel lengths. Because of the complicated nature of correctly modelling C gb when the transistor is turned off.116) and (1. especially when the substrate is lightly doped. The capacitors C sb and C db are also smaller when the channel is not present. 1995]. Another factor causing this degradation is that.3 Advanced MOS Modelling 39 tosubstrate capacitance. Another case where C gb is small is just after a transistor has been turned off.115) If the gatetosource voltage is around 0 V.5 x 10 V 1m. (1. reduced output impedance. subthreshold operation. These shortchannel effects will be briefly described here.1. carrier velocity begins to saturate. If the gate voltage has been very negative for some time and the gate is accumulated. ShanChannel EHeds A number of shortchannel effects degrade the operation of MOS transistors as device dimensions are scaled down. equation (1. thereby lowering the effective mobility. Using this equation in the derivation of the loV eff .3 ADVANCED MOS MODEWNG In this section. we look at three advanced modelling concepts that a microcircuit designer is likely to encountershortchannel effects. before the channel has had time to accumulate. = WLC o. A firstorder approximation that models this carriervelocity saturation for electrons is given by Iln E 1 + E/E c (1.118) where E is the electric field and Ec is the critical electrical field.
soch as the generation of electronhole pairs by impact ionization and avalanching.120) Fo r ~ nC o . It ca n be show n that thi s mobil ity degrad ation is equivalent to a finite series so urce resistance given by Rs x = .8 .lnng transist or ). as Vo s is increased. I E C~ nCo. Another important shortc hannel effect is due to hot carriers. Taking channel len gth s larger than the minimum allo wed help s to minimi ze this degradation. for a 0 .24 Dra intosubstrole current caused ioniza tion at drain end of chan nel. it can be sho wn [Gray. th is resi stan ce might be o n the order o f 6 kO per urn of width (again.. thereby further lowering the output impedance of a shortchannel device.~ m techn ology. These highvelocity carriers can cause harmful effects.6 V. 1. 1. In many vo ltagetocurrent conv ersion ci rcuits that rely on the squarelaw characteristic. 19931 that the drain currem is now given by 10 ~ nC o = 2[1+8V.24. These extra electronhole pairs can cause currents to flow from the drain to the substrate..40 Cha pter 1 • InlegroledCircuit Device s and Mod elling characteristics of aMOS tran sistor . Thi s effeci can be modVO»Vtn Gale current Vo »O . for a 0. this inaccuracy can be a maj or source o f error. IW V'eN L eff ( 1.8 ~ m.'. and the lrue relationship will be so mewhe re bel ween linear and sq uare..11 9) where 8 = 1/ (LE c ) and.e I ". might have a typi cal value of 0.. as shown in Fig. Thi s sat ura tio n cau ses the sq uarelaw characteristic of the currentvo ltage relation ship 10 be inaccurate. = 90 ~A /V '.. In addition.. Thi s eq uiva lent series so urce resistan ce is typicall y larger than the physi ca l so urce resistance.bn~~~~~ . a phenomenon known as draininduced barrier lowering (DIBL) effectively lowers V.. Transistors with short channe l lengths also experience a reduced output impedance because depletion region variatio ns at the drain e nd (which affect the effective c hannel len gth) have an increased proportional effect on the drain current./'" current /'" Draintasubstrate e ~current Fig. This lower output impedance is the main reason that cascode current mirrors are becoming increasingly popular..W ( 1.. by electronhole pa irs generated by impa ct . punchthrOUg~.
Thus.122) and it has been assumed that Vs = 0 and Vos > 75 mV. the transistor is more accurately modelled by an exponential relationship between its control voltage and current. it should be noted that shortchannel transistors have much larger subthreshold currents than longchannel devices.e. In this region. . the drain current is approximately given by the exponential relationship [Geiger. However. the accuracy of the square law equations is poor. these highenergy electrons are no longer limited by the drift equations governing normal conduction along the channel. this effect can cause dc gate currents. the channel length becomes effectively zero. Subthreshold Operation The device equations presented for MOS transistors in the preceding sections are all based on the assumption that Veff (i. 1990] r. =' Ioo(~)e(qvGs/nkT) where (1. This mechanism is somewhat similar to punchthrough in a bipolar transistor.121) n = (1. this current flow can cause voltage drops across the substrate and possibly cause latchup. As a result. A third hotcarrier effect occurs when electrons with enough energy punch through from the source to the drain. somewhat similar to a bipolar transistor. often more harmful is the fact that any charge trapped in the oxide will cause a shift in transistor threshold voltage. In the subthreshold region. as well as external circuitry). VGS . In a MOS transistor. As a result.) is greater than about 100 mV and the device is in strong inversion. If Veff < 100 m V. Finally. As a result. Another hotcarrier effect occurs when electrons gain energies high enough so they can tunnel into and possibly through the thin gate oxide.3 Advanced MOS Modelling 41 elled by a finite draintoground impedance. where the collector depletion region extends right through the base region to the emitter. hot carriers are one of the major factors limiting the longterm reliability of MOS transistors. resulting in unlimited current flow (except for the series source and drain impedances. the transistor is in weak inversion and is said to be operating in the subthreshold region. In addition.1. The constant I oo might be around 20 nA. When this is not the case.. This effect is an additional cause of lower output impedance and possibly transistor breakdown. It should be noted that all of the hotcarrier effects just described are more pronounced for nchannel transistors than for their pchannel counterparts because electrons have larger velocities than holes. this effect is one of the major limitations on achieving very high output impedances of cascode current sources. as the next section describes.V.
the leakage current also doubles for every II 'C rise in temperature. However. Since the intrinsic concentration..42 Chapter 1 • IntegratedCircuit Devices and Modelling Although the transistors have an exponential relationship in this region. n. except in very lowfrequency and lowpower applications.126) where N c and Nv are the densities of states in the conduction and valence bands and E g is the difference in energy between the two bands. is the intrinsic concentration of carriers in undoped silicon. in the late 1970s.125) and n. the transconductances are still small because of the small bias currents. Normally.123) where Aj is the junction area. is a strong function of temperature (it approximately doubles for every temperature increase of II 'C for silicon). and x d is the thickness of the depletion region. ~o is the effective minority carrier lifetime.124) where ~n and ~p are the electron and hole lifetimes. Roughly speaking. Thus. In addition. This leakage current imposes a maximum time on how long a dynamically charged signal can be maintained in a high impedance state.4 BIPOLARJUNCTION TRANSISTORS In the early electronic years. transistors are not operated in the subthreshold region. is given by (1. ~o is given by (1. 1. matching between transistors suffers because it now strongly depends on transistorthresholdvoltage matching. the majority of microcircuits were realized using bipolarjunction transistors (BJTs). For example. Leakage Currents An important secondorder device limitation in some applications is the leakage current of the junctions. x d is given by 2K sEo (<1>0 + V r ) qN A (1. and the transistors are slow because of small currents for charging and discharging capacitors. microcircuits that used MOS . n. the leakage current is also a strong function of temperature. The leakage current of a reversebiased junction (not close to breakdown) is approximately given by (1. the leakage current at higher temperatures is much larger than at room temperature. this leakage can be important in estimating the maximum time a sampleandhold circuit or a dynamic memory cell can be left in hold mode. Also.
n' w Fig . with BJT microc ircuits rema ining popular for high. For lateral pnp transistors. A typical cross section of an npn bipolarjunction transistor is shown in Fig. the base current is much smaller than the collectortoemitter currentit may be only 1/100 of the co llector current for an npn transistor. Although this structure looks quite co mplicated. the base contro l termin al has a nonzero input current when the transistor is co nducting current (from the co llector to the emitter for an npn transi stor. bipolar CMOS (BiCMOS) technologies.4 Bipolcrlvnction Tra nsistors 43 transistors began to domin ate the indust ry. from the emitter to the collector for a pnp transistor). Si02 insulator (field oxide Metal Buried collector region Substrat e or bulk Fig. Modem bipolar transistors can have unitygain frequenci es as high as 15 to 45 GH z or more.~. co mpared to unitygain frequencies of only I to 4 GH z for MOS transi stors that use a techn ology with similar lithography resoluti on. in bipolar transistors.. Unfortunately. More recentl y. and thus it is important for an analog designer to become familiar with bipolar de vices. 1.'.25 n' Effective base region p" A cress section of an npn bipolarjunction transist or. BiCMOS technologies are particularly attracti ve for mixed analogdigital applications. . the base current may be as large as 1120 of the emittertnco llector current.25.26 A simplified structure of an npn transistor. at low frequ encies.'. 1. In a good BJT transistor. 1.26. "&~. where both bipnlar and MOS transistors are realized in the same microcircuit.speed appli cations. it corresponds appro ximatel y to the equivalent structure show n in Fig. 1.1. Fortun ately. Ba se .. the width of the base Base The base contact surrounds the emitter contact to minimize base resistance. have grown in popularity.
Thus. partly because the base width is small. the npn transistor can be considered a current amplifier at low frequencies. In other Holes V B E = 0. less than I 11m). but.27 The symbols representing [o] an npn bipolorjunction transistor and pnp bipolarjunction transistor. we consider here an npn transistor with the emitter connected to ground.7 V Emitter n' collector n" emitter Electrans p base . is small (typically. a much larger proportional current will flow from the collector to the emitter. We will see that when the baseemitter pn junction becomes forward biased. current will stall to flow from the base to the emitter. 1.28 Various components of the currents of an npn transistor. 1. (bl a region. the base must be more lightly doped than the emitter. VB' is less than about 0. . Basic Operation To understand the operation of bipolar transistors.28. and no current will flow. 1.3 V Depletion region Fig. 1. the transistor will be cut off. as we will see. Also.27. The circuit symbols used to represent npn and pnp transistors are shown in Fig. V CE > 0.44 Chapter 1 • IntegratedCireuit Devices and Modelling Collector Emitter Ie = ~IB '" 100Is (Typical) ~It Emitter (a) npn Ie = ~Is '" 201s (Typical if lateral) ~Ic Collector (b) pnp Fig. If the base voltage.5 V. as shown in Fig. W.
resulting in the ratio of the collector current to the base current being a constant that. the vertical base width. where they are now minority carriers. electrons) diffusing across the junction. Any of these minority electrons that get close to the collectorbase junction will immediately be "whisked" across the junction due to the large positive voltage on the collector. This independence ignores secondorder effects such as the decrease in effective base width. no holes from the base will go to the collector. is small. This ratio. and almost all of the electrons that diffuse from the emitter to the base reach the collectorbase junction and are swept across the junction. The base current. to a firstorder approximation. it starts to conduct. thus contributing to current flow in the collector. Typical values of ~ are between 50 and 200. determined by the hole current flowing from the base to the emitter. there are many more electrons injected from the emitter than there are holes injected from the base. Because the emitter is more heavily doped than the base. and the amount of this electron current is determined by the baseemitter voltage. A simplified overview of how an npn transistor operates follows: When the baseemitter junction becomes forward biased. if the transistor is not cut off and the collectorbase junction is reverse biased. The result is that the collector current very closely equals the electron current flowing from the emitter to the base. This scale current is proportional to the area of the baseemitter junction. However. the emitter current is approximately equal to the collector current. W. holes) and majority carriers from the emitter (in this case. due to the increase in the width of the collectorbase depletion . diffuse away from the baseemitter junction because of the minoritycarrier concentration gradient in the base region. the electrons that travel from the emitter to the base. is independent of voltage and current. a small base current controls a much larger collectoremitter current.25. similar to any forwardbiased junction. it can be shown (see Appendix at the end of this chapter) that the collector current is exponentially related to the baseemitter voltage by the relationship I C = I cs e VSE/VT (1.128) where Ie and 18 are the collector and base currents. 1. Since the collector current is approximately equal to the electron current flowing from the emitter to the base. which attracts the negatively charged electrons. Assuming the collector voltage is large enough so that the collectorbase junction is reverse biased.127) where I e s is the scale current. In a properly designed bipolar transistor. but since the hole current is much smaller than the electron current. W. The current consists of majority carriers from the base (in this case. is defined to be ~ " Ie 18  (1. Note that (1. is also exponentially related to the baseemitter voltage.collector voltage. The total emitter current is the sum of the electron collector current and the hole base current. typically denoted as ~.127) implies that the collector current is independent of the. The much smaller base current very closely equals the current due to the holes that flow from the base to the emitter.4 BipolarJunction Transistors 45 words.1. such as that shown in Fig.
3V Fig. with a typical value being from 50 V to 100 V. The intercept voltage value. A largesignal model of a BJT operating in the active region is shown in Fig. . a typical plot of the collector current. V A. the dependence is linear with a slope that intercepts the VCE axis at V CE = VA for all values of Is.29 Typical plat of I c versus VCE for a BJT. 1.46 Chapter 1 • IntegratedCircuit Devices and Modelling Transistor breakdown region V CEsat == O. 1. Such a collectoremitter voltage is required to ensure that none of the holes from the base go to the collector.30 A largesignal model for a BJT in the active region. This dependency results in a finite output impedance (as in a MOS transistor) and can be modelled by modifying equation (1. 1. The fact that the curves are not flat for VCE > VCEsa! indicates the dependence of I c on VCEo Indeed. to a good approximation.129) LargeSignal Modelling A conducting BJT that has a VCE greater than VCEsa! (which is approximately 0. region when the collector bias voltage is increased. for different values of Is is shown in Fig. as a function of collectortoemitter voltage.127) [Sze. Fig. To illustrate this point.29 for a practical transistor. 1.30. is called the Early voltage for bipolar transistors.3 V) is said to be operating in the active region.j981] to be VIC = Icse VBe/V'(1 + CE) VA (1. Ic. VCE.
1. This additional modelling of the finite output impedance is normally not done in largesignal analysis without the use of a computer due to its complexity. ~Is. 1.. It should be noted that the value of V CEsa' decreases for smaller values of collector current.135) where VA is the Earlyvoltage constant.131) (1.V.130) which is similar to a diode equation. but with a multiplying constant of Ics/~ = Iss· Since IE = Is + Ic . and holes from the base will begin to diffuse to the collector. the basecollector junction becomes forward biased. I.132) where u has been defined as u= ~ ~+I (1. is shown in Fig.1.2 to 0. we have ~ + I.133) and for large values of ~.3V + Fig.3 V).31. can be approximated as u=I=1 ~ I (1. As the collectoremitter voltage approaches VCEsa' (typically around 0. Ic ~Vc_ VCEsa. we have Is = Ics e V"IV = T ~ (1.134) If the effect of VCE on Ic is included in the model. when the transistor is saturated or in the saturation region.4 BipolarJunction Transistors 47 Since Is = Ic/~./V T I CS ~or equivalently ( _  I ESe V"IVT (1. A common model for this case. should be replaced by a current source given by I c = ~Is ( I + VA VCE)_ (1. the currentcontrolled source. = O.31 A largesignal model for a BJT in the soturo . tlon region.
Dur . in the lightly doped region of the collector. first the base current will reverse.epitaxial region of the collector to the n" collector region. BaseCharge Storage of a Saturated Transistor When a transistor becomes saturated. and can often be ignored.epitaxial region is so named because it is epitaxially grown on a p region. in saturation. Also. however. Thus. before the collector current will change. Cd' between the base and emitter given by (see Appendix at the end of this chapter) ( 1. C j is much less than Cd' unless the transistor current is small. C j . will include the baseemitter depletion capacitance.137) where the base overdrive current. and continuing on through the lightly doped n. Is » Ie/~. Most of the charge storage occurs in this region. Normally. Qs' must be removed. Qb' will be removed. and (1. After Q s is removed. ~E (ignoring the storage of electrons in the base that diffused from the collector). but this charge is normally smaller. is approximately equal to the hole current from the base to the collector. C be .136) where ~b is the basetransittime constant.Ie/~. the constant ~s is normally much larger than the base transit time. in parallel with Cd' Normally. through the collector junction. Recall that this minority charge is responsible for Ie. we see that the diffusion capacitance is proportional to Ie. increases drastically. defined to be Is . The major component of this charge storage is due to holes diffusing from the base. the saturation charge. even more so. the base minority charge. When a saturated transistor is being turned off. The total baseemitter capacitance.48 Chapter 1 • IntegratedCircuit Devices and Modelling BaseCharge Storage in the Active Region When a transistor is in the active region. the constant ~b' often by up to two orders of magnitude. The n. additional charge storage occurs because electrons that diffused from the collector are stored in the base. The specific value of ~s is usually found empirically for a given technology. the minoritycharge storage in the base and. The magnitude of the additional charge stored by a transistor that is saturated is given by (1. many minority carriers are stored in the base region (electrons are stored in an npn transistor). so this charge must be removed (through the base contact) before a transistor can turn off.137) can be approximated by (1.138) The constant ~s is approximately equal to the epitaxialregion transit time. However. As in a forwardbias diode. Since the epitaxial region is much wider than the base. this charge can be modelled as a diffusion capacitance.
In ISR+ IS] Ie [I SR+ 13 (1. 1:.13 For 1:b = 0. calculate the time required to remove the base saturation charge using (1.139). to avoid the long turnoff time that would result. the time required to remove the storage charge of a saturated transistor is much larger than the time required to turn off a transistor in the active region.140). Is. EXAMPLE 1. the time to remove as greatly dominates the overall charge removal. Solution Using (1. is much shorter than the epitaxialregion transit time. the expression in (1. one never allows bipolar transistors to saturate. Is = 0. 19881 I. In both of the cases just described. In highspeed microcircuit designs. we have I .1. and I SR = I rnA.140) is approximately equivalent to the much simpler one in (1.139). Typically. ~ as ISR  ~.2 rnA. 19881 Is = ~. the tumoff time for this case. If the reverse base current (when the saturation charge is being removed). LE' then one can derive a simple expression for the time required to remove the saturation charge.)_ ISR ~ Is 'I B R ( 1.(IB_I. the tumoff time of the BJT would be so slow as to make the circuit unusable in most applications.3 = 20 ns (1. I sR.  10. If the time required to remove the base saturation charge. In this case. remains constant while as is being removed. the collector current will decrease until the transistor shuts off. the forward base current during saturation.139). Nevertheless.4 BipolarJunction Transistors 49 ing this time. Ie = I rnA.139) where ~s " ~E' Normally. will be much smaller than the reverse base current during saturationcharge removal. = 100 ns (a small value for 1:s). then we have [Hodges. then our original assumption that Is « ~E " ~s would not be true. denoted by I SR. Compare these results to the time required to remove the base minority charge for the same I SR. and compare it to the time obtained using the more accurate expression of (1.2 ns. f3 = 100.l40) The reader should verify that for IsR» Is and I sR» Ie/~.141) . Is. If this were not the case.7 (2 x 104 ) 10. when Is is not much less than ~E' is given by [Hodges.
except it includes a finite baseemitter impedance.' Thus.142) which is fairly close to the first result.140). r.144) Base Vb rb c.50 Chapter 1 • IntegratedCircuit Devices and Modelling Using (1. The time required for an active transistor to remove the base minority charge.2 ns (1. The hybridit model is shown in Fig. 1.32. Vb.143) This is approximately 100 times shorter than the time for removing the base saturation charge! SmallSignal Modelling The most commonly used smallsignal model is the hybridit model. Ie' to the smallsignal baseemitter voltage.32 The smallsignal model of an active BJT. and then we will discuss the parasitic capacitances. The transistor transconductance. This model is similar to the smallsignal model used for MOS transistors. +ro ie Collector Ve :+ tb Cbe +v  be 9mvbe I C " "'i e ve Emitter Fig. Qb.. As in the MOS case. we have 17. r. ale aV SE (1. we have Ie 9m = =  Vb. 9m' is perhaps the most important parameter of the smallsignal model. 1. we will first discuss the transconductance.. and it has no emittertobulk capacitance. . The transconductance is the ratio of the smallsignal collector current. 9m' and the smallsignal resistances. is given by (1.
In integratedcircuit design.lSI) Using (!.150) we therefore have fIT = alB aV B E (!. so the bias currents are usually made proportional to absolute temperature (since VT is proportional to absolute temperature).l4S) again.lSO) again.147) where VT is given by (1.146) (1. it is important that the transconductance (and hence speed) remain temperature independent. we have (!.153) Since (!.130) we have (1.l4S) Then 9m = Using (!.4 BipolarJunction Transistors 51 Recall that in the active region (!. The presence of the resistor fIT reflects the fact that the base current is nonzero. we obtain (1.1. the transconductance is proportional to the bias current of a BJT. Thus. (1.lS2) or equivalently.lS4) .149) Because from (1.148) and is approximately 26 mY at a room temperature of T 300 "K. We have (1.
we have aVSE alE . use the emitter resistance. This constant is usually between 2. .52 Chapter 1 • IntegratedCircuit Devices and Modelling we also have = + at. although small (typically a few hundred ohms). '0' models the dependence of the collector current on the collectoremitter voltage. note that 9m'0 = VA/VT is a constant value independent of the transistor operating point.000 for an npn BIT and is an upper limit on the attainable voltage gain for a singletransistor amplifier. Repeating (1. o  (1. 1.129) hen: for convenience.155) = 9 = (~) ~ 9m C< Some alternative models.000 and 8. This resistor.where 'e = Continuing.25).159) Thus.156) '0 = al c aVCE (1.= C< 9m (1. The resistor rb models the resistance of the semiconductor material between the base contact and the effective base region due to the moderately lightly doped base p material (see Fig.157) The smallsignal resistance. As an aside. can be important in limiting the speed of veryhighfrequency lowgain BJT circuits and is a major source of noise. usually called T models (see page 55). re. I c = Icse V"/VT(1 + ~CAE) we have (1. . aVSE aVSE = 9m + m 9m 13 (1.158) ( 1. ar.160) which is inversely proportional to the collector current.
we have (1. p= 100. This is one of the reasons why it is possible to realize a singletransistor BJT amplifier with a much larger gain than would result if a MOS transistor were used.= . in Section 1.167) The diffusion capacitance. fe' f o' and Solution We have 9m =  Ie VT = lOx 10' A 0.136) as . it can be shown that the maximum gain decreases with larger bias currents in a squareroot relationship. Also note that this BJT maximum gain is independent of the bias current.6 kQ ( Ll62) fe a 9m = C p 6 = 25.7 Q 101 100 10' O O ( Ll63) f = . For MOS transistors. Recapping. The highfrequency operation of a BJT is limited by the capacitances of the smallsignal model. especially at high current levels (and therefore at high frequencies).166) biased junction. C be . a rough approximation for C j is where Ci is the depletion capacitance of the baseemitter junction. We have already encountered one of these capacitances. is given by (Ll65) Note that this gain is much higher than the 52. For a forwardCJ = 2A EC j eO (1.026 Y = = 385 mA/Y (Ll61) fn p 9m = 2.4 BipolarJunction Transistors 53 EXAMPLE 1. calculate 9m' f n.1. and V A = 100 Y.= 100kQ o VA Ie (LIM) and gmro' the maximum possible gain with a singletransistor amplifier.9.6 that was found for a single MOS transistor in Example 1.14 For Ie = gm ro· I rnA.. Cd' is given in (1.1.
Ac. 1.168) The capacitor. A common indicator for the speed of a BIT is the frequency at which the transistor's current gain drops to unity. "'co' the builtin potential for the collectorbase junction. CCS' which is the depletion capacitance that results from this area. when its collector is connected to a smallsignal ground. It should be noted that the crosssectional area of the collectorbase junction.172) . which is shown in Fig.9 V).169) where Ac is the effective area of the collectorbase interface.33. despite the lower doping levels. This size differential results in Ac C jCO being larger than AE Cjeo.171) and ( 1. This frequency is denoted It and is called the transistor unitygain frequency.. AE . C cb . Finally. Due to the lower doping levels in the base and especially in the collector (perhaps 22 5 x 10 acceptors/m' and 102 1 donors/rrr'. Cj . the baseemitter junction capacitance at 0 V bias. 1. respectively). Since this is a graded junction.170) where AT is the effective transistor area and C jSO is the collectortosubstrate capacitance per unit area at 0V bias voltage.25. Since this area is quite large. We can see how this frequency is related to the transistor model parameters by analyzing the smallsignal circuit of Fig. is typically much larger than the effective area of the baseemitter junction. we can approximate C eb by ACC jeo c. will be much larger than either C eb or the depletion capacitance component of C be. will be less than that of the baseemitter junction (perhaps 0. The value of C es can be calculated using 1 + VC8)1I2 ( "'so (1. the resislor rb is ignored because it has no effect on ib since the circuit is being driven by a perfect current source. We have (1. models the depletion capacitance of the collectorbase junction. another large capacitor is C es' the capacitance of the collectortosubstrate junction.54 Chapter 1 • IntegratedCircuit Devices and Modelling (1.75 V as opposed to 0. In the simplified model in part b. that is. = (1 + V CBJ1I3 "'co (1.
1.4
ib
BipolarJunction Transistors
55
,1 1 1 'I'. ····f 'f 1 ,1 1+ '! I I ····n
+
"I'll
'b Cbel
COb
+
i,
1
II
COOl
(a)
ib
i,
+
+
Cbe
COb
Vbe
(b)
Fig. 1.33 (a) A smallsignal model used to find 1,; (b) an equivolent simplified model.
Solving for ie / ib gives (1.173) At low frequencies, the current gain is 9mfrr' which equals the expected value of ~ (using (1.153))_ At high frequencies, ie / ib is approximately given by ie 9m frr 9m  (w )I ~ = ,::=,,::,  w(C be + Ceb)f rr ib w(C be + C eb) l (1.174)
To find the unitygain frequency, we set ICie/ib)(wt)1 = I and solve for Wt, which results in (1.175) or It = 9m 2it(C be + C eb) (1.176)
Often, either It, COt. or 'tt = 1/ COt will be specified for a transistor at a particular bias current. These values indicate an upper limit on the maximum frequency at which the transistor can be effectively used. The hybridit model is only one of a number of smallsignal models that can be used. One common alternative is the lowfrequency T model shown in Fig. 1.34. Use of this T model often results in a much simplified analysis. compared to use of the hybridit model, and thus it is useful for hand analysis.
56
Chapter 1 • IntegratedCircuit Devices and Modelling
rb
V b o~'\Iv'
v,
1.5 DEVICE MODEL SUMMARY
Fig. 1.34
A lowfrequency, smallsignal T
model for an active BJT.
As a useful aid, all of the equations for the largesignal and smallsignal modelling of diodes, MOS transistors, and bipolar transistors, along with values for the various constants, are listed in the next few pages.
Constants
19 q = 1.602 X 10 C
n,
= 1.1 x 10 16 carriers/m 3 at T = 300
x

I 23 k = 1.38 X 10 JK
Eo ::; 8.854 x·IOK s  11.8
12
F/m
Ko, 
3.9
flo = 0.05 m'/Y· s
Diode Equations
ReverseBiased Diode (Abrupt Junction) Cj =
flp = 0.02 m 2/Y· s
c.,
R
Q = 2C jo4>o
1+4>0 C IO = ~
R
1
I+4>0
C jG =
qKsE o NoNA
~ 24>0
qKsEaN o 'fN
24>0
NA+ No
A»
N
D
4>0 = kT
q
In(NA~O J
n,
1.5
Device Model Summary
57
ForwardBiased Diode
10 = se
I
VD/V T
o, D Is = Aoqn ,(  +  i LnN A LpN o
kT
p)
VT
= 
q
 26 mY at 300 OK
SmallSignal Model of ForwardBiased Diode
rd = 10
VT
10
C T = Cd+C j
Cd = ' T 
C j = 2C ,o 
VT
'T = 
L' n Dn
MOS Transistor Equations
The following equations are for nchannel devicesfor pchannel devices, put negative signs in front of all voltages. These equations do not account for shortchannel effects (i.e., L < 2L min ) .
Triode Region ( VGS > V,", V DS:S V.,,)
58
Chapter 1 • IntegratedCircuit Devices and Modelling
GlF =
kT ,:;;q In (N
A)
Y=
j2qK"EoN A
Cox
Cox =
tax Ve,,)
Kox£o
SmallSignal Model in Triode Region (for Vos«
Vg
ros
V,
ot_......JV\rto
Vd
rds
=
 1
~nCox(~)v elf
Cio(A, + WLI2) C'b = Cdb =
c.,
1 = Cgs  2WLCox + WLovCox
H
1+<Po
Active (or PinchOff) Region ( VGS > V
,n, VOS ;:' Volf)
~nCoxW , 10 =    (VGSV,nrll +A(VOSVelf)] 2 L
A=
1 L jvos  Velf + <Po
V,n = V,n_ O + y(jV SB+ 2GlF  j2GlF)
Velf = VGSV,n =
210
~~nCoxW/L
1.5
Device Model Summary
59
SmallSignal Model (Active Region)
Cg,

I I
9m Vgs
:4l
9svs ~
~
Foe <>
CdbI

v
9m =
l!'Cox(~)V eff

9m = J2l!,C ox(W/L)I o Y9m 2JV ss + 2 <1> FI
1
9m =
210 Veff
I
9s = 9s
krds
r ds =
= 0.29m
A.I o

A.=
2LJVos  Veff + <1>0 2 C gS = 3WLCox + WLovC ox C Sb = (As + wuc, + P sCisw
s O krds = J2K E qN A C gd = WLovC ox C jO JI + Vss/<1>o
CIS =
C db = AdCjd + P dCj.sw
C ld =
C jO JI +Vos/<1>o
Typical Values for a O.8!,m Process
VI' = 0.8 V
VIp = 0.9 V
60
Chapter 1 • IntegratedCircuit Devices and Modelling
Co,
=
1.9 x 10
X
3
pF/(llm)
2
Cj CgS(Overlap)
= 2.4 X
104 pF/(llm)2
C j_sw = 2.0
10 pF/llm
4
= 2.0 X 104 pF/llm = 0.9
Y
<\IF = 0.34 Y
Y = 0.5 y
'/ 2
<1>0
t ox = 0.02
urn
Ns = 6 X 1021 impurities/m 3
BipolarJunction Transistors
Active Transistor
Ie
VsE/VT I = ese
V
T
= kT
q
T (
 26 mY at 300 oK
For more accuracy, Ie
= lese V"/V I + ~eAE)
 Is
les
= WN A
AEqD,n;
=
Ie
~
IE
= (1+~)Ie = Ie = (~+l)Is a
a
I
~ ~
= =
Is
Ie
D,NDL p DpNAW
= 2.5
NDL p NAW
=
1+~
SmallSignal Model ofan Active BiT
Base
Vb
oJVIrf.....~ 1~___1~'o
+
i,
Collector
V,
I l
!
I
1.6
SPICEModelling Parameters
61
gm = fe
Ie VT
fIT
==
VT Is VA Ie
= P
gm
== 
a
fo
gm
gmro
VA VT
Cd
= 'b = gm'b V
T ATC;so (1 + Vest' <P so
Ie
c., = C1+C d
c., =
AeC;eo
c., =
(1+Vest'
<Pea
1.6 SPICEMODELLING PARAMETERS
This section briefly describes some of the important model parameters for diodes, bipolar transistors, and MOS transistors used during a SPICE simulation. It should be noted here that not all SPICE model parameters are described. However, enough are described to enable the reader to understand the relationship between the relative parameters and the corresponding constants used when doing hand analysis.
Diode Model
There are a number of important dc parameters. The constant Is is specified using either the parameter IS or JS in SPICE. These two parameters are synonyms, and only one should be specified. A typical. value specified for Is might be between 1018 A and 10 15 A for small diodes in a microcircuit. Another important parameter is called the emission coefficient, n. This constant multiplies VT in the exponential diode IV relationship given by
(1.177)
The SPICE parameter for n is N and is defaulted to I when not specified (I is a reasonable value for junctions in a microcircuit). A third important de characteristic is the series resistance, which is specified in SPICE using RS. It should be noted here that some SPICE programs allow the user to specify the area of the diode, whereas
62
Chapter 1 • lnteqrutedCircuit Devices and Madelling
others expect absolute parameters that already take into account the effective area. The manual for the program being used should be consulted. The diode transit time is specified using the SPICE parameter IT. The most important capacitance parameter specified is CJ. CJO and CJ are synonymsone should never specify both. This parameter specifies the capacitance at 0 V bias. Once again, it may be specified as absolute or as relative to the area (i.e., F/m'), depending on the version of SPICE used. Also, the area junction grading coefficient, MJ, might be specified to determine the exponent used in the capacitance equation. Typical values are 0.5 for abrupt junctions and 0.33 for graded junctions. In some SPICE versions, it might also be possible to specify the sidewall capacitance at 0 V bias as well as its grading junction coefficient. Finally, the builtin potential of the junction, which is also used in calculating the capacitance, can be specified using PB. PHI, VJ, and PHA are all synonyms of PB. Reasonably accurate diode simulations can usually be obtained by specifying only IS, CJ, MJ, and PB. However, most modem versions of SPICE have many more parameters that can be specified if one wants accurate temperature and noise simulations. Users should consult their manuals for more information. Table 1.1 summarizes some of the more important diode parameters. This set of parameters constitutes a minimal set for reasonable simulation accuracy under ordinary conditions.
MOS Transistors
Modem MOS models are quite complicated, so only some of the more important MOS parameters used in SPICE simulations are described here. These parameters are used in what are called the Level 2 or Level 3 models. The model level can be chosen by setting the SPICE parameter LEVEL to either 2 or 3. The oxide thickness, t ox ' is specified using the SPICE parameter TOX. If it is specified, then it is not necessary to specify the thin gateoxide capacitance (COX' specified by parameter COX). The mobility, ~n' can be specified using DO. If DO is specified, the intrinsic transistor conductance (~nCox) will be calculated automatically, unless this automatic calculation is overridden by specifying either KP (or its synonym, BETA). The transistor threshold voltage at V s = 0 V, V'n' is specified by VTO. The bodyeffect parameter, y,
Table 1.1 Important SPICE parameters far modelling diodes
Model Constant Brief Description
Transport saturation current Series resistance Diode transit time Capacitance at 0 V bias Diode grading coefficient exponent Builtin diode contact potential
SPICE
Parameter
IS RS
Typical Value
10 17 A
Is
Rd
30 Q 12 ps 0.01 pF 0.5 0.9V
TT
CJ MJ
'T
CiO
ill;
PB
<1>0
1.6
SPICEModelling Parameters
63
can be specified using GAMMA, or it will be automatically calculated if the substrate doping, NA , is specified using NSUB. Normally, one would not want SPICE to calculate y because the effective substrate doping under the channel can differ significantly from the substrate doping in the bulk due to thresholdvoltage adjust implants. The output impedance constant, A, can be specified using LAMBDA. Normally, LAMBDA should not be specified since it takes precedence over internal calculations and does not change the output impedance as a function of different transistor lengths or bias voltages (which should be the case). Indeed, modelling the transistor output impedance is one of weakest points in SPICE. If LAMBDA is not specified, it is calculated automatically. The surface inversion potential, 12'i>F1, can be specified using PHI, or it will be calculated automatically. Another parameter usually specified is the lateral diffusion of the junctions under the gate, LD, which is specified by LD. For accurate simulations, one might also specify the resistances in series with the source and drain by specifying RS and RD (typically only the source resistance is important). Many other parameters exist to model such things as shortchannel effects, subthreshold effects, and channelwidth effects, but these parameters are outside the scope of this book. The modelling of parasitic capacitances in SPICE is quite involved. Originally, this modelling was not very accurate since it did not include charge conservation for the gate charge. However, this modelling has greatly improved in recent commercial versions of SPICE. The capacitances under the junctions per unit area at 0V bias, (i.e., CIO) can be specified using CJ or can be calculated automatically from the specified substrate doping. The sidewall capacitances at 0 V, C Iswo, should normally be specified using CJSW because this parameter is used to calculate significant parasitic capacitances. The bulk grading coefficient specified by MJ can usually be defaulted to 0.5. Similarly, the sidewall grading coefficient specified by MJSW can usually be defaulted to 0.33 (SPICE assumes a graded junction). The builtin bulktojunction contact potential, <Po, can be specified using PB or defaulted to 0.8 V (note that 0.9 V would typically be more accurate, but the resulting simulation differences are small). Sometimes the gatetosource or drainoverlap capacitances can be specified using CGSO or CGDO, but normally these would be left to be calculated automatically using COX and LD. Some of the more important parameters that should result in reasonable simulations (except for modelling shortchannel effects) are summarized in Table 1.2 for both n and pchannel transistors. Table 1.2 lists reasonable parameters for a typical 0.8l.lm technology.
Bipolar Junction Tronsistors
For historical reasons, most parameters for modelling bipolar transistors are specified absolutely. Also, rather than specifying the emitter area of a BJT in (I.lm)' on the line where the individual transistor connections are specified, most SPICE versions have multiplication factors. These multiplication factors can be used to automatically multiply parameters when a transistor is composed of several transistors connected in parallel. This multiplying parameter is normally called M.
64
Chapter 1 • IntegratedCircuit Devices and Modelling
Table 1.2 A reasonable set of MOS parameters for a typical O.8~m technalogy SPICE
Parameter
Model Constant
Brief Description
Transistor threshold voltage (in V)
Typical Value
0.7:0.9 500: 175 1.8 x 10' 6 x 10' 0.5: 0.8 3 x 10":7.5 x 10" 0.7 0.9
) 2
VTO UO TOX
v,»;
~":~p
Carrier mobility in bulk (in
cm 2tV os)
01)
to,
Thickness of gate oxide (in
LD
GAMMA NSUB PHI PB CJ CJSW MJ MJSW
LD
y
Lateral diffusion of junction under gate (in m) Bodyeffect parameter The substrate doping (in cm 3 ) Surface inversion potential (in V) Builtin contact potential of junction to bulk (in V) Junctiondepletion capacitance at OV bias (in F/m Sidewall capacitance at 0 V bias (in F/m) Bulktojunction exponent (grading coefficient) Sidewalltojunction exponent (grading coefficient)
NA:N D
12 $ FI
<1>0
GjO
C j _S W ()
2.5 x 1()':4.0 x 104
2.0 x 10 10:2.8 x 10.10
m
j
0.5 0.3
m J sw
The most important dc parameters are the transistor current gain. ~, specified by the SPICE parameter BF; the transistortransport saturation current. I e s, specified using the parameter IS; and the Earlyvoltage constant. specified by the parameter VAF. Typical values for these might be 100, 10'" A, and 50 V, respectively. If one wants to model the transistor in reverse mode (where the emitter voltage is higher than the collector voltage for an npn), then one might specify BR, ISS, and VAR, as well; these are the parameters that correspond to ElF, IS, and VAF in the reverse direction. Typically, this reversemode modelling is not important for most circuits. Some other important dc parameters for accurate simulations are the base, emitter, and collector resistances. which are specified by RB, RE. and RC, respectively. It is especially important to specify RB (which might be 200 0 to 500 0), The important capacitance parameters and their corresponding SPICE parameters include the depletion capacitances at 0V bias voltage, CJE, CJC. CJS; their grading coefficients. MJE, MJC, MJS: and their builtin voltages, VJE, VJC, YJS, for baseemitter, basecollector, and collectorsubstrate junctions. Again, the 0 Y depletion capacitances should be specified in absolute values for a unitsized transistor. Normally the baseemitter and basecollector junctions are graded (i.e., MJE, MJC = 0,33), whereas the collectorsubstrate junction may be either abrupt (MJS = 0.5) or graded (MJS = 0.5). depending on processing details. Typical builtin voltages might be 0,75 Y to 0.8 V. In addition, for accurate simulations. one should specify the forwardbase transit lime, 'F, specified by TF. and. if the transistor is to be operated in reverse mode or under saturated conditions, the reversebase transit time, 'tR, specified by TR. The most important of the model parameters just described are summarized in Table 1.3. Once again, many other parameters can be specified if accurate simulation is desired. Other parameters might include those to model ~ degradation under high or
1.7
Table 1.3 The mast impartant SPICE paramelers far madelling BJTs
Appendix
65
SPICE
Parameter
Model Constant
Brief Description
Transistor current gain in forward direction Transport saturation current in forward direction
Typical Valne 100 2 x 1018 A 50Y 500 Q 30 Q O.oI5 pF 0.018 pF 0.040pF 0.30 0.35 0.29 12 ps
4
TIS
BF ISS YAF RB
RE
p
Ics
VA
rb
Early voltage in forward direction
Series base resistance Series emitter resistance Baseemitter depletion capacitance at 0 V
RE
Cjeo
Cjao Cjao
CJE CJC CJS MJE MJC MJS TF TR
Basecollector depletion capacitance at 0 V
Collectorsubstrate depletion capacitance at 0 V Baseemitter junction exponent (grading factor) Basecollector junction exponent (grading factor) Collectorsubstrate junction exponent (grading factor)
me me m,
'F
Forwardbase transit time
Reversebase transit time
'R
low current applications and parameters for accurate noise and temperature analysis. Readers should refer to their SPICE manuals for descriptions of these parameters.
1.7 APPENDIX
The purpose of this appendix is to present derivations for device equations that rely heavily on device physics knowledge. Specifically, equations are derived for the exponential relationship and diffusion capacitance of diodes, for the threshold voltage and triode relationship for MOS transistors, and for the exponential relationship and base charge storage for bipolar transistors.
Diode Exponential Relationship
The concentration of minority carriers in the bulk, far from the junction, is given by Eqs. (1.2) and (1.4). Close to the junction, the minoritycarrier concentrations are much larger. Indeed, the concentration next to the junction increases exponentially with the external voltage, Vo, that is applied in the forward direction. The concentration of holes in the n side next to the junction, p., is given by [Sze, 1981]
Pn =
( 1.178)
Similarly, the concentration of electrons in the P side next to the junction is given by
66
Chapter 1 • IntegratedCircuit Devices and Modelling
n, Vo/VT = e
o
NA
(1.179)
As the carriers diffuse away from the junction, their concentration exponentially decreases. The relationship for holes in the n side is
Pn(X) = Pn(O)e
xvL
c
(1.180)
where X is the distance from the junction and Lp is a constant known as the diffusion length for holes in the n side. Similarly, for electrons in the P side we have (1.181) where Ln is a constant known as the diffusion length of electrons in the P side. Note that Pn (0) and np (0) are given by (1.178) and (1.179), respectively. Note also that the constants Ln and Lp are dependent on the doping concentrations N A and N D, res peelively. The current density of diffusing carriers moving away from the junction is given by the wellknown diffusion equations [Sze, 1981J. For example, the current density of diffusing electrons is given by dnp(x) qD  n dx (1.182)
where Dn is the diffusion constant of electrons in the P side of the junction. The negative sign is present because electrons have negative charge. Note that Dn = (kT /q)~n' where u, is the mobility of electrons. Using (1.181), we have (1.183) Therefore (1.184) Thus, the current density due to diffusion is proportional to the minoritycarrier concentration. Next to the junction, all the current flow results from the diffusion of minority carriers. Further away from the junction, some of the current flow is due to diffusion and some is due to majority carriers drifting by to replace carriers that recombined with minority carriers or diffused across the junction. Continuing, we use (1.179) and (1.184) to determine the current density next to the junction of electrons in the P side:
qD nn (0) Ln p
(1.185)
1.7
Appendix
67
For the total current of electrons in the p side, we multiply (1.185) by the effective junction area, AD' The total current remains constant as we move away from the junction since, in the steady state, the minority carrier concentration at any particular location remains constant with time. In other words, if the current changed as
we moved away from the junction, the charge concentrations would change with
time.
Using a similar derivation, we obtain the total current of holes in the n side, I D . p, as
ADqDnnj VD/V T I o.p = ::: e LpN D
,
(1.186)
where On is the diffusion constant of electrons in the p side of the junction, Lp is the diffusion length of holes in the n side, and ND is the impurity concentration of donors
in the n side. This current, consisting of positive carriers, flows in the direction oppo
site to that of the flow of minority electrons in the p side. However, since electron carriers are negatively charged, the direction of the current flow is the same. Note also that if the p side is more heavily doped than the n side, most of the carriers will be holes, whereas if the n side is more heavily doped than the p side, most of the carriers will be electrons. The total current is the sum of the minority currents at the junction edges:
I =A
D
Dq, L N
n2(~ + 2}V L N
nAp 0
D/V,
(1.187)
Equation (1.187) is often expressed as
I D  I se where
VD/V,
o,
(1.188)
Is =
On ADqn,,(  +  
J
LnN A
LpN D
(1.189)
Equation (1.188) is the wellknown exponential currentvoltage relationship offorwardbiased diodes.
The concentrations of minority carriers near the junction and the direction of cur
rent tlow are shown in Fig. 1.35.
DiodeDiffusion Capacitance
To find the diffusion capacitance, Cd' we first find the minority charge close to the junction, ad' and then differentiate it with respect to VD. The minority charge close to the junction, ad' can be found by integrating either (1.180) or (1.181) over a few diffusion lengths. For example, if we assume npo , the minority electron concentration in the p side far from the junction is much less than np(O), the minority electron con
68
Chapter 1
•
IntegratedCircuit Devices and Modelling
Direction of positive current
Hole
~
•
diffusion
Po
n, Immobile charge
n,(O)
Electron diffusion
Po(O)
p,(O)e Poo xp
x IL
p p
.
P
•
n po
+ + + +
"
+ + + +
+ + + +
J
np(o)eX,/L,
n P side
1
f
n side
x,
Depletion region
Fig. 1.35 The concentration of minority carriers and the direction of diffusing carriers near a forwardbiased junction.
!
t
t
centration at the junction edge, we can use (1.181) to obtain
o,
= qADI; np(x) dx = qA o o np(O)e = qAoLnnp(O)
f
e<>
X/L
_ "dx
(1.190)
Using (1.4) for np(O) results in (1.191)
In a similar manner, we also have
(1.192) For a typical junction, one side will be much more heavily doped than the other side, and therefore the minority charge storage in the heavily doped side can be ignored since it will be much less than that in the lightly doped side. Assuming the n side is heavily doped, we find the total charge, Qd' to be approximately given by Qn' the minority charge in the p side. Thus, the smallsignal diffusion capacitance, Cd' is given by (1.193) Using (1.187) and again noting that No» N A, we have
1.7
Appendix
69
(1.194) Equation (1.194) is often expressed as (1.195) where
~T
is the transit time of the diode given by
~T
= 
L' n Dn
(1.196)
for a singlesided diode in which the n side is more heavily doped.
MOS Threshold Voltage and the Body Effect
Many factors affect the gatesource voltage at which the channel becomes conductive. These factors are as follows:
1.
2.
The workfunction difference between the gate material and the substrate material The voltage drop between the channel and the substrate required for the channel to exist
its immobile charge, to exist
3. The voltage drop across the thin oxide required for the depletion region, with
4. The voltage drop across the thin oxide due to unavoidable charge trapped in the thin oxide The voltage drop across the thin oxide due to implanted charge at the surface of the silicon. The amount of implanted charge is adjusted in order to realize the desired threshold voltage.
5.
The first factor affecting the transistor threshold voltage, Vth , is the builtin Fermi potential due to the different materials and doping concentrations used for the gate material and the substrate material. If one refers these potentials to that of intrinsic silicon [Tsividis, 1987], we have
<PF.Gate
= 
kT In q n,
(NO)
(1.197)
for a polysilicon gate with doping concentration N D, and
<PF.S'b
=
kT q In(n;) N
A
(1.198)
for a p substrate with doping concentration NA . The workfunction difference is then given by
70
Chapter 1 • IntegratedCircuit Devices and Modelling
= kT In(NONAJ q n' ,
(1.199)
The next factor that determines the transistor threshold voltage is the voltage drop from the channel to the substrate, which is required for the channel to exist. The question of exactly when the channel exists does not have a precise answer. Rather, the channel is said to exist when the concentration of electron carriers in the channel is equal to the concentration of holes in the substrate. At this gate voltage, the channel is said to be inverted. As the gate voltage changes from a low value to the value at which the channel becomes inverted, the voltage drop in the silicon also changes, as does the voltage drop in the depletion region between the channel and the bulk. After the channel becomes inverted, any additional increase in gate voltage is closely equal to the increase in voltage drop across the thin oxide. In other words, after channel inversion, gate voltage variations have little effect on the voltage drop in the silicon or the depletion region between the channel and the substrate. The electron concentration in the channel is equal to the hole concentration in the substrate when the voltage drop from the channel to the substrate is equal to two times the difference between the Fermi potential of the substrate and intrinsic silicon, <PF' where
<PF
=
kT q In(N~ I nJ
(1.200)
Equation (1.200) is a factor in several equations used in modelling MOS transistors. For typical processes, <PF can usually be approximated as 0.35 V for typical doping levels at room temperature. The third factor that affects the threshold voltage is due to the immobile negative charge in the depletion region left behind after the p mobile carriers are repelled. This effect gives rise to a voltage drop across the thin oxide of QslCOX' where
Qs =
qNAxd
(1.201)
and x d is the width of the depletion region. Since
2K sEoI2<PFI
qNA
we have
(1.202)
(1.203) The fourth factor that determines Vln is due to the unavoidable charge trapped in the thin oxide. Typical values for the effective ion density of this charge, Nox' might be 2 x 10 14 to lOIS ions/rrr', These ions are almost always positive. This effect gives rise to a voltage drop across the thin oxide, Vox' given by
qN ox Vox =   =  Cox Cox
o.,
(1.204)
1.7
Appendix
71
The native transistor threshold voltage is the threshold voltage that would occur naturally if one did not include a special ion implant used to adjust the threshold voltage. This value is given by
Vtnative
(1.205)
A typical native threshold value might be around D. I V. It should be noted that transistors that have native transistor threshold voltages are becoming more important in circuit design where they might be used in transmission gates or in sourcefollower buffers. The fifth factor that affects threshold voltage is a charge implanted in the silicon under the gate to change the threshold voltage from that given by (1.205) to the desired value, which might be 0.7 V for an nchannel transistor. For the case in which the sourcetosubstrate voltage is increased, the effective threshold voltage is increased. This is known as the body effect. The body effect occurs because, as the sourcebulk voltage, VSB' becomes larger, the depletion region between the channel and the substrate becomes wider, and therefore more immobile negative charge becomes uncovered. This increase in charge changes the third factor in determining the transistor threshold voltage. Specifically, instead of using (1.203) to determine 0B' one should now use
(1.206)
, If the threshold voltage when V SB = 0 is denoted VtnD then, using (1.205) and (1.206), one can show that
( 1.207)
=
Vt no + r( JV SB + 2<1> F JI2<1>FI) I1
where
y=
J2qN AK s£ o
Cox
(1.208)
The factor y is often called the bodyeffect constant.
MOS Triode Relationship
The current flow in a MOS transistor is due to drift current rather than diffusion current. This type of current flow is the same mechanism that determines the current in a resistor. The current density, J, is proportional to the electrical field, E, where the constant of proportionality, o, is called the electrical permittivity. Thus,
J = crE
(1.209)
72
Chopter 1 • InlegroledCircuit Devices and Modelling
This constant for an ntype material is give n by
o = qn u,
where n is the concentration per unit volume of negative carriers and ity of electrons. Thus. the current density is given by
~n
(1.2 10) is the mobil(1.2 11)
Nex t, consider the current flow through the volume shown in Fig. 1.36. where the volume has height H and width W. The current is flowing perpendicular 10 the plane H x W down the length of the volume . L. The current. I. everywhere along the leng th of the volume is given by I=J W H (1.2 12)
The voltage drop along the length of the volume in the direction of L for a distance dx is denoted dV and is given by d V = E(x) d x Combining (1.211). (1.212). and (1.213). we obtain (1.213)
qu, WHn (x ) dV = I d x
(1.2 14)
where the carrier densi ty nIx) is now assumed to change a long the length L and is therefore a function of x. As an aside. we examine the case of a resistor where n (x ) is usually co nstant. A resistor of length L wou ld therefore have a curre nt give n by
=
q~ nWH
L
/' N
( 1.215)
Thus, the resistance is given by
R = :::co:
(1.2 16)
Unit volume
i
H
Fig. 1.36
~....t::::*===,,:;;1 J .,.
unit volume
Current flaw through
:=~~==:::;~~ w V L
?
Current Rowing through a unit volume.
1.7
Appendix
73
Often this resistance is presented in a relative mann er. in which the length and wid th are removed (since they can be des ign parame ters) but the height rem ains included . In this case. the resulting expression is commonly referred to as the resistance per square and design ated as R D where
(1.2 17)
The total resistance is then given by ( 1.218)
This equation is important when calculating the resis tance of interconnects used in integrated circ uits. In the case of a MOS transistor. the charge densi ty is not constan t down the chan nel. If. instead of the carrier density per unit volume, one expresses nIx) as a function of charge den sity per square area from the top looking dow n. we have
Qn(x) = qH n (x)
Su bstituting ( 1.219) into ( 1.214) results in
~ nWQ n< x )dV
( 1.2 19)
= I dx
( 1.220)
Eq uation ( 1.220) applies to dri ft current through any struc ture that has vary ing charge den sity in the directi on of the current llo w. It ca n also be applied to a MOS tran sistor in the triode region to derive its IV relation ship. It should be noted here that in this derivation. it is assum ed the sou rce vo ltage is the Mime as the substrate voltage. Sin ce the tran sistor is in the triod e region. we ha ve V DG <  Vtn . This requirement is eq uivalent to VDS < VGS  Vln = Veff . It is ass umed thai the effective channel length is L. Assum ing the vo ltage in the channel at distance X from the so urce is given by Vch (x), from Fig. 1.37. we have
Qn(x ) = C o,IVGS VC h(X) V'nl
Substituting ( 1.22 1) into ( 1.220) resu lts in
~ nWC o, [VG S Vch ( x ) Vt nldVC h = IDd x
( 1.22 1)
( 1.222)
v« = 0
o,« :
n+
Fig. 1.37
The tra nsistor definitions used in developing the transistor's IV relationship .
74
Chapter 1 • IntegratedCircuit Devices and Modelling
Integrating both sides of (1.222), and noting that the total voltage along the channel of length L is V DS' we obtain
r
!
f
o
VDS
~nWCox[VGSVch(x)VtnldVch =
fL
oIDdx
(1.223)
which results in
(1.224) Thus, solving for I D results in the wellknown triode relationship for a MOS transistor:
( 1.225)
It should be noted that taking into account the body effect along the channel, the triode model of (1.225) is modified to
(1.226) where a. _ 1.7 [Tsividis, 1987].
Bipolar Transistor Exponential Relationship
The various components of the base, collector, and emitter currents were shown in Fig. 1.28, on page 44. Figure 1.38 shows plots of the minoritycarrier concentrations
n" emitter
region
p" base region
b(O)
current
n" collector region
Electron
•
p,(O)
p
eO
,
OIl
Hole curren\ n
,
P
P
x
Fig. 1.38
=
0
"
W
The concentrations of minority carriers in the emitter, base, and collector.
1.7
Appendix
75
in the emitter, base, and collector regions. The current flow of these minority carriers is due to diffusion. By calculating the gradient of the minoritycarrier concentrations near the baseemitter junction in a manner similar to that used for diodes, it is possible to derive a relationship between the electron current and the hole current of Fig. 1.28. The concentration of holes in the emitter at the edge of the baseemitter depletion region is denoted Pe(O). This concentration decreases exponentially the farther one gets from the junction, in a manner similar to that described for diodes. The concentration far from the junction, peO, is given by
,
PeO
=
N
nj
(1.227)
o
where No is the doping density of the n" emitter. At a distance x from the edge of the emitterbase depletion region, we have Pe(x)
where
x/L = Pe(O)e '
(1.228)
,
= 8
nj
VsE/V T
(1.229)
No and where VBE is the forwardbias voltage of the baseemiuer junction. At the edge of the baseemitter depletion region, the gradient of the hole concentration in the emitter is found, using (1.228), to be dPe(x) I = dx X= 0 Using (1.229), we can rewrite this as (1.231) The hole current is now found using the diffusion equation
I pe = AEqD p dPe(x) I
(1.230)
( 1.232)
dx
x=o
where AE is the effective area of the emitter. Recall that the minorityhole current in the emitter, I pe, is closely equal to the base current, lB' After combining (1.231) and (1.232), we obtain (1.233)
76
Chapter 1 • IntegratedCircuit Devices and Modelling
The situation on the base side of the baseemitter junction is somewhat different. The concentration of the minority carriers, in this case electrons that diffused from the emitter, is given by a similar equation, ( 1.234) However, the gradient of this concentration at the edge of the baseemitter depletion region is calculated differently. This difference in gradient concentration is due to the close proximity of the collectorbase junction, where the minority carrier (electron) concentration, nb(W), must be zero. This zero concentration at the collectorbase junction occurs because any electrons diffusing to the edge of the collectorbase depletion region immediately drift across the junction to the collector, as stated previously. If the base "width" is much shorter than the diffusion length of electrons in the base, Ln, then almost no electrons will recombine with base majority carriers (holes) before they diffuse to the collectorbase junction. Given this fact, the decrease in electron or minority concentration from the baseemitter junction to the collectorbase junction is a linear relationship decreasing from nb(O) at the emitter junction to zero at the collector junction in distance W. This assumption ignores any recombination of electrons in the base as they travel to the collector, which is a reasonable assumption for modem transistors that have very narrow bases. Thus, throughout the base region, the gradient of the minoritycarrier concentration is closely given by
(1.235)
Combining (1.235) with the diffusion equation, we obtain
dnb(O)
AEqDn(j)(
(1.236)
Remembering that I n b is closely equal to the collector current Ie, we have
I C = I cs e VsE/VT
where
(1.237)
( 1.238) The ratio of the collector current to the base current, commonly called the transistor commonemitter current gain and denoted ~, is found using (1.237), (1.238), and
doping levels.237) and (1.239) explains why heavily doped emitters are important to achieve large current gain.240) Using (1. Base Charge Storage of an Active BJT Figure 1.233). equation (1. we have (1. is given approximately by (1. For example. the basetransit time constant is specified for a given technology and takes into account other chargestorage effects not considered here. 1990.243) ignoring secondorder effects. and D n = 2.238) to obtain o.234) for nb(O).239) which is a constant independent of voltage and current. Lp > W. We have (1. The derivation of ~ just presented ignores many secondorder effects that make ~ somewhat current and voltage dependent and are beyond the scope of this book.7 Appendix 77 (1.242).244) . = D i. we have 'T 'b' If the current in a BJT changes. A typical value might be between 50 and 200. given by (1. and base width. Noting that No » NA . the base charge storage must also change. = 'bIe 2 n W2 (1. Using (1. since the base storage of electrons dominates the other effects. Normally. This change can be modelled by a diffusion capacitance.1.239) does reflect the approximate relationships among ~. we have ~» 1. for more details.242) where 'tb' called the basetransit time constant. (1.5 Dp . and is therefore often denoted 'T' However. Qb. Regardless of secondorder effects. Cd' between the base and the emitter terminals.241) This equation can be rewritten using (1.38 shows a minoritycarrier storage in the base region. Interested readers should see Roulston. we have = (1.
Sunset Beach.5 V r ds (n) = 8000L (~m)/ID(mA) in active region C j = 2. New York.0 X 10. New York. S. New York. Sze. Y. M. John Wiley & Sons. Tsividis.245) This equation is similar to that for a diode. 1987. 3rd. Roulston. New York.p = 0.8 REFERENCES R. Physics of Semiconductor Devices. Gray and R.4 X 104 pF/(~m)2 4 C i sw = 2. 1.n • Cgs(OverlaPI = Cgdroverlap) 2. Geiger. Hodges and H.pF/(~m)2 • . McGrawHill. McGrawHill. Jackson. McflrawHill. = 'bli' T Ie (1. California. Allen.8 V '/ 2 Y = 0. Wolf. D.78 Chapter 1 • IntegratedCircuit Devices and Modelling Using (1.9 X 10. 1981. VLSl: Design Techniques for Analog and Digital Circuits. 1993.244) and Ie . P. 1995. Strader. P. Analog Integrated Circuits. Meyer.0 X 104 pF/~m pchannel MOS transistors: ~pCox = 30 ~A/V2 V. ed. 1988. assume the following hold throughout the problems section: • • Room temperature = 300 0 K npn bipolar transistors: 13 = 100 V A = 80 V 'b=13ps 1'5 = 4 ns r b = 330 n nchannel MOS transistors: ~nCox = 92 ~A/V2 V = 0.000 L (~m)/ID (rnA) in active region = . = lese VBE/V T results III c. Analysis and Design of Digital Integrated Circuits. Wiley Interscience.pF/~m 3 Cox = 1. and N.9 V Y = 0. Silicon Processing for the VLS/ EraVolume 3: The Submicron MOSFET. New York. D. 2nd ed.8 V ' / 2 r ds (n) = 12. Operation and Modeling of the MOS Transistor.9 PROBLEMS Unless otherwise stated. Semiconductor Devices. 1990. S. New York. Lattice Press. 1990. G. 1. McGrawHill.
1 1. A.70 % time).9 Derive the lowfrequency model parameters for an nchannel transistor having 25 22 doping concentrations of No = 10 and NA = 10 with W = I0 urn . L = 1. estimate the new value of 10 if Vos is increased by 0.9 X 10. Estimate the time it takes for the output voltage to change from 5 V to 1. P1. and then at time 0 it changes to 0 V.1. PIA. does the builtin potential.pF/(~m)2 C9sloverlapj 4 .8 AMOS transistor in the active region is measured to have a drain current of 20 ~A when Vos = Veff. <Po.e.5 V.3 Estimate the hole and electron concentrations in silicon doped with arsenic at a 25 3 concentration of 10 atoms/m at a temperature 22°C above room temperature. Initially.0 X 10.t.2. 1. the input is 5 V.7 Find 10 for an nchannel transistor having doping concentrations of 22with 25 No = 10 and NA = lO W = 50 urn .4 1.1 V. Assuming A remains constant. Problems 79 = CgdlOverlaPl = 2.2 urn . and Vos = Veff. increase or decrease when the temperature is increased] 1 °C above room temperature? 1.5 Compare your answers for Problem 104 to those obtained using a SPICE simulation.5 X 10 pF/(~m) 4 C j _sw = 2.6 Verify that when Vos = Veff is used in the triode equation for a MOS transistor. and Vos = Veff. VGS = 1. 1. When Vos is increased by 0. Estimate the output impedance.. . VGS = 1. Repeat for an input voltage change from 0 V to 5 V and an output voltage change from 0 V to 3. How much charge on each side would be present in a 10 urn X 10 urn diode? A silicon diode has 1. the current equals that of the active region equation given in (1. the t>. It is biased by a 43k£! resistor connected between the cathode of the diode and the input signal.0 V.1 V.67). 10 increases to 23 ~A .3 V . as shown in Fig.5 um .5 V (i. 1. Is the resulting material n type or p type? For the pn junction of Example 1. rds ' and the output impedance constant.2 for a 5V reversebias voltage.5 V.5 X 10 pF/~m 3 Cox = 1.4 Calculate the amount of charge per (~m)' in each of the nand p regions of the pn junction of Example 1. R o'V\r1>o 43 kQ vout o Fig. 1.4 pF/~m 1. = 12 ps and Cio = 15 IF. L = 1.9 C j = 4. Assume that VS8 = 1.2 1.
m .1 V.29 (RE) = 30 a. A bipolar junction transistor has the following SPICE parameters (the SPICE name for the parameter is included in parentheses): Is (IS) = 2.10 1. C db. 0 10 ~m/0. Assume that the source and drain junctions extend 4!lm beyond the gate.80 Chapter 1 • IntegratedCircuit Devices and Modelling 1.0 x 10'8 B F (BF) = 100 BR (BR) = I 'F 1.15 VA (VA) = 50V I" (TF) = 12 x 10 . Repeat Problem 1. calculate 9m. PlLl . Find its 99 percent settling time (the time it takes to settle to within I percent of the total voltage change).2!lm. and C Sb for a transistor having W = 50 urn and L = 1.14 1. Also assume that V'n = V'no' Repeat the question for Vin chang~ ing from 3 V to 3._r I mm . but now take into account the body effect on V'n' For an npn transistor having Ie = 0. Taking into account only the channel charge storage. rn • reo roo and 9mro. (MJS) = 0.1 rnA. assuming half the channel charge goes to C L .27 15 C JeO (CJC) = 18 x 10 F <l>e (VJC) = 0.2 V (the gate voltage remains at 5 V). resulting in source and drain areas being As = Ad = 200 (!lm)2 and the perimeter of each being P s = P d = 58 p.11 1.. 5V v.S 9 'R (TR) = 4 x 10 s 15 Cjeo (CJE) = 15 x 10.11. .8 TTL. Consider the circuit shown in Fig. the input voltage has a step voltage change at time 0 from I V to 1.12 For the same circuit as in Problem 1.9 V me (MJE) = 0.37 15 C Jso (CJS) = 40 X 10.F <l>s (V JS) = 0.7 V me (MJC) = 0.11. You may ignore the body effect and all capacitances except C L .64 V rn..13 1.F <l>e (VJE) = 0. where Vin is a de signal of 1 V. determine the final value of Vo ut when the transistor is turned off. P1.11 Find the capacitances C gs' C gd.i o You! C L = 1 pF Fig.
Next.16 1. . Estimate the time it takes its output voltage to saturate.139). The time constants of the individual nodes can be added to arrive at an overall time constant for the approximate firstorder transient response of the circuit.15 has a OV input. using the concepts of average capacitance and firstorder transient solutions for each node.5 V? V DD = 5 V 48 k!1 v. At time 0 its input changes to 5 V.: Fig. assume that the input changes from 5 V to 0 V at time O. PUS 1. Verify that forI SR» Is and IsR» Ie / [3.17 Compare your answers to Problem 1.9 Problems 81 Rb (RB) = 500 R c (RC) = 90 Initially. the circuit shown in Fig.1.140) simplifies to Eq.15 tojhose obtained using SPICE. Eq. (1. P1. (1. How long does it take the output voltage to change to 3.
After processing is presented. Although metallurgicalgrade silicon is about 98 percent pure. Finally. To realize snch a wafer. Here. in which the geometry of circuit elements and wiring connections is defined. This deposited electronicgrade silicon is very pure . circuit layout is covered. For illustrative purposes. Layout is the design portion of integratedcircuit manufacturing. by using typical design rules. This process leads to the development of photographic masks used in manufacturing a microcircuit. one starts by creating metallurgicalgrade silicon through the use of a hightemperature chemical process in an electrodearc furnace. of course. circuit layout is related to the transistor models. it has far too many impurities for use in realizing microcircuits. this section also describes many of the possible variations during processing. While emphasis is placed on CMOS processing. we describe here an example nwell process (with. a p substrate) and two layers of metal. Although the list is not complete. Pure silicon is precipitated onto thin rods of singlecrystalline silicon. it is shown that once the layout is completed. singlecrystalline. one can make reasonable assumptions to approximate transistor parasitic components before the layout has been done.1 CMOS PROCESSING In this section. the values of certain elements in the transistor models can be determined. Next. lightly doped wafer. The Silicon Wafer The first step in realizing a microcircuit is to fabricate a defectfree. The concepts of design rules and their relationship to microcircuits are emphasized.CHAPTER Processing and Layout This chapter describes the steps and processes used in realizing modern integrated circuits. This knowledge is necessary for accurate computer simulation of integrated circuits. Next. It is also shown that. 2. this chapter concludes with a discussion of a destructive mechanism in CMOS circuits known as latchup. the technology required for BJT circuits is also described. including matching and noise considerations. a siliconcontaining gas is formed and then reduced. Analog layout issues are then discussed. the basic steps involved in processing a CMOS microcircuit are presented.
I CMOS Processing 83 but. a singlecrystalline ingot is slowly pulled and turned from the molten silicon using the Czochralski method. Such a doping level would give a resistivity of 10 to 20 Q. often a company other than the processing 1. The Czochralski method starts with a seed of single crystal silicon. As it cools. 21 A starting wafer of p. A typical wafer might have a thickness of about I mm. boron impurities would be added to produce a p . the silicon is melted once again and allowed to cool. or e beam. As a result.' Selective coverage for well definition is performed as follows.ingot.000. Normally. a lightly doped silicon ingot results. and the pull rate and speed of rotation determine the diameter of the crystalline rod or ingot. wells are normally n type and contain pchannel transistors. the surface of the wafer might be doped more heavily. the company that produces the silicon wafers is not the same company that eventually patterns them into monolithic circuits. which defines where the well regions will be located. In our example process. chemically etched to remove mechanically damaged material. Nowadays. This layered approach results in an epitaxial wafer. Wells arc doped regions thai "vill contain one of the two types of transistors realized in a CMOS process. it is also polycrystalline. M" is created. and then finepolished again with 8i0 2 particles in an aqueous solution of NaOH. First.might be doped around the level of NA 2 X 10 donorv rn'. The ingot is cut into wafers using a large diamond saw. ten to twenty different masks might be required. and a singlecrystal epitaxial layer of the opposite type might be grown over its surface before the wafermanufacturing company delivers the wafers to the processing company. em. heavily doped silicon is added to the melt before the singlecrystalline ingot is pulled. Sometimes. here we describe this photographic process in the context of preparing the wafer for defining the well regions. Producing a silicon ingot can take several days. a glass mask. To obtain singlecrystalline silicon. Very often. or dark. Although photolithography is used throughout the manufacturing of an integrated circuit. the glass mask can be thought of as a negative of one layer of the microcircuit. in the regions corresponding to the well locations.e. unfortunately.. The glass mask is created by covering the mask in photographic materials and exposing it to an electron beam. 4 to 8 inches) with lengths usually longer than I meter. The typical cost for these masks is currently around $50. . After the ingot is sawed into wafers.2. After the doped silicon diffuses through the molten silicon. each wafer is polished with AI20 s. Such exposure results in the well regions on the glass mask turning opaque. In a typical microcircuit process. Because a high degree of precision is required in manufacturing these masks. = Photolithography and Well Definition Photolithography is a technique in which selected portions of a silicon wafer can be masked out so that some type of processing step can be applied to the remaining areas. Typical diameters might be 10 to 20 em (i.
84 Chapter 2 • Processing and la yout company makes the masks. Whereverthe light strikes. PR. it may not be removed . . the dopants needed 10 form the well are introduced into the silico n using either diffu sion or ion implantation (directly through the thin oxide. in cases where it has not been removed) . Thi s step is shown in Fig. Phot oresist is a light sensitive polymer (similar to late x). the well regions) are not exposed. The photoresist is rem oved in these areas using an o rganic so lvent. in which the exposed photoresist is dissol ved by the organic solvents. where the exposed photore sist remains after the masking. or polymerize. the uncovered 8i02 may also be removed using an acid etch. Si02 Selectively hardening a region of photoresist using a gloss mask. Ultraviolet light Glass mask p' s ubstrate Fig. In this case. using a computer and a layout CA D so ftware program. is controlled by a computer dependent on the contents of a database. There are also positive photoresists. 2. the poly mers cross. The first step in maskin g the surface of the wafer is to thermall y grow a thin layer of silico nd ioxide (8 i0 2 ) to protect the surface of the microcircuit. The database required for the e beam is derived from the layout database produced by the de signer.. is evenl y applied. the photoresist remains where the mask was opaque. while spinning the microcircuit to a thic kness of around I urn.1 Hardened photoresis t. The procedure ju st described invol ves a negati ve photoresist. MI' is placed in close proximity to the wafer. After the photoresist in the well regions is removed. Thi s change makes these regions insolubl e to an o rganic solvent. the mask.e. The exposure of the opaque regions of the mask . Details of this step are discu ssed later. In the next ste p.link.) In the next step. in so me processes where this layer is very thin . 2. (Ho wever. the remaining photo resist is baked to harden it. Next . On top of the 8 i02 • a negati ve photoresist. and ultra violet light is projected throogh the mask onto the photoresist. The regions where the mask was opaqoe (i. PRt. by the electro n beam.1 . By using both positive and negative resists.
As just men tioned. Gas containing phosphorus 2PH 3 + 40 2 n well ' " Si0 2 p' s ubstrate Fig. This technique is now largely repl acin g diffusion becau se it allows more independent co ntrol over the dopant concentratio n and the thickness of the doped regio n. the rem ainin g hardened photoresi st is stripped usin g ace tone. 2~2 . The resulting cross seclion. In both implantation methods. Thi s mass se pa 0 c.2. do pants are introduced as ion s into the wafer. The io ns are then focused and sent through a mass separator. T he dopant concentration will be greates t at the sur face and wi ll dec rease in a Gaussian profile furthe r into the si licon . Thi s leave s 8i0 2 that was protecte d by the hard en ed phot oresist to ma sk all of the non well (i. In ion implantation .. T he high temperature of the di ffus ion furnace . after di ffusi ng the n well. If a p we ll had been desired. In the case of forming an n we ll. but it takes a much longer lime to diffuse. Arsenic cou ld also be used. typ ically 900 to 1. 2. then bo ron wou ld have been used as the dopant. as shown in the functional representation of an ion implanter in Fig .diffu sion and ion implantation. An alternative techniqu e for introducing dop ants into the silico n wafer is ion implantation . is show n in Fig . 2.1 00 causes the dopants 10 diffuse into the silicon both vertically and horizontally.2 Forming an n well the opening in the Si02 _ by diffusing phosphorus from a gas into the silicon .3. through . The ions arc ge nerated by bomba rding a gas with electrons from an arcdisc harge or co ldca thode so urce. Nex t. subs tra te) region s. there are two approaches for introducing these dopants.e . the next step is to introduce dopants through the openi ng where the we ll region will be located . In d iffusion imp lan tatio n. 10 protect the comple mentary region and impl ant the original region.1 CMOS Processing 85 a single mask can sometimes he used for two stepsfi rst. the wafers are placed in a quartz tube ins ide a heated furnace. the dopant in the gas would probably be phosphorus. usually the 5i02 in the well region will lirsl be remo ved using an acid e tch. to protect one region and impl ant the complementary region and second. A gas co ntaining the dopant is introd uced into the tube. Diffusion and Ion Implantation A fter the photoresist over the well region has been rem o ved.
2.2.06 11m into the silicon. rator bends the ion beam and sends it through a narrow slit. the beam is again focused and accelerated to between 10 keV and I MeV. . The narrow profile results in a heavyconcentration over a narrow distance. The beam current and time of implantation determine the amount of dosage. Two problems that occur with ion implantation are lattice damage and a narrow doping profile. with the majority of Ion dopant concentration Depth into silicon wafer Fig. the beam is purified.4 Dopant profiles ofter ion implantation both before and after annealing.3 An ionimplantation system. Next. Since only ions of a specific mass pass through the slit. depth and dosage are controlled independently. as is shown in Fig.4. The ion current might range from 10 IlA to 2 rnA. arsenic ions with an acceleration voltage of 100 keV might penetrate approximately 0. Thus. The lattice damage is due to nuclear collisions that result in the displacement of substrate atoms. 2. For example. The deflection plates sweep the beam across the wafer (which is often rotated at the same time) and the acceleration potential controls how deeply the ions are implanted.86 Chapter 2 • Processing and layout Vertical and horizontal deflection plates uuu nnn ~~ ~ ~ IIII IIII T ~ Separating Focusing Acceleration slit lens plates Ion beam Target ~ ~ Focusing lens ~ Ion source Fig.
after all the implantation steps have been performed but before any metal layers have been created. . The Si0 2 is then removed with a hydrofluoric acid etch. wherever the mask M2 is not opaque. wherever it is not protected by the photoresist. Chemical Vapor Deposition and Defining the Active Regions The next few steps use the fieldoxide mask. everywhere the fieldoxide is not desired. is removed by etching it away with a hot phosphoric acid. These steps result in a thin layer of thermal Si0 2 .).06 urn ± 0.2. the photoresist is left intact after the organic dissolution step. Both of these problems are largely solved by annealing. minimizes the overlap between the gatesource or gatedrain regions. the remaining photoresist is chemically removed with a process that leaves the remaining Si3 N. the positive photoresist is deposited. In other words. this step will be done using positivephotoresist such that.i For ntype dopants. ion implantation has been largely replacing diffusion for forming nand p regions because of its greater control over doping levels. will act as a mask to protect the active regions when the thick fieldoxide is being grown in the fieldoxide regions. under the opaque regions of the mask where the fieldoxide is not desired. which allows devices to be more closely spaced and. arsenic is used for shallow implantations. For example.4. such as the source or drain junctions. the Si3 N. I CMOS Processing 87 ions being at 0. which allows the bonds to reform. The hardened photoresist is left on top of the Si3 N. It should be noted that annealing is performed only once during processing. the metal would melt. and then allowed to cool slowly. Although more expensive. intact. M2. the photoresist will be softened. Si3 N. exposed through the mask. FieldImplants and the FieldOxide The next step in our example process is to implant the fieldimplants under where the fieldoxide will be grown. Next. A thin layer of thermal SiOz is first grown everywhere to protect the surface of the silicon lattice. This heating stage thermally vibrates the atoms. to protect it where the fieldoxide is not desired. If annealing were done after deposition of a metal layer. Another important advantage of ion implantation is the much smaller sideways diffusion. After this step. and hardened. Finally. Phosphorus might be used for the well.02 urn. making the doping levels more uniform. as well as a layer of silicon nitride (Si3N. perhaps for 15 to 30 minutes. more importantly for MaS transistors.000 DC. as shown in Fig. to form the thick fieldoxide as well as the field implants (used to isolate devices). 2. This process is called chemical vapor deposition. boron will be implanted under the fieldoxide 2. Next. Annealing is a step in which the wafer is heated to about 1. is deposited everywhere during a gasphase reaction in which energy is supplied by heat (at about 850 DC). . Often. Boron is always used to form the p regions. Annealing also broadens the concentration profile. M2' dissolved. The remaining Si3N. or CYD.
water vapor is introd uced over the surface at a moder ately high temperature. all the active region s.e . Afte r the ex pose d photores ist has been dissol ved . are pro tected fro m the field impl ant s by the 8 i3N4 • 8i0 2 • and PR.. where pchannel tran sistors will eventually reside. Often. it is not necessary to incl ude fieldimplants under the fi eld oxid e of the well region s becau se the heavie r doping of the well (co mpared to that of the substrate ) norma lly g uarantees that the silico n will ne ver invert under the field oxide in the se regi ons. M that was o riginally " used fo r impl ant ing the n wells. so the nwell region s do not rece ive the p imp lant. but now a positi ve pho toresist is used . In a wet process.5 .88 Chapter 2 • Processing and l ayout everywh ere except in the well region s. Thi s implant g uarantees that the silicon under the field oxide will never invert (or becom e n ) when a co nductor ove r the fieldoxide has a large vo ltage .impla nts in the substrate regions . Th e fieldimplant wi ll be a high energy im plant with a fairly high dop ing level. Th ere are two different ways tha t 8 i0 2 can be grow n. For the fieldox ide in the we ll regio ns. dark). When imp lanting the field. the co mplete we ll reg ions arc a lso protecte d by PH... 2. Not ice that at this step. w hich correspond s to the we ll regions. where eventually the tra nsis tors will res ide. I ) PR3 PR2 Boron ions PR2 + ++ ++ + III ++++ n well ++++ Fieldimpl ants \I ++ ++ +++ + Si0 2 p" substrate Fig. The wate r vapor diffuses into the silico n and. reacts acc ording to the form ula 8i + 2 H 2 0 > 8 i0 2 + 2H 2 (2 . which are intended to be unconnected . 81° 2.2. afte r so me intermediate steps. an ntype implant such as arsenic (As) co uld be used . . Add itionall y. we now have the cros s section shown in Fig.5 The crass section when the fieldimplants are being farmed . PH. Growing the FieldOxide Th e next ste p is to grow the fieldoxi de . leakage currents co uld occur between the j unctions of separate nch annel transistors in the substrate regi on. it is necessary to first cover the wells with a protecti ve photoresist. Thi s positi ve photoresist remains w here the mask is opaque (i.. Th is ca n be done using the sa me mas k. If this implant were not performed .
oxide in the substrate region has fieldim plants under it. around 800 to 1200 "C. are "removed. After the galeoxide has been grown. as shown in Fig. oxyge n is introduced over the wafer .6 The cross section olter the fieldoxide hos been grown. When grow ing thermal S i0 2 • the wet process is faster because H2 0 diffuses faster in silicon than O 2 does.silicondiox ide sandwic h is left. ~ nweu : J \ ! p' fieldimplants p. donors are implanted so that the final thres hold voltages of the transisto rs are correct. and S5 percent above . the field. grow ing the fieldoxid e starts with a dry process. II should be mentioned here that many processes differ while realizing the thresholdadjust step. Note that in our exa mple process.6. 2.03 um. this S i02 is also rem oved. because the S i3 N. . whereas the fieldoxide in the wells does not. 2. and reacts according to the fonn ula Si + O 2 ~ S i0 2 (2. usually with hydrofluoric acid. T he reaction does not occ ur whereve r CVDdeposited S i3 N. PR 2 and PH. and finishes with a dry process. S i02 takes up approximately 2. bUI the dry process results in denser. thin gateox ide is then grown using a dry process. the Si 3 N. The resulting cross section is shown in Fig.2) Since both of these processes occur at high temperatures. Before the field oxide is grown.substrate Fig. is removed using hal phosphoric acid. normally at a slightly higher tempera ture than that used in the wet process .2 times the volume of the original silicon . remains. Wherever the process does occur. the volume increases beca use oxygen atoms have been added . what previous ly was the surface of the silicon.1 CMOS Processing 89 In a dry process. GateOxide and ThresholdVoltage Adjusts In the next step. changes 10 a wet process.6. This increase will cause the S i0 2 to exte nd approxi mately 4S percent into. II is grown everywhere ove r the wafer to a thickness of about 0. The highquality. Specifically. Note that this implantation is perfo rmed direct ly throug h the thin gateoxide since it now covers the entire surface . highe rqualit y S i02 that is less porous .•~. 2. the oxide that results is sometimes ca lled a thermal oxide.0 I to 0. but the siliconnitride.==~ . is relatively inert to both water and oxygen. SiaN.2. Some times . usually only a dry process is used. Si02 Fieldoxide L ~ . When thin layers of S i0 2 are grown. as the next section describes. If a thin layer of S i02 is under the S i3 N•• protecting the surface.
no additional mask is required.9 V. If the n wells are doped a little heavier than ideal. the same single boron thresholdadjust implant will bring it to around 0.1 V to its desired value of 0.n from its native value of around 0.7 to 0.substrate Fig. A double threshold adjust allows optimum well doping.8 V. the threshold voltages of both the p. By using a single thresholdvoltageadjust implant for both nchannel and pchannel transistors. The major problem with using a single thresholdadjust implant is that the doping level of the n well is higher than optimum. but a number of additional processing steps are needed. Polysilicon Gate Formation The next step in the process is the chemical deposition of the polysilicon gate material. then the second of two types of transistors has to be protected by. In a simple process. a negative photoresist while the first type is being implanted. say. Both approaches are currently in commercial use. a positive photoresist can be used with the same mask to protect the first type of transistor while the second type is being implanted.90 Chapter 2 • Pracessing and layout Thin gate 8i02 Fieldaxide ++\+ + n well Gate threshaldvaltageadjust implant p" fieldimplants p. two photoresist masking .steps are eliminated. 2.3) . This higher doping level increases the junction capacitances and the body effect of the transistors in the well. The cross section at this stage is shown in Fig. As a result. Thus. M]. The mask used is normally the same mask used in forming the n wells.7 Cross section aher the thin gateoxide growth and threshaldadjust implant.2.6 V. If the different transistors are individually implanted. the native threshold voltage of the pchannel transistors in the well will be around 1. although the double thresholdadjust implant is growing in favor as device dimensions decrease. One method to create polysilicon is to heat a wafer with silane gas flowing over it so the following reaction occurs SiH. Next. We saw in the Appendix of Chapter I that the nchannel transistors require a boron implant to change V. > Si + 2H 2 (2.8 to 0.and nchannel transistors are adjusted at the same time.7. in other words.
A new mask . PR•. more importantly. say. After the nonhardened photoresist is removed. This thin galeoxide layer is used to proteet the surface during the next step of junction impla ntation. In our example process. Very often. 2. everywhere except where the p" regions are desired.25 u rn. the polysilicon is etched away using a reactive plasma etc h. The cross section at this stage is shown in Fig. a nd O pen ing Conta ct Holes The next step involves the ion implantation of the junctions. the silicon that is deposited is noncrystalline. the p" junctions are formed first by placing positive photoresist.2. this silicon is often referred to as polysilicon. As a result . Notice that the p + junctions of the pchannel transistors are defined on one edge by the fieldoxide and. This approach is used both when epitaxial layers are grown in bipolar processes and in some of the more modern CMOS processes. and its thickness might be aro und 0. it was the gate polysilicon and the photoresist over it that protected the channel region from the p" implant . The p' regions are then ion implanted.8 Cross section after depositing and pctterning the polysilicon gates . Depo siting Si0 2. when depos iting the polysi licon gates. the original surface is 8 i02 and the wafer is heated only to abo ut 650 °C. around 1.9. Th us.250 °C. Thi s polysilicon is then patterned using a new mask. T he mask is opaq ue where hardened polysilicon shou ld remain. the depo sited silicon will also be single crys tal. M•. next to the active gate area by the edge of the polysilicon gate .1 CMOS Processing 91 Fig. 2. However. M. PR. possibly through a thin oxide in some processes.. and the original surface of the wafer was single crystal. and a posit ive photoresist. The cross section at this phase is shown in Fig.8.. If this reaction occurs at high temperatures. A typical final resistivity for polysi licon might be 10 to 30 0 10 . is used in thi~ step . . after the polysilicon is deposited.000 to 1. During the implantation of the boron. it will be ion impla nted with arsen ic 10 increase its conductivity. the polysil icon gate material covers the entire wafer. This etch removes all of the polysilicon not protected by photoresist but removes very lillie of the underlying 8 i0 2 . After the deposition ju st described. Implanting the Junctions. or amorp hous.2 .
After the junctions have been implanted and P Ro has been removed. that was used for the previous step. Thu s.9 C ross section after ionimplant ing the p' junctions. Also notice that a p " junction has been implanted in the substrate region . M 2 (i. M. the co mplete wafer is co vered in CV D 8i02 . a small Lov.. rem ains). The p' active regions are then protected using the same mask . 2. is used to connec t the substrate to ground in microcir cuits. resultin g in very little overlap (i. both in MOS processes and in BJT processes. In addition.10 C ross section a fter ionimplanting the o f. the underside of the wafer would norma lly be connec ted to gro und as well.2. M. Also. The development of this selfaligned process has pro ven to be an important milestone in realiz ing small highspeed transistors.10. called a substrate lie. Thu s. the photor esists are all removed using acetone.. through a package connection. these are the two most import ant masks in any MOS process.e.92 Chapter 2 • Processing and layout Polysilicon Polysilicon Substrate connection p' substrate Fig.. and the mask used in defi ning the active regions.. but now a negative photoresist. as defined in Chapter I). The n + junctions are then implanted using arsen ic. Thi s protect ive glass layer can be deposited at moderPolysilicon gates p' pchannel junctions Substrate tie nchannel junctions Fig. Next. the mask used in defining where 8i3N. junctions. The cross section at the end of this stage is shown in Fig.e. is used. note that the effective channel areas of the transistors are defined by the intersection of the gatedefining mask. P Ro. Th is junction. These substrate tics are liberally placed tbroughout the microcircuit to help preven t latchup. .2. the p" jun ctions are selfaligned 10 the polysilicon gates. a problem discussed at the end of this chapter.
5J. The metal is deposited using evaporation techniques in a vacuum. and then a second layer of metal is deposited and etched using mask Mg and photoresist PR lO • Often the primary use of this top layer of metal might be to distribute the power supply voltages. Next. Some of the possible variations are as follows: 1.. are possible. . This twintub process allows both wells to be optimally doped. A cross section of the final microcircuit for our example process is shown in Fig. This example process is a fairly representative CMOS process. broaden the concentration profiles of the implanted dopants. 15 to 30 minutes) at temperatures up to 1. often involving additional masks. a lowtemperature annealing might take place to give better bonds between the metal and the silicon. The contact holes are defined using mask M. and Overglass Deposition After the first layer of CYD Si02 has been deposited. Two wells may existone for pchannel transistors and one for nchannel transistors. Annealing. Historically.2. Depositing and Patterning Metal. which allow for much denser interconnect. The final microcircuit processing step is to etch openings to the pads used for wire bonding. interconnect metal is deposited everywhere. although often an additional layer of Si3 N4 might be deposited because it is more impervious to moisture. However. additional contact holes are formed using mask M.25 to 0. annealing entails heating the wafer in an inert gas (such as nitrogen) for some period of time (say. The bottom layer would be used more often for local interconnects in gates. As mentioned earlier in this section. 2. The next step is to open contact holes through the deposited Si0 2 . the wafer is annealed. This final step would use mask Mg and photoresist PR J l . The deposited Si0 2 might be 0. aluminum (AI) has been used for the interconnect. or possibly ion bombarding in a sputtering system.11. it is patterned using mask M6 and positive photoresist PR" and then it is etched. and positive resist PR. This extra poly layer can be used to realize highly linear polytopoly capacitors in which a thin thermal oxide is used to separate the two layers. an additional layer of CVD Si0 2 is deposited. However.000 "C. many variations. This layer would be CVD Si02 . this process is repeated a third and possibly a fourth time to give up to four levels of metal.lm. After the last level of metal is deposited. The resulting thermal vibrations heal the lattice damage sustained during all the ion implantations. After the metal is deposited on the entire wafer. At this time. The temperature of this annealing must be less than 550°C so the aluminum doesn't melt.1 CMOS Processing 93 ately low temperatures of 500°C or lower. 2. In some modern processes. or overglass. An additional polysilicon layer may be deposited over the first layer. The heat required for evaporation is normally produced by using electronbeam bombarding. recently other metals have been used that have less of a tendency to diffuse into the silicon during electrical operation of the microcircuit. a final passivation. is deposited for protection. Next. and increase the density of the deposited Si02 . and photoresist PRg.
9. and a p'epitaxiallayer would be grown. I GQ / D ). 7. mixedmode microcircuits).implants may exist under the fieldoxide in the well regions as well as under the field oxide in the substrate regions. it greatly minimizes substrate noise in microc ircuits that have both analog and digital circuits. Finally. it is usuall y necess ary to add several additional steps so that the surface is made smoother.11 Final cross section of an exa mple CMOS microcircuit. Often. This type of process is called a BiCMOS process and is beco ming particularly popular for both analog and digital highspeed microcircuits. In a multimetalIayer process.94 Chapter 2 • Processing a nd layout 3. 10. Additional processing steps may be used to ensure that bipo lar transistors can be included in the same microcircu it as MOS transistors. 4. 8. 2. Before the epitaxiallayer is grow n. 5. Thin film nichrom e resistors may ex ist under the top layer of metal. The microcircuit might have three. and it is also more immun e to gamma radiation in space. This type of wafer is similar to that used in processing bipo lar transistors.. Field. and is becomin g more co mmon in CMOS proces sing. Th is is normall y done by a reacti ve etching proce ss in which the metal is covered with Si0 2 and the hills are etched faster than the valleys. but of the opposite type. four. to obtain better fill in and less diffusion into the silicon surface. the nchann el and the pchannel transistors might have separate thresholdvoltageadjust implants. or live layers of metal. Different metals might be used for the co ntacts than for the interconnect. 6. The transistors may be realized in an epitaxial layer.implant Welt tie Substrate tie p'substrate pchannel transistor Fig. static randomaccess memory (SRAM) cells. 11. the top of the substrate would be dope d p". after each metalpatt ernin g step. (i. or plan arized. the substrate would be n". p" field. ln this case. . Thi s high resistivity is used to reali ze resistor loads in fourtransistor. T he advantages o f this type of transistor are that it is more immune to a destructive phenom enon called latchup (described at the end of this chapter).e. An additional polysilicon layer might be formed that has an extremely high resistivity (say.
the n + collec tor contact regio n is implanted. using one of a variety of possible methods. and possibly the collector. selfaligned bipo lar transistor with oxide isolation. Thu s. an n" singlecrystal epitaxia l layer is deposited. polysilicon is used to contact the emitte r. Thi s region extends from the surface down to the n + burie d region under the transistor. [2 shows for a typical npn BJT struclure. the surface of the silicon is typically etched to form empty cavities. before the fieldoxide is grown and after the openings in the S i3N.2 BIPOLAR PROCESSING The processing steps required for realizing bipolar transistors are simi lar to those used for realizing MOS transistors. A bipolar proce ss normally starts with a p. with some modifications.2. In a modem process. The first masking step involves the diffusion (or ion implantation) of n" regions into the substrate wherever transistors are des ired. In the next basic step. The base polysilico n is removed in the active area of the transistor. the base.substrate. rather than presentin g the complete realization of modern bipolar transistors. as Fig. Next. However. we briel1y discuss some of the modifications needed for realizing them .2. Si02photoresist sandwich have been made. .2 Bipolar Processi ng 95 2. the base p + polysilicon is depos ited first. 2. the base polysilicon is covered with a thin layer of p" poly Base Collector n" poly AI Emitt er n" poly Base p+ p" substrate n+ Si0 2 p" Fig. After the field oxide is grow n. The term "poly" refers to polysllicon. This extra etching step allows the fieldoxide to extend further down into the epitaxia l region. Next. during a hightemperature step.12 P Cross section of a modern. the boron dopant from the polysilicon contact diffuses into the silicon undernea th the base polysilicon to make the underlying region p". These n + regions are used to lower the series co llector resistance. This polysilicon is heav ily doped p + so that later. the fieldoxide is formed for isolation. Norma lly.
when the cells are being connected. perhaps 0. one would rarely allow a computer to automatically generate the layout of a memory cell where space and capacitive loading of the connecting buses are critical. The designer might then interactively modify this automatically generated layout. I. The layout program then automatically sizes the masks to account for any lateral diffusion or etching loss. the base is ionimplanted to p type silicon. ~ . the true emitter has not yet been formedonly the emitter n + polysilicon has been laid down. the p + and n + masks used for the source and drain regions are usually generated automatically.96 Chapter 2 • Processing ond layout Si0 2 .3 CMOS LAYOUT AND DESIGN RULES It is the designer's responsibility to determine the geometry of the various masks required during processing. these cells are then parametrically adapted to a required size. the designer must still take direct control of the layout of critical cells. this procedure results in a selfaligned process since the use of the Si0 2 spacer allows the base polysilicon to determine where the emitter is finally located. which separates the base polysilicon from the emitter polysilicon. and the corresponding geometries for every layer are automatically generated. During overall layout. At this point. The importance of this process is that.12. Thus. the program might allow the designer to work in the final desired dimensions. 2.or smallerdimension masks. For example. as shown in Fig. as time goes on.5 urn in thickness. However. However. During annealing. highfrequency bipolar transistors can be realized using methods similar to those used in realizing modem MaS transistors. the n+ from the emitter polysilicon diffuses into the base p silicon to form the true emitter region. by the program. we describe some typical layout design rules and the reasons for these rules. Often. thereby minimizing the base resistance. Also. or connected. Here. Thus. When designing the layout.2~m length. they might be automatically placed and routed. Next. As a result. very small. The process of defining the geometry of these masks is known as layout and is done using a computer and a CAD program. 2. . For example. the layout of some circuit cells might already be performed and stored in a library. The program might then produce a mask that had a 1. a digital microcircuit designer must be knowledgeable about the design rules that govern the layout required for the process used. this sizing produces larger.6~m line width. In a modem layout program. This increased mask sizing would account for the junction overlap due to lateral diffusion and the polysilicon loss due to etching. the p + dopants from the base polysilicon also diffuse into the extrinsic base region. through the use of selfaligned contacts and fieldoxide isolation. allows the base polysilicon (or contact) to be very close to the emitter polysilicon (or contact). leaving an opening over the active area of the transistor. when the wafer is annealed. especially when the layout must be small or the resulting circuits must be fast. the layout becomes more automated as more cells become available. typically the designer does not need to produce the geometry for all of the masks because some of themasks are automatically produced by the layout program. This Si02 spacer. For example. and then n + polysilicon is deposited for the emitter. a designer might draw a polysilicon line so that a transistor would have a 1.
.. The intersection of these two masks beco mes the channel region of MOS transistors.13 101 A Si mplified view of a portially finished transistor and Ib) the correspond ing layou t of the active . When we express design rules in term s of A. and contac t masks.. and Fig..2.2. mask. .. This generalization allows many of the des ign rules to be simply expressed.). 13(a).751. then a separati on L Active regia. 2. Thus. which shows a simplified view of a MOS transistor . 2. polysilicon.. the poly mask runs vertically. 1. we assume that each mask has a worstcase alig nment of under 0.13(b) . conside r Fig.13(b) shows the smallest possible transis tor that can be realized when a co ntact must be made to each junction.. Th e length of the poly that intersects the activeregion mask is the transistor width. 2. or poly. and the width of the poly line is the transistor length. we ca n guara ntee that the relative rnisalignment betwee n any two masks is under 1. W. independent of the true value for the mini mum channel length (i. 21.. Figure 2. is 1/2 the gale length. where I. For exa mple..3 CMOS layou t an d Design Rules 97 The two most important masks are those for the active region and for the gate polysilicon. Also shown are many of the minim um dim ensions in [eon s of A. i (a) Fieldoxide region Polysilicon mask \ 41 i Contact mask l~H w Effective gate region (b) Fig. If an ove rlap between any two regions of a microc ircuit would cause a destructive short circuit.13 shows. which shows the co rrespon ding layout of the active mask and the polysiJicon. as Fig. In Fig.e.51. The desig n rules for laying out trnnsistors are often exp ressed in terms of a quanti ty. 13(b). L. 2.
14 Mask misalignment that results in ca tastrophic short circuits and an example of a noncotostrophic misalignment.w~'j \.. Another design rule is that active regions should surround contacts by at least II... causing the transistor to be always turned off.\ "''I'''''\''~'' "'". ".13(/J).. To . the Gate poly Source junction Drain junction Noncatastrophic misalignment Sourcetogate short circuit Sourcetodrain short circuit Fig. 2. \~~ "". having the source (or drain) region surround the contact by I A guarantees an overlap of at IcaSI 1...\ ~ "'~.\ . an overl ap exist s between the edge of the activereg ion mask and the contact mask. The circuit still works correctly as long as sufficient o verlap exists between the contact and the active masks so that a good connection is made between the aluminum interconnect and the junction... For example. 2. If these two regio ns overlap in the microcircuit.. Since the junctions are implanted everywhere in the active region except under the gate. this error also shortcircuits the gate toground. If the source happens to be connected to ground."'''"' \~~ t""\'j':'\\\""''' 'S.~.. For example. then the act ive region must exlend past the polysilicon region by at least 51.\ 1.14 .. consider the poly mask and the contact mask in Fig ..51. this misalignment causes a short c ircuit between the source and the drainthus the design rule that poly silicon must alway s extend at least 21.13 a contact is to be made to a junction. 2. as shown in fig. (the minimum contact width is 21. Thus..\~". If. then the metal used to contact the source jun ction is also shortcircuited to the gate poly. Another example o f a catastrophic failure due 10 misalignm ent is a gate that does not fully cros s the acti ve region (also shown in Fig.prevent this type of short. assume that in Fig. in reality .t.. The few design rules just descrihed are sufficient to allow one 10 estima te the minimum dimensions of a junction area ami perimeter before a transistor has bee n laid out.. no disastrous shorts oc cur..14 ). guarantees this will neve r happen. 2. past the active region.). Since the maximum relative misalignment is 1.51. .98 Chapter 2 • Processing and Layout between the corresponding regions in a layout of 21. 2.\ \~.\.
2. Similarly.15 10) A series connection of two transistors and {b) a possible la yout. Note thai the perime ter does not include the edge betwee n the junction and the active c hannel separating the ju nctio n and the gale beca use there i ~ no fieldimplant along this edge . note that they are onl y estimates: the true layout will differ somewhat from these rough estimates. 21. Sometime s. and the . 31.3 CMOS layout and Design Rules 99 minimum area of a small junction with a contact to it is As with a contact is given by = Ad = 5AW (2.idcwall ca pacitance is there fore smaller along thai edg e . .13. The active. and contact "'~"' (a ) II A n 21. 31.15«(/). J. _ (b) n Fig. However. They may also be used in SPICE to simulate circuits so the para sitic capacitances are determined more accurately. • 101. _ 21. a single j unction can be shared betwee n two transistors.2.5) These estimates may be used when estimating the parasitic capacitances in the transislor models. when it is important to minimize the capacitance of a junction. 3. the perimeter of a junction' P s = P d = IOA+W (2. 2. poly . 2.4) where W is the transi stor wid th.. For example. in Fig. con sider the series connection of two transistors shown in Fig.
we have decreased the junction area by using the fact that the transistor is much wider than the single contact used. in a SPICE simulation. where we have AJ .5)5(~m) ~ = 12. the ratio of the perimeter to the area increases and the sidewall capacitance becomes more important. Also.15. = 0.9) . It is of interest to note that as transistor dimensions shrink. sometimes wide transistors require additional contacts to minimize the contact impedance. all of the area and perimeter could be specified in one transistor description. 2. we have AJ 1 = 5AW = and P J 1 = lOA. Contrast this case with junction J 2 . the physical sizes are W = 5 urn and L = 1 urn. the two contacts used for junction J 1 result in roughly half the contact impedance of junction J. and A. Thus. for junction J I' using the formulas of (2. Next.6) Since this junction is connected to ground. and J 3 for the circuit in Fig. For example. = 8(~m) 2 2 2 = W + 12(0.5). respectively. and especially the perimeter of this junction. consider the shared junction.15(b).1 Assuming A. Since the junction sidewall capacitance is directly proportional to the junction perimeter.5) + 5] urn = 10 urn (2. However. Here we have a junction area given by AJ 3 = 2AW = 5(~m)2 (2.5 urn . Alternatively. + W = [10(0. . are much smaller than those given by equations (2. its parasitic capacitance is unimportant and little has been done to minimize its area. find the area and perimeters of junctions J I' J 2 .4) and (2. and the area and perimeter of the other junction could be specified as zero.100 Chapter 2 • Processing and Layout masks might be laid out as shown in Fig.7) 5(0.8) The perimeter is unchanged. Notice that a single junction is shared between transistors 0 1 and O 2.5). and since this capacitance can be a major part of the total junction capacitance (because of the heavily doped fieldimplants). since the junction is shared..4) and (2. resulting in P J2 = 10 um . minimizing the perimeter is important. = 0.. 2.5 urn. Solution Since the width and length are shown as lOA. The area. = 2AW+ 121.5(~m) 2 (2.5) (2. Thus. the area and perimeter should be divided by 2 when they are specified in each transistor description. and 2A. EXAMPLE 2.
. is SA. The reduction in the perimeter is even more substantial. 2. a p+substrate tie can be much closer to a well because it is always connected to ground and is separated from the well by a reversebiased junction.16 that metal is used to connect the junctions of the pchannel and n channel transistors." An additional design rule has been implicitly introduced in the previous example. with reference to the layout of a digital inverter. This result is much less than the 1Ol1m perimeter for node J]. Notice also that the minimum spacing between the n well and the junctions of nchannel transistors.3 CMOS Layout and Design Rules 101 Since this is a shared junction. Normally. which is connected to VDD' the circuit would not work. Note that it is not possible to share junctions between nchannel and pchanneltransistors.11) for the shared junction: so sharing this perimeter value over the two transistors would result in (2. in the substrate. Here we have PJ3 = 4A 211 m (2.15. 2. Notice that the n well surrounds the pchannel active region. the closest an nchannel transistor can be placed to a pchannel transistor is 8A. This limitation is one of the reasons for the larger parasitic capacitances sometimes encountered in CMOS microcircuits as opposed to ~MOS microcircuits. Several design rules are required in addition to those just mentioned. part of the active region boundary is only 2A away from the gate. A typical dimension here might be 2A. Since a pchannel junction must be inside the well by at least 3A and an nchannel junction must be outside the well by SA. one of the first steps an experienced designer takes before laying out important highspeed cells is first to identify the most critical nodes and then to investigate possible layouts that minimize the junction capacitance of these nodes. in a SPICE simulation we would use As (2.10) for each of the two transistors. 2. Notice in Fig. Notice that for junction J.16. where only nchanneltransistors are used. the metal must overlap any underlying contacts 4. Conversely.2.5 (11m)' . This large spacing is required because of the large lateral diffusion of the n well and the fact that if the nchannel junction became shortcircuited to the n well. This minimum junction area is the typical design rule for this case. Because minimizing the junction capacitance is so important. Some of these are described next.12) 111m for the appropriate junction of each transistor when simulating it in SPICE. and therefore the p+ junctions of the pchannel transistors. which is much less than 12. in Fig. by at least 3A. shown in Fig.
ncha nnel transistor n" junctions (b) p+ substrate tie Fig.102 Chapter 2 • Processing and layout by at least .16 that a single contact opening.\. 2. 2.\. 2. for the nchanneltransistor. known as a butting contact.16. where it is 4. the same as the minimum width for polysilicon.16. can be used to contact both the pchannel transistor source and an n + well tie.\'. However. Also. (a) p" junction pchannel transistor Poly interconnect Active region v. a v'" v.. because both will be connected to VDO' Although the outlines of the p + and n + masks are not shown in Fig.16 10) A CMOS digital inverter and (bl a possible la yout with several design rules illustrated . A typical minimum width for firstlevel metal might be 2. one half will be doped P + (the pchannel ju nction) and one half will be doped n' (the well tie). under the contact. it can be wider as in Fig... Notice also in Fig. 2. wide .. .
. node 2 will have a much greater junction capacitance than node I. Assuming node 2 is the source. respectively.I7(a). These might be 2A.3 CMOS Layaut and Design Rules 103 butting contact was used to connect the nchannel source to a p + substrate tie. and the device is in the active region. Thus. and 3A.17.I7(b) shows the circuit corresponding to the layout in Fig. In a typical set of design rules. . node I should be connected to the more critical node. Figure 2. Figure 2. such as polysilicon or heavilydoped silicon. This concludes our brief introduction to layout and design rules. and metal 2 might also be lA. The use of many contacts in wide junction regions greatly minimizes voltage drops that would otherwise occur due to the relatively high resistivity of silicon junctions compared to the resistivity of the metal that overlays the junctions and connects them. Normally.5 urn. Because it has a larger total junction area and especially a larger perimeter.. metal I. find the 5. 2A. A simplified layout of this approach is shown in Fig. and 3A.17(c) shows the same circuit redrawn differently. the reasons for using and the methods of applying these rules is similar to that which has been described..2 Consider the transistor shown in Fig. However. where it is clear that the circuit consists of four transistors connected in parallel. lA. and A. 2. is recommended to lower the resistivity of the interconnect." Design rules also specify the minimum pitch between polysilicon interconnects. and fifth junction regions are connected by metal to realize node 2. The use of metal to overlay a higherresistivity interconnect. whereas the first. its length is 2A. some of these are butting contacts if either node I or node 2 is connected to an appropriate power supply. third. Finally. a wide transistor is composed of smaller transistors connected in parallel. Also notice the large number of contacts used to minimize the contact impedance. and both will be connected to ground. For example. the rules might specify that no transistor can be more than lOOA. Metal 2 requires a larger minimum pitch because it resides further from the silicon surface where the topography is less even. EXAMPLE 2. from a substrate tie.2. As a final example. These rules are necessary to prevent latchup. many more design rules are used than those just described. 2. respectively. 2. The minimum widths of poly. = 0. In a modern process. metal I interconnects.I7(a). when the equivalent transistor is connected to a circuit.. Notice that the second and fourth junction regions are connected by metal to node I. Normally. the design rules are usually available to the layout program and are automatically checked as layout progresses. and a maximum distance between substrate ties is also specified... node I is the drain. a maximum distance between transistors and well (or substrate) ties is specified. and metal 2 interconnects. where the transistors have been drawn in the same relative positions. where the total width of the five parallel transistors is 80A. where four transistors that have a common gate are connected in parallel. a phenomenon described at the end of this chapter. note that when one does modern microcircuit layout. we describe the layout of a large transistor.
J. (hJ the schema tic drown in the same relative positions as the layout . an d leI the circuit redrawn to make the parallel transistors more obv ious. 2. Node 2 (c) Fig. J• • Gates Node 2 (a) v« Node 1 Node 2 (b) V a Node 1 J.17 Connecting four transistors in parallel to realize a single large tra nsistor : (oj the layout .Node 1 Metal interconnect Active region • • • • • • • • • J. 104 .
)Ci sw = 0. Also find the equivalent capacitances if the transistor were realized as a single device with source and drain contacts still evenly placed. C d b can be estimated to be c. the drain.C j + P J2Cj_sw) = 0. we find AJ = 5A x SOA = 400A' = 100 (11m)' and P J = 5A+5A+SOA = 90A = 45 11m resulting in C d b = 0.pF/llm. In the case where the transistor is a single wide device. 2. node I has less capacitance than node 2 since it has less area and perimeter.4 X 104 pF/(llm)' and C j _sw = 2.. even without the additional capacitance due to the WL gate area. Solution Starting with node I. =0 11 m resulting in an estimate for C Sb of C Sb = (AJ] + AJ3 + AJ5 + WL)C j + (P J] + PJ3 + PJ. we find that the areas of the junctions are equal to AJ2 = AJ4 = 6A x 20A = 120A' = 30 (11m)' Ignoring the gate side.2.4 Analog Layout Considerations 105 sourcebulk and drainbulk capacitances given the parameters C j = 4 2. = and 2(A J. = 30 (11m) The perimeters are found to be z P J] = P J5 = 5A+5A+20A = 30A = 15 11m and PJ3 = P J.017 pF For node 2. . These issues can be broadly divided into two categoriesmatching and noise issues.0 X 10. Note that in this case.4 ANALOG LAYOUT CONSIDERATIONS When one designs analog circuits.043 pF.036 pF It should be noted that. we have 2 AJ] = AJ5 = 5A x 20A = 100A = 25 (11m)' AJ3 = AJ. C d b is nearly twice what it is when four parallel transistors are used.033 pF and C Sb = 0. the perimeters are given by P J2 = P J4 = 6A+6A = In = 6 11m As a result. the source. several important layout issues should be considered to realize highquality circuits. rather than four transistors in parallel.
where all nchannel transistor is show II as we look a long the channel from the dr ain to the so urce. occurs when layers such as polysilicon or me tal are being etc hed. for e xample. The result is that the e ffective width o f the tran sistor is less than the width drawn o n the layout mask. The width o f the transistor is defined by the width of the acti ve reg ion (as o ppo sed 10 the width o f the polysilicon line).18(0 ) shows how an effective well area will typically be larger than its ma sk due to the lateral diffusion that occurs not just during ion implantation but als o durin g later high temperature steps. . 2. 18(b) . but man y othe r secondorde r effects influence the realized cornpo5iO. such as annealing. Fig ure 2. Fig . For example. shows ove retching that occ urs under the Si0 2 protective layer at the po lysilicon edges and causes the po lysilicon layer 10 be smaller than the correspo nding mask layo ut. 2. and this width is determined by the field oxid e. protection Polys ilicon gate 5 iO. mask (a) (b) Polys ilicon gate Transistor channel ////// p" field implants (e) Channel width narrowing Fig. 2. Thi s incre ased doping raises the effec tive tran sistor threshold voltage ncar the sides of the transistors and therefore decreases the channel charge den sity at the edges. Some examples of these effects are illustrated in Fig.18. protection Well Overetch ing Lateral diffusion under 5iO. a variety o f twodimensional effects can cause the effective sizes o f the components to differ from the sizes of the glass layout masks. The examples shown illustrate typica l sizing effects.18 Va rious twodimensional effects causing sizes of realized microcircuit compo nents to diffe r F rom sizes of layout ma sks. I 8(c) . known as ove retching .106 Chapter 2 • Processing and la yout Matching Issues W hen integr ated components are realized using lithographic techniques. A third e ffec t is shown ill Fig . Anot her effect. 2. The p + field implant under the fieldo xide causes the effecti ve substrate doping to be greater at the sides o f the transistors than elsewhe re.
Maloberti. fo r best accuracy. 19 in sim plified fonn [O' Lea ry.:=========='=========:: . Nex t. G M1 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • DC:=:=:===:'.2 . When precision matc hing between transistors is requ ired . even when this mea ns adding extra unused componen ts. hel ps match errors caused by gradient effects across a microci rcu it.J • • • • • • • II! • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • G M2 M2 Fig. 1991 . ca pacitors. T hese other effects inc lude tho se ca use d by boundary co nditions of an object. Th ese inaccu racies also affec t the ratios of sizes. .4 Analag layaut Cansideratians 107 ncnt sizes. they are commonly laid o ut usin g multi plegat e finger s si milar to the layout shown in Fig. 19941. An exa mple of a co mmo nce ntroid layout of two identical matched transistors whos e sources are co nnected is shown in Fig.. 19941. then not o nly sho uld the indi vidu al tra nsistors be reali zed by co mbining a singles ized unit tran sistor. such as the temperature or the gateoxide thickness changi ng across the microci rcuit. the boundary conditions around all objects should be matched. 2.. but the fingers for on e tra nsis tor sho uld be inte rdigitated with the fingers of the second transistor. For these reasons. altho ugh to a lesser degree . 2. when the ratio is not un ity (unless the secondorde r size error effects are matched). For this reason. and resistors. Transistor Layouts Transistors in analog circuits are typically much wider than transistors in digital circuit s. Also. and the unevenn ess of the su rface of the microcircuit [Ma loberti. Matc hing secondorder size error effects is done mainly by mak ing larger objects out of several unitsized compo nents connected together. the size of the opening in a protective layout th rough whic h etching occurs. 2 . 17. we give so me examples of how to ap ply these principles with regard to rea lizing tran sistors. 19 A cornrnoncenfroid layout for a differential sourcecoupled pair. known as commonce ntro id layo ut. This approach. the abso lute sizes of microc ircuit components ca n se ldo m be acc urately determined .
and therefore one outside finger is used for M I and one is used for M.. Inside the structure. capacitor size is given by (2. Ideally. each of the individual transistors should be realized from a single unitsized transistor.similar to what is usually done for transistors. Forexample. this commoncentroid layout is not typically used except where very accurate capacitors are required. This layout technique greatly minimizes nonidealities such as opamp inputoffset voltage errors when using a differential pair in the input stage of an opamp. and so on. When it is not. if we assume that a capacitor has an absolute overetching given by . if a current ratio of 1:2 were desired. good designers strive to realize circuits in which only unitsized capacitors are needed. Thus. fingers would only be included for better matching accuracy and would have no other function. the fingers occur in doublestwo for M" two for MI .108 Chapter 2 • Processing and layout Each of the two transistors is composed of five separate transistor fingers connected in parallel. Errors due to the gradient of the oxide thickness can then be minimized by interspersing the unitsized capacitors in a commoncentroid layout so the gradient changes affect both capacitors in the same way. the layout is symmetric in both the X and y axes. For example. Thus. whereas the second capacitor might be realized by six unitsized capacitors. The gates of these dummy fingers are normally connected to the most negative powersupply voltage to ensure they are always turned off (or they are connected to the positive power supply in the case of pchannel transistors). two for M2 . The former effect is usually dominant and can be minimized by realizing larger capacitors from a parallel combination of smaller. The outside fingers have separate secondorder size effects. and any gradients across the microcircuit would affect both M I and M2 in the same way. Unfortunately. analog circuits require precise ratios of capacitors. then the input transistor might be made from four fingers. When current mirrors with ratios other than unity are required. Specifically. for the greatest accuracy. whereas the output transistor might be realized using eight identical fingers. all fingers should be inside fingers only. Capacitor Matching Very often. If only unitsized capacitors are used. In addition. to realize two capacitors that have a ratio of 4:6.13) The major sources of errors in realizing capacitors are due to overetching (which causes the area to be smaller than the area of the layout masks) and an oxidethickness gradient across the surface of the microcircuit. overetching error can still be minimized by realizing a nonunitsized capacitor with a specific perimetertoarea ratio. again. the first capacitor might be realized from four unitsized capacitors. Outside. first note that the error due to overetching is roughly proportional to the perimeter of the capacitor. then any overetching will leave the capacitor ratio unaffected. this situation is not always possible. To determine the correct ratio. unitsized capacitors. or dummy. Since oxidethickness variations are not usually large in a reasonably small area.
E r :: .16) The relative error in the capacitor is therefore given by boG.'" Cideal 2boe(x l + YI) X\Yl (2. 2. '" 2boe(x l + YI)G O X (2. their perimetertoarea ratios should be kept the same. we see that the relative errors are the same if they both have the same perimetertoarea ratio.. Normally. if the errors were not small. (2.4 Analog Layout Considerations 109 boe and that its ideal dimensions are given by XI and YI' then its true dimensions are given by XIa = XI . This ratio is given by GI(1 +E rl ) Go(1 + E.2boe) (2. which is reasonable since. When a nonunitsized capacitor is required.14) This situation is illustrated in Fig.. the relative capacitor error is approximately proportional to the negative of the ratio of the ideal perimeter to the ideal area (assuming only small errors exist. then that capacitor sizing would probably not be used). Using (2. rather than their absolute sizes.17).e .2. and the true capacitor size is given by G a = GoxxlaYla = GOx(xl .) If the two capacitors have the same relative errors (i. Capacitor errors due to over .2boe)(YI . the unitsized capacitor will be taken square. This leads to the following result: To minimize errors in capacitor ratios due to overetching. then their true ratio is equal to their ideal ratio even when they are not the same sizes. it is usually set to between one and two times the unitsized capacitor and is rectangular in shape. Thus.15) When this error is small.. so that it has the same number of corners as t>e True capacitor size Ideal capacitor size Fig.18) En = Er2)..2boe.2boe and YIa = YI . even when the capacitors are different sizes. the error in the true capacitance is given by (2. 2.17) Thus.20 etching. When we realize two capacitors that have different sizes. then the secondorder error term can be ignored and (2.20. usually the ratio of one capacitor to the other is important.15) can be approximated by boG.
3 Show a layout that might be used to match two capacitors of size 4 and 2.24).25) which can be solved to give (2. respectively. we find the quadratic equation y. except this nonunitsized capacitor is now rectangular. are similarly defined.23) and (2. we have (2.26) is applied to a positive number. and sidelength of a unitsized capacitor. which ensures that the square root in (2.314 units. Rearranging (2. + y. 2x I (2. we have (2. Defining K to be a desired nonunitsized capacitor ratio. PI = A. is then given by (2.20) where P I and P.2Kx y + KX. represent the perimeters of the two capacitors. . l = 0 (2.20). EXAMPLE 2. . + y. area.19) where C I .110 Chapter 2 • Processing and Layout the unitsized capacitor.21) which implies that K can also be written as the ratio of perimeters. . Equating the ratios of the perimeterstoareas implies that P.26) Recall that K is assumed to be greater than one. K= This can be rearranged to become x.24) Combining (2.19).22) ! f x.23) (2. AI' and XI represent the capacitance. Variables C" A" x" and y. Also rearranging (2. we have (2. Al (2. where a unitsized capacitor is 10 urn x 10 urn .24). The value for x.
314 units. We break the 2.314 units A capacitor layout with equal perlmerertocreo 4 units and 2.314) = 19. the choice of sign affects only the rectangle orientation. The lengths of the sides for this rectangular capacitor are found from (2.21 ratios of 2. we have the capacitor layout as shown in Fig.314 units. Several other considerations should be followed when realizing accurate capacitor ratios. . Each capacitor in the 6.26). Thus. The parasitic capacitances of these tabs should be matched as much as possible. Usually the bottom plate of capacitors will be the first layer of polysilicon or. in some technologies.2. It is usually possible to realize the bottom plate over the top of a well region that has many contacts connected to a lownoise powersupply voltage.314unit capacitor up into one unitsized capacitor in parallel with another rectangular capacitor of size 1. and the polysilicon plates must be interconnected through polysilicon tabs at the sides.. which are almost always polysilicon. an ionimplanted region. Solution Four units are simply laid out as four unitsized capacitors in parallel. resulting in y.5. These tabs will contact to metal in a region where the bottomplate polysilicon is not present.lrn ll l 19. in other words. 2. Another common matching technique is to ensure that the boundary conditions around the unitsized capacitors match. = 10 Ilm(1. This well region acts as a shield to help keep substrate noise out of the bottom plate of the capacitor. 2.22." The interconnection of the top plates. This boundarycondition matching is accomplished by adding additional topplate polysilicon around the outside boundaries of unitsized capacitors at the edge of an array. 2.314 2  1.4 Analog layout Considerations III 10 urn 10J. can often be done in firstlevel metal with contacts to the polysilicon plates. which is the same as the ratio for the unitsized capacitor.314 ± J1.6 urn 6.561lm or 6. This region is usually common to many unitsize capacitors. Many of these principles are illustrated in the simplified layout of two capacitors shown in Fig. In some technologies this is not possible.717Ilm Either of these results can be chosen for y" and the other result becomes x.72 urn 4 units Fig. This matching often entails adding additional tabs that are not connected anywhere.21 Note that the ratio of the area of the rectangular capacitor to its perimeter equals 2.
whereas the bottom plate ca n be co nnected to less critical nodes suc h as opamp outputs. O ther choices incl ude diffused o r ionimplanted regions such as junctions. Thi s sa ndwic h. the interes ted reader can see fAllstol.22) is to cover the top plates with the first layer o f metal . Another possibility is deposited and etched thinfilm resistors suc h as nichro me (consisting of 80 percent nickel and 20 percent chromium) or tantalu m. Th e ca pac ito r plate formed from the "sandwiched" top level of polysilicon is then connected to critical nodes. Resistor Layout Integrated resistors can be realized us ing a wide variety of different co nductors. Th e temperature coefficient of ionimplanted or diffused resistors lends to be posi tive and large (espe . An addi tio na l technique so me times used (not show n in Fig .112 Chapter 2 • Processing and l ayout Well contacts Polysilicon bottom plate PolysHicon top plates Polysilicon edge matching Well region Fig.like struc ture nol o nly gives additional capac ita nce per area but mort importantly . . fig ure consists of two unitsized capacitors. which is a deposited and etched male rial. A popular choice is polysilicon. Therefore the lOp plate should be co nnected to critical nodes such as the virtual in put s of opamps. 1983: O ·Leary. which is then co nnec ted 10 the boltom plate. 2. An important consideration when using capacitors in switchedcapacitor circuits is that the bottom plate usuall y bas mo re noise co upled into it than the lap plate because of the large parasi tic ca paci tance be lween the bottom plate and the silico n region.22 A simplified layout of a capa citor array. 1994] . For more details concerning the realization of integrated capacito rs. shields the lop level of ! pol ysil icon from elec tro mag netic interfe rence in the air. 2. or base regions. such as the virtua l inputs o f amplifie rs. 199 1: Maloberti. wells.
which we assume are electrons. In a modem process. and the six bends contribute 12. nonlinear resistance varies greatly with voltage because the depletionregion width is dependent on voltage in the more heavily doped conductive region. Regardless of the type of resistor used. 8 To obtain mediumsized resistors. Tbis depletionregion width variation is substantially smaller in a polysilicon resistor. For the structure shown. a polycide.l (2. the typical resistivity encountered in integrated circuits is small. Thus. The total resistance is then given by L R = R D W (2. 1977]. Grebene. one must usually use a serpentine layout similar to that shown in Fig. When thinfilm resistors are available in a particular technology. 1987. The positive temperature coefficients are primarily due to mobility degradation that results from temperature increases.e.11 squares" [Glasser. and the gate layer is not useful for realizing moderatesized resistors. This equation is valid for resistors with electron carriers.66 squares.lID = 1. In implanted and diffused resistors. and No is the concentration of carriers. the equations governing the resistance (see the Appendix of Chapter I) are given by (2. When calculating the resistance of such a structure. perhaps 150/0. or silicide. where the gates are formed from a sandwich of a refractory meta] over polysilicon.28) where L is the length of the resistor and W is the width of the resistor. negative temperature coefficients for specially doped.29) 7. Often. For resistors with holes as carriers. then the resistivity is much smaller. For example.23. they would have contributed 2.659 k!. the two contacts contribute 0. the total is 82.' t is the thickness of the conductor. p = I/(q~nNo) is the resistivity.lID. one must make allowance for the bends and for the end contacts. 9. On the other hand. which is one of the major reasons polysilicon resistors are preferred over implanted resistors even though they often require more area due to the low resistivity.000 ppm/X'.94 squares.94 D x 20 !. and each bend contributes 2. If the bends had been semicircular rather than square.27) where R D is the resistance per square. 1. the typical resistivity of the polysilicon layer used to form transistor gates is about 20 !. they are almost always the preferred typeunfortunately. p = tI(q~pNA)' 8. i. If the resistivity of the resistor is 20 !. the temperature coefficient for thinfilm resistors can be as small as 100 ppm/X'. highresistivity polysilicon. the contact structure chosen contributes 0. each finger contributes 10 squares each for a total of 70 squares. then the total resistance is R = 82.000 to 3. . they are seldom available. Polysilicon resistors usually have large positive temperature coefficients (say. 2..96 [J each.2. For example. 1984].28 squares.000 ppm/PC) for lowresistivity polysilicon ranging to moderately large.lID.4 Analog layout Considerations 113 cially for larger resistivities) with values as large as 1. Polysilicon is the layer most commonly used to form resistors inside microcircuits.14 squares [Reinhard.
2.114 Chapter 2 • Processing and la yout 0 . should be added to give a total resistance of abOUI 1. layout for a resistor . 2. Note that quite large structures are required even for relativel y small resistances when gate poly is used to realize the resistor.24 A more accu rate.70 kQ. 2.23 A typical layout for a n integrated resistor. about 20 Q per coni act. When very accurate resistor rati os are required and the ratio can be expre ssed as a rat io of integer values. To this value. but larger. an additi onal impedan ce due to the contact s.14 0 • 10 0 4 2.24 can be Dummy resistor Dummy resistor Fig.110 • • Fig. then an architecture similar to that shown in Fig. .
(Noise is due to capacitive coupling between the substrate and a large resistor structure. For modelling purposes. which can inject very large current spikes. 1994]. At a very minimum. although it will result in a corresponding increase in capacitance. Ideally. 2. the substrate can be modelled as a number of seriesconnected resistors with the p" ground connections modelled as resistordividers . the reader is referred to [O'Leary. it is still possible to use two different bonding wires extending from a singlepackage I/O pin to two separate bonding pads on the integrated circuit. By having the analog power supplies separate. For lownoise designs. Noise Considerations Some additional layout issues help minimize noise in analog circuits.) Also. even if a single bonding pad is used for both analog and digital circuitry. In the ideal case. The p + connections to ground help keep a lowimpedance path between the substrate and ground. This structure might result in about 0. which is available in many SPICElike simulators. Maloberti.26 shows. With analog circuits. For more information on realizing accurate resistor ratios. 2. two dummy fingers have been included to match boundary conditions.1 percent matching accuracy of identical resistors if the finger widths are relatively wide (say. Another common precaution is to layout the digital and analog circuitry in different sections of the microcircuit. sometimes multiple pins are used for additional supply and grounds for very large microcircuits. as Fig. another pair of pins may be used for the supply voltage and ground for digital output buffers. it is a good idea to place a shield under a resistor that is connected to a clean power supply. The resistor consists of several fingers connected at their ends using lowresistivity metal. as Fig. two separated nets from the bonding pad out should be used for the different types of circuitry.8!im technology).25 shows. Most of these issues either attempt to minimize noise from digital circuits coupling into the substrate or analog power supplies. In addition. a glitch is injected on the digital power supply and in the surrounding substrate. or try to minimize substrate noise that affects analog circuits.4 Analog Layout Considerations 115 used. it is critical that different powersupply connections be used for analog circuits than for digital circuits. Every time a digital gate or buffer changes state. As with integrated capacitors. these duplicate power supplies are connected only off the chip. the parasitic capacitance between the resistor and the shield should be modelled during simulation. Also. This approach matches errors caused by the contact impedance between R 1 and R 2 .2. Finally. separate pins are used for the positive power supply and for ground in both the digital and analog circuits. 1991. This shielding helps keep substrate noise from being injected into the conductive layer. The two sections should be separated by guard rings and wells connected to the powersupply voltages. Its secondorder effects on circuits such as RC filters can often be eliminated using optimization. An appropriate shield might be a well region. we prevent this noise from affecting the analog circuitry. The reason the powersupply interconnects must be separated is that the interconnect does not have zero impedance. Where a single l/O pin must be used for the power supply. a metal shield over the top of a resistor may also be necessary. lO!im in a 0.
the p.. I ..:.. The use of the n well between p + connections helps to further increase the resistive impedance of the substrate between the analog and digital regions due to graded substrate doping. having a small impedance to ground.26 Separating analog and digital areas with guard rings and wells in an attempt to minimize the injection of noise from digital circuits into the substrate under the analog circuit.27 shows examples of the use of shields. Specifically. 1 . In this example. This +Analog regIon Digital region + Fig. the n well also operates as a bypass capacitor to help lower the noise on VDD' Another important consideration when laying out a circuit that includes both analog and digital circuits is the use of shields connected to either ground or to a separate powersupply voltage..... Digital powersupply net ! I Fig.. . an n well is used to shield the substrate from the digital interconnect line.. These lowimpedance ground connections help keep substrate noise from propagating through the resistive substrate.. Finally. The well is also used to shield an analog interconnect line from any substrate noise..substrate often has 10 times higher doping at the surface of the microcircuit compared to the doping level below the n well..116 Chapter 2 • Processing and Layout f ~ lIO pad Analog powersupply net .. p + connections. which leads to a tenfold increase in substrate resistivity between the twa...25 Using separate nets for analog and digital power supplies... 2. Figure 2..2.
two ground (Gnd) lines. A well is placed und er the clo ck lioes as a shield. perpendicular to the metal I interconnect lines . it also help s prevent latchup. which is connected to V OD ' Additi onal layer s that me often used as shields are the polysili con layer s. Careful thought should go into the overall placem ent of different block s in a mixedmode analog digital microcircuit. the shie ld ground is also connected to metal lines that se parate the analog and digit al lines from each other and from other interconnect lines. an additional metal shield might be placed above the lines as well. For subrnicron technologies. Any charge flowin g through the substrate is attracted to this layer and doe s not propagate into sensitive analog s regions.27 Using shields helps keep noise from being copocitively coupled into and out of the substrate. as is used in the critical o pamp sec tion. An epitaxial process place s 0 co nductive layer und er all transistors. Perhaps the most effective technique for minimi zing the propa gation of sub strate noise in a mixed mode microcircuit containing both analog and digital circuitry is the use of an epitaxial process. A possible arrangement for an analo g sec tion ontaining switchedcapaci to r circuits is shown in Fig . This final shield may be somewhat exc essive . then the digit al ground con be used for the shields. and a V DO line . shield is ideally conn ected to 0 ground net that is used only for shie lds.2. 2.4 Analog layout Considerations 117 Ground line used for shielding Analog interconnect Digital interconnect p. Also note that a separate V DO line is used to connect to the n well s under the switches.2 8. this ep itaxial process is becoming more common because of its reduced latchup sensitivity. Notice that an n well shield is beio g used under the capa citors. Although this process is more e xpen si ve. Finall y. If this type of connection is not possible due to layout and space constraints. It should also be mentioned that the n well shield also acts as a bypa ss capacitor. . Notice also that the cloc k lines are oat only as for from the opamp s as possible. this helps minimize noise in the substrate. but it can often be easily realized in many parts o f the microcircui t if ground and powersupply lines are distributed in metal 2. althou gh this is not ideoI. a region where digital interconn ect s exi st. In the example. substrate Fig. 2. Thi s shield is connected 10 a separate ground line (perhaps digit al ground) from the one used in the opamp region because this shield will likely have quite a bit of clo ck noise coupled into it. but are also separated by two well s and a Vss interconnect that is liberally conn ected to the substrate.
Many other techniques have been deve loped by vario us com panies . which are used as bypass capacitors.11 8 Chapter 2 • Processing a nd layout Voo Opamp 1 Opamp2 Opa mp 3 Contact to substrate Vs s } Opamps • n well undercapacitor region • Gn d } Vaa Capacitors Region for nchannel switches Switches • n well under pehannel switch region • Gnd n well shield and bypass capacitor Fig. but the preceding techniques give the reader a good idea of the types of practical conside rations necessary when realizing highperformance analog microcircuits. this resu lts in a significant increase in bypass capacitance.5 LATCHUP One of the effects that CMOS designers must be wary of. is latch up. all)' lint/sed space sho uld be fi lled with additional contacts 10 both the substrate and 10 the wells. 2 8 A possible floor pion for on analog section containing switchedeopocitor circuits One last technique for noise minimiza tion in analog microci rcuits should always be used: After layout has been finished. . These triggering voltage drops often occur when power is first applied to a CMOS microcircuit. large substrate or well voltage drops . 2. 2. This effect can occur when there are relatively large substrate or well currents or. that might be caused by capacitive coupling. equivalently. In a typical microcircuit. especially as dime nsions shrink.
30 along with some of the parasitic resistances due to the lightly doped substrate and well regions. 2. 2. This SCR effec tively shancircuits the power supply on the microcircuit and.7 V 0. and (b) the voltages after latchup has occurred . However. the parasitic bipolar transistors are off.29 Cross section of a CMOS inverter with superimposed schematic of the porositic tra nsistors responsible for the latchup mechanism. and O' c0 . The circuit realizes two crosscoupled commonemitter amplifiers in a positive feedback loop. To understand latchup.9 V Vee = 5 V R. Q2 0. and the voltages are as shown in Fig.5 LctchUp 119 A latchedup microcircuit is equivalent to a turnedon siliconCOli/rolled rectifier (SCR) between the power supply and ground.2. Normally. Q2 OV V".2.. Vee = 0. is a venical p np. which is sometimes referred 10 as a crowbar switch. 2.). . Thi s is the equivalent circuit of an SCR.2 V Rp Rp (a) Fig. whereas 0 .30(.30   (b)  10) The equivalentcircuit of the porasitic bipolar transistors.o1 5V R. substrate Fig. 2. irreparable damage will probably occur (such as a fused open bonding wire or interconnect line). The parasitic bipolar circuit has been redrawn in Fig. if latch up is somehow triggered. unless the supplycurrent is limited. consider the cross section of the CMOS invener shown in Fig. they tum on when the Q2 p. with the base being formed by the nwell region . with the base being formed by the p: substrate. is a lateral npn.29 with the parasitic bipolar transistors 0.
especially one with highly doped buried layers. Alternatively.30(b). and most importantly. Latchup can be triggered in several ways. with typically used spacings. the output of the CMOS inverter. the voltages are approximately those shown in Fig. The current gain of the lateral n p n can be decreased by larger spacings between nchannel and pchannel transistors.and pburied regions and an intrinsic epitaxial region that is separately and optimally ion implanted to form the nchannel and pchannel regions. For example. The loop gain is kept less than unity primarily by decreasing a. the loop gain of the crosscoupled bipolar inverters must be kept less than unity. ensuring that the back of the die is connected to ground through a eutectic gold bond to the package header is helpful. R n and R p are decreased mainly by having lowimpedance paths between the substrate and well to the power supplies. which connects the substrate to ground.9 V. any transistors that conduct large currents are usually surrounded by guard rings. the design rules normally specify a maximum distance between any place in the nchannel region of the microcircuit and the closest p + junction. device performance is only marginally affected. Also. One way to achieve these lowimpedance paths is to have many contacts to the substrate. that completely surround the highcurrent transistors. Q2' might be 50 to 100 and is difficult to minimize. Alternatively. and a. Also. then excessive current will flow and some portion of the microcircuit may be destroyed. One of the best ways of preventing latchup is to use an epitaxial process. If the inverter is large Cas in the case of an output buffer). This turnedon SCR effectively places a shortcircuit across the powersupply voltage and pulls VDO down to approximately 0. In addition. with an nwell technology. If the power supply does not have a current limit. For example. or to the n well for pchannel transistors. and as a result. Similarly. in the pchannel regions. the maximum distance to the nearest n + junction. glitches will be capacitively coupled to the base nodes of the parasitic bipolars and may cause latchup. This low loop gain is normally achieved by keeping the current gains of the parasitic bipolars as low as is possible. 2. one might use a p. if a p + substrate has a pepitaxial layer in which the transistors are placed. is capacitively coupled to the bases of the bipolar transistors by the junction depletion capacitances of the MaS drains. which connects the n wells to VDO. but the highly conductive p + substrate has very little impedance to ground contacts and to the package header. For example.29.120 Chapter 2 • Processing and Layout loop gain is larger than unity. . When the output of the inverter changes. by keeping shunting resistors R n and R p as small as possible. This selfaligned twintub technology is very immune to latchup due to the highly conductive buried layers. is specified. after layout is completed. These guard rings are connections to the substrate for nchannel transistors. To prevent latchup. Vinv in Fig. substrate currents caused by hotcarrier electrons can also result in voltage drops large enough to trigger latchup. these capacitances will be large. The current gain of the vertical pnp. 2. a good designer fills any unused areas with extra connections to the substrate and well regions.substrate that has n + . the product ~npn~pnp is still normally greater than I. However.
" in Design of AnalogDigital VLSI Circuits for Telecommunication and Signal Processing. WileyInterscience. 256K BiCMOS"SRAM Technology. "Practical Aspects of Mixed Analogue and Digital Design. F. Grebene.8llffi. pp. ed. Bipolar and MOS Analog Integrated Circuits. R. Allen. R. Englewood Cliffs. Haveman. Peter Peregrinus. 1989. Haveman. R." in AnalogueDigital Asics.4 x 10 pF/(~m) 4 C j • sw = 2. and N. Geiger. introduction to integrated Circuit Engineering. New York. Design Tools.9 X 10.n • . Nowell. Haken. S. no. Academic Press.6 REFERENCES D. Maloberti. Allstot and W. Maloberti. New Jersey. R. 8. England. O'Leary. AddisonWesley. 967986.7 PROBLEMS Unless otherwise stated. Houghton Mifflin. Black." IEEE Proceedings. 1987. P. Integrated Circuit Engineering: Design.0 x 10 pF/~m 3 Cox = 1." in BiCMOS Technology and Applications. McGraw Hill. Alvarez. VIS!: Design Techniquesfor Analog and Digital Circuits. Ekund. A. and J. ed. 1977. pp. and Applications. A.2. F. Circuit Techniques. Massachusetts.9 Y Y = 0. "Technological Design Considerations for Monolithic MOS SwitchedCapacitor Filtering Systems. "BiCMOS Process Design. Prentice Hall.5 y ' /2 rds (0) = 8. R. Tsividis. A. Stevenage. J. 1984. 1991. Wiley. August 1983. December 1987. New York. 2. p. 1990. S.8 v'" rds (0) = 12. Boston.0 X 104 pF/~m pchannel MOS transistors: ~pCox = 30 ~A/y2 Vip = 0. SubakSharpe. P. 841843. "Layout of Analog and Mixed AnalogDigital Circuits. and L Hutter.OOOL (!ffil)/Io(mA) in active region 4 2 Cj = 2.OOOL (~m)/Io (rnA) in active region 'b • . assume the fol1owing hola throughout the problems section: • npn bipolar transistors: ~ = 100 VA = 80 Y = 13 ps 't s = 4 ns rb = 3300 nchannel MOS transistors: 2 ~nCox = 92 ~A/Y V = 0.8 Y Y = 0. Franca and Y. i987 Intern. Vol.pF/(~m)2 Cgs(overlap) = Cgd(overlap) = 2. ed. and Applications.7 Problems 121 2. Muraka and M. Electronic Materials. et al. Peckerar. Fabrication. 1989. Reinhard. R. Strader. Franca. Massachusetts. 1994. "A O." Digest of Technical Papers. New York. Kluwer Academic Publishers. Glasser and G. 326. Electron Devices Meeting. D. Soin. Reading. 71.
p olysilicon ~ ••~. P2.. Simpl ify the circ uit. = 4 .10 Find the transistor schematic for the CMOS logic ci rcui t rea lized by the layout shown in Fig .%.4 2.0 X 10 "" pF / ~ m 2..9 X 10 Ci s W = 2. What are the major problems associated with a sing le threshol dvo itageadj usl implant' What is the reason for using a field implant and why is it often not need ed in the well reg io ns' What are the major tradeoffs in using a wet process o r a dry process when growing thermal Si02 '! Why is polysi licon rat he r than meta l used to realize ga tes of MOS tran sistors? Why can't a microcircu it be annealed after metal has bee n deposited"! sepa rate d from po lysi licon"! Why"! 2.2 Place the following processing steps in their correct order: metal deposition and patterning.122 C hapler 2 • Processing and L ayaul C . 1 Discuss briefly the relationships between an ion beam's acceleration potential. Assu me L = 21. Gi ve the widths of all transi stors .% // / I ¥ r : Active region :::C1 I . Assume L = 21.:i / J /j/ ..5 2. and give the sizes of all tran sistors.8 W hat minim um distance . in terms of A. ~ Metal  ~ ~ 'le// Fig.. b c :.7 2. we ll impl ant ation. junction implan tation. a r r. P2. . where A = I 11 m.. fieldoxide g row th . 10 3 ' pF / ( ~ m r pF / ~m 2. if possible. _ 1 ~. and the time of implantation on the resulting doping profil e . field implantation.5 C o.. the beam current.5 .10. polysilicon deposition and patterning. = 1.9 Find the circuit that the layo ut shown in Fig . ////// ~". . wo uld yo u ex pect that metal should be 2.9 reali zes.9 2.~.. X 10 X p F/( ~m) ' C gs< overlaPI = C g d< overlaPI = 2./j0 ~ 4 101.~. P2.3 2.6 2.
15 Given that a unitsized capacitor is 5 urn x 5 urn and that the ebearn lithography rounds all sizes 10 0.4 um.) 2. 2. . but assume 2 para llel tra nsistors.2 where an overall transistor width of 801.1 for the case in which the IwO transistors do not physically share any junction. each of width 101..14? What is the new matching accuracy if the capacitor sizes are doubled to 18 and 9. give the area and perimeter of each junction that is not connected to V oo or 10 ground. what is the matching accuracy due to rounding of the capacitors found in Problem 2. Sketch a layout for Ihe two capacitors such that their ratio will be maintained during overetching. are used . 2.523 . P2. 16 . what is the resistance of a long line that is 2 u rn wide and 1.10 2.046? Given that a polysi licon layer has 7 0 1 0 . but assume 8 parallel transistors. are used.13 Repeal Example 2..2.12 2. n well • • • • A B p diffusion Active region Ou t n diffusion Metal ~ c Gnd Fig. Repeal Example 2. In tabular form.7 Problems 123 where A = 0... each of width 401. 14 We desire to match two capacitors of relative sizes 9 and 4 .2 where an overall transistor width of 801.. is still des ired.1 urn. 2. is still desired.000 urn long? (Ignore any contact rcsistance. but each junction is realized in a way similar 10 junction J. 11 Repeal Example 2..
23.124 Chapter 2 • Processing and layout 2. as shown in Fig. 2. What is the resulting height and width of the overall resistor layout? . where enough bends are used such that a line drawn along the middle of the serpentine resistor has length 1.000 urn (the last finger length might be short).17 Repeat Problem 2.16 for the case in which the resistive line is laid out in a serpentine manner.
I" was replaced with an open 125 . most of the smallsignal analyses presented can be applied to bipolar circuits with little change. singlestage amplifiers with active loads. Although some bipolar circuits are described. then 0. CMOS mirrors and gain stages are emphasized because modern designs mostly make use of CMOS technology. A good knowledge of these building blocks is critical to understanding many subjects in the rest of this book and for analog IC design in general. Fortunately.at the output node. and it is assumed that both transistors are the same size.1. when finite output impedance is considered. To find the output impedance of the current mirror. fundamental building blocks are described..2(a). in which it is assumed that both transistors are in the active region. These blocks include a variety of current mirrors.. the smallsignal impedance looking into the drain of 0" to be less than infinite. Finally. where ix is the current flowing out of the source and into the drain of 0. alone. Before finding f o ut ' consider the smallsignal model for 0. foul is given by the ratio vJi x .1 SIMPLE CMOS CURRENT MIRROR A simple CMOS current mirror is shown in Fig. 3.CHAPTER Basic Current Mirrors and SingleStage Amplifiers In this chapter. Note that 0. the finite output impedance of the transistors will cause the smallsignal output impedance of the current mirror.e. although it is assumed that most readers are already somewhat familiar with them. Vqs ' However. rau" the smallsignal circuit is analyzed after placing a signal source. and differential pairs. v x. is diode connected (i. In addition. the gain stages covered are shown with currentmirror active loads since such loads are almost always used in integrated circuits. as shown in Fig. whichever transistor has a larger drainsource voltage will also have a larger current. If the finite output impedances of the transistors are ignored. In addition. 3. rather than using resistive loads and ac coupling. and 0. its drain and gate are connected) and that Ii' does not exist in the smallsignal model. singletransistor amplifiers are described here for completeness. will have the same current since they both have the same gatesource voltage. Then by definition. 3. that is.
This same result holds in the bipolar case and is also equivalent to the smallsignal model for a diodehence the name diodeconnected transistor. Also note that a lowfrequency smallsignal model is used for 0 1 (i. the circuit is simplified to the equivalent smallsignal model shown in Fig. The Theveninequivalent output voltage isO since the circuit is stable and contains no input signal.. as shown in Fig. 3. 'v = +gmI V g S l = vy rdS I (3. Here. This should come as no surprise. This circuit's Theveninequivalcnt output impedance is found by applying a test signal voltage.3(b).2 101 The smallsignal model for Q. Thus. v gs2 equals 0 no matter what voltage level V x is applied to the currentmirror output. since 9m'v gs z = 0. _ (a) (b) Fig. and Ibl the equivalent smal~signal model for Q. This smallsignal model can be further reduced by finding the Theveninequivalent circuit. v.e. 3. as shown. 3. the output impedance equals 1/9ml "rd S I ' Because typically rd S I » 1I9ml' we approximate the output impedance to be simply 1I9ml (which is also defined to be rSl ) .3(a). the current iy is given by . 3. 10 ". all the capacitors are ignored in the model).2(b).126 Chapter 3 • Basic Currenf Mirrors and SingleStage Amplifiers I~ I Q.1) and recalling that the output impedance is given by vyli y .... Fig. """l14l~ . since MOS transistors operate unilaterally at low frequencies.1 A simple CMOS current mirror. 3.rout Q. iy . The smallsignal output impedance. circuit because it is an independent current source. where V gS2 has been connected to ground via a resistance of 119m I' Since no current flows through the 119mI resistor. Using the model just described leads to the simplified smallsignal model for the overall current mirror. v y ' at VI and measuring the signal current. :~ a. is simply equal to roez . which results in the equivalent model shown in Fig. rout.
then a 0. if initially lout is measured to be 101 u... 3...5 V increase in output voltage would result in a . find rout for the current mirror and the value of 9ml' Also.3) resulting in rs l = 119m] = 935 Q..2) The value of 9ml is given by 9ml = J2!lnCox(W/L)IDI = \.1 Consider the current mirror shown in Fig.V = 128 k Q ! l A rout (34) . 3.:.5 V change in the output voltage. where lin = lOa u A and each z transistor has W/L = 100 !lm/\..~ . V g S2 9m2 Vgs2 . Solution Since the W/L ratios of 0 1 and Oz are the same.. gm. The change in output current can be estimated.Given that !lnCox = 92 !lA/V . Thus.6 urn .... using rout. In other words.1. as AI U out 0.. estimate the change in lout for a 0.8 V and rds = rs. . (!lm)]I[I D (rnA)]..1 (3..: (a) (b) Fig.3 10) A smallsignal model for the current mirror of Fig.5 = 3.1 and simplified smallsignal model. (bl a EXAMPLE 3.000 x \.A (due to mismatch or a larger VDS voltage). V ln = 0. + Ux : .. .:..3. .07 mAN (3.9 = t. Note that this rSI value is significantly less than rdSI' which equals rdsZ in this case. Q..6 = I 28 k •• 0. the nominal value of lout equals that of lin = 100 u A.oon. we have n rout = rdsZ = 8.1 Simple CMOS Current Mirror 127 Q.3.
an nchannel commonsource amplifierhas a pchannel current mirror used as an active load to supply the bias current for the drive transistor. . An active load makes use of the nonlinear.3. as shown in Fig. 3.l load were required with a 100flA bias current. rd S I' and the drain Fig. The output resistance.5 A smallsignal equivalent circuit for the commonsource amplifier. 3. R" is made up of the parallel combination of the draintosource resistance of 01' that is. for a given powersupply voltage. are the Thevenin equivalent of the input source.3. Fig. largesignal transistor equations to create simultaneous conditions of large bias currents and large smallsignal resistances. if a lMf. a highimpedance output load can be realized without using excessively large resistors or a large powersupply voltage. Here. 3. This commonsource topology is the most popular gain stage. 3.4 is shown in Fig. As a result.128 Chapter 3 • Basic Current Mirrars and SingleStage Arnplihers new output current of about 105 flA. r~<lVout R. a resistiveload approach would require a powersupply voltage of I Mf. Vi' and R i. For example. By using an active load. a larger voltage gain can be achieved using an active load than would be possible if a resistor were used for the load.4.4 A commonsource amplifier with a currentmirror active load.2 COMMON·SOURCE AMPLIFIER A common use of simple current mirrors is in a singlestage amplifier with an active load. A smallsignal equivalent circuit for lowfrequency analysis of the commonsource amplifier of Fig. It is assumed that the bias voltages are such that both transistors are in the active region. especially when highinput impedance is desired. Note that this estimate does not account for secondorder effects such as the fact that rds changes as the output current changes.l x 100 flA = 100 V.5.
This resistiveload approach also greatly increases the power dissipation. therefore. therefore. What is the gain of the stage? Solution We have 1.06 mAN (3. currents. rd.6 = 8.1 rnA = 192 kO (3._n(O) = 8.000 x 1. and rd. EXAMPLE 3. that is.. 3. as shown in Fig.3 SourceFollower or CommonDrain Amplifier 129 tosource resistance of O 2 . To achieve similar gains with resistive loads. = 100 !LA. highfrequency stages. and the technology used. is . much larger powersupply voltages than 5 V must be used.4.8) Using Eq. we have Av = 9ml(rd'l II rdd = 1. However.6 !Lm 0.5) Depending on the device sizes.6) Also.4 (3. this source always has 0 current. we have vg'l = vin and._p(O) = 12. Notice that the voltagecontrolled current source modelling the body effect has not been included since the source is at a smallsignal ground. In this example. Using smallsignal analysis.7) = 12.000 x rnA urn = 128 kO 0.6!Lm in Fig. !LpCox = 30 !LA/V'. (3.3.06(12811192) = 81. and. rd". it should be mentioned here that for lowgain.1 and rdS2 (3. it may be desirable to use resistor loads (if they do not require much silicon area) because they often have less parasitic capacitances associated with them. 1. 0 1 is the source follower and 0. a typical gain for this circuit is in the range of 10 to 100.9) 3. I bi.5).2 Assume all transistors have W/L = 100 !Lm/1. (3.3 SOURCEFOUOWER OR COMMONDRAIN AMPUFIER Another general use of current mirrors is to supply the bias current of sourcefollower amplifiers.000L (!Lm)/I D (rnA). 3.6. and that !LnCox = 90 !LA/V'. They are also typically less noisy than active loads.ooOL (!Lm)/I D (rnA).
. it does have the ability to generate current gain. In reality. an active load that supplies the bias current of Q I' These amplifiers are commonly used as voltage buffers and are therefore commonly called source followers. since the input and output nodes are at the gate and source nodes. Note that the voltagecontrolled current source that models the body effect of MOS transistors has been included. Note that in Fig. 3. r dSI is in p1l. This relationship makes the body effect equivalent to a resistor of size IIg s I ' which is also in parallel with r ds l and r d s2' Thus. with the drain node being at smallsignal ground. 3. 3. This body effect is included because the source is not at smallsignal ground and the body effect is a major limitation on the smallsignal gain..10) '.130 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers +_OV o ut ..V out we have (3.. 3. However.7. ideally the smallsignal voltage gain is close to unity. A smallsignal model for lowfrequency analysis of this sourcefollower stage is shown in Fig. although this circuit does not generate voltage gain.<:>V VS1 out = Vs1 Fig.6 A sourcefollower stage with a current mirror used to supply the bias current. 3.... 3.8. . it is somewhat less than unity. the smallsignal model of Fig.rallel with r d s2' Notice also that the voltagecontrolled current source modelling the body effect produces a current that is proportional to the voltage across it. Although the de level of the output voltage is not the same as the de level of the input voltage.. Active load Fig.+....7 is equivalent to the simplified smallsignal model of Fig.7 The lowFrequency model of the sourcefollower amplifier....... They are also referred to as commondrain amplifiers. in which R Sl = rdsIl1 r d" II 119s I' Writing the nodal equation at v aut ' and noting that V gs I = Yin . respectively.7.
= 30 ~A/V2. 9d" and 9d52' might be onetenth that of the bodyeffect parameter.000L (~m)/ID (mA). the transistor output admittances. a consistent methodology should be maintained when writing nodal equations. = 8. j . it is worth mentioning here that the authors have found that.] Fig. where all transistors have W/L = 100 ~m/ 1. This node voltage is multiplied by the sum of all admittances connected to the node.12) Also.3 SourceFollower or CommonDroin Amplifier 131 L+ovoul R.3. we have (3. Yn = 0.6. 3. Whenevera variable is designated G it is assumedthat the variable is an admittance andthat j . Solving for Vout/Yin' we have 9ml + 9s1 + 9d" + 9d52 Normally. and each is multiplied by the connecting admittance.6 urn. = 90 ~A/V2.000 . Therefore.6 0.11) vin 9ml + G" EXAMPLE 3. there is no signal flow from the output to the input. Notice also that at low frequencies the stage is completely unilateral. where Ri is the resistance of the same component.13) I. The next negative terms are the adjacent node voltages. 1. ~pCo. G = I/R i . I bias = 100 ~A. to minimize circuit equation errors.1 rnA ~m = 128 kQ (3. In other words. The last terms are any current sources with a multiplying negative sign used if the current is shown to flow into the node. where G S I = l/R"l Before proceeding. The methodology employed here is as follows: The first term is always the node at which the currents are being summed.5 V ' /2 .3 Consider the source follower of Fig. Av =  vout = 9ml 9ml (3. 9". it is seen that the bodyeffect parameter is the major source of error causing the gain to be less than unity. rdsn(Q) = 8. Repeating. ~nCo. What is the gain of the stage? Solution Notice that many parameters are the same as in Example 3.3.2. 9" is on the order of onetenth to onefifth that of 9ml' Also.8 An equivalent smallsignal model for the source follower.
14) To calculate this parameter. in integrated applications. this voltage is dependent on the application and cannot be known accurately beforehand.10.16) Note that. Notice that v gs l = V S] and therefore the two current sources can be combined into a single current source. we need to know the sourcebulk voltage. (Eq. and then. we include the bodyeffect parameter throughout the analysis. This stage is commonly used as a gain stage when a relatively small input impedance is desired.16 + 1/128 + 1/128 1. 3.11). we have A v  (3. but it is the best one can do without more details.86 VN (3. 9s' If the body effect were not present. .4 COMMONGATE AMPLIFIER A commongate amplifier with an active load is shown in Fig.99 VN. To see this result. f o ut ' is found to be 119 m t at low frequencies. the output impedance of the current mirror formed by O 2 ) is much less than f ds l ' the input impedance. In this model. For example. Another common application for a commongate amplifier is the first stage of an amplifier designed to amplify current rather than voltage. Specifically.15) 1. the gain would be around 0. 3. the input impedance at low frequencies can be considerably larger than 119 m l . it might be designed to have an input impedance of 50 Q to terminate a 50Q transmission line.9. one can simply ignore the body effect for transistors with grounded gates. and that VS8 ~ 2 V. VS8' Unfortunately.132 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers The equation for the bodyeffect parameter.11.16 mA/V 2)2 +0. We therefore have 0. is (3. This is somewhat arbitrary. This simplification is always possible for a transistor that has a grounded gate in a smallsignal model. 3. 3. after the analysis is complete.87) from Chapter I. the voltagedependent current source that models the body effect has been included.5· 9m 9s1 = '' = 0. consider the smallsignal model shown in Fig. as mentioned above. when the impedance seen at Vout (in this case. simply replace the constants 9mi with 9mi + 9si' However. However. and considerably simplifies taking the body effect into account.In this case.159m = 0. as shown in Fig.06 + 0. 1. the fact that this result is so far below unity is mainly due to the bodyeffect parameter. If we use straightforward smallsignal analysis. Here we will assume that 5 V power supplies are being used.7 Using (3. for this example. the impedance seen at Vout is often on the same order of magnitude or even much greater than rds I.06 = 0.
. Fig.] 9ml + 981 + 9dS! G L + 9d" ~.9 A commongate amplifier with a cur rentmirror active load..4 ~ CommonGate Amplifier 133 Active load =.V. we have (3. .. At node V OU1 ' we have vou. ..11 A simplified smallsignal model of the commongate amplifier. .17) vo ut = v. ."""'10 voul R.... 3..JI. .. )Vs ] = 0 Rearranging slightly.rro YOU! Fig. ..3.10 The smallsignal model of the commongate amplifier at low frequencies.( G L + 9d.( 9 m] + 9 . 3.>~ L O2 ~ rout v. b + R. ..: Fig. ) .. .1~ where it should be noted that this gain is approximately equal to 9m]/(G L + 9d")' .3. 9 dS] .
' This increased input impedance must be taken into account in applications such as transmissionline terminations. we have rin = .  Yin 9ml + 901 + 9dol 9ml (3.9do' (3. The attenuation from the input to the transistor source can be considerable for a commongate amplifier when R o is large.20) VOl I + 9do' GL I + 9dol GL Alternatively. io Yin:..18) and (3.:. This rule states that the gain is the ratio of the admittance connected between two nodes.::= Gs Gs + Yin (3..20) to replace Vo' Vin we have (3.. is given by i o = Vol(gml +901 +9dOI)V ou.I == Yin I (1 + RL rdsl J (3.19) = IIr in .' Using (3.22) Yin' using the admittancedivider rule. In some examples..18) and (3.=:c. is about 219m' for low frequenciestwice as large as the expected value of 119m. rin.24) 2.23). we find that the overall dc gain is given by (3.. R L » rdOI)' and so the input impedance for this commongate amplifier is much larger than 119ml' This increased input impedance often occurs in integrated circuits and is not commonly known.... R L is approximately the same magnitude as rdo . R L = rdo" Since.23) = G s Go + ". we have Combining (3.:.9.' the input impedance./G L 9ml + 90' + 9dol Using (3.= I +9do.21) 9ml With the pchannel active load shown in Fig.19) to find the input admittance.:. 3. is much larger than rdol (i.e. divided by the sumof that admittance andthe admittance betweenthe secondnodeandground.134 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers The current going into the source of 0.. This at~nuation is given by  vs1 vin = :. . in this case. the currentmirror output impedance realized by 0.
Note that the current ix sourced by the applied voltage source is equal to the current through the degeneration resistor. Rs.rout Rs Rs Fig. vxixR s + (ds2 (3. Therefore.28) : ~1 0. .25) and (3. Since no current flows into the gate. .13 The smollsignoi model for the sourcedegenerated current source. .26) into (3.12 A current mirror with source degeneration.12.5 SOURCEDEGENERATED CURRENT MIRRORS We saw in Section 3. a sourcedegenerated current mirror can be used.1 that a current mirror can be realized using only two transistors.3. the gate voltage is 0 V.26) Setting ix equal to the total current through 9m'v gs and rds . Rs . gives (3. where the output impedance of this current source was seen to be rds " To increase this output impedance.3.13.27) gives ix = l x 9 m. we have v.25) Also.27) Substituting (3.5 SourceDegenerated Current Mirrors 135 3. The smallsignal model for this current mirror is shown in Fig. 3. o ". note that V gs = vs (3. 3. 3. = ixR s (3. ov 1 9ml ++v x ix Rs '+' v« ix Rs Fig. as shown in Fig.
.4 Consider the current mirror shown in Fig.07 + 0. .)] V Ix =rds2[I+Rs(9m. Vtn = 0.5 V due to the de bias current through it. It should be noted that the above derivation ignores the body effect of the transistor.31) Also..32) Now. as in Example 3. we have (3. making use of (3. As discussed earlier.1.29m· Solution Nominally.6 = 128 b. since the gate is at a smallsignal ground.4. the output impedance is given by rout = 128k[I + 5(1. where lin = 100 ~A.33) Note that this result is nearly eight times the output impedance for a simple current mirror as found in Example 3.+9s.1.07 + I ~8)J = 955 kQ (3. each transistor has W/L = (100 ~m)/(1.1 (3.2 x 1. 3.29). and rds = [8. lout = lin' and thus we find the smallsignal parameters for this current mirror to be 9m2 = J2~nCox(W/L)Iout = 1. we find the output impedance to be given by (3. Assume the body effect can be approximated by 9s = 0. the body effect can be taken into account by simply replacing 9m2 in Eq.8 V.30) where 9S2 is the bodyeffect constant. This result is only slightly different since 9 s is roughly onefifth of 9m' EXAMPLE 3.136 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers Rearranging.)] (3. even though the source of the transistor is not connected to a smallsignal ground. Given that 2 ~nCox = 92 ~A/V . and Rs = 5 kQ.29) where 9ds2 is equal to IIr dS" which is much less than 9m2 (recall that 9m = I/r s)' Thus. in Section 3. in the derivation of the output impedance of cascode current mirrors.000L (~m)]/[ID (mA)].12. (3.000 x 1.[I+Rs(9m2+9s2+9ds.29) with 9m2 + 9s" This substitution results in rout x =. the output impedance has been increased by a factor approximately equal to (I + Rs9m2)' This formula can often be applied to moderately complicated circuits to quickly estimate the impedances looking into a node. = rds. 0.07 mA/V rds2 rv 8. Such an example follows.6 urn). Also note that the voltage drop across R s equals I00 ~A x 5 kQ = 0. find rout for the current mirror..
note that the output impedance looking into the drain of O2 is simply rdsz which is seen using an analysis very similar to that which was used for the simple current mirror. Velf was defined in (1. 3.rdS4[l + rdS2( gm4+ gS4)] .3. There is a disadvantage in using a cascade current mirrorsit reduces the maximum outputsignal swings possible before transistors enter the triode region. Thus. These current mirrors have output impedances that are larger than that of a simple current mirror by a factor of gmrdsthe maximum gain of a single transistor. First. the output impedance is given by rout = rdS4[ 1+ rds.gm4) Thus.36) Fig.54) as (3. .rdS4(rds.(gm4 + gs4 + gdS4)] .6 HIGHOUTPUTIMPEDANCE CURRENT MIRRORS In this section two highoutputimpedance current mirrors are describedthe cascode and the Wilson current mirrors. This significant increase in output impedance can be instrumental in realizing singlestage amplifiers with large low.frequency gains. recall that for an nchannel transistor to be in the active region (also called the saturation or pinchoff region) its drainsource voltage must be greater than Velf . and might be a value between 10 and 100.14 A cascade current mirror.35) (3. the output impedance has been increased by a factor of gm4rdaz which is an upper limit on the gain of a singletransistor MOS gainstage. the output impedance can be immediately derived by considering 0 4 as a current source with a sourcedegeneration resistor of value rdaz Making use of Eq. Cescode CurrentMirrors A cascode current mirror is shown in Fig.34) V elf " VGS  V tn (3. depending on the transistor sizes and currents and the technology being used. and noting that 0 4 is now the cascode transistor rather than 0" we have rout = rds4[1 + Rs ( g m4 + gS4 + gds4)] where now Rs = rdaz Therefore.3. (3. To understand this reduction.29).14.6 HighDutputlmpedance Current Mirrors 137 3.
is V'n (about 0. then they also all have the same Veff and.This loss of signal swing is a serious disadvantage when modern technologies are used that might have a maximum allowed powersupply voltage as small as 3 V. Iou. Since the smallest output voltage. Specifically. we see that (3. = [8. the drainsource voltage of Q.41) rdsz = rds4 := (3. Solution Nominally. Also find the minimum output voltage at Vout such that the output transistors remain in the active region.000L (~m)]I[lo (rnA)]. V04' can be without Q 4 entering the triode region is given by VOS2 + Veff . Given that ~nCox = 2 92 ~A/V . V'n = 0.5 Consider the cascode current mirror shown in Fig. the same gatesource voltages.8 V) greater than what is required. 3.07 mA/V We also have 8. VGSi = Veff + V'n. and r d .138 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers which was shown in (1. we will see how the cascode current mirror c. where lin = 100 ~A and each transistor has W/L = (100 ~m)/(1. 3. is larger than the minimum needed to place it at the edge of the active region. find rou' for the current mirror (approximate the body effect by 0.(ln be modified to maintain large output impedances and yet still allow for near minimum voltages at the output of the mirror.14.000 x 1.38) and (3.29m).1 (3. the drainsource voltage of Q.40) which.6 um) . EXAMPLE 3. is V'n greater than the minimum value of 2Vett.14. therefore.39) Thus. from Fig.37) If we assume all transistors have the same sizes and currents.80) to be given by Veff = 210 (3. the minimum allowed voltage for V0" is given by V0" > V O + Veff = 2V e tt l + V'n S2 (3.42) . Also. = lin' and thus we can find the smallsignal parameters for this current mirror to be 9m4 = J2~nCox(W IL)I ou' = 1. In the next chapter.8 V.6 = 128 kQ 0. again.
6 HighOutputImpedance Current Mirrors 139 Now.. Basically. This feedback arrangement increases the output impedance by an amount equal to I plus the loop gain. which.8 = 1. . otherwise the voltage at the gate of 0 3. we first need to determine Veff: (3.18 V.3. the output impedance is given by fout = 128k[128(1. senses the output current and then mirrors it to lOt.44) Thus.19 + 0. the minimum output voltage is determined to be 2 x 0. in turn. taking into account that 0 4 has source degeneration equal to 119m' (i. lin. the output impedance without the feedback due to at. Assuming fin is approximately equal Fig.The factor of 112 is due to the voltage attenuation from the gate of 0 4 to its source. Note that lOt must precisely equal lin. 3. 0 4 would either increase or decrease. making use of (3. this is a modified Wilson current mirror.15 The Wilson current mirror.35).45) where fin is the input impedance of the biasing current source I in.l5 3 lt is an example of using shuntseries feedback to increase the output impedance [Sedra. shown in Fig. 1991].. is subtracted from the input current. Actually. Assuming all devices are matched.e.07)] = 21 Mn (3. where 0 3 has been added to make the drainsource voltages of 0) and O 2 approximately equal. 3. The loop gain is approximately given byA L " 9mt(f dSl 2 II fin) (3. which is responsible for the 2 factor.3.). Wilson Current Mirror Another commonly used current mirror is the Wilson current mirror. and the negative feedback loop forces this equality. the smallsignal impedance of diodeconnected a.2 x 1.07 + 0. 0 3 would be 2f d s4 . caused by the source degeneration of the diodeconnected a. a.43) To find the minimum output voltage. which improves the absolute matching of lin and lout.
3. and sometimes with an improvement in speed. it should be noted that 0 3 is not required in the Wilson current mirror. is 2V e ll .I6(b) has an nchannel input (or drive) transistor. . 0. 3. 3.:. Without this transistor._r:. a commonly used configuration for a singlestage amplifier is a cascade configuration. For this reason. the smallsignal output impedance would remain the same. 0" and an nchannel commongate cascode transistor. Two examples of cascode amplifiers are shown in Fig. The configuration shown in Fig. This configuration is usually called a foldedcascade stage. but a pchannel transistor is used for the cascode (or commongate) transistor. This minimizes any shortchannel effects. The first is that they can have quite large gain for a single stage due to the large impedances at the output. it is usually slower than the telescopiccascode amplifier because although parasitic capacitances at the source of the cascode transistor are similar in both cases. and 0. the minimum allowed voltage across the current mirror.140 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers to rost. To enable this high gain. + V'n' which is similar to that of the cascode current mirror. The second major reason for the use of cascode stages is that they limit the voltage across the input drive transistor.then the loop gain is given by AL 9 =CCm. the impedance levels of the foldedcascade stage are roughly three times larger due to the smaller transconductance of pchannel transistors as compared to nchannel transistors.:' '" 4 (3. the same drainsource bias voltages. the cascode current mirror is often preferred over the Wilson current mirror.47) which is roughly onehalf the output impedance for that of a cascode current mirror. There are two major reasons for the popularity of cascode stages. Finally. Unfortunately. the current sources connected to the output nodes are realized using highquality cascode current mirrors.:..16. The configuration in Fig. and thus minimizes inaccuracies caused by the largesignal output impedances of the transistors. It allows the de level of the output signal to be the same as the de level of the input signal. before 0 4 enters the triode region. Normally this high gain is obtained without any degradation in speed.l6(a) has both an nchannel commonsource transistor.46) and the output impedance is therefore given by rout == (3. This configuration is sometimes called a telescopiccascode amplifier. 3. the output current would be slightly smaller than the input current because V DS' would be larger than V DS" However. In terms of output voltage swing. It has been included to give 0.7 CASCODE GAIN STAGE In modern Ie design.d':. This configuration consists of a commonsourceconnected transistor feeding into a commongateconnected transistor.
or cascade. 0" was given by y in2 = =9. transistor. with only minor modifications. The analysis of the cascade gain stage is based on the telescopic stage of Fig..p ra.p then the total impedance at the output node is = 9mr out  (3. we found that the lowfrequency impedance looking into the source of the commongate..3. I b ia s ' Assuming I b ias is a highquality source with an output impedance on the order of RL '= 9m.::m::. we know that the impedance looking into the drain of cascade transistor O 2 is app!oximately given by (3. we can use part of the analysis done previously for the commongate stage.16(a). Repeating Eq.7 CascodeGoin Stoge 141 +. and to simplify matters since we are only deriving an approximate solution. From the section on cascade current mirrors.16(b).49) R 2 a . 3. (3.48) The total impedance at the output node is rd2 in parallel with R Lo where R L is the output impedance of the bias current source.16 101 A telescopiccoscode amplifier and (b) a foldedcascode amplifier. which becomes more important with modern technologies having very short channellength transistors.0 Vbias oi Vout t~oV out (a) (b) Fig. To find the approximate lowfrequency gain..51) 9d" I + 9d'2 GL GL ._+_9:. (3. also applies for the foldedcascade stage of Fig.20) here for convenience.d:::S::2 = 9m2 I + (3.50) We have dropped the indices here under the assumption that the transistors are somewhat matched. 3.3._+=9. The same analysis.:s:.
Therefore. one problem in estimating 9ds is that it is voltage dependent. Defining the differential input voltage as v. we ignore the output impedance of the transistors temporarily. We have A = vs2vou' =' 9m 9m2 =' _ 9m 9m2 =' _~(9m)' v G L + 9ds2 V. A differential pair together with a biasing current source is shown in Fig. rather than just knowing that it will be greater than some minimum value. A lowfrequency.n es v" . prudent designers should never construct a design for which successful operation requires knowing the gain precisely. This is a fairly representative number.250..55) .53). 3.n' =' . we have A v = 1. and again assuming all elements are somewhat matched so that the indices can be dropped. 3.142 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers Note that the indices are changed to reflect the fact that is the commongate transistor rather than 0 1.52) a. For example. 9ds' for the different transistors. almost all amplifiers use what is commonly called a differential transistor pair.49) into (3.=' 9ds 1+ 9ds 9d.51).18..n Vs' 29ds9ds2 2 9ds 29ds (3..54) The reader should be cautioned that (3. 3.5 mAIV and rds is on the order of 100 kn.17. is therefore given by = _ 9m Yin2  vs2 = V in 9m 1 9dsl + 2gds (3. 9m Y. smallsignal model of the differential pair is shown in Fig.6 Assuming 9m is on the order of 0.54). EXAMPLE 3.54) is only approximate. Substituting (3. To simplify the analysis. To realize this differential input.l9m The gain from the input to the source of 2 (3. primarily due to the difficulty of accurately determining the output admittance.v>.8 MOS DIFFERENTIAL PAIR AND GAIN STAGE Most integrated amplifiers have a differential input. we have a. This smallsignal equivalent circuit is based on the T model for a MOS transistor that was described in Chapter 1.18) and (3. what is the gain of the cascade amplifier? Solution Using (3.53) The overall gain can then be found using (3. we have (3.
3. since id 2 = iS2 = i d I' we find that id2 = Yin 9mt 2 (3.3.56) id l = Vln 9mt 2 Also.8 Mas Differential Pair and Gain Stage 143 V" 01 Fig.58) Thus. we have (3. v " v Fig. ignoring transistor output impedances. Since both 0 1 and O 2 have the same bias currents.17 A MaS differential pair. we have id t = iS I = 9. 3.59) Also. if a differential pair has a current ntirror as an active load. a complete differentialinput. defining a differential output current. we find (3. as shown in Fig.id2 . then the following rela(3. 3.I V. singleendedoutput gain stage can be realized.19. 9mt = 9m2' Therefore. iOU! tionship is obtained: id t .18 The smallsignal model of a Mas differential pair.57) '" Finally.n (3. This circuit is the typical first gain stage of a classical twostage integrated opamp in which the input differential pair is realized using nchannel transistors and the active currentmirror load is realized using pchannel transistors.60) . From the smallsignal analysis of the differential pair.
61) This result assumes that the output impedance is purely resistive.60) and the fact that id 2 = is I ' we have (3. However.e.3. Using (3. 3. C l .0 YOU! 0 Fig. Thus.. is usually larger than the parasitic capacitance at the 0 1.. when highfrequency effects are important (which may be the case when compensating an opamp to guarantee stability). and 0" whereas 0 3 was replaced by an equivalent resistance (since it is diodeconnected).. because the impedance at the output node.0. and the hybridrt model was used for 0 4 .1 . The evaluation of the output resistance. 3.20 is commonly used. +0. rout. for this differential stage. then the gain is given by (3..62) where ZOUI = rout II 11 (sC l ) .is determined by using the smallsignal equivalent circuit and applying a voltage to the output node.. singleendedoutput MOS gain stage. This model implicitly assumes that the time constant at the output node is much larger than the time constant due to the parasitic capacitance at the node at the sources of 0.. the very simple model shown in Fig..20 A smallsignal model for the differentialinput amplifier.. 119m' II 119m')' Also.. 3.21.. source node (i..19 A differentialinput. . . then this assumption may not be justified. as seen in Fig.144 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers Fig. Note that a positive smallsignal current is defined as the current going into the drain of a transistor. the capacitance at the output node. This assumption is usually justified. Note that the T model was used for both 0.. roul ' is much larger than the impedance at the 0. C l . O 2 source node. and O 2 . If there is also a capacitive load.
the output resistance.65) However.63) implying that the resistance seen in the path taken by iXl is equal to r d54' Now. 3.. assuming that the effect of f d 5 1 can be ignored (since it Is much larger than f 51 ) ..67) . vx rdsa (3. fout is defined as the ratio v.. The smallsignal model for the calculation of the output impedance of the differentialinput.. the current i X4 (assuming 9m4 is given by (3.64) fd5. rout is given by (3.'. I" ~ iS1 rcs t r" iS2 iS1 l rcea iszl r" ~ Fig. ~ rds4 ~ 9m4 va i iX1 i ii ~ ~ X4 i. singleendedoutput MOS gain As usual. we see that the current i X2 is given by vx iX2 = . Finally.Ii x ' where ix is given by the sum i x = iX1 + iX2 + iX3 + ix4 • Clearly.f d S2 + (f 51 II f 5 2 ) f5 1 Vx (3.21 stage. causes the two currents iX] and iX4 to cancel each other. since rd52 is typically much greater than II f 5 2 • This iX2 current splits equally between i51 and i52 (assuming f 5 1 = f 5 2 and once again ignoring r os1)' resulting in V x 2r d S2 (3. since the current mirror realized by 0. I/f 5 • = I I f5 ] and rd sJ is much larger than f sJ ) . when the current splits equally between r51 and r52' the current mirror of 0] and O.38 + rds3 MOS Differential Pair and Gain Stage 145 II rs3 ixs v. and 0 4 results in iX4 = ix.66) In other words. where the second approximation is valid. < iX21 ~ ~ + v.
73) 3. Vout.7 Consider the gain stage shown in.8 V._ = 128 k" u 0. and rds = [8.70) (3. find the output impedance. 1 rd. rout. Solution To find the bias currents.OO _ & 8 . resulting in I Dt = I D..22 A simple bipolar current mirror.07 mA/V The output impedance of 0. and 0 4 is given by (3. = 200 /lA and all transistors have W/L = (100 /lm)/( 1. 3.(W/L)(lbias12) = 1. 3.) 1 (3. A simple bipolar current mirror is shown in Fig. the gain for this stage is (3.O_ x I.9 BIPOLAR CURRENT MIRRORS The most popular bipolar current mirrors are very similar to the MOS current mirrors.69) EXAMPLE 3. splits evenly between the two sides of the differential circuit.71) rds2 = rds4 = _ .19. This current mirror has an out Fig.68) Therefore.Fig. Av ' is given by Av = 9mt(rd.146 Chapter 3 • Basic Current Mirrors and SingleSlage Amplifiers which results in the simple relationship rout = r ds 2 II r dS4 (3.and the gain from the differential input to the output.3. we assume that I bia. ..6 urn). Given that /lnCo' = 92/lA/V'.1 (3. where I bia.000L (/lm)]llID (mA)]. the transconductance of the input transistors is equal to 9mt = 9m2 = J2/lnCo. at low frequencies the gain. = I D3 = I D = roo /lA 4 Therefore.72) Thus.22. Vtn = 0.
75) Fig.. an emitterfollower buffer. and Q. Q3' is added to supply the base currents. resulting in IO"t '" I.n' In one commonly used modification of the simple bipolar current mirror. its output current is slightly smaller than the input current.74) where ~ is the transistor current gain.24.9 Bipolor Current Mirrors 147 put current almost equal to its input current. This additional transistor minimizes the errors due to finite base currents.e. Such an arrangement is almost always used for current mirrors when lateral transistors" are used because of their low current gains (i.n( I . In fact.3. and Q. this relation is approximately given by IO"t '" (1 ~2/~)I. In another oftenused variation of the simple current mirror. the output impedance is now found to be given by (3.. The output impedance of both of the previous current sources is equal to the output impedance of Q" which is ra'.24 A current mirror with emitter degeneration. 3. In an analysis similar to that given for the MOS current mirror with source degeneration. emitter degeneration is added. as shown in Fig. 3. pnp transistors are only available as lateral devices. 4. For large ~. This approach results in larger output impedances and also minimizes errors caused by mismatches between Q. . In many bipolar processes. An example of this current mirror is shown in Fig.3.2/~2). due to the finite base currents of Q. 3. Taking these two base currents into account results in I (1 + 2/~) I In (3. Ws on the order of only 1020).. Fig.23.23 A current mirror with fewer inaccuracies caused by finite base currents.
For the Wilson current mirror. come from lout. (a) (b) Fig. It can also be shown that both of these current mirrors have an output.148 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers for R e « fn .25. the base currents of 0 3 and 0 4 are supplied by lin' whereas the base currents of OJ and 0.25 V.25 Highoutput impedance (a) cascade and (b) Wilson current mirrors. As a result. as shown in Fig.(I +9m2 Re) = f 02( 1+ V VAe) T = lIr02 (3. = ro. defined to be V Ae' is about 0.25 V.4/~. Chapter 6 describes some improved MOS current mirrors that have become popular recently.77) assuming V Ae = 0. the output current is smaller than the input current by a factor roughly equal to I .3. this current mirror is designed so that the bias voltage across Re . The Wilson current mirror is preferred in bipolar realizations because the cascade mirror exhibits large errors. where VT = kT Iq = 26 mV at 300 oK.impedance on the order of [Gray. . Normally. which is often the major source of noise in bipolar wideband circuits. It can be shown that the errors due to finite base currents are on the order of 2/~' [Gray. one can use either a cascade or a Wilson current mirror. It should be mentioned here that the addition of these R e resistors also minimizes the noise output current of this current mirror. This implies that Re is given by Re Using the relationship gives f out  VAe  Ie2 'O VAe Ie2 (3.76) 9m2 = Ie 2/VT . 1993]. To achieve still higher output impedances. 1993] (3. 3. generated by the base resistance thermal noise. due to the fact that the base currents of all of the transistors are supplied by lin only.78) This concludes the review of commonly used current mirrors.
equal to R s + rb)' Notice that R E and r0 are in parallel. 3. where R" = R E II rO' The analysis of the gain of this circuit is done in two steps.3. Because of its importance in translinear circuits. which allows us to derive the overall gain. Its smallsignal model at low frequencies. the device base resistance rb has been ignored. where the bipolar T model has been used. The current in the emitter.: Fig.e.79) Therefore. is found. 3. and also of some relatively general principles for coming up with quick estimates of input and output impedances of bipolar circuits. (3.26. except that its input impedance is not infinite and its gain is normally much closer to unity. Here we shall see some simple rules for dealing with this finite base impedance during smallsignal analysis. we also look at the largesignal behavior of the differential pair. . This allows a slightly simplified smallsignal model to be analyzed.. one difference is the finite base impedance of bipolar transistors.81) v. First.10 BIPOLAR GAIN STAGES In this section.27(a). allowing us to calculate the gain from the input to the base.3. as shown in Fig. 3. since it can be easily taken into account after the fact by simply making R s slightly larger (i.10 Bipolar Gain Stages 149 3. A bipolar emitter follower with a resistive load is shown in Fig. we look at two bipolar circuitsremitter followers and differential pairs. the input impedance looking into the base of the transistor.80) This gives (3. R b .26 A bipolar emitter follower. The analysis of its lowfrequency response provides a good illustration of the use of the bipolar T model. is shown in Fig. Although much of the smallsignal analyses follow those of their MOS counterparts very closely. the gain from the base to the output is found. Second. Emitter Follower A bipolar emitterfollower is very similar to a MOS source follower. Ie' is given by (3.27(b). In this smallsignal model.
83) illustrate a principle that is generally applicable for bipolar circuits: At low frequencies.82) 9m (3.26(b).86) can be written by simply inspecting the actual circuit. where the .81) and (3. 3. + Rio) + R s Rio + 119m (3.83) gives Equations (3.27 10) The smallsignal model for the bipolar emitter follower and (bl a simplified Alternatively. (a) (b) Fig. the overall gain is now given by v out vbv out v in = V in Vb = ( ([3+ l)(r. transfer functions such as that given by (3. = ([3+1). which is equal to the impedance seen looking into the emitter. The smallsignal model for this analysis is shown in Fig. 3. which is the output.84) The gain from the base to the emitter.150 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers ~ib + ro ib Vb Rs Vin ib ~ 'b r. 3. Vout RE model. using the resistordivider formula. equivalently. when they are reflected into the base. is easily found from Fig.+ R E ) ( ) Rio ) ([3 + I)(r. Continuing. we now have = (3.28. again using the resistordivider formula. = Rio Rio + 119m (3. to be given by vou' Vb = Rio Rio +f.84) and (3. without actually analyzing the smallsignal model.85). resistances in series with the emitter appear [3 + I times larger when seen looking into the base or.85) Using (3.= ([3+1)[3/([3+1) 9m (3. noting that a ([3+I)r.86) With a little practice. It is also interesting to find the output impedance of the emitter follower at low frequencies excluding Rio.
88) . (3. f. .3. v' .89) This is an example of a general principle for bipolar circuits. = ~+I (3. we have vx=vb+ixre = ibR s + i. equivalently.10 Bipolar Gain Stages lSI input source has been set to 0 and the impedance R.Therefore.87) since ix = ie. or. Rs a.!'itter as R ==+f.28 The smallsignal model for finding the output impedance of an emitter follower.f. 3. Bipolar Differential PairLargeSignal A bipolar differential pair is shown in Fig. This circuit's largesignal behavior can be analyzed by first recalling the exponential relationship for a bipolar transistor.3.29 A bipolar differential pair. are reflected to the emitter. Rs ~+l  + . Fig.=+• i.29. ~+I ~+I ~+I v. The total output impedance of the emitterfollower is now simply R. Ixr e This gives the impedance seen looking into the eI. in parallel with Rio. First note that ~+l i. = I x (3.rv Fig. = v/i.3. ~R. is to be found. Resistances in series with the base are divided by ~ + I when they are seen looking into the emitter.
and assuming Ie 1 .91) C2 YT In(I ) (3.Y..93) = I s 2 .d is shown in Fig.96) (3.. .I  (VsE/VT) s6 (3.d = 0 and saturate near lEE or 0 for differential input voltages approaching 4 YT (around 100 mY).= 0 Combining (3. Finally.YS E I + YS E2 .94) .v: . (3.30. where we note that the currents are split equally at Y.93). alEE (3.30 Collector currents for a bipolar differential pair.. Now.90) which can be used to find the baseemitter voltages (3.= I e2 6 lSI (3.92) Is.94) and (3.95) where a is defined to be ~/ (~ + 1) and is due to some currents flowing through the base terminals. we can write (3. writing an equation for the sum of voltages around the loop of input and baseemitter voltages. we have Y· . and (3. we can write alEE = I CI + I c ' (3. In addition.v j/V T = 6 Vid/V T where Y. Note that the relations shown 4 2 o 2 4 Fig..97) A plot of these two currents with respect to Y.95).91). we have I c I = . 3. combining (3.d is defined as the difference between Y· and Y.152 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers IC .92). 3.
3.3. Bipolar Differential PairSmallSignal The smallsignal model for the bipolar differential pair of Fig. 3. resulting in 9ml = 9m2).+re2 Fig. defining Y id = v: ..32 Finding the input impedance of a bipolar r2 differential pair.Y.e.. 3. (3. The impedance..29 Fig.10 Bipolar Goin Stages 153 in (3. r.96) and (3. (a/9ml) + (a/9m2) aVid aVid (3.31 The smallsignal model of a bipolar differential pair.. consider the smallsignal model shown in Fig..98) In the case where both transistors have the same bias currents through them (i.31.is grounded and we wish to find the impedance rid looking into the base of 0 1.the input impedanceof this differential pair can be found using the impedancescaling rule just discussed. '2' seen looking into the emitter of O 2 is simply 'e2' v + v re. rei + re. we find the same result as for a MOS differential pair.97) are hyperbolic tangent functions. where Y. and thus this currentvoltage relationship for a bipolar differential is commonly referred to as the tanh relationship.99) A similar result holds for ie2 • Finally. Specifically.2 Fig. 3.. the nominal differential voltage is 0.. we have IS shown In ic I = ex i e I = = . 3. . Once again.32.
103) V.+SCgdl +sC.11 FREQUENCY RESPONSE In this section.) gml I + sa + sb (3. or. the total emitter resistance to the ground of 0 1 is re l + roz. . ( 1.VlnGln . together with the load capacitance. whereas C gdl is the gatetodrain capacitance of 0 1. C gs l is the gatetosource capacitance of 0 1.VoutSCgd I = 0 (3. is made up of the parallel connection of the draintobulk capacitances of 0 1 and 0.)V. at the output node. C L. there is much insight that can be obtained by finding the dominant frequency effects in integrated circuits.100) 3. to obtain VI (Gin + sC gs I + SC gdl) .4 is shown in Fig. The capacitance C. Here.101) where Gin = IfR ln.102) where VI = Vg S !. Solving (3.SC gdl +gm\v\ 0 (3. Note that we have assumed that the output capacitance of the input source can be ignored. 3. we have V out C9dl gm\ R. we look at the frequency response of many of the previous circuits. the impedance.154 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers since the base is grounded. C L dominates. At node V I' we add all of the currents leaving the node and set the sum equal to zero.101) and (3. CommonSource Amplifier A smallsignal equivalent circuit for highfrequency analysis of the commonsource amplifier of Fig.33. one can use nodal analysis. To analyze the circuit at high frequencies. we have Vout(G.and using the impedance reflection rule. Although the precise calculation of frequency responses is most often left to computer simulations.33 A smallsignal model for highfrequency analysis of the cammonsource amplifier. V out R2 Fig.102) (somewhat tediously). Also. rid = (~+ I )(rei + rez) (3. Usually. equivalently. 3. rid' seen looking into the base of 0 I is equal to ~ + I times the emitter resistance. Thus. 3.s.
unless R.104) and b = R. The frequency for the second pole can be . the firstorder term in the numerator. gml R. can be ignored. 1993].n. I + s{ R. is R 2 . The .107) J2 gives I R.) (3. replacing the capacitor in question with a voltage source.) (3. I 1 Frequency Response 155 where (3. setting ing for I = jW_3 dB and solv(3. we have A(s) = V out =' v. For the commonsource amplifier.n[C gst + Cgdl(l +A)] (3. C gdl must be small. I 09) where A = gml R.(CgdlCgsl + CgslC.105) At freqnencies where the gain has started to decrease but is still much greater than unity. when the gain is not much greater than unity. the second pole and the zero should be considered.108) dominates. and then calculating the resistance seen by that capacitor by taking the ratio of the voltage source to the current flowing from the voltage source.n « R" the first term in the denominator of (3.108) As an aside. sb. is the magnitude of the lowfrequency gain. S(C gd 1/ 9m l). At higher frequencies.) 1+ R. Often. the resistance seen by C gs ] is the input source impedance R. and the secondorder term in the denominator.. and the resistance seen by C.(C gdl + C 2 ) } S g R (3.n ml . and we have w_ 3 dB =' 1 R. it is of interest to note that the result for the 3dB frequency is the same result that one would obtain if the zerovalue timeconstant analysis technique were used [Gray.nR. In this technique.3dB frequency for the complete circuit is then 1 divided by the sum of the individual capacitor time constants.) + R 2 .(C gd 1 + C.n [C gSl + C gdl (I + gm 1 R. The time constant seen by the capacitor is then simply the capacitor multiplied by the resistance seen by that capacitor.n( 1+ gml R. For this case. the resistance seen by C gdl is R. Also. The term C gdl (I + A) is often called the Miller capacitance because it is the equivalent capacitance obtained when one uses the Miller approximation [Sedra. 1991J.)] + R. one calculates a time constant for each capacitor by assuming all other capacitors are zero. + CgdlC. Because the size of C gd 1 is effectively multiplied by one plus the gain of the amplifier.106) The lowfrequency gain is as expected.n[C gs l + C gdl (I + gml R.3.
8 Use the same parameters as in Example 3. The 3dB frequency (in hertz) is equal to 1_3 dB =0 [2Ilt ] [ R . + CgdlC. = 0. Solution We have R. We will show that these types of amplifiers can have complex poles.103). C dbl = 20 fF.2 along with the following: R. EXAMPLE 3.156 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers found by assuming that the poles are real and widely separated and that the denominator can therefore be expressed as 0(5) = (1+~)(I+~) ro p l (i)P2 =0 I+~+_S_'_ COp I o.(C gdl +c. is equal to 0. = 36 fF. = rdSI 11 rds ' = 77 kQ (3.112) and C. 3.36 pF (3. C gs l = 0.2 for analyzing the twostage amplifier for its frequency response. C L = 0.)] +R. The time constant due to R" namely. C gdl = 0.015 pF.»' (3. and thus a designer should be careful that the circuit .110) The coefficients of (3.26 us. namely.4.110) can then be equated to the coefficients of the denominator of (3.n[C gs l + C gdl (I + A)]. it should be stated that the highfrequency analysis of sourcefollower amplifiers is somewhat involved.>pl (Op2 (3. = C L + C dbl + C db. (3.). so it will not be given here.n = 180 kQ. =0 Cgdi 9ml CgslCgdl + CgslC.2 pF.(C gdl + C.113) The time constant due to R in. Estimate the 3dB frequency of the commonsource amplifier in Fig.03 us. R.111) It should be mentioned that the Miller approximation results in a very different and incorrect approximation for the frequency of the second pole. This analysis is almost identical to that used later in Section 5.3 pF. the equation for the approximate frequency of the second pole of the denominator is simply given as (J)p. and C db. However. R. is now equal to 0.114) = 550 kHz SourceFollower Amplifier Before proceeding.n[ C gSI +C gdl (1 +9mIR.
so we have (3. Capacitor Gs includes both the load 'capacitor..and the voltagecontrolled current source modelling the bodyeffect current source can be modelled by a single resistor.35 An equivalent smallsignal model for the source follower. Third. G L . the overall gain from v in to v ou! is found and the results are interpreted.. 3.. L . The smallsignal model used for this circuit. However. At node v ou! ' we set the sum of the currents that leave the node to zero..36. but it is very complicated for this example.115) Rin rein +<. Nodal analysis is possible...11 Frequency Response 157 does not exhibit too much overshoot and ringing. 3.3..rdez.34 The configuration used to analyze the frequency response of the source follower.. This model allows us to analyze the simplified smallsignal model shown in Fig. We also show a compensation circuit that results in only real axis poles and therefore no overshoot and ringing. looking into the gate of ai' but not taking into account G gd l .. the gain from v g I to V OU! is found. Second.0 Vout Fig. 3.. Yg . the admittance. where again RSl = rdsl II rddl ( 1)/951 and the input capacitance is given by Gin = Gin + Ggd l . the gain from iin to v g I is found.. as Fig.3.+oVout v. and the parasitic capacitor.. rds t. is shown in Fig... which includes the parasitic capacitances..__. is found.. The analysis proceeds in four steps. 3. Finally. we suggest that only advanced readers cover this subsection in detail.. . Fig. First.34 shows. The frequency response of the source follower can be found by modelling the source as a Norton equivalent circuit and adding a load capacitance. because the material is complex..35. G s b l ' Similar to what was done at low frequencies..
121) Using (3.158 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers +VgS1 L4. and solving for Y 9 = Ig1/v gt• we have Yg = g1 = vg . Yg' looking into the gate of Q I' but not taking into account the current entering C gdl. we see that the transfer function is second order.36 A simplified equivalent smallsignal model for the source follower.. Solving for Vou.lV9I' we have v o ut _ = sC gS ! + 9ml S(C gs l + Cs) + gml + G S1 vg1 (3... V g1.. If they are .119) and rearranging gives Vgt I.120).3. _ I..:.117).116) to eliminate You. I sCgst(sC s .116) and (3. in (3. The input current is given by igl = (v g1 . Specifically..n(C gs l + C s) + Cin (gmt + G S1) + CgstG st = CgslC s + C~n (C gs t + Cs) (3. it has two poles (roots of the denominator) that may be either real or complex conjugate.n(gmt + G s t) b = G.o vout Fig. to the gate voltage.Vout)sCgsl (3..n+Yg) Substituting (3.n = VgI(SC~n +G. we then have A( S) sCgS ! + gmt = vo ut = _""'=.n = S(C gs l + Cs) + gmt + G s t a + sb + S2C (3.122) Thus.n a + sb + S2C (3.119) i.116) The next step is to calculate the admittance. (3..118) into (3.n.G S1) S(C gst +Cs)+gml +G s t I.117) Using (3. as (3.120) where a = c G..c::.118) We can write an equation relating the input current.
n(9m! + G S!) (3. this is equivalent to the requirement that 0 ~ 0. and no overshoot will occur (although the circuit will be slow). if the load. or both become large). parameter roo is called the pole frequency and parameter 0 is called the Qfactor 5 [Sedra.5. In summary. (3. The Q factoris 1/2 times the inverse of the dampingfactor.e.5. then the magnitude of the transfer function has its maximum at de and no peaking will occur (assuming the zero is at a very high frequency and therefore has negligible effect). When the timedomain response is investigated.122) and solving for roo and 0 results in G. equating the coefficients of (3. source follower (and emitter follower) circuits can exhibit large amounts of overshoot and ringing under certain conditions. both poles must be real.123) 52 1++rooO roil where roo and 0 can be found by equating the coefficients of (3. And when Cin and G S! become small (G S! becomes small when the transistor's source is connected to the substrate.3. then the step response of the circuit will exhibit overshoot and possibly ringing. 1991]. It is well known that if Q < JI/2 '" 0.e.5. then becomes small.. to have no peaking in the step response. The dampingfactoris an alternative method of indicatingthe pole locations in secondorder transfer functions.126) If 0 is greater than 0.123) to the coefficients of (3. To determine if the transfer function will exhibit ringing. large ringing) when Gin becomes small and C. note that if C" C. the percentage overshoot of the output voltage can be shown to be given by % overshoot = lODe 1[/ J4Q 1 2 5 (3. which eliminates the body effect).707. the poles will be complex conjugate.122) can be written in the form A(5) = A(O) N(5) (3.n' or both become large (i. for 0 = JI/2. . Fortunately.!. and the circuit will exhibit overshoot. This potential problem is a disadvantage when using source followers. Although this 0 equation is rather complex. Here. the parasitic capacitances and output impedances in practical microcircuits typically result in only moderate overshoot for worstcase conditions. restrictions on the Q factor can also be found to guarantee no peaking for a step input. Specifically..123) to the coefficients of (3. the 3dB frequency is equal to roo. (9m! + G S!)+ CgS!G S! (3. then the circuit will have a large 0 (i.125) o = JG in(9m! + GS!)[CgS!C S + Cin(C gs! + Cs ) ] GinC s + c. '" C g. Furthermore.124) For the source follower.122). the input capacitor. In the case where 0 > 0. o 5.1 1 Frequency Response 1S9 complex conjugate.
Thus.128) (3.9 Use the parameters in Example 3.06 rnA/V.133) The zero frequency is found using (3.n = C. and therefore its highfrequency analysis is not included here.34 MHz 7 (3. c.118) can be rewritten as . However.127) C gs 1 and is typically at a much higher frequency than w o' EXAMPLE 3.131) (3.n = 180 kQ. note also that the numerator zero of the transfer function lies on the negative real axis at a frequency given by Wz = gmt (3.IJ40'1 = 8m /0 (3. we have 9ml = 1. rdS2 = 128 kQ. they can be eliminated by adding a compensation network. Find wo. Q.130) G" = 9" + 9d" + 9ds2 = 0. C L = 10 pF.34. C gs 1 = 0.n + C gdl = 45 fF (3.176 mA/V C s = C L + C Sbl = 10. 3.132) = 0. note that (3. To see this.8 This results in an overshoot for a step input given by % overshoot = I 00 e .2 pF.16 rnA/V.04 pF and so we can find roo as CgslC s + C'n(C gs l + C s) = 5. C Sbl = 40 fF. and 9s1 = 0. we have C. Solution From Example 3.127) to be 844 MHz. For both CMOS source followers and bipolar emitter followers. note that the problem of complexconjugate poles can be more severe for bipolar emitter followers.3 and assume that R. and the frequency of the zero for the source follower in Fig. C gdl = 15 fF.129) (3.3. when complexconjugate poles occur. rds ! == 128 kQ..24 x 10 rad/s = 2rr x 8. and = 30 fF. and thus it can almost certainly be ignored.160 Chapter 3 • Basic Current Mirrors ond SingleStoge Amplifiers Finally. A bipolartransistor emitter follower is very similar to a CMOS source follower.
122) becomes A(5) = i.1 1 Frequency Response 161 (3. In this case..135) and the approximations result from the fact that typically Cs > C gs1 and gml > G s1 ..134) where gmlCgslCs (gml + G")(C g.120) becomes V g1 ===_C_g""s.37 A circuit that has the same odmittonce as the input impedance looking into the gate of a source follower (and ignoring gd ) . Fig.137) G.135). This is the same admittance as the circuit shown in Fig.n gml + G" (I +:J(I + ( :J (3.. + C s) (C g " + Cs ) ' Cg" Csg ml (3.9S=I_C::L=+= C gs1+ C L C~n + C g s ! (3.37. r (3.n C' in _C=.n where Cg.3. 3.. as shown in Fig. If a third network consisting of a capacitor of size C I and a resistor of size R I' in series. is connected to the gate of the source follower.. Thus. then the negative elements are cancelled.138) Yg 21 R. 3. the input admittance is the same as a capacitor in parallel with a series combination of a negative capacitor and a negative resistor.3..) 1+5= ( gml) gml R.1C:s=) ' G in + S (C in + C gs1+ c.38.136) and (3. e . (3. as given in (3. The resulting input admittance is then simply C 2 .
162 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers t<ro VOUI Fig. '" + C )2 '" g" .3 kQ (3.38 Addition of a compensation network Ie. = 9m' + G" = 9m' + G" c. or.170 pF (3. Solution Using (3.38. When the poles are complex.) to compensate for the negative components of the admittance looking into the gate of the source follower.34.142) .n. add the compensation network.126) or a SPICE transient anafysis to look for overshoot. the poles are now guaranteed reaf. 3. (9m' + G"HC g" + C. linear) region. then increase either C.61 MHz (3. we have C.) (C 0. C s' or both. 3. + C L CL (3..135). alternatively. and R. the recommended procedure is to check to see if the poles are complex by using either (3. » C gH Regardless of the approximation. The resistor can be realized by a MOS transistor biased in the triode (i. 3.e.. and no overshoot will occur. C g"C.140) R .9m' 49.14f) The capacitor is a reasonabfe value to be realized on chip. '" and 9m'C g"C. find the compensation network and the resulting first and second poles of the source follower in Fig.10 Using the same parameters as in Example 3. Assuming the compensation network is used. as shown Fig. p. EXAMPLE 3.139) The approximation is accurate when C. when designing source followers (or emitter followers). Therefore.9. the poles of the transfer function then become = 21t x 3.
then the overshoot can be tolerated.C L (3. C L is the major contributor). At high frequencies.143) The speed penalty paid for using the compensation network is quite high. = 9ml + GS 1 = 2IT x 19. the time constant due to the output node almost always dominates since the impedance is so large at that node. and if the resonant frequency of the source follower is substantially greater than the unitygain frequency of the amplifier. HighOutput Impedance Mirrors Both the Wilson and the cascode current mirrors introduce highfrequency poles into the signal transfer function. In other words.16) is usually left to simulation on a computer. Assuming that the time constant at the output stage dominates.1s 9m C L Rou.. because the pole frequency without compensation was around 8 MHz whereas here the dominant pole is at 3. + Cdb" the load capacitance C L . The approximately equivalent time constant of these poles is C gs / 9m The proof of this statement can been found by doing a highfrequency. however. Cout. I 1 frequency Response 163 and p.144) . an approximate analysis is not too complicated. and no compensation network is necessary. the 3dB frequency is approximately equal to the inverse of the time constant. it should be mentioned that if the sourcefollower buffer is intended to be used in an opamp (and thus feedback will be placed around the buffer). Finally. CommonGate Amplifier The frequency response of the commongate stage is usually superior to that of the commonsource stage due to the low impedance. fin' at the source node.6 MHz. The total capacitance at the output node.3. ' smallsignal analysis (where the capacitances of the smallsignal models are included in the analysis). C b ia s (normally. assuming G L is not considerably smaller than 9dsl' Analysis of the frequency response of the commongate stage is left as an exercise for the reader. is the parallel combination of C gd. 3.3 MHz c. This analysis is left as an exercise for the reader. Cascode Gain Stage The exact highfrequency analysis of a cascode gain stage (Fig. we have (0_3 dB  = 29. and the output capacitance of the bias current source. + C L (3.
where (3. Notice that the circuit of Fig.145) Cd' = C gd2 + C db2 + C L + C bias In the zerovalue timeconstant analysis.39. here. but will be included here for clarity.40(b). and it is labelled 1 CgS]' The resistance seen by C gsl is R in. 3. (the cascode transistor) at low frequencies. 3.13. In this transformation.3. . where the resistance Rd ] is the parallel combination of rdsl and the impedance seen looking into the source of 0. VxNext. Ul_ 3 dB' is estimated to be 1 divided by the sum of all the time constants.39 The smallsignal model of the cascade gain stage. The advantage of this estimation technique is that it gives some insight into the relative importance of each capacitor in determining the overall 3dB frequency. We have (3. In this circuit. the resistance seen by Cgd] is found by calculating the ratio of Vx to Ix (the current leaving Vx ). The circuit of Fig.147) Also. The final time constant is then given by this resistance multiplied by Cgd]' The smallsignal model for this analysis is shown in Fig. we changed the ground node (which node is called ground is arbitrary in an analysis) and the direction of the voltagecontrolled current source. and therefore. TCgsl C S2 = C db] + C Sb2 + Cgs' = C g sl R in (3. Yin is set to 0 V) and each capacitor is considered in tum with all other capacitors set to zero. 3.13. The corresponding time constant is found and labeled 1 c i .40(a) can be redrawn as the equivalent eircuit shown in Fig.164 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers A more accurate (though still not exact) estimate may be found using the zerovalue timeconstant analysis method of [Gray. the first time constant found is the one that corresponds to C gsl. 3. 3.40(b) is essentially the same as the circuit of Fig. so formal methods are used in its calculation.e.. 3.146) The calculation of the time constant corresponding to Cgd] is more involved. The analysis here is essentially the same as that used in Fig. 1993]. The smallsignal model being analyzed is shown in Fig. 3.148) Fig. Then the 3dB frequency.40(a). C gdl is replaced by a voltage source. which was used for finding the output impedance of a sourcedegenerated current source. all independent sources are set to zero (i. (3.
R d J.n(G d 1+9mJ)] I.147) into (3..148) and solving for vx/i x gives rCgd l =.then this time constant is approximately given by ~Cgdl . . v. (b) 3. say. Therefore..11 Frequency Response 165 (a) Fig. 9ds (3.152) and therefore (3. ros.149) The admittance looking into the source of the cascode transistor.151) Substituting this result into (3. on the order of a transistor output impedance. y sz .40 tance seen Two equivalent smallsignal models for calculating the resis by Cgd 1. Namely. is the parallel combination_of this admittance and rd " .9m1 Vg1 i.52). we have (3. Substituting (3. C gd l  9m r 2 a s (3. Q2' was found previously in (3.154) This time constant can be almost as large as the corresponding time constant for a commonsource amplifiera fact not well known.153) If R in is large. we have (3.150) The impedance. (3. = R d J[I+R. 3.149)..
3 us 'Cd2 = . and Cbi. rds = 100 kQ. note that C s' = C dbl + C Sb2 + C gs2 = 0. but normally C d2 will be much larger than C gdl (because C L is often large).s = 20 fF. which is approximately given by (9mr'dS)/2 from (3..166 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers The resistance seen by capacitor C S2 is rds l in parallel with the impedance seen looking into the source of Q2' which.222 The 3dB frequency. is approximately rds.11 Assume that for both the input transistor and the cascode transistor.+ C S2. from (3. Estimate the 3dB frequency of the cascade amplifier of Fig. The sum of the time constants is then given by 'ttotal == 'tCgs I + 'tCgd 1 + 'tCs2 + 'tCd2 9mras rds 9mras '" CgslRin + C gdl .157) is estimated to be 1/'101". Solution The time constants associated with each capacitor are readily evaluated using (3.154).159) 'tCS2 rds = C S2. First. we have rds 'Cs2 '" C S22 (3.50). 9m = 1 mA/V. Thus.155) The resistance seen by C d2 is the output impedance of the cascode amplifier. C gd = 15 fF. the time constant due to C d2 is given by 9mras 'Cd2 '" Cd22(3.= 13 ns 2 C 9mras d2 2 = 25.156) Note that this time constant has the same form as (3.158) = CgslRin = 36 ns = C 9mras gdl 2 = 75 ns (3.s = 5. C db = 20 fF.52). c. R in = 180 kQ.26 pF Cd' = C gd2 + C db2 + C L + Cbi. Csb = 40 fF. C L = 5 pF.16(a).Thus.+ C d2 .157).2 pF. EXAMPLE 3. making 'Cd2 dominate. = 0.. 3. (0_3 dB' (3.055 pF We have 'regs I (3.
the gain is approximately given by A(s) '" A s/ <0_3 dB v (3. typically one pole dominates. the time constant at the output node dominates. C dbl in parallel with C gdl is less than C gs.5 J). and the second most important time constant is that due to C gdl. Because this capacitance is not excessively large and the impedance at the node. and thus we can reasonably model the amplifier gain as A(s) = A v 1+ S/<O_3 dB (3..11 Frequency Response 167 As expected.161) using (3. '" 9m'. this node would still be the primary factor determining the second pole of a cascode amplifier. the total capacitance at the source of Q. in amplifiers with a small source impedance. In addition. the time constant at that node can usually be neglected. at frequencies much larger than the 3dB frequency.54) and (3. although its effect on the 3dB frequency is negligible. Before leaving this section. (3. Gl + SC l ) At frequencies where <0» l/(rdsCl). unless either the source impedance or source capacitance is very large. Almost always. As we just saw. is then simply given by the total capacitance at that node divided by 9m'. Such a substitution results in 9m2 I+ = 9ds' G l +sC l ( Gl + sC l ) 9m2 9ds' + G l + sc. is C gs' in parallel with Cdbl in parallel with C gdl. and Yin. can be found by using (3..3kHz.162) '" 9m' ( =9ds2 + sc. It is easy to derive an upper bound on the time constant at the source of Q. However. Therefore. some comments should be made about the highfrequency operation of cascodegain stages. where G l is replaced by G l + SCl.161) are quite good. at frequencies substantially larger than <0_3 dB' which is usually the frequency band of operation. the terms in s dominate. the 3dB frequency is accurately given by <0_3 dB '" l/~Cd' = 2ltx6. The approximate time constant due to the node at the source of Q. is equal to KC gs" where K is between I and 2 (usually closer to I).144) and (3. Therefore. Using . The total capacitance at the source of Q. the admittance at the source of Q. 1/9m" is small.3. It should also be noted that the approximations of (3.144).160) Thus.
= 1. was magnified by the gain of the commonsource amplifier. where a typical value of 0.5· 0. For a telescopiccascade amplifier. Solution Normally. Finally. Also note that Cll p 2 has a very strong dependence on the channel length. EXAMPLE 3. we have Cllp 2 > 1. the unitygain frequency of a typical design might be limited to around onehalf the frequency of the lower bound second pole. to the source of O 2 .165) is relatively independent of that actual design once Veff2 is chosen. . the time constant at the gate of the input transistor can be important when the source resistance is large.02 2 m IV· s. In other words. = 0.7 X 109 rad =21t· 276 MHz. the effective size of C gd . has decreased to 119m2' and there is not much gain from the gate of 0. In this example. In most practical opamp designs. at high frequencies.8llm technology. Recall that in a commonsource amplifier. and using IIp = 0.163) for the foldedcascade amplifier (for the telescopiccascade amplifier. Therefore.25 V is chosen for v. the minimum length of a cascade transistor in an analog circuit might be 25 to 50 percent of the minimum length of transistors used in digital circuits. the effective impedance at the source of 0.164) gives the approximate frequency of the second pole (ignoring the time constants at other nondominant nodes): I (Op2 ==  'ts 2 = 9m2 = C S2 (3.12 Estimate the lower bound on the frequency of the second pole of a foldedcascade amplifier for a 0.«. and Veff. and Veff2 is usually determined by maximum signalhandling requirements. respectively. substitute Iln for IIp) ' and using (3. Veff' (3.165) This equation is an upper limit on the unitygain frequency of any amplifier that uses a cascade gain stage. Note that (3.2 urn. the upper bound would be 690 MHz.25 V. though not as important as in a commonsource stage.168 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers 9m2 = IlpCOX~). the typical unitygain frequencies would be 138 MHz and 345 MHz for the foldedcascade and telescopiccascade amplifiers. assuming L. since a cascade gainstage does not suffer as much from a Miller effect.8 urn = 1.
and approximately 2. 1¥ Active load :=J1<!>. Note that the gain is 36 dB. circuit diagrams.:IC Q 2 o Fig. . which corresponds to approximately 63 VN.ac dec 10 Ik lOOOOMeg .op . rather than to its source. are in the active region. 3. where it should be noted that the body of Q 1 is tied to ground. 3. but does not contain transistor model parameters. NETLIST: vdd 1 ibias 2 m3 2 m2 3 ml 3 Vlll 4 0 0 2 2 4 0 I 1 0 1 1 0 de 5 de lOOu pmos w=IOOu 1=1.6u pmos w=IOOu 1=1.6u nmos w=IOOu 1=1.12 SPICE Simulation Examples 169 3.42.2.6u de 0. has to be set such that both Q. Simulation of Example 3. 3.lib ".43.3. 3. and Q. Simulation of Example 3. and simulation results for selected examples in this chapter are presented.12 SPICE SIMULATION EXAMPLES In this section.849 ac I .2 The circuit for Example 3.41 where a 5V power supply is used. The bias voltage.3 The circuit for Example 3.3 is shown in Fig..2 is shown in Fig.5 V appears across the drainsource nodes for each of them. V in .41 Circuit for Example 3.end The frequency plot for this simulation is shown in Fig.print vdb(3) .option post . netlists.Icmos_models" library . Each of the nellists contains the circuit elements and commands used in the simulations.
op . 3..ac dec 10 Ik lOOOMeg .6u de 2 ac I .".43 Circuit far Example 3.3.6u nmos w=IOOu 1=1.. NETLIST: I vdd ibias I m3 2 m2 3 ml 1 vin 4 0 2 2 2 4 0 0 0 3 0 0 0 de 5 de lOOu nmos w=IOOu 1=1.3.3.end The frequency plot for this simulation is shown in Fig. 0 Fig.44..option post . library .170 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers an ~ ! 10· 10' Frequency [Hz] 10" Fig.86 VN.Icmos_models..3 dB.lib . +OV o ut Active laad 0"'" .6u nmos w=IOOu 1=1. . The gain is 1. which corresponds to 0.42 Frequency simulation result for the commonsource amplifier.print vdb(3) ..
..45 Circuit for Example 3.8..849 ac I 0. Simulation of Example 3.2 SPICE Simulatian Examples 171 1.6 2.print vdb(3) 1 JY' Active load ::J1.8 " " .: o _ Fig. 3...2 24 2.4 1.6 1.. NETLIST: vdd I ibias 2 m3 2 m2 3 ml 3 rin 5 yin 5 cl 3 0 0 2 2 4 4 0 0 I I 0 I I 0 de 5 de l00u pmos w=lOOu 1=1. .44 Frequency plot for the sourcefollower circuit.12 1.45.8 is shown in Fig.}> 2 2.ac dec 20 lk lOOMeg .6u pmos w=lOOu 1=1.3p .6u l80k de 0.6u nmos w=lOOu 1=1.8 The circuit for Example 3.op ..3.3.3.8 0 10' 10' 10' 10· Frequency (Hz) 10' Fig.iC I bias Q2 v.
.lib ". where we see that the 3dB frequency occurs around 460 kHz.end The frequency plot for this simulation is shown in Fig.Icmos_models" library .46.9 is shown in Fig.47 Circuit for Example 3.9 The circuit for Example 3. 3.. Simulation of Example 3.3.47.option post . VOu! lin lC. .o  0 I bias 2 Fig. NETLIST: vdd 1 vss 2 ibias 3 rin 4 0 0 2 0 de 5 dc5 de l00u 180k 4 Rin Q.46 w' 10" 10" Frequency[fU] w' Estimateafthe3dB frequency far a common source amplifier. 3. 3.172 Chapter 3 • Basic Current Mirrars and SingleStage Amplifiers eo so au J ~ ro 0 w " w' Fig.9.
0 source follower.op .s Time [$1 2.end The step response of the source follower is shown in Fig.e i.10 is shown in Fig.5 3 x 107 Fig. Simulation of Example 3. The overshoot here is about lO percent._ .10 The circuit for Example 3. 3."<..tran 0. 3.option post .48 The step response of showing a 1Opercent overshoot. The compensation network that eliminates the complex conjugate poles is included. o_6~ {l.6u pulse (0 5u IOn 0 0) .7 / / L  12 1 _1.5 t.lib .3i/ o ~ 0..12 {)3". cin cl ml iin 4 3 1 o o 4 3 4 o 2 30f lOp nmos w=100u 1=1.48. <l.. NETLlST: 1 vdd vss 2 ibias 3 o o 2 de 5 de 5 dc 100u . 3.5n 300n .print v(3) .5: ._ SPICE Simulotion Exomples 173 o.49.3.lemos_models" library . The simulation is used to obtain the frequency plot from which the first and second poles of the resulting source follower are determined. /' ..
3. The first pole occurs around 3.print vdb(3) .6u de 0 ac 1 O.3k .Icmos_models" library .end The frequency plot of this source follower is shown in Fig. 0 . 3.50. rin do cl ml iin cl rl 4 4 3 1 4 4 5 0 0 0 4 0 5 0 3 2 180k 30f lOp nmos w=IOOu 1=1.49 Circuit for Exomple 3.op .3.lib ".17p 49.174 Chapter 3 • Basic Current Mirrors ond SingleStage Amplifiers Fig.50 The bode plot of a source follower with compensation network..6 MHz. 10' 10" 10 7 Frequency [Hz] Fig. whereas the second pole occurs around 16 MHz.10.
3. . through 0 6 form a cascode current mirror to produce I bias ' The width and length of the pchannel transistors are chosen such that their 9m and rds are matched to those of the nchannel transistors.op .11 The circuit for Example 3.ac dec 10 0. library .1 loooMeg .e.52. 3.12 SPICE Simulatian Examples 175 Simulation of Example 3. 10. NETLIST: vdd ibias m4 m5 m6 m3 m2 ml cI vbias yin I 6 o o 6 7 7 6 3 7 I 1 8 4 I I I I 6 7 8 2 2 4 2 3 5 o o o 5 o o o de 5 dc lOOu pmos w=390u 1=2u pmos w=390u 1=2u pmos w=390u 1=2u pmos w=390u 1=2u nmos w=IOOu 1=1. The gain at de is 80 dB (i.end The frequency plot of this cascode amplifier is shown in Fig.lib ''.3.51 Circuit for Example 3. Notice that 0..11.6u nmos w=IOOu 1=1.lemos_models.option post .8425 ac 1 .000 VN) and has a 3dB frequency around 2 kHz.5 de 0. Fig.51.6u 5p dc 2.11 is shown in Fig. 3. ..print vdb(2) .
t991. Sedra and K.n • pchannel MOS transistors: z J. Gray and R. 1993. 3. New York. . Microelectronic Circuits.13 REFERENCES P. = 1.9 X 10. John Wiley & Sons. Cj = 2.lm 3 Co.5 v'? rds (0) = 8. 3rd ed.lm) C isw = 2. 3.lA/Y V = 0.9 Y 'Y = 0. R. 3.pF/(J.lm)' 4 Cgs(OverlaPI = Cgd(overlaPI = 2. New York. S. G. C.0 X 10.8 y l /2 v.lm)/I D (rnA) in active region 4 .lpC o. A. Rinehart & Winston.lnCo.14 PROBLEMS Unless otherwise stated. Holt. Smith.4 x 10 pF/(J.000 L (J. = 30 J. Meyer.pF/J.lA/Y = 0.8 Y 'Y = 0. Analysis and Design of Analog Integrated Circuits.0 x 10"" pF /J.. assume the following: • npn bipolar transistors: p = 100 VA = 80Y t b = 13 ps 't s = 4 ns r b = 3300 nchannel MOS transistors: 2 J.52 The frequency plot of the cascade amplifier.lm • . = 92 J."'IueI'IC)'[Hz1 Fig. 3rd ed.176 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers :t ~I J 10: w· F.
and (b) the source is connected to the substrate.000L (/. assume eaclT transistor is composed of three gate stripes. Assume all transistor sizes are the same. where I. and transistor 0. I bias ' Assume all transistor sizes are the same.14 r ds (n) = l2. assume the de bias voltage of the output node is halfway between ground and the 5V powersupply voltage. Derive an equation for the impedance looking into the source of a source follower.5 x 10 pF/(/. 3.3 For the commonsource amplifier in Fig.101) and (3.000L (/.as.Im)/Io (rnA) in active region 4 . Also assume the following: rosn (n) = 8.n = 80 /.6 urn.5 pF when (a) the source is not connected to the substrate.1 Consider the current mirror shown in Fig. rout. Based on this geometry.5 X 10. 3.OOOL (/. Find the nominal output current as well as the output impedance.as = 75/.3.10. assuming that all transistors have W/L = 75 /.6 urn.Im)/I o (rnA) r dS'p (n) = 12. = 1. 3.Im)/Io (rnA) 3.10 Assume that the commongate amplifier of Fig.6. 3.Im 3 Co.Im) 4 C j •sw = 2. In this step. assume there is a load capacitor.2 For the commonsource amplifier in Fig.103) can be derived from nodal equations (3. C L. 0. Derive the 3dB frequency of the amplifier. Use a smallsignal model similar to that in Fig. Find the relationship between the 3dB frequency and the bias current. 3. find the minimum output voltage such that both transistors remain in the active region.pF/(/.9 X 10. Derive the lowfrequency output impedance of the source follower shown in Fig.4.1. 3. transistor 0.4. and (b) the source is connected to the substrate.4 In the highfrequency analysis of a commonsource amplifier.7 3. Ib. has W/L = 100 /. Repeat Example 3.Im/1. The first step is to estimate the areas and peripheries of the junctions based on simple layout rules.pF//. Also. 3.Im/l.6 3. 3.6 um.<. has W/L = 25 /. 3.5 pF when (a) the source is not connected to the substrate. C j = 4. derive the relationship between the bias current.8 3.Im/1.Im/1.1 rnA and that all transistors have a W/L of 100 /. show that the transfer function given in equation (3.9.9 has a bias current of .1 3. 3.6 urn and that Ib.5 Find the 3dB frequency of the commonsource amplifier in Fig. Repeat Example 3. but assume C L = 0.0 X 104 pF//. the next step is to estimate the parasitic capacitances of the smallsignal modeL In this step. but do not take into account C s and R".Im Problems 177 3. 3.Im)' Cgs(overlap) = CgdloverlaPl = 2.1A.lA.8. and the de gain.4. but assume C L = 0.102). that dominates the frequency response.
11 3. Using smallsignal analysis. 3.17 Repeat Problem 3. Remember to include the effect of the output impedance of the input current source. and show that it is approximately given by Ignore the body effect. Repeat Example 3.11 Derive the output impedance of the current mirror shown in Fig. in which a cascode amplifier is analyzed to find its 3dB frequency.2 pF C gd 15 if C sb = 40 if C d b = 20 if .n = 180 kU C L = I pF C gs = 0. Fig.5 pF.11. find the equation for the output impedance. Find the 3dB frequency of the amplifier. Derive an expression for the frequency at which the magnitude of the gain of a cascode amplifier has decreased to unity.178 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers R. What is this value when the parameters of Example 3. P3.15 3.1 mA and transistor sizes given by W /L = 50 I1m/ l. 3. but include the voltagedependent current source that models the body effect.11. where a diodeconnected transistor has been included in series with the source of the outputtransistor. Include in your analysis the voltagedependent current source that models the body effect.16 3. P3.13 3. find the output impedance of a MaS cascode current mirror. except that C L = 2 pl.14. rout. of a MaS Wilson current mirror.? .12 3.14 A MaS nchannel cascode current mirror has a bias current of 0.6 11m. but assume C L = 0. What is the minimum output voltage allowable across the current mirror without any transistors entering the triode region? Using smallsignal analysis. And assume the input source has a 30iF output capacitance.11 are used.
21~.) For the bipolar cascode current mirror shown in Fig. P3.23. What is the required value for R. 3.21 For the bipolar Wilson current mirror shown in Fig.2 rnA 0 V OD = 5 V Fig. for ~ » I. P3. (Neglect finite output impedances.25(a). Iout/I'n. Ib'as.23 3. rc ' into account for both transistors. derive the relationship between the bias current.4 but realized using bipolar transistors.19 3.26 3.25(b)./I'n .20 Derive the current gain. for ~ » I.25 3. show that the output impedance. Iou.22.5mA bias current? Derive the lowfrequency input impedance and the gain of a bipolar commonbase amplifier. for large ~. this gain is I .22 Derive the output impedance of the simple bipolar current mirror shown in Fig.14 Problems 179 3. What are these values for a 0. this gain is 1 .27. Derive the 3dB frequency of a bipolar commonemitter amplifier.22 3. (1 + 9m2(R e II f f n)) .24 3.3. derive the current gain. P3. show that the current gain. this gain is given by lout ~ I _ ~ I'n ~ 3. 3. f out ' is approximately given by f out = o. Derive the lowfrequency gain and output impedance of a bipolar emitter follower that is biased with a current mirror. and show that.22. for the bipolar current mirror shown in Fig. Iou/I'n' for the bipolar current mirror shown in Fig. Take the finite output impedance. and the de gain.) Derive the current gain.18 3. and what is the output impedance if we want the transistors to be biased at 0. Iout/I'n ' is given by = 2 3. and show that. 3. 3.27 For a commonsource amplifier similar to that in Fig.2/~2 (Neglect finite output impedances. and show that. For the circuit shown in Fig. 3.
30 3. find the largesignal current gains of cascode and Wilson current mirrors.28 Taking into account the finite current gain of bipolar transistors. For the differentialinput stage in Fig. assume that I bias = O. .lm/1.lmA.29 Assuming ~ » I and 9mr0 » ~.29 for a bipolar cascode current mirror. show that the output impedance of a bipolar Wilson current mirror is approximately given by rout == 2 ~ro 3.6 urn. P3.19.31 Repeat Problem 3. all transistors have W /L = 100 J. but ignoring the finite output impedance.27 3. and the load capacitance is 100 pF.180 Chapter 3 • Basic Current Mirrors and SingleStage Amplifiers Vbia s Fig. Find the de gain and the 3dB frequency. 3. 3.
inherent noise refers to random noise signals that can be reduced but never eliminated since this noise is due to fundamental properties of the circuits. Some examples of inherent noise are thermal. inherent noise can be significantly reduced through proper circuit design. dEm. signaltonoise ratio.1 TIMEDOMAIN ANALYSIS Since inherent noise signals are random in nature. Specifically. Examples are power supply noise on ground wires (such as a 6DHz hum) or electromagnetic interference between wires. The outline of this chapter is as follows: First. in this section. Interference noise can be significantly reduced by careful circuit wiring or layout. shotfand flicker noise. we define the following terms in the time domain: rms value. analysis in the frequency domain results in more powerful analysis tools than does analysis that remains strictly in the time domain. This type of noise mayor may not appear as random signals. a basic understanding of noise sources and analysis is required. Another motivation to study noise analysis is to learn basic concepts of random signals for a proper understanding of oversampling converters. such as using multiple base contacts to change the resistance value of the base of a transistor. Interference noise is a result of unwanted interaction between the circuit and the outside world. or between different parts of the circuit itself. and noise summation.CHAPTER Noise Analysis and Modelling To develop good analog circuit design techniques. Next. However. 181 . a timedomain analysis of noise signals (or other random signals) is presented. we define here some basic tools to effectively deal with random signals. and noise summation are presented. 4. The purpose of this chapter is to present some fundamentals of noise analysis followed by an introduction to electronic noise sources and circuit analysis. basic concepts such as rms value. Noise models for circuit elements are then presented. two circuit noise analyses are performed to give the reader some experience in such analysis. Here. As with deterministic signals. a frequencydomain analysis of noise is presented. and finally. Inherent noise is only moderately affected by circuit wiring or layout. SNR. In contrast. such as changing the circuit structure or increasing the power consumption. It should be mentioned here that this chapter deals with inherent noise as opposed to interference noise.
a longer T gives a more accurate rms measurement. For those more rigorously inclined. such as that shown in Fig. it could just as easily be current noise or some other quantity.3 0.• ~ 1 Time (5) 0.1.8 Fig.2 0.182 Chapter 4 • Naise Analysis and Modelling 0. throughout this chapter we will assume all noise signals have a mean value of zero. the average power dissipated.1. we assumethroughout this chapter that random signals areergodic. or root mean square. the rms current value is defined as Inlrms) '" W: i~(I) dr 2 (4.~ i I ~ D. or a noise current.in watts. in(I). equals the normalized noise 1. Typically.  Rms Value Consider a noise voltage.2) The benefit in knowing the rrns value of a signal is that it indicates the normalized noise power of the signal.1) where T is a suitable averaging time interval.4 0. voltage value is defined I as Vntrrns) es I [T T Lv~(I) dt]112 (4. implying theirensemble averages can be approximated by theirtime averages. 4.3 0 .1 vo(t)(V) 0 0. if the random signal vn(l) is applied to a IQ resistor. Specifically. It should be noted that this noise signal appears to have an average value of zero. Similarly. v n(l) . In fact.6 0. 4.1 Example of a voltage noise signal (time domainJ. which simplifies many of the definitions and is also valid in most physical systems. . Although this signal here is a voltage signal. An example of a random noise signal in the time domain is shown in Fig.1 0. 4. P dtss. The rms.2 0.2 0.
Pow :. that has a normalized signal power of V~umsl and a normalized noise power o! V~lrmsJ' the SNR is given by SNR = 10 log [V.lrms J] = 20 log [~ xlrms l] V ntrrns) n(rms) (4. In other words.4. V~lrms) and I~lrmsJ' are sometimes referred to as the normalized noise powers of these two signals.6) Clearly.:: SNR " 1010g ::.(t) . One common measure is that of dBm.1 Find the rms voltage of a OdBm signal referenced to a 50n resistor. v.::::. whereas a 1IlW signal corresponds to 30 dBm. Units of dBm Although dB units relate the relative ratio of two power levels. a noise signal with an rms value of I mV (rms) dissipates the same power across a resistor as a de voltage of I mY.: gn aIL ::. it is also common to reference the voltage level to the equivalent power dissipated if the voltage is applied across either a 50n or a 75n resistor. then SNR = 0 dB. When voltage levels are measured. P ores = I nums) x I 2 n = I nums) 2 (4. EXAMPLE 4. for a noise current.4) As a result.1 TimeDomoin Anolysis 183 power and is given by P diss = V ntrrns) ~ 2 _  V2 nrrrnsj (4. when the meansquared values of the noise and signal are the same. :.:. where all power levels are referenced by I mW.5) Thus. assuming a node in a circuit consists of a signal. Similarly. What is the level in dBm of a 2volt rms signal? .3) This relationship implies that the power dissipated by a resistor is the same whether a random signal or a de level of k volts (rms) is applied across it. For example.. a lmW signal corresponds to 0 dBm. [ noise power (4. SNR The signalronoise ratio (SNR) value (in dB) of a signal node in a system is defined as si".::e r] . it is often useful to know a signal's power in dB on an absolute scale. in(t). the square of the rms values. applied to a In resistor.
as shown in Fig. Then we can write V. .11) + (a) (b) Fig.) = 19 dBm 0.(I)] dl (4. what can be said about the rms value of the combined signal" We answer this question as follows.oums) = .2236 and would dissipate 80 mW across a 50Q resistor. I 2 TJT o[Vnl(I)+Vn. (a) voltage.2 Combining two noise sources. (4. 4.9) where vnI(I) and v n2(1) are two noise sources with known rms values Vnl(rms) and V n2(rms)' respectively. The measured voltage is referenced only to power levels that would occur if the voltage were applied.8) Note that the measured voltage may never be physically applied across any 50Q resistor.10) (4.2236 (4. Noise Summation Consider the case of two noise sources added together.0 2010g ( . a 2volt rms signal corresponds to 2. Similar results are obtained if the power is referenced to a 75Q resistor.2. If the rms values of each individual noise source are known.7) Thus. and (bl current. Define vno(l) as vno(l) = vnI(I) + v n2(1) (4.4.184 Chapter 4 • Noise Analysis and Modelling Solution A OdBm signal referenced to a 50Q resistor implies that the rms voltage level equals V u ms) = )(50 Q) xl mW = 0..
!:.. . (4.. Note that...2 11 V. An example of two fully correlated (though deterministic) sources are two sinusoidal signals that have the same frequency and a phase of 0 or 180 degrees with each other. The last term shows the correlation between the two signal sources.12) With this definition..15) where the sign is determined by whether the signals are in or out of phase with each other. the meansquared value of their sum is given by 2 2 2 (4. orthogonal) when signals are uncorrelated. EXAMPLE 4.14) Vnotrrns) = Vn I (rrns) + Vn2(rms) This relationship indicates that two nns values add as though they were vectors at right angles to each other (i... 1. Fortunately.1 TimeDomoin Anolysis 185 Note that the first two terms in the righthand side of (4. In this fully correlated case. a value of C = ± I implies the two signals are fully correlated. Values in between imply the signals are partially correlated.11) are the individual meansquared values of the noise sources. as C sa . we have little reason to analyze partially correlated signals since different inherent noise sources are typically uncorrelated.2 Given two uncorrelated noise sources that have Vnllrms) = 10 IlV and Vn2(rms) = 5 11 V. An alternate way to write (4.16) which results in V norrmsj = 11. the meansquared value of their sum is given by Vnoums) = [Vnllrms) ± V n2(rms)] 2 2 (4. is to define a correlation coefficient. in this case where the signals are fully correlated..Vn1 (rms) Vn2(rms) f1fT nl(t)Vn2(t) dt 0V (4....4. C. whereas C = 0 indicates the signals are uncorrelated.. In the case of two uncorrelated signals..:. how much should V n1 (rrns) be reduced while Vnztrrnsj remains unchanged? Solution Using (4.. It is of interest to contrast this uncorrelated case with that for fully correlated signals. vnl(t) and vnlt). the nns values add linearly (similar to aligned vectors). If we are required to maintain the total nns value at 10 11 V.. Also.e. find their total output nns value when combined.11) that better indicates the effects of signal correlation. C .13) It can be shown that the correlation coefficient always satisfies the condition I .14) results in V2 = (10' + 52) no(rms} (4.11) can also be written as 2 Vno(rms) = 2 Vn1(rms) + V n 2(rms) + 2CV n 1(rms)Vn 2(rms) 2 (4.
historically. Vnll) 1.3 Example of voltage spectral density (frequency domain).l V and V n2(rms) :::: 5 u V. redncing Vn1lrms) by 13 percent is equivalent to eliminating Vnztrms r altogether! The above example has an important moral. for (a) spectral density. To reduce overall noise.5 Hz is 10 (J. 4. and (bl root spectral density.1 is applied to a spectrum analyzer. For example. the vertical axis is a measure of the normalized noise power (meansquared value) over a IHz bandwidth at each frequency point.00 100 2 (~V) 10 Spectral density ~V 31. 4. random signals have their power spread out over the frequency spectrum. 4. Noise Spectral Density Although periodic signals (such as a sinusoid) have power at distinct frequency locations.186 Chapter 4 • Noise Analysis and Modelling To maintain V notrms : :::: 2 :::: 10 J.0 10 1001. 4. This section presents frequencydomain techniques for dealing with noise signals and other random signals.1 1. such units have been commonly used in the measurement of continuoustime spectral densities.16 1. the vertical scale is in units of microvoltssquaredlhertz. In other words. Note here that although the horizontal scale is the usual frequency axis. we have 10 V~ l t rrns j + 52 (4.)Hz 3.0 1.2 FREQUENCYDOMAIN ANALYSIS As with deterministic signals. concentrate on large noise signals. the measurement at 100 Hz in Fig. if the timedomain signal shown in Fig.0 10 (a) Hz 1.lV.17) which results in Vnllrms) = 8.5 Hz and 100. the resulting spectrum might look like that shown in Fig.000 (Hz) 0.7 J. . 4.3(0).lV)'.000 (b) (Hz) Fig. It should be noted that units of hertz (Hz) (rather than radians/second) are used throughout this chapter since.1 1001.0 0. For example.6 10 Root spectral density . the frequencydomain techniques are useful for dealing with random signals such as noise. Therefore.3(0) indicates that the normalized power between 99.
000 (11 V')/Hz. Note that the horizontal axis remains unchanged although there is a roothertz factor in the vertical axis. if the signal corresponding to Fig. 4. one can obtain the total meansquared value by integrating the spectral density 2. V/ . then the spectrum analyzer's reading is independent of the filter's bandwidth. A random noise signal has a frequency that is continually changing through a broad continuum of frequencies. A spectrum analyzer is sensitive to only a narrow frequency range that is the passband of its filter. V~(f) (or.3(b). For example.3(a) were measured at around 0. as the resolution bandwidth goes to zero. It is often convenient to plot the square root of the noise spectral density when we deal with filtered noise. equals 1.(I) are voltssquaredlhertz. the random signal has the same frequency as the spectrum analyzer's filter. Since the spectral density measures the meansquared value over a IHz bandwidth. the meansquared value also becomes zero. whereas those of I~(I) are ampssquared/hertz. if the signal is not a random signal wandering in and out of the frequency range of the spectrum analyzer's filter. the measured meansquared value should be normalized to the value that would be. the bandwidth of the bandpass filter is determined by the resolutionbandwidth control. and it measures the meansquared value in that range. the spectrum analyzer effectively measures what percentage of time the random signal is in the frequency range of its filter. Thus. Taking a square root results in Vn(l) . In a laboratory spectrum analyzer. as the average normalized noise power over a IHz bandwidth. The filter of the spectrum analyzer reacts with a time constant approximately given by t ~ I 1tW (4.e. we define the noise spectral density. It should be emphasized here that the meansquared value of a random noise signal at a single precise frequency is zero. I~(f). V~(f) is a positive realvalued function. However. Also. which. The narrower the bandwidth of the filter. Such a result would not occur when a lOOHz sinusoidal waveform is measured. the less percentage of time the signal is within its frequency range. as the reso"lution bandwidth increases.jj1z). 4. We will refer to Vn(f) as the root spectral density which is expressed in units of volts/roothertz (i. trum analyzer is as follows. in the case of current. but is a deterministic signal at the center frequency of the filter. when scaled to a IHz bandwidth.! Conversely..2 FrequencyDomain Analysis 187 of V.obtained for a bandwidth of I Hz when the noise spectral density is stated in units of V. the resulting units are amps/roothertz.18) where W is the bandwidth of the filter. An intuitive explanation of how a random noise signal is measured using a spec Thus.1 Hz using a resolution bandwidth of I mHz. Thus. so does the measured meansquared value. In other words. In either case.4.4. the meansquared value of the signal shown in Fig. For some of the time.3(a) measured at 100 Hz is directly proportional to the bandwidth of the bandpass filter used for the measurement. The units 2 . . the meansquared value measured would be I (I1V)'. In the case of current noise. and therefore the smaller is the spectrum analyzer's output. as shown in Fig./ (Hz).
Thus.Hz bandwidth. the output of a 30Hz filter is 30 Hz x 10 (!IV)' = 300 (!IV)' (or an rms value of J300 !IV). In other words. the spectral density is the same for positive and negative frequencies. resulting in a value of 1 (!IV)' (or an rms value of 1 !IV).3 What meansquared value would be measured on the signal shown in Fig. voct) . and the total meansquared value remains unchanged. A twosided definition results in the spectral density being divided by two since. EXAMPLE 4. it should be mentioned here that the spectral density function. f. a white noise signal would have a flat spectral density.3 at 100 Hz when a resolution bandwidth of)O Hz is used on a spectrum analyzer? Answer the same question for a O. as shown in Fig. A noise signal is said to be white if its spectral density is constant over a given frequency.21) and V nw is a constant value. where Vn(l) is given by (4. 4.lHz resolution bandwidth.V 0 2 0(1) dl (4.20) Finally. For a 0.19) (4. This relationship is known as the WienerKhinchin theorem.188 Chapter 4 • Naise Analysis and Modelling over the entire frequency spectrum. White Noise One common type of noise is white noise. the rms value of a noise signal can also be obtained in the frequency domain using the following relationship: Vz o(rmsl = and similarly for current noise. 4. for realvalued signals. Since the noise spectral density is 10 (!I V)' 1Hz at 100 Hz.4. again primarily for historical reasons. the measured value would be 10 times smaller than for a IHz bandwidth. It should also be noted that the relationship just shown defines a onesided spectral density function since the noise is integrated only over positive frequencies as opposed to both negative and positive frequencies. Solution Since the portion of spectral density function is flat at about 100 Hz. V~(I).1. . is the Fourier transform of the autocorrelation function of the timedomain signal. the measured value should simply be proportional to the bandwidth.
0 10 100 1.(f) = ( .5). V~(f) . or flicker.0 1/1 noise dominates 32 6 a V. noise.22) where k. 3. or flicker.' The spectral density. x10 ) +(1 1If noise corner f 10.2 1.000 dominates White noise Fig. Note that the I/f noise falls off at a rate of 10 dB/decade since it is inversely proportional to Ji. The intersection of the IIf and white noise curves is often referred to as the l/fnoise corner (it occurs at 10 Hz in Fig.2 1. noise is also referred to as pink noise since it has a large lowfrequency content.5. .1 / 1.000 f (Hz) Fig. is a constant. Thus.(I) 10 dB/decade Rootspectral density X (~) 10 3.23) Note that it is inversely proportional to Ji (rather than f).6 ) ' .2 FrequencyDomoin Anolysis 189 V n(f) (~) Root spectral density 10+ 3.4. 4. of IIf noise is approximated by V~(f) = k' f (4. An example of a signal having both IIf and white noise is shown in Fig. the spectral density is inversely proportional to frequency.0 V (I) n =V nw = 3.4. V. or Flicker./ 10 100 1.1 1. 4.5 A noise signal that has bath I /f ond white noise. IIf noise is given by Vn(f) = kv Ji (4.4 An example of a white noise signal. 1If." In terms of root spectral density. Ilf.0 0.4.2_~_V )Hz +tt+t_ 0. and hence the term "lIf noise. Noise Another common noise shape is that of 1/f.
the total output meansquared value is given by V2 norrms) = f"'" IAU21t1)1 2 Vnm dl 2 0 (4.(j21tf)I2V~m (4.26) The relationship in (4. 4. = IA(j21t1)12V~. uncorrelated noise sources combine to form the total output noise. filtering. consider the system shown in Fig.(l) 1 ~V~o(l) A(s) .2. It is also of interest to consider the case of multiple uncorrelated noise sources that are each filtered and summed together.24) The term 21t1 arises here since. The following relationship between the input and output signals can be derived using the definition of the spectral density. straightforward transfer function analysis is applied when using root spectral densities.25) If we wish to work with root spectral densities. we replace S with jro = j21t1. A(s) represents a linear transfer function as a result of some circuit amplification. As a result of (4.6.(I) Vno(l) = IA(j'2 nt) IVn.26) should make intuitive sense since it indicates that the transfer function simply shapes the root spectral density of the input noise signal.27) 2 Vn.190 Chapter 4 • Naise Analysis and Modelling Filtered Noise Consider the case of a noise signal.(I). Vn.3 IA. and not its phase. whereas squared terms are required to deal with spectral densities.() I I Fig. whereas the spectral density is shaped by IAU21t1)I' (as seen by (4.24). the output spectral density is given by V~o(l) = L i == 1. the filter outputs are also uncorrelated. filter} to a naise signal. Note that the output spectral density is a function only of the magnitude of the transfer function. 4. It is important to note here that the root spectral density is simply shaped by IA(j21t1)1. For example. for physical frequencies. or both. we can take the square root of both sides of (4. we see the benefit in dealing with the root spectral density rather than the spectral density. V~o(l) = IA(j21t1)12V~m (4. being filtered by the transfer function A(s). Hence. Specifically.24)).24) resulting in (4. As a result. as shown in Fig. Vno(l) .e. In this case. one can show that if the input random signals are uncorrelated. 4.7 in which three filtered. . Here.6 Applying a transfer function [i.
0 10 100 10 3 10' (c) (d) Fig. that has a white root spectral density of 20 nV/ Jlfz. we have V nttrmsj = 2 f10 5 2 dl = 0 20 4 x 10 (nV) 72 (4.8 (01 Spectral density for Vn. as shown in Fig. 4.7 Filtered uncorrelated noise sources contributing to total output noise.(I) . r. resulting in 6.4. for this simple case.(t).. (c) RC filter frequency response. What is the total noise rms value if it is filtered by the RC filter shown in Fig.3 l! V rms .4.1)1 (dB) R Vni(l) wry~ = 1 kQ Vno(l) I 10 I 100 (a) 10 I3 I 10' • Vno(l) 1 1o . EXAMPLE 4.0 IA(j2.4 Consider a noise signal.:j':1 1. . 4. where it is assumed the RC filter is noise free? Solution For the noise meansquare value from de to 100kHz of Vn. one could also obtain the rms value bY multiplying 20 nV/ Jlfz by the square root of the frequency span.8(b). or JlOO kHz .0 10 1 1 + S/2"l o 10 = 103 100 10 3 [~) . Find the total noise rms value between de and 100kHz. Ib) RC filter to shape noise.3 l! V rms.8(a). Note that. 1591'F (b) A(s) = a 20 1. Id) Spectral density for V no(l) . Vnll). 4.2 FrequencyDomain Analysis 191 noise sources Uncorrelated Vn2(1) Fig.28) resulting in an rms value of Vnftrmsj = 6./Hz 10' 20 2 1.2"RC IC = 0.
Thus. to obtain the root spectral density of Vno(I). filter order) is increased. 4. Thus. Mathematically.8(c). The term brick wall implies here that the IHz bandwidth of the filter is passed with a gain of one. Thus. Ao. one could measure the spectral density function by filtering a noise signal with a brickwall bandpass filter having a IHz bandwidth. The noise bandwidth of a given filter is equal to the frequency span of a brickwall filter that has the same output noise rms valae that the given filter has when white noise is applied to both filters (peak gains are the same for the given and brickwallfilters}.8(b) with 10 = (1I2ITRe).192 Chapter 4 • Noise Analysis and Modelling For the filtered signal. given a filter response with peak gain Ao. In other words. whereas all other frequencies are entirely eliminated. practical filters can only approach a brickwall response as their complexity (i. in theory. The transfer function of Ars) is given by . The lesson here is that you should not design circuits for larger bandwidths than your signal requires. for lowerorder filters with a IHz passband. the term noise bandwidth is defined. consider a firstorder.(fl with the frequency response.. Noise Bandwidth We just saw that the spectral density function is determined by the noise power within each IHz bandwidth. 4. Such a response would occur from the RC filter shown in Fig. we can multiply the root spectral density of Vn.30) a I + (~)' 1 0 = 6. otherwise noise performance suffers.79 J. 9 = (4.(I) since highfrequency noise above I kHz was filtered. 4. However.l V rms. as the original filter. 4. For example.24 x 1O'(nV)' which results in an rms value of V notrms j = 0.29) where 10 = 10'. we find that the RC filter has the frequency response shown in Fig. To account for the fact that practical filters have more gradual stopband characteristics. the noise meansquared value of Vno(l) between de and 100 kHz is given by ro' 20' dl = (4. Therefore. Vno(l) . as shown in Fig. more noise power is passed than what is simply in a IHz bandwidth. Note that the noise rms value of Vno(l) is almost 1/10 that of Vn. the noise bandwidth is the width of a rectangular filter that has the same area and peak gain. lowpass response with a 3dB bandwidth of 10 ' as shown in Fig.8(d).9(0). the output root spectral density is given by Vno(f) 20 X 10.e. IAQ2ITfll.
V~w df = Vnwfoarctan (f )\. then the total output noise rms value equals./ 1 0 1010 (dB) 20 fa 100 .(f). 0 1 0 10 (b) 'It . then fo = I 21tR eqC (4.36) Thus. Vn.4.9 (a) A firstorder. (4. Vno(rms) = Vbrick(rms)' results in 1tfo f.35) Finally. and (b) a brickwall filter that has the some peak gain and area as the firstorder response. and the resistance seen by that capacitor. A(s) = 1+21tfo This results in the magnitude response of A(s) being equal to s (4. for the common case in which a firstorder circuit is realized by a capacitor. lowpass response.. V brick(rms) 2 == ff~ 0 V nw df == V nwfx 2 2 (4. C.4. Req . = 2 (4. is a white noise source given by Vn/f) = (4. is applied to the filter shown in Fig. . lowpass filter with a 3dB bandwidth of f o equals 1t(fo/2).31) IA(jf)1 = [ I + (U v. the noise bandwidth of a firstorder.= 20 (f)2 1.34) 1+ fo 0 If this same input signal. Note that. The total output noise rms value of Vno(f) is equal to Vno(rms) 2 2 V~w1tfo = f.32) ] An input signal. 4.33) where Vnw is a constant.ck(j2ltf)1 20 dB/decade 0 FrequencyDomoin Anolysis 193 IA(j2ltf)1 0 (dB) 20 10 100 1 0 10 (a) .. Vn/f). equating the two output noise rms values. 112 (4.9(b).37) .2 A(s) = 1 1 + s/2ltlo IAbr. I I x =1a 2 Fig.
when white noise is applied to the filter input. as shown.84 x 1O'(nV)2 (4. Such approximations are particularly useful in noise analysis. Vn. For the region N the total meansquare noise is given by " N.10. where large inaccuracies occur naturally due to such things as unknown parasitic effects and incomplete noise models. integration formulas become much simpler when one needs only to integrate under linear functions and add together the resulting portions.39) Similar results for noisebandwidth relationships can be obtained for higherorder and bandpass filters. The following example demonstrates this approach.6 x lO'cnV)' (4. One such approximation is the estimation of total noise byintegrating over frequency with the assumption that piecewiselinear Bode diagrams are exact. EXAMPLE 4. the output root spectral density. the frequency range is broken into four regions. in the firstorder case just described. as shown in Fig. through N4. being applied to the amplifier A(s). we have 3.38) The advantage of knowing the noise bandwidth of a filter is that. To perform piecewise integration of Vno(l).194 Chapter 4 • Noise Analysis and Modelling and the noise bandwidth is given by Ix = 1 4R eqC (4. = f~OO2~ 2 ]00 dl = 200' In(l)I] = 1.(I). 4. Find the output noise nns value of Vno(1) above 1 Hz. the total output noise meansquared value. With such an approximation. Piecewise Integration of Noise Although simulation and computer techniques can analyze circuits or systems quite precisely (depending on their modelling accuracy).40) In the region N2 . V~o(rms)' is equal to (4. N. Solution As shown. it is often convenient to make approximations that are useful in the early design stages. Specifically. the total output noise meansquared value is easily calculated by multiplying the spectral density by the noise bandwidth.41) . VnO(I)' is determined by the addition of the Bode diagrams for Vni(l) and A(s).5 Consider an input noise signal. .
. 4 20 10 100 <. lowpass response and simply remove the noise portion resulting from under ../ 1 <._........ ·14 N2 .L..10 Root spectral densities and amplifier curve example.. V no(l) is the output noise that results from applying an input signal with noise V n. .(f) 200""'~++++i+I (~J 20Ij=:"'!Ioool01....__ _.... resulting in N....(I) to the amplifier Ars)... for region N4 ..1)] 20 (dB) 0 .. 10' _1/1curve 103 10 lOs 10' Frequency (Hz) Vno(t) 200 20 2 1 10 100 (~) 10 3 10 4 10 S 10' 10' Frequency (Hz) I'" N..33 X 10 8(nV)' (4.2 FrequencyDomain Analysis 195 Vn..J 4 s 1 10' 10 100 103 10 lO Frequency (Hz) . IA(j2..L..__ _...l__+ 2L_ _L_ _~_ _l. Region N3 ramps up rather than down.. = ro...1'" 3 N4 • Fig...l. 4....42) Finally. we can use the noise bandwidth result of a firstorder.....4. 20'1' (10 3 ) 10 dl = (20 )2[!131.._ _./4 N . J IO' 3 10 3 10' = 1.
we have. However. It . we discuss noise models for popular circuit elements where all three mechanisms occur. For example. there is little need to find the noise contributions in the regions N I' N2 . For example. 4. Such an observation leads us to the I1f noise tangent principle. one must be careful in cases where the spectral density curve runs parallel to a I1f tangent line for an appreciable frequency span. 4.5 ~V rms (4.7 ~V rms is quite close to the total noise value of 77. N. Therefore.44) An interesting point to note here is that in the preceding example.196 Chapter 4 • Noise Analysis and Modelling 104 Hz.5 ~V rms. In this section. This noise has a white spectral density and is proportional to absolute temperature. consider once again Fig. Thermal noise is due to the thermal excitation of charge carriers in a conductor. If a much lower frequency bound is used.10.10 indicates that the noise around 10' dominates. first we briefly describe these noise phenomena. because the integration of I Ix approaches infinity if either the upper bound is infinity or the lower bound is zero. the largest power contribution will touch it first. shot. However. region N I does not contribute much noise since the noise was only integrated above I Hz.43) Thus. in this example. and N3 . lowering a I1f line toward the root spectral density of Vno(f) in Fig. by lowering this constant power! frequency curve. (4. this region can also contribute appreciable noise power. the total output noise can be estimated to be Vno(rmS) = (N 1 + Nz + N J + N4 ) 2 2 2 2 1/2 = 77. where the region N I runs parallel to the I1f tangent line. However. 1If Noise Tangent Principle The lIf noise tangent principle is as follows: To determine the frequency region or regions that contribute the dominant noise. Thus. in practice. 1988]. 4.3 NOISE MODELS FOR CIRCUIT ELEMENTS There are three main fundamental noise mechanismsthermal. Specifically. The reason this simple rule works is that a curve proportional to l/x results in equal power over each decade of frequency. lower a 1/f noise line until it touches the spectral density curvethe total noise can be approximated by the noise in the vicinity of the lIf line [Kennedy. and flicker. = 76.
Flicker noise is also commonly referred to as I/f noise since it is well modelled as having a IIf" spectral density.45) where k is Boltzmann's constant (1. This noise occurs because the de bias current is not continuous and smooth but instead is a result of pulses of current caused by the individual flow of carriers. 1928] and analyzed using the second law of thermodynamics by H. It should be mentioned here that therroal noise is also referred to as Johnson or Nyquist noise since it was first observed by J. Shot noise was first studied by W.3 Noise Models for Circuit Elements 197 is not dependent on bias conditions (de bias current) and it occurs in all resistors (including conductors) above absolute zero. An alternate way to write (4. Resistors The major source of noise in resistors is thermal noise. 1918]. it is a significant noise source in MOS transistors. to reduce the therroal noise due to resistors. shot noise is dependent on the de bias current. 4. With such an approach. where a is between 0. Since the root spectral density is proportional to the square root of the resistance.4. (4.45) is to note that a lkQ resistor exhibits a root spectral density of 4. therroal noise places fundamental limits on the dynamic range achievable in electronic circuits. Flicker noise is the least understood of the three noise phenomena. Although both bipolar and MOSFET transistors have flicker noise. Johnson [Johnson. whereas it can often be ignored in bipolar transistors. Flicker noise usually arises due to traps in the semiconductor.06 nV I JHZ in therroal noise at room temperature (300 OK). where carriers that would norroally constitute de current flow are held for some time period and then released. It is found in all active devices as well as in carbon resistors: but it occurs only when a de current is flowing. Schottky using vacuumtube diodes [Schottky.38 X 10'23 JK. but shot noise also occurs in pn junctions. . 1928]. T IS the temperature in Kelvins. we can also write (4.3. B. Shot noise is also typically larger than therroal noise and is sometimes used to create white noise generators. Nyquist [Nyquist. the spectral density function.8 and 1. is found to be given by Vim = 4kTR . As just discussed. The fact that lower resistance values cause less thermal noise becomes much more apparent when we look at kT Ie noise in capacitors later in this section. As such. VR(I). it appears as white noise and can be modelled as a voltage source. one must either lower the temperature or use lower resistance values. V~(I).46) Note that. in series with a noiseless resistor.I). It can also be modelled as a white noise source. Thus. and R is the resistance size. Carbon resistors are not used in integratedcircuit design but are available as discrete elements.
kT (4. as shown in Fig. rd ' is used for modelling and is not a physical resistor. A common practice is to combine all these noise sources into two equivalent noise sources at the base of the transistor. VR(I) . The spectral density function of the current source is found to be given by I~(I) = 2ql o 19 (4. equals 2 I. as shown in Fig.49) ql o Note that the Thevenin equivalent circuit can also be used. Specifically. 4. and the term is the inputreferred collectorcurrent shot noise (it is often ignored). V. given by I~(f) = V'(I) = 4kT _R_ R' R (4.6 x 10.(I) = 4kT(rb + _1_) 29m (4.51) where the 2qI B term is a result of basecurrent shot noise. the equivalent input voltage noise. can be replaced with a parallel current noise source. the KIB/I term models IIf noise (K is a constant dependent on device properties).48) where q is one electronic charge (1.11 shows. The equivalent input current noise. . hence. Diodes Shot noise is typically the dominant noise in diodes and can be modelled with a current source in parallel with the smallsignal resistance of the diode. It should be noted here that the smallsignal reslstance.C) and I o is the de bias current flowing through the diode.(I).(f). 4.11. as Fig.(I) = 2q I B +  (KI + I 1~(f)I' B Ie) Ie (4. rd' is given by the usual relationship. the flicker noise of the base current. I. is given by V.47) Both resistor models are summarized in Fig. 4.50) where the rb term is due to the thermal noise of the base resistance and the 9m term is due to collectorcurrent shot noise referred back to the input. Here. and the thermal noise of the base resistance. Bipolar Transistors The noise in bipolar transistors is due to the shot noise of both the collector and base currents.11. IR(f).11. the series voltage noise source. The smallsignal resistance of the diode. rd does not contribute any thermal noise. 4.198 Chapter <I • Noise Analysis and Modelling An alternate model can be derived by finding the Norton equivalent circuit.
~ .4.Values depend on opamp . ~ 29 m I~(f) = 4kT R Diode y (Forward biased) BJT kT rd = qI o 2 (Noiseless) * Vd(f) = 2kTr d rd = qI o I'(f) d = 2qI o (Noiseless) Vf(f) (Active region) ~ * V~(f) (Noiseless) = 4kT(r b + _1_) J I I' .3 Noise Models for Circuit Elements 199 Element Noise Models Resistor t R .~. (I) = 2q Is + +  1~(f)12 MOSFET . .11 Circuit elements and their noise models. . all uncorrelated V~(f) ~'~+(f) * Fig. 4. 'n_(f).2 f n() ~ let t ~eleSS) + Vn(f).'V~(f) * ("'~'I ~ = 4kTR (Noiseless) .Typically. 'n+(f) . (I) ~.I 3 gm WLCoxf Simplified model for low and moderate frequencies I~(f) = 4kT(~Pm Opamp . t o(!)i ~ '~(f) V~(f) = K WLCoxf ~ ~~ (Active region) o@i V~(f) ~ (Noiseless) K V2 (f) = 4kT (2f + . a ( K Is i. Note that capacitors and inductors do not generate noise.. I.
If the transistor was in triode. In other words. WL. the input current noise source is partially correlated with the input voltage noise source.200 Chapter 4 • Noise Analysis and Modelling A couple of comments here are that the noise of rb typically dominates in VP).53) for the case V DS = VG S . Thus. typically pchannel transistors have less noise than their nchannel counterparts since their majority carriers (holes) are less likely to be trapped. noise analyses are done just by including this noise source between the transistor drain and source. Sometimes. The flicker noise is modelled as a voltage source in series with the gate of value V'I _ g() . However. when the transistor is in the active region. 4. As a result. L. it is common practice to assume that the input voltage and current noise sources in a bipolar transistor are uncorrelated. analysis may be simplified if it is replaced by an equivalent input noise source.' MOSFETS The dominant noise sources for active MOSFET transistors are flicker and thermal noise. 5. then the correct analysis is more difficult and beyond the scope of this text. we note that the drain current is equal to the gate voltage times the transconductance of the device.VT · Often. .52) where the constant K is dependent on device characteristics and can vary widely for different devices in the same process. larger devices have less l/f noise. the thermal noise current in the drain due to the channel resistance would simply be . and thus. the channel cannot be considered homogeneous. and gate capacitance per unit area. and Cox represent the transistor's width. however.WLC K ox I (4. To find the equivalent noise voltage that would cause this drain current. An important point to note here is that the l/f noise is inversely proportional to the transistor area. Ii (I) . or. P becomes small. as shown in Fig. If neither noise source dominates. Also. and the basecurrent shot noise often dominates in the inputcurrent noise. Fortunately. In this case. at high frequencies. II. respectively. because it typically dominates at low frequencies unless switchingcircuit techniques are used to reduce its effect. Id(l) = 9m Vi(I). The derivation of the thermal noise term is straightforward and is due to the resistive channel of a MOS transistor in the active region. mathematically. Such an integration results in the noise current in the drain being given by (4. An exception to this is highfrequency designs in which the collector shot noise becomes more important because. the total noise is found by integrating over small portions of the channel. this case is not often encountered in practice. l/f noise is extremely important in MOSFET circuits. The variables W. given by Id(l) = (4kT)/r ds' where rds is the channel resistance. the equivalent voltage and current noise are not derived from the same noise sources. length.
EXAMPLE 4.3 Noise Models for Circuit Elements 201 Thus.4. one should be aware that this simplified model assumes the gate current is zero. if in doubt. However. Considering IIf noise only. so we have Id = 2 10 (f) = IOK9~ WLC 0' f (4. = 1O(f) = 2 IOK9~ = K (4. it should be noted that no gate leakage noise terms have been included in this noise model since.6 A large MOS transistor consists of ten individual transistors connected in parallel.53) by 9~ results in the simplified MOSFET model. the IIf noise can be modelled as a current source going from the drain to the source with a noise spectral density of (4. . 9m = 10' is equal to 10 9m' Thus. which in this case is 10 WL.11. Finally. the drain current noise spectral density of the equivalent transistor is ten times larger. but the input voltage noise spectral density is ten times smaller. we have V. one should use the model with the thermal noise placed as a current source in parallel with the drainsource channel. also shown in Fig. although most noise analysis can be performed using the simplified model. Although this assumption is valid at low and moderate frequencies. in modern process. 4. where there is now only one voltage noise source. the draincurrent noise spectral density is ten times larger. Cgs' at higher frequencies.52). In summary. an appreciable amount of current would flow through the gatesource capacitance.55) When this noise is referred back to the input of the equivalent transistor. When ten transistors are connected in parallel. dividing (4.56) since the transconductance of ten transistors in parallel. This result is expected because the input voltage noise source due to Ilf noise is inversely proportional to the equivalent transistor area.54) where 9m is the transconductance of a single transistor. what is the equivalent input voltage noise spectral density for the ten transistors compared to that of a single transistor? Solution From (4. the gate leakage is so small that its noise contribution is rarely significant.
C. notation is simplified from V n(f) to V n . as shown in Fig.4. In fact. Also. dominates. the current noises can often be ignored at low frequencies since their values are small. With an opamp that has a MOSFET input stage. is noiseless.12. .12(a). A similar conclusion can be drawn with In+(I). R. 4. as shown in Fig.13(b). we will see that the capacitor noise meansquared value equals kT IC when it is connected to an arbitrary resistor value.13(a). is large. the circuit shown in Fig. Here.11. and Ib) equivalent noise model circuit. Capacitors and Inductors Capacitors and inductors do not generate any noise. R. 4.12 (b) Opamp circuits showing the need for three noise sources in an opamp noise model. To determine the total noise meansquared value across the capacitor. C. lowpass. 4. t C (a) (b) Fig. In Fig. Here. Consider a capacitance. 4. as shown in Fig.12(b) indicates that the output noise voltage equals Vn(I).13 (a) Capacitor. in parallel with a resistor. the voltage noise source. filtered signal with VR(I) as the R~Vno(f) VR(f) = J4kTR . and so on. R. Assume the resistance. if Vn(l) is not included in the model. The equivalent circuit for noise analysis is shown in Fig. in parallel with a resistor of arbitrary size. for bipolar input stages. a unitygain buffer with no resistors indicates that the circuit output is noiseless. However. 4. However. Vn(f).202 Chapter 4 • Noise Analysis and Modelling ~Vno(f) 10(1) ~2 = ig~ored: V~o V~ Actual: V2 = V2 + ( I n_R)2 no n (a) Fig. they do accumulate noise generated by other noise sources. 4. the current noise may dominate if the resistance.4. all three noise sources are typically required. we note that Vno(l) is simply a firstorder. If 10(1) is not included in an opamp model.12(c). as shown in Fig. Opamps Noise in opamps is modelled using three uncorrelated inputreferred noise sources. 4.
. Some feedback circuits can make the noise smaller but signal levels are also typically smaller (see Problem 4. the minimum capacitor size that can be used (without oversampling) is 16." Thus.6 pF (4. kT I~o(rms) = T (4. what capacitor size is needed to achieve a 96dB dynamic range in an analog circuit with maximum signal levels of I V rms? Solution The value of noise that can be tolerated here is 96 dB down from I V rms .60) 6. Eq. which have reduced bandwidth but larger noise spectral density.8 ~V rms (4.9) . Therefore.7 At a room temperature of 300 "x.59) Vn(rms) Thus. regardless of the resistance seen across it. V~(f)(~\ 2)' = (4kTR)(~X_l_) 2 27[RC (4.58) C kT 2 = 16. (4. and since the input has a white spectral density. The use of this minimum capacitor size determines the maximum resistance size allowed to achieve a given time constant.3 Noise Models for Circuit Elements 203 input. we recognize that the noise bandwidth is given by (7[/2)1 0 (see Section 4.57). either the temperature must be lowered or the capacitance value must be increased.4. the total output meansquared value is calculated as V~o(rms) = 2 VnO(rmS) .2. it should be stated that this noise property for capacitors gives a fundamental limit on the minimum noise level across a capacitor. Finally. Finally. we have = 15.8). it should be mentioned that the equivalent noise current meansquared value in an inductor of value L is given by (see Problem 4. EXAMPLE 4.36). compared to large resistances. the rms voltage value across a capacitor is equal to JkT IC . to lower the noise level. which is Vn(rms} Using (4.6 pF.57) = C kT In other words. Such a result is due to fact that small resistances have less noise spectral density but result in a wide bandwidth.
these choices of noise sources simplify the circuit analysis. When <Pclk drops. 1.000) and all samples are averaged. if many samples are taken (say. and In+(I) represent the opamp's equivalent input noise. the transistor turns off and. as shown in Fig. the averaged value will have a reduced noise level. . Specifically. whereas their noise values add as the root of the sum of squares. Vn(l) .14. 4. in an ideal noiseless world. the resistance when the transistor is switched on causes the capacitance volt age noise to be equal to JkT IC. the noise as well as the desired signal is held on C. However.4 NOISE ANALYSIS EXAMPLES In this section. the input voltage signal at that instance would be held on capacitance C. This fact suggests a method to reduce the noise level of a signal measurement.15. 4. As a result. 4. For example. when thermal noise is present. Opamp Example Consider an inverting amplifier and its equivalent noise model. taking only one sample results in a noise voltage of JkT IC . one should obtain a sampled value of an analog voltage.204 Chapter 4 • Noise Analysis and Modelling Sampled Signal Noise In many cases. switchedcapacitor circuits make extensive use of sampling. in the case where v in is a de (or lowfrequency) signal. However. Note that current noise sources are used in the models for R 1 and R" whereas a voltage noise source is used for R 2 • As we will see. the main purpose of this section is to give the reader some experience in analyzing circuits from a noise perspective. Consider a basic sampleandhold circuit.14 A sampleendhold circuit.4. Although some useful design techniques for reducing noise are presented. when the switch is turned off. The reason this technique improves the measurement accuracy is that. their signal values add linearly. ~c1k V in 1 n rc J Fig. This technique is known as oversampling and will be discussed at length with respect to oversampling converters in Chapter 14. In(f). lt should be noted that this noise voltage will not depend on the sampling rate and is independent from sample to sample. a fundamental limit occurs for sampled signals using a capacitance C an rms noise voltage of JkT IC. when individual sampled values are summed together. as shown in Fig. a variety of circuits are analyzed from a noise perspective. Thus. and the remaining noise sources are resistor thermal noise sources. Here. and sampleandhold circuits are commonly used in analogtodigital and digitaltoanalog conversion.
15 (a) Lowpass filter.4. due to the three noise sources at the positive opamp terminal can be found as follows: By converting In. and R.. Thus. consider the output noise voltage. resulting in an infinite amount of meansquared volts. to a voltage source (by multiplying it by R 2 ) . V~o. if R. and their total current sum is fed into the parallel combination of C.4. V~o2(f).« R" then its gain approximately equals unity for all frequencies. ' the lowfrequency gain is roughly R.I R]. since the voltage across it is zero due to the virtual ground at the negative opamp terminal (assuming a highgain opamp). However. This noise portion is then shaped by a lowpass filter with a 3dB frequency equal to 10 = 1/(2rrR. (a) (b) Fig. In the case where R. These three noise currents add together. and I n_. due only to In" I nt.C t) . we see that the three noise voltages are summed and are applied to the positive opamp terminal.4 Noise Analysis Examples 205 R.62) This equation indicates that this part of the output noise meansquared value equals the sum of the noise voltages. and this noise portion is then shaped by the shown transfer function. + R. using superposition and assuming all noise sources are uncorrelated. the output noise meansquared value due to these three noise currents is given by (4.61) This equation indicates that this part of the output noise value equals the sum of the noise currents multiplied by R~. for practical circuits. the output meansquared value. and its 3dB frequency is the same as in the . the gain drops off above the unitygain frequency of the opamp. (I). Since the gain from the positive opamp terminal to the output signal is easily found. Note that no current passes through R. and thus the noise is effectively lowpass filtered. the output noise meansquared value due to these three noise sources is given by (4. Thus. the noise would exist up to infinite frequency. First. for an ideal opamp. Using superposition further. For this transfer function.» R. and (b) equivalent noise model.
= 9. 10 = l/(2ltR.406' + 1. Thus.65) (4. Finally.64) EXAMPLE 4.(I) + V~o2(1) or.63) z = VnO!(rms) 2 + V' noztrrns) (4.28 pAlJHZ (4. . = lOOk. and the unitygain frequency ofthe opamp.15.4 Ii V)' . above 10 .:2 I Vno'(rms) = (147 nV/"Hz) x 4(100 kn)(160 pF) (4.6 pAlJHZ.C. Also. the resistor noise sources are equal to In' = 0. one should also include the opamp's positive input noise (with a gain of one) integrated over the region between I. where 10 = l/(2ltR.28' + 0.61).(O) = [I~I(O) + I~.)l o' Thus. and that its unitygain frequency equals 5 MHz. find the SNR for an input signal equal to 100mV rms .66) Vnz = 12.67) V~o. both its noise currents are In(l) = 0. R I = 10 k.1 k. Specifically. the gain drops off at20 dBI decade.61) also indicates that this noise is lowpass filtered..(O) + I~(O)lR.6')( I x 10= (147 nV/JHZ)' 12 ) '( 100 k)' (4. 4.. r.).68) Since (4. the rms output noise value due to these three sources can be found using the concept of a noise equivalent bandwidth. the gain only decreases to unity and then remains at that level. Solution Assuming the device is at room temperature. Treating the Bode plot as exact and noting that. if rms values are found. = (0. = 160pF. as shown in Fig./R.206 Chapter 4 • Noise Analysis and Modelling case of the noise sources at the negative opamp terminal (i.C.)). However. Vno(rms) (4.406 pAlJHZ In' = 1. and R. R. = (R.69) = (18. the total output noise meansquared value is simply the sum V~o(l) = V~o. (4. Assume that the noise voltage of the opamp is given by Vn(l) = 20 nV IJHZ.2 nV IJHZ The lowfrequency value of V~ol(l) is found by letting I = 0 in (4. in this case. we multiply the spectral density by (ltlo)l2.e.8 Estimate the total output noise rms value for a lOkHz lowpass filter. when C. this transferfunction reaches unity around I.
Thus. we wish to find the optimum bias current to minimize the equivalent input noise of this amplifier (i. one can find the equivalent input noise value by dividing the output noise value by the circuit's gain and then relate the input signal and noise meansquared values.1 x 4R. To obtain the SNR for this circuit with a lDOmV nns input level. we find V~o'(O) to be given by V~02(O) = [l~+(f)R. one can find the output signal meansquared value and relate that to the output noise value.70) This noise is also lowpass filtered at fo until f 1 = (R. contributes to the output noise through both its thermal noise and the noise current of the oparnp's positive input.(f) + V~(f)](1 + Rt/R J)' = (24. should be eliminated in a lownoise circuit (assuming de offset can be tolerated). we have z 9 Vnoztrrns) = (265 x 10. as would choosing an opamp with a lower noise voltage.I R J)f o' where the noise gain reaches unity and it remains until ft = 5 MHz (i.). the unitygain frequency of the opamp). ( _ 1_ ) + (24.16. 4.e.1 nV/$)'x = (265 nV/$)' n' (4.72) It should be noted here that the major source of noise at low frequencies is due to the opamp's voltage noise.4 Noise Analysis Examples 207 To estimate the output noise due to the sources at the positive opamp tenninal. Alternatively.71) Thus. which gives an SNR of SNR = 2010g(~) = 77 JlV 82 dB (4.73) Note here that using a lowerspeed opamp would have reduced the total output noise. Since its only purpose is to improve the de offset performance. + V.6 Jl V)' 1O9)'(~\f.lV nTIS (4. R.. Taking the first approach results in an output signal level of I V nns . Vn(f). Bipolar CammonEmitter Example In this example. breaking this noise into two portions..C t = (74. we consider a bipolar commonemitter amplifier.fJ) 2/ (4.38) to calculate the first portion. Also note that R. .4. maximize the signaltonoise ratio of the amplifier). as shown in Fig.e. Here. the total output noise is estimated to be Vno(rms) = JV~ol(rmS) + V~02(rmS) = 77 J. and using (4.
75) These assumptions are reasonable since usually Iii noise is not important for bipolar transistors. the input voltage noise due to the transistor alone is given by V~(f) = 2kT/ gm and the input current noise due to the transistor alone is given by (4.)9mRcl' Now the gain from the input voltage noise source to the output is given by Av = . Therefore.77) To represent the output noise due to the input current source by an equivalent input (4. Also. (4. and the impedance looking the output noise due to I~(f) is given by (4. note that transistor output impedance. First.78) .. the gain from the base to the collector (ignoring the fo ) is equal to 9mRc.= 9mRc Vi r. into the base is f. Therefore. although the base resistance has temporarily been ignored.76) V~. + Rs voltage source. and the collector shot noise is usually not a major component of the input current noise source for wideband examples.74) Ij(f) = 2qI B .(f) = I~(f)[(Rs II f.16 A bipolar commonemitter amplifier. r. we have v. We should state that it is assumed here that the collectorcurrent shot noise dominates in the input voltage noise source and the basecurrent shot noise dominates in the input current noise source. it will be taken into account shortly by simply modifying the size of the source resistance. (4. The first step is to replace the input current noise source by an input voltage noise source.208 Chapter 4 • Noise Analysis and Modelling Fig_ 4.
16. (4.4.. 2(kT)' 2qIeR~ ~ + 4kTR s (4.83) These two equations are good approximations for most applications of bipolar commonemitter amplifiers. and the base resistance is given .ola.82) ql e f' Alternatively.82) can be expressed in terms of 9m = qIe/(kT) as in [Buchwald. (I) + V.82) with respect to Ie and set the result to zero.84) opt = .4 Noise Analysis Examples 209 We can now replace all noise sources by a single voltage noise source. C e = I pF. R s = 500 Q.85) EXAMPLE 4. '2 (4. where R e = 10 kQ.+ ql e . Ji3 (4. we have .(I) = + 2qI sR s + 4kTR s 9m Substituting 9m (4. However. Finally. which includes the noise due to the input voltage noise source and the input current noise source of the transistor.(f) = V. we differentiate (4. the second term (which models the transistor collector shot noise) decreases with increasing collector bias current. Vi = 10'a. 9m = (4.79) The first «wo terms represent the noise of the transistor and the third term represents the noise of the source resistance. we find V.9 Consider the commonemitter amplifier shown in Fig.78).82). Using (4.80) = qIe/(kT) and Is = Ie/~. the first term models the transistor basecurrent shot noise and increases with increased bias current. as well as the noise of the source resistor. 1995] (4. and (4.. (I) V i tota! = + R + s+r b e (4. = 10Ial(l) = . 2kT . ~ = 100.eq(l) + 4kTR s . 4. the terms modelling the noise of the source resistor and the transistor base resistor are independent of the transistor bias current. We have V. = . (4.75). Notice in (4.74). equivalently.81) The noise of the transistor base resistor can now be included by replacing R s with R s + rb to obtain 2(kT)' 2qle(R s + rb ) ' 4kT(R ) . This yields the rather simple result of Ie = opt or. To find the optimum bias current.
even though the source resistance is moderately small.(I)] tl2 = 19. V n2 (4. we now use (4.026 x implying that 500 + 300 JWO = 0. V no' The gains from Vn l and Vn' are the same as the gains from the input signals. we find Ie =opt = 0.46 x 1017 V1Hz 'J (4. Voltage noise sources are used here since we will be addressing the lowfrequency noise performance of this stage. Even for no source resistance.210 Chapter 4 • Naise Analysis and Modelling by r b = 300 n. we have assumed matching between transistor pair 0 t and 0.84).91) where R o is the output impedance seen at V no' . At room temperature. as presented in Fig.87) To find the output noise spectral density. nol v. 4.= 12. as well as in pair 0 3 and 0 4 .90) CMOS Example In this example. Assuming the RC time constant at the collector dominates the frequency response.325 rnA (4. for a very low source resistance. 300 OK).1 J.86) Ie 9m = .l V (4.83) to find Vi = 2 total (I) = 4kT(500 + 300 + 40 + 40) = 1.5 mA/V VT (4. find the optimum bias current and the total equivalent input noise. Note that each of the transistors have been modelled using an equivalent voltage noise source. We start by finding the gains from each noise source to the output node.88) Notice that the noise due to the source resistance dominates.11. (i. Thus. resulting in I V = IV nol = 9ml a. Solution Using (4.e.17. the noise bandwidth of the amplifier is given by Ix = 4R eC e 2 I = 25 MHz (4. as shown in Fig. It should be mentioned here that in the following derivations. the major way to improve the noise is to minimize the base resistance by using larger transistors (or to combine a number of parallel transistors). we look at the input circuitry of a traditional twostage CMOS opamp.89) resulting in the total inputreferred voltage noise given by I V nkrms) = [x Vi = tota. 4. the thermal noise due to the base resistance would still dominate.
for the white noise portion of V n1(1) and V n3(1).93) Since this last gain factor is relatively small compared to the others. by dividing it by the gain. 4. the output noise value is seen to be given by (4. we have (4. V neq(I). it will be ignored from here on. the drain current is unaffected by Vn3' This implies that the gate voltage of Q 3 is also unaffected by V n3 .95) Thus.(I) = 4kT(~X~) 3 9ml (4. due to the symmetry in the circuit. Thus.96) . Using the gain factors just shown. Therefore. Next. Therefore. for Vn3 • notice that the current through this voltage source must be zero because one side is connected to the gate of Q 3 only.17 A CMOS input stage for a traditional opomp noise sources with MOSFET shown. the drain of Q 2 will track that of Q 1 • As a result. the noise gain from Vn5 to the output can be found by noting that it modulates the bias current and the fact that. assuming all other sources are zero. the last gain factor is given by Vo nl I V n5 9m5 29m3 (4.4 Noise Analysis Examples 211 t<> Vno (Output) Fig. Vn3 is equal to v gs4' and the gain from Vn3 to the output is the same as the gain from Vn4 to the output.94) This output noise value can be related back to an equivalent input noise value. 9ml R o' which results in 2 2 Vneq(l) = 2V 2 nl(I)+2V ni f)(9m3)' 9ml (4. in the smallsignal model.92) Finally. we make the substitution V~.4.
We note some points for I/f noise here: 1. This limits the signal swings somewhat.e. Taking W I wider also helps to minimize Ilf noise. (4. we see here that the two pairs of transistors contribute an approximately equal amount of noise. 3. letting each of the noise sources have a spectral density given by v: (I) n!  _ K I I WlC 1 ox ' (4. we make the following substitution into (4. Taking l3 longer greatly helps due to the inverse squared relationship in the second term of (4.100) we have [Bertails.10 I). 2 [K I (IlnX K. In other words. 4. . However. noise.101) is due to the pchannel input transistors. 5. (Recall that it helps white noise.ll J~ ~ (4. this decreases the inputreferred noise of the pchannel drive transistors.97) 3 9ml 3 9ml 9m3 Assuming 9m3/ 9m I is not far from unity.99) ru nr n' (W/l)lll p Now. to look at the effects of I/f. Specifically. and this noise is inversely proportional to the transconductance of 9m I . The input noise is independent of W" and therefore we can make it large to maximize signal swing at the output. K..212 Chapter 4 • Noise Analysis and Modelling resulting in Y~eq(l) = (9 3 C)k (_ )+C6}T m 1) T1 )'(_ 6 (4. 0 1 and O 2 . For II = l" the noise of the nchannel loads dominate since > IIp and typically nchannel transistors have larger Ilf noise than pchannel transistors (i. as well. 9m I should be made as large as possible to minimize thermal noise contribution.95). but it also increases Iln 2. which arenot the dominant noise sources. > KI ) .98) resulting in y 2(1) = 2y 2 (I) + 2Y' (I)[(W /lhlln] (4. or flicker.. but it may be a reasonable tradeoff where low noise is important.) Taking II longer increases the noise because the second term in (4. which normally greatly dominates at low frequencies.101) is dominant. and the second term is due to the nchannel loads. 0 3 and 0.101) Recall that the first term in (4. 1979] 2 Y nj(l) = Coxl Will + IIp WIl.
R F " The I/f noise of the transistor is ignored because it is assumed that the circuit is high speed.18 A fiberoptic transresistance preamp..19 are the two major noise sources.<>Vout Fig. The light produces electron hole carriers in the depletion region of the reversebiased diode. Cox ('2J 'I (4. 4. In lownoise applications. . and therefore the output of the amplifier becomes positive.19. the analysis would be almost unchanged. Fiberoptic preamps areoften realizedusingJFETtransistors as well. namely the thermal current noise at the drain of Q I and the thermal noise from the feedback resistor. 7. such as a reversebiased diode.' the preamp can be modelled as ~hown in Fig. such that thermal noise dominates.18. as shown in Fig.4 Noise Analysis Examples 213 the inputreferred noise of the nchannelload transistors.. The photodetector is modelled as an input current source along with a parasitic capacitance.4. The light from the fiber cable hits a photodetector.103) FiberOptic Preamp Example The most popular means of detecting light from a fiberoptic cable is to use a transresistance amplifier.. The noise due this second stage is also ignored since the noise sources in the second stage are not amplified by the gain of the first stage. we can integrate (4.101) from value given by 'I to'. causing current to flow through the resistor. to ==:::::Illl ===t Fiberoptic cable + >. The second (and perhaps subsequent) stage is modelled by an amplifier that has a gain of A. 4.102) where In K. to find the equivalent input noise (4. an active load would be too noisy. Gin' Also shown in Fig. which are the dominant noise sources! Finally. butsince theirthermal noise model is identical to the noise model of (he CMOS transistor. A popular choice for the first stage of the amplifier is to use a commonsource amplifier with a resistor load. 4. Assuming a CMOS transistor is used.4.. .
Thus..104). given by 1+ Av RFCT (4. one would choose R F as large as possible to limit this noise.20.4.. the noise current source I~ can be replaced by an input current noise source having a spectral density of 4kTIR F . In a typical design. this constraint greatly amplifies the thermal noise due to input transistor Q I' as we will see next. However.. we have the 3dB frequency of the amplifier. used for noise analysis.. The only parasitic capacitance considered in the transistor model is C gs• since the gain of the first stage is only moderate. A simplified smallsignal model of this preamplifier.fA. Unfortunately. this choice is constrained by the bandwidth requirements of passing the signal frequencies.214 Chapter 4 • Noise Analysis and Modelling L~~:lI I R = 4kT IR 2 +.105) to place the 3dB frequency as small as possible without substantially attenuating the signals. due to the resistor load. 4..105) For a given amplifier gain and detector capacitance. The bandwidth of the second amplifier must be substantially greater than that of the input node to guarantee stability. The gain from the noise source I~ to the output is found by using nodal analysis to be .0 Vout I. = 4kT(~~m Fig.'. and therefore we can assume that C gd and Cdb can be ignored. From (4. is shown in Fig... R F is chosen using (4.. The transfer function from lin to the output is found by using nodal analysis to be (4.. This makes the dominant node for determining stability the input node.. >.104) where Av = AlA2 is the total voltage gain of the preamp and C T = C gs + C in.19 A simplified model for a CMOS fiberoptic preamp. It is also found that this is the same transfer function from I~ to the output.
Vout  l = I~ = 4kT(~pm   Fig. (I) = 4kT + 4kT (2)1 + (j) (R T) . A2 . we know the second pole frequency of the amplifier must be almost four times greater than the closedloop 3dB frequency when lead compensation is not used.109) Notice that the second term starts to quickly increase at a frequency of 8. given by F 2 I.4.106) to obtain (4.107) We use (4.4.' Continuing.20 A simplified smallsignal model used for noise analysis. Lead compensation could possibly be achieved by placing a capacitor in parallel with R F This is beyond the scope of this text. Furthermore.106) At low frequencies. . we use (4. From the discussion on compensation in Chapter 5. this gain is approximately given by 119m' whereas at high frequencies it is as much as I + Av times greater. the highfrequency output noise due to 0 1 is much greater than the lowfrequency noise due to 0 1. (4. in order to refer the noise due to a I back to the input.o l A2 Cg.104) and (4.4 Noise Analysis Examples 215 RF I~ vg = 4k~ iin c.108) and we add to this the input noise source that models the noise of the feedback resistor to obtain the total inputreferred noise. Thus.1'':' RF 3 9mR~ 2 C 2 (4. the only bandwidth limitation of this noise at high frequencies is due to the finite bandwidth of the second amplifier.
SC14.216 Chapter 4 • Naise Analysis and Modelling (4. Massachusetts.110) which is a relatively low frequency. 1995. Continuing. The only parameter left for the designer to choose is the width of the input transistor and.4. Kluwer Academic Publishers. pp. "LowFrequency Noise Considerations for MOS Amplifiers Design. Bertails. P. pp..1928. RF 39mRF 3 9m 4kT 8kT03C T = +RF 3 9m .111) Using the facts that (4. August.115) 4. Analysis and Design ofAnalog Integrated Circuits.. G. of SolidStare Circuits. Vol. therefore. B. .1993. A. 1. normally 2/(39mRF)« I.113) we can write (4. Holt. = 4kT(1 + _2_)+ 8kT03"C. C. Kennedy. 2 (4. V elf is taken as large as possible given powersupplyvoltage and powerdissipation constraints. 1979. Johnson.2 3 C.114) is minimized by the choice C gs = C. J. and we have I~(f) . E. Phys. New York. Grayand R. Norwell. & Winston. John Wiley & Sons. New Y(l 1988. Rev .( gs 2 C +C . Meyer. Buchwald and K.5 REFERENCES J. Operational Amplifier Circuits: Theory and Applications. (I) := 4kT . C gs' It can be shown (by differentiating the second term of (4.+ .n' in which case we have 2 1 4 L 2 I. Rinehart. Vol." IEEE J.114) RF 9 ~n V elf C gs Normally. No. 97109.. 32.n 0 ( R 9~nVelf F J (4.111) as I~(l) := 4kT + 16 kT _ L_ 03. 773776.114) with respect to C gs and then setting the result to zero) that the second term of (4. . Integrated FiberOptic Receivers.112) and that (4.n) 2 (4. Martin.. R.
their noise model is the same as a single resistance of value R I + R" Repeat the problem for parallel resistances. New York.! as opposed to being referenced to 75 r. "LowNoise Monolithic Amplifier Design: Bipolar versus CMOS. At 0. 1928. The output noise of a circuit is measured to be 40 dBm around 100 kHz when a resolution bandwidth of 30 Hz is used. P4.8.s. a lowfrequency measurement has a noise value of 60 dBm when a resolution bandwidth of I MHz is used. 541567. 57. D. P4. 1986. and V0 for the opamp circuit shown in Fig.1993. Massachusetts.. respectively. 1989. Probability and Random Processes for Electrical Engineering. September 1991. What is the expected dBm measurement if a resolution bandwidth of to Hz is used? Find the root spectral density in V I JHZ. pp. where the opamp has a unitygain frequency of I MHz and equivalent input voltage and current noise sources of Vn(l) = 20 nV I JHZ and 1n(l) = 10 pAl JHZ.6 4. Kluwer Academic Publishers.1 Hz.7 on p.3. A. Y. Connelly. 218. 4. What can you say about the area under the curves of the two sketches? Consider the circuit shown in Fig. are in series.! resistance in parallel. Chang.3 4. Find the total noise power in dBm for the cases in which the two noise sources are (a) uncorrelated.1 4. 4. M. Van der Ziel. find the noise level at V. 4. H.6 Problems 217 A. Estimate the total rms noise voltage at V0 . Reading. pp. Nyquist. AddisonWesley. assume dBm values are referenced to 50 r. pp. Vol. Assuming IIf noise dominates. LeonGarcia.6 PROBLEMS Unless otherwise stated.!.7 4.4.5 4. Noise in Solid Stare Devices and Circuits. Sansen. when two resistors of values R I and R. (c) C = +1. Sketch the spectral density of voltage noise across a 100pF capacitor when it is in parallel with a Ikr. John Wiley & Sons.!? Consider the sum of two noise sources of values 20 dBm and 23 dBm. and (d) C = 1. (Leipzig). A. what is the difference in db ifit is expressed in dBm referenced to 50 r. 919. Low Noise Electronic System Design. Ph). Steyaert. Motchenbacher and J.! resistor. what would be the expected noise value (in dBm) over the band from I MHz to I Hz? Show that. By what factor is the noise value at V0 larger (or smaller) than kT II nf'? How do you account for this increase (or decrease)? Also explain why the noise value at V." Analog Integrated Circuits and Signal Processing 1.8 . New York. Assuming an ideal noiseless opamp. C. Ann. Boston. Phys. W.2 Ifa signal is measured to have V(rms) volts. ItOI13. Vol. 32.4 4. and W. 1918. (b) C = 0. John Wiley & Sons. is smaller than kT I I n F. Make another sketch for the same capacitor but with a IMr. Rev. Schottky. Z.
9. P4. P4. P4. Assume the opamps are ideal and noiseless. ino(t) .10 The two circuits shown in Fig. using only dominant noise sources.11 Modify circuit I in Fig. P4. lowpass filter.9 Consider an inductor of value L and an arbitrary resistor in parallel.7 1 nF 1k 1k v.8 4. P4. Show that the current noise.10 such that the new circuit has the same transfer function but uses an 80pF capacitor instead of an 80nF capacitor. (c) Repeat (b) for circuit II. what is the new total output noise? . P4. as shown in Fig. 4.9 4. If the opamp is ideal and noiseless. Ideal noiseless opamp Fig.218 Chapter 4 • Noise Analysis and Modelling 1 nF 20 k Oparnp Vn(l) = 20 nV/JHz In+(I) = In)!) = 10 pAlJHz It = 1 MHz 10 k Fig. (a) Show that the two circuits have the same inputoutput transfer function. has a noise value given by I' notrrns) = kT L ~ rr L fR  i no (l) :r  Fig.10 realize a firstorder. (b) Estimate the total output noise for circuit I.
.6 7k 14 k Problems 219 10k 7k Vi 10k 80 nF Vo ~ 14k Vi 80nF + I Fig. lowpass filter given by A( s) = ... Compare your result with that obtained when using the l/f tangent principle.. pass filter is (nI2)l o..0 0.14.01 0.4 0. .0 10 100 <.13 Frequency (Hz) 4. 40 ~ .: 4.. estimate the total noise above 0..... P4..l+ 2 II 4.14 Consider the noise root spectral density of the signal shown in Fig. 1k .12 4.0 0.3. P4.04 10 k 100 k 0.. P4.1 ~ ~ r. Find the total rms noise value using a graphical approach for 0... 10 k 100 k Frequency (Hz) Fig.. 4.1 Hz for the spectral density shown in Fig. P4.. Show that the noise bandwidth of a secondorder. Sketch the root spectral density for the output signal.' . 1k 4.1 / V V 1. as shown in Fig.. low Ao S)2 (1 + .. Eq. Estimate the total output rms noise value by applying the l/f tangent principle. ..36).13 Using the l/f tangent principle.4. Consider a bandpass amplifier that has equivalent input noise root spectral density and amplifier response.10 1 >. Bandpass amp gain Equivalent input noise spectral density: (nV IJHz) 100 10 1.15 We saw on page 193.1 1..13. (4..0 10 100 0.01 to cc Hz...o) (2nl is equal to (nl 4 )10 .01 0.. that the noise bandwidth of a firstorder.
. that both its noise currents are In(l) = 0. = InF. how does the equivalent input noise density change? ...16. 4.. resulting in 9ml = 9m2 = I rnA/V and 9m3 = 9m4 = 0.whenC.. and that its unitygain frequency equals 2 MHz.18 Consider the CMOS differential input stage shown in Fig.5 mA/V. as shown in Fig.14 4..220 Chapter 4 • Noise Analysis and Modelling Vo 100 (~) . where lin is a IrnA bias current plus a looIlA(rms) signal current.17 Estimate the total output noise rms value for a lowpass filter../Hz .. . If the bias current is doubled. 4. = 1....R. estimate the resulting SNR (in dB) for the two current mirrors over a 50MHz bandwidth (also assume the output noise is white). P4.. Also. 100 Frequency (Hz) 1 k <. 4.15..6k. 10 1.16 Consider the two bipolar current mirrors shown in Fig.1 r.. Assume that the noise voltage of the opamp is given by V0(1) = 20 nVI JHZ.. = O.1 Fig.16 4..6 pA/.. Assuming that the base resistance for each transistor is rb = 330 f. 10 k 100k 0. where' 0 5 supplies a bias current of lOa IlA.R.andR. P4. find the SNR for an input signal equal to 100mV rms... P4. Find the equivalent input noise spectral density associated with thermal noise.)HZ.17.0 0..l and dominates the output noise.0 10 <. 1.= 16k..01 0. i3 i3 = 100 200 Q = 100 Q 200 (a) (b) Fig.
19. However. 5. the design of a traditional opampnamely. Although the twostage CMOS opamp is a classic circuit used in many integrated circuits. it is an excellent example to illustrate many important design concepts that are also directly applicable to other more modem designs. other more modern architectures have gained popularity recently. The second gain stage is normally a commonsource gain stage that has an active load. These more advanced architectures are described in Chapter 6. The output buffer is normally present only when resistive loads need to be driven. In a CMOS integrated circuit.1. where a complementary process that has reasonable ntype and ptype devices is available. This example illustrates compensation techniques needed to ensure stability in closedloop amplifiers as well as to introduce a number of other important design techniques. The first gain stage is a differentialinput singleended output stage. When properly designed. 5. a bipolar version is similar (but slightly more complicated). the twostage opamp has a performance very close to more modem designs and is somewhat more suitable when resistive loads need to be driven. opamp loads are often. 221 . I Furthermore. then it is seldom included. the twostage CMOS opampis used. Capacitor C c is included to ensure stability 1. 3. If the load is purely capacitive. often very similar to that shown previously in Fig 3. Fullydifferential opamps are also described Chapter 6. "Twostage" refers to the number of gain stages in the opamp. but not always. often very similar to that shown in Fig.1 TWOSTAGE CMOS OPAMP The twostage circuit architecture has historically been the most popular approach for both bipolar and CMOS opamps. purely capacitive. one should not overlook the potential of the twostage opamp because fullydifferential versions of this classic opamp are wellsuited to lowvoltage applications since they do not require cascode output stages. Although a CMOS version of this twostage opamp is described here.1 actually shows three stagestwo gain stages and a unitygain output stage.CHAPTER Basic Opamp Design and Compensation This chapter describes the fundamental principles of basic opamp design. A block diagram of a typical twostage CMOS opamp is shown in Fig.4. To illustrate many of these principles. such as ensuring zero systematic inputoffsetvoltage and processinsensitive lead compensation. Figure 5.
19 will be discussed later in this section.5 and 2 times the minimum transistor length Qs 2 300 300 500 :::J1.222 Chapter 5 • Basic Opamp Design and Compensation >_. the numbers next to the transistors represent reason able transistor widths for a lurn process. All transistor lengths are 1.2 Differentialinput first stage  Q3 Q.Differential input stage Fig. ... An example of a practical CMOS version of the twostage opamp is shown in Fig. Because C c is between the input and the output of the highgain second stage.19..2.. 3.. it is often called a Miller capacitance since its effective capacitive load on the first stage is larger than its physical value.50 Bias circuitry Fig. This example is used to illustrate many of the important design principles when realizing the twostage amplifier. when the opamp is used with feedback.. 5..41I:.6 urn."... '.. This is a complementary differential gain stage to that shown previously in Fig. Reasonable sizes for the lengths of the transistor might be somewhere between 1. Commonsource second stage Q7 A CMOS realization of a twostage amplifier. 3. 5.A. Also. 5.\ VOU1 Second gain stage Output buffer A block diagram of a twostage opomp. It should be noted that the first stage has a pchannel differential input pair with an nchannel currentmirror active load. The tradeoffs between having pchannel input transistors versus this stage and the alternative stage of Fig.
1) Recall from Chapter I that 9mt is given by 2 J.70).. + V.5.as 2 (5.) 1 (5. as is the case when an nwell process is used (currently. This equation is at best approximate and ignores all shortchannel effects that become more important for shorter channel lengths in modern technologies. (5. except for a level shift. of transistor by a. which is a major limitation on the maximum positive output voltage. this gain is one of the most critical parameters of an opamp. rds! . This connection is only possible when 0 8 is realized in a well that is isolated from the bulk. for this example opamp. then the gain of the buffer stage is given by . one would require a pwell or twinwell process to realize this output stage. This stage is often called a source follower. resulting in (3. For lowfrequency applications. the substrate of 0 8 is at the same voltage as the source of 0 8 . OpampGain First we discuss the overall gain of the opamp. This connection also results in a smaller de voltage drop from the gate to the source of 0 8 .2) Also.5) where G L is the load conductance being driven by the buffer stage. When it is not possible to tie the substrate of 0 8 to its source. 0 6 . an approximation to the finite output impedance. Its gain is given by (9m7)( rds6 II rdS7)' Thus. is given L rds! = a ' JV DG. Thus. and is repeated here for convenience: Av t = 9mt(rds . because the source voltage follows the gate voltage of 0 8 . whereas digital logic typically makes use of the minimum transistor length.3) 6 where a is a technologydependent parameter of around 5 X 10 I m.4) The third stage is a commondrain buffer stage.l p C 0' [w) L t rb. As Chapter 3 shows. I TwoStage CMOS Opamp 223 of a particular technology. the gain of this sourcefollower stage is given by A VJ 9m8 '" GL + 9m8 + 9ds8 + 9ds9 (5. a popular process). The second gain stage is simply a commonsource gain stage with a pchannel active load. 1 r ds. The gain of the first stage has already been derived. we have JV AV2 = 9m7(rds6 1 r dS7) 1 (5. r0. Tying the substrate of 0 8 to its source eliminates gain degradations due to the body effect. As shown.
Y = 1/2 6 ~ 0.8 V.7 V). Finally.224 Chapter 5 • Basic Opcmp Design and Compensation AV 1 . 5. and RL = 10 kil.5 V. 9. and 2<1>F is twice the difference between the Fermi level in the bulk and the Fermi level of intrinsic silicon (around 0.6) where 9. Thus. 0 7. y is the bodyeffect constant (around 0.2). Using (5. It should be mentioned here that these very rough draingate voltage approximations are reasonable since (5. and Og. J I D = I D = (W 6/W.5 V whereas the transistors in the other two stages have draintogate voltages of I V.\ Find the gain of the opamp shown in Fig.7) Voltage V88 is the sourcetosubstrate (or bulk) voltage.90 rnA/V. is a bodyeffect conductance and is given by (5. assume the draintogate voltages of the firststage transistors equal 0. we find that all of the transistors in the first stage have output impedances of . 9m7 = 1. Since I D. With the use of (5. we need to estimate the output impedances of the transistors.2 using the following assumptions. we use (5. Solution First the bias currents are calculated.3) together with the given approximations that the firststage transistors have VDGi = 0. Next. the power supplies are VDD = V 88 = 2. perhaps 50 percent at best. Assume the bias current of the input differential pair is given by I D .)I D = 100 JlA 5 7 6 and IDS = ID = (W9/W 7)ID = 167 JlA 7 9 We can now calculate the transconductances of ai' O2.3) is only of very moderate accuracy. we have 9ml = 9m'= 0.16 mA/V. These values for the transistor output impedances can be corrected later once a SPICE analysis is run.35 V. Also assume 2 the following process parameters: JlnCox = 3Jl pC ox = 96 JlA/V . we have 10 1 = 10 . a = 5 x 10 IV/m. EXAMPLE 5. To estimate output impedances. and V. do not assume the substrate of 0 8 is connected to its sourcerather. = 100 JlA.5 V.<I>F = 0.5 V . whereas the transistors in the second and third stages have VDGi = I V.5 VI/'). is around 9m/ 5. To find these impedances. and 9m8 = 3.775 mA/V. assume it is connected to the negative power supply. = I O = 10 4 = I D / 2 = 50 JlA . = 9m3 G L + 9m8 + 9'8 + 9d'8 + 9ds9 (5.n = V'P = 0. = 100 JlA.3).
Recall thatthe unitygain frequency of an opampis that frequency wherethe magnitude of the openloop opamp gain has decreasedto one.2 V/V Using (5. The benefit of performing the hand calculations is to see how the gain is affected by different design parameters. we also assume that transistor 0 16 is not present.(rds .6). but aspects such as slewrate limiting (see next subsection) should be included in the simulation. which is included to achieve lead compensation and it has an effect only around the unitygain frequency of the opamp. Frequency Response We now wish to investigate the frequency response of the twostage opamp at frequencies where the compensation capacitor. The last parameter we need to calculate is the bodyeffect conductance of = 2. This allows us to make a couple of simplifying assumptions. which normally dominates at all frequencies except around the unitygain frequency of the opamp. as we will see when we discuss compensation in Section 5.2. but still at frequencies well below the unitygain frequency of the opamp.5 V.7) and assuming VO " . is at ground results in VS B8 A v' = 9m. we calculate that 1 r dS4) 1 = 70. C e.1). C e. we will ignore all capacitors except the compensation capacitor.85 V/V Thus.44 rnA/V. Using (5. 2. Finally. using (5.5. This corresponds to midband frequencies for many applications. This transistor operates as a resistor. 5.Av2Av3 = 6. has caused the magnitude of the gain to begin to decrease. It is worth mentioning that this simplified circuit is often used during systemlevel simulations when speed is more important than accuracy. = 64 kn 0 8 .4). = The output impedances of transistors in the second stage are 107 kn whereas the output impedances of transistors in the output stage are rdsS = rds.3.1 rds' TwcrStage CMOS Opamp 225 = r ds' = r ds 3 = r ds 4 = 182 kn r ds 6 = r ds. First.' Second. it should be mentioned here that this result is a rough approximation and should be verified using SPICE. 9m8 G L + 9m8 + 9s8 + 9ds8 + 9dS9 = 0. 102 V/V And using (5. .090 V/V. and thus we have 9S8 = 0. Once again. The simplified circuit used for analysis is shown in Fig. the total gain is equal to Av.
Yin 01 Q.8) The gain in the first stage can now be found using the smalIsignal model of Fig.11). If we further assume that A. then the overalI gain.12).9) and (5. we have  =AA~ 3 'sCcA . Ceq. +i= Fig..3 ~"VVout 9m1 Yin A simplified model for the opamp used to find the midband fre quency response.10) For midband frequencies. where = rds211 rds411C S eq = I (5. = I sC CA2 (5. 5. The second stage introduces primarily a capacitive load on the first stage due to the compensation capacitor.11) For the overalI gain. given in (5. 300 300 v. (5. C c. and we can write I Zoutl  sc. Using MilIer's Theorem [Sedra. '" I.20. one can show that the equivalent load capacitance. simplifies to . 3. (5. the impedance of Ceq dominates. resulting in A. 1991].12) using (5. is given by. f.226 Chapter 5 • Basic Opamp Design and Compensation Qs Vbias 01 V in+ 300 0+.9) (5. at node v.
the currentmirror pair 0 3 and 0 4 is shut off because 0 I is off. the current coming out of the compensation capacitor. goes entirely through 0 1 and also goes into the currentmirror pair.771 x 10. is a large negative voltage. = OJ la/ (21l) = 24. When v.2 Using the same parameters as in Example 5.e. Both of these effects will cause the unitygain frequency to be slightly smaller than that calculated. Thus. the bias current. and assuming C e is the unitygain frequency in Hz? 5 pF.771 rnA/V and (5. 105' Defining the slew rate.14) Note here that the unitygain frequency is directly proportional to gm I and inversely proportional to C e. to be the maximum rate that v 2 can change.12 Thus.5. Performing such a procedure with (5. The slew rate is the maximum rate at which the output changes when input signals are large. what Solution Using gml 0.5 Slew Rate Another important highfrequency parameter of an opamp is its slew rate.13) Av(s) = gml sCe This simple equation can be used to find the approximate' unitygain frequency. we have 3. C e' (i. Specifically.1 TwoStage CMOS Opamp 227 (5.14). In either case. we find that fta = 154. 105' goes directly into C e. we find that 0. <Uta' we set IAvUOJta)1 = I. EXAMPLE 5. When the opamp of Fig. to find the unitygain frequency. It is approximate because it is assumed that A3 s 1 and that the higherfrequency poles are being ignored. 10 4 ) is simply equal to 105 since O 2 is off. all of the bias current of Os goes into either 0 1 or O 2 . and now the bias current.2 Mrad/s MHz. 5. SR. and solve for OJta. we obtain the following relationship: gml OJ la =  Ce (5.3 5 X 10.. los.13). the maximum current entering or leaving C e is simply the total bias current.1.2 is limited by its slew rate because a large input signal is present. . When v ln is a large positive voltage. 0 3. and recalling that v out " v..0 4 . depending on whether v in is negative or positive.
It is usually constrained to be less than twothirds of the secondpole frequency.2. the only ways of improving the slew rate for the twostage CMOS opamp is to increase Vott I' w'a' or both. a lower transconductance in the first stage decreases the de gain and increases the equivalent input thermal noise (see Chapter 4.:~:.a' EXAMPLE 5.16).=:=. Normally one has little control over w assuming a given maximum power dissipation is allowed. we have SR = 210 1w gmt . what is the slew rate? What circuit changes could be made to double the slew rate but keep w and bias currents unchanged? .4).18) we finally have another relationship for the slewrate value.15) where we used the charge equation q = CV. As we will soon see. we have C c = gm. It should be mentioned here that increasing Vott I lowers the transconductance of the input stage. and substituting this into (5.a . and assuming C c = 5 pF. we can also write 210 1 SR =  = dq/dt = (5. Section 4.19) V e ft ! := (5. on compensation. Although increasing Vettt helps to minimize distortion.14).=w'a = V ettl w. Since 10 5 = 210 1.228 Chapter 5 • Basic Opamp Design and Compensation SR ss dVO"tl dt max ax = Iccl m = Cc (5.lwta.:.3 Using the same parameters as in Example 5.a J2~pCox(W/L)llol where (5. Also. obtaining a high slew rate and unitygain frequency are two of the major reasons for choosing pchannel input transistors rather than nchannel input transistors. . 210 1 S R = c:=~:::::.17) Recalling that gml = 2~pCoxG='} 10 1 (5.16) Cc where 10 I is the original bias current of Q I with no signals present. which leads to I C(dV /dt). as we will see in Section 5.20) from Chapter I.1. using (5.a (5. As a result.
. one could let WI = W. Fig. when the differential input voltage is zero (i.5. as shown in Fig.5. Indeed. To ensure that no systematic inputoffset voltage exists. gml should be halved. consider the first two stages of the opamp.4 The input and gain stages af the fwostage apamp.4. Systematic Offset Voltage When designing the twostage CMOS opamp. by 4 (i.: olEU: 300 300 Vout2 300 150 . To maintain the same unitygain frequency.16). 10 6.21) To double the slew rate while maintaining the same bias currents. the output voltage of the first stage. if one is not careful. we have S R = 2 x 50 Il A = 20 V Ills 5 pF (5. it is possible that the design will have an inherent (or systematic) inputoffset voltage. the value of VGS7 should be given by (5. To see what is necessary to guarantee that no inherent inputoffset voltage exists. . this was the case for many of the original designs used in production microcircuits. = Vin).e. VGS7' should be that which is required to make 10 7 equal to its bias current.5 pF.22) Q5 v. C c should be set to 2. Specifically.J fi IL Q.e. = 75 urn).1 TwoStage CMOS Opamp 229 Solution From (5. when v . 5. which can be accomplished by decreasing the widths of Q I and Q.
.4 Consider the opamp of Fig. and by satisfying (5. feedback will cause the differential input voltage of the first stage to be equal to a nonzerovoltage needed to ensurethatthe second stage does not clip. (5. Therefore. 210 4 J.IA. then the output of the second stage (with 0 6. or.23) results in (5.= (W/L)4 (W IL)6 2 :::c (W/L). and we want the output stage to have a bias current of 150 J.24) so equating (5. these effects cause only minor offset voltages. EXAMPLE 5. (5.2.24) to satisfy (5. equivalently.22) and (5.23) This value is the voltage necessary to cause 10 . VGS" is given by (5. and 0 4 are each changed to widths of 120 J. Since = (W/L)6 (W/L).22). When the opamp is incorrectly designed to have an inherent inputoffsetvoltage. the output voltage of the first stage./2 (5.25) or.27) we see that the necessary condition to ensure that no inputoffset voltage is present is (W ILl.230 Chapter 5 • Basic Opamp Design and Campensation When the differential input voltage is zero. 5.28) which is satisfied for the sizes shown. when the current density of 0 4 is equal to the current density of 0" guarantees that they both have the same effective gatesource voltages. to satisfy (5. Note that this analysis ignores the voltage drop of the levelshifter output stage (0" 0 9 ) and any mismatches between the output impedance of pchannel and nchannel transistors.28)." However. offset voltages on the order of 5 mV or less can be obtained.) would clip at either the negative or positive rail since this stage has such a high gain. If this value is not achieved.26) This equality.In C ox( W / L )4 + Vln (5. the gatesource voltage of 0 4 is given by VGS 4 = . 4.0. to be equal to 10 6 . in other words. the drain voltages of both 03 and 0 4 are equal by arguments of symmetry. Fortunately. :::c.Im. where 0.
Finally. This result is seen from (5. which is critical when highfrequency operation is important. For a given power dissipation.29) W _ 7  2(450)(120) = 360 300 urn (5. and since it should have 50 percent more current than 10 5 . the overall de gain is largely unaffected by the choice since both designs have one stage with one or more nchannel drivinglransistors. Having a pchannel input first stage implies that the second stage has an nchannel input drive transistor. are both proportional to the transconductance of the second stage. and thus most knowledgeable designers choose a pchannel input for the first stage.1 TwoStage CMOS Opamp 231 Find the new sizes of Q 6 and Q 7 ' such that there is no systematic offset voltage. we use (5. The choice of which configuration to use depends on a number of tradeoff's that are discussed here. The one disadvantage of having an nchannel source follower is that. and one stage with one or more pchannel driving transistors. for nwell processes. and therefore the unitygain frequency as well. It is also possible to realize a complementary opamp where the first stage has an nchannel differential pair and the second stage is a commonsource amplifier having a pchannel input drive transistor. the effect on the equivalent second pole due to its load capacitance is minimized. This arrangement maximizes the transconductance of the drive transistor of the second stage. since an nchannel transistor has a higher transconductance. it is not possible to . As we will see in the next section. Another consideration is whether a pchannel or nchannel sourcefollower output stage is desired. Typically.28).19) since pchannel input transistors for the first stage have a larger Veft than would be the case for nchannel input transistors (assuming similar maximum widths have been chosen to maximize the gain). there is less degradation of the gain when small load resistances are being driven. This slewrate improvement can be one of the most important considerations. Solution Since 10 6 determines the bias current of the output stage. and therefore bias current.30) nChannel or pChannellnput Stage The twostage opamp discussed above has pchannel input transistors. First. Also. which is another important consideration. the equivalent second pole.5. having a pchannel inputpair stage maximizes the slew rate. which leads to (5. an nchannel source follower is preferable because this will have less of a voltage drop. its width should be 50 percent greater than W 5 ' resulting in W6 = 450 urn For Q7.
However.31) 5. Some useful circuittechniques to reduce the effects of IJf noise arccorrelated double samplingand chopper stabilization. Section 4. 5. almost all the material discussed here applies to most other opamps as well. Finally. unitygain frequency. This IIf noise source can be especially troublesome unless special circuit design techniques are used. and minimizes Iff noise. but also has good settling characteristics.2 FEEDBACK AND OPAMP COMPENSATION This section discusses using opamps in closedloop configurations and how to compensate an opamp to ensure that the closedloop configuration is not only stable.232 Chapter 5 • Basic Opamp Design and Compensation connect the source to the substrate.4). A(s).' Typically. for opamps that drive purely capacitive loads. it is minimized by using input transistors that have large transconductances (Chapter 4. is normally used. Before discussing compensation. When thermal noise is referred to the input of the opamp. such as a foldcdcascode opamp (discussed in Chapter 6). thereby minimizing the voltage drop. Optimum compensation of opamps is typically considered to be one of the most difficult parts of the opamp design procedure. having a firststage with pchanncl inputs minimizes the output noise due to the Iff noise. then a more modem architecture. Noise is another important consideration when choosing which input stage to use. and for this case. a pchannel input transistor for the first stage is almost always the best choice because it optimizes slew rate. when using a twostage opamp. pchannel transistors have less Iff noise than nchannel transistors since their majority carriers (holes) have less potential to be trapped in surface states. Perhaps the major noise source of MOS opamps is due to Iff noise caused by carriers randomly entering and leaving traps introduced by defects near the semiconductor surface. Thus. Although the twostage opamp is used as an example. In summary. However. then a straightforward procedure can be used that almost always results in a nearoptimum compensation network. the buffer stage should not be included. . note that. the output stage is clearly not a consideration. The same is not true when thermal noise is considered. if the systematic approach taken here is used. some properties of feedback and closedloop amplifiers will first be reviewed. which unfortunately degrades the slew rate. is given by Ars) (5. FirstOrder Model of ClosedLoop Amplifier A simple firstorder model for the transfer function of a dominantpole compensated opamp. when thermal noise is a major consideration. with the major disadvantage being an increase in wideband thermal noise.
33) into (5. The feedback tenm. ~. 6. represenis the feedback factor. it should be mentioned that all the poles and zeros in this chapter occur on the real axis and are represented by the notations wp and w z ' respectively.31) for the case in which wp 1 «w« Wta' we have at midband frequencies A(s) '=  W ta s (5. We then have the following approximation. especially when the closedloop configuration has large gain.35) At midband frequencies.5. The actual poles and zeros are the negatives of these terms.' Substituting (5." Recall that the definition of the unitygain frequency of an opamp.33) From here on. The unitygainfrequency of an optimally compensatedopampcan be very differentfrom COla due to highfrequency poles and zeros thatare ignoredin the firstorder model. A(s).S. but may not be the case for applications such as damped integrators. we will define w'a to be exactly equal to Aowp" which is approximately equal to the unitygain frequency of the opamp (assuming a firstorder model for the opampt. 1991]. cop and <Oz are the inverses of the coefficients multiplying the S terms in the denominatorsand numerators. the feedforward amplifier. At this point. the transfer function of the closedloop amplifier may be found by substituting (5. To be more precise. w'a' is the frequency at which IAUw'a)1 = 1.34) into (5.I +~A(s) (5. 5. An opamp with feedback can be modelled by the block diagram shown in Fig. which is assumed to be frequency independent. ACL(s).5 [Sedra. However. resulting in Fig.32) Thus. Ao wta/ro p 1 (5. at midband frequencies (5.35). respectively. this is typically the case for amplifiers. . since rota » W p 1: IAUWta)1 = 1 '= . we have the following important relationship for this firstorder model: Wta '= Aowpt (5. for this model is given by A CL (s) _ A(s) . is the (realaxis) dominant pole.34) This approximate relationship is often used to analyze a closedloop circuit for the effects of the opamp's finite bandwidth at midband frequencies.2 Feedback and Opamp Campensatian 233 where A o is the de gain of the opamp and wp . Here.S A black diagram af a feedback circuit. 7.34) is still valid. models the openloop response of the opamp. It can be shown using signalflow graph analysis that the closedloop gain.
and dependent only on highfrequency poles and zeros.. the results here are used only to estimate the necessary unitygain frequency for a circuit to settle within the linear settlingtime segment. However. For example. Thus. This charge transfer is closely related to the opamp's step response. we discuss only the linear settling time by modelling the opamp as ideal but with a finite unitygain frequency. the nonlinear settling time is due to slewrate limiting. the 3dB frequency of the closedloop gain ofan optimally compensated amplifier is approximately equal to the unitygain frequency of the loop gain. the settling time is defined to be the time it takes for an opamp to reach a specified percentage of its final value when a step inPut is applied. the component sizes of the compensation network and rota will be shown to depend on the desired closedloop gain for an optimally compensated amplifier. I3rota '" rot' where rot is the unitygain frequency of the openloop transfer function. t. This settling time consists of two distinct segmentslinear and nonlinear settling time segments. in switchedcapacitor circuits. the opamp may not reach a slewrate limit at all. Such a simplification results in a simple settling behavior that can be easily analyzed. for optimally compensated opamps.234 Chapter 5 • Basic Opamp Design and Campensatian = I I (5. Another simplification is to use the firstorder opamp model. for optimally compensated amplifiers.36). In contrast. . resulting in a nonlinear settling time of zero. and thus this portion is strongly dependent on the output's step size. we recognize that the time constant of the closedloop amplifier. Simulations should be used in the latter parts of a design to determine more accurate settlingtime estimates. For example. the charge from one or more capacitors must be mostly transferred to a feedback capacitor within about half a clock period. From (5. the closedloop amplifier has a closedloop gain at low frequencies approximately equal to 1/13 8 and it has a 3dB frequency given by e. For inverting configurations. which is still given by ~A(s).36) Thus. 13. is given by 8. It will also be shown that. Thus. for small step sizes in the output signal's level. and the closedloop gain at low frequencies is given by Kill But these facts have no effect on the discussions to follow regarding optimum compensation because we are primarily interested in the loop gain. (5.35) should be modified to be ACL(s) == KA(s)/[ I + ~A(s)]. dB = I3ro ta (5. which has a 90degree phase margin. independent of the actual closedloop gain. The linear settlingtime portion is due to the finite unitygain frequency of the opamp. rot is independent of the feedback factor. Here. Linear Setlling Time The settlingtime performance of integrated amplifiers is often an important design parameter. As a result.37) It will be shown shortly that. and thus it sets a minimum value for the overall settling time independent of the step size of the opamp' s output.
. With this exponential relationship. 5.39) to be given by vout(t) = Vstep(Ietl . . note that just after the step input. then one must allow e. the settling time needed becomes approximately 7. to reach 0.5. Recall that the transient response of any firstorder circuit is given by x(t) = X(=)(X(=)x(t)]etl ' (5.41) dt toO If the slew rate of the opamp is largerthan this value. = W_ 3 dB Feedback and Opamp Compensation = 235 (5. ) (5. C. the time required for a firstorder circuit to settle to within a specified value can be found. : : C. For C.1 percent accuracy is ueeded in the linear settlingtime portion corresponding to 0.1 percent accuracy. if I percent accuracy is required.5 One phase of a switchedcapacitor circuit is shown in Fig.2 . Vstep is the size of the voltage step. = O. I cf't+'i+ >'0 Vout A(s) Fig. EXAMPLE 5.6. the step response is found using (5. For tl example.6 One phase of a switchedcopocitor circuit... A difficulty with this network in a nonswitched circuit is that no bias current C.6. For settling to within a 0. If 0. find the required unitygain frequency in terms of the capacitance values.. is the time constant of the circuit. no slewrate limiting would occur.1 us . where the input signal can be modelled as a voltage step.39) where.? Solution We first note that a capacitive feedback network is used rather than a resistive one. given by d Vout(t) I = V  step r (5. 5.40) Here. the slope of the output will be at its maximum. and C. = IOC" what is the necessary unitygain frequency of the oparnp? What unitygain frequency is needed in the case in which C.ZC.01. Also.38) 13wta The important result here is that the 3dB frequency determines the settlingtime response for a step input. For the closedloop amplifier. which is achieved at a time of 4.
in a switched circuit using a CMOS opamp. the firstorder model given by (5. whereas in the case of C.42) Now for 7~ settling within 0. is given by ~ I/(sC I ) . . note that the feedback factor is simply a constant value since it is determined by a capacitive divider consisting of C I and C2· The feedback factor.44) where wpl is the first dominantpole frequency and weq is the pole frequency that models higherfrequency poles. ~. .2 ns. rather than the attenuation.8 MHz.I. we see that r must be less than 14.C'J( 14. and. they can be modelled reasonably well by a single additional pole. we can model A(s) by A( s) . However. l/(~Wla)' we see that wta. Second.1 us.43) For the case in which C. '(1 + slwpl)(1 + Slw eq ) Ao (5. 0. which cause possible instability. In practice.'" I.. It ignores highfrequency poles and zero. even though they may be at frequencies greater than ro. . Fortunately. 1991] since we are mostly interested in the phase shifts.2 ns ) I (5.. lOCI' a unitygain frequency of 12.2C I' f ta should be larger than 66.45) =2 i= 1 It should be noted here that the approximation in (5. . + I (CC. (5. It is important to accurately model the openloop transfer function at higher frequencies where the loopgain is approximately unity. we q is found from simulation as the inverse of the frequency at which the transfer function has a 135° phase shift (_90° due to the dominant pole and another 45° due to the higherfrequency poles and zeros). is given by m n . this connection shown occurs only for a short time and does not cause any problems. wp " and zeros.3 MHz is needed. due to higherfrequency poles and zeros. when all poles and zeros are on the real axis. I/(sC I ) + I/(sC 2 ) C. Opamp Compensation When one is compensating an opamp.(Oeq ffipi cozi i I I I (5.. Specifically.45) is different than that given in [Sedra. since r .236 Chapter 5 • Basic Opamp Design and Compensation flows into the negative opamp input terminal.o. The relationship to approximate weq given a set of realaxis poles.31) is insufficient. 00".
= tan(90° .tan. wt/w p l (l/~)Ao. and therefore.e.52) can be used to derive w. is given by la A(s) = s(l + s/w 00 = LG(s) = ~A(s) = s(l + s/weo) ~w'a (5. 1+ ..47) The unitygain frequency. can now be found by setting the magnitude of (5. 00" of the loop gain. L LG(jw). PM S (5.51) (5. one can write. 00. then.52) (5.PM) which implies that 00.47). Note also that from (5.50) = [ro.47) equal to unity after substituting S = jw.5.l (w/ weo) This equation implies that at the unitygain frequency. it is independent of the closedloop gain as well.46) eo) Note that this approximation result is especially valid at the unitygain frequency of the loop (which we are presently interested in) since./w eo = tan(90° . PM. and so (5.)2 W eo = (Ot ~ (5. Once this is done and the equation is rearranged. (Oeq ~w.)2 (Oeq (5. From (5.53) = LLG(jw.PM)w eo Equation (5. ~. is found as LLG(jw) = 90 0 .l (w../ weo) and. Note that the unitygain frequency of the loop is independent of the feedback factor.33). When the opamp is included in a circuit that has a feedback factor. which is almost certainly much greater than 1. . from (5.00.)(1800) = 90 0 . 00» Wp I' we see that 1 + jw/w p i = jw/w p l . LG(s). PM is defined as the difference between the loopgain phase shift and 180°.2 Feedback and Opamp Compensation 237 At frequencies much greater than the dominant pole frequency.« weo)' The phase margin. ~. is an oftenused measure for how far an opamp with feedback is from becoming unstable. we have (5./w eo for a specified phase margin. ~ w'a . LG(s).49) for the special case in which the unitygain frequency is much less than the equivalent nondominant pole frequency (i.48) we have w'a = w'JI ~ +( 00. at frequencies around w'a' the loop gain. in the case of an optimally compensated amplifier. w.tan.48) O)eq This equation will be used shortly to relate a specified phase margin to the Q factor of the closedloop configuration. the phase shift.44) can be accurately approximated by (5. therefore.
268' = 1.. and thus.. 1991]. .707. which implies that the loopgain unitygain frequency.46). However. K 1++woQ S (5.238 Chapter 5 • Basic Gpamp Design and Compensation EXAMPLE 5../21t = 13. and rearranging gives Ac LO (5. = w.53). for ~ = I. Using (5.54) where (5.268w eq .54) can be equated to the general equation for a secondorder allpole transfer function. S+QS+wo s' wt Recall that parameter 00 0 is called the resonant frequency and parameter Q is called the Q factor" [Sedra.44) into (5.4 MHz. if Q = JI72 = 0. When the step response is investigated. (5. w'a = w.s 1/2 times the inverse of the damping factor. then the magnitude of the transfer function will have the widest passband without any peaking. it would be extremely difficult to adequately compensate the opamp. When considering optimum compensation.JI + 0. The damping factor is an alternative method of indicating the pole locations in secondorder transfer functions. is closely approximated by a secondorder transfer function. The Q factor i. lOt. It should be noted here that this approximation is inaccurate in the case where the highfrequency poles and zeros are quite close to 00. I" is given by I. written as H2 ( s ) = ..9 MHz. we also have. The result of (5. the 3dB frequency is equal to 000 .03500" which implies that I'a = w'a/21t = 13. if leq = weq/(21t) = 50 MHz? What is w'a? ~ I. in this case.49). = 0.6 A closedloop amplifier is compensated to have a 75 0 phase margin for What is 00. It is well known that. restrictions on the Q factor can also be found to guar9.34) is not accurate enough and one must use the more accurate relationship for A(s) given in (5.(00°) . substituting (5. for Q = JI72. the closedloop response near the unitygain frequency.Kw o . Furthermore.35). Assuming ~ is frequency independent.55) Thus. we have 00.56) . this case is ignored. Solution Using (5.
622 0. although it will not be optimally compensated and will be slower than necessary.52) can be used to find co.5.59) where the approximation of Q is valid since j3Ao » I and coP] « coeq. if the opamp is compensated for 13 = I.700 0. given both process and temperature variations. the percentage overshoot of the output voltage is given by .270 Percentage overshoot for a Q factor step input 13.008% 0.1 leads to some interesting observations. and percentage overshoot PM (Phase margin) 0.717 0.. then the phase margin should be at least 75°. it is guaranteed to be stable for all other 13. for a generalpurpose opamp where 0 < 13 '" I.7% 4. Second.] (5. This procedure gives us the information in Table 5.57) Equating (5. These phase margins are much larger than what was traditionally thought to be necessary. for there to be no peaking in the step response.a coeq (5. it is necessary that both poles be real.a COeq and (5. Table 5.58) Q = J(l + j3Ao)lcop]co eq l/co p ] + lIco eq " Jj3A oCOp ] co eq = JI3CO. again.5.54) with (5. which can then be substituted into (5. w. In the case where Q > 0. Equation (5. when 13 '" 1).470 0. (5.360 0. Finally.56) and solving for COo and Q results in COo = J(l + j3Ao)(cop]co eq) " JI3co. values of 80° to 85° should be the nominal phase margin to account for these variations.48) to find j3(co'alco eq).4% 0.817 0. Finally. Table 5. given both process and temperature changes.527 . Q /actar. when the feedback network is frequency independent and less than unity.57) can be used to find the corresponding percentage overshoot for a step input. if one wants to ensure that there is no overshoot for a step input.59) to find the equivalent Q factor. % overshoot = lODe )40' . one should design for a phase margin of at least 65°.1. (i.1 The relationship between PM. a frequency response with Q " J1i2 roughly corresponds to a phase margin of 65°. Specifically.lw.e. It is now possible to relate a specified phase margin to the Q factor. First.3% 8. Therefore.This result can be substituted into (5. Thus.7% 1.580 0. it is worth mentioning here that.".5. the worstcase phase margin occurs for 13 = 1. which is equivalent to the requirement that Q '" 0.lcoeq.925 0.2 Feedback and Opamp Compensation 239 antee no peaking. Normally.
To make the discussion easier to visualize.e.7 The first two stages of the twostage opump. The addition of such an extra lefthalfplane zero is what is commonly called leadcompensation. R c. including the compensation network. Without Q'6' we have a righthalfplane zero. the first two stages of the opamp.60) Transistor Q I6 has V OS I6 = 0 since no de bias current flows through it. The capacitor. 5. (i.. this transistor operates as a resistor. It should be noted here that rds indicates the drainsource resistance of Q I6 when it is in the triode region as opposed to the finiteoutput impedance of Q I6 when it is in the active mode. and thereby the frequency. C c. Thus. and therefore Q I6 is hard in the triode region. of value giveo by Rc = JlnCox(~t V (5.is used to indicate the drainsource resistance in both caseswhether the transis . 5. including the compensation network. realizes what is commonly called dominantpole compensation. wta ' since (repeating (5.7. wp l ).240 Chapter 5 • Basic Opamp Design and Compensotion Os VbiaS1 o1F='i 300 300 Vout2 Vbias2 1 300 Fig..61) eff16 This transistor is included in order to realize a lefthalfplane zero at frequencies around or slightly above 00. are shown in Fig. Compensating the TwoStage Opamp It is now possible to consider compensation of the twostage opamp. ros. w'a = AOwp 1 (5. It controls the dominant first pole. The same notation. which makes compensation much more difficult.33) here for convenience).
If an output buffer is present.. If this assumption is not valid.. Also..64) (5. 0(5).. also includes the capacitance needed to drive Q 9 in Fig.. In the smallsignal model.62) (5.66) (5. tor is in the active or the triode region. then C u is the output load capacitance.o YOU! R.8 A smallsignal model of the twostage opamp used for compensation analysis. 5. it is assumed that the first stage is much faster than the second stage and can therefore be modelled by a simple voltagecontrolled current source.67) and (5. whereas the root is in the right half plane if OJ: < o.68) It is possible to find approximate equations for the two poles based on the assumption that the poles are real and widely separated. = C.... Note that the notation [I + (sl m ) 1 implies that the root is in the left half plane if (Ox > 0 . R2 Fig... 10 This assumption allows us to express the denominator. = C d b? + C d b6 + C u Note that if no output buffer is present. we have R = j r ds .63) (5. .65) C I = C db 2 + C db• + Cgs? r d s6 11 rds? R. we first assume Rc = 0 and perform nodal analysis at the nodes designated by VI and v out ' The following transfer function is obtained: V o ut vin where = I + sa + sb (5.2.5.5. where the output buffer has again been ignored.e. To show the need for R c. then it is extremely difficult to properlycompensate the opamp for unitygain stability.P1P!I"v'lr. then C l 2 is the load capacitance introduced by the output buffer and C. One simply has to check which region a transistor is operating in to ensure that the correct equation is used to determine rdsA simplified smallsignal model for this opamp is shown in Fig. as II 10.8. 11. .2 Feedback and Opamp Compensation 241 v. 1I r d s' (5. 5.
Fortunately. Also note that increasing C e moves the dominant pole. (5. Indeed.72) This zero should come as no surprise since there are two signal paths having opposite signs in the smallsignal circuit of Fig. co" is located in the right half plane and is given by 9mJ Ce (5. Lead Compensation If the smallsignal model of Fig. from (5.' is given by I cop I == R. This separation tends to make the circuit more stable.9mJ R. 5.69) and solving for cop' and co p2 results in the following relationships. cop.71) 9mJ C. the separation between the first and second poles increases.8one through the voltagecontrolled current source. as we discuss in the next subsection. From the preceding relationships for cop. The dominant pole. This makes stability more difficult. +C. because of this righthalfplane zero. + C e) I . in the transfer function of the opamp. Making C e larger does not help matters because this decreases the frequencies of both the first pole and the zero without making them more widely separated. then a thirdorder denominator results.(C. as 9mJ increases. The first two poles are still approximately at the frequencies . cop. However.70) . it introduces negative phase shift.66). Because the zero is in the right half plane. 5.Rle c ( 1+ gm7 R2) 1 (5. or phase lag. another zero. cop. it is often impossible to choose C e such that the step response has no overshoot (assuming R e = 0). Note that. + Ce(l + 9mJR2)] + R.R.8 is reanalyzed with a nonzero Re.' to a lower frequency without affecting the second pole. all is not lost.' This effect also makes the opamp more stable. C e. co.66) equal to the coefficients of (5. a problem arises due to the righthalfplane zero. and cop" we can see that.69) OJ p I ffi p 1(J)P2 Selling the coefficients of (5. since introducing Re allows adequate compensation. hence. the use of a Miller capacitance for compensation is often called polesplitting compensation. cop" is given by 9m e JC (5.lC.242 Chapter 5 • Basic Opamp Design and Campensatian D(5) = (1 + ~)(l + ~) = I + ~ + _5_ Wp1 W p2 . 9 m Jv" and the other through the compensation capacitor.C e whereas the nondominant pole..
For this case. Also. is often not known a priori. (Obtaining this phase margin is the reason we chose 125° in step 2.14) that Ult 9ml/CC' then one should choose R c according to = Rc I =1.2Ult (5.71) and solving for R c results in the following equation for R c : R c = . 20 percent larger [Roberge. The third pole is at a high frequency and has almost no effects.73) equal to (5.75) Unfortunately. + C') ':::"': 9m7 Cc present. C c = 5 pF.. Ulp .74) to eliminate the righthalfplane zero altogether. C.) This can be achieved by taking C c according to the equation C c = CcA' It might be necessary to iterate on C c a couple of times using SPICE. thus resulting in a 55 0 phase margin. This is the frequency that we would like to become the unitygain frequency of the loop gain. let the frequency be denoted co. (5.70) and (5.71). Start by choosing.2 Feedback and Opamp Compensation 243 given by (5. somewhat arbitrarily.76) Assuming R c » (1I9m7)' then Ulz = II(R cCc). . (5. one should satisfy the following equation: Ulz = 1.1 [1 + C. 3. and recalling from (5. Alternatively. Let the gain at this frequency be denoted A' . 1975]. Setting (5. one could choose R c to be even larger and thus move the righthalfplane zero into the left half plane to cancel the nondominant pole.29m' (5. Using SPICE. (5. the zero is now determined by the relationship. One could take (5.77) This approach leads to the following design procedure for lead compensation of a twostage CMOS opamp: 1. Choose a new C c so that Ult becomes the unitygain frequency of the loop gain. 2. find the frequency at which a _125 0 phase shift exists.5. especially when no output stage is The third possibility (recommended by the authors) is to choose R c even larger yet to move the now lefthalfplane zero to a frequency slightly greater than the unitygain frequency that would result if the lead resistor were not presentsay.78) .73) This result allows the designer a number of possibilities. However.
80) Finally. hopefully. In most cases. The first pole contributes _90 0 phase shift. SPICE can be used again to finetune the device dimensions to optimize the phase margin to that obtained in steps 4 and 5. 6. However.) (5. the higherfrequency poles and zeros (except for the lead zero) will not move to significantly lower frequencies when C c is increased. Choose R c according to I 1.)(1 +5/(0 2) Ao(l + 5/00.200.244 Chapter 5 • Basic Opamp Design and Compensation 4. 12 This allows a margin of 5 ° to account for processing variations without the poles of the closedloop response becoming real. This situation sometimes occurs when unexpected zeros at frequencies only slightly greater than OOt are present. This choice is also almost optimum lead compensation for almost any opamp when a resistor is placed in series with the compensation capacitor. and the equivalent second pole contiguities approximately 40° phase shift. The size of the transistor can be chosen using equation (5. the lead zero contributes approximately 45° phase shift.61). otherwise.79) 5. The resulting phase margin is approximately 85°. the transient response can be poor.81) 12. leaving the zero near to the final resulting unitygain frequency. which is repeated here for convenience: Rc = rd.7 An opamp has an openloop transfer function given by A(s) = ='=(I +S/oop. . or the phase margin is not adequate. If. but it (or a very similar procedure) has been found to be almost optimum for compensating most types of opamps. one should check that the gain continues to steadily decrease at frequencies above the new unitygain frequency. This will move both OOt and the lead zero to lower frequencies while keeping their ratio approximately constant. Not only does the procedure just described apply to the twostage opamp. after step 4. This choice will increase the unitygain frequency by about 20 percent. then increase C c while leaving R c constant.C c (5. EXAMPLE 5. do not also move to lower frequencies. t6 = I ~nCox(~)'6 Vefl t6 (5. thus minimizing the effects of higherfrequency poles and zeros which. It might be necessary to iterate on R c a couple of times to optimize the phase margin. The final step is to replace R c by a transistoe. which will end up about 15 percent below the equivalent secondpole frequency.
respectively. setting IA(joo.: LA(joo..200. ./00.200. the dominant pole.2 Feedback and Opomp Compensation 245 Here. 00. (a) Assuming OOz 7 =. Assume that 00.) = 35' (5.82) (s/oop.2 x 10' = 21t x 33 MHz and again using (5.) = . find oop./oop.)1 = = I (5. the value for 00. note that at frequencies much greater than the dominantpole frequency (i. Alternatively.5.88) ~ (Ot = "'. / 0 0 2 ) (5. Both sides can be squared. what is the new unitygain frequency.81) can be approximated by A o( I + s/ooz) A( S) " ./00.e..)(1 + s/oo.)jl + (00. find the new phase margin.84) => 00.82) now gives (oo. = 21t X 50 MHz and that An = 10".82) results in An =I (5. (b) Assuming OOz = 1.. we need LA(joo.)' (5.' ( 0 0 .jl + (oo/ooz)' This equation can be solved for the new unitygain frequency. ? Also.86) = 21t x 4. Solution First. AD is the de gain of the opamp and 00" 00" and 00 2 are the frequencies of a zero.) = 90 0 ./00 2 results in tan' (00. which can be solved exactly." . (5. setting IA(joo." ' (5..87) in (5./00. (where 00. so that the opamp has a unitygain phase margin of 55'. 00.t a n . we set OOz = 1. and the equivalent second pole. is as found in part (a».1800 + PM = _125° Setting (5. 00» oop.82) to find the phase angle at 00.85) (5.84) and solving for 00../00.======::=jl +(00.) (a) For CO z 7 = we use (5. fonnd in part (a) can be used as an initial guess.83) For a phase margin of PM = 55°. and the unitygain frequency. Next. = 21t x 42 MHz To find the new unitygain frequency. resulting in a quadratic equation in (Ot.)' Auoop.28 kHz ooUI + (00.)' Au (b) First..83) equal to (5.)' such as the unitygain frequency..)1 = 2.
= 21t x 46. one finds that ro..4llrn processes). then the lead zero will also be proportional to the transconductance of Q7' As a result.Cd 1I9m7.P Also. the lead zero is at a frequency given by 1 roz = . when a resistor is used to realize lead compensation. +C. These highfrequency poles and zeros will typically degrade the phase margin by an additional 5° or 10°. 13.8 MHz. the lead compensation will be mostly independent of process and temperature variations.91) We see here that the second pole is proportional to the transconductance of the drive transistor of the second stage. the ratios of all of the transconductances remain relatively constant over process and temperature variations since the transconductances are all determined by the same biasing network.lp is relatively constant for a given process (say. we have OOt =  9ml Cc (5. and rop . if R c can also be made to track the inverse of transconductances. .89) Note that this phase value gives a phase margin of 95°. most of the capacitances also track each other since they are primarily determined by gate oxides.14) and (5. Repeating (5. ' as well as all other highfrequency poles and zeros..73). which is a 40° improvement! Normally.. 9m7' Also.6llffi to O. the improvement would not be this great due to additional highfrequency poles and zeros (which have been ignored here).lrn process) butoften varies more significantly from process to process (say. (5.) = .l roz ) tanI(ro. the improvement from using lead compensation is substantial..) = 85. The ratio Iln/j.l ro.6J. This unitygain frequency is a 34 percent increase over that found in part (a).246 Chapter 5 • Basic Opamp Design and Compensation and (5. Repeating equations (5. We can solve for the new phase shift by using LA(jro. 9m I' Furthermore. the lead zero will remain at the same relative frequency with respect to ro.90° + tanI (ro. After four iterations.92) Thus.88) can be solved iteratively.. Making Compensation Independent of Process and Temperature This section shows how lead compensation can be made process and temperature insensitive.90) and 9m7 C . the unitygain frequency is proportional to the transconductance of the input transistor of the first stage.71) here. In other words.Rc ) (5. and in particular 1/9m7. a O.0° (5. Regardless of this degradation. from O.
96) II Squaring and simplifying.1 (5. which consists of a bias stage. . recall that R c is actually realized by 0 . we see that the following condition must be satisfied: 107 I OlJ = (W/Lh (W/L)lJ (5. 5. all that remains is to ensure that Veff16/V efl7 is independent of process and temperature variations since clearly the remaining terms depend only on a geometric relationship. the ratio I o7/IOlJ is set from the current mirror pair 0 6.94) Thus. To see this result. the product Rc 9 m7' which we want to be a constant.93) (5. second stage.95) Therefore. is given by R c9m7 = (W/ Lh Veff7 (W IL)" Veff" (5. the second stage. 6 . 9m7 is given by 9m7 = ~nCox(W/LhVefl7 (5. all' resulting in .97) However. 5. and compensation circuit of the twostage opamp. These two effective gatesource voltages can be made equal by taking = (5. First we must make Va = Vb' which is possible by making V ett l] = V efl7. consider the circuit shown in Fig. The ratio Veffl6/Veff7 can be made constant by deriving V GSI6 from the same biasing circuit used to derive VGS7' Specifically. and therefore we have Rc = Also.07 0" Vbiasof 1 I OlJ = (WIL)6 (W/L).5.2 Feedback and Opamp Compensation 247 It turns out that Rc can be made proportional to 1I9m7 as long as Rc is realized by a transistor in the triode region that has an effective gatesource voltage proportional to that of 0 7 .98) 25 06 300 Fig.9.9 The bias circuit. and the compensation network of the twostage opamp.
we need to satisfy the follow(W/L)6 (WILl. (W/L)" = (W/L). we have the product R c 9m7' given by R 9 C m'   (W/L). 1990]. around the loop consisting of a". we have VGS I J = VGS IS + IDIsR B (5. al" As a result. a . This relationship can be very useful for. we have guaranteed that the drainsource resistance of a transistor in the triode region is inversely matched to the transconductance of a different transistor. we will see that it's quite simple to make all of the transconductances of transistors in a microcircuit match the conductance of a single offchip resistor. substituting (5. from (5.100) 2I D " ~nCox(W IL). we also must have I D IS I D " .95l.98).IDO) into (5.6 (W/L)" (5. we have Ve fll l = Veff7. This stabilization can be achieved by using a circuit approach first proposed in [Steininger. As a result. 5. As a result. it is assumed that (W/L)IO = (W IL) II' This equality results in both sides of the circuit having the same current due to the currentmirror pair 0 10.10. Next. to make Ve ff 13 ing relationship: Ve ff 7 . to a firstorder effect. Indeed. in which transistor transconductances are matched to the conductance of a resistor. First. V e ff l 6 V e ff l 3 V e ff l 2 ~nCox(W IL)" = (WILl" (W ILl" (5.97) and (5. Biasing an Opamp to Have Stobie Transconductonces We have seen that transistor transconductances are perhaps the most important parameters in opamps that must be stabilized. This relationship can be very useful in modem circuit design.102) . using these gatesource relationships and noting that ID l2 = ID l3 . The bias circuit is shown in Fig. we also have Ve ff l . we can write a" v.many other applications as well. and R B.. (WILl" (W/L).s. the transistor transconductances are independent of powersupply voltage as well as process and temperature variations.248 Chapter 5 • Basic Opamp Design and Compensation Thus. Now.2 Finally. and therefore we also have Va = Vb' Since the gates of and 0 ' 6 are connected and their source voltages are the same. This approach results in the possibility of onchip "resistors.101) which is only dependent on geometry and not on processing or temperature variations. = Ve fll 6 .99) Assuming this condition is satisfied. in the next subsection.3 (5." realized by using trioderegion transistors that are accurately ratioed with respect to a single offchip resistor.
the transconductance of Q 13 is determined by geometric ratios only. and recalling that Vett. temperature. = V GS.4>~[: 25 :::114>~[: 25 Fig. V" from (5.105) (5..107) Thus.104) = 10 15 . _ 9m13 [ (W/L)ls / R B (5. process parameters. both sides.2 25 Feedback and Opamp Compensation 249 ::::H"1~~C: :::n.(W/L)13}. we can also write 21 0 13 Iln Cox(W/L)13 Rearranging.106) and recalling that 9ml3 = J2IlnCox(W/L)13loI3 results in the important relationship 2 1.10 A bios circuit that gives very predictable and stable transistor transconductonces. resulting in  V" we can subtract the threshold voltage.103) This equation can also be written as 21 0 13 IlnCox(WIL)13 and since 10 13 (5. or any other parameters with large variability. For the special case of (W/L)IS = 4(W/L)13. 5. we obtain (5. we have simply . independent of powersupply voltages.5.
are used.111) As long as the effective gatesource voltages have not initially been designed to be too large. this is not necessarily the case. A final limitation is that at high temperatures.25 V at room temperature. the effective gatesource voltages also increase. W / L) I x9mlJ ( n 013 (5. if onchip resistors. it is necessary to add a startup circuit that only affects the operation if all the currents are zero at start up.I D. . 14. the ratios of the currents are mainly dependent on geometry. The body effect will modify the equation slightly.108) Note that. We thus have. this corresponds to a 27percent reduction from room temperature of (300 OK) to 100°C (373 OK). this limitation is tolerable in most applications. 9mi = (W IL). and. for all nchannel transistors. this circuit unfortunately can have a second stable state where all the currents are zero. This effect can be made of little consequence by replacing the simple current mirrors with cascade mirrors. . Possible startup circuits will be described in Chapter 6. since (5. not only is 9mlJ stabilized. 14 A typical value for effective g}'!esource voltages might be 0. The major limitation is due to the transistor output impedance. Since the carrier mobility is proportional to T. therefore. but the relationship will still depend primarily on geometry alone.2 V to 0. but all other transconductances are also stabilized since all transistor currents are derived from the same biasing network. thereby limiting signal swings more than 312 is the case at normal temperatures. such as well or diffusion resistors. In addition. the effective gatesource voltages increase by 27 percent to keep the transistor transconductance unchanged. It is stable as long as the loop gain is less than unity. in Chapter 6 we will see that by using wideswing current mirrors.110) It should be noted here that the preceding analysis has ignored many secondorder effects such as the transistor output impedance and the body effect. To guarantee this condition doesn't happen. the currents and effective gatesource voltages increase substantially to offset the mobility degradation and to keep the transconductances stable. which is the case when (W/L)IS/(W/L)13> 1. The bias circuit just presented is an example of a circuit having positive feedback. However. Also. this effect will be somewhat offset by their positive temperaturecoefficient dependency.250 Chapter 5 • Basic Opomp Design and Compensation I 9m13 = Rs (5. Although the use of cascade mirrors appears at first glance to require large power supplies..109) and for all pchannel transistors 9mi = (5. Thus.
+ g 5 10 12 300 500 7 7 150 7 Q3 Q4 '.' Commonsource 'v' Output buffer 7 second stage Fig. The size of 0 16 is selected for proper lead compensation.1 and 5.6um NMOS w=150um 1=1.6um 8k PMOS w=300um 1=1. 5.lIC 25 Vi.6um PMOS w=300um 1=1.11 All transistor lengths equal 1.3 SPICE SIMULATION EXAMPLES In this section. 5.2.6um NMOS w=25um 1=1.6um NMOS w=25um 1=1.' 7 Vss Q7 Q9 '.6um NMOS w=100um 1=1. :1I.6um NMOS w=25um 1=1.6um PMOS w=300um 1=1.5 PMOS w=25um 1=1..5 de 2.6um de 0 I I 4 5 6 7 I 8 8 7 7 I I 7 7 7 7 I I I 7 7 vin .2 is shown in Fig. SPICE simulation results are presented for Examples 5.5.' Bias circuitry Differentialinput first stage '. NETLIST: vdd vss mlO mIl ml4 ml2 ml5 m13 rb m5 ml m2 m3 m4 I 7 2 3 2 3 4 5 6 8 \0 12 10 12 9 0 0 2 2 3 3 5 5 7 2 9 II 10 10 0 de 2.1 and 5..5.6um NMOS w=150um 1=1.1 and 5. R b is chosen such that 0 5 has a de current of 100 IlA. Simulatians of Examples 5.6 I'm.3 1 SPICE Simulation Examples 251 25 o. 1 300 13 Q. The circuit for Examples 5.11.oj .6um PMOS w=25um 1=1..2.
' 10' 10$ Frequency [Hl] 10 6 .1 because the values for the transistor output impedances in the example are rough estimations.6um w=500um 1=1.Icmos_models" library .12. 5. G. where we see that the de gain is 67 dB (i.6um w=300um 1=1.1k lOOMeg . 2240 VN). 5. The unitygain frequency is shown to be 25 MHz. Gray and R. The gain of the opamp is different from the handcalculation result from Example 5.ac dec 20 0.options brief .op .252 Chapter 5 • Basic Opamp Design and Compensation 20 .. 1.. John Wiley & Sons. vin+ m6 mS m7 m9 cc ml6 11 13 I 13 14 15 15 0 2 13 12 12 13 3 1 14 7 7 12 I 7 7 7 7 de 0 ac PMOS NMOS NMOS NMOS 5pF . R.6um w=100um 1=1. Meyer. Analysis and Design of Analog Integrated Circuits.12 A frequency plot of the twostage opamp. New York.NMOS 1 w=300um 1=1. K.5.4 REFERENCES P.option post .end The frequency plot result is shown in Fig. . 1993. Operational Amplifiers. 1975.6um . John Wiley & Sons..' Fig. which corresponds closely to the handcalculated result since this calculation does not depend on poorly modelled variables.e.print vdb(l4) . 3rd ed.. Roberge.lib ".6um w=500um 1=1. New York.
0 X 10 4 • pchannel MOS transistors: pF/~m /lpC ox = 30 /lA/y2 = 0.(O) = 12. C. S. 2631. J. what is the output voltage range of the opamp of Fig. Vol.0 x 10 pF//lm 3 Cox = 1. and C c = 10 pF. all transistor lengths are 1.. a.2 5.5 PROBLEMS Unless otherwise slated. Find the slew rate. Sedra and K. No. May 1990.pF//lm ' Cox = 1. 5. 5. 6. all transistor lengths are 1.6 urn .p) = 2.3dB frequency of the first stage. c.9 x 103 pF/(/lmf 4 C9. 5. Holt. Smith. Rinehart & Winston.5 X 104 pF/(/lm)' 4 Cj. Estimate the inherent inputoffset voltage.2? What is the range of the commonmode input voltage. 3rd ed. Steininger. 1991.pF//lm v. What circuit changes could be made to double the slew rate while keeping w.5. 5. "Understanding WideBand MOS Transistors.3 5.9 X 10.p) = CgdIOverl. 5.8 yl/2 rd. 5.(O) = 8. but let C c = 4 pF. Estimate the . 5." IEEE Circuits and Devices.2 to maintain zero systematic offset voltage? Assume 0.000 L(/lm)/Io(mA)in active region C J = 2. Ignoring the body effect.3.2.4 X 104 pF/(/lm)2 4 C jaw = 2.4 Repeat Example 5. C j = 4. and C c unchanged? How should the sizes of 0 6 and 0.5 X 10.8 Y Y = 0.0 X 10.000 L(/lm)/Io(mA) in active region.9 Y Y = 0. Estimate the unitygain frequency of the opamp. M. and los = 100 /lA. For the twostage opamp of Fig.pF/(/lm)' CgS(OverlaPl = CgdfOVerlap) = 2. New York. assume the following: • nchannel MOS transistors: /lnCox = 92 /lAN' V'n = 0.4 are both SO um wide. b.. change in Problem 5.5 Problems 253 A.5 . and 0 4 of the twostage opamp of Fig.1 Assume that los = 100 /lA.w = 2.5 y I/ 2 rd.loverl. pp. Microelectronic Circuits.2 urn . assuming ±5 Y power supplies are used" Assume los = 100 /lA.3.
. 5. Happ(s). other realaxis poles. and zeros such that Aoxn(1 +~) (OZI Hrs) = .. but take the body effect into account and find approximate answers. therefore.<l Vout Fig.. 160 MHz......8 Consider a system response.I I. Explain why this circuit would then oscillate for large positive output values..45)? A twostage opamp has a compensation capacitor connected between the input and the output of the second stage. and 180 MHz. His}. 10 kQ Vin o"vl\r.. with one dominant pole.9 5.=50kQ R.. PS. Using iteration. where 0 16 is placed on the output side of Cc (rather than where it is shown).l0 .. when H(s) is approximated by Happ(s) such that the phase of the two systems are approximately equal at (0.. find the frequency where the phase shift is _135 0 and.6 5. 5. Ao (I +~XI +~) W 1 ffi p eq Show that.10 An opamp has its first pole at 3 kHz and has highfrequency poles at 130 MHz.2. How does this compare to the estimate given by equation (5. What is the required size of the compensation capacitor if the phase margin is to be 55 0 forthe feedback configuration shown in Fig.1O? R.254 Chapter 5 • Basic Opamp Design and Campensatian 5. (Oeq should be equal to _I = (()eq I..."  ( I + ~)n(1 + ~) cup 1 (I)PI Also consider another approximating function. Assume the input transistors of the first stage have a transconductance of 0._I wpi (()zi 5.. It has an equivalent secondpole frequency of 60 MHz. find the equivalent time constant that models the highfrequency poles..i >. given by Happ(s) = "'.7 Consider the opamp shown in Fig.5...775 mAN and the gain of the output buffer is exactly unity.. Repeat Problem 5. P5. of Hts).
Find approximate equations for the resonant frequency and the Q factor of the denominator of the transfer function of the closedloop amplifier.10. in order to obtain lead compensation? An opamp has an openloop transfer function given by H(5) = (I+~XI +~) WI Ao W.71).13 Assume Ao = 104 and w.2 urn .Q I4 having sizes of 10 /lm/1. what is a nearoptimum size for a capacitor to be placed in parallel with R. Find W I and wt so that the phase margin is 80°.e.12 For the result of Problem 5.11 5. 5.14 5. is added such that the frequency of the zero is the same as the resulting openloop unitygain frequency.2 urn and Q I5 having a size of 40 /lm/ 1. Prove that the frequencies of the first and second poles of the amplifier of Fig.2 are still given by (5. For Q I2 .15 Find the transfer function of the closedloop amplifier. assuming a feedback factor p exists.5. wt . An opamp has an openloop transfer function given by A( 5) Ao I = 51.70) and (5.) 5. Design the bias circuit of Fig. 5. wz . 5.((I + 51z) '=+ 51. what is the required size of R? What would the effective gatesource voltage be at 70°C? Confirm your answer using SPICE.5 Problems 255 5.25 V for all transistors. even when lead compensation is used (i. . when R c is included in Fig. A zero. 5.. = 108 radJs.10 to have V'lIt = 0.8).
6. and A. transistors 0.1 and is often called the "wideswing cascode current mirror" [Sooch. The basic idea of this current mirror is to bias the drainsource voltages of transis tors 0. and 0. circuits exist that do not limit the signal swings as much as the current mirrors discussed in Chapter 3. the design of two modern opamps having singleended outputs is presented. if the sizes shown in Fig. Fortunately. the basics of "currentfeedback oparnps" are presented. 6. a discussion of advanced current mirrors is presented first. alone would operate if its gate were coo 256 . Specifically. will be biased right at the edge of the triode region. which may not be tolerated in certain applications. While this twostage opamp has been used in many commercial integrated circuits.CHAPTER Advanced Current Mirrors and Opamps The classical twostage opamp was discussed in Chapter 5. the use of conventional cascade current mir rors limits the signal swings available. note that the transistor pair 0" 0 4 acts like a single diodeconnected transistor in creating the gatesource voltage for 0. Unfortunately. to be close to the minimum possible without them going into the triode region. Babanezhad. design principles are discussed for realizing opamps having fully differential outputs. and assuming the classical squarelaw equations for long channellength devices are valid.. Finally. 1985. 1987]. recently a number of alternate opamp designs have been gaining in popularity and are the topic of this chapter..1 are used. 6. it becomes more difficult to achieve reasonable opamp gains due to transistor outputimpedance degradation caused by shortchannel effects. One such circuit is shown in Fig. Following the currentmirror section. Since many of these opamps make use of more advanced current mirrors. designers are often forced to use cascade current mirrors. These two transistors operate very similarly to how Q.1 ADVANCED CURRENT MIRRORS WideSwing Current Mirrors As newer technologies with shorter channel lengths are used. As a result. where we see that these opamps can have large gainbandwidth products without the need for adjusting the compensation capacitance. Before seeing how these bias voltages are created. Next..
(6. V OS2 = V OS3 = VGSVGSI = VGs(nVett+Vtn) = v. 6.5) This drainsource voltage puts both O 2 and 0 3 right at the edge of the triode region. We therefore have V elt = V ett2 = VetO = 2~2 Iln Co.. This matching makes the output current. (6. Thus. we have V etfs = (n + I)Vett (6. 0 4 has little effect on the circuit's operation.1) Furthermore.1 The wideswing cascode current mirror. I . in which case the current mirror operates correctly as long as .« (6. Other than this.6.6) A common choice for n might be simply unity. and 0 3 . I bia s typically is set to the nominal or maximum input current. lin.4) Furthermore. The reason for including 0 4 is to lower the drainsource voltage of 0 3 so that it is matched to the drainsource voltage of O 2 . To determine the bias voltages for this circuit. more accurately match the input current.1 Advanced Current Mirrors 257 v. being given by Thus. nected to its source. lin' If 0 4 were not included. = (n + nv. and assume all of the drain currents are equal.lout = lin W/L W/L (n + 1)2 IW/L Fig. let V ett be the effective gatesource voltage of O 2 and 0 3 . since Os has the same drain current but is (n + I)' times smaller.2) Similar reasoning results in the effective gatesource voltages of Ot and O... the minimum allowable output voltage is now V O Ul > V ettt + V ett. lout.(W/L) (6. then the output current would be a little smaller than the input current due to the finite output impedances of 0.
It should be noted that this circuit was analyzed assuming the bias current. Q.5 V.. (6. Specifically.) often has larger voltages across it. it should be mentioned that this current mirror is presently becoming the most popular CMOS current mirror and is therefore very important in many analog .1 V to 0. smaller than the size given in Fig. and Q 3 with slightly larger drainsource voltages than the minimum required (perhaps 0.1 to bias transistors Q.e. an experienced designer would take (W IL). 6. though the drainsource voltage of Q 2 and Q 3 will be larger than necessary except when the maximum [in is applied. As a result. some devices will enter triode and the output impedance will be reduced for larger lin values (say.. but such an effect during transient conditions can often be tolerated. and Q4' which causes their threshold voltages to increase. a few design comments are worth mentioning. This choice of gate lengths helps eliminate detrimental shortchannel effects. one need only ensure that YIn be greater than nV eff for Q 4 to remain in the active regionnot a difficult requirement. A typical size might be twice the minimum allowable channel length. we need VOS4 > Ve ff4 = nV e ff Q 3 is connected to the drain of 0 4. lin' Since. However.258 Chapter 6 • Advanced Current Mirrors and Opamps Vout > 2Veff (6. This increase would also help offset a secondorder effect due to the body effect of Q. I bias . which tends to push Q 2 and QJ more into the triode region. that might otherwise result. Finally. therefore. such as the draintosubstrate leakage currents of Q.7) With a typical value of Veff between 0.15 V larger). and Q4 would be chosen to have longer gate lengths since the output transistor (i. as their gatesource capacitances are the most significant capacitances contributing to highfrequency poles. A final common modification is to choose the lengths of Q 2 and Q 3 just a little larger than the minimum allowable gate length (as the drainsource voltage across them is quite small). and I bias might be scaled to have lower currents while keeping the same current densities and. saturation) region even when the voltage drop across the mirror is as small as 0. Before leaving this circuit. To find VOS4' we note that the gate of resulting in VOS 4 = VGJ . In most applications. Perhaps the more common choice in a wideswing opamp is to let [bias equal the nominal value of lin' With this setting. Minimizing the lengths of Q 2 and Q 3 maximizes the frequency response.4 V to 0. This increase accounts for the fact that practical transistors don't have a sharp transition between the triode and active regions. there is one other requirement that must be met to ensure that all transistors are in the active region. there is some choice as to what I bias value should be chosen. lin may be a varying current level. in general. the same effective gatesource voltages. some voltage swing will be lost.e. during slewrate limiting). equals the input current. the wideswing current mirror can guarantee that all of the transistors are in the active (i. to save on power dissipation. One choice is to set I bias to the largest expected value for lin' Such a choice will ensure that none of the devices exit their active region.V OS J = (V e ff + Yin)  Veff = YIn (6.2 V and 0.9) As a result.8) to guarantee that Q 4 is in the active region. In addition.25 V. the bias branch consisting of Q. but Q.
0 Vbias_p Vcasc _p Small W/L . ::::J~+=II. Transistors 0 8 and 0 9 operate as a diodeconnected transistor at the input side of the mirror. The current for this biasing transistor is actually derived from the bias loop via 0 10 and Oil. The cascode transistors 0 6 and 0 9 have gate voltages derived from diodeconnected 0 14 . Vbiasn ~ Cascade bias ~ Startup circuitry A constanttransconductance bias circuit having wideswing cascode current .2. The pair 0 3 . . L4o ~ Bias loop Fig. The output current comes from 0 1. without greatly restricting signal swings. This circuit is a modification of thecircuit described in Fig 5.6. Similarly. The gate voltages of cascode transistors 0 1 and 0 4 are derived by the diodeconnected transistor Os.10. along with the diodeconnected biasing transistor Os.2 mirrors.1 Advanced Current Mirrors 259 designs besides opamps. 6./ Q. the pchannel wideswing cascode current mirror is realized by 0 609. The next subsection will show how it can be incorporated into the constant 9m bias circuit described in Chapter 5. The complete circuit is shown in Fig.<~jl:. and has both wideswing current mirrors and'a startup circuit} The nchannel wideswing cascode currtnt mirror consists of transistors 0 104. 0 4 acts similarly to a diodeconnected transistor at the input side of the mirror. This modification greatly minimizes most of the detrimentarsecoridoidei"Jl1perrectlons caused by the finiteoutput impedance of the transistors. WideSwing ConstantTransconductance Bias Circuit It is possible to incorporate wideswing current mirrors into the constanttransconductance bias circuit described in Chapter 5. The currentmirror output current is the drain current of 0 6 . which has a bias current derived from the bias loop via 0 12 and Ou.:=.6.
and the circuit will remain in this stable state forever.2. and it is used to increase the output impedance.6. is also shown in Fig. and thereby turning them off so they no longer affect the bias loop. 017 will come on. >1ICO. 0 16 .3. These latter two loops also constitute positive feedback but with very little gain. 6. For example. alB' is replaced by an actual resistor (perhaps realized using a well resistor). which will start up the circuit. Once the loop starts up. A simplified form of this circuit is shown in Fig. Enhanced Outputlmpedence Current Mirrors Another variation on the cascode current mirror is often referred to as the enhanced outputimpedance current mirror. v. it is necessary to include startup circuitry that affects only the biasloop in the case that all currents in the loop are zero. The addition of this amplifier ideally increases the Ilo"t \. 017 will be off. . This circuit is only one example of a startup loop.8jlm technology). To ensure this condition does not happen. Since alB operates as a highimpedance load that is always on. An example of a startup circuit consisting of transistors 0 15. and the two loops used for establishing the bias voltages for the cascode transistors.. . the gates of 0 15 and 0 16 will be pulled high.3 The enhanced outputlmpedonce cur rent mirror.' pulling the gates of 0 15 and 0 ' 6 low. sinking all of the current from ai. 6. it also allows the performance of the realized opamp to be accurately predicted using moderately simple equations prior to realization. and there are many other variations. 0l7' and ai. The basic idea is to use a feedback amplifier to keep the drainsource voltage across O 2 as stable as possible.} Fig.260 Chapter 6 • Advanced Current Mirrars and Opamps The bias loop does have the problem that at startup it is possible for the current to be zero in all transistors. sometimes the pchannel transistor. It is of interest to note that the bias circuit shown consists of four different loopsthe main loop with positive feedback. O2 Voul. These transistors then will inject currents into the bias loop.~. Shown next to each transistor are reasonable WtL dimensions (in urn) of a possible realization that had its operation experimentally verified (it was realized in a O. irrespective of the output voltage. the startup loop that eventually gets disabled. In the event that all currents in the bias loop are zero. 1+ . Because this circuit allowed for accurately predictable transconductances.
q(l +A) (6. It should be mentioned that the technique just described for outputimpedance enhancement is not useful when bipolar transistors are used due to the finite base current of the transistors (see Problem 6.10) In practice. Rout'" 9mtrdstrd. using the results from Chapter 3.6. II) S1't around its unitygain frequency.4 A commonsource amplifier with output impedance enhancement. has a transfer function given by A(s) = A 0 .13) Vbia s CL Fig. This parasitic conductance is a result of collisions between highly energized electrons resulting in electronhole pairs to be generated with the holes escaping to the substrate.= 9m2 ( Rout(s) I IC ) . A(s). The generation of these electronhole pairs is commonly called_. t =_0 A 1+ S1 (6.cUonizatiQ!l. 6.8). Find approximate equations for any additional poles and/or zeros introduced by the gain enhancement circuit that are significant around the unitygain frequency of the commonsource amplifier shown in Fig.4. the output impedance might be limited by a parasmc conductance between the drain of 0t and its substrate due to shortchannel effects.o(S) S L (6.1 Assume an amplifier.1 Advanced Current Mirrars 261 output impedance by a factor equal to one plus the loop gain over that which would occur for a classical cascade current mirror.. . EXAMPLE 6. Assume the gain of the commonsource stage is given by Av(s) Vout(S) I = V. Specifically. 6.12) where Rout is now a function of frequency and given by Rout(s) = 9mtrdstrdS2(l +A(s)) (6.
and therefore.14) 9m'( 1+ A(s)) which can be inserted into (6. we see that there is a lefthandplane zero at a frequency given by (6.17) which is the approximate unitygain frequency of the amplifier. Also. Furthermore.16). the added pole frequency is approximately given by p. = 1 Rou'(s) = =~::.15) and rearranging gives Av(s) = 9m2(A o + S1.:.) +SL1 1 From (6.9ds2 9ml Substituting (6.(l + A(s)) sCL(l + A(s)) + 9ds. but the pole at de is not accurate since we have made use of approximate equations that are valid only near the unitygain frequency of the amplifier.  Ao 1. Thus.15) 9m.) . typically the first term in (6.  ro'z (6. note that the term A o/1. (6.. 9ml C .9m2 (6. the other pole location is a good approximation and it occurs in the lefthalfplane given by (after some rearranging) = +'t~ AO 1 C L R' (6. we have defined (6. A(s).18) dominates. we have Gou'(S) 1.262 Chapter 6 • Advanced Current Mirrors and Opamps Solution Note that at high frequencies..20) .18) Here.12) giving Av(s) = 9m2 sC L + Gou'(S) 9dSl9ds2 SC + L 9ml(l+A(S)) (6.16) C S (A OL+ 9dsl9dSZ1. However. it is not possible to assume that IA(jro)1 » Working with conductances. there are two poles.11) into (6. is a value near the unitygain frequency of the amplifier.19) which is approximately the output impedance of the cascode mirror without enhancement and is quite a large value.
.6.. although these extra opamps can be scaled to have less power dissipation. The feedback amplifier in this case is realized by the commonsource amplifier consisting of 0 3 and its current source I B I . Fig. their drainsource voltages are given by VOS2 = Voss = Veff3 + V" (6. 1979] for singleended input amplifiers and more recently described almost simultaneously in [Bult. In addition. 1990] for differentialinput amplifiers.. the frequency response of the enhancement amplifier shouldn't have a large detrimental effect on the overall frequency response.. will very accurately match Ii. Assuming the output impedance of current source I B I is approximately equal to r dS3' the loop gain will be (9m3rds3)/2. This limitation is especially harmful for modern technologies operating with power supply voltages of +ILQ.1 Advanced Current Mirrors 263 Therefore. and their effects mostly cancel each other out.. The implementation proposed by Sackinger is shown in Fig. and I B I • As a result. Ii" and I B2 operates almost identically to a diodeconnected transistor..5 The Socktnqer implementation of the enhanced outputirnpedcnce current mirror. like the new zero. . O 2 . if the unitygain frequency of the enhancement loop is greater than the unitygain frequency of the opamp.' The Sackinger realization is much simpler than that proposed by Bult. the new pole also occurs around the unitygain frequency ofthe amplifier... and the final ideal output impedance will be given by rout  9m I 9m3 rdsl rdS2 rds3 2 (6.22) rather than the minimum required.5. In a modern fully differential opamp.21) The circuit consisting of 0 4 .6. The enhanced outputimpedance current mirror appears to have been originally proposed in [Hosticka.. Bult proposed that complete opamps be used for each current mirror.. This reduction is a result of O 2 and 05 being biased to have drainsource voltages much larger than the minimum required. this might increase the number of opamps by four. but is used instead to guarantee that all transistor bias voltages are accurately matched to those of the output circuitry consisting of 0 1. 1990] and [Sackinger. Iou. but has a major limitation in that the signal swing is significantly reduced.. t . 0 3 . 6. OS' 0 6 . Specifically..t L Q. which would be equal to Vett 2.
1994]. is biased on the edge of the triode region and the minimum output voltage is given by (6. except for OJ and 0 7 . we find that the gate voltage of 0. the level shifter is the diodeconnected transistor.3 V or lower. except for 0 3 and 0 7 .25) (6. In the next subsection. all transistors have the same effective gatesource voltages. equals VGJ = 2V ett + Vln and the drainsource voltage of 0. biased with current I bias ' The circuitry at the input basically acts as a diodeconnected transistor while ensuring that all bias voltages are matched to the output circuitry so that lout accurately matches lin' Shown next to each transistor is a reasonable width in urn. 1990] for use in currentmode continuoustime filters and was then used in the design of widesignalswing opamps [Coban. As a result. an alternative realization is described that combines the wideswing current mirror with the enhanced outputimpedance circuit. as shown in Fig.264 Chapter 6 • Advanced Current Mirrars and Opamps 3.23) all transistors are biased with nearly the same current density. 1994. Martin. 6. lin . Current source 7I bias is typically set to the nominal or maximum input current.24) Therefore. Thus. except that diodeconnected transistors used as level shifters have been added in front of the commonsource enhancement amplifiers. 1990]. At the output side. V ett. which have gatesource voltages of 2V ett because they are biased at four times the current density.26) Fig. = V S 4 = VGJV G S4 = (2Vett+Vln)(Vett+Vln) = Vett (6.6. 0.6 A wideswing current mirror with enhanced output impedance. It is very similar to the enhanced outputimpedance current mirrors of [Sackinger.6. Note that for the case in which I bias = I in /7 (6. 0 4. is given by V os. WideSwing Current Mirror with Enhanced Output Impedance This current mirror was originally described in [Gatti.
6. assuming I bias is set to oneseventh the nominal or maximum input current value. This is because during largesignal transients.1 Advanced Current Mirrors 265 With the shown values for the W/L ratios.6.6.7.6 has now been separated into two transistors. the outputs of the enhancement loops can slew to voltages very different from those required after settling..2. 6. The first fact is that sometimes it may be necessary to add local compensation capacitors to the enhancement loops to prevent ringing during transients. = lin Vcescn oj 70 Fig_ 6. and Qs. This variation obtains the bias voltage of the cascode transistor of the input diodeconnected branch from the biasgeneration circuitry of Fig. the power dissipation would be almost doubled over that of a classical cascade current mirror. when outputimpedance enhancement is desired. 6. Finally. and it can take a while for the outputs to 4Ibias I lout I .6. It is predicted that this current mirror will become more important as the newer technologies force designers to use smaller powersupply voltages.7. as the additional poles introduced by the enhancement circuitry would then be at lower frequencies. There are a couple of facts that designers shoukfbe aware of when they use outputimpedance enhancement. but with wideswing mirrors. This circuit suffers slightly with regard to largesignal de matching. it has been found through simulation that the modified circuit of Fig. 6. 6.7 is less prone to instability than the circuit of Fig. Notice also that Q. lin' However. Then. of Fig. Also. which limit voltage swings. one simply includes the appropriate enhancement amplifiers and the only change required to the original amplifier is to connect the gates of the output cascode mirrors of the appropriate current mirrors to the enhancement amplifiers rather than the biasgeneration circuit. Q. 6. in Fig. . This change allows one to design an opamp without the outputimpedance enhancement. The second fact is that the inclusion of outputimpedance enhancement can substantially slow down the settling times for largesignal transients. but has less power dissipation and area than the circuit of Fig. albeit at the expense of speed.7 A modified wideswing current mirror with enhanced output impedance. the shortchannel effects of newer technologies make the use of current mirrors with enhanced output impedance more desirable. 6. it is possible to bias the enhancement circuitry at lower densities and thereby save on power dissipation. A slightly modified version of the wideswing enhanced outputimpedance mirror is shown in Fig.
These improvements are obtained by having only a single highimpedance node at the output of an opamp that drives only capacitive loads. it is often desirable to describe a circuit without showing which particular current mirror is used. that can be used in a particular circuit application. Ibl Example of a simple current mirror. 6. it should be mentioned that for illustrative purposes. Thus. 6. it is not necessary to use a voltage buffer to obtain a low output impedance for the opamp. By having all internal nodes of relatively low impedance. Whether this is worth the substantial increase in gain (perhaps as much as 30 dB or so) depends on the individual application.8(b).266 Chapter 6 • Advanced Current Mirrors and Opamps 1:K (8) (b) Fig. 6. 1: K.8(a) might be realized by the simple current mirror shown in Fig. The admittance seen at all other nodes in these opamps is on the order of a transistor's transconductance.2 FOLDEDCASCODE OPAMP Many modem integrated CMOS opamps are designed to drive only capacitive loads. It should also be mentioned that these low node impedances result in reduced voltage signals at all nodes other than the output node. each having various advantages and disadvantages. which is the lowimpedance side (with an impedance typically equal to 119m)' The arrow also designates the direction of current flow on the input side. however. Finally. and thus they have relatively low impedance. 6. represents the current gain of the mirror. The arrow is on the input side of the mirror.8 101 A symbol representing a current mirror. However. For example. it is possible to realize opamps having higher speeds and larger signal swings than those that must also drive resistive loads. the current signals in the various transis . some circuits in this book will be shown with a particular current mirror (such as the wideswing mirror) to realize a circuit architecture. With such capacitiveonly loads. In these cases. the current mirror shown in Fig. As a result. A typical settlingtime difference might be around a 50percent increase. return to the necessary voltages. we make use of the currentmirror symbol shown in Fig.8(a). the speed of the opamp is maximized. The ratio. from an architectural perspective. it should be kept in mind that similar circuits using almost any of the current mirrors just described (or described elsewhere) are possible. CurrentMirror Symbol It should now be clear that there are a number of different currentmirror circuits. 6.
6. discussed previously. its gain can be quite reasonable.000.. the opamp usually becomes more stable but also slower. on the order of 700 to 3. as shown in Fig. and O 2 are nchannel transistors in Fig. Therefore. . The design shown is a differentialinput singleended output design. as the load capacitance gets larger. the differentialpair transistors consisting of 0. Q2 v. Because of their reduced voltage signals but large current signals. the ratio of the output current to the input voltage). One of the most important parameters of these modern opamps is their transconductance value (i. An example of an opamp with a highoutput impedance is the foldedcascode oparnp. or Operational Transconductance Amplifiers (OTAs). thereby maximizing the de gain of the opamp.9. Note that all current mirrors in the circuit are wideswing cascade current mirrors. The use of these mirrors results in highoutput impedance for the mirrors (compared to simple current mirrors). these types of opamps are sometimes referred to as currentmode opamps. QIO L Fig.e.: + Ibias2 le Q. 6. whereas the cascade transistors consisting of 0 5 and 0 6 are pchannel transistors. Such a high gain occurs because the gain is determined by the product Q5 Q6 <>j Yin Q. For example. It should be mentioned that even though a foldedcascode amplifier is basically a single gain stage.9. 1.' With these opamps. some designers refer to these modem opamps as transconductance opamps.9 A foldedcoscode opamp.2 FoldedCcscode Opamp 267 tors can be quite large.6. we shall see that the compensation is usually achieved by the load capacitance. Thus.6. The basic idea of the foldedcascode opamp is to apply cascode transistors to the input differential pair but using transistors opposite in type from those used in the input stage. This arrangement of oppositetype transistors allows the output of this single gainstage amplifier to be taken at the same biasvoltage levels as the input signals.
as will be discussed in Example 6. a" a" is applied to the load capacitance. V8 I and V82 would be connected to Vcascp and Vcascn. Since the bias current of one of the cascode tran sistors is derived by a current subtraction. Thus the inclusion of 0 12 and OIJ allows the opamp to recover more quickly following a slewrate condition. It should be mentioned that a simplified bias network is shown so as not to complicate matters unnecessarily when the intent is to show the basic architecture. This drain current is established by 1b. 6. and realizes dominantpole compensation.as. 0 8 . If lead compensation is desired. In applications where the load capacitance is very small.2. such as when the compensation capacitance is mostly supplied by the load capacitance. . a". This approach eliminates inaccuracies due to secondorder effects caused by transistors having nonequal widths. it is assumed that the differential output current from the drains of the differential pair. it is often possible to include a resistor in series with the load capacitance). 6. a resistor can be placed in series with C L . C L . SmallSignal Analysis In a smallsignal analysis of the foldedcascode amplifier. any current mirrors used in deriving these currents should be composed of transistors realized as parallel combinations of unitsize transistors. the smallsignal current from passes directly a. and commonmode feedback circuitry would be added.e. it is more often possible than many designers realize (i. it is necessary to add additional compensation capacitance in parallel with the load to guarantee stability. and hence the a. for it to be accurately established..as.as2/2. to (W/L)". and 0 10 . While lead compensation may not be possible in some applications. In addition. of Fig. and the output impedance is quite high due to the use of cascode techniques. C L . be derived from a singlebias network. minus 1b. as is discussed in a later section in this chapter. or a. more importantly. The bias current of one of the pchannel cascode transistors. these transistors prevent the drain voltages of a I and O 2 from having large transients where they change from their smallsignal voltages to voltages very close to the negative powersupply voltage.2.268 Chapter 6 • Advanced Current Mirrars and Opamps of the input transconductance and the output impedance. In practical realizations. and 1b. or 0 6 .asl might be replaced by the constanttransconductance bias network of Fig.. An important addition of the foldedcascode opamp shown is the inclusion of two extra transistors. Specifically. it is necessary that both 1b.2 to maximize the output voltage signal swing.as. One is to increase the slewrate performance of the opamp. In this case.as2/2.respectively. The shown differentialtosingleended conversion is realized by the wideswing current mirror composed of 0 7. transistors in the outputsumming current mirror as well. a" and 1b. during times of slewrate limiting. an and 0l3' These two transistors serve two purposes. However. and the ratio of (WILl" or (W/L). In a differentialoutput design. The compensation is realized by the load capacitor. these might be replaced by two wideswing cascade current sinks. The bias currents for the input differentialpair transistors are equal to 1b. is equal to the drain current of a.
and the output impedance of the opamp (i. for large load capacitances.6. the load capacitance dominates. when an nchannel transistor current mirror is used. on the order of gmr~s/2 or greater if outputimpedance enhancement is used.. the impedance of any additional network added for stability. Note that this approach also maximizes the de gain (i.) since not only does it maximize 9m\' but it also maximizes rout by resulting in all transistors connected to the output node being biased at lower current levels (for a given total power dissipation). assuming the load capacitance is large enough so that the unitygain frequency is much less than the limit imposed by the second poles.28) where r0" is the output impedance of the opamp. This impedance is quite high.(s) = gm.. a polezero doublet occurs at frequencies quite a bit greater than the opamp unitygain frequency and can usually be ignored.27) Here.(S) V. gmt r0". while the current from 0. when the compensation is realized by the output capacitance only. This impedance consists of the parallel combination of the output load capacitance. and we can ignore the unity term in the denominator and thus ~ave Ay = sC gmt gmt (6. Thus. =  CL (6.ZL(s) (6. Hence. This is based on the assumption (hat 9 m 5 and 9m6 are much larger than 9dS3 and 9dS4" .. the bias currents of the cascode transistors cannot be well established since they 2.e. ignoring highfrequency poles and zero.29) L from which the unitygain frequency of the opamp is found to be W. The transconductance of the input transistors is maximized by using wide n.2 FoldedCoscode Opomp 269 from the source to the drain of 0 6 and thus C L . ). we have Ay  _ 9ml roul I + srO"C L (6. A practical upper limit on the ratio of the bias currents of the input transistors to the currents of the cascode transistors might be around four or so.30) Therefore. If too high a ratio is used. maximizing the transconductance of the input transistors maximizes the bandwidth. For midband and high frequencies. the approximate smallsignal transfer function for the foldedcascode opamp is given by Ay = Vo.channel devices and ensuring that the input transistor pair's bias current is substantially larger than the bias current of the cascade transistors and current mirror. goes indirectly through 0 5 and the current mirror consisting of 0 7 to 0 102 Although these two paths have slightly different transfer functions due to the poles caused by the current mirror..e. looking into the drains of 0 6 and 0. gm t is the transconductance of each of the transistors in the input differential pair and ZL(s) is the impedance to ground seen at the output node.
This is true only at high frequencies. and out of the load capacitance. are turned off during normal operation and have almost no effect on the opamp.31) where the approximate term is valid at mid and high frequencies. As a consequence. .2 times the unitygain frequency.270 Chapter 6 • Advanced Current Mirrors and Opamps  + ''rout R c + l/sC L I (6. The second poles of this opamp are primarily due to the time constants introduced by the impedance and parasitic capacitances at the sources of the pchannel cascode transistors. they substantially improve the operation during times of slewrate limiting [Law. a. 1983]. However. all of the bias current of 0 4 will be directed through the cascode transistor through the n channel current mirror. minimizing junction areas and peripheries at these two nodes is important. the output voltage will decrease linearly with a slewrate given by a" 3. The impedances at these nodes is one over the transconductances of the cascode transistors. Here we see that. these impedances can be reduced by making the currents in the pchannel cascode transistors around the same level as the bias currents of the input transistors. a 12 and 0 13." Since pchannel transistors are used here. This is the case of interest here. To appreciate their benefit. Slew Rate The diodeconnected transistors. Since O 2 is off. Thus. Assume there is a large differential input voltage that causes a. The parasitic capacitance at the sources of the cascode transistors is primarily due to the gatesource capacitances of the cascode transistors as well as the draintobulk and draintogate capacitances of the input transistors and the current source transistors OJ and 0 4 . these impedances are typically substantially greater than the source impedances of most nchannel transistors in the signal path. to be turned on hard and O 2 to be turned off. Therefore. Rc can be chosen to place a zero at 1. wherethe output impedance of the amplifieris small due to the load and/or compensation capacitance. when highfrequency operation is important. possibly biased at lower currents. and 0 6 . as in Chapter 5. the impedance looking into the source of 0 6 is given by R S6 = 1 19 m 6 + RL/(Qm6rds6)' where R L is the resistance seen looking out the drain of Q(. At low frequencies. consider first what happens during times of slewrate limiting when they are not present..
This additional slewing time greatly increases the distortion and also increases the transient times during slewrate limiting (which occurs often for opamps used in switchedcapacitor applications).6. The maximum transistor width should be 300 urn and channel lengths of 1.32) Also. This increased bias current results in a larger maximum current available for charging or discharging the load capacitance. 6. where a large differential input causes a 1 to be fully on while O 2 is off. causing Ib. set the bias current of all to be 1I30th that of 0 3 (or 0 4) such that its current can be ignored in the power dissipation calculation. the current in a 11 increases. 3 . When the opamp is coming out of slewrate limiting.2 Find reasonable transistor sizes for the foldedcascode opamp shown in Fig. To see this increase in bias current. In summary. Their main purpose is to clamp the drain voltages of 0 1 or don't change as much during slewrate limiting. A second.s2 to decrease until it is equal to 10 3 .9 to satisfy the following design parameters.s2 will go into the triode region. In this case. As a result.5 V power supplies are used and limit the power dissipation of the opamp to 2 mW. Next.'52' Note that the current in 0 4 also increases since it is equal to the current in 0 3. but the maximum available current for charging or discharging the load capacitance is also greater during times of slewrate limiting. 0 12 and 0 . the diodeconnected transistor 0]2 conducts with the current through 0]2 coming from the diodeconnected transistor all' Thus. more subtle effect dynamically increases the bias currents of both 0 3 and 0 4 during times of slewrate limiting. not only are the voltage excursions less. What would be a reasonable size for a compensation resistor in series with C L . consider a case similar to the one just described. EXAMPLE 6. causing the currents in bias transistors QJ and Q 4 to also increase. Also find the unitygain frequency and slew rate.. Set the ratio of the current in the input transistors to that of the cascode transistors to be 4:1. This increase in bias current of 0 4 results in an increase of the maximum current available for discharging C L . the drain voltage of a I approaches that of the negative powersupply voltage. are so they included.2 FoldedCoscodeOpamp 271 SR = 10 4 CL (6. since all of Ib"S2 is being diverted througb 01' and since this current is usually designed to be greater than 10J' both 0 1 and the current source Ib'. both without and with the clamp transistors. if lead compensation were desired? • • Assume ±2. Also. until the sum of the currents of 0 12 and 0 3 are equal to the bias current Ib. a.6 urn should be used in all transistors. consider the case where the diodeconnected transistors. • . the drain voltage of 0 1 must slew back to a voltage close to the positive power supply before the opamp operates in its linear region again.
06 08 09 0 10 60/1. whose widths should be set to the maximum value of 300 urn. we let all transistor channel lengths be 1. This choice allows us to immediately determine the sizes of most transistors using (L WJ i = fljC o x V~ffj 210.6 20/1.6 10/1. is equal to 10 3 + 10 4 .:=10 (6. which is equal to 2(Iol + 10 6 ) . we have (6. assume the load capacitance is given by C L = 10 pF. Now.34) This bias current for Is implies that 10 3 = 10 4 = 51 0 5 = 200 ilA. we have Is = los = 10 6 = I tota. Also.35) and then round to the closest multiple of 10 in transistor widths.6 a" 013 all 10/1. The width of Q II was determined from the requirement that lOll = 10 3/30 = 6. Defining Is " 10 5 = 10 6 and noting that we are asked to make 10 1 = 410 6 . 01 a. Finally. The widths of Q 12 and Q l3 were somewhat arbitrarily chosen to equal the width of QIl' Note that.6 a.33) Since the power dissipation is specified to be 2 mW.25 V except for the input transistors.6 ilA.  (6.6 10/1.6 300/1. and that ~nCox = 3~pCox = 96 ilA/V'. When the widths found were larger than 300 um .1 lists reasonable values for the resulting dimensions of all transistors. 6.6 300/1.6 300/1.6 urn. as O2 300/1. I tota" excluding the current in the bias network. keeping in mind that if a larger transistor is to be matched to a smaller one. and 10 1 = 10 2 = 410 5 = 160 u A.6 20/1.272 Chapter 6 • Advanced Current Mirrors and Opamps • • All transistors shonld have effective gatesource voltages of around 0. as requested. the larger transistor should be built as a parallel combination of smaller transistors.1 The Iransislar dimensians (in I'm) of theopamp of Fig.6 20/1. 0.6 60/1.6 .6 20/1. they were limited to 300 um . The transconductance of the input transistors Table 6. Solution The total current in the opamp. = . Table 6. the widths of the input transistors were set to a value of 300 urn to maximize their transconductance.9. Note that the larger widths are exactly divisible by the smaller widths of a transistor of the same type and thus allows larger transistors to be realized as a parallel combination of smaller transistors. round all transistor widths to the closest multiple of 10 um.
39) When the clamp transistors are included.6.4xlO8 radls => It = 38 MHz CL (6.38) Rc = =.= 2.10.= . R c . By using good current mirrors having high .36) The unitygain frequency of the opamp is given by Wt gml = .aS2 But (6. which is substantially larger than the slew current available without the clamp transistors.41) and (6.37) A reasonable size for the lead resistor.29 m l The slew rate without the clamp transistors is given by SR = 04 = 20 V/~s CL 1 (6..40) (6.2C L wt 1.= 347 n 1.43) which implies that the value of 1011 during slewrate limiting equals 10.44) More importantly.3 CURRENTMIRROR OPAMP Another popular opamp often used when driving onchip capacitiveonly loads is shown in simplified form in Fig. the time it takes to recover from slewrate limiting will be substantially decreased. 6.40) and solving for 10 11 gives 1 Oil  (6.42) _ Ib. we have 1012 + 103 = Ib.42) into (6. This larger bias current will give a slewrate value of SR = 04 = 32 V/~s CL 1 (6.(W/L)1 = 2.a'2 + 6.32 rnA.6 ~A + 1012 Substituting (6.53 ~A and 10J = 104 = 301 0 11 = 0.6 ~A 31 (6. during slewrate limiting.41) and 1011 = 6. 6.3 CurrentMirror Opomp 273 is given by gml = J2IoI~nCo. in series with C L .4 mAN (6. It is immediately seen that all nodes are low impedance except for the output node. is given by I I (6.
Using (6.n(s) = K9mtZL(S) = Kgmtrout 1 + sroutC L = Kg mt sC L (6. a reasonable overall gain can be achieved. we can solve for the unitygain frequency. .. we have Av = Vout(S) V..10 A simplified currentmirror opamp.. The overall transfer function of this opamp will closely approximate a singlepole operation...6. resulting in ~t<l Vout Ib 10 14 Fig. 6.11. output impedance._0 YOU! 1:K Ib Fig. In a similar analysis to that given for the foldedcascode opamp.45).45) The K factor is the current gain from the input transistors to the output sides of the current mirrors connected to the output node.11 = KIt = KIb/2 A currentmirror opamp with wideswing cascode current mirrors. A more detailed example of a currentmirror opamp is shown in Fig.6.274 Chapter 6 • Advanced Current Mirrors and Opamps 1:K .
48) Obviously.47) into (6. The slew rate of the currentmirror opamp is found by assuming there is a very large input voltage. 6. C ox (W/L) .). (6..49) For a given total power dissipation. . If K is increased too much. and if it is very important that speed is maximized.. the total current available to charge or discharge C L is Kl b . all of the bias current of the first stage will be diverted through either Q 1 or Q2' This current will be amplified by the current gain from the input stage to the output stage. J3+K CL (6.Cox(WIL) .3 CurrentMirror Opamp 275 = KJ2I D d.6. Increasing K increases the capacitances of these nodes while also increasing the equi valent resistances. this slew rate is maximized by choosing a large K value. and Q9' secondly. the oparnp's transconductance is larger (i.I. for a given total power dissipation. CL (6. and therefore. the total current. the widths of transistors at the input sides of current mirrors will be smaller. This result gives a currentmirror opamp superior slew rates when compared to a foldedcascade 4. during slewrate limiting.I. for larger values of K." As a result.47) is known for a given powersupply voltage. Thus. (i. Both of these effects cause the transconductances of transistors at the input side of current mirrors to be smaller.46) If the power dissipation is specified. and the drains of Q. From experience it has been found that a reasonable compromise for a generalpurpose opamp might be to let K = 2. we obtain tota') K 2(I + K J. K might be taken as small as one. with K = 4 and during slewrate limiting. l/gm) will be larger. the important nodes for determining the nondominant poles are the drain of Q l' primarily. I tota' = (3 + K)I D . In the circuit shown in Fig.Cox(WIL)] CL (6. In the case where the load capacitance is small. The use of large K values also maximizes the gain for I tota. an increase in C L will be required to keep rot below the frequency of the equivalent second''pole to maintain stability. This simple result assumes the unitygain frequency is limited by the load capacitance rather than any highfrequency poles caused by the time constants of the internal nodes. In this case. the equivalent second pole moves to lower frequencies.e.11. 3 = K J2Itota'J. K). For example. the equivalent second pole will limit the unitygain frequency of the opamp. and therefore the impedances (in this case. Kg m . The slew rate is therefore given by SR =  xr. Substituting (6. Also. Increasing K implies that the currents at the input sides ofthe current mirrors are smaller. fixed since rout is roughly independent of K for large K. 4/5 of the total bias current of the opamp will be available for charging or discharging C L . the unitygain frequency is also larger.46).l. A practical upper limit on K might be around five. Thus.e. increasing K decreases the bandwidth when the equivalent second poles dominate.
assuming the equivalent second pole does not dominate. The bias currents of transistors in the output stage are twice that of the input stage. except those in the output stage.6 11m and transistor widths as given in Table 6. 6.6 60/1.6 60/1. As seen in the chapter on noise.6 60/1. a smaller transconductance results in larger thermal noise when the noise is referred back to the input of the opamp.1 0" 30/1. Estimate the equivalent second pole. The transconductance of the input transistors is (6.6 .6 120/1. the bias currents of all transistors..11 has all transistor lengths equal to 1. which is 160 !lA. Find the slew rate and the unitygain frequency.2 The Iransislar sizes (in ~m) lar the apamp used in Example 6. IlnCox = 31lpCox = 96 IlA/V .2. In summary.51) Table 6. there are no problems with large voltage transients during slewrate limiting for the current mirror opamp. the total power dissipation is specified to be 2 mW (ignoring the power dissipation of the bias network. even when the clamp transistors have been included in the foldedcascade opamp.92 fF/llm2 Would it be necessary to increase C L if a 75° phase margin were required without using lead compensation? What if lead compensation were used? Solution Since the total bias current is given by (3 + K)l b / 2. Notice that 2 K = 2.5 V power supplies are used. due primarily to the larger bandwidth and slew rate.6 60/1. the currentmirror opamp is usually preferred over a foldedcascode opamp. However. we have I _ 21'o'a' _ 2P".6 60/1.. EXAMPLE 6.3. which would normally be small). are 80 IlA .6 09 07 08 0'0 0" 0 12 60/1.3 Assume the currentmirror opamp shown in Fig. Also.6 120/1.50) Thus.6 300/1. 300/1. and ±2.6 01.6 60/1.IS V b  (3 + K)  (3 + K) = 160 IlA (6. assuming Cox = 1. Assume C L = 10 pF.6 60/1. it will suffer from larger thermal noise when compared to a foldedcascade amplifier because its input transistors are biased at a lower proportion of the total bias current and therefore have a smaller transconductance.6 30/1.276 Chapter 6 • Advanced Current Mirrars and Opamps opamp.
. The unitygain frequency is now given by OJ. = 119m" and = 1. CL = 32 V/~s (6.56) With these values of impedance. the junction capacitances will be ignored to simplify matters. Here. The other important time constant comes from the parasitic capacitors at the drain of 0 9 . The dominant node almost certainly will occur at the drain of I' The impedance at this node is given by a R. = 2.59) resulting in = 0.369 pF.52) This result should be compared to the 38 MHz unitygain frequency of the 2 mW foldedcascade opamp of the previous example. = 54 MHz CL (6.4xH) rad/s => I.86 kG (6. the time to be R.4 rnA/V.85 ns. K9ml 8 = . = 0.29 kG.55) resulting in (6.58) (6. Continuing.60) '3 .C. (6. We therefore have tances of a. we have a. and this amount can be determined using simulation.51 ns.54) In addition. showing that currentmirror opamps are superior when driving large capacitive loads.53) which compares favorably to 20 V /~s for the foldedcascade opamp without the clamp transistors (although it equals the value of 32 V /~s for the foldedcascade opamp with the clamp transistors).29 kG (6. the time constant for this node is given by (6.57) In a similar manner. the slew rate is given by SR =  «r. and r = constant for the drain of R.= 3. hence.3 CurrentMirror Opomp 277 The transconductance of the opamp will be K times this or 3.6. In reality. = 0. R. = 119m3 = 2. When estimating the equivalent second pole. we can calculate the impedances and. C. the capacitance will be primarily due to the gatesource capaciand 0 8 . The time constant of the equivalent second pole can now be estimated to be gi ven by (6. the draintobulk capacitances of the input transistors could contribute a significant factor.
If lead compensation is to be used. 6.5 MHz.27 times the equivalent second pole from Table 5..64) . This near equivalence helps to minimize harmful effects caused by the polezero doublet introduced at high frequencies (i.7 pF. This unitygain frequency can be realized by increasing C L to lO pF times 54 MHz/42.61) 't 2eq If lead compensation is not used and a 75 0 phase margin is required. the unitygain frequency increases by about 20 percent to 51 MHz.4 LINEAR SETTLING TIME REVISITED We saw in Chapter 5 that the time constant for linear settling time was equal to the inverse of ro_ 3 dB for the closedloop circuit gain. To achieve this unitygain frequency.62) However.27 ns.8xlO radls = 21t X 61 MHz 8 (6.. which is over a three times improvement as compared to when lead compensation is not used.1 of Chapter 5.7 MHz. As a result.e. to the output (i. resulting in C L being 32.e. the unitygain frequency must be constrained to be less than 0.7 times the equivalent secondpole frequency.7 MHz. As a final comment. which is 42. After the lead resistor is added. notice that the delay through the signal path from the drain of 0. For the foldedcascade opamp. (6. the unitygain frequencies of the foldedcascade and currentmirror amplifiers are strongly related to their load capacitance. We also saw that ro_ 3 dB is given by the relationship ro_ 3 dB = 13ro. Specifically. ~2 + ~3 = 1.63) whereas for a currentmirror opamp.278 Chapter 6 • Advanced Current Mirrors and Opamps This result gives an equivalent second pole at the approximate frequency of P'eq =  I = 3.36 ns) is approximately the same as the delay through the signal path from the drain of 0 t to the output. resulting in the new value of C L being 12. it is equal to OOt = K9 m t CL (6. which is t t = 1. while for the classical twostage CMOS opamp the unitygain frequency remains relatively constant for varying load capacitances.5 MHz.6 pF. The benefits of lead compensation are obvious. the unitygain frequency can be chosen so that only a 55 0 phase margin is achieved before the lead resistor is added. This approach would allow the unitygain frequency to be as high as 0. we need to increase C L by the factor 54 MHz/16. its unitygain frequency is given by rot = gmt CL (6. around the frequency of the second pole) by the existence Q[ two signal paths. their settlingtime performance is affected by both the feedback factor as well as the effective load capacitance. the unitygain frequency must be less than 16.
4 Consider the currentmirror opamp with no lead compensation in Example 6.3 being used in the circuit shown in Fig. while C c is a compensation capacitance that might be added to maintain a sufficient phase margin. + Cp)] + lI(sC.6. Therefore.92 fF/lJm' = 0.1 percent accuracy? Solution First. 6.46 pF.oad' as well as that seen looking into C. Fig.66) EXAMPLE 6. Specifically. we have C L = C c + C'oad + C. treating the negative opamp input as an open circuit. their unitygain frequency is inversely proportional to the load capacitance. C p represents parasitic capacitance due to large transistors at the opamp input as well as any switch capacitance. + C. Thus we see that for both these highoutput impedance opamps. is seen to be given by the parallel combination of C c and C.) = c. is 0. the effective load capacitance is given by .67) The capacitance seen looking into the inverting input of the opamp is onehalf this value since the gatesource capacitances of the two input devices are in series. + Cp)] I/[S(C. The feedback network is due to capacitances Cl' C" and C p resulting in f3 = 1/[s(C.(C. (6. At the input side. the effective load capacitance. is equal to the series combination of C 2 together with C. the gatesource capacitances of the input devices of the currentmirror opamp can be calculated to be C gs ' = 300 x 1. + Cp. + Cp) C. 6.92 pF (6. C p .. + c. Thus. the parasitic capacitance. What is the linear settling time required for 0.6 x 1.12 A general circuit for determining the 3dB frequency of 0 closedloop cmpliher. 6.12 with C. consider the general case shown in Fig.65) The effective load capacitance seen by the opamp output is found by analyzing this circuit from a seriesshunt feedback perspective.4 Linear Settlinq Time Revisited 279 c. Combining all these capacitances together. The capacitance seen looking into C. + c. = C 2 = C c = C'oad = 5 pF. + C 2 (6.12. To determine the 3dB frequency of a closedloop opamp. C L . C. At the opamp output. C'oad represents the capacitance of the next stage that the opamp must drive.
the noise rejection of a fully differential design will be much better than that for a singleended output design.72) Finally.61 pF L 5 + 5 + 0. since only the difference between signals is of importance. X (6. Also. almost certainly. for 0.46) = 12. since both sides of the differential signal see the same noise. substrate noise will usually feed in through junction capacitances. One of the major driving forces behind the use of fully differential signals is to help reject noise from the substrate as well as from passtransistor switches turning off in switchedcapacitor applications. and will then be rejected. In other words.69) (6. With opamps.68) 10 radls 8 (6. For example. then ideally the noise will affect both signal paths identically. they are referred to as fully differential opamps. which are nonlinear with voltage. 6. In reality. which is the signal of interest.9 MHz Now.8 ns (6.46 which results in 2 X 1. ~. this technique results in differential outputs as well as inputs. One drawback of using fully differential opamps is that a commonmode feedback (CMFB) circuit must be added.46 + 5 1 = = 7.1 percent accuracy. The reason for this noise rejection is that if the circuit is built in a symmetric manner (sometimes referred to as a balanced circuit). This extra circuitry is needed to establish the . However. the noise will have no effect on the differential signal.280 Chapter 6 • Advanced Current Mirrors and Opamps C = 5+5+ 5(5+0.5 FULLY DIFFERENTIAL OPAMPS Most modern highperformance analog integrated circuits make use of fully differential signal paths.71) ~ resulting in = 5 = 0. we need a linear settling time of 71 or 54 ns.70 12.7 mNV = 2.61 pF or equivalently.48 5 + 0. this rejection only partially occurs since. the clock feedthrough noise introduced by switches turning off usually has some voltagedependent nonlinearities that can cause more noise to feed into one path than the other. and hence. unfortunately. the mechanisms introducing the noise are usually nonlinear with respect to voltage levels.70) is seen to be (6. thereby injecting a differential noise. the feedback factor. II = 42.
the CMFB circuitry is often a source of noise injection and can also substantially increase the load capacitance that needs to be driven. the design of a good commonmode feedback circuit is nontrivialq:. V cntrt. although the signal swings are not usually limited. otherwise noise on the power supplies may be significantly amplified such that the output signal becomes clipped (or distorted).~it usually must have a speed performance comparable to the unitygain frequency of the differential P!!lh.. a commonmode feedback (CMFB) circuit has been added. the commonmode voltage is left to drift. however. The nchannel currentmirror of Fig. The inputs to the CMFB circuit are the two outputs of the fully differential amplifier.which may result in large commonmode signals being injected. Typically. preferably close to halfway between the powersupply voltages. Ideally. differential designs are becoming more and more popular. The unitygain frequency. perhaps constituting a majority in new microcircuit designs. Also. The CMFB circuit will detect the average of these two outputs and force it to be equal to a predetermined value. For this reason. the commonmode loop gain is not typically large enough to control its value. Fully Differential FoldedCascade Opamp A simplified schematic of a fully differential foldedcascade opamp is shown in Fig. it will keep this commonmode voltage immovable. a welldesigned.6. The gate voltage on the drive transistors of these current sources is determined by the output voltage. as we shall see in the next section.9 has been replaced by two cascade current sources.5 Fully Differential Opamps 281 V commonmode (i. Without it. Another drawback of fully differential opamps is that in many designs. Such is not the case with differential signals as the differential loop gainis typically quite large.e. one composed of Q 7 and Q8' the other composed of Q 9 and QIO' In addition. This slewrate reduction occurs because the" maximumcurrent for skWmg is ofiffillmited by fixedbias currents in the output stages. since. For example. the negativegoing current in the output stage is fixed. in the fully differential amplifiers to l5'e presented shortly. straightforward continuoustime designs often don't work when largedifferential signals are presem. is usually increased because one of the currentmirrors is typically eliminated from the signal path.s. these continuoustime CMFB circuits are the major limitation on maximum allowable signals. average) output voltage. even when switchedcapacitor CMFB circuits (described in the next section) are used. the maximum current available for the negative slew rate is limited by the bias currents of Q 7 or Q9' If the CMFB circuit .. 6. 13.fhcsingleended slewrate in one direction is substantially reduced when it is compared to that of equivalent si~gre:endedolilpUt ctesig. although the opamp is placed in a feedback configuration. Note that when the opamp output is slewing. This speed requirement is necessary. S'ec6nit. As we will see in the next section.of the commonmode feedback circuit. often limiting the signals substantially more than the differential signalpath circuitry does. fully differential amplifier works very well and can substantially improve the noise rejection. even when large differential signals are present. Q. Regardless of some of the limitations just described.
namely the drain nodes of the input devices.... n. and it is important to maximize the bandwidth. rather than pchannel transistors.6. In any case. Also. .ctedd~sTgn"presented earlier. Each signal path now consists of only one node in addition to the output nodes. fully differential foldedcascode opamps are usually designed with the bias currents in the output stage equal to the bias currents in the input transistors.e.. would become smaller due to the input transistors now being pchannel transistors. the CMFB circuitry could possibly be slower.1IC :11'3t' Vcntrl Q. These nodes will most certainly be responsible for the equivalent second poles. This complementary circuit would result in the impedance at the drains of the input devices being the inverse of the transconductance of nchannel transistors. The tradeoff involved is that the opamp's transconductance. Fig....13 A fully differential foldedcascode opamp.0+ c>j Q. is very fast.and pchannel transistors and the power supplies interchanged) would be preferable to maximize the frequency of the equivalent second poles. as the current sources being modulated would also have to be pchannel drive transistors.. If these transistors are not included (as has historically been the case). clamp transistors all and a 12 have been added. and therefore the opamp's de gain. Also. these will be increased dynamically to some degree during slewing. a complementary design is often a reasonable choice for highspeed fully differential designs. a complementary design (i.282 Chapter 6 • Advanced Current Mirrors and Opamps Qs ::II... For this reason. but seldom to the degree of a singleended output fully differential opamp.. as in the si~gle~e.... to minimize transient voltage changes d\lring slewrate limiting. In cases where the load capacitance is small. Q. +""""1~f<>Vout CMFB circuit Q8 :Jf. the time to recover from slewrate limiting of the foldedcascade amplifier can be comparatively poor.. resulting in smaller impedances and therefore faster time constants.~c::: Q6 +1.
._(!D.:=H' Vcntrl Fig.15..6. If a generalpurpose fully differential opamp is desired. nchannel current mirrors.. for reasons similar to those discussed for the foldedcascade opamp. nchannel inputs are preferable in the former case and pchannel inputs are preferable in the latter case. 6. but now the current mirrors at the top (i. and by whether maximizing the de gain or the bandwidth is more important. + ~<~f_oVoul CMFB circuit 04 :If.mirrors and current sources is probably a good choice..Il.14. The first 1:K 1:K ""'1r. Which design is preferable is primarily determined by whether the load capacitance or the equivalent second poles are limiting the bandwidth. nchannel input transistors will give lower thermal noise (due to their larger transconductances).6. As with the foldedcascode design. then this design with large pchannel input transistors. One of the limitations of the fully differential opamps seen so far is that the maximum current at the output for singleended slew~nJL!. as shown in simplified form in Fig. this circuit can be realized as shown or in a complementary design..14.I1. a current gain of K = 2. It is possible to modify the designs to get bidirectional drive capability at the output. Also.<>+ 0.. 6. and wideswing enhanced outputimpedance cascade .is limited by fixed current sources.e.£irectiQ. with pchannel input transistors. and pchannel bias current sources. the pchannel current mirrors) have been replaced by current mirrors having two outputs.e. 6. compared to all other fully differential alternatives. as is shown in Fig..14 A fully differential currentmirror opamp.5 Fully Differential Opamps 283 Alternative Fully Differential Opamps An alternative design is the fully differential currentmirror opamp.. . This opamp is similar to the current mirror design of Fig. whereas pchannel inputs will result in less opamp inputreferred l/f noise.
The advantage of the input stage in this opamp is that during slewrate limiting. A third alternative. Assume now the differential output is slewing in the positive direction. For example. is shown in Fig. but the total current in the other differential pair will dynamically increase substantially. the current being sinked from Vnut. Each differential pair is composed of an nchannel and a pchannel transistor.: K:1 Fig. This circuit has an improved slew rate at the expense of slower smallsignal response due to the addition of the extra outputs on the pchannel mirrors and the additional nchannel mirrors. and a differential pair consisting of pchannel transistor 3 and nchannel transistor 4 • The other input stage consists of level shifter and 6 . the differential input will be very positive and the slewing current going into V0"'+ will be Kl bias . 1985]. For this case. although it is required. one differential pair will turn off. 6. assuming a large positive input as. a 1:K 1:1 1:1 Q2 fo Vin_ Vout+ v.6. At each output node. The second output has a gain of one and goes to a new nchannel current mirror that has a current gain of K. Specifically.will also be Kl bi• s. . as before. This design has two differentialpair input stages connected in parallel.284 Chapter 6 • Advanced Current Mirrors and Opamps output has a current gain of K and goes to the output of the opamp. Of course. commonmode feedback must be added to the circuit of Fig. 6. and differential pair and In addition. currents originally coming from the nchannel transistor of one differential pair and from the pchannel transistor of the other differential pair are summed. and some levelshift transistors. there are four current mirrors to sum the drain currents of all differential pair transistors at the output nodes. as shown. but due to the additional nchannel mirrors. as a a a. one input stage consists of a levelshift circuit composed of source follower a.15 1:K A fully differential opomp with bidirectional output drive. Note here that for simplicity.16 [Castello. which makes use of a classAB input stage. although in many applications this tradeoff may be well merited. the CMFB circuit is not shown. and diodeconnected a 2 .15. where it is mirrored a second time and then goes to the opamp's opposite output.
which contribute to the equivalent second pole. causing it to slew in a negative direction. but has additional current mirrors and complexity. This design also has a fairly large slew rate when compared to the simpler fully differential currentmirror opamp of Fig.17. 6. In addition.: K:1 1:K Fig. The disadvantage of this design is that the levelshift circuitry required at the input increases the noise and adds additional parasitics. + 3V eff above the lower power supply (and typically higher for the slewrate performance to be maintained). However. This is a major problem when 5V power supplies are being used. whereas the current from 0 7 goes through a current mirror to the Vout. and it effectively eliminates this design from consideration for use with 3. and the slew rate is very important. Another advantage of this design is that the noise voltages due to the input transistors sum in a squared . 6. the load capacitances are large.6. giving this opamp a very large slewrate performance.6. 0 4 turns off. Another alternative for a fully differential opamp is to use two singleended output opamps with their inputs connected in parallel and each of their outputs being one output side of the fully differential circuit.3V power supply voltages. the commonmode range of the input must remain at least 2V. As a result.16 A class AB fully differential opamp. voltage. the pair OJ. 0. An example of such an approach using currentmirror subcircuits is shown in Fig.5 Fully Differential Opamps 285 K:1 1:K Vout+ v. The currents at this time of slewrate limiting will be much larger than the smallsignal bias currents. for applications where the powersupply voltages are large.14. while the current through the pair 0 7. causing it to slew in a positive direction. the increased current through 0 8 goes through a current mirror to the V OUI+ node. this approach is quite reasonable. CMFB circuit not shown.node. increases.
286
Chapter 6 • Advanced Current Mirrars and Opamps
K:1
1:K
Vout+
K:1
v.:
v:
1:K
Fig. 6.17
A fully differential apamp composed of two singleended output currentmirror opamps.
not
CMFB circuit
shown.
fashion, while the two signal paths sum linearly.' As a result, this design has an improvement in signaltonoise ratio of the inputreferred gain by a factor of j2, or 3 dB. Also, the increase in total power dissipation is not significant when K is moderately large. As for the previous design, the compensation of the commonmode feedback loop is more difficult than for designs having fixed current sources biasing the output stages. Another alternative design is shown in somewhat simplified form in Fig. 6.18. The advantage of this circuit is that due to the use of both nchannel and pchannel transistors in the two differential input pairs, the input commonmode voltage range is increased [Babanezhad, 1988; Hogervorst, 1992; Caban, 1994]. This feature can be particularly important when low powersupply voltages are being used. When the input commonmode voltage range is close to one of the powersupply voltages, one of the input differential pairs will turn off, but the other one will remain active. In an effort to keep the opamp gain relatively constant during this time, the bias currents of the stillactive differential pair are dynamically increased. For example, if the input commonmode voltage range was close to the positive powersupply voltage, Q 3 and Q 4 would turn off, and Q 6 would conduct all of I,. This current would go through current mirror M 1 and increase the bias current of the differential pair consisting of Q 1 and Q2' which is still active. A similar situation occurs if the input commonmode voltage is near the negative powersupply rail. With careful design, it has been reported that the transconductance of the input stage can be held constant to within 15 percent of its nominal value with an input commonmode voltage
5. See Chapter 4 regarding noise.
6.6
CommonMode Feedback Circuits
287
I, ...
M,
Fig.6.18
An opamp having roiltorei! input commonmode voltage range. CMFB cir
cuit not shown.
range as large as the difference between the powersupply voltages [Caban, 1994].
6.6 COMMONMODE FEEDBACK CIRCUITS
Typically, when using fullydifferential oparnps in a feedback application, the applied feedback determines the differential signal voltages, but does not affect the commonmode voltages. It is therefore necessary to add additional circuitry to determine the output commonmode voltage and to control it to be equal to some specified voltage, usually about halfway between the powersupply voltages. This circuitry, referred to as the commonmode feedback (CMFB) circuitry, is often the most difficult part of the oparnp to design. There are two typical approaches to designing CMFB circuitsa continuoustime approach and a switchedcapacitor approach. The former approach is often the limiting factor on maximizing the signal swings, and, if nonlinear, may actually introduce commonmode signals. The latter approach is typically only used in switchedcapacitor circuits, since in continuoustime applications it introduces clockfeedthrough glitches. An example of a continuoustime CMFB circuit is shown in Fig. 6.19 [Martin, 1985; Whatly, 1986]. To illustrate its operation, assume a commonmode output voltage of zero and that Vout is equal in magnitude, but opposite in sign, to Vout.' Furthermore, assume the two differential pairs have infinite commonmode input
288
Chapter 6 • Advanced Current Mirrors and Opomps
I.
Q,
V"h oj
Q,
Vcntrl
I
I·i
Q,
1./2 ~Ii
il./2 + M
Fig.6.19
An example of a continuoustime CMFB circuit.
rejection, which implies that the largesignal output currents of the differential pairs depend only on their input differential voltages. Since the two pairs have the same differential voltages being applied, the current in 0 1 will be equal to the current in 0 3 , while the current in 0, will equal the current in 0 4 , This result is valid independent of the nonlinear relationship between a dilJerential pair's input voltage and its largesignal differential drain currents. Now, letting the current in 0, be denoted as 10 2 = I B/2 + M, where I B is the bias current of the differential pair and M is the largesignal current change in 10 2 , the current in 0 3 is given by 10 3 = OB/2)  M, and the current in Os is given by
(6.73)
Thus, as long as the voltage V0"1+ is equal to the negative value of V0"1' the current through diodeconnected 0 5 will not change even when large differential signal voltages are present. Since the voltage across diodeconnected Os is used to control the bias voltages of the output stage of the opamps, this means that when no commonmode voltage is present, the bias currents in the output stage will be the same regardless of whether a signal is present or not. Note, however, that the above result does not remain valid if the output voltage is so large that transistors in the differential pairs turn off. Next consider what happens when a commonmode voltage other than zero' is present. For example, assume a positive commonmode signal is present. This positive voltage will cause the currents in both 0, and 0 3 to increase, which
6. For this example. it is assumed that positive and negative power supplies are present and that the desired commonmode voltage is zero. In a singlesupply application, the gales of O 2 and Q~ would be connected to a bias voltage equal to the desired output commonmode voltage.
6.6
CommonMode Feedback Circuits
289
causes the current in diodeconnected Os to increase, which in turn causes its voltage to increase. This voltage is the bias voltage that sets the current levels in the nchannel current sources at the output of the opamp. Thus, both current sources will have larger currents pulling down to the negative rail, which will cause the commonmode voltage to decrease, bringing the commonmode voltage back to zero (or almost zero). Thus, as long as the commonmode loop gain is large enough, and the differential signals are not so large as to cause transistors in the differential pairs to turn off, the commonmode output voltage will be kept very close to ground. The size of the differential signals that can be processed without one of the differentialpair signals turning off is maximized if the differentialpair transistors are designed to have large effective gatesource voltages. Alternatively, source degeneration can be used to allow them to have larger input signals without all of the current being directed to one side of the differential pair. However, even when this maximization is performed, the CMFB circuit still limits the differential signals to be less than what can be processed by the rest of the opamp. Finally, it should be noted that when realizing the CMFB circuit of Fig. 6.19, the current sources Is should be highoutput impedance cascade current sources to ensure good commonmode rejection of the two differential pairs. A modified version of the CMFB circuit of Fig. 6.19 is shown in Fig. 6.20 [DuqueCarillo, 1993]. This version adds an additional transistor (0,) and an additional current source to make use of the other sides of the differential pairs, which were previously unused in Fig. 6.19. This change effectively doubles the commonmode gain of the circuit for little additional complexity. As reported in [DuqueCarillo, 1993], it has very good linearity (better than 0.01 %).
0,
,..+,+
Is I"J2 + Mb I"J2  Mb
+,..+,
Vout+ ~
O2
Vcntrl . .
I
ile<p.....+_'
I"J2Mb
+
Fig. 6.20 A modified CMFB circuit having twice the commonmode gain as that of Fig. 6.19.
290
Chapter 6 • Advanced Current Mirrors and Opamps
V001+
ol
0,
20 k!1 20 kQ
1.5 pF
1.5 pF
VA = VCM(Velfl +V tt )
Vcntrl ........ir:
V,ef = (V elfl + V tt )
Fig. 6.21
An alternative continuoustime CMFB circuit.
An alternative approach for realizing CMFB circuits is shown in Fig. 6.21 [Banu, 1988]. This circuit generates the commonmode voltage of the output signals (minus a de level shift) at node VA' This voltage is then compared to a reference voltage. V,eb using a separate amplifier. Although this approach works well, it has a major limitation in that the voltage drop across the sourcefollower transistors 0 1,0, severely limits the differential signals that can be processed (unless transistors with native threshold voltages, such as 0.3 volts, are available). This limitation is particularly important when small powersupply voltages are used. In addition, the additional nodes of the commonmode feedback circuitry make the circuit slightly more difficult to compensate. When bipolar transistors are available, as is the case in a BiCMOS process, this approach is much more desirable. An important consideration when designing CMFB circuits is that they be well compensated. Otherwise, the injection of commonmode signals can cause them to ring or even possibly become unstable. Thus, when the circuit is being designed, the phase margin and stepresponse of the commonmode loop should be found and verified by simulation. Often, the compensation of the commonmode loop can be realized using the same compensation capacitors used to stabilize the differential loop. This. multipurpose compensation is achieved by connecting two compensation (or loading) capacitors between the opamp outputs and ground (or some other reference voltage). The other approach would be to use a single compensation capacitor connected directly between the two outputs, but this method only compensates the differential loop. It should be mentioned that by having as few nodes in the commonmode loop as is possible, compensation is simplified without having to severely limit the speed of the CMFB circuit. For this reason, the CMFB circuit is usually used to control current sources in the output stage of the opamp, as opposed to the current sources in the input stage of the opamp. The high speed of the CMFB circuit is neces
6.7 CurrentFeedback Opamps
291
Vbias
Vcntrl
""'
Fig. 6.22 A switchedeapacitor CMFB circuit.
sary to minimize the effects of highfrequency commonmode noise, which could be amplified, causing the opamp outputs to saturate. Finally, it should be stated that designing continuoustime CMFB circuits that are both linear and operate with low
powersupply voltages is an area of continuing research.
A third approach for realizing CMFB circuits is based on the use of switchedcapacitor circuits. An example of this approach is shown in Fig. 6.22 [Senderowicz, 1982; Castello, 1985]_ In this approach, capacitors labelled C e generate the average of the output voltages, which is used to create control voltages for the opamp current sources. The de voltage across C e is determined by capacitors C s, which are switched between bias voltages and between being in parallel with C e. This circuit acts much like a simple switchedcapacitor lowpass filter having a de input signal. The bias voltages are designed to be equal to the difference between the desired commonmode voltage and the desired control voltage used for the opamp current sources. The capacitors being switched, C s, might be between onequarter and onetenth the sizes of the nonswitched capacitors, C e. Using larger capacitance values overloads the opamp more than is necessary during the phase <1>2' and their size is not critical to circuit performance. Reducing the capacitors too much causes commonmode offset voltages due to charge injection of the switches. Normally, all of the switches would be realized by minimumsize nchannel transistors only. except for the switches connected to the outputs, which might be realized by transmission gates (i.e., parallel nchannel and pchannel transistors both having minimum size) to accommodate a wider signal swing. In applications where the opamp is being used to realize switchedcapacitor circuits, switchedcapacitor CMFB circuits are generally preferred over their continuoustime counterparts since they allow a larger output signal swing.
6.7 CURRENTFEEDBACK OPAMPS
The last type of opamp described in this chapter is referred to as a currentfeedback opamp. This type of opamp has become popular recently, particularly in applications
292
Chapter 6 • Advanced Current Mirrors and Opamps where high gain and high speed are required [Comlinear, 1985; Bowers, 1990]. One of this opamp's advantages is that its closedloop gain can be changed, when used in a feedback application, without significantly affecting its loop gain. Because of this feature, a single compensation capacitor of one size can be used irrespective of the gain selected. As will be seen, the opamp is similar to many of the highspeed CMOS opamps described above, in that all nodes are low impedance except for the node where the compensation capacitor is located. Currently, the most popular technology used for realizing currentfeedback opamps is a highspeed complementarybipolar technology having vertical pnp transistors that have speeds comparable to vertical npn transistors. A simplified example of a currentfeedback opamp is shown in Fig. 6.23, where R o is the impedance at the output of the current mirrors. The input signal, v;n' is applied to a highimpedance input, while a feedback current connects to a lowimpedance node labelled V n The impedance seen looking into this lowimpedance node is on the order of II (29m I)' Ignoring stability issues, the basic operation of this currentfeedback opamp can be understood as follows. The voltage at v n is equal to the input voltage, v;n' due to the classAll unitygain buffer stage consisting of 0 1, O 2 , and the two diodes. Now assuming Ro is very large and ignoring C c (which is included for compensation), a small feedback current, if' results in a large output voltage, v out' Thus, during stable
I R .!L2
I R  if
2
IR
...
Q,
Vn
1:1
+
C, Ro R2
if
... Unitygain buffer
Va",
v;
Q2
I
Feedback
+IR
it
resistors
R,
...
I R + if
1:1
"2
(
Wilson current mirror
IR + JL
2
...

Fig, 6.23 A currentfeedback apamp.
6.7
CurrenfFesdbock Opamps
293
operation, if ~ 0 such that v o " , goes to a finite voltage value. Finally, v o " , is seen to be related to v; = v;o due to the two resistors, R, and R,. Specifically, noting that if = 0, we have
R,
=
R2
R I + Rz
(6.74)
which can be rearranged to give the following input/output relationship:
o ut
v
vin
_R I
(6.75)
To understand the feedback nature of the currentfeedback opamp, we make some simplifying assumptions here. First, assume that the transistor current gain, [3, is infinite. Also assume that the impedance looking into the emitters of Q, and Q" which is 1/(9m' + 9m2)' is much smaller than R, II R,. Finally, assume the feedback current, i" splits equally between the two transistors Q, and Q,. Although this equal current splitting assumption is unnecessary (since the two currents will add to if in any case), it does make the explanation simpler. The signal being fed back in the opamp is the signal current if coming from the feedback network of R, and R, and going into the emitters of Q, and Q,. Recalling that Vo = V;O' this current is given by
. If
= IA  'R =
.
.
"
vo ut  vin   in = vo ut  v· ( v R, R, R,
m
R,
1+  1)
R,
(6.76)
Now, with Q, and Q, having infinite current gains, [3,the collector currents of Q, and Q, are both equal to their bias currents, IR' added to their fedback signal currents, if / 2 . This current is mirrored by current mirrors whose outputs are summed at the highimpedance node. Note that this highimpedance node sees an impedance to ground equal to the compensation capacitor, C e, in parallel with a high resistance, R o' This resistance, R o' is large, typically on the order of (9mr.l)/4. The loop gain for this circuit can be found by breaking the loop at the top of R, and injecting a signal, v.; at the top of R,. By breaking the loop at the lowimpedance output of the unitygain buffer, there is only a small error in ignoring the loading effect of the feedback network. The loop gain is then equal to the ratio of V0", to Vx' while zeroing the input signal, V;O. The loop gain, LG(s), is seen to be LG(s) =
lv, If
=
(IflVO"']
V;o
(6.77)
= 0 and letting Vx = V O " "
The first term in (6.77) can be found using (6.76) for We have
R,
(6.78)
assuming again that Vx = V;o' For the second term, note from Fig. 6.23 that the smallsignal portions of the currents from the current mirrors sum together and both
294
Chapter 6 • Advanced Current Mirrors and Opamps
flow out of the parallel combination of C c and R o' resulting in
Vout =      '  sCe + l/R o
Substituting (6.78) and (6.79) into (6.77), we have
LG(S) =
r,
(6.79)
R IR
0 ,
1+ sCeR o  sCeR,


1
(6.80)
where the approximation is valid at high frequencies. Thus, we see here that the highfrequency behavior of the loop gain is independent of R, . As a result, one can change R, to realize various closedloop gains without affecting the unitygain frequency or the closedloop stability. Using (6.80), we see the unitygain frequency, 00" is given by
00, '"  
I
CeR,
(6.81)
To find the closedloop transfer function, we can substitute (6.79) into (6.76) and simplify to obtain
Ac'(s) = 
v.:
Vin
=
I/R, + l/R, Ro(R, + R,)( 1 ) = (6.82) l/R, + l/R, + sc, (R o + R,)R, 1 + sCC<R o II R,)
For R o » R" which is typically a good assumption, we have
Ac'(s) '"
R, + R,(
R,
1
1 + sCeR,
I )
(6.83)
Thus, the 3dB frequency of the closedloop transfer function is given by
00
3 dB 

C R
(6.84)
e ,
which is the same as the unitygain frequency of the openloop response, and is independent of R, and the lowfrequency closedloop gain. Therefore C e can be chosen once, for a given R" and will remain optimum to a firstorder approximation, irrespective of R, and the closedloop gain. This independence is one of the main benefits of using currentfeedback amplifiers. Specifically, they can attain very high 3dB frequency values for large closedloop gains, or in other words, large gainbandwidth products. For example, if a currentfeedback amplifier has a closedloop gain of unity and a 3dB frequency of 100 MHz, it has a gainbandwidth product of 100 MHz. Now, by simply reducing R " the same amplifier might have a closedloop gain of 20, but its 3dB frequency remains near 100 MHz, and thus its gainbandwidth product is near 2 GHz! It should be noted here, though, that above 100 MHz the gain would most likely fall off quite a bit faster than 20 dB/decade, since the nondominant poles will be only somewhat greater than 100 MHz. This compensation independence does not occur for the more common voltagefeedback amplifiers. With voltagefeedback amplifiers, as the closedloop gain is
6.8
SPICE Simulation Examples
295
increased, the closedloop 3dB frequency is decreased by the same amount if the compensation capacitor remains the same. As a result, the gainbandwidth product for a voltagefeedback amplifier remains constant for a given compensation capacitor. For example, if a voltagefeedback amplifier has a closedloop gain of unity and a 3dB frequency of 100 MHz, when the closedloop gain is changed to 20, the 3dB frequency . lowers to 5 MHz. However, in this case, the gain above 5 MHz will fall off at20 dB/ decade until somewhat greater than 100 MHz (when the nondominant poles come into effect). In addition, it should be noted that for a given fixed closedloop gain, voltagefeedback amplifiers can achieve similar gainbandwidth products to their currentfeedback counterparts if one is allowed to change their compensation capacitor. Specifically, for larger closedloop gains, the feedback factor ~, and thus loop gain, is decreased; as a result, a smaller compensation capacitor can be used to obtain the same phase margin. In most practical realizations of currentfeedback amplifiers, Darlingtonpair transistors are used in the input stage to decrease the input bias currents required. Unfortunately, this approach makes the opamp somewhat noisier and increases the opamp input offset voltages somewhat. Another limitation is the requirement that R I be taken much larger than the impedances looking into the emitters of Q I and Q2' namely l/(9ml + 9m2)' As a result, R I , and therefore R, as well, need to be larger than would be desired for optimum highfrequency performance. This limitation is more severe in highgain applications where R I « R,. Additionally, these currentfeedback opamps typically make use of a purely resistive feedback network and may become difficult to compensate if reactive components (such as a capacitor) are used in the feedback network. Regardless of these limitations, currentfeedback opamps exhibit excellent highfrequency characteristics and are quite popular in many video
and telecommunications applications.
6.8 SPICE SIMULATION EXAMPLES
In this section, simulation results for Example 6.2 and Example 6.3 are presented.
'I
Simulation of Example 6.2
The circuit for Example 6.2 is shown in Fig. 6.24. First, the clamp transistors, Q I2 and are excluded. Bias voltages VB I and VB2 are set such that all transistors are active, and an ac analysis is performed to determine the unitygain frequency. Next, the opamp is placed in unitygain configuration, and a step response is performed to determine the slew rate. Finally, the clamp transistors are included, and the resulting slew rate is determined. NETLIST: vdd I vss 2
QI3'
o o
de 2.5 dc 2.5
296
Chapter 6 • Advanced Current Mirrors and Opamps
Qs
8 9
2
v;
~
+
Q,
Q,
11
13
14
+......< V
0",
10
I bias2
2
15
VB'
01
Q7
Q8
Q. :If.....~ Q"
2
2
£ 1
Fig. 6.24 A foldedcascode opamp.
PMOS w = lOum I = 1.6um tic 6.6J,t PMOS w = 300um I = 1.6um PMOS w = 300um I = 1.6um NMOS w = 300um I = 1.6um NMOS w = 300um I = 1.6um de 32011 PMOS w = 60um I = 1.6um PMOS w = 60um I = 1.6um NMOS w = 20um I = 1.6um NMOS w = 20um I = 1.6um NMOS w = 20um I = 1.6um NMOS w = 20um I = 1.6um lOp 347 dc 0.75 de I de 0 ac 1 de 0
rn l l
ibias1 m3 m4 m1 m2 ibias2 m5 m6 m7 m8 m9 mlO CI Rc vbl vb2 vinlO vin9
3 3 6 7 6 7 11 13 14 13 14 16 17 14 18 8 15
10
9
3 2 3 3 9 10 2 8 8 15 15 13 13 18 0 0 0 0 0
1 1 II 11 7 6 16 17 2 2
1 1 2 2 I 1 2 2 2 2
The frequency plot of the foldedcascade opamp is shown in Fig. 6.25, where we find that the unitygain frequency occurs at about 40 MHz. The step response of the foldedcascade opamp without clamp transistors is shown in Fig. 6.26(a), where we
8O
80
F
,,'

6.8
SPICE Simulatian Examples
297
~
~I
1
,.
Frequency [Hz]
,,'
Fig. 6.25
opamp.
Frequency plat of
the Ioldedcoscode
••
~ 0,6
( ,

:>:
~
}"r
~,
'5 0.4
l .
02~
1
_Tim@[5J
.10')
.~._~,
._~_.~~ .. 0 ' 2 3 4 5 6
c
~
t
a
~~._j
3 4 5
1
;;me[SJ
6 .107
(a)
(b)
Fig. 6.26 The step response of the clomp transistors.
Ioldedccscode opamp la} without clamp transiMars and (b) with
find the slew rate is about 23 VI/oiS. The step response of the foldedcascode opamp with clamp transistors is shown in Fig. 6.26(b), where we find that the slew rate is now 27 V//ols. While this slewrate improvement is not that substantial, it should be noted that the main advantage of including the clamp transistors is to help the opamp
recover from slewrate conditions more quickly.
Simulation of Example 6.3
The circuit for Example 6.3 is shown in Fig. 6.27. First, an ac analysis is performed to determine the unitygain frequency. Then the opamp is placed in unitygain
298
Chapter 6 • Advanced Current Mirrors and Opomps
5
.  ......c Vout
8
10
2
Fig.6.27 A currentmirror opamp.
2 10 14 = KI,
2
= KI"I2
configuration, and a step response is performed to determine the slew rate. NETLIST: vdd vss m5 m6 m3 m4 m1 m2 ib m7 m8 m9 m10 mll m12 ml3 m14 c1 vb2 vb1 vinl vin2 1 2 4 7 3 6 3 6 8
II
12 14 13 14 13 16
17
13 5 18 9 10
0 0 3 6 5 5 9 10 2 6 3 5 5 18 18 14 14 0 0 0 0 0
1 1 4 7 8 8 1 1 11 12 16 17 2 2
1 1 1 1 2 2 1 1 1 1 2 2 2 2
de 2.5 de 2.5 PMOS w = 60um I = 1.6um PMOS w = 60um I = 1.6um PMOS w = 60um I = 1.6um PMOS w = 60um I = 1.6um NMOS w = 300um I = 1.6um NMOS w = 300um I = 1.6um 160um PMOS w = 60um I = 1.6um PMOS w = 120um I = 1.6um PMOS w = 60um I = 1.6um PMOS w = 120um I = 1.6um NMOS w = 30um I = 1.6um NMOS w = 60um I = 1.6um NMOS w = 30um I = 1.6um NMOS w = 60um I = 1.6um lOp de 0.6 de 1.24 de 0 ac I de 0
The frequency plot of the opamp is shown in Fig. 6.28(a), where it is seen that unitygain frequency is about 50 MHz. The step response of the opamp is shown in Fig. 6.28(b), where it can be determined that the slew rate is about 30 V/lls.
6.9
"
References
., .. _  
299
"
0.8~ 0.6
}
0.40.2'
0
_20 L
~,
W'
10'
10' F,eqlJllnc:yIHzI
10'
w·
0
a
T;melsJ
e
• 10'
(a)
(b)
Fig.6.28
Simulation results for 0 currentmirror opamp. (0) Frequency response.
lbl Step response.
6.9 REFERENCES
J. N. Babanezhad, "A RailtoRail CMOS Opamp," IEEE 1. of SolidState Circuits, Vol. 23, no. 6, pp. 14141417, December 1988.
1. N. Babanezhad and R. Gregorian, "A Programmable GainILoss Circuit," IEEE J. of SolidState Circuits, Vol. 22, no. 6, pp. 10821090, December 1987.
M. Banu, J. M. Khoury, and Y. Tsividis, "Fully Differential Operational Amplifiers with Accurate Output Balancing," IEEE 1. of SolidState Circuits, Vol. 23, no. 6,pp. 14101414, December 1988. D. F. Bowers, "Applying 'CurrentFeedback' to Voltage Amplifiers," Analog Ie Design: The CurrentMode Approach. C. Toumazou, F. J. Lidgey, and D. G. Haigh, eds., Peter Peregrinus, London, 1990. K. Bult and G. J. G. M. Geelen, "A FastSettling CMOS Opamp for SC Circuits with 90dB DC Gain," IEEE 1. of SolidState Circuits, Vol. 25, no. 6, pp. 13791384, December 1990.
R. Castello and P. R. Gray, "A HighPerformance Micropower SwitchedCapacitor Filter," IEEE J. of SolidState Circuits, Vol. 20, no. 6, pp. 11221132, December 1985.
A. Caban and P. Allen, "A 1.75V RailtoRail CMOS Opamp," Proceedings of the IEEE Int. Symp. on Circuits and Systems, Vol. 5, pp. 5.4975.500, London, June 1994. Comlinear Corporation, "A New Approach to Opamp Design," Comlinear Corporation Application Note 3001, March 1985.
J. F. DuqueCarillo, "Control of the CommonMode Component in CMOS ContinuousTime Fully Differential Signal Processing," Analog Integrated Circuits and Signal Processing, An International Journal, Kluwer Academic Publishers, September 1993.
U. Gatti, F. Maloberti, and G. Torelli, "A Novel CMOS Linear Transconductance Cell for ContinuousTime Filters," proceedings of the IEEE Int. Symp. on Circuits and Systems, pp. 11731176, New Orleans, May 1990. R. Hogervorst, et aI., "CMOS LowVoltage Operational Amplifiers with ConstantGj, RailtoRail Input Stage," proceedings of the IEEE Int. Symp. on Circuits and Systems, pp. 28762879, San Diego, May 1992. B. Hosticka. "Improvement of the Gain ofMOS Amplifiers," IEEE J. of SolidState Circuits, Vol. SC14, no. 14, pp. 1111~1114, December 1979, S. Law, Private conversation, Xerox Corp., 1983. K. Martin, Class notes, UCLA, 1985.
0 X 10." U. Sooch." U. 4. pp. February 1990. where Veff is chosen to be 0..550.10 PROBLEMS Unless otherwise stated. Assume both transistors are in the active region. 6. 1. August 1986. "A HighSwing." IEEE 1.pF/~m 3 Cox = 1. October 1985. and assume 9ml = 9m2' rdsl = r ds2. Shih and P. 6.8 V = 12.p = 0. C. D. of SolidState Circuits. Assume n is chosen to be I in Fig.2 if the lengths of OJ and 0 4 are decreased to I urn to maximize speed? .3 What are the drainsource voltages of OJ and 0 4 from Problem 6. find the required size for all transistors assuming they all have lengths equal to 1. 17.0 X 10. Vol. ignore the body effect. R. patent no. C.()()OL(~m)lID(mA) in active region Ci = 4.pF/~m 4 • pchannel MOS transistors: 2 ~pCox = 30 ~A/V V. no. E. "Reference Refreshing Cyclic AnalogtoDigital and DigitaltoAnalog Converters. no. and 9mrds» I. except (W/L).O()()L(~m)/I~(mA) in active region 4 Cj = 2Ax 10. A. assume the following: • nchannel MOS transistors: 2 ~nCox = 92 ~A/V V'n = 0. Guggenbuhl.0 x 10 pF/~m rdS(O) 6. February 1986.S.1 and all transistors are taken to be equal sizes. "A Family of Differential NMOS Analog Circuits for a PCM Codec Filter Chip. albeit after [Coban 1994]). Senderowicz. Whatly.2 Calculate the output impedance of the twotransistor diodeconnected circuit shown in Fig." IEEE}. 6. 21.sw = 2. Vol. patent no. Assume that lblas= 50 ~A. pp. of SolidState Circuits. pp. S. 544554. December 1982.9 X 10. 1994. of SolidState Circuits.5 x 10 pF/~m 3 Cox = 1.9 V I/ 2 Y = 0. no.5 V rdS(O) = 8. Gray.284. 10141023.pF/(~m) 4 Cj •sw = 2.1 6. R.9 X 10. is chosen so that V DS3 = V DS2 = Veff3 + 0. Ignoring the body effect.. P6. 4573020.pF/(~m)2 4 Cgs(ovenap) = Cgd(ovenap) = 2. "MOS Cascade Current Mirror.S.2 V for all transistors except 0.6 urn. Vol.300 Chapter 6 • Advanced Current Mirrors and Opamps K.1 using smallsignal analysis. "FullyDifferential Operational Amplifierwith DC CommonMode Feedback.5 x 104 pF/(~m) 2 4 C i ." IEEE J.8 V I/ 2 Y = 0.15 V. HighImpedance MOS Cascade Circuit. Laboratory notes (independently derived. et a1. N. Martin. Sackinger and W.pF/(~m)2 Cgs(OVenaPI = Cgd(ovenap) = 2. 289298. 25. 4. 6.
2 to give Vel B = 0. P6. 6. Assume that all current sources are ideal and that lin = 7Ibias ' Compare this to the output impedance of a wideswing cascode current mirror where the gate of Q. Using smallsignal analysis and ignoring the body effect.. Assume 6.9 . 6.[ds2(l +A).rVB 6. ':' Fig. 6. estimate the output impedance. 6.6 with the WIL ratios shown and assuming all lengths are 1.2 V at 20°C? Assume Jln varies as in Problem 6. 6.8 For the circuit shown in Fig.2 has a temperature dependence of +0.3 has an output impedance given by [out" 9m'[ds. with the transistor sizes given in Table 6. 6.5 6.2 V? Assuming that u.10 For the foldedcascode amplifier shown in Fig.9. What would Veff 3 be at 100 °C if it was 0.2. 6.1. What is an upper limit on the output impedance assuming RE » r. show that the circuit of Fig.10 Problems rout 301 o+H::: Q2 '~c:: Q. A = 0) for the same case.6 What is the value required for R s in Fig.8.1 6.8 Vbias 01 A RE Fig. Assume Ibia s = 50 JlA.7 6.3%/°C. P6.e. P6. is proportional to T 3/2 • what would V eff 3 be at 100°C if it was 0. was connected to Vcascn from the biasgeneration circuitry of Fig.2 V at 20°C? Assume that R s from Fig.5.6 urn. ? Compare this to the upper limit on the output impedance of a simple cascode mirror (i. find the unitygain frequency and the slew rate. 6.4 6. For the circuit shown in Fig. using smallsignal analysis. find the output impedance.
2 and Example 6. with the transistor sizes given in Table 6. Assume the load capacitances are 10 pF between each output and ground.1. improves the initial unitygain frequency by 20 percent and the phase margin by 30 degrees.3.feedback opamp described in Example 6.18 . find the load capacitance. and load capacitances. junction capacitances can be ignored. also assume the input voltage is a IV step change.11 For the foldedcascade amplifier shown in Fig. how close must the output voltage come to its final value before its output voltage rate of change is less than the slew rate? How long would this take? How much longer would be required for linear settling to I percent of the total voltage change at the output? What are the singleended slew rates of the fully differential foldedcascade and current mirror opamps. total power dissipation. = 1. and that the power dissipation is I mW.17 6. = C c = C'oad = 5 pF. that C L is 10 pF.4. respectively? Calculate the slew rates in both the positive and the negative directions.11 with lead compensation.9. What is this ratio for K equal to I. 2. Assume the total bias current in the opamp. and 4? Consider the current.302 Chapter 6 • Advanced Current Mirrors and Opamps ±2 V power supplies are used. with C. for a 70° phase margin.14 6. 6.15 6. assuming K = 2 and the current densities are the same as those of Example 6.13 6. is determined by a specified power dissipation.12. For the folded 6.9 to the unitygain frequency of the currentmirror opamp of Fig. To simplify matters. are K times greater than the bias currents in 0 5 and 0 6 . and that the power dissipation is I mW. I'ota'. in a feedback configuration shown in Fig.3. 6.200. 6. assume the bias currents of 0. estimate the approximate frequency of the second pole caused by the parasitic capacitances at the drains of 0. For the foldedcascade opamp. Assume ±2 V power supplies are used. Would the opamp slew rate limit? If so. What size resistor should be used? What is the final unitygain frequency and slew rate? Assume lead compensation with 00. that C L is 10 pf'..11 in terms of K and I tota' assuming both amplifiers have the same size input transistors. 6.9.16 6. What should C L be to achieve 70° phase margin? What would the corresponding unitygain frequency and slew rate be? For the amplifier of Problem 6. and 0. What is the linear settling time for 1 percent accuracy? For the case described in Example 6. Derive an equation for the unitygain frequency in terms of K and I tota" Then show that the unitygain frequency is maximized by taking K large. 6.13. and assuming a currentmirror opamp described in Example 6. C L . For the foldedcascade amplifier shown in Fig.13. but this time show that the de gain is optimized by taking K large. Derive an equation for the ratio of the unitygain frequency of the foldedcascade amplifier of Fig. 6. and 0.12 6. = I pF and C. define K to be I D2/I D7 . Repeat Problem 6.
P6.5 V power supply voltages.6. K.05 pF. a" 6.23 Derive the lowfrequency gain of the currentfeedback amplifier of Fig. 6. 6. and Ib. what Veft bias voltage should be used for the pchannel transistors to maximize signal swing? What is the maximum singleended signal swing before the gain of the commonmode feedback circuitry goes to zero and why? Repeat Problem 6.24. Assuming linear settling.10 Problems 303 cascode design. Capacitor C p is the parasitic capacitance at the opamp input.1 pF and I pF.22 6. Assume the nwells ofthe pchannel transistors are connected to Voo . Ignoring the body effect.19 has ±2. Also.21 Derive the slew rate of the fully differential opamp of Fig. P6. without assuming that the impedance looking into the emitters of a I and O2 is zero. and that the current sources require 0. 6.21. derive 1 m for M = I. Sketch 1 for other values of C I between 0. while Co is the output capacitance.13 have not been included. but do not ignore the body effect.5 V across them in order to have all transistors remain in the active regions. Co = I pF.op.24 Consider the circuit shown in Fig.23 6.25 Based on the results of Problem 6.15 in terms of C L. 6.24 6.as' Derive an equation for the unitygain frequency of the fully differential opamp shown in Fig. 6. . where a highoutputimpedance opamp is used.al' Assume the CMFB circuit of Fig. show that the optimal value for minimizing the time constant of this circuit is given by CI. assume the current sources biasing the output stages do not change during transients. = JMCoC p Fig.24. .20 6.19 6.n and C p = 0.16 in terms of K and Ito. 6. assume the clamp transistors and 0 12 of Fig.
Capacitor C p is the parasitic capacitance at the opamp input.5 V across them in order to have all transistors remain in the active regions. .24 Fig. and Q 2 is zero.05 pF. P6. Co = I pF. where a highoutputimpedance opamp is used. forothervaluesofC. 6. but do not ignore the body effect.24.25 Based on the results of Problem 6. and I blas ' Derive an equation for the unitygain frequency of the fully differential opamp shown in Fig.13 have not been included. Assuming linear settling. Also. 6. and that the current sources require 0. show that the optimal value for minimizing the time constant of this circuit is given by C 1•OP' = JMCoC p 6.23 6.6. 6.19 has ±2.15 in terms of C L .19 6. derive 'min for M = I.24.16 in terms of K and I'o'al' Assume the CMFB circuit of Fig.5 V power supply voltages. between 0. assume the clamp transistors Q 11 and Q 12 of Fig.1 pF and I pF. assume the current sources biasing the output stages do not change during transients. Assume the nwells of the pchannel transistors are connected to V DD' Derive the lowfrequency gain of the currentfeedback amplifier of Fig.20 6. while Co is the output capacitance. Consider the circuit shown in Fig.24 6. Sketch. P6.21 cascode design.22 6. Ignoring the body effect. Derive the slew rate of the fully differential opamp of Fig.10 Problems 303 6. 6. 6. what Velf bias voltage should be used for the pchanneltransistors to maximize signal swing? What is the maximum singleended signal swing before the gain of the commonmode feedback circuitry goes to zero and why? Repeat Problem 6.21. K. and C p = 0.23 without assuming that the impedance looking into the emitters of Q.
This offset might be on the order of 2 mY to 5 mY for typical MOS processes. where a number of different approaches are discussed. ~ 7. 7.1 has a resolution limited to the inputoffset voltage of the opamp. The main drawback to this approach is the slow response time since the opamp output has to slew a large amount of output voltage and settles too slowly. As we will see in Chapter 13. 7.g<:jnjectiQ. we examine a simplistic approach of using an openloop opamp for a comparator. temporarily ignoring this slow response time. 1975. An alternative architecture that can resolve signals with accuracies much less than the inputoffset voltages of opamps is shown in Fig. A number of other approaches are also described. or to compare the size of one signal to another.. v. 304 .1 A simplistic approach of using an openloop opamp for a comparator. However. and others.1 USING AN OPAMP FOR A COMPARATOR A simplistic approach for realizing a comparator is to use an openloop opamp. such as multiplestage comparators. as we will see. recent examples of both CMOS and pipolar comparator circuits are also described. They also find widespread use in many other applications. A comparator is used to detect whether a signal is greater or smaller than zero. which is inadequate for many applications. we will first investigate another problem due toinputoffset voltage. we look at comparator design and practical limitations. such as data transmission. Although this approach is too slow for practical applications.CHAPTER Comparators Perhaps the second most widely used electronic components (after amplifiers) are comparators.n errors. and fully differential comparators. 1978]. Yee. comparators are used in large abundance in AID converters. In this chapter. First. 7. Finally. The simplistic opamp approach shown in Fig. as shown in Fig.: Fig. Although this circuit has been used many times in early analogtodigital converters. switching power regulators. 7.1. positivefeedback trackandIatch comparators.setvoltage all_d char.2 [McCreary. it is a good example to use when we discuss several design principles for ~~zin~i!'P~t:()ff.
find the maximum clocking rate of the comparator circuit if reset and comparison phases are equal and if six time constants are allowed for settling. a .. 7.. the output of the opamp swings to a large negative voltage. Next. the bottom plate' of the capacitor C (i. If the input signal is greater than zero.2. Therefore..OVout Fig. The circuit of Fig. the reset switch. The opamp is now in an openloop configuration. These two cases are easily resolved and the decision can be stored using a simple digital latch.1 Consider the case in which a 0. the output of the opamp swings to a large positive voltage. where the opamp's output should be 5 V. the output of the opamp is also connected to the inverting input of the opamp by closing switch Sr' Assuming the opamp is ideal. with unityqoin feedback during <1>. At the same time. this connection causes the capacitor to be charged to zero volts.. and the top plate is connected to the inverting input of the opamp. which have finite gains and require compensation to be stable during the reset phase.2 operates as follows: During <p" known as the reset phase. (~'a is a slightly advanced version 'Pt so that chargeinjection effects are reduced.V difference between the cases in which the input signal is either 0. the left side of capacitor C) is connected to ground.e. 7. Solution After the comparison phase. the output of the opamp should have a 5. S" is turned off. Assuming the opamp's unitygain frequency is 10 MHz.2 Cancelling the offset voltage of a comparatorthe comparator here must be stable. during the comparison phase. The bottom plate of a capacitor has significant parasitic capacitance between it and ground.~ of aX /') Bottom plate + >. it is almost always connected to the less sensitive input side rather than to the critical amplifier side (see Chapter 10). The limitations of this approach become apparent when one considers nonideal opamps. 7. However. If the input signal is less than zero.7. .25 mV or 1.5mV signal must be resolved using the circuit shown in Fig.) it is not preferable nowadays. EXAMPLE 7.. and the bottom plate of the capacitor is connected to the input voltage. I Using an Opamp far a Comparator 305 ~'a ~2 Yin C 0 ~. it is a simple example that can be used to illustrate many important design principles.
.. Q. Assuming the reset time is the same as the comparison time. the clock frequency can be no greater than 500 Hz a frequency that is much too slow for most applications.3 The openloop transfer function of the opamp used to realize the comparator.4'. thereby greatly speeding up the opamp during this phase.. as is typical for CMOS. Here.' 2. By assuming that the dominantpole compensation is used to guarantee stability during the reset phase.16 ms (7.5. then analog ground can be considered to be at 2. C e. . it simpiifieJ oparnp"schemailcls"snown m Fig. Using this technique. which disconnects the compensation capacitor. we obtain an openloop transfer function for the opamp similar to that shown in Fig. transistor Q.. During the comparison phase.1) During the comparison phase.V power supplies are being used and that digital output values are the same as the powersupply voltages. If a single power supply voltage of 5 V is used. it is possible to use Phase. is used to achieve lead compensation when it is on during the reset phase.25 mY. <1>. 7. L_L "i~ Frequency fa = 1 kHz 10 MHz Fig.3. Onepossibility for ~ing up the comparison time is to disconnect the compensationcapaciror duri. the opamp gain must be at least 10. 7.5 V.306 Chapter 7 • Comparators IA(w)1 A o = 80 dB 1. In this opamp. the 3dB frequency of the opamp is given by t 3 dB = A = o It I kHz (7.000 YIV. then approximately 1 ms is needed for the comparison phase. the output of the opamp will have a transient response similar to that of a firstorder system that has a time constant given by 't I = .gthe comparison For example.2) 21tt3 dB If six time constants are allowed for settling during the comparison phase.7. This assumes that ±2.'= 0.' As a result.. is turned off.. +0.
Unfortunately. to be described shortly. it is usually possible to tolerate an inverting comparison since it can be made noninverting through the use of a digital inversion somewhere else in the system. To appreciate this cancella . is opencircuited at that time (assuming the parasitic capacitors are ignored).2. In switchedcapacitor comparators. If this is adequate. the topplate voltage follows Vin). This input offset might be caused by device mismatches or might be inherent in the design of the comparator. is never charged or discharged during operation. Specifically.7. and. the clock phasing shown in Fig. One superior aspect of the approach just described is that the input capacitor. Besides. InputOffset Voltage Errors One source of error is due to the inputoffset voltage of the opamp. input offset is not a problem since it is stored across the capacitor during the reset phase. and other approaches. connected to the inverting input of the opamp. If the switches attached to the bottom plate had their phases interchanged. This approach greatly minimizes the charge required from the input when Vin changes. 7. then the approach is reasonable. clock frequencies ten to fifty times greater than would otherwise be the caseperhaps as high as 25 or 50 kHz in our example.2 should be used. C in Fig. thus. this often isn't adequate.4 An opamp that has its compensation capacitor disconnected during the comparison phase. then the comparison operation would be noninverting. we like to use a reasonably large input capacitor to minimize clockfeedthrough effects (described in Section 7.1 Using an Opamp far a Camparatar 307 ~. This charging/discharging requirement puts severe constraints on the input signal source. are necessary.2.2). 7. 7. in phase <1>" C is always charged to 0 V. and the voltage across capacitor C remains at 0 V (in other words. In phase <1>" the top plate. such as that shown in Fig. but now capacitor C must be charged or discharged during the reset phase since the bottom plate follows Vin. 7. Normally. and then the error is cancelled during the comparison phase. whereas the top plate remains at virtual ground. t+o Vout Fig.
during '4>" as shown in Fig.2. This error is due to unwanted charges being injected into the circuit when the transistors tum off. and (b) during the corn parison phase. VoH $. $2 Yin 0 C S.5 The circuit configuration (0) during the reset. Fig.5(0). which can be large in CMOS microcircuits..n + Voff ' which results in the comparator output becoming negative if V. also commonly called clock feedthrough. I Voff + Voff + >. 7. assuming the opamp has an inputoffset voltage given tion. but it also minimizes errors caused by lowfrequency IIf noise.n is less than zero. the switches are normally realized by either nchannel transistors alone or CMOS transmission gates (which consist of nchannel transistors . The right side of the capacitor has a voltage given by V.. $.. + Voff (8) During $2 Yin + . Next. 7.. For the comparator in Fig. C Voff $. then the inverting input of the opamp is at the voltage Voff ... which implies that the input capacitor is charged to Voff during this phase. regardless of the value of Voff ' Not only does this technique eliminate inputoffset voltage errors.n is greater than zero or positive if V.. Assuming the opamp gain is very large.<lV out (b) by V off . assume the opamp has an inputoffset voltage error that is modelled as a voltage source in series with one of the opamp's inputs.. 7. 7.phase. ~+ _ Voff ~ S.. the left side of capacitor C is connected to the input voltage.2 CHARGEINJECTION ERRORS Perhaps the major limitation on the resolution of comparators is due to what is referred to as charge injection..5(b).7..308 Chapter 7 • Comparators During $. The circuit configuration during the reset phase is shown in Fig. .
Also shown in Fig. both of which must tum off). For a transistor in the triode region that has zero V DS • it doesn't matter which junctions are called the drain and the source.L." In the circuit shown. Transistors turned on also have channel charge. .iij.2 ChargeInjection Errors 309 in parallel with pchannel transistors.6 The comparator in Fig. 3. If the clock waveform is very fast. with nehannel switches and overlap parasitic capacitances shown. 7. . 7.. unless Veff is very small) is due to the overlap capacitance between the gate and the junctions.' The channel charge of a transistor that has zero VDS is given by (7. The OCh/2 charge that goes to the output node of the opamp will have very little effect other than causing a temporary glitch. where the switches have been realized as nchanncl transistors. 4.. all transistors are nchannel. 7.. . Finally.2. implying that the channel charge is negative.3) This charge often dominates. C OV1 V' COV3 .L. <1>2 I .. .. which introduces an error.6. for an ncharmel transistor.6 shows the comparator of Fig. Consider first when 0 3 turns off. since both junctions are at the same potential. Since this charge is negative.ugh it is not shown in Fig. I C OV1 . the node .. When MOS switches are on.L. one should remember to include the channel charge dispersion of any transistors that change from being on to off.. Figure 7. 7.. 1987]..'i I.7.. but this does not typically affect circuit performance since the charge comes from lowimpedance nodes. Fig_ 7.6 are jhe parasiticcapacitances due to gatedrain and gatesource overlap capacitors. . the OCh/2 charge that goes to the invertinginput node of the opamp will cause the voltage across C to change. However.. the channel charge due to 0 3 will flow equally out through both junctions [Shieh. they operate in the triode region and have zero volts between their drain and their source. which must flow out from the channel region of the transistor to the drain and the source junctions. The second charge (typically smaller. Transistors also accumulate channel charge when turning on. charge errors occur by two mechanisms.. When MOS switches turn off.. v: t .. The first is due to the channel charge.2. c V" + >"0 Vout Q.
4) since the effective gatesource voltage of 0 3 is given by Veff. 2C (7. !lOC2 !lVout = !lV C2 = . More will be said about this assumption shortly.nCeq = !lV.n = (V DD . (7.The change in V" due to the overlap capacitance is now found to be given by !lV" = (V DD . Ceq. the charge flow into this equivalent capacitor is given by CIC.7) This formula is often useful when calculating charge flow in integrated circuits.n''C I +C 2 All of the charge that flows into Ceq is equal to the charge flow into C I. CIC. = VGS3 .7. This assumes the clock signals change from VDD to Vss . 7. 7.. and !lV.6) = !lV. This situation is shown in Fig. Thus. This formula is used to calculate the voltage change at the internal node of two series capacitors.n = VDD .7. we have C j = C ov.= C.Vs s).n is changing and we want to calculate the change in Vout = Vcz. we have so.. . where it is assumed that V.Vtn)CoxW. The voltage change due to the channel charge is given by L\ V" = = = (V DD . To calculate the change in voltage due to the overlap capacitance. when the voltage at one of the end terminals changes.V.5) When Vi n changes.Vss)Cov Cov+C (7. Fig.8) This change is normally less than that due to the change caused by the channel charge since C ov is small.n . (7.L. given by a. The preceding voltage change in V" is based on the assumption that turns off slightly after 0 3 turns off. = C.V. which is also equal to the charge flow into C.6 to calculate the change in V" due to the overlap capacitance of 0 3 when it turns off.7 A capacitor divider.. C. For this case. it is first necessary to introduce the capacitordivider formula. It can be applied to the circuit of Fig.The series combination of C I and C 2 is equal to a single capacitor. Ceq = C + C I z (7.310 Chapter 7 • Camparators voltage V" will become negative.
~ " . In addition. Thus. . has no effect for a simpler reasonsthe comparison has already been made when it turns off.injection due to Q 3 if we assume that Q 2 turns off slightly after Q 3 does [Haigh.8·sho\vs'iSilltple digital circuit. its charge injection causes a negative glitch at V'. 1980]. a will be advanced slightly (by two inverter delays). '" '2:'~ftYo.5 V. this gives a voltage change in ~V" of ~ V" = 9..8 V. and V55 = 2.2 Chorqelnjection Errors 311 EXAMPLE 7. Later. a do not overlap with <P2 and <P2a' Also. but not insignificant. The argument for this arrangement is slightly complicated. = 10 !lm/0. 1983].5 mV that should be resolved. This result is on the order of 10 times greater than the value of ±2.7 mY. ' whereas the clock voltage of Q 3 is denoted <P'a (<p.6. The total change is found by adding the two effects so that ~V" = 22. the voltage V' will settle to V ln regardless of the previous charge injection of Q.n = 0.5 mV is required from the circuit of Fig. .rtlieother switches. originally developed by ope of the authors [Martin. but it will have much less effect than the charge. (WILl. the voltage V" is unaffected by the charge injection of Q. The following values are given: C = I pF.2 Assume that a resolution of ±2.7. The overlap capacitance is given by C ov = W 3L o vC o . This time difference is the reason why the clock voltage of Q 2 is denoted <p. turns on. Therefore. 7. and <P. Co. compared to <p.6 mY. but goes as follows: When Q 2 turns off.92 fF/(!lm)2. ~~ . = 1. additional measures should be taken to minimize the effects of charge injection if this resolution is required.1 mY.1b.sha[g£ injection oLQ1_aiiit .92 fF. when Q. by turning off <P'. we have ~V" = 13. Lov = 0. that is capable of generating the desired clock waveforms.. advanced). This is not the case if Q 2 is turned off at the same time or before Q 3 is turned off.g. The charge injection of Q. assuming the clocks do not overlap.4). What is the change in ~ V" when Q 3 turns off? Solution Using (7.1 urn. assuming that Q 3 has already turned off... Making ChargeInjection Signal Independent The charge injection due to transistors Q. _. which is smaller than the change due to the channel charge. Clearly. its charge injection has no effect when it turns on because the right side of C is connected to an open circuit at that time. VDD = 2.8).8 urn . Using (7. V.5 V. but this will not cause any change in the charge stored in C since the right side of C is connected to an effective open circuit. 7. In summary. fIg. the voltage at the left of C is unaffected by the charge injection of Q2' and the voltage across C is also unaffected by the charge injection of Q 2 . the circuit is affected on}y)Z:i. = 1. <P..a first. The waveforms <P. and Q 2 may cause temporary glitches. .
Also. Minimizing Errors Due to Charge Injection The simplest way to reduce errors due to charge injection is to use larger capacitors. fully differential comparator is shown in Fig. For our previous example. 7. this large amount of capacitance would require a large amount of silicon area. similar to what is often done for opamps. 7. switchedccpocitor comparator. + Fig. capacitors on the order of about 100 pF guarantee that the clockfeedthrough errors are less than 0. singlestage. . Thus.2.312 Chapter 7 • Camparatars Fig. a bottom plate capacitance of about 20 pF would have to be driven by the iflput circuits.8 A clack generator suitable for generating the desired clock waveforms for the comparator in Fig. when the comparator is taken out of reset mode. 7.5 mY. Unfortunately.9. integrated capacitors have parasitic capacitances between the bottom plate and the substrate that might be about 20 percent of the size of the realized capacitor.9 A fully differential. switchedcapacitor. An alternative approach for minimizing errors due to charge injection is to use fully differential design techniques for comparators. 7. Ideally. which would greatly slow down the circuits. A simple example of a onestage.
drops. The only errors now are due to mismatches in the clock feedthrough of the two switches.IO(b).7. $. <P._. . The clock feedthrough of the second stage can be stored on the coupling capacitors between the second and the third stages. A third alternative that can be used along with fully differential design techniques is to realize a multistage comparator [Poujois. Although this technique is almost always used along with fully differential configurations.10 ate clock waveforms.IO(a). with (hi the cppropri Fig. drops and the switch of the first stage has charge injection. Consider the time when ljl. For this reason. 7. which will typically be at least ten times smaller than in the singleended case. along with the parasitic capacitances of the firststage switch.' vm ~2 C. I ~ . When ljl. 1978. Consider the threestage comparator shown in Fig. where the clock feedthrough of the first stage is stored on coupling capacitors between the first and second stage. Vittoz. 0 1 injects charge into both the inverting input and the output of the first stage through parasitic capacitors C p l and C pb respectively.11 illustrates this case. 1985]. Figure 7. the commonmode voltage may be slightly affected.~. thereby eliminating its effect. along with the appropriate clock waveforms shown in Fig.7.2 ChargeInjection Errors 313 the clock feedthrough of reset switch 0 3 • matches the clock feedthrough of 03b~ In this case." ~2 I I I (b) "I (0) A multistoge comparotor used to eliminote clock feedthrough errors. but the differential input voltage is unaffected. The charge injected at the first stage <P. virtually all modern integrated comparators utilize fully differential design techniques." oJ T ~ ~. and so on. we will explain the technique using singleended configurations. C2 OA1 C3 Vaut  (a)  ~. ~ ~ ~ <Pl' $. 7. for simplicity.
this is the input voltage needed to cancel the effect of the clock feedthrough of the third stage coming out of reset mode).4. Voo = 2. the inputoffset voltage of the first stage was still cancelled by storing it on coupling capacitors between the first and second stage during a reset mode. is charged up to the output error caused by the clock feedthrough of the first stage. = 0.92 fF/(~m)2.10. Therefore.314 Chapter 7 • Comparators :~: ~t·~~c. However. thereby eliminating its effect.' turns off and the second stage goes from closedloop reset mode to openloop comparison mode. C3 + OA1 + :>t~ OA2 Fig. its charge injection is not cancelled. However. The charge injected at the inverting input causes this node to become negative. In a similar manner. . 7.1 urn. EXAMPLE 7.. La. when <il. However. 1978]. at this time.8 urn . The amount by which this node voltage becomes negative is calculated using the analysis method described previously. This approach is described Section 7. when the first stoge is injecting output causes only a temporary glitch there. the second stage is still being reset and C. V" = 0. The first stage of the comparatar in Fig. 7. Q. the error it causes in resolving an input voltage to all three stages is equal to the voltage transition at the inverting input of the third stage divided by the negative of the gains of the first two stages (i.' ~ ~ VDD 'r/~ Negative charge injection C. the first stage was not reset. Finally.8 Y. this amount will be in the range of tens of millivolts. the third stage is still in reset mode and the clock feedthrough of the second stage is stored on coupling capacitor C 3 . and . the output of the first stage becomes positive by anamount equal to the negative transition of the inverting input multiplied by the first stage's gain. After the inverting input becomes negative.e. = 1. assuming that coupling capacitors of around I pF are used.5 Y. transistor sizes are W/L = 10 ~m/0. In any practical case.11 charge. In a variation on this multistage approach [Poujois. <il~' is still high. Co.3 Assume all capacitors are I pF. when the third stage turns off.
= Co.2. . This circuit is a very rough approximation of a multistage comparator when it is not being reset.10) +__. To see why this multistage approach can be fast. What is the inputoffset voltage error caused by the clock feed through of the third stage when the third stage comes out of reset? Solution The values used are identical to those used in Example 7. which is much less than the resolution found in Example 7.9) Thus. which slow down the circuits. uncompensated inverters. especially when it is combined with fully differential circuit design techniques.2 ChargeInjection Errors 315 vss = 2.5 Y. as shown in Fig. The parasitic load capacitance at the output of the ith stage is approximately given by c. Therefore. this approach does have the limitation that it requires multiplephase clock waveforms. or 22.12 =!= by using a cascade of firstorder gain Realizing a comparator stages.7. 7. and each stage has a gain of 20.7 mY = 57 u V AlA? r (7. the equivalent inputoffset voltage is 57 IlY...1 (7.. the charge injection at the inverting input of the third stage is the same as that found in the solution to Example 7.7 mY.c. consider the simplified case of a cascade of firstorder.V In = 22.. However. The input signal that can overcome this 22.2 of 22..e.2. Speed of MultiStage Comparators The approach just described can be used to realize veryhighresolution comparators. each stage consists of a singlestage amplifier that has only a 90° phase shift and therefore does not need compensation capacitors (i.'.12. it can still be reasonably fast because each of the individual stages can be made to operate fast.7.7 mY. Although the multistage approach is limited ill speed due to the need for the signal to propagate through all the stages.. each stage has a 90° phase margin without compensation).7 mY value is given by !J. Typically. + CgS.. Fig._<:>Vout v" oj =.
then the overall transfer function is given by (7. which would normally be due to junction capacitance. then the transfer function of a single stage is approximately given by A.(s) = AD· .16) I P'i + n 51 WP' i Thus.13) where WP'i =A (01_i O. If one assumes the stages are matched. and C gs _i+ ] is the gatesource capacitance of the input transistor of the succeeding stage. (7.(s) =1 + 5 ~) I W =: An a (7.10) will not necessarily be true for the last stage. the unitygain frequency of a single gainstage is on the order of onehalf the unitygain frequency of a single transistor. a cascade of n stages has a time constant approximately given by (7. for the same overall gain. i 2A o _C gs•i !..17) == 2 nAo 't T 9m where '1: r = Cgs/9m is the approximate transit time of a single transistor (i. Thus. I + 51 WP_ i gmi (7. i < C gs . the 3dB frequency of a single stage is on the order of onehalf the unitygain frequency of a transistor divided by the gain of the stage. which is roughly given by 2A o times the transit time of a single transistor.316 Chapter 7 • Comparators where C O. where 9mi is the transconductance of the input capacitor of the i th stage. (7.e. but the load of the last stage should be of the same magnitude.11) 2C gs.. which.15) This result can be approximated by a firstorder transfer function. i + ] since junction capacitances are usually less than gatesource capacitances.14) Thus. This result should be compared to using a single opamp. If one has a cascade of n stages. < 2C gs. the time constant of the cascade of firstorder stages is approximately equal to n times the time constant of a single stage. i (7. then normally C O. implying that one can usually assume c. resulting in Atota. Equation (7. If one assumes the ith stage has a de gain AU• i and that the ith stage is well described by a firstorder transfer function. lover the unitygain frequency of a single transistor). will have a time constant considerably greater than 2 A~ times the transit '[total 2nA oC gs . In other words. i is the output capacitance of the ith stage. The unitygain frequency of a single stage is then on the order of 9mi w" .. where all higherorder terms are ignored...12) or larger.
20) is very useful in quickly accessing the speed and resolution capabilities of a given technology.20). s.1 ns.(W/L) (7. again from Chapter 2. after simple manipulation. EXAMPLE 7.8llm technology that Ao = 20.625 mV. If we assume that 3. n = 3. V eff == 2I D IlnCo. and.8llm technology.17). the general principles apply to more complicated. This corresponds fairly closely to stateoftheart realized comparators in a 0. the widths of the transistors are relatively unimportant. Recall from Chapter 2 that C gs = :3 C o. as Fig.5 V.21) Equation (7.3 latched Comparators 317 time of a single transistor. which corresponds to a clocking frequency of 40.05 M'/V .3 LATCHED COMPARATORS Modern highspeed comparators typically have one or two stages of preamplification followed by a trackandlatch stage. What is the maximum clocking frequency of the comparator? Solution Using (7.7.« (7. arrive at 'total =' 2nA oCgs 9m  ~nAoL2 3 Ilnv. is required for each half period.20) where. First. and that (7. 7.18) for a transistor in the active region. 1985] shows in simplified . . assuming they are large enough so that C gs dominates parasitic capacitances due to interconnect and external loading. and Iln = 0.13 [Yukawa. fully differential stages as long as each stage is first order and doesn't require compensation. It also gives some insight into designing comparators. then a complete period requires 6. W L 2 (7. Second.17) can be simplified further. we have 'total = 4.1 MHz.19) into (7.19) We can substitute (7. Velf = 0. the effective gatesource voltages of input drivers of each stage should be as large as possible. Although the preceding speed estimate is valid for simple singleended stages only.18) and (7.4 Assume for a 0. Equation (7. 7. The resolution is on the order of 5 V I A~ = 0.
this kickback will enter the driving circuitry and cause very large glitches. if very high speed but only moderate resolution is required.1 and 7. if a comparator toggles . perhaps 4 to 10. and. is still much smaller than the voltage levels needed to drive digital circuitry. when positive feedback is enabled. The preamplifier usually does not have gains much greater than 10. Without a preamplifier or buffer.318 Chapter 7 • Campara tors V~ut Preamplifier stage TrackandIatch stage Fig. The rationale behind this architecture is as follows: The preamplifier or preamplifiers are used to obtain higher resolution and to minimize the effects of kickback (which will be explained shortly). is faster than the multistage approach just described. although sometimes it may simply be a unitygain buffer. In highresolution applications.@ckhac"hdenotes the charge transfer either into or out of the inputs when the trackandlatch stage goes from track mode to latch mode. It is not good practice to eliminate "tfie preamplifier altogether since kickback into the driving circuitry will then result in very limited accuracy. especially in the case when the impedances seen looking into the two inputs are not perfectly matched. thus. fonn for a CMOS implementation. This charge transfer is caused by the charge needed to tum the transistors in the positivefeedback circuitry on and by the charge that must be removed to tum transistors in the tracking circuitry off. The positive feedback regenerates the analog signal into a fullscale digital signal.2. even when good resolution is needed. and then amplifies it again during the latchphase. although larger than the comparator input. For example. The output of the preamplifier. The trackandlatch stage then amplifies this signal further during the track phase.7. in a manner similar to that described in Sections 7.13 A typical architecture for a highspeed comparator. The preamplifier typically has some gain. One very important consideration for comparators is to ensure that no memory is transferred from one decision cycle to the next. The trackandlatch stage minimizes the total number of gain stages required. otherwise its time constant is too large and its speed is limited. capacitive coupling and reset switches are also typically included to eliminate any inputoffsetvoltage and clockfeedthrough errors.
can be found by analyzing a simplified circuit consisting of two backtoback inverters. such as those shown in Fig.':'.15 A linearized model of the trockcndlctch stage when it is in its latch phase. latch) phase. For this linearized model. especially in track mode. then each of the inverters can be modelled as a voltagecontrolled current source driving an RC load. which speeds up operation when the comparator resolves small input signals. The circuitry shown in Fig. 7.14 Twa becktobock inverters used as a simplified model of a trackandlatch stage in its latch phase. where Av is the lowfrequency gain of each inverter. 7.e. V AV RL y '±\ II ~ CL RL 1+  v. For example. it might have a tendency to stay in that direction.22) V.':' l~g§ otherwise the time constants are too large. LatchMode Time Constant The time constant of the latch. Fig. 7. The trackandlatch stage has many variations. which has a transconductance given by G m = Av/R L . we have (7.13 has internal nodes of the latch reset to both Voo and ground when the Vtlch signal is low.3 Latched Comparators 319 in one direction. and that the inverters are in their linear range.14.~_t. 7. although it will suffice in many applications. which limits the speed.13 should be considered only symbolic.. Another consideration for comparators is that the gain ~ho~~_not ~.15. 7. when it is in its positivefeedback (i.7. one can reset the different stages before entering track mode. If we assume that the output voltages of the inverters are close to each other at the beginning of the latch phase. . Not only does this eliminate memory. This tendency is sometimes called hysteresis. the comparator shown in Fig. In order to eliminate it.7. but it also sets the comparator to its trip point. as shown in Fig. = z e Fig. This might be achieved by connecting internal nodes to one of the power supplies or by connecting differential nodes together using switches before entering track mode.
26) is a firstorder differential equation with no forcing function. the voltage difference increases exponentially in time with a time constant given by r '<teh = RlC l Cl m A v  I := .Va is the initial voltage difference at the beginning of the latch phase. Voe(A. Note that 'Itch is roughly equal to the inverse of the unitygain frequency of each inverter.23) by R l and rearranging gives T[dV (7.28) gives '<teh = . Note that (7. = R l C l is the time constant at the output node of each inverter.30) where K.22) and (7.28) where..I dt !'.25) from (7. Substituting (7.31) where KJ might be between 2 and 4.30) into (7. (7. (7. Equation (7.320 Chapter 7 • Comparators and ~> = _Cl(d~y)_(~:) Multiplying (7.V = Vx.  !'. In the case of MOS devices. V = !'.5 and I.24) and y) r (dV + Vy = AvV x Cit .27) where!'. G m = Av/R l is the transconductance of each inverter.31) implies that '<teh depends primarily on the technology and not on the design (assuming a reasonable design is used . Also.25) where.29) and (7. Thus.26) where !'.. or specifically.. (7. Its solution is given by ()If. normally the output load is proportional to the gatesource capacitance of a single transistor.Vy is the voltage difference between the output voltages of the inverters. K] is a proportionality constant between I and 2. = G (7.= K J  K. the inverter transconductance is proportional to the transconductance of a single transistor.29) Here. and is given by (7.24) and rearranging terms gives '_)(d )_ [_ tN Av . again.23) Cit x) +V x = AvVy (7.. Subtracting (7...:. L' L'  K'~nVeff ~nVeff (7. might be between 0.V (7.
5. The literature on integrated circuit technology has many examples of latched comparators.5 Assume for a 0. For example. This comparator has the positive feedback of the second stage always enabled.7. 7. 1990]. Sometimes. Vo is small. For a given technology. when the two diodeconnected transistors of the gain stage are enabled. L'. it is possible that circuit noise can cause the initial voltage difference to become small enough to cause metastability.V'og.5 ORz. 7. The combination of the diodeconnected transistors of the gain stage and the transistors of the .32).ln = 0. Note also the similarity between (7.68 ns. and the circuit is stable. In other words.20). V'og.34 ns. the gain around the positivefeedback loop is less than one. Fig.31) and (7. and J. the equation for the time constant of a cascade of gain stages.5 V.16 shows a comparator presented in [Song.05 M2/V~ s. perhaps larger than the allowed time for the latch phase.32) If L'. this latch time can be large. we have T lle h = 0.lm technology that K3 = 2.31) is very useful in determining a rough estimate for the maximum clock frequency of a latchandtrack comparator. Such an occurrence is often referred to as metastability. the maximum clock rate would probably be limited by the frequency response of the preamplifiers and the trackandlatch during the track phase. (7. In a typical comparator. which corresponds to a clocking frequency of 1. Veil = 0. then. Assuming this is half the total period (which might be quite an optimistic assumption).V o = IO mY.4 EXAMPLES OF CMOS AND BiCMOS COMPARATORS This section describes a number of highspeed comparators that are currently popular.27).e = 2 V. What is the maximum clocking frequency of the comparator? Solution Using (7. L'. even when the initial voltage difference is large enough. the differential output voltage of the latch does not increase enough to be recognized as the correct logic value by succeeding circuitry.e to be obtained in order for succeeding logic circuitry to safely recognize the correct output value. rather than by the speed of the latch during the latch phase.4 Examples af CMOS and BiCMOS Comparators 321 that maximizes Veil and minimizes C L ) . the smallest possible period for a trackandlatch might be 0. EXAMPLE 7. If it is necessary for a voltage difference of L'. by using (7. because its initial value is too small.8J. we find the time necessary for this to happen is given by (7. In track mode.
A third comparator was designed. while still buffering the kickback from the input circuitry. thereby keeping all node time constants small and giving fast operation. which allows for input signals that have large commonmode signals. preamplifier and a positivefeedback trackand positivefeedback loop acts as a moderately large impedance and gives gain from the preamplifier stage to the trackandlatch stage.: Preamp Gain stage 0 Positive feedback Fig.322 Choprer 7 • Comparators +<> + v. with appropriate clock waveforms shown in Fig. 7. the linearity of the commonmode feedback circuitry is noncritical since. in fully differential comparators. the positivefeedback stage is precharged low. This design also uses precharging to eliminate any memory from the previous decision.16 A twastage comparator thor has latch stage. and characterized by K.18. 7. fabricated. there is no ambiguity in resolving the sign of the input signal. J 7 [Norsworthy. A second comparator is shown in Fig.7. For example. 1989]. Measured (but . Unlike in fully differential opamps. This design eliminates any inputoffset voltages from both the first and second stages by using capacitive coupling.19. Martin in 1984 (unpublished) and is shown in Fig. The diodeconnected loads of the preamplifier stage give a limited amount of gain in order to maximize speed. whereas the digitalrestoration stage is precharged high. This design also uses diodeconnected loads to keep all nodes at relatively low impedance (similar to currentmode circuitdesign techniques). whenever large signals are present (and the commonmode feedback circuitry becomes nonlinear). somewhat similar to what is done in Domino CMOS logic [Krambeck. It also has commonmode feedback circuitry for the first preamplifier stage. This allows a simple differential pair to be used for CMFB circuitry. 7. 1982J.
is described in [Razavi. + +01 Digital signallevel restoration Latch 01El j' Positive feedback Fig.7.7. then the effect of the clock feedthrough of 8. 1992]. the inputoffset errors of the first stage can still be eliminated by resetting the right side of the coupling capacitors between the first stage and the second stage. In the realization described in [Razavi. This stores any offset voltages of the first stage on the capacitors. The performance measured was limited by the test setup rather than by the circuitry. 7. 1992]. It is based on the idea that it is not necessary to reset the first stage.20. the inputs to the preamplifier are connected directly to ground (or to a reference voltage). 1985]. despite a very old 5~m technology. [Vittoz. assuming that the gain of the first stage is not too large [Poujois. unpublished) performance of this circuit resulted in a O.4 Examples of CMOS and BiCMOS Comparators 323 Latch 01 +0 v. A simplified schematic of this comparator is shown in Fig. A fourth comparator that is realized in a BiCMOS technology and that exhibits very good performance. on the input resolution is divided by the gain of the first stage. During the reset phase.17 A twostage comparator. 1978].ImV resolution at a 2MHz clock frequency. this comparator is one of the better BiCMOS designs to date. and 8. When the comparator is taken out of reset phase. Indeed. and the outputs of the coupling capacitors are connected to ground as well. the first stage is a BiCMOS .
G. Note also that the switches are realized using pchannel transistors. consisting of MOS source followers followed by a bipolar differential amplifier and emitterfollower output buffers. is discharged to the minus supply through Mil' and X2 and Y2 are discharged to .22. preamplifier. along with positive feedback for fast operation. 7.324 Chapter 7 • Comparators Firststage cammonmade feedback First switchedcapacitor gain stage Second gain stage C'A C'A Positive feedback stage Fig. Notice that the circuit operates between ground and a negative voltage supply. The trackandlatch stage has both a bipolar latch and a CMOS latch. 7. as shown in Fig.18 A twostage comparator with capacitive coupling to eliminate lnputojlset voltage and clockfeedthraugh errors. is low and <1>2 is high. X 1 and Y 1 are connected to ground through switches M 1 and M 2. <1>.21. 7. as shown in Fig. During the reset phase.
jl Fig.7.7. 7. 1992]. . + v.4 Examples of CMOS and BiCMOS Comparators 325 Fig.: Fig.1 B.21 A BiCMOS preamplifier.20 A simplified schematic of the comparator described in [Razavi.19 The clack waveforms required by the comparatar in Fig. 7.7.
22 The BiCMOS trackandIatch stage in [Razavi. After a short delay. Also described in [Razavi. Next. is about onefifth the size of C I and C 2 . 1992]. and low power. The offset of this bipolar latch is quite small. at this time. since C. InpuHransistor Charge Trapping When realizing very accurate CMOS comparators. which turns on M 12 ' thereby activating the positive feedback action of Q s and Q6' This develops a differential voltage between XI and Y I of about 200 mY. which is needed for the transient response of the preamplifier. the minus supply through M9 and M 10' Also. and M6 are to prevent nodes XI and Y I from being discharged very far from ground toward the minus power supply and at the same time to amplify the 200mV difference signal developed by the bipolar latch to almost a fulllevel CMOS voltage change. 1992] is an interesting CMOSonly comparator. M 3 and M 4 are off. but which interested readers may investigate. when activated. an error mechanism that must be considered is charge trapping in the gate oxide of the input transistors of the MOS . the only power dissipated is that required to charge C 3there is no de power dissipation. which activates the CMOS part of the latch consisting of crosscoupled M. changes state. Also note that. the latch is accurate. Thus. which is not described here. and M6 and crosscoupled M 7 and M 8. The reasons for including crosscoupled M. which leaves XI and Y I floating and connects the outputs of the preamplifier to its input signal.7. relatively fast. <il2 becomes low. A short time after the bipolar latch is activated. the inverter connected to C. This low voltage turns on M3 and M4 . <ill becomes high. and its output voltage will drop. typically on the order of one millivolt or less.326 Chapter 7 • Comparators Fig.
When n channel transistors are stressed with large positive gate voltages. This effect correlates well with transistor l/f noise and is much smaller in p channel transistors..23 A comparator with little hysteresis. or in addition.1 to I mY. 1993]...to preventtrapping. the effective transistor threshold voltage is increased. are trapped. Alternatively. An alternative approach is to flush the input transistors after each use where the junctions and wells of nchannel transistors are connected to a positive power supply whereas the gates are connected to a negative power supply." Also. electrons can become trapped via a tunneling mechanism in which electrons tunnel to oxide traps close to the cOnduction band. pchannel transistors exhibit [rapping for positive gate voltages since only electrons. Therefore. is described in [Miller. This effectively eliminates the trapped electrons [Swanson. (Hysteresis is caused by charge trapping. One possible means of minimizing this effect. 7.. by using pchannel input transistors.... The time constant for the release of these trapped electrons is on the order of milliseconds and is much longer than the time it takes for them to become trapped. they should never be turned off. .currents s: pchannel inputs with small hysteresis Fig. assuming we have a BiCMOS technology. and not holes. 1989]. This leads to a comparator hysteresis on the order of 0.4 Examples of CMOS and BiCMOS Comparators 327 Small bias . two input stages can be used for the comparatora rough stage can be used during times when 5. charge trapping must be considered and minimized..23.. which allows the inclusion of two additional smallcurrent sources in the input stage. this guarantees that the pchannel input transistors never tum off. 1990] and is illustrated in Fig. 7. During the time they are trapped. the charge trapping is greatly minimized because pchannel transistors exhibit much less hysteresis than nchannel transistors.7.) comparators [Tewksbury. A BiCMOS technology allows diodes to be used in the input stage. When very accurate comparators are needed...
1988]. Besides increasing the resolution. 7. The preamplifier is a simple differential amplifier that might have a gain of around 5. During track phase. The trackandIatch stage is very similar to a currentmode digital latch. 1993. The outputs of the third differential pair are connected back to the highimpedance output nodes in a crosscoupled manner so that positive feedback results.4 and 0. . 1990]. this preamplifier helps to eliminate kickback from the trackandIatch stage. 12 is diverted to the differential pair consisting of A. When latch mode is enabled.24 [Wakimoto.6 V (depending on the logic levels being used). and 0 6 . where preamplifier and trackandIatch stages are used. 7. The inputs to this third differential pair come from the outputs of the second differential pair through emitterfollower buffers consisting of 0 9 and OJO.' Preamplifier TrackandIatch stage Fig.5 EXAMPLES OF BIPOLAR COMPARATORS Highspeed bipolar comparators are typically latched comparators. Tan... There are two reasons for using the emitterfollower buffers. A typical example is shown in Fig. These buffers isolate the '. When this positive feedback is enabled. as shown previously in Fig. the differential pair consisting of transistors 0 3 and 0 4 is enabled and operates as a second differential amplifier.24 A typical bipolar comparator. 7.328 Chapter 7 • Comparators large signals with overloads are possible.13. 7. whereas a fine stage can be used during times when accurate comparisons are necessary and it can be guaranteed that no large signals are present [Swanson. it takes the initiallysmall differential voltage and quickly amplifies it to between 0.
This resistor prevents the cascode transistors from turning off completely during the latch phase. which speeds this loop up and eliminates the need for emitterfollower buffers in the loop. Finally.7. a cascode commonbase stage is added just below the output voltages. This stage is used to isolate the outputs from the positivefeedback loop. and therefore the comparator operates as a cascode amplifier during this phase. In this comparator. When the comparator goes into latch mode. the input signals go to a differential pair that is always turned on (even during the latch phase). it is used as an example to illustrate many comparator design principles. This in turn allows for much smaller resistors to be used in the positivefeedback loop. They also isolate the same high impedance nodes from the output load capacitance. Also. 7. a] and 0 4 are on. the kickback from them is greatly reduced without adding additional preamplifier stages. a larger resistor is added between the emitters of the cascode transistors.25 [Van de Plassche. the collector current from the input transistors is redirected from the commonbase transistors to transistors and which are connected in a positivefeedback loop. a. 1988]. A small current source is added to the tracking differential pair so that this differential pair doesn't turn off completely when the comparator is in hold mode. . This maximizes the bandwidth during the tracking phase. During the track phase.5 Examples of Bipolar Comparators 329 highimpedance nodes at the collectors of the second and third differential pairs from the baseemitter capacitances of the third differential pair. Although this comparator has never been experimentally tested. A third bipolar comparator is shown in Fig. a" Fig.7. Since the bias current of the input transistors is never turned off. This makes the comparator faster when it goes from hold mode into track mode.25 A second bipolar comparotor. Another architecture for a bipolar comparator is shown in Fig. They operate as commonbase transistors.26. 7. which also speeds up the transition from latch mode to tracking mode.
. June 1983." IEEE J. H. "New ClockFeedthrough Cancellation Technique for Analog MOS Switched Capacitor. pp. 104106. pp. "A LowDrift Fully Integrated MOSFET Operational Amplifier. Singh. S. S. SolidState Circuits Conf. S.330 Chapter 7 • Comporotors Moderately small resistors ~ . _ _ _. L. Timko. Nestler. Ternes. February 1990. 17." IEEE J. Vol. 499503. Haigh and B. Vol. 3. 237244." Electron. Symp. 614619. pp. 2."' Cascode stage Larger resistor to prevent transistor turning off Preamp or buffer Small bias current to prevent transistors turning off Fig. McCreary and P. SC22. C. Law. "A 14bit 80KHz SigmaDelta AID Converter: Modeling. 168169. Fetterman. M. "A Switching Scheme for SwitchedCapacitor Filters. S.6 REFERENCES D. Borel. Martin. 256267. "HighSpeed Compact Circuits with CMOS. Lee. of SolidState Circuits. IEEE Int. Post. Ferguson.26 / A third bipolar comparator. I. 371379. 1992. SC13. K. no. April 1989. L. pp. 4. Vol. . no. Design. 18. G. and P. "Improved Circuits for the Realization of SwitchedCapacitor Filters. Norsworthy. "An 18b 1Olls SelfCalibrating ADC. CAS27." IEEE Intern. "IEEE J." IEEE J. 2. and G. Circuits and Systems. Y. Lee. Krambeck. E. G. of SolidState Circuits. R. pp. "A Differential SwitchedCapacitor Amplifier. Poujois and J. K. Vol. Martin. of SolidState Circuits. pp. 7." IEEE Trans. SC1O. no. pp. and Performance Evaluation.. February 1987. pp. no.7. April 1980. on Circuits and Systems. Mueck. 24. H. "AllMOS Charge Redistribution AnalogtoDigital Conversion TechniquesPart I. L. C. Vol. June 1982. Vol. Lee. and H. Vol. Which Reduces Effect of Parasitic Capacitances Associated with Control Terminals. R." Proc. 1. 586589. August 1978. Lett . R. Gray. no. and S. Miller. Ozcolak." IEEE J. M. of SolidState Circuits. of SolidState Circuits. December 1975.
13281338. Song. December 1992. June 1978. Swanson.4 x 10 pF/(~m) 4 C jsw = 2. IEEE Press." IEEE J. B.9 X 10. Tompsett." IEEE J. 6. Akazawa. Van de Plassche and P. "Method and Circuitry of Decreasing the Recovery Time of a MOS Differential Voltage Comparator. 3. Englewood Cliffs. Assume $Ia drops before $1 drops. and B. Vol. September 1993.247.9 x 10~ pF/(~m) 2 4 CgS(Overlap) = Cgd(OVenaPI = 2. Wakimoto. Vol. no. 23. April 1989. "A lmV MOS Comparator. 542543.0x 10 pF/~m 3 Cox = 1.pF/(~m)2 Cgs(OVenaPI I/ 2 = Cgd(OVenaP) = 2. Razavi. "Dynamic Analog Techniques. no. afSolidState Circuits. Vol. pp. R. December 1990. E. 13181327. of SolidState Circuits.9 Y Y = 0. T. "A CMOS 8bir HighSpeed AID Converter. A. Vee. of SolidState Circuits. S.8 Y Y = 0. pp. T. 5. 23. et al. "The Effects of Oxide Traps on the LargeSignal Transient Response of Analog MOS Circuits. no. 2. no.pF /~m 7. Piscataway. Shieh." IEEE J. of SolidState Circuits." IEEE J.7 PROBLEMS Unless otherwise stated. December 1990. M.0 X 104 pF/~m • pchannel MOS transistors: ~pCox = 30 ~A/y2 VIp = 0. of SoltdState Circuits. VoL 27. 6.8 v'? r ds (n) = 12. SC13. December 1988. so that only the charge injection from OJ need be considered. Antognetti. Vol. L." IEEE J." IEEE J. of SolidState Circuits. no.S. and G. E. 6. and L. P7. Y. no. of SolidState Circuits. "ErrorCorrection Techniques for HighPerformance Differential AID Converters.000 L (~m)/ID (rnA) in active region 4 2 C j = 4. pp. 7.0 X 10." U. 13341344. Vol. 24. "An 8bit looMHz FullNyquist AnalogtoDigital Converter. "Design Techniques for HighSpeed.5 x 10 pF/(~m) 4 C i sw = 2. J. Vol. B. Wooley. Lee." in Design of MOS VLSI Circuits for Telecommunications. June 1985. pp. L. pp. pp. 19161926.210. 13451350. 25. S. as shown in Fig. M." IEEE J. of SolidState Circuits. pp. Heller. no. Principles of Data Conversion System Design. December 1988. Prentice Hall. S. New Jersey. Sheu. 6. pp. of SolidState Circuits. pp. H. New Jersey. 25." IEEE 1. Tan. Vol.7. J. Yubawa. L. Tsividis and P.1. 1985." IEEE J. 12. "Measurement and Analysis of Charge Injection in MOS Analog Switches.5 y rds (n) = 8000 L (~m)/ID (rnA) in active region 4 2 Cj = 2. Y. and S. 294297. H. Miller. Vittoz. 1995. Terman. 2. "A lOb 15MHz CMOS Recycling TwoStep AID Converter. A. K. April 1987. Razavi and B. Y. SC20. Konaka. Patil. 775779.1 A simple CMOS inverter is used as a comparator. Tewksbury. assume the following: • n channel MOS transistors: 2 ~nCox = 92 ~A/Y V l n = 0. Baltus. ed. Lee. no. What is the change in V cut due to this charge injection? . 22. HighResolution Comparators.5 x 10 pF/~m Cox = 1. "Si Bipolar 2GHz 6bit Flash AID Conversion LSI. and M.7 Problems 331 B. patent no. Vol. G. 277281.
2 7. What is the inputvoltage offset error due to the charge injection of the reset switch of the last stage only? Estimate the time constant for the inverter used in Problem 7.. Show that the overall inputreferred clock feedthrough is given by IVerr .4 7.6 7.5 V. Assume opamps are offset free and that they remain in their linear region after their reset switch is opened.1 during its reset phase and also during its comparison phase. and that all transistor lengths are 0.8 urn.3 7. P7. <P~.. and that there are only nchannel transistors in the signal path... <p~".4 where offsets of the opamps are not ignored. iln = 0.5 7.c V out 30~m z 5 urn Fig. 7. and ignore overlap capacitance. Give reasonable device widths of the comparator in Fig.5 V (i. 7. is the error due to the reset switch of the ith opamp. each having a gain of IS.:"'''+.1 are cascaded as shown in Fig. .05 M2 IV .16 so that the first stage has a gain of 5 and so that the latchandtrack stage has a gain of 10 when . W 5/W 4 = iln/ilp).10.u: 0 92 urn sv 5 L.25 V. is the input and Verr.! 7.. Do not ignore the body effect on the threshold voltage of Q I .7 Assume that three stages of inverters identical to the inverter used in Problem 7. For the circuit shown in Fig. Further assume that a comparator is realized by a cascade of three stages. If three time constants are required for settling during the openloop comparison phase.e..332 Chapter 7 • Comparators Assume the transistors in the inverter have sizes chosen such that the inverter threshold voltage is at V DD/2 = 2.. find the voltages at each of the opamp inputs at the end of <p. what is the maximum frequency of operation for the comparator? What is the resolution? You may assume that Vett = 0. 7.10. What is the inputreferred offset and clock feedthrough? Assume a MOS transistor's unitygain frequency is approximately given by ro u = gm/Cgs' Find an expression for rot in terms of Vett and Cox' Assume a single gain stage without compensation has a unitygain frequency given by rot = ro u / 2 . Also assume the inverter gain is 24 at Vout = 2. s . <PI' and <P2' where V. 31I (AIA2 ) · Repeat Problem 7.
The WfL of the nchannel is 5 /.lm wide and that the bias current of the first stage is 0.4 V across them? You may assume that for the bipolar transistors V CEsat = 0.8 urn and the WfL of the pchannel is 15 /. The CMOS transmission gate shown has an input voltage of 2.7. how long would it take the differential output voltage to change by 50 mV? Consider the comparator in Fig.11 Fig. If the differential output voltage is 50 mVat the beginning of the latch phase.5 V when it turns off.1 rnA.7.8 Assume the comparator of Fig. Estimate the change in output voltage due to charge injection. 7.!! . 7.9 7. Assume the total parasitic capacitance between the output node and ground is 50 fF. 7. Also ignore changes due to overlap capacitance.lm/O.16 with the device sizes found in Problem 7. P7.7 Problems 333 in track mode and a loop gain of 4 when in latch mode.10 7. Estimate the equivalent time constant of the latchandtrack stage when the comparator is in latch mode.lm/O. If the input signal changes from 0 to 5 mV at time 0.3 V. 7.7. and that the clock signals change very fast.8 urn.16 has the device sizes found in Problem 7. how long would it take for the output voltage to change to a differential voltage of 2 VO What is the minimum powersupply voltage that can be used for the comparator in Fig. What will the final output voltage be? 7. Assume the input transistors are 25/. V DD = 5 V.25 if the current source and the resistive loads both require 0. Estimate the equivalent time constant when the comparator is in track mode.
The first of these parameters is a sampling pedestal or a hold step. the use of a sample and hold (at the front of the data converter) can greatly minimize errors due to slightly different delay times in the internal operation of the converter. Finally. some common analog building blocks are described other than those already presented. A translinear gain cell is commonly used to create an amplifier whose gain can be adjusted through the use of a controlling input current.CHAPTER Sample and Holds. A sample and hold (SIB) is used to sample an analog signal and to store its value for some length of time. Perhaps more importantly. this error should be as small as possible. is the sampleandholdcircuit. A bandgap voltage reference is often used to bias circuits or to supply a reference to which other voltages are compared. Before discussing the basic principles of sampleandhold circuits. especially in dataconverter systems. This is an error that occurs each time a sample and hold goes from sample mode to hold mode. 334 . otherwise it can introduce nonlinear distortion. 8. there is always a small error in the voltage being held that makes it different from the input voltage at the time of sampling. and Translinear Circuits In this chapter. a translinear multiplier is realized by interconnecting two gain cells and finds a variety of uses in applications such as a modulator (in a communication system) or a phase detector (in a phaselocked loop). this error should be signal independent. bandgap voltage references. Obviously. Specifically. it is worthwhile to mention that sampleandhold circuits are also often referred to as "trackandhold" circuits. Voltage References.1 PERFORMANCE OF SAMPLEANDHOLD CIRCUITS An important analog building block. and translinear gain cells and multipliers are discussed. Normally. circuits to realize sample and holds. it is necessary to mention some performance parameters used in characterization. these two terms are synonymous except for a few particular switchedcapacitor sampleandhold circuits that do not have a phase where the output signal is tracking the input signal. During this change in operation. Before proceeding. 1. In many cases. Sampleandhold circuits are necessary components in many dataacquisition systems such as AID converters.
A fifth limitation is aperture jitter or aperture uncertainty.1 Performonce of SompleondHold Circuits 335 2. Some of the mechanisms whereby these errors arise in particular sample and holds are described in the next section using specific SIH examples. Other performance parameters are also important when realizing sample and holds.2. These include parameters such as dynamic range. a sample and hold will have both smallsignal and largesignal limitations due to its 3dB bandwidth and finite slew rate. gain. when in sample mode. referred to as the beat test. caused by effects such as leakage currents due to the finite base currents of bipolar transistors and reversebiased junctions. the output voltage will no longer be affected by changes in the input voltage. it is appropriate to first describe a popular method for testing SlHs. S. Both the 3dB bandwidth and slew rate should be maximized for highspeed operation.8. this droop rate is so small it can often be ignored. a number of design principles whereby these errors can be minimized are explained. Example waveforms for the input signal. Testing Sample and Holds Before describing various SIH architectures. In welldesigned sample and holds. 3. when in hold mode. usually through parasitic capacitive coupling from the input to the output. Specifically.' The output of this system is demodulated to a low frequency equal to the difference between the frequency of the clock signal and that of the input signal. the input signal changes rapidly. In addition.1. a track and hold. In reality. 8. A third important parameter is the speed at which a sample and hold can track an input signal. then the output of the track and hold would be resampled by a second track and hold clocked on the opposite phase as the original. This test consists of clocking the SIH at its maximum clock frequency and applying a sinusoidal input signal that has a frequency slightly different than the clock frequency. Yet another limitation (somewhat less important in highspeed designs) is the droop rate in hold mode. Another parameter is a measure of how isolated the sampled signal is from the input signal during hold mode. Ideally. and the output signal of the sample and hold are shown in Fig. The test setup for a beat test is shown in Fig. in fact. linearity. there is always some signal feedthrough. the sampling signal. This error is the result of the effective sampling time changing from one sampling instance to the next and becomes more pronounced for highspeed signals. This lowfrequency signal is then characterized using a spectrum analyzer or by digitizing it using a highaccuracy AID converter clocked at the difference frequency and then analyzed using a computer. . and offset error. 1. 8. If the circuit being tested is. 4. this signal feedthrough can be greatly minimized. respectively. In this mode. In most CMOS designs. when highspeed signals are being sampled. This error is a slow change in output voltage. resulting in small amounts of aperture uncertainty causing the held voltage to be significantly different from the ideal held voltage.
When <1>Clk goes low.. but now the output of the AID converter would be loaded into the computer at a sampling rate equal to the beat frequency. and Translinear Circuits .8. If a computer is used for analysis. Voltage References.. Example waveforms for the test setup of Fig. the signal would normally be curvefitted to a sinusoidal wave at the beat (i. difference) frequency.f)t] ~ S/H elk b 4>smpl 4 AID and computer Sampling signal with sampling frequency f.2 /: . Output signal of sample and hold Input signal Sampling signal Fig. 8. It might be mentioned that a very similar test setup can be used for analogtodigital converters. This ideal closestfit sinusoid would then be subtracted from the measured signal. V' will ideally stay constant from then on. 8..2 MOS SAMPLEANDHOLD BASICS Perhaps the simplest sample and hold that can be realized using a CMOS technology is shown in Fig.3... 8.1 The test setup far characterizing a sample and hold using a beat test.mpi Fig.e. V' follows V in. Yin Spectrum analyzer = A in Sin[21t(f smp1+ h.1. having a value equal to Vin at the instance <1>Clk . and the error signal would be analyzed for RMS content and spectral components using a fastFourier transform.336 Chapter 8 • Sample and Holds. When <1>CIk is high. B.
. Vi' this result assumes that the clock signal.1 L+_l 0.e. If clock <l>CIk turns off fast. the negative charge that goes to the node with Chid connected to it (i..8.8).8. Unfortunately. It should be noted here that Yefl.Hold Basics 337 Vi. node y') will cause a negative voltage change that is long lasting (until the next time 0 1 turns on again). resulting in a t.3 An openloop track and hald realized using MOS technalagy.1 2 (8. will flow equally into both junctions [Shieh. o. = CoxWLYefl_1 Chid zc.I is given by (8. However.(Y DD .2 $clk MOS Sornpleond.. 2C hld  Vi') (8. However. which is nonlinearly related to the input signal. Y' will have a negative going hold step at this time caused by the channel charge of 0 1. went low. If one assumes the source impedance at the node Vi' is very low. 1 = YGSIY" Here.Y i . 1987] since the channel becomes pinched off at both ends (i. When 0 1 turns off. goes between Y DD and the most negative voltage in the circuit. The change in the voltage Y' is found by using the relationship = CY. we have t. This nonlinear relationship with Vi' results in distortion for the overall sampleandhold circuit. Using a derivation similar to that used to find (7. The charge flowing to the junction labelled Y' is therefore given by 0CH 2 = CoxWLYefl. next to the junctions) while the charge is flowing out to the two junctions. 0CH.e. then the glitch at this node will be small and have a very short duration. <l>clk. then the channel charge.4) .2) = YDDY.. >OVout Fig.3) Notice that t. Y' '" CoxWLo. Y' is linearly related to Vi"~ which results in a gain error for the overall sampleandhold circuit. it will cause the junction voltages to have negative glitches. t. Since this charge is negative. more importantly. Vi"~ due to variations in the sourcesubstrate voltage (assuming the substrate is tied to one of the voltage rails). is the input voltage at the instance a I turns off. = CoxWL(Y DD. its channel charge must flow out from under its gate into its junctions. There is also an additional change in Y' due to the gate overlap capacitance.Yss) Chid (8.YI .1) where Yefl. Y' = t. Y' is also linearly related to Ytn.° C h1 d .
The average offset is given by Vottsetavo = L'.3). and (W IL). these conditions are seldom possible to achieve in practice.. ¢lclk I Chid . Unfortunately.5 V and the input signal is I V peak to peak.lm/0. and Translinear Circuits where V88 is the most negative voltage in the circuit. Voltage References. and appears simply as an offset since it is signal independent.V'(l V) = 10. This component is usually smaller than that due to the channel charge.. This result is somewhat true when V in is in the middle region between the power supplies. G>CIk' is relatively noise free.V'(1 V)+L'. it is seen (as is explained shortly) that the Vin o~ 0. EXAMPLE 8. When the finite slopes of the clock waveforms are taken into account. it may cause noise problems if care is not taken to ensure that the clock signal. Find the hold step for V in equal to I V.. One approach is to replace the nchannel switch by a CMOS transmission gate.8 V. However. as shown in Fig.V'(l V) = 2. and then repeat for V in equal to I V.69 mY.3). Solution At V in = I V. 8.= 6.1 Consider the sample and hold of Fig.4. assuming the clock waveforms are fast and exactly complementary.5) which is a reasonable estimate of the amount of de offset injected in this example. using (8. For example.26 mY. V'n = 0. Use the estimates for errors at ± I V to estimate the de offset.92 fF/{J.1 ><l v.48 mV (8. At V in = I V. we find L'.8. = (5 I.: Fig. 8. if the clock signal has powersupply noise on it due to being realized with a simple inverter tied to digital power supplies.338 Chapter 8 • Sample and Holds. Therefore.lm)2. again using (8. we find L'. There have been a number of changes proposed to minimize the signaldependent hold step. Assume the power supply voltages are ±2. then the charge injection due to each transistor will cancel when the transmission gate turns off.3 with Chid = I pF. the powersupply rejection ratio of this circuit might be poor.V'(I V) 2 . this error component is not typically important since signalindependent offsets can often be removed in most systems.4 An openloop track and hold reo]ized using a CMOS transmission gate. Cox = 1.8 urn). The idea behind this approach is that if the size of the pchannel transistor is taken the same as the nchannel transistor.. I.
this technique usually can minimize the hold pedestal to less than about onefifth the value it would have without it.. Another modification.. When the ideal ratio is not onehalf..j >0 V out Fig. Seldom will these two effects have the same magnitude in practice. ... when Vin is closer to V DD.6 The clock waveforms for V in and tPclk used to illustrate how a finite slope for the sampling clock introduces samplingtime jitter. . In practice. often proposed to minimize clockfeedthrough errors. Even if we ignore the errors caused by nonperfect clock waveforms. it is necessary a. tumoff times of the transistors are signal dependent and this signal dependence causes the nchannel transistor to tum off at different times than the pchannel transistor..8. a" Sampling jitter Fig. However.. then the charges will cancel. when the clock waveforms are fast. The theory behind this technique is that if the width of is taken exactly onehalf that of and if the clock waveforms are fast. 8.. it is difficult to make the ratio equal to the optimum required for perfect cancellation..8. The opposite happens when the input signal is closer to the negative power supply. is to add a dummy switch as shown in Fig... 1975]. however. For this to be the case. it is seldom possible to have the clock waveforms change fast enough so thaT the ideal ratio of widths is exactly onehalf..5 An openloop track and hold realized using an nehannel switch along with a dummy switch for c1ockfeedthrough cancellation. the charge from the pchannel transistor is greater than that from the nchannel transistor because of its larger effective gatesource voltage resulting in a positive hold step. 8.. ~ Vi" 0' ' .5 [McCreary.2 MOS SornplecndHold Basics 339 <Pclk Q..
54 ns to +0. while it is still on. the sampling transistor will turn off when <l>Clk is 1.2 Consider the SIH circuit of Fig.nabove v.nis 0. Solution First.5 ns) = 3.6 ns. 8. This clock arrangement guarantees that the cancelling charge of Q. Thus. the true sampling time is earlier than the ideal sampling time..3 turns off when <l>Clk is V. the input impedance of the sample and hold is greatly increased. the de error due to this buffer will be divided by the gain of the input opamp (although the inputoffset of the input opamp will remain). Another advantage of this configuration is that even if the unitygain buffer at the output has an offset voltage.33 V/ns) = 0. as shown in Fig. is high.7 V)/(3.8 V greater than the input signal. the sampling time occurs when <l>clk is D. 8.75 ns after the clock first starts to move.0. A more elaborate sampleandhold circuit is to include an opamp in a feedback loop.340 Chapter 8 • Sample and Holds. as shown in Fig.6. the samplingtime uncertainty is 0. transistor Q 1 of Fig. where Vin is a 20MHz bandlimited signal with a 2Vpp amplitude. Assume the ideal sampling time is defined to be the negativegoing zerocrossing of <l>clk' The true sampling time is that when the samplingclock voltage passes through the value when it is one transistor threshold voltage drop above the input voltage.5 V with linear rise and fall times of 1.3 is caused by clock waveforms having finite slopes. 8.2 V. In other words. Thus. Assume that <l>Clk is a lOOMHz square wave having a peak amplitude of ±2. 8. 8. we note that the slope of <l>Clk is (5 V)/( 1.. Also.33 V Ins.81 . assuming the ideal sampling time is 0. and the true sampling time is when the clock waveform is 0.06 ns from the ideal sampling time. the input voltage at that time is stored on Chid' similarly to a simple sample and hold. which is (0.3. the true sampling time is late.5 ns. Therefore. whereas when Vin is less than 0 V. and Translinear Circuits EXAMPLE 8.21 ns after the clock first starts to move down. which is 0. A disadvantage of the configuration shown is that the speed of operation can be seriously degraded due to the necessity of guaranteeing that the loop is stable when it . For Vin equal to I V. changes slightly after that of Q . the sampling jitter is from 0. very simple source followers can be used for the output buffer.6. What is the maximum uncertainty of the sampling time? Assume V.7.8 V. <l>clk.21 = 0.8 V. cannot escape through Q. By including an opamp in the feedback loop.81 ns after the clock first starts to move upward. To understand this error source consider the waveforms for Vin and <l>Clk shown in Fig. Voltage References. when Vin is above ground. 8. When <l>Clk goes low. Another source of error for the simple sample and hold of Fig. that the clock of Q. When Vin is I V. When the clock. the complete circuit responds similarly to an opamp in a unitygain feedback configuration.
In this configuration. 8.3.2 MOS Scmpleond. Another source of speed degradation is that when in hold mode. switch 0.7 Including an apamp in a feedback laap of a sample and hold to increase the input impedance. it will take some time for the opamp output voltage to slew back to its correct closedloop value. keeps the output of the first opamp close to the voltage it will need to be at when the T/H goes into track mode. but improved. but rather is placed in the feedback path of a second opamp. Lim. when a I turns off. A similar. the voltages on both sides of switch a I are very nearly signal independent. 1974. 01' similar to the simple S/H of Fig. Chid Adding an additional switch to the S/H of Fig. B. 8.oV o ut I Fig. Thus.8.. the holding capacitor is not going to ground. Q3 >.8.8 imize slewing time. 8. Perhaps the most important of these is due to the fact that. 8. This slewing time can be greatly minimized by adding two additional transistors as shown in Fig. This configuration has a number of desirable features.8. When the sample and hold next goes back into track mode.£. assuming the second opamp has a large gain.7 to min. there will still be charge injection to the left side of Chid' which will cause the output voltage of opamp 2 to G>clk .Hoid Basics 341 01+ >+0 Vo ut Fig.. 1991j. resulting in its output almost certainly saturating at one of the powersupply voltages. It should also be noted that this trackandhold configuration still has errors due to charge injection from the switch. is closed. the opamp is open loop.9 [Stafford. .. configuration is shownjn Fig. During hold mode. The errors due to finite clock rise and fall times are also similar..
This switch grounds the output of the first opamp during hold mode. 8. 1989]. QI' during the closedloop phase. 1987. In addition. 8. t: v. the charge injection due to Q I will cause some de offset but no distortion...342 Chapter 8 • Sample and Halds. This grounding keeps the output of the first opamp close to the voltage it must change to when the StH goes back into track mode.9 by including some additional circuitry intended to minimize the hold pedestal and thereby minimize the de offset [Martin. . 8. have a positive hold step. The switch also greatly minimizes signal feedthrough when the StH is in hold mode by grounding the signal path. the sampling time will not change because of the finite slopes of the samplingclock waveform. The basic idea is to match the charge injection into Chid with a similar charge injection into Chid' Since these capacitors are chosen to have the same size.8. but this hold step will be just a de offset and will be signal independent..8. but with clockfeedthrough cancellation circuitry added.10 An S/H similar to that of Fig. their voltage changes will match. This limitation is worsened since there are now two opamps in the loop along with the on resistance of the sampling switch.9. In other words. This approach greatly speeds up the time it takes the StH to return to track mode. Nayebi.i $.9 An improved configuration for an S/H as compared to that of Fig. and Translinear Circuits Opamp 1 + t: >__0 V out Opamp2 Fig.8. Another advantage is due to the inclusion of Q.10 shows an interesting modification of Fig.:  oj 0. and the common Chid Opamp 1 lPclk + Yin . Voltage References.. Figure 8.  l Opamp 2 C. A major limitation of this configuration is that the speed will be degraded because of the necessity to guarantee stability in the track mode.1d Fig. o] lPclk 0.
Before proceeding. resulting in the sample and hold acting as an inverting lowl is on and pass circuit having a '3dB frequency given by ffi_ 3 dB = l/(RC). the output voltage will remain constant from then on. in CMOS technologies. Furthermore. The major limitation of this approach is a secondorder effect caused by a mismatch in impedance levels at the left of a 1 and the bottom of a. this configuration could be a very viable alternative. Errors due to this mismatch can be minimized by including small capacitors (0. These extra capacitors help keep these nodes at constant voltages while the clocks are turning off.3 Examples of CMOS S/H Circuits 343 mode rejection of the opamp will eliminate the effects of these voltage changes on the output voltage of the SIH. 1989] was a fully differential design and is a very reasonable choice for many S/H applications. but could also limit the signal swing. it is difficult to definitively state which configurations are superior or inferior. assuming the clock waveforms are fast. the required output buffer would not only limit speed. the optimum choice for a sampleandhold circuit is highly dependent on the application's requirements and the technology available.11 [Ishikawa. Unfortunately. as described in Section 8.8.. it should be noted that many of these circuits could also be realized in a BiCMOS technology. For these rea sons. is off. Since the junctions of a l are always at voltages very close to ground.4. the clock feed through of this sample and a a. In bipolar and BiCMOS technologies. 8. choosing the best circuit is nontrivial and a matter of ongoing research. When in track mode. For even higher speeds. where a speed advantage would be obtained by increasing the unitygain frequency of any opamps used. R >__0 V out Fig. a number of CMOS SIH circuits are described other than those already mentioned.3 EXAMPLES OF CMOS S/H CIRCUITS In this section. It should be mentioned that the configuration of [Nayebi. such opamps are difficult to obtain. 8.5 pf to I pf) between each node and ground. Unfortunately. Another structure for an SIH circuit is shown in Fig. 1988]. When O. a BiCMOS circuit can make use of a bipolar diode bridge. turns off. Therefore. This configuration is intended to operate at higher speeds. 8. . assuming a highspeed opamp capable of driving resistive loads is available.11 An inverting track and hold.
Yet another SIH architecture is shown in Fig. but without having a resistor included in series with the load capacitor (as would be required if lead compensation was desired). When the TtH goes into hold mode. 8.12 is attractive for highspeed CMOS applications that are not too demanding. Shown in Fig. 8. the signal dependence of the clock signals can be minimized by having clock signals that change above and below the input signal by fixed amounts. This track and hold places the opamp into a unitygain follower during track mode. .i+ c.13 [Lim.' Furthermore. In a CMOS technology.14(a) is the circuit configuration when the StH is in sample mode. During hold mode. that this capacitor improved the speed of the StH. In the implementation described in [Ishikawa. the charge feedthrough from QI' although signal dependent. this is not too difficult to realize using diode clamps in a bipolar or BiCMOS technology. the effective hold capacitor is the <Pclk Vi" 0. the topology of Fig. Thus the total capacitance that needs to be charged or discharged during this mode is C I + C. the configuration is as shown in Fig.. it is more difficult. This can be partially realized using a highoutput impedance OT A by having a load capacitor connected to ground. During this mode. the opamp must have a lowimpedance output. transistor Q.1 '. and both capacitors are connected between the input voltage and the virtual input of the opamp. 8._OV c. the input signal is stored across C I' since Q I is turned off.. and Translinear Circuits hold is signal independent... Voltage References.12 A simple naninverting sample and hold with clackfeedthraugh cancellation. Ideally. 8. out I Q. The function of Q. 8.. is to minimize signal feedthrough when in hold mode and to keep the common node of the resistive network close to the voltage required when the StH goes back into track mode. 2. At the same time. and supported by analysis. Fig.344 Chapter 8 • Sample and Holds. Regardless. Also. >. It was reported. will be matched by the charge feedthrough from Q" since both are at the same voltage and have the same clock waveforms. For this to be true.. 1988].. 8. either. finite clock rise and fall times do not make the sampling time a function of the signal. the positive input terminal of the opamp is connected to Vi" at this time. During this mode. is also turned off. Also. an additional small bypass capacitor was included in parallel to the input resistor.12 [Sane. 1991].... As will be seen in the next section.14(b). the opamp is being reset. 1993]. Another alternative is shown in Fig.
. Miller capacitor given by = (I +A)(c. Since the voltage changes at the output VinO b (a) r C2 Yo".... . (8.....1 Fig...... 8.3 Examples of CMOS S/H Circuits 345 .14 The circuit configurations of the S/H of Fig..11...8....13 during 10) sample mode and Ib) hold mode.OVOU1 C2 Vin "_J I ' . Vin~ Gi (b) Fig...13 An openloop architecture but with a Miller holding capacitor..8..C..6) which is typically much larger than the capacitance that needs to be charged during the sampling mode.. +C.. 8. J C. This allows smaller capacitances and therefore smaller switches to be used than would otherwise be the case.
1991]. Voltage References. and shortly thereafter 0\ and 0 3 are turned off. a. Because and tum off slightly before and 0 3.15 adds two unitygain buffers and two more switches to help improve accuracy. and also the output impedance of the S/H is very low. At the same time. Note the similarity between this configuration and that of Fig. Next. 8. These SlHs tend to be quite accurate but not necessarily fast. During this time. and are turned off. it is easy to design the amplifier for very high speed. A. At lower frequencies. obviously. a.346 Chapter 8 • Sample and Holds.8. Also. An interesting variation somewhat similar to the SlHs of Figs. or the speed is seriously degraded.15 >eo v. and Translinear Circuits of the amplifier are very small. During sampling. A simple example is shown in Fig. This connects C] and C. This configures the circuit as shown in Fig. is turned on. 8.15. a. 8. The sampling switch. the opamp is being reset and the positive terminal of the opamp is charged to 0 V. a. their clock feedthrough is not only signal a. 8.14(b).16 [Real. all switches are on except a. a" does inject signaldependent charge as in other openloop architectures. Finally.13 and 8.: A simple switchedcapacitor SjH. C H is charged up to V i n . This will cause the output voltage to be equal to Vi" irrespective of the inputoffset voltage of the opamp. there are a number of sampleandhold architectures based on switchedcapacitor technology that are often used. the sample phase. Note how similar this SIH is to the SIH of Fig. The unitygain feedback holds the output during this phase. + Fig.13. During $" capacitor C H is connected between the input signal source and the inverting input of the opamp. . The SIH is shown in Fig. the inverting input and the output of the opamp are connected together. is turned off slightly before a. during the sample phase. V of f ' Thus. This places a requirement on the opamp to have a very large slew rate. Specifically. during $2' the opamp is taken out of reset mode. especially if a. At the same time. but again this is minimized by the large size of the Miller hold capacitance..17.. together and charges them to tht: input voltage. 8.V o ff ' Next. the input impedance is quite large due to the inclusion of buffer B]. the opamp output is invalid during $\. This causes the voltages at both of these nodes to be equal to the inputoffset voltage of the opamp. Note that this circuit is an example of a sample and hold that is not thought of as a trackandhold circuit. and the capacitor C H is connected between the opamp output and its inverting input. 8. the opamp output voltage will be very close to 0 V rather than tracking the input voltage.
.15 is the SIH shown in Fig. The charge injection of 0 3 is signal dependent and does affect the output voltage.. Fig... .3 Examples of CMOS S/H Circuits 347 C1 C. An interesting variation on the SlHs of Figs.0 Vout C. 8. and the second opamp is holding the previouslysampled input voltage..8. 8.10 and 8. Fig....8. 8.. This TIH has an output that is always valid and incorporates a number of features.16 A recycling S/H . C s is sampling the input voltage. .13.. independent but largely cancels due to the commonmode rejection of the input stage of the amplifier [Martin.. 1992]. .. During the next . .16 when in hold mode. During sample mode. The charge injection of 0 1 and O 2 does not affect the output voltage. the inputoffset voltage of the first opamp is stored across C O F' At the same time.8. 1987J.18 from [Gatti. 8. C.17 The S/H of Fig.. but its effect is minimized by the loop gain similar to the SIH of Fig.
and Translinear Circuits '. 1992]..£.. Yin . The other switches ideally do not cause appreciable errors due to clock feedthrough.1 f. phase. . is cancelled by the clock feedthrough ofswitch 8 6 and the added buffer network. This arrangement causes the output voltage to be equal to the justsampled input voltage.£.. This circuit combines a sample and hold with a lowpass filter and was used to convert a signal from the sampleddata domain to the continuoustime domain at ~. s...348 Chapter 8 • Sample and Holds...18 A switchedeapacitar S/H. 8.8. 8. C. The details concerning the operation of this TIH and the required clocking wavefomns are left for the interested reader to consult [Gatti... + v. ~1oj ~.. Valtage References. The clock feedthrough of switch 8 2 is cancelled by the clock feedthrough of switch 8 3 ... 1991]..19 A switchedeapacitar sample and hald and lawpass filter.:   Fig. ~. the inputoffset voltage of the first opamp is eliminated.. and C s is connected to the output while the feedback loop is enabled. C.19 [Sooch. .. Yet another example of a switchedcapacitor SIH is shown in Fig.+ Fig. The clock feedthrough of switch 8.
C (8. and D" as well as between D. For lowfrequency signals. it can be shown using switchedcapacitor analysis techniques [Martin.4 BIPOLAR AND BICMOS SAMPLE AND HOLDS In this section.18) do have dc offsets due to clock feedthrough from the switches connected to the inverting inputs of the opamps. 8. which came from previous samples. bipolar and BiCMOS sampleandhold circuits are described. and D4 . fully differential sample and holds can be used. similar to what is described in [Martin. is turned on and evenly divides between D. its charge is shared with the charge being stored across C". the output voltage will equal the input voltage in the steady state. A more practical realization of a diodebridge track and hold is shown in Fig.where rd =  VT 1m =  VT I B/2 (8. these offsets are largely signal independent assuming the opamp has a reasonable gain.8) In hold mode. it is possible to minimize these offsets by including a clockfeedthrough cancellation network connected to the positive input of the opamp. Next.k . during <P2' it is connected between the output and the inverting input of the opamp. 2ltC. Chid' open circuited. V'rk is at a higher voltage than V hid' . Here. Alternatively. While this example does not eliminate the effects of opamp finiteinput voltage offsets.20 [Erdi.8. 8. which also helps minimize the effects of clock feed through. Higher frequency changes in the input signal will be lowpass filtered. leaving the hold capacitor. it does have the advantage that its output is always valid. 1987]. as shown in Fig. Also.4 Bipolar and BiCMOS Sample and Holds 349 the output of a highquality audio digitaltoaualog converter based on oversampIing techniques. Most of the early integrated bipolar sample and holds were based on using a diodebridge switch. I B .7) where Iel k is the clock frequency. both current sources labelled I B are turned off. The switchedcapacitor samplehold circuits just shown (except for that of Fig. It should be noted that BiCMOS sampleandhold circuits are often realized using the CMOS techniques described above. For C 2 greater than C I by at least a few times. 1980] that the 3dB frequency of the lowpass filter is approximately given by I CI L'dB =' I. 1990]. 8. In track mode the bias current. At this time. During <PI' C I is connected between the input voltage and ground. 8. 1978]. we look at BiCMOS circuits more closely related to their bipolar counterparts. However. During track mode. unlike the previous two examples. The lowpass filtering was used to help convert from a singlebit highfrequency signal to a decimated lowerfrequency multibit signal. This current division results in a lowimpedance path between the input and the output with a smallsignal impedance of rd.21 [Matsuzawa.
. Since 0.21 An improved example of a diodebridge track and hold. 8. 0.350 Chapter 8 • Sample and Halds. 0. 0. 0. Also. Vh1 d Vtrk J Chid Fig. Is l Chid Fig. Voltage References. during this phase. 8. and O 2 will be on and conducting 2I B• Half of this current comes from the current source connected to the node V.92 is turned off and 0 1 is turned on. during track mode.. the diode bridge is low impedance. The output voltage will also track this node through the unitygain output buffer. and the node V3 will track the input signal. The other half comes from the current source connected to node V 1 after going through the diode bridge.20 A bipolar track and hold based on using a diode bridge. the current from the source connected to the node V2 now Os 0. v: 03 V3 yOU! V. is turned off. When the track and hold is placed in hold mode. the diodes 0 5 and 0 6 are reverse biased. and lranslinear Circuits 0. VOU1 v: 03 0. Thus.
nodes V. 1990]. When the simple circuit of Fig. or D3 will become forward biased. regardless of the value of Yin' Thus. the voltage changes of nodes V.20 is in hold mode.21 is that the sampletime uncertainty caused by the finite slope of the clock waveforms is greatly minimized. The other half comes from Vout through diode D" causing it to become forward biased. The magnitude of this signal feedthrough is easily calculated using the capacitordivider formula. the charge from tuming the diode bridge off. This would increase the maximum allowable signalswing excursion to three diode drops. Thus. Perhaps the most important of these is that the clock feedthrough is signal independent. which will tend to clamp the input signal. Finally. turn off faster than regular diodes and have smaller hold steps. Half of this will come from the current source connected to node V. turning it on. Furthermore.4 Bipolar and BiCMOS Sample and Holds 351 flows through the diode D6 . Therefore. are connected to Vout through lowimpedance paths consisting of conducting diodes D. This independence occurs because when the diode bridge turns off. 8. 8. to be one diode drop above Vout which causes diodes D3 and D4 to become reverse biased. This causes V. and D6 . a third advantage of Fig. In the BiCMOS realization presented in [Matsuzawa. It should be mentioned that in many implementations. and a voltage one diode drop above Yin' respectively. will be reverse biased. At the same time.21 has a number of advantages compared to the simple circuit of Fig.21 that the maximum inputsignal excursions during hold mode are limited to less than two diode drops above or below the input signal voltage at the time the track and hold went into hold mode.20.. will be one diode drop below Vout and diodes D. 8. are from a voltage closely equal to Yin. One of the major limitations of bipolar SlHs is a droop in the voltage being stored across a capacitor during hold mode. For highspeed track and holds. This signal feedthrough is minimized in the improved circuit of Fig. and D. and. 8. which would normally be caused by finitebased currents of bipolar input transistors. one of the diodes D. the diodes would all be Schottky diodes. and D6 with two series diodes. and the node V 3 is disconnected from the input signal.21 is that when in hold mode. the charge from D. the diodes are turned off but are floating. all the diodes in the diode bridge are reverse biased. and V. and changing the reversebias voltage of the diodes in the bridge. respectively. 8. thus. The input signal is then capacitively coupled through the junction capacitance of these reversebiased diodes to the hold capacitor. will be conducting current 2I s. which don't have minority carrier charge storage when they are on. Furthermore. and V. to a voltage one diode drop below Yin. This effectively shields the node V 3 from the input signal during hold mode. because during hold mode. Q. Otherwise. the input signal range can be increased by replacing each of D. will (to a firstorder degree) cancel the charge from D3 and D4 . 8. The circuit of Fig. V.21. this input amplitude restriction is not usually a serious limitation as peak signals are usually limited to be less than one volt.8. caused by the finite base currents of bipolar tran . the signal feedthrough is substantially smaller. assuming fast clock waveforms. and D. is signal independent. 8. It should be noted in Fig. the input transistors to the unitygain buffer were pchannel MOS transistors that minimized the droop on the hold capacitor during holdmode. A second advantage ofFig. which also minimizes the effects of charge injection.
1992]. through D. then Q 3 will be conducting 3IB • I B of this will come from M.22 [Wakayama. An example of a fully differential diodebridgebased TIH is given in [Colleran. . but operate differently. This will cause Q" D" and D2 to turn off and Q" D3 . during slewing the current available to charge or discharge the holding capacitors is dynamically increased to 3I B rather than the quiescent I B . and D" to turn on. This SIR uses bipolar switches that appear similar to the diode bridge switches. and D j .::::==~=i. Diodes D 3 and D" are reverse biased and Vout2 is isolated from V in . the current sources were realized using resistors. 8. 1993J. or Q. When V"" is greater than Vhl d j . and additional circuitry was also included to minimize errors introduced by these resistors. and M. This arrangement can possibly be used to effectively double a data rate. An interesting BiCMOS SIH is shown in Fig.. and I B ofthis will come from M. to a firstorder approximation.<>V out1 L__~__'::==+===j. the other is in hold mode.20.22 A BiCMOS sample and hold. Also. Finally. rlr~.) and that the load current on the input source is constant (and equal to the base current of the emitter followers). In this phase. Ms. Notice that the input is buffered from the holding capacitors by emitter followers (either Q. and the differential signal is. I B of this will come from M6 . are accurately determined by the feedback loop including M M. 1992]. and Vout2 will track Vin . In this example. through Qj.~o Vh1 d1 V out2 r Fig. Voltage References. as is explained in [Wakayarna. 8. and D" have been reversed compared to the circuit of Fig. When V'I" is less " than Vh ld " then Q" will be conducting 3I B . One of the major ways of minimizing this droop is to use fully differential approaches where the droop is the same in both paths.352 Chapter 8 • Sample and Holds. Since both Qj and D j are conducting. Vout t will equal V in . 8. and Translinear Circuits sistors. VOUli will be isolated from Vin . Note that the direction of diodes D. and the unitygain buffer. unaffected. The ratios of the currents in M" Mj . when one output is in track mode.
Robertson. Rather. except the switches are realized using bipolar switches. and Vorenkamp. the actual value of the reference is difficult to determine accurately because of the process sensitivity of the difference between the threshold voltage of an enhancement device and a depletion device. Petschacher. Some alternative and interesting BiCMOS examples include [Fernandes. 1991. will be discussed. The first approach is not popular nowadays because the breakdown voltage of a zener diode is typically larger than the power supplies used in modem circuits. although it can be used to make quite stable references. 1993]. the first two approaches are not covered here. Some alternative and interesting bipolar examples include [Moraveji. . especially in data acquisition systems. this block will supply a fixed dc voltage of known amplitude that does not change with temperature. this PTAT voltage is realized by amplifying the voltage difference of two forwardbiased baseemitter (or diode) junctions. The interested reader is referred to the applicable references. A bandgap voltage reference system is shown symbolically in Fig. 8.5 BANDGAP VOLTAGE REFERENCE BASICS Another important analog building block. Voltage references based on the last approach are commonly called "bandgap" voltage references for reasons that will become apparent shortly. Bandgap Voltage Reference As just mentioned.23. 1990. a bandgap voltage reference is based on subtracting the voltage of a forwardbiased diode (or baseemitter junction) having a negative temperature coefficient from a voltage proportional to absolute temperature (PTAT). and Real.8.12. In addition. The second approach cannot be used in most CMOS circuits because depletion transistors are not typically available. There have been a number of approaches that have been taken to realize voltage references in integrated circuits. There have been a number of other alternative bipolar and BiCMOS track and holds that have been reported in the literature. the last approach. 8. 1989. 2. 8. which makes use of the basic architecture shown in Fig. For these reasons. 1990.5 8andgap Voltage Reference Basics 353 An alternate mCMOS SIH is described in [Sone. As we shall see. is a voltage reference. Making use of the difference in the threshold voltage between an enhancement transistor and a depletion transistor. 1992]. 1991]. Ideally. Cancelling the negative temperature dependence of a pn junction with a positive temperature dependence from a PTAT (proportionaltoabsolutetemperature) circuit. Making use of a zener diode that breaks down at a known voltage when reverse biased. These include 1. 3. which is currently the most popular for both bipolar and CMOS technologies.
T.354 Chapter 8 • Sample and Holds.!. This negative temperature dependence is cancelled by a PTAT temperature dependence of the amplified difference of two baseemitter junctions biased at fixed but different current densities. it is seen that if there are two baseemitter junctions biased at currents J. Writing the baseemitter voltage as a function of collector current and temperature. +mkT In(ToJ+ kT In(~J To BEa To q T q Jell (8. For Ie constant. and Translinear Circuits A forwardbiased baseemitter junction of a bipolar transistor has an IV relationship given by (8./kT where Is is the transistor scale current and.3. J e and T are the collector current density and temperature. To.23 ence.J+ V . as long as their ratio remains fixed. V Go is the bandgap voltage of silicon extrapolated to 0 "K (approximately 1. VB E will have approximately a 2 mV 1 0 K temperature dependence around room temperature.11) where AE is the effective area of the baseemitter junction. This proportionality is quite accurate and holds even when the collector currents are temperature dependent. while the subscript 0 designates an appropriate quantity at a reference temperature.206 V). = qln (J'J J. whereas VBE is the baseemitter junction voltage at the true temperature.!. Tsividis. Also. J eo is the collector current density at the reference temperature. the difference in the junction voltages is proportional to absolute temperature. and J" then the difference in their junction voltages is given by kT tN B E = V2V. whereas J e is the collector current density at the true temperature. VBEO is the junction voltage at the reference temperature. respectively. Voltage References. Also. has a strong dependence on temperature.10) Here.9) Ie = Ise qV.26 V PTAT Generator Fig. (8.. V ref = 1. 1967.10). T. A simplified circuit of 0 bandgap voltage refer . although not shown.12) Thus. To. 1980] VE B = VGO(1  . 8. it can be shown that [Brugler. Specifically. and m is a temperature constant approximately equal to 2. (8. k is Boltzmann's constant. Note that the junction current is related to the junction current density according to the relationship To. Using (8.
15) along with (8. It will be seen shortly that when realizing a bandgap voltage reference. whereas J. the voltage dependence is 59. What is the difference in their baseemitter voltages and what is its temperature dependence 0 Solution Using (8.12). as explained next.8. we have ~VBE= kT In(J 2) = 1.7 mV 301 300 (8.12) and (8.= 59. Now. assume that the difference between two baseemitter voltages is multiplied by a factor of K and added to the baseemitter voltage of the junction with the larger current density.38XIOq J1 1. the voltage difference will be ~VBE = 59. Later.10). we have (8. Using (8.14) Thus.13) Since this voltage is proportional to absolute temperature. although the output voltage is temperature independent. We therefore first assume = (8. after a 1 0 K temperature increase. we will first assume the junction currents are proportional to absolute temperature.o is the same current density at the reference temperature.602 X 1019 23(300)ln(lO) = 59. is the current density of the collector current of the ith transistor. the junction currents tum out to be proportional to absolute temperature (assuming the resistors used are temperature independent).5 mV 1300 "K or 0. it will be verified that this proportionality relationship is true when circuit realizations are described. If we want this relation .198 mV 1 0 K .15) where J. to simplify derivations.16) Equation (8. Thus. if it is desired to cancel the temperature dependence of a single VBE' then ~ VBE should be amplified by about a factor of 10. Since the temperature dependence of a single VBE is 2 mV 1 0 K .5 mV.5 Bandgap Voltage Reference Basics 355 EXAMPLE 8.5 mV (8.3 Assume two transistors are biased at a currentdensity ratio of 10: I at T = 300 "K.16) is the fundamental equation giving the relationship between the output voltage of a bandgap voltage reference and temperature.
] q J. 2 (J (8.24 . the result is (8.356 Chapter 8 • Sample and Holds.16) with respect to temperature and set the derivative to zero at the desired reference temperature. we need V rel _ = VGo+(mI)o q xr.3.20) V. Voltage References. Notice that this value is independent of the current densities chosen. (8.17) equal to zero at T = To.= (VsEo_2VGo)+Kln ..2] +(ml)In (To I ] I k k sr To q JI q T (J (8. From (8. The reason for the name of the bandgap voltage should now be apparent.0258 xr.21) In(~:] at 300 x.VSEfl. we need (8. Specifically. this correct output voltage will be achieved by trimming at the time the wafer is being tested. and Translinear Circuits ship to be zero at a particular temperature.el_o = 1.19) For the special case of To = 300 OK and m = 2.18) The left side of (8. The output voltage of the reference for temperatures different from the reference is found after backsubstituting (8.N.18) is the output voltage Vrei at T = To from (8. Thus for zero temperature dependence at T = To.18). In many integrated voltage references.17) Setting (8.16).19) into (8. In . the required value for K is V GO + (m .1 ) . Thus. for zero temperature dependence. we can differentiate (8.V SEO2 kr. if a larger current density is chosen.24 V for zero temperature dependence.22) and .2 0. we see that for zero temperature dependence at the reference temperature. (8. From (8. q K= 1.19) implies that (8.18) and (8.16). then K must be taken appropriately smaller to achieve the correct reference output voltage. After some manipulations.16). the output of a bandgap voltage reference is given by the bandgap voltage plus a small correction term to account for secondorder effects. we have rel .
we have x and (8. Substituting these values into (8.8 J.24 V (8.5 x 10 parts. 8.25) where ppm represents parts per million. It should be mentioned here that practical effects result in voltage references with typically 4 to 10 times larger values than this small amount of temperature dependency.lV /0 K _ . Since R 3 = R" this guarantees that both transistors have the same collector currents and collectoremitter voltages.6 CIRCUITS FOR BANDGAP REFERENCES Bipolar Bandgap References A voltage reference originally proposed in [Brokaw. has eight times the current density of QI' resulting in J. n 19 1.26) . we can write To = 293 T = 273 "K.24 V. Solution Recalling that 0 "K corresponds to 273 °C..Z''K = 6.I ) 1. 8. In the next section. Therefore. A simplified schematic of the circuit is shown in Fig.38 x 10.6 x 10273 23 For a reference voltage of 1. a practical bipolar realization of a bandgap reference will be described.6 Circuits for Bandgap References 357 (8. Also. It should also be noted that the ideal firstorder temperature of this bandgap voltage circuit is 0 ppmz PK at the reference temperature of 20°C. Present the result as ppm z FK.23). The amplifier in the feedback loop keeps the collector voltages of Q I and Q.8.4 Estimate the temperature dependence at 0 ° C for a bandgap voltage reference that was designed to have zero temperature dependence at 20°C.24) aV ref _ sr (23 . EXAMPLE 8. = 8 (8.5 ppmvvK 1.24.lV /oK results in 8J..1 (293) . Q.23) These equations can be used to estimate the temperature dependence at temperatures different from the reference temperature. notice that the emitter area of Q I has been taken eight times larger than the emitter area of Q. a dependency of 8 J. 1974] has been the basis for many bipolar bandgap references.lV/oK 6 = 6. equal.
. 8. +  2R I R.65 0. It is immediately recognizable that K= 2R. But (8.27) Also VR.. would be trimmed while monitoring Vret to force it equal to the desired reference voltage.358 Chapter 8 • Sample and Halds. the optimum value for .30) which is of the form desired to realize a bandgap reference.}:::f.24 .21)  RI R.29) into (8. VBE. = x 2 I 1. R. I R' = = ""'::'= = R. !N BE (8. Fig.65 V...28) and (8. and Translinear Circuits . . Furthermore. from (8. (8. Valfage References.0. We have for the circuit (8.32) In an integrated implementation. = IRIR I = 21R .28) VR..24 A simplified schematic of a bipolar bandgap voltage reference. R. or R.31 ) Assuming V BE20 = 0.0258 x In(8) = 5. (8..VBE .R.o Vret R.5 (8.29) Substituting (8.27) gives Vref = VBE. R.
as assumed earlier. 8. we have kT In(J'J q_ J.12) and (8.6 Circuits for Bondgop References 359 R. 1974] for additional details concerning this realization. In applications where it is desirable to have reference voltages larger than 1. is temperature independent). this voltage might be determined empirically during the prototype phase of the design cycle. R. a modified bandgap reference as shown in Fig. from (8. It is not difficult to show that the output voltage is now given by (8. all currents are indeed !'TAT. (8. ><~<l Vref R2 Rs Fig. unfortunately.25 can be used.24 V. has the undesirable feature that the circuit power dissipation goes up considerably at high temperatures. but.24 V.B. which makes it more difficult to dissipate the heat. It is worth mentioning here that !'TAT currents are often used to bias many bipolar circuits. 8.33) implying that all currents are proportional to absolute temperature (assuming that resistor R.34) Resistor R 3 has been added to cancel the effects of the finite base currents going through R4 and should be chosen according to the formula in the figure.29). R. Thus. . as they result in transistor transconductances being independent of temperature. This transconductance independence has the desirable feature that circuit speed is relatively independent of temperature. The interested reader is referred to [Brokaw.II Rs R. Notice also.25 A bipolor bondgop with output voltoges greoter thon 1.
40V ref R3 . 8. R3 I.27(a) for nwell processes [Kujik. e 12 .j. and Translinear Circuits CMOS Bandgap References The most popular method for realizing CMOS voltage references also makes use of a bandgap voltage reference despite the fact that independent bipolar transistors are not available. R. Voltage References.360 Chapter 8 • Sample and Holds. These transistors have reasonable current gains.. .26(a). which can be high due to the large lateral dimensions between the base contact and the effective emitter region. but their main limitation is the series base resistance. .27 Bandgap voltage references implemented with well transistors in (a) an nwell CMOS process...27(b) for powell processes lYe. These CMOS circuits rely on using what are commonly called well transistors. Q. R2 .tl v.substrate (a) n: substrate VDD (b) Fig. 1982]. These devices are vertical bipolar transistors that use wells as their bases and the substrate as their collectors..26 Vertical CMOS well transistors realized in 10) an nwell process and (b) a pwell process. 1973] or Fig. and [b] a pwell CMOS process. these vertical bipolar transistors are pnp types with their collectors connected to ground. 8.j..".. 8. 8.. To minimize errors due to this base resistance. In an nwell process (the most common modern process). + >.26(b). 8. It is possible to use these transistors to implement bandgap voltage references using configurations similar to those shown in Fig. (a) (b) Fig. ttl+ 12 . 8.1 rnA. R. as shown in Fig.j. the maximum collector currents through the transistors are usually constrained to be less than 0. as shown in Fig. I. they would be npn transistors with their collectors connected to the positive power supply. In a powell process. p.j.
= 80 u A.27(a). have the same voltage across them. we have Y re. q R. assuming the opamp has large gain and that its input terminals are at the same voltage. Also. (8. 8. Using this fact and substituting (8.38) gives v. greater than R" which causes I. (8. + '.35) results in V ref = Y EB. = !!.=J. The opamp feedback also makes the voltage across R..27(a).12) that (8. R. I. 0 = 0.I n ' R. recalling from (8.36) Now.37) using (8. is the same as the current through R2 .39) in (8. = YEB j + .38) which is in the required form to realize a bandgap reference. = Y EB.65 V at T = 300 OK. the bipolar transistors are often taken the same size. R2 R. where I.5 Find the resistances of a bandgap voltage reference based on Fig. equal to the voltage across R. (8. + Y AI (8. = 8 /lA.vEB R. then (8. = Y A . . and YEB1. R. In this case. 8.41) It is immediately recognizable that K= R.40) and using (8. since the current through R. a. (8. to be larger than I.42) EXAMPLE 8..37) into (8.36). we would have Jj R.kT [R J 3 R. and the different currentdensities are realized by taking R..35) Also. In integrated realizations of this reference. .8..39) since R j and R.dYEB R3 R2 (8.6 Circuits for Bondqop References 361 With respect to the nwell implementation of Fig. we have Y A .
n I q (II) 12 = 59 mV (8. 0. The errors caused by this temperature dependence can be eliminated by offsetting Y refO slightly positive from the value given by (8. we have Y R.362 Chapter 8 • Sample and Halds.0258 x In(lO) = 9. In CMOS realizations of the references just described.43) = YrefoYEBIO = 0. which requires approximately a gain of 10 to cancel temperature dependency (actually 9.44) Also.. Voltage References. recalling from (8.3.Y EB = kr. as found in Example 8.2.8 kO 12 8 uA and (8.93 (8.50) where 11 = 2.43 kO (8.27(b) are essentially identical to those just given for the nwell reference. The design equations for a voltage reference that is suitable for powell processes and shown in Fig. and Translineor Circuits Solution Recalling from (8.45) 12 R I = R.47) R2 = R.= 7.24. these resistors have a temperature dependence approximately given by [Michejda.19) to . 1984] R(T) = Ro Tn Tri (8.93 in this case).0.. we find that fl.46) Now. we require Y RI (8.22) that K= therefore 1. Unfortunately.24 V therefore. the large value resistors are often realized by well resistors. since Y R l = Y R I .40) and noting that J I I J 2 = (since the sizes of Q I and Q 2 are assumed to be the sarne).59 V R] = = = 73.48) It is of interest to note here that using (8.49) gives the temperature dependence value of 198 mV 1 6K. K = 7. from (8.38 kO II (8.65 V 0. 8.35).59 V (8.20) that Y reto = 1.
Together. $. error approximately given by [Song. as we saw in (8. 1983]. a I mV offset error that is temperature independent causes a temperature coefficient (TC). 1982. $J c. Meijer. A detailed explanation of how the amplifier shown in Fig.. This results in an error term in the equation for tN BE that is roughly equal to K times the inputoffset voltage of the opamp. 1983J TC error " 26 ppm/oC (8. there is still an inherent temperature dependence of the bandgap voltage reference.28 operates is deferred until Chapter 10.I ) q Assuming the effects of the temperature coefficient of the resistors have been minimized.51) V ref• O = kT O VGo+(m+ll. but the interested reader is referred to [Palmer. 8.52) One means of eliminating this source of error is to use switchedcapacitor (SC) amplifiers that have inputoffset compensation circuits [Song. Fig.23). 1981. the next major source of error is often due to the inputoffset voltage of the opamp [Michejda. For example.l $~C3 $. 1984]. 101 I $. Minimizing thesesecondorder effects is beyond the scope of this book.28. 1983] to see examples of how errors due to secondorder effects have been minimized. these two error sources limit the best achievable temperature coefficient to about 25 ppmz'rK. a further temperature dependence occurs because VGO varies slightly with temperature (which has been ignored in the above analysis).8.6 Circuits for Bondgap References 363 (8. where switchedcapacitor circuits are discussed.28 An SCbased voltage reference that is insensitive to opamp inputoffset voltages. 8. The amplifier shown results in a circuit having its output valid at all times and is less sensitive to finite opamp gain. In addition. . One possible SCbased voltage reference is shown in Fig. Assuming errors due to the inputoffset voltage of the opamp have been minimized. Song. 1987]. = e $2 = C2  ~1$2 v. where it makes use of an amplifier described in [Martin. KC. 8.
which in this case are realized by the baseemitter junctions of 0. 8. They are also useful in realizing fourquadrant analog multipliers. 'l_. These gain cells are useful when building circuits requiring varying gain. . The second stage is a differential pair. /. The output current. io ' is a scaled version of 1 1 0 3. or (8.r. in [Tzanateas. Voltage References.. • ie3 . and O2. Fig. 1990]. 1979] a voltage reference was reported that was based on a realized PTAT voltage from the difference of the sourcegate voltages of two MOS transistors biased in weak inversion. is given by Vee Q. we recall the relationship between the baseemitter voltage and collector current. These four transistor gain cells are also commonly called twoquadrant multipliers or Gilbertgain cells. :. 1985].29 A fourtransistor gain cell. where lateral npn well transistors were used. io I. as will be seen in the next section. A translinear gain cell is shown in Fig... 8. To analyze this cell. Also.53) Thus. 1968a. o .364 Chapter 8 • Sample and Holds. such as in adjustable continuoustime filters and voltagecontrolled amplifiers. and Translinear Circuits An alternative realization of a CMOS bandgap reference was reported in [Degrauwe. 8.e see that the voltage at the emitter of 0. It has differential inputs and outputs that are current signals.V + ~. i io 2 = 1 0 1 1 . The first stage simply consists of pn junction loads.7 TRANSUNEAR GAIN CELL An important analog building block for bipolar circuits is the translinear gain ce1l 3 [Gilbert. "I.29. Gilbert.. The interested reader can consult the references for details on these circuits. ignoring the base currents of 0 3 and 0 4 ..
54) where a = /3/(/3 + 1).01) (I s 2/ o. are matched such that the difference between v e 2 and vel' we have = I s 2 . 1 and II' 2 An important point to note here is that not only is the difference between i and C3 IC4 linearly related to the input current.56) Note that this voltage difference.8. the collector current.. io' is given by = 1 0 I.10 that the largesignal emitter currents through a differential pair are given by and Therefore. iC4 is equal to (8. To analyze the Current output from the differential pair of 0 3 and 0 . we recall 4 from Section 3. 1= (VT)ln 1 . we have Ve . and defining!'!. the output current is equal to a scaled version of the input current where the scaling factor is determined by the ratio of two de bias currents. does not depend on the scale current. is equal to (8. we have (8.V. This result is important since it implies that .59) In a similar manner.7 Tronslineor Gain Cell 365 (8. For O 2 .58) (8.61) In other words.55) Now.60) Finally. the output current. Is. lSI (8. !'!.V to be (8.57) and for IX = 1. ] II (8. but also each of i C3 and i is also linearly C4 related (except for the de bias current). assuming 0 1 and 0. i c3.
assuming all transistors should remain in the active region with at least 20 /lA of emitter current? Solution Making use of (8. the extreme values of I. the peak current ef 10 I should be less than 180 u A. 8.5 to 4. 8. Q 2 and Q5. Q6' while the other gain cell consists of the differential pair QJ' Q 4 and makes use of the same voltage generating pair. such as frequency modulators in communication systems or phase detectors in phaselocked loops. what is the maximum peak current that should be used for 10 1. Q 2 and QJ' Q4' EXAMPLE 8. Note that if II were varied while 12 remained fixed.60). We can analyze this multiplier by making use of the results for the gaincell circuit just discussed preceding. Since they are biased with 200 u.8 TRANSUNEAR MULTIPLIER A translinear multiplier" is one approach for realizing a fourquadrant multiplier circuit. should be four times that of II> which is 800 u A.5 is needed. one should be aware that there are mechanisms that will create distortion in a gain cell. . recognizing the similarity of this circuit with that of Fig.59) and (8. Multiplier circuits are useful in a variety of applications. Q5.29 where II is fixed to a bias current of 200 u A. Therefore. 1968b]. one gain cell consists of the two differential pairs QI. are 100 /lA and 800/lA. 12 should be onehalf of II> which is 100 /lA.29 and making use of (8. while I. it does not affect the linearity of the overall circuit. note that the gain and linearity are not dependent on any transistor parameters such as J3 or Is. What are the extreme values of 12 needed? Also. Specifically. varies such that the gain changes from 0. such as mismatches between transistors and the occurrence of linear resistances in the pairs QI. A translinear multiplier can be realized using two translinear gain cells. Voltage References. Note that the preceding multiplier circuit is effectively two gaincell circuits with their output signals crosscoupled.A. and Translinear Circuits even if the difference between these two currents is not taken precisely. as seen in the sixtransistor translinear multiplier shown in Fig. 8.366 Chapter 8 • Sample and Holds. However. when a gain of 0. I. A translinear multiplieris also commonly called a Gilbert multiplier or an analog multiplier.A each. we find the following four collector currents: 4.61). When a gain of 4 is needed. Furthermore. the maximum peak level of 1 1 would change as II was varied.30 [Gilbert. Q6' Thus. The maximum peak current of 10 1 is found by noting that the emitter currents of either transistors Q I or Q 2 should not go below 20 u. 0 8.6 Consider the gain cell shown in Fig.
+ i. (8. . can be made positive or negative (as it is the amount of the bias current deviation from I.66) and I.8 Translinear Multiplier 367 (I.io " ic ' + iC3 = I. remains constant. (I. with respect to the ratio of two positive bias currents and is therefore only a twoquadrant multiplier.i. . .i2 ) 2 (1. II.. (8. Recall that a gain cell can only scale i. i 1i2 I.Thus.). if i. 21.) 2 + (1. .68) Thus.63) (8. . and so the output current.8. we combine collector currents to obtain i. in Fig. (8. if i. 11 . (8.30 A sixtransistor translinear multiplier. . 21.64) iC3 = iC4 = (1. (Input 1) Fig.l. this multiplier is called a fourquadrant multiplier. In addition.. + i... note that i. io• is a scaled positive or negative version of i.29. (8.) (1. To find the output currents. 2 ic ' = + 21. 8. I. and can be scaled by the ratio i. .i. I.i.67) and taking the difference of these two equations results in 10 =  . I. I. A similar result occurs with respect to the output signal and i l. 21. Also. ± in what was simply a bias current of 21. + i.) (1. 2 I.). 8.l. i 1i2 I. remains a constant value and linear in i.62) (I. once again these four collector currents are linear in i. + i. (8. we see that the output signals are linear with respect to i. .)..i.65) Note here that we have made the substitutions of signal currents.
6. Abidi. Maloberti. pp. . Voltage References. F. of SolidSlate Circuits. 120122. such a limit results in the peak gains being ±0. H. "A Precision FETLess SampleandHold with High ChargetoDroop Current Ratio. and Translinear Circuits If voltage inputs. J. December 1989. 365373. Vittoz. Palmisano. E. 353365. Haigh. June 1967." IEEE J. Gilbert. 12. Vol. 11511157.30. S. December 1985. SC2. A gain of zero would occur if collector currents of 0 5 and 0 6 were equal. rather than current inputs. 8. R. Vo!. of SolidState Circuits.. B. Fernandes. C. and 12 are fixed bias currents of 100 ~A and 200 ~A. Gatti. As seen from (8.9 REFERENCES P. "CurrentMode Circuits from a Translinear Viewpoint: A Tutorial. 388393. SC J. pp. pp. Toumazou. December 1968b. respectively." IEEE J. December 1978." IEEE J. "A 14Bit lOl. 0/ SolidState Circuits. Brugler. Degrauwe. 24. If i. what is that maximum gain for io/iz. of SolidState Circuits. Brdi and P. Miller. Henneuse. no. G. where I. "Silicon Transistor Biasing for Linear Collector Current Temperature Dependence." Analog IC Design: The CurrentMode Approach. Lidgey." IEEE 1.. is the gaincontrolling current. "CMOS Voltage References Using Lateral Bipolar Transistors. Miller. G. F. W. and G. to io' while gain is possible if the input signal is taken to be i. 11871199. B. More linear." IEEE J. Peter Pcregrinus.368 Chapter 8 • Sample and Holds. pp. Mallison. "A Precise FourQuadrant Multiplier with Subnanosecond Response. are desired. 27. Examples of these circuits are given in Chapter 15. B. 1. M. the magnitude of i I should be limited to 80 ~A. The simplest of these are differential pairs having emitter degeneration. January 1992." IEEE J. no. December 1993. pp. Gilbert. 6.ls Subranging AID Converter with 5/H. Vol. 28. 8. Leuthold. 1990. no. Ie Bandgap Reference. "A New WideBand Amplifier Technique. O. 864873. Oguey." IEEE 1. "An Accurate CMOS SampleandHold Circuit. Descombes. and A. Brokaw. pp. then one can precede the multiplier with voltagetocurrent converters. of SolidState Circuits. o. M. EXAMPLE 8. and D. of SolidState Circuits. Vol. London. 20. J.7 Consider the translinear multiplier circuit shown in Fig. but more complicated. 3. pp. of SolidState Circuits. assuming all transistors should remain in the active region with at least 20 ~A of emitter current? Solution To maintain 20 ~A of current through 0 5 or 0 6 . December 1968a. 13. Note that this multiplier circuit cannot get gain from i. Vol. December 1974. pp. no. where continuoustime filters are discussed." IEEE 1." IEEE J. 3. Gilbert. Vol. 5758. "A lOb. 75MHz TwoStage Pipelined Bipolar AID Converter. Vol. and G. pp.68). of SolidState Circuits. Vol. U. Colleran and A.8.fSolidState Circuits. Vol. voltagetocurrent converters include local feedback to eliminate distortions due to the modulation of the baseemitter voltages. 14851491. ed. "A Simple ThreeTerminal 9.
. of SolidState Circuits. Wooley." IEEE J. 11391143. R. Vol. pp. of SolidState Circuits. Sooch. Nayebi and B. 634643. of SolidState Circuits. Tsividis. 18. Palmer and R. SC18. "A CurvatureCorrected Micropower Voltage Reference. February 1991. of SolidState Circuits. 10761084. and B." IEEE 1. and K. 6. no. Nicollini and D.Song and P. Vol. Vol. Moraveji. 643651. no. P. pp. SolidState Circuits Conf. 26. Kujik. "A lOb l00Msample/s Pipelined Subranging BiCMOS ADC. no." IEEE J. no. Lim and B. Martin. "A 14b Linear. 6. "A Complete Monolithic Sample/Hold Amplifier. Gray. R. Y. December 1993. M. 222226. of SolidState Circuits. Circuits and Systems. Sane. J. Meijer. et al. Kim. G. Ishikawa and T. pp 15071516. December 1990. pp. Michejda and S. 28. J. Mangelsdorf. no. "A Precision CurvatureCompensated CMOS Bandgap Reference:' IEEE 1. December 1980. SClO. no. B. April 1991. K. Vol. of SolidState Circuits." 91st Audio Engineering Society Conv. Vol. Wooley. SC17. Lett" no. Patil. McCreary and P." IEEE J. Vol. 166167. SolidState Circuits Conf. 6. and Y. February 1981. no. "A Wideband 10bit 20Msps Pipelined ADCUsing CurrentMode Signals." IEEE Int. "A Differential SwitchedCapacitor Amplifier. Salama. 24. Yol. and R. "New C1ockFeedthrough Cancellation Technique for Analog MOS SwitchedCapacitor. Schmale. A. 2. Blanchard. "A Precision Reference Voltage Source. Martin. Vol. "Measurement and Analysis of Charge Injection in MOS Analog Switches. of SolidState Circuits. Real.. no. "18Bit Stereo D/A Convener with Integrated Digital and Analog Filters. K. K. 381387. et al. pp." IEEE 1. Vol. of SolidState Circuits.. 237244. and A. 655657. Gray. pp. L. P. B. K. "An 8bit 50MHz CMOS Subranging AID Converter with Pipelined WideBand S/H." IEEE Int. of SolidState Circuits." IEEEJ. 6. "Improved Circuits for (he Realization of SwitchedCapacitor Filters. Y.. pp. pp." IEEE J.8. 162163. Mercer. Astegher. 4150. pp. pp." IEEE 1. 12. Vol. pp. December 1989. Ozcolak. Vol. pp.. SolidState Circuits Conf. 6. June 1973. "AllMOS Charge Redistribution AnalogtoDigital Conversion TechniquesPart I. a/SolidState Circuits." IEEE Trans. Vol. Tzanateas. SC8. Vol. R. "A lOb 30MHz TwoStep Parallel BiCMOS ADC with Internal S/H. K. Tsividis. Sheu." IEEE Int. February 1991. R. 5859. 150ns SampleandHold Amplifier with Low Hold Step." IEEE J. SC14." IEEE Int. Gray. and G. April 1987. 4. 15. Petschacher. October 1991. K. 13391346." IEEE J." Elctron. of SolidState Circuits. pp. C. 160161. P. SolidState Circuits Conf. December 1983." IEEE J." IEEE Int. F. Martin. of SolidState Circuits. Shieh.January 1991. P. J. pp. pp. 277281. Reprint # 3113(yl). 22. Vol. Vol. "A 14b. 250ns SampleandHold Subsystem with SelfCorrection. D. 9. 1. no. pp. "Accurate Analysis of Temperature Effects in IcY BE Characteristics with Application to Bandgap Reference Sources." IEEE 1. C. pp.. "A Precision CMOS Bandgap Reference. of SolidState Circuits. Nishida. 1. "A lObit Video BiCMOS TrackandHold Amplifier. Dobkin. 4. "A CMOS Bandgap Voltage Reference. December 1974. P. Lechner. Y. of SolidState Circuits. "A New CurvatureCorrected Bandgap Reference. pp. Real and D. G. 6. of SolidState Circuits. "A CMOS Bandgap Reference for Differential Signal Processing. Senderowicz. no." IEEE J. April 1980. pp. February 1990. 25. "A HighSpeed SampleandHold Technique Using a Miller Hold Capacitance. 6. no. no. and N. Stafford. . Lee. December 1975. December 1982. December 1984. 13091315. 104106. SC22. pp. B. 10141021." IEEE J. H. 371379. Vol. CAS27. Nakadai. van Zalinge.. pp. Zojer. Matsuzawa. afSolidState Circuits. 164165. pp. C. "A 10b 75MSPS subranging ND converter with integrated sample and hold. M. 26. June 1979. February 1987. A. S. Jessner. 1992. and C. L. N. Vol. SC19. G. Tsukahara. February 1990. 23. Ternes. 11801186.9 References 369 M. December 1988. SolidState Circuits Conf." IEEE J. Robertson. no.
Widlar. 4 2 C j = 2.9 Y Y = 0. 8. and Y. 8. Yoshida. February 1971. no.9 X 10. 23.0 X 10. 3233. .pF/~m 3 Cox = 1. "A 1.3 The TIH of Fig. find the offset. Tanimoto.0 x 10 ~ pF/~m 8.3. 27. and linearity error of the simple S/H of Fig. pp. Vol. 12.. no.000 L (~m)/ID (rnA) in active region. assume V in is a 20MHz sinusoid with a 2 Y pop amplitude. and the case when it turns on substantially after the sampling switch.5 has transistors that are I0 ~m/0. 8. 4 2 C j = 4 . Vol. Lett" Vol.370 Chapter 8 • Sample and Holds. and Translinear Circuits P.w = 2.5 X 10 pF/(~m) 4 Cj_.. T.pF/(~m)2 Cnsroverteor = Cgd(OVe"aPI = 2. pp.1 Using the transient analysis of SPICE with a sinusoidal input signal of 2 Y peaktopeak.w = 2.pF/~m pchannel MOS transistors: ~pCox = 30 ~A/Y 2 V. February 1992. Compare the final hold pedestal between the case when the dummy switch turns on substantially before the sampling switch turns off. no.5 ns.2llm BiCMOS SampleandHold Circuit with a ConstantImpedance SlewEnhanced Sampling Gate. Tsividis. R. "Bandgap Voltage Reference Sources in CMOS Technology:' Electron.2 For the TIH of Fig. H.pF/(~m)2 4 CgS(Overlap) = Cgd(overlap) = 2." IEEE J.8 urn and a lpF hold capacitor. Verdaasdonk.8 v'? rd.p = 0. of SolidState Circuits. Ye and Y.4. Vorenkamp and J. assume the following: • nchannel MOS transistors: ~nCox = 92 ~A/Y 2 • V'n = 0. "New Developments in Ie Voltage Regulators:' IEEE J. (n) = 12.5 X 10. 8. of SolidState Circuits. 16971708.5 Y with rise and fall times of 1. December 1992.0 X 10. 8. SolidState Circuits Conf. 18. 27.10 PROBLEMS Unless otherwise stated. Also assume that <\lelk is a lOOMHz square wave having a peak amplitude of ±2. Assume the clock waveforms are fast enough that the channel charge of the transistors is evenly distributed between the two junctions.pF/~m 3 Cox = 1.000 L (~m)/ID (rnA) in active region. R. M." IEEE Int. What is the maximum time difference between the turnoff times of the nchannel and pchannel transistors? Ignore the body effect. "A lOb 50MS/s Pipe lined ADC. 8. 1.4 X 10 pF/(~m) 4 Cj. Voltage References. gain.5 y r ds (n) = 8. Tasai. SC6.9 X 10. Wakayama.8 Y I/ 2 Y = 0. pp. January 1982.
41) holds for the voltage reference of Fig. If a commonmode noise signal of 5 ~A appears on I I ' what is the size of the output signal due to that noise signal" Repeat for a commonmode noise signal on I. Assuming V SEO 2 .10 Assume the SIH of Fig. and the capacitor ratio C I/C 2 • Take the ztransform of this difference equation. 8. where V ref.4 Assume the second stage of the S/H of Fig.11 8..21 has each of D. This means that diodes and BJT transistors are available. 8. what is the value required for K in order to get zero temperature dependence at T .23). Design a clockdriver circuit so that the clock voltages go from two diode drops above the input voltage (in track mode) to two diode drops below the output voltage (in hold mode).5. where I. Consider the gain cell shown in Fig. Also assume the input signal is a 5MHz sinusoid with a 2 Vpop amplitude and the clock signals are at 20 MHz and go between +2.10 Problems 371 8. 8. Show the voltages at all nodes for the cases of sampling a I V input and a I V input for before as well as after track mode.15 Consider the translinear multiplier shown in Fig. 8.5 8. with rise and fall times of 1. .7 Assume the SIH of Fig. Derive the output voltage of the SIH of Fig.25. 8. .15 when the ~' s of the transistors' worstcase mismatch is 5 percent.19 at the end of <il.6 8. and i I is set such thatthe gain io/i. Assume two transistors in a PTAT are biased at a currentdensity ratio of 8 : I at T . 8.5 V. ei wT to find the frequencydomain transferfunction of the S/H. is high).22) and (8.5 to 4. 2.5 V and 2.65 V.8..15 has a finite gain of AD' Derive the output voltage in terms of Vin and An during hold mode (i. and D6 replaced by two series diodes. 8.f elk 8. I . Assume the opamp in the SIH of Fig. is fixed to a bias current of 200 ~A while II varies such that the gain changes from 0. 0. What are the extreme values of I t needed" Also.5 ns. What is the sampling time uncertainty? 8. 0. felk> where f elk is the sampling frequency. show that t 3 dB 8..13 8. 320 OK for a currentdensity ratio of 8: I in the two transistors? 8.8 1C = 2nC. assuming all transistors should remain in the active region with at least 20 ~A of emitter current? 8. where II . in terms of the input voltage at the end of <ill' the output voltage at the end of <ill from the previous period.5 V.12 is being realized in a BiCMOS process. 320 OK.9 8. 200 ~A. I. 8. Making the assumption that e iwT es 1+ jroT for 00« (liT) .10 has a gain of 30 and a unitygain frequency of 100 MHz. What is the difference in their baseemitter voltages and what is its temperature dependence? . and substitute z .e. when <il. Prove that equation (8. 8. .30. 100 ~A. Find values for the bipolar reference of Fig.14 Prove equations (8.27(b). what is the maximum peak current that should be used for iot.29. 8.12 8.16 Repeat Problem 8.
Assume a 5 V power supply is available. .17 Design a fourquadrant translinear multiplier having differential voltagecurrent conversion stages based on entitler degeneration at both inputs and a differential voltage output.372 Chapter 8 • Sample and Holds. All transistors should be biased at 0. Valtage References.2 rnA. and Translinear Circuits 8. Design the multiplier so that when both differential inputs are I V the differential output should be I V.
. xc(!)' is band limited through the use of an antialiasing filter (not shown)..1.(t) x(n) = x.(nT) ND converter . This chapter presents some basic concepts of discretetime signals and filters. a discretetime filtering technique known as switchedcapacitor filtering is probably the most popular approach for realizing fully integrated analog filters. 9. Switchedcapacitor filters are in the class of analog filters since voltage levels in these filters remain continuous. For example. where it is assumed that the continuoustime signal. Convert to impulse train (a) X'h(t) x..(t) Sample and hold x(n) = x. DSP refers to Discretetime signal processing.(!) (b) Fig.CHAPTER DiscreteTime Signals A basic understanding of discretetime signal processing is essential in the design of most modern analog systems. which may be accomplished using fully digital processing or discretetime analog circuits such as SWitchedcapacitor filters. discretetime signal processing is heavily used in the design and analysis of oversampling analogtodigital (AID) and digitaltoanalog (D/A) converters used in digital audio and instrumentation applications. switchedcapacitor filters operate and are analyzed using discretetime steps but involve no AID or D/A converters.1 Performing DSP on analog signals.(nT) Convert to discretetime sequence YIn) Y.(t) Hold Y'h(t) Analog lowpass filter Y.. yen) Y'h(t) D/A converter with hold Analog lowpass filter Y.1 OVERVIEW OF SOME SIGNAL SPECTRA Consider the spectra of sampled and continuoustime signals in the block diagram systems shown in Fig. (a) Conceptual realization. Some sIt) x.(t) . 9.(t) x. and (b) typi cal physical realization. In other words. Also. 373 . 9.
1 and 9. where T equals the inverse of the sampling frequency. The remainder of this chapter confirms these spectral relationships and introduces other basic discretetime concepts.2 Some time signals and frequency spectra. Some relationships for the signals in Figs. ~ 21. xs(t). 9. 9. but the baseband spectrum repeats every Is (assuming that no aliasing occurs and hence. an antialiasing filter is needed). s(t) is a periodic impulse train in time with a period of T. Xc(t). 2. but the sampling frequency is normalized to I. related to the continuoustime signal. ~ 1 0 n $~X(ffi) (21tl o)/l. Is. Here.2. f'J) 21t ~ 41t ~ffi A~ fo Time X'h(f) .(f) x(n) 10 ~ I. ~ f Frequency Fig. example time signals and frequency spectra for this system are shown in Fig. Xs(t) has been scaled by 1 such that the area under the pulse . x(n) has the same frequency spectrum as xs(t). Xs(t) has the same frequency spectrum as xc(t).rp I.2 LAPLACE TRANSFORMS OF DISCRETE·TIME SIGNALS Consider the sampled signal.(f) t 10 ~ 1 I. cy> 21. 9. 3.3. as shown in Fig. $~X.2 are as follows: 1. multiplying Xs(l) by this response helps to remove highfrequency images). 9. Here. The frequency spectrum for Xsh(t) equals that of Xs(t) multiplied by a response of (sin x)/x (in effect. 9.374 Chapter 9 • DiscreteTime Signals A~X.
we have xc(nT) xs(nT) = . Txs(nT). We define '}(t) to be the step function given by '}(t) " { I o (I < 0) (I~O) (9. "'" xc(nT)e· snT (9.9. 5. and so we plot tx.jt) instead of Xs(t). xsn(t).3) so that we can now write xs(l) as Xs(t) = n =_0<> I.nT Xsn(s) = ~ S xc(nT)e s (9. so we can find the Laplace transform of xs(l) in terms of xc(I). where Xsn(t) is zero everywhere except for a single pulse at n T.4) Note that these signals are defined for all time.. Using the notation that Xs(S) is the Laplace transform of xs(I). Thus. equals xc(nT).5) Since xs(t) is merely a linear combination of xsn(I). xsn(I).(t) (Single pulse at nT) Fig.. can be written as xc(nT) ['}(InT)'}(InT T)] T (9.9. (All pulses) nT TX. we find the Laplace transform Xsn(S) for xsn(l) to be given by I(Ie''') . at t = nT. The singlepulse signal. as T > 0.2) Then xs(t) can be represented as a linear cornsination of a series of pulses. xsn(l) (9. at nT equals the value of xc(nT)..1) such that the area under the pulse. In other words.3 Sampled and continuoustime signals. the height of xs(t) at time nT goes to ce .6) n =QO .T (9. we also have (for T '" 0) Xs(S) = ~C : )I.2 Laplace Transforms of DiscreteTime Signals 375 .
is given by SUul) . by performing this convolution either mathematically or graphically. for a discretetime signal. when T 4 0.) (9. Specifically.8) where s(l) is a periodic pulse train.13) Equations (9. X s{JUl) . note that. or mathematically. Xs(l) . To use this fact. can be found by replacing S by j co in (9. the spectrum of sit). shown in Fig. !.6) goes to unity.13). Xs(1 ± kl s)' where k is an arbitrary integer as seen by substitution in (9.11) where 0 denotes convolution. It is well known that the Fourier transfurm of a periodic impulse train is another periodic impulse train. in the limiting case as T 4 0. and therefore no aliasing occurs if XcUul) is band limited to I s/2. 1 + x + (x'/2') +"'. 2. .XcUul) 0 Stjco) 2rr (9.8) in the frequency domain. 9. I TL k= 0'0 XcU2rrl .376 Chapter 9 • DiscreteTime Signals Using the expansion eX .7).jk2rrl s) (9. we have (9. L o(co_ k k ==_DO ~ 2. Finally. the term before the summation in (9. xc(l)s(l) (9. we have XsUul) . L n == 0(1 .13) also confirms the example spectrum for Xs(I). Xs(t) can be written as the product xs(l) . I ~ TL k == X (.9) where 0(1) is the unit impulse function. s(I). x/I).10) Now writing (9. j k2rr) c JUl  T (9. also called the Dirac delta function. xs(I).7) n ==_DO Spectra af DiscreteTime Signals The spectrum of the sampled signal. Therefore. the spectrum of XsUul) can be seen to be given by .12) and (9.12) or. SUUl).2. Note that. a more intuitive approach to find the spectrum of xs(t) is to recall that multiplication in the time domain is equivalent to convolution in the frequency domain. The relation in (9.13) show that the spectrum for the sampled signal.nT) (9. equivalently. equals a sum of shifted spectra of xc(I). However. Xs(l) . for T 4 0.
note that the signal xs(t) cannot exist in practice when r > 0 since an infinite amount of power would be required to create it. (Integrating Xs(l) over all frequencies illustrates this remark. Specifically. then Y(z) = H(z)X(z). One way of thinking about this series of numbers as they relate to the samples of a possible continuoustime signal is that the original sample time. where ® denotes convolution. ZkX(Z) 2.9. Specifically.k) . in both time and frequency. justifies the spectral relation between Xs(l) and X(ltl) shown in Fig. Two properties of the z transform that can be deduced from Laplace transform properties are as follows: 1.3 zTransform 377 Finally. the signal xrm is simply a series of numbers that may (or may not) have been obtained by sampling a continuoustime signal. Similarly: multiplication in the time domain is equivalent to convolution in the frequency domain. = I Hz). equivalently. T.e. whereas Xs(S) is the Laplace transform of the signal xs(t) as t > O. In other words. whereas the original continuoustime signals have frequency units of cycles/ second (hertz) or radians/second. .17) This normalization results in discretetime signals having 0) in units of radians! sample..14) we can write (9..) 9.) (9. Convolution in the time domain is equivalent to multiplication in the frequency domain. the relationship between Xs(l) and X(ltl) is given by Xs(l) = X ( 2rrl t:.15) n =_DO where X(Z) is called the z. For example. 9.transform of the samples xc(nT)... Specifically. Such a normalization of the sample time. Note that Xiz) is not a function of the sampling rate but is related only to the numbers xc(nT).. has been effectively normalized to one (i. defining (9.2. a continuoustime sinusoidal signal of I kHz when sampled at 4 kHz will change by rr/2 radians between each sample. If xrn) . then x(n .16) or. the ztransform is merely a shorthand notation for (9. X(Z).3 zTRANSFORM For our purposes..7). T. if yen) = hen) ® x(n).. I. the following frequency scaling has been applied: 2rrl ltl = Is (9.
EXAMPLE 9. . for X(w). . Other examples of discretetim~ sinusoidal signals are shown in Fig.. . '. 15 .. . n . . For a more detailed discussion of this unit topic. 1/ . .. . How does Xuo) differ between the two sampling rates'? Solution By sampling at 12 Hz. . For example. 15 " (b) . .(f) is sampled at 12 Hz.1 Consider the spectra of Xc(f) and X. normally discretetime signals are defined to have frequency components only between 1t and 1t rad/sample. . . . . . ... It should be noted here that discretetime signals are not unique since the addition of 21t results in the same signal. resulting in the signals shown in Fig..(f).(f). 9.5. . . . . .9. . Therefore. . ... .. such a discretetime signal is defined to have a frequency of 1t/2 rad/sample. . : . is 4 Hz. the spectrum of Xc(f) repeats every 12 Hz.(f) and X. . . . 12 Hz is normalized to 21t rad/sample. ... . .. whereas for X2(w ). 4 Hz is normalized to 21t rad/sample.. . 10 \. shown in Fig. . .2. . see [Proakis.. Note that. . 1992].. .. Thus. . where X. . . . n n/4 rad/sample = 1 /8 cycles/sample n/2 rad/sample = 1/4 cycles/sample (d) (c) Fig. ..4 Some discretetime sinusoidal siqnols.. Compare the time and spectrum plots of X. . . . .. . 9. . . ..4. 9. .. . 5 . ..378 Chapter 9 • DiscreteTime Sigoals x(n)  x(o) n 5 10 15 ii n/8 rad/sample x(O) Orad/sample = 0 cycles/sample = 1/ 16 cy~les/sample (a) x(nj . . . . . ' . . . a discretetime signal that has a frequency of 1t/4 rad/sample is identical to that of 91t/4 rad/sample. where fa is I Hz and f.
the result of downsampling is to expand the original spectra by L. one can show that the spectra of the resulting n ~ ~OJ n M 2rr I"m 0 4n 6 L = 4 M 2n ~ OJ 6 Fig. whereas upsampling is used to increase the sample rate. . In this case. the spectra of the original signal must be band limited to 1t/L before downsampling is done. Upsampling is accomplished by inserting L .9.TT'1mTTlITTr+ t • f (n) 12 Hz (Zrt ) 24 Hz (4n) «(j) ) Fig.6 shows. 9.7. As Fig.9. and (b) frequency domain. Downsampling is used to reduce the sample rate (hopefully.I zero values between samples.4 Downsampling and Upsampling 379 • f 8 Hz (4n) ( (j)) +~~~u.5 Comparing time and frequency of two sampling rates. Downsampling is achieved by keeping every Lth sample and discarding the others. Although noninteger downsampling and upsargpling rates can be achieved. Thus. 9. here we consider only the case in which L is an integer value. the signal must be sampled L times above its minimum sampling rate so that no information is lost during downsampling. to avoid digital aliasing. In other words.9. 9A DOWNSAMPLING AND UPSAMPLING Two operations that are quite popular in discretetime signal processing are downsampling and upsampling..6 (b) Downsampling by 4: (a) time domain. as shown in Fig. without information loss).
(n) in Example 9.. the original signal should be band limited to niL. if we .2 As an example of downsampling of the signal x. Specifically. the new series is x.e.9. X 7.. X 3. . This operation is useful when one wishes to increase the effective sampling rate of a signal. when every third sample is kept and the others are discarded (i. In other words. X4 (ro). EXAMPLE 9. find the new spectrum. if the original series of numbers is Solution XI' x 2. Note that no information was lost in this example because the initial images of the signal x. In fact. the frequency axis is scaled by L such that 2n now occurs where L2n occurred in the original signal. Follow the next two examples carefullythey help explain the spectral changes due to downsampling and upsampling.1..1. and thus its spectrum is simply X 3(ro) = X(ro). .1.7 41t M 21t m (b) jMMMM 1t 1t ~ m 6 21t Upsampling by 4: (a) time domain. .e. find the new spectrum. Clearly the solution here is that the new sequence is equivalent to xm) in Example 9.. if two zeros are inserted between each sample (i. . upsampled signal are identical to the original signal but with a renormalization along the frequency axis. EXAMPLE 9. it can be shown that.380 Chapter 9 • DiscreteTime Signals n ~4 (a) ~ n Lb o 6 Fig.(ro). and (h) frequency domain. X. particularly if postfiltering is then applied..(n) were far enough apart. to avoid any aliasing during downsampling by the factor L. X\O' . . when we downsample by 3). X 4. if the downsampling operation results in the spectra overlapping one another. x4 . However. then an aliasing phenomenon occurs that is similar to that which occurs when sampling an analog signal lower than the Nyquist rate. when a signal is upsampled by L.3 As an example of upsampling of the signal x(n) in Example 9.
In other words. . The resulting signals are shown in Fig. x..9. where it is zero between its impulses. . where the sampling frequency is normalized to 2n. and the Laplace transform is used to observe its frequency response.8. In other words. recall that it is simply a frequency normalization of X'4(f).(ro) in Example 9. With such a sampling frequency. Time 8 Hz (~J Fig. the effective sampling rate might be thought of as 12 Hz. 9. then the resulting signal will equal x 2(n).. In other words. Thus. if the original series of numbers was xrn) = x.. but now the images at 4 Hz and 8 Hz remain in contrast to X. Finally. the normalization is effectively being done for a time period smaller than that between nonzero impulses. by inserting extra zeros between samples. Xl' x. However. and had a spectrum Xuo). To find X 4(ro) . 0. note that if signal processing is used on the samples x 4(n) to eliminate the two images at (2n)/3 and (4n)/3. In this example..9. we note that xsil) is equal to the signal x. Recall that x'4(1) is defined for all time. since two zeros are inserted. . 0. the series xrn) is simply a normalization of the time between impulses to I. Solution Perhaps the simplest way to conceptualize the insertion of these extra 0 samples in a series is to look at Xs4(1) in time and frequency when we let IS4 = 12 Hz. then the new series of numbers is now x 4(n) = (x.1. we can use upsampling and digitalsignal processing to derive signals that are the same as if the analog signal were sampled at a much higher rate.) and has a spectrum Xiro). as long as an analog signal is originally sampled higher than the Nyquist rate.4 Downsompling and Upsompling 381 upsample by 3). the images remain the same while the normalization along the frequency axis is different. 0. x" 0.(I).8 12 Hz (2rr) Frequency f'I:\ 16 Hz ~ f (83rrJ «0) Spectrum of a discretetime signal upsompled by 3..(l). and thus X s 4(1) = X.
In other words. For example. An example of a discretetime. This filtering of discretetime signals is most easily visualized with the shorthand notation of ztransforms. is an impulse (i.18) The poles for this filter are determined by finding the roots of the denominator polynomial. often one wishes to perform filtering on a discretetime signal to produce another discretetime signal.5 DISCRETETIME FILTERS Thus far.9.9. This continuoustime filter is also defined to have two zeros at oo since the denominator polynomial is two orders higher than the numerator polynomial.. hm). the transfer function of a lowpass.382 Chapter 9 • DiscreteTime Signals 9.9 Discretetime filter system. . which are .6z + 0.J'~L Hrz) I L~ yin) (y(n) equals h(n) if um) is an impulse) (Discretetime filter) Fig.05 z' .e. and two zeros are again at cc . might appear as (9. however. and the substitution 5 = jro is equivalent to finding the magnitude and phase of vectors from a point along the jOJ axis to all the poles and zeros. except that. However. To find the transfer function of Hrz). hm). we have seen the relationship between continuoustime and discretetime signals in the time and frequency domain. polynomials in z are obtained.19) Here. Frequency Response of DiscreteTime Filters The transfer functions for discretetime filters appear similar to those for continuoustime filters. where the output signal is defined to be the impulse response. urn) .8 ± 0. lowpass transfer function is given by the following equation: H(z) = 0. which is the ztransfonn of the impulse response.IO(a». Hc(s). instead of going along the vertical jro axis as in the splane. The transfer function of the filter is said to be given by Htz). when the input. To find the frequency response of Hc(s). an input series of numbers is applied to a discretetime filter to create an output series of numbers. the poles and zeros can be plotted in the splane (Fig. Consider the system shown in Fig. the poles now occur at 0. 1 for n = 0 and o otherwise).0 ± 1.65 (9.1 j in the z plane. instead of polynomials in 5. continuoustime filter.7321j for this example. um). 9. 9. the poles and zeros can be plotted in the zplane.1.1.
.J""'f". 10) Continuoustime.14). Note that substituting z = el'" in the zdomain transfer function. 90 kHz. To simplify notation. 100 Hz.9. 9. 1 zplane <0=0 x X (POles) .. However. In summary. e l "' . . 10 kHz.10 Transfer function response. the unit circle contour is used.. 9. for filters with real coefficients. the poles and zeros always occur in complexconjugate pairs (or on the real axis). and 100 kHz. 50 kHz. so the magnitude response of the filter is equal to that for rr 5 ro 5 2rr (the filter's phase is antisymmetric). Going around the circle again gives the same result as the first time.10. I kHz. and Ib) discretetime. Before we leave this section.4 Assuming a sample rate of Is = 100 kHz. a word of caution is in order.9. co is different for the two domains..e.. so that z = e l "' . ro = 0) and at ro = 2rr.e. note that .19) for 0 Hz.. they would affect the phase response. Also note that poles or zeros occurring at Z = 0 do not affect the magnitude response of Hrz) since a vector from the origin to the unit circle always has a length of unity. I = Is) for Xs(I). these variables are not equal in the two domains.5 '\ High frequency DiscreteTime Filters iro 383 splane <0 J<O = j<o 00 = 1t/2 ':lIl. implying that the frequency response repeats every 2rr. In addition. EXAMPLE 9. and care should be taken not to confuse values from the two domains..10(b). is simply a result of substituting 5 = jro into (9. find the magnitude of the transfer function in (9. (0 = 2 31t (b) Fig. where T has been normalized to I. the unit circle. (a) Ii' dc j<o = 0 (()=1t j . is used to determine the frequency response of a system that has its input and output as a series of numbers. We see here that in the discretetime domain... z = I corresponds to the frequency response at both de (i. Also.. . I and co. However.!he frequency response of a filter need be plotted only for 0 5 co 5rr (i. are used in both the continuoustime and discretetime domains in Fig. as shown in Fig. whereas the jmaxis is used for a system that has continuoustime inputs and outputs.3.. Hiz). as discussed in Section 9. the time normalization of setting T to unity implies that co = 2rr is equivalent to the samplingrate speed (i. the same variables.e. The continuoustime domain is used here for illustrative reasons only since the reader should already be quite familiar with transfer function analysis in the sdomain. e . 05 ro 5 Is/2) since. However.
9.0 + jO. Find the value of 00.0 0.1 I e iO eJo.(J~1l 10 50 90 100 e j O.a). where the zero is not shown since it is at DO. where 0 < a < I..1.384 Chapter 9 • DiscreteTime Signals Table 9. since their z plane locations are the same.20) . we need be concerned only with the magnitude of the denominator of Hrz) and when it becomes larger than its de value. The magnitude of the denominator of Hiz) for Z = 1 (i.O 1. I s/2 = 50 kHz. when it becomes write. Note that the gain of Hiz) is the same at both 0 Hz and 100 kHz. J2 J2 h2 I . Finally.149 0. as expected. note that the minimum gain for this transfer function occurs at Z = I.11.1 I. Next. Is.5 Consider a firstorder Hrz) having its zero at = and its pole on the real axis.809 . Table 9. Also. first we find their equivalent zdomain locations by normalizing Is to 2n. Ii I EXAMPLE 9..968 0. does it correspond to? Solution Consider the polezero plot shown in Fig.5878 1.O 0. Mathematically.06279052 0. where the magnitude of Hrz) is 3 dB lower than its de value.2 1l e'" e J Ui lt e j21l 1.0154 0.8'1 What fraction ofthe sampling rate.0 + jO.809 + jO. Thus we can unit circle and is shown as I.1 Findingthe gain af H(zj at same example frequencies z plane locations Frequency (kHz) z = x + jy IH(zll o 0.0 Solution To find the magnitude of Hrz) at these frequencies.9997 0. or equivalently.e. Since the zero is at 00. we find the gain of Hrz) by putting these zdomain values into (9. What is the 3dB value of 00 for a real pole at 0.0 + jO.9980267 + jO. in Fig.1 summarizes the results.149 1.19) and finding the magnitude of the resulting complex value. This vector changes in size as z goes around the larger than I.O 09999803 + jO.= e I'"~ a" "L(Ia) (9.OO628314 0.jO.()O~1l eJo. de) is shown as the vector I. the transfer function is represented by Hiz) = b/(z .5878 . 9. the gain is the same at both 10 kHz and 90 kHz since their zplane locations are complex conjugates of each other.
128. or 12. Stability of DiscreteTIme Filters To realize rational polynomials in z. 9.wehave l(cos(ro)a)+jsin(ro)I' = 2(1a)' cos'{ro) . Writing a iw = cos(ro)+jsin(ro).8. S·1 building blocks). discretetime filters use delay elements (i.5 zptane DiscreteTime Filters 385 1 J2(1a) 1 j I.(2a) cost eo) + a' + sin'{ro) = 2( 1 _ a)' 1(2a) oos(ro)+a' = 2(12a+a') which is rearranged to give the final result.22) (9. this equation is written as zY(z) = bX(z) + a Y(Z) where the zdomain property of delayed signals is used. Consider the block diagram of a firstorder.e.23) ro = cos "(2 zia a 1) (9.=(la) Fig. 1. We define the transfer function of this system to be Htz) given by .84 degrees.9.e..21) (9. ro = 0.2241/(211) times Is or.11 Polezero plot used to determine the 3dB fre quency of a firstorder. The result is that finite difference equations represent discretetime filters rather than the differential equations used to describe continuoustime filters. discretetime filter shown in Fig. A finite difference equation describing this block diagram can be written as yen + I) = bx(n) + ay(n) (9. z' building blocks) much the same way that analog filters can be formed using integrators (i.. 9. Such a location on the unit circle corresponds to 0. equivalently.2241 rad. discretetime filter.24) For a = 0.25) (9. (9.26) In the zdomain.04.12.
y(O) = k where k is some arbitrary initial state value for y. Hrz) sa Y(z) = b Xiz) z.. I for n = 0 and 0 otherwise). Although this stability result is shown only for first order systems.28) Clearly.25). as expected. and one can show that the system oscillates at 1. we let the input. linear. 9. is given by h (n) = (n < 1) 0 { (a"'b+a"k) (n z t ) (9.e.27) which has a pole on the real axis at z = a. IIR and FIR Filters Infiniteimpulseresponse (IIR) filters are discretetime filters that. and the system is marginally stable (in fact. the response. it is a discretetime integrator). discretetime filter. this places the pole at Z = I. ) . in the preceding firstorder example. in general. assuming infinite precision arithmetic. h(n).386 Chapter 9 • DiscreteTime Signals y(n + 1) b xtn) . For example. discretetime filter. if a = I.a (9.12 A firstorder. according to (9. timeinvariant. In other words. xm). y(l)=b+ak y(2) = ab + ak y(3) = ./2. Locating some poles on the unit circle is similar to poles being on the imaginary jro axis for continuoustime systems. be an impulse signal (i.~ a y(n) Fig. Hrz). which gives the following output signal. if Zpi are the poles. If we let a = I. is stable if and only if all its poles are located within the unit circle. their outputs remain nonzero. then IZpil < 1 for all i. the pole is at Z = I. To test for stability. an arbitrary. a'b + a''k 4k y(4) = alb + a More concisely. when excited by an impulse. For . this response remains bounded only when [a] 5 I for this firstorder filter and is unbounded otherwise.
has a slowly decaying impulse response). However..5 DiscreteTime Filters 387 example. Thus. Bilinear Transform With modem filter design software. it remains nonzero for a finite value of n. their outputs go precisely to zero (and remain zero) after a finite value of n. the filter given in (9. y(n) = 3[x(n)+X(nI)+X(n2)] I (9. the value of T can be chosen arbitrarily as long as the same value is used in each transformation. Finiteimpulseresponse (FIR) filters are discretetime filters that. but they all occur at Z = O. although its impulse response decays to zero (as all stable filters should). but with a much lower order. Applying an impulse signal to this filter results in an output that is nonzero for only three samples and.1)/ (Z + 1) I where T is the sampling period. . Some advantages of FIR filters are that stability is never an issue (they are always stable) and exact linear phase filters can be realized (a topic beyond the scope of this chapter).27) is an IIR filter (for a not equal to zero) since. an IIR filter can meet the same specifications as an FIR filter. for many specifications. the bilinear transform is defined as 5 ::: (2/T) [( Z . As an example of an FIR filter.30) This filter is essentially a running average filter since its output is equal to the average value of its input over the last three samples.31) The inverse transformation is given by z = 1+ P Ip (9. another approach draws on the wealth of knowledge of continuoustime transferfunction approximation and uses the bilinear transform. when excited by an impulse. However. Note that this FIR filter has poles. desired discretetime transfer functions that meet specifications can be obtained entirely within the discretetime domain.29) Defining the transfer function for this filter to be Hrz). the bilinear transform is defined to be given by! p = zI z+ 1 (9.e. particularly in narrowband filters in which the poles of an IIR filter are placed close to the unit circle (i. we have normalized T to 2 since we use the bilinear transform only as a temporary transformation to a continuoustime equivalent. this is an FIR type filter. It should be noted here that in many other textbooks. and then we inverse transform the result back to discrete time.32) I. therefore. Assuming that Hc(p) is a continuoustime transfer function (where p is the complex variable equal to O'p + jn). consider the following filter. Here. we can easily show that (9.9.
35).31).4. with a little analysis. 2j sin(rol2) . e. 0. find the 3dB frequency of a firstorder discretetime filter. we will see that this bilinear transfonnation also maps the unit circle. Z . Note that the order of Hrz) equais that of Hc(p) since. .e. we substitute Z .34). map to n equal to 0 and =.2213 rad/sample.Jtanro 2 cos(rol2) Thus.8 and zero of I are mapped to a pole at 0. according to (9. However.31). . (/2) ./2) are mapped to pplane locations of 0 and ee.11111 rad/s. respectively. such that Htz) es Hc[(zI)/(z+I)] With such an arrangement. Solution Using (9. we see that the zplane pole of 0.8 and a zero at1. To see this mapping. HcU tan(rol2)] (9. ej(ffiI2 J( ej(ml2) _ e j(ml2») p . 0. Note that this result is very close to that in Example 9. or 1. in the zplane to the entire jn axis in the pplane. Hrz).36) (9. ej(ffil2)(ej(ro!2) +e j(ffil2)) (9. Such a continuoustime filter has a 3dB frequency at n .388 Chapter 9 • DiscreteTime Signals A couple of points of interest about this bilinear transform are that the zplane locations of I and I (i.34) As a check.35) and so the response of Hrz) is shown to be equal to the response of Hc(p).128. note that the zplane locations of I and I. Using (9.34). respectively. each p term is replaced by another firstorder function. EXAMPLE 9. and choose the discretetime transfer function. that has a pole at 0. elm.6 Using the bilinear transform. wefind that the equivalent 3dB frequency value in the z plane is given by ro .5. respectively. which correspond to OJ equal to 0 and n . However. except with a frequency warping according to (9. one can show tharH(eij . and we have n .m into (9. de and 1. Hrz). the two results are not in exact agreement since a zero at I is also present in this example.. tan(rol2) Z plane are mapped to locations on (9. we see that points on the unit circle in the the jn axis in the pplane. Hc(p).11111 and to a zero at co in the pplane.33) . One way to use this transform is to design a continuoustime transfer function.
find a firstorder Hrz) that has a 3dB frequency at Is/20.7265 The constant k can be determined by setting the de gain to I. we look at the frequency response that occurs when we change a discretetime signal back into an analog signal with the use of a sampleandhold circuit. Such a 3dB frequency value is obtained by having a p plane zero equal to co and a pole equal to 0.7 Using the bilinear transform.39) . Transforming these continuoustime pole and zero back into the zplane using (9. a zero at I. Therefore. Thus.6 SampleondHald Response 389 EXAMPLE 9.34).1584. xsh(l). xsh(l) is well defined for all time. A sampleandhold signal.0. is related to its sampled signal by the mathe matical relationship Xsh(t) = n L ==_cc x c(nT)[1'l(InT)1'l(InT . once again. the frequency value.37) Note that.e S L <>0 xc(nT)e. Solution Using (9. Hrz) appears as Hrz) = k(z + I) z .1584 rad/s.314159 is mapped to n = 0. Note that here we plot a frequency response for all frequencies (as opposed to only up to I s / 2 ) since the output signal is a continuoustime signal rather than a discretetime one. or equivalently. Hc(p) should have a 3dB frequency value of 0. is equal to Hsh(s) = 1. Hsh(s).eST S (9.7265. I s 120 .32) results in a zplane zero at I and a pole at 0. or equivalently.1584 rad/s. 9. and thus the Laplace transform can be found to be equal to sT Xsh(S) = 1.T)] (9. which results in k = 0.snT n =_000 (9. IH(l)j = I.9. OJ = (2rr)/20 = 0.1368.38) I _ esT = Xs(S) S This result implies that the hold transfer function. and a de gain of 1.6 SAMPLEANDHOLD RESPONSE In this section.
Fig. a I. It should be noted here that this frequency shaping of a sample and hold occurs only for a continuoustime signal. the images of x(n) are all of the same height (i. Assume . find the magnitude of the output signal.9. 9. Multiplying this sine response by X.8 ~ For a lOkHz input sinusoidal signal of I V rms. Sampleandhold response (also called the sine response]..390 Chapter 9 • DiscreteTime Signals 31. in fact. The spectrum for Hsh(s) is found by substituting 5 = jro into (9. a sample and hold before an AID converter simply allows the converter to have a constant input value during one conversion and does not aid in any antialiasing requirement. It should be mentioned here that this transfer function is usually referred to as the sampleandhold response although.8 Consider the discretetime signal processing system shown in Fig. and at the images 40 kHz and 60 kHz.13.e.1(b).(f) in Fig. Y'h(I).j roT12 xsin(roTI2) sh jro (roT12) The magnitude of this response is given by (9.39).41) and is often referred to as the (sin x)/x or sine response.h(l) having smaller images at higher frequencies (due to the sine response). resulting in H (j'ro) = l_e. I. 9. EXAMPLE 9.2 confirms the spectral relationship for X'h(f). where a sample (and clock rate) of 50 kHz is used and the digital filter has the response Htz) = z0. 21. although the sample and hold before the AID converter shown in Fig. 9. 9. 31.40) IH or en (jroll = T1sin(roT1211 IroTl21 (9.jroT = Txe. This magnitude response is illustrated in Fig.I(b) would result in x. they are not multiplied by the sine response) since it is a discretetime signal.13 21. it only accounts for the hold portion. at 10 kHz. In other words. Specifically.
Vaidyanathan. Analog MOS Integrated Circuit.j = e j04' = cos (04)· . P.1 mV ems' respectively. New Jersey. 9. the magnitude of H(z) is found for a lOkHz signal when the sampling rate is 50 kHz by noting that e j(2. Oppenheim and R. Schafer. C. and Applications. Ternes.7 REFERENCES R. [H(e i04 ' )[ = 0. G. we need only multiply the filter's gain by the sine response shown in Fig.k) H Z'X(Z). New York. Also assume the converters complement each other such that a IV de signal into the AID converter results in a IV de signal from the DI A converter if the converters are directly connected together.8 Problems 391 the quantization effects of the AID and DI A converters are so small that they can be ignored.9355 = 175 mV ems (note that the T term cancels with a similar T term due to the creation of a discretetime signalsee (9.1559. the magnitude of the sampleandhold response for a lOkHz signal when using a 50kHz clock is equal to IH sh (10 kHz)1 = T sin(ltlO/50) = 0.93551 (ltlO/50) and therefore the magnitude of YSh(l) at IG. 9. Proakis and D. John Wiley & Sons. A. Macmillan.95 10571 To determine the magnitude of YSh(l) at various frequencies.9. New Jersey. Digital Signal Processing: Principles. 1993. It + jsm .13. 1989. then x(n . the magnitude of Hsh(f) at 40 kHz and 60 kHz is 0.2). DiscreteTime Signal Processing. Englewood Cliffs. (04 It ) . P.1 Show that if x(n) H Xtz). = 0./50 kH. 9.309017 .309017 + jO. G. 1992.8 PROBLEMS 9.8) + jO. x 10 kH.2 What is the maximum amount of downsampling that can be applied to xS2(n) in Example 9. Solution First.186864 1(0. respectively. Specifically.2399 and 0. New York.95 1057 and therefore the gain of Hrz) for a lOkHz signal is found to be given by. Manolakis. Prentice Hall. Similarly. Gregorian and G.1 before aliasing occurs? . 9. Algorithms.0. V. resulting in the magnitude of Ysh(l) at 40 kHz and 60 kHz to be 43.kHz is equal to 18686 x 0. Englewood Cliffs. 1986.13) in Section 9. Prentice Hall. Multirate Systems and Filter Banks.2 = 0. W. J.'> for Signal Processing.7 and 29.
A 100Hz sinusoidal signal. Repeat Example 9..05z z .1 kHz.4 9.7 9.6 9. at 100 Hz.3 9.14 9. }. Find the location of the poles and zeros of the transfer function given by H(z) in (9.10 9. but assume an input signal frequency of 100 Hz and find the magnitude of the output signal. which describes a filter with input urn) and output yrn).. xm).9 kHz.1 kHz. insert 7 zeros between samples).11 9.13 9.12 9. Hrz) = 9. Before any smoothing filter is applied and assuming the magnitude of xsh(l) at 100Hz is I V rmswhat is the magnitude of xsh(l) at 300 Hz? Also. but upsample by 8 (i. what is the magnitude and phase response for Hrz) at lsi 4? Check the frequency domain result with the time domain result.0. Find the location of the pole required in a firstorder filter that has its zero at oc such that its 3dB frequency is at IJ 10. a maximallyflat passband (i. when its input is a sinusoidal waveform of peak height 1 at lsi 4 and its initial state is zero. 99. a zero atI. In other words. Give a block diagram showing how one might convert 020 kHz bandlimited audio signal from a sampling rate of 50 kHz to 40 kHz. Upsampling and downsampling are often used for converting between two sample rates. as well as the location of the 3dB frequency.13. Hrz).9 kHz and at 10. by finding the gains at de and at (J) = n . Is downsampling a linear operation? Repeat Example 9. find the magnitude of xsh(l) at 500 Hz and at 700 Hz . Find a firstorder Hiz) that has a 3dB fr~quency at I s/30. 0. and a de gain of 1.392 Chapter 9 • DiscreteTime Signals 9. 9. when the impulse is I at n = 1 and 0 otherwise) assuming y(O) = O. 0.e.15 . is digitally created using a 400Hz sampling rate producing a sampleandhold signal. find an H(z) to realize a secondorder transfer function with a de gain of one. Using a bilinear transform.e.5 Is downsampling a timeinvariant operation? If so.8.. 0. .8 0. I.3.. the input waveform is the series of numbers { I. I.e. Using a frequency analysis. and find the magnitude of xsh(l) at 9.. If not. Sketch the magnitude response (in dB) of the following transfer function. explain. Find the output sequence of a discretetime integrator. Hrz) = I I(z .O. Sketch the magnitude response from (J) = 0 to (J) = 21t.I) Determine y(n) when u(n) is an impulse (i.I). but assume the lOOHz signal is digitally created using a lOkHz signal. I. Repeat Problem 9.95 9.3y(n . y(n) = um) . and 100. and a 3dB frequency at I kHz when the sampling rate is 100 kHz. ysh(I). Q = 1I Ii in the continuoustime domain).9 Consider the following difference equation. give a simple counter example. xsh(l).19).
If the microphone output is sampled at 100 kHz. firstorder frequency response with a pole at 10 kHz. how much attenuation is required in the antialiasing filter for 80dB noise rejection around 100kHz? .8 Problems 393 9.16 A 05kHz voiceband microphone is modelled as having a lowpass.9.
1 percent). capacitors. Hosticka. This chapter will introduce the basic principles of switchedcapacitor filters as well as some other nonfiltering functions realized using switchedcapacitor circuits. switchedcapacitor circuits have become extremely popular due to their accurate frequency response as well as good linearity and dynamic range. However. Young. clock frequencies can also be set very precisely through the use of a crystal oscillator. and modulators. 1977. Fortunately. switches. Opamps The basic principles of switchedcapacitor circuits can be well understood assuming ideal opamps. A switchedcapacitor circuit operates as a discretetime signal processor (although without the use of AID or D/A converters). Brief descriptions of each of these blocks and their important nonidealities with respect to switchedcapacitor circuits are given in this section. switchedcapacitor circuit techniques can be used to realize a variety of other signalprocessing blocks such as gainstages. As a result. 1972. Such an accuracy is orders of magnitude better than that which occurs for integrated RC tjple constants (which can vary by as much as 20 percent). these circuits are most easily analyzed with the use of ztransform techniques and typically require antialiasing and smoothing filters. 1977.1 BASIC BUILDING BLOCKS A switchedcapacitor circuit is realized with the use of some basic building blocks such as oparnps.CHAPTER SwitchedCapacitor Circuits Perhaps the most popular approach for realizing analog signal processing in MOS (or BiCMOS) integrated circuits is through the use of switchedcapacitor circuits [Poschenrieder. voltagecontrolled oscillators. Fried. Caves. In addition to creating filtering functions. some important opamp nonidealities in practical switched 394 . 1966. its overall frequency response remains a function of the clock (or sampling) frequency. and nonoverlapping clocks. 10. Once the coefficients of a switchedcapacitor discretetime filter are accurately determined. 1977]. Accurate discretetime frequency responses are obtained since filter coefficients are determined by capacitance ratios which can be set quite precisely in an integrated circuit (on the order of 0. As a filtering technique.
C p l . is known as the bottom plate capacitance. doubling the load capacitance would halve the unitygain frequency and improve the phase margin. or between two metal layers. Of less concern is opamp input impedance as it is essentially capacitive assuming MOSFET input stages are used. there also exists a substantial parasitic capacitance. which may be as large as 20 percent of C l . slewrate. Modern SC circuits are often realized using highfrequency singlestage opamps having very large output impedances (on the order of 100 kQ or much larger). C p 2 . C p 2 . since the substrate below the poly2 layer is an ac ground (the substrate is connected to one of the power supplies or analog ground). which also serves as the compensation capacitor. in these singlestage opamps. Since the loads of these opamps are purely capacitive (never resistive). A top plate capacitance. A general rule of thumb is that the clock frequency should be at least five times lower in frequency than the unitygain frequency of the opamp assuming little slewrate behavior occurs and the phase margin is greater than 70 degrees. However. unitygain frequency and phasemargin. is formed as the intersection of area between the two polysilicon layers. Fortunately. polyl and poly2. A nonzero dc offset can result in a high output de offset for the circuit depending on the topology chosen.1 Basic Building Blocks 395 capacitor circuits are de gain. a techniqueknown as correlated double sampling can significantly reduce this output offset and at the same time reduce low frequency opamp input noise (known as Ilf noise). The unitygain frequency and phase margin of an opamp gives an indication of the small signal settling behavior of an opamp. Thus. as shown in Fig. Capacitors A highly linear capacitance in an integrated circuit is typically constructed between two polysilicon layers. The thin oxide is an insulating layer separating the two relatively conductive polysilicon layers. while the thick oxide is also an insulating layer but of much thicker width. 2.I(a)2 These capacitors are known as doublepoly capacitors. I The de gain of opamps in a MOS technology intended for switchedcapacitor circuits is typically on the order of 40 to 80 dB. The finite slew rate of an opamp can limit the upper clock rate in a switchedcapacitor circuit as these circuits rely on charge being quickly transferred from one capacitor to another. Thus. Low de gains affect the coefficient accuracy of the discretetime transfer function of a switchedcapacitor filter. their de gains remain high despite the lack of an output buffer stage. The desired capacitance. It is also possible to realize capacitors between other layers such as polysilicon and heavilydoped silicon. It should be noted here that their unitygain frequency and phase margin are determined by the load capacitance. it is not uncommon for opamps to slewrate limit. at the instance of charge transfer.10. . C l . L BIT input stages are rarely used as they would result in charge leakage due to their nonzero input bias current. This large parasitic capacitance. and de offset. 1O.
10. a relatively low on resistance (so that the circuit can settle in less than half the clock period). and introdu ce no offset . and have on resistances in the 100 0 to 5 kO range depending on transistor sizing. consider the ideal nchannel tran sistor switch shown in Fig.2. C pt. 10. Alth ough a switch can be imp lemented using a single transistor. Leakage current is typically dominatedb)" reverse biased diode.. as MOSFET switches have off resistances in the GO range. where the bottom plate is often expli citly shown to indicate that a larger parasitic capacitance occurs on that node . to ground exists on the bottom pla te of C 1 while a smaller para sitic capacitance. For exampl e..Y The use of MOSFET transi stor s as switches satisfies these requirements. as shown in Fig. As a convent ion. C. the signal range of the switch is reduced . In summary. the sig nal <I> is one of two logic levels typic ally corresponding to the maximum and minimum powe r supply levels. rather thanthe MOSFETchannel which i ~ assumed off. the switch is assumed to be on (i. 10. as shown in Fig.8 V. 1 A daublepoly ca pacitor.1(b ). The switch can 3. 2. voltage when turned on (as does a bipol ar switch whose on volta ge equals VeEls.2(b) being used in a circuit having power supplies of 0 to 5 V and a threshold voltage of V'n = 0. . also exist s due primarily to the interconnect capacitance. Th e symbol for a switch and some MOSFET circuit s that reali ze a switch are shown in Fig.396 Chapter 10 • SwitchedCa pacitor Circuits Cross section (a) Equivalent circuit (b) Fig. shorted) . Here. 10.e. C.2(c).2(b) and Fig. Switches The requirements for switches used in switchedcapacitor circ uits are that they have a very high off resistance (so little charge leakag e occurs).' have no offset on voltages. Nate tha t a large parasitic ca pocitanc e. exists on the top plate . the equivalent model for a single integrated capacitor is three capacitors.. when the clock signal <I> is high. but it is typically much smaller (on the order of I to 5 percent of G I ) . 1O. 1O.
1O.0 to 5 V. I Basic Building Blacks 397 o u.2. This combination is commonly called either a CMOS switch (as opposed to an NMOS switch of Fig. the term nonoverlapping clocks refers to two logic signals running at the same frequency and arranged in such a way that at no time are both signals high. 1O. the signal range for this switch is limited from 0 to 4. while channel charge injection is reduced by careful switch timing. 1O. A similar argument can be made for the pchannel switch shown in Fig. as seen in Section 10.V or around 4. ~ (d) Fig.n Nonoverlapping Clocks At least one pair of nonoverlapping clocks is essential in switchedcapacitor circuits.. Nonlinear capacitance effects are alleviated through the use of parasitic insensitive structures.. channel switch. . . as discussed in Section 10.10....2(c) except that its signal range would be limited from 1. Thus. As seen in Fig.TL. the full signal range of 0 to 5 V can be achieved using two transistors in parallel. and capacitive coupling from the logic signal. Note that the time axis in Fig. 10. (b) n ... [c] pchannel switch. the switch can only equalize the two voltages if V I and/or V2 are lower than V DD . These clocks determine when charge transfers occur and they must be nonoverlapping in order to guarantee charge is not inadvertently lost. While this signal range is acceptable in many situations.o (e) v.0 V taking the body effect into account. Such a normalization illustrates the location of the sample numbers of the discretetime signals that occur in switchedcapacitor filters. o. as shown in Fig... channel charge injection.2(d). (b) 1 1 <p~$ v..~v.2(a)) or a CMOS transmission gate.. T. Some of the important nonideal switch effects in switchedcapacitor circuits are the nonlinear capacitance on each side of the switch. in this case.2 Switch symbol and same transistor circuits: (a) symbol.. As a convention.. Idl transmission gate. 1O.. when the switch is on. However. its gate voltage will be VDD or 5 V.. we denote the sampling numbers . 1O.5..J"'L.0 V. to each side of the switch. v.3(a) has been normalized with respect to the clock period.3(a).. (8) c v. always be turned off irrespective of the input voltage by putting 0 V on its gate.
398 Chapter 10 • SwitchedCapacitor Circuits v. delay blocks are used to ensure that the clocks remain nonoverlapping. is deemed to be 1/2 sample off the integer values as shown (i. (n .2) . 1981]. (n . Here.. the locations of the clock edges of <il. To analyze this circuit's behavior.1/2). One simple method for generating nonoverlapping clocks is shown in Fig. ~$2 VOII [) [) [) 3 n2 1 n2 (a) 1 n+2 Q T P4~2  1 tiT (b) ~ Fig. into node V2 is given by (10. 1O. we analyze the circuit from a charge perspective. (n + I). !>O" that is transferred from node V. 1O.3 Nanaverlapping docks.. and <il.2 BASIC OPERATION AND ANALYSIS Resistor Equivalence of a Switched Capacitor Consider the switchedcapacitor circuit shown in Fig.3/2).) just before the end of clock phase <il" while the end of clock phase <il. 10. need only be moderately controlled to allow for complete charge settling (assuming separate lowjitter sample and holds are used at the input and output of the overall circuit). 101 Clock signals. it should be noted that it is not important that the falling clock edge of <il. C x' times the voltage across it. 2 n1 [) . Recall that the charge on a capacitor. v.). are assumed to be a pair of nonoverlapping clocks. and V.. However.3(b) [Martin. during each clock period. C I is charged to V.4 Q [) n+1 4tiT f. the change in charge (in coulombs) over one clock period. (n . In general. to be integer values (i. we have ax = CxV x (10. etc. occur precisely onehalf a clock period earlier than the falling edge of <ill . $.e. 10.e. where V. Vx ' In mathematical terms. are two de voltage sources.I).1) Now.  b~~. and <1>2' Ib} A possible circuit implementation of nonoverlapping clocks from a single dock. t Votta n $. Therefore. and <il. since <il.4(a). is equal to the capacitance value. These delays could be implemented as a cascade of an even number of inverters or perhaps an RC network. (n). etc. and then V. ax.
4 Resistor equivalence of a switched capacitor. and therefore the equivalent resistance is inversely related to the capacitance and clock frequency.e. IOA(a) will equal that forthe resistor circuit of Fig. Since this charge transfer is repeated every clock period.5) Note that the above relation makes intuitive sense. it should be noted that this resistor approximation is mainly useful for looking at the lowfrequency behavior of a switchedcapacitor circuit. is equal to the average number of coulombs/second and is given by I avg :. For moderate input frequencies (in relation to the sampling frequency).. Fig. Discretetime analysis can be used in switchedcapacitor circuits because the charge transfers are dependent on values of node voltages at particular instances in time and are ideally independent of transients during nonsampled times.V. Finally.: (10. lavg (in amps). the average current. In addition. the sampling frequency fs = I IT).3) where T is the clock period (i. a larger amount of charge is transferred each period. Req (lOA) we see that the average current through the switchedcapacitor circuit of Fig.10. If C I is increased.(V. so the average current is higher. we can find the equivalent average current due to this charge transfer by dividing by the clock period.. the same charge is transferred each period but at a faster rate. Relating (10.. increasing the average current is equivalent to decreasing the equivalent resistance seen between the two voltage nodes. an accurate discretetime analysis is required.V2 ) every clock period (a) Req = (b) T C. (oj Swltchedccpccitor circuit (b) Resistor equivalent. as discussed in the next subsection.3) to an equivalent resistor circuit shown in Fig.2 Basic Operation and Analysis 399 IlQ = C. 10. as the clock frequency is increased. IOA(b) if R eq =~=_ICI C. 10A(b) where leq = VI . In other words.f s (10. which would also increase the average current. . For example.
Now also at time (nT . To analyze this circuit. 10. ParasiticSensitive Integrator An example of one of the first switchedcapacitor discretetime integrators [Hosticka. In other words. Here.T) at time (n T .T) implies that the charge on C.T). 10. veo(I). . <PI is just turning off (and <P2 is off) so the input signal veil) is sampled. to indicate to the reader that the output sigI\il1 is valid at the end of <P I in keeping with the samplingtime convention shown in Fig. is equal to C2 v eo(nT . we again look at the charge behavior and note that a virtual ground appears at the opamp's negative input.). an extra switch is shown near the output voltage. 1977] is shown in Fig. Such a large impedance typically requires a large amount of CMOS silicon area if it is realized as a resistor without any special processing fabrication steps. This structure is sensitive to parasitic capacitances (not shown]. Assuming an initial integrator output voltage of veo(nT .1 What is the equivalent resistance of a 5 pF capacitance sampled at a clock Irequency of 100 kHz" Solution Using (10.3(a).T). it is not important because ve. a clock. and a relatively small capacitance. another circuit that uses the output of this discretetime integrator should sample veo(l) on <P I' Note however that no assumptions are made about when ve. we have 1 12 (5 x 10 )( 100 X 103 ) What is interesting here is that a very large impedance of 2 MQ can be realized on an integrated circuit through the use of two transistors.400 Chapter 10 • SWitchedCapacitor Circuits EXAMPLE 10. resulting in the charge on C I being equal to Fig.5. 10.(I) changes its value (it could be either <PI or <P.(I) is sampled at the end of <PI by the circuit shown.5).S A discretetime integrator.
T 12) and we can combine (10. nT) as indicated by the switch shown near vco(t) in Fig.10. and therefore a negative output voltage. 6(bl $2' . At the end of JIl2 (once things have settled out).vco(nT) = C. as shown in Fig. to be given by ZI Htz) " Vo(Z) = . 1O.C I vc. c. we note that once JIl. V.(nT .(nT) and vo(n) = vco(nT).9).8) (10. When JIl2 goes high.v. we also have Vo(Z) = Z·IVo(Z) .7) to write C.<nT ." (a) Fig. However. To find this charge.5. the charge on C 2 at time (n T) at the end of the next Jill is equal to that at time (rrT .6 The parasiticsensitive integrator circuit for the two clock phases: (a) $.2 Basic Operation and Analysis 401 C.(n) = vc.11) c. or mathematically.6) is correct. we can write the charge equation (10. its switch forces C I to discharge since it places a virtual ground on the top plate of C I' as shown in Fig. thus. ~oo. 10.vco(nT) = C.<nl) Taking the ztransforrn of (10.6) The negative sign in (10.vco(nT .CIZ'IV. 10. C. .T) (10. Htz).T) . Note that a positive input voltage will result in a negative voltage across C.5: vo(n) = Vo(nl)C. this discharging current must pass through C 2 and hence the charge on C I is added to the charge already present on C 2 .10) from which we can finally find the transfer function. I  Z·I (10.(Z) CI (10. 10.9) C2 ( 10. Therefore. turns off.7) Dividing by C 2 and using the discretetime variables v.T). the charge on C 2 will remain the same during the next Jill' until JIl2 turns on again in its next cycle.6(a). the integrator is an inverting integrator.(z) C.6) and (10.vc.(CIJ .T/2).6(b). Although (10. we would like to find the charge on C 2 at the end of Jill (or equivalently."'.vco(nT . we have the following discretetime relationship for the circuit of Fig. 1O.6) reflects the fact that the integrator is an inverting integrator.
I ..11) approximates the transfer function of an ideal continuoustime integrator... which is equivalent to taking the sampled voltages and then using them as inputs to a sample and hold for this particular SC integrator.l. z .....JDL.. .. ..... the voltages are constant at other times (ignoring secondorder effects).. the transfer function would be rewritten to eliminate terms of Z having negative powers to give Vo(Z) Htz) es Viz) = lC. Often.:.rr~ V OO ~2t_:_.... ~t ~t ___ () __.._.. It does not say anything about what the voltages are at other times..2 Show that for frequencies much less than the sampling frequency..7. equation (10...__.._~.~t Fig.._ .._DL... 10....::~. EXAMPLE 10.5.402 Chapter 10 • SwitchedCopocitar Circuits "l:==o... Note here that the discretetime equation derived only represents the relationship of the voltage signals vetC!) and vco(t) at the time (n T).... : .. 10. !] {\.. In actual fact. and thus the transfer function can be accurately defined in an integrated circuit.l . ...._...I (C. Note that this transfer function realizes its gain coefficient as a ratio of two capacitances.. \ 'd'Hr~....12) Some typical voltage waveforms for this discretetime integrator are shown in Fig._..L""""~~r.7 Typical voltage waveforms for the discretetime integrator shawn in Fig..) I (10. 10......JD_ _DL. which occurs just before the end of <1>.
13) + j sinun'T) (10.. The ZIIO in the numerator represents a simple delay and can be ignored.16) into (10. we see that the transfer function is approximately that of a continuoustime integrator having a gain constant of roT K. the input capacitance of the oparnp. C p 4 accounts for the bottom plate parasitic capacitance of C 2 as well as any extra capacitance that the opamp output must drive.11) can be rewritten as C 1] Z1I2 Hz) . while C p3 represents the parasitic capacitance associated with the top plate of C 2.2 Basic Operation and Analysis 403 Solution Equation (10.13) gives Htz) = ( ~:] T ] = j2 sin( ~ (~:J ~:~ (10. Finally. the period. .10.8. and that of the <1>0 switch. (10. C p2 represents the parasitic capacitance of the bottom plate of C 1. 10.16) Substituting (10. Here.14) where T.J.\ ZIIO (10.17) for « 1. = (~) CoT (10. The addition of such parasitic capacitances results in the circuit shown in Fig. C p 1 represents the parasitic capacitance of the top plate of C 1 as well as the nonlinear capacitances associated with the two switches. we make use of the fac: that Z = e iwT = costro'T) (10.C ZI12_Z112 ( .(2 To find the frequency response. is one over the sampling frequency. JroT] SI. Therefore.15) and (10. Thus.18) which is a function of the integrator capacitor ratio and clock frequency only. Thus far we have ignored the effect of the parasitic capacitances due to the creation of C 1 and Co as well as the nonlinear capacitances associated with the switches.15) and = cos Z1I0 roT 2 (2 ].
z~ I (10. 1978] allowed the complete filter to be insensitive. 1978. 10. we see that the gain coefficient is related to the parasitic coefficient C p l . 10. although it may affect the speed of the opamp. 1978]. whereas the inverting integrators (Fig. Jacobs. ingenious circuits known as parasiticinsensitive structures were devel oped [Martin. C l is effectively "hooked" up backwards. 10. When <1>2 turns on. v c. and therefore the transfer function of this discretetime integrator including the effects of parasitic capacitance is given by l Htz) = . Analyzing this circuit as before. The development of the parasiticinsensitive inverting integrator [Martin. C. Such . Also. 1978]. we can immediately discard the effect of C p2 since it always remains connected to ground. as shown in Fig. and the discharge now occurs through what was the ground node rather than the input signal side. In accounting for these parasitic capacitances. as shown in Fig. we note that C p l is in parallel with C. 1O. ParasiticInsensitive Integratars The parasiticinsensitive integrator was a critical development that allowed the realization of highaccuracy integrated circuits. 1978.9) were parasitic insensitive. To overcome this deficiency. which greatly decreased secondorder errors.19).9. as shown in Fig.IO(b). 1978. In the first integrated integratorbased filters. Allstot. Jacobs. C p4 is connected to the opamp output. (nT . two extra switches are used. Finally. is charged to C. the noninverting integrators (Fig.8 A discretetime integrator with parasitic capacitances shown.8) were parasitic sensitive [Allstot.404 Chapter 10 • SwitchedCapacitar Circuits ~P4 vrm Fig.C + C P I] . Similarly. it would not affect the final settling point of the opamp output. 10. 10.T).19) From (10. To realize a parasiticinsensitive discretetime integrator. the effect of C p3 on the transfer function is small since it is always connected to the virtual ground of the opamp.I ( C. therefore.IO(a). which is not well controlled and would be partially nonlinear due to the input capacitances of the switches and topplate parasitic capacitance. note that when cl>l is on.
ZI  C 2 1 . However during <I> . With the rest of the analysis being performed as before.20) Note that (10.T 122(b) Fig. since C p2 always remains discharged (after settling). ' Ibl ~2' . v. Here.= V.(nT . the transfer function.11. Hiz).I) does not affect the charge that is placed on c. Therefore.2 Basic Operation and Analysis 405 c.8. Z to give (10.20) represents a positive discretetime integrator with a full delay from input to output (due to the ZI in the numerator. 10.21) To investigate the behavior of this noninverting integrator with respect to parasitic capacitances.on./nT .10.. it also does not affect the operation of the circuit. which represents a oneperiod delay) so we refer to the circuit of Fig.10 The nan inverting discretetime integrator an the twa clack phases: 101 ~.(Z) (C I] .9 as a delaying discretetime integrator.(n) and discharged to ground. 10. As was done for the stray sensitive inverting integrator of Fig. C p3 and C p 4 do not affect the operation of the circuit as before. v.(n) Fig. a reverse connection results in veo(l) rising for a positive ve. the fact that C p I is also charged to v.(nT _ T) ~ ~~ (a) rCl~ .(z) C.9 A non inverting delaying discretetime lnteqrotot. and therefore the integrator is noninverting./nT  C. consider the same circuit drawn with parasitic capacitances. C p2 is either connected to ground through the <\>1 switch or to vir tual ground through the <1>2 switch. for this discretetime integrator is given as Vo(z) Hrz) " .ZI (10.jnot sensitive to parasitic capacitancesj. one often rewrites the transfer function to eliminate negative powers of I] Hrz) es V = (C z 11 o(Z) V. C p l is continuously being charged to v.(n .. as shown in Fig. 10. vco(t) v. Finally.T). 10. 10. v. In addition.
...(z) . . but with the two switch phases on the switches near the input side of C I (that is. However.(n) V. With this arrangement..(nn. At the end of <ilIon... C.12 [Martin. In summary. 10.22) Also note that C I is fully discharged at the end of <il2 on. we can write (10. To obtain an inverting discretetime integrator that is also parasitic insensitive...( n) . in effect changing the charge on C 2 by that amount. Thus... Therefore.J"'C... 10. 10.. When <il2 is turned on. C pl is discharged through the <il2 switch attached to its node and none of its discharging current passes through C I to affect the charge accumulating on C 2 .. the topplate of C I) interchanged as shown in Fig.12 A delayfree discretetime integrator (not sensitive to parasitic capacitancesj.. Now when <ill is turned on. the charge left on C 2 is equal to its old charge (before <ill was on) subtracted from the charge needed to charge up C I to vc..L V.. while the parasitic capacitances may slow down settling time behavior.23) C2 vi n) V.v. the same circuit as the parasiticinsensitive noninverting integrator can be used. 10..L . 1978]..406 Chapter 10 • SwitchedCapacitor Circuits $. we have the following charge relationship: (10. c $. the current needed to charge C 1 passes through C 2 ..(z) ~' $. .9.. C I is charged up to Vc. >. Fig. $21'1. note that the charge on C 2 does not change when <il2 turns on (and <ill is off).J"'C. they do not affect the discretetime difference equation that occurs in the integrator shown in Fig.(l). Fig. it also does not affect the circuit operation.11 A parasiticinsensitive integrator with parasitic capacitances shown. Therefore.
(nT .= . we have vo(n .(z) ~[CI)_Z_ C.10. the transfer function.22)..I) . since the charge on C.(Z) C. a few rules can be developed to create and analyze such circuits.T).2 Basic Operation and Analysis 407 Note that vc. Substituting in (10.26) Finally.(z) and V 3(Z) are given by C 2) ( ZI ) = [ C A IzI (10. SignalFlowGraph Analysis Clearly. we note that its relationship to Vo(z) is simply an inverting gain stage given by (10. Consider the threeinput integrator shown in Fig. dividing by C" and switching to discretetime variables. it is clear that the inputoutput relationships for V.28) For the input V I(Z). Using the principle of superposition.13. and sign changes can be achieved by simply crosscoupling output wires.24) Taking the Z transform of both sides. 10. . while the delaying integrator has a positive gain. note that the above delayfree integrator has a negative gain. (10.27) (10. 1. many modern integrated circuits make use of fully differential signals for improved noise performance.m) C1 (10. Hrz). at the end of <1>1 is related to the value of vc. v. for this delayfree integrator is found to be 1 Vo(z) Hiz) " . While these sign changes in the gain can be quite useful in singleended switchedcapacitor designs. and therefore the integrator is considered to be delay free. Z ~ I (10.[C ) IV.ZI (10.25) is often rewritten as H(z) " Vo(Z) = V. As before.25) where the fact that the numerator has a purely real term is indicative of the integrator being delay free.(nT) occurs in the above equation rather than vc.C.29) with the output once again being sampled at the end of <I> 1 as shown.(nT) at the same time. So instead. applying the charge equations just described would be quite tedious for larger circuits.
we see that to obtain an equivalent signal flow graph. and (10. Combining (10. 1O. If a delaying switched capacitor is used.13(b). it is represented by C 2 Z. should be sampled on l\>1 when the switchedcapacitor inputs sample their input signals on l\> I' As before. however. for a delayfree switchedcapacitor input. this transfer function might often be rewritten in powers of Z rather than ZI. Note. a gain factor of C I(I . Finally.29).Fig. that the output.31) . (bJ Equivalent signal flow graph.30) Such a relationship can also be represented by the signal flow graph shown in Fig. the block (IICAH I /(1 .13 Threeinput switched capacitor summing/integrator stage.ZI) is used. 1O. where the input stages have been separated from the opamp stage.cZ)JC )V 3(Z) lCA lCA zI lCA zl 3J(_Z (10. For a nonswitched capacitor input stage. while three different gain factors are used to represent the possible input stages. (oj Circuit. a gain factor of C 3 is used. (10.28). 10. resulting in Vo(z) = JSJVI(Z) + (C'J(_I)v. the inputoutput relationship for the circuit of Fig. Vo(Z).27).13(a) is equal to (10. Thus.I.ZI)1 is used to represent the opamp stage.
14 A firstorder activeRC filter.15. as do resistive inputs). for signal frequencies moderately close to the clock frequency. the behavior of the switchedcapacitor circuit is precisely determined through the use of the z domain signalflowgraph approach just discussed.10. zp' given by (10. An equation that describes this signal flow graph is (10.14.32) from which the transfer function for this firstorder filter is found to be Hrz) _ = lZl ~ 3 + C CA (10. . However.34) Fig. The resulting firstorder switchedcapacitor filter and its equivalent signal flow graph are shown in Fig. To obtain a switchedcapacitor filter having the same lowfrequency behavior. the resistors are replaced with delayfree switched capacitors (delayfree inputs are used since they create negative integration.33) The pole of (10. Such an equivalence is often used to derive good switchedcapacitor filter structures from their activeRC counterparts. 10. a switched capacitor is equivalent to a resistor.3 FirstOrder Filters 409 10. which results in a pole location. although such structures would behave very similarly for lowfrequency input signals (when compared to the clock frequency). A general firstorder activeRC filter is shown in Fig. while the nonswitched capacitor feed in is left unchanged.3 FIRSTORDER FILTERS We saw on page 398 that at low frequencies.33) is found by equating the denominator to zero. 10. 10.
.35) Therefore. it becomes a discretetime integrator.(z) " " C A ~. The zero of (10. this zero location is also restricted to the real axis between zero and one. " C 3 Vi(z) c..36) Finally. in other words.. V. In this way. the de gain for this circuit is found by setting z = 1. +C. which results in a zero location. as expected.5C. it should be noted that in a fully differential implementation.. Additionally. and therefore the circuit is always stable. Ibl equivalent signal flow graph.(1z. C. C3 (10. with C 3 = 0 the circuit's pole is at z = lor.37) . a zero at z = 1 could be realized by setting C...n. zz. In fact.. this pole is restricted to the real axis between zero and one. given by Zz = ' C.410 Chapter 10 • SwitchedCapacitor Circuits " C..1. which results in the de gain being given by H(1) =  c. (10.') (b) (~J1 _1 _ Z 1 Vo(z) Fig...J.. (10. C.15 A firstorder switchedcapacitor filter: (al circuit [no switch sharing). >. effective negative capacitances for C" C" and C 3 can be achieved by simply interchanging the input wires. = 0. Note that for positive capacitance values. (a) V o(z) . 10. for positive capacitance values.33) is found by equating the numerator to zero..
the frequency warping between the two domains. Clearly.I )/(z + I) as described in Section 9. is given by Hrz) = k(z+l) z . the zero at I is mapped to n = ee. making use of the bilinear transform p = (z . n = tan(w/2). zp' of value = . would be half the size of those representing C 2 and the input wires interchanged into the C.33) (and assuming C A = 10 pF) results in .43762 1.3044 This pole is mapped back to a z p Z domain pole.3044 2in the continuoustime domain.53327 where k is determined by setting the de gain to one (i. Hrz).3 Find the capacitance values needed for a firstorder switchedcapacitor circuit such that its 3dB point is at 10 kHz when a clock frequency of 100 kHz is used.0. the pair of capacitors representing C. maps the 3dB frequency of 10 kHz (or 0.(z) is applied to that input branch.3 FirstOrder Filters 411 In other words.= 0. In addition.3044 rad/s and a zero at cc ..21t) = 0. Hrz) = 0. EXAMPLE 10.. Therefore.10.23337(z + I) z .e. It is also desired that the filter have zero gain at 50 kHz and the de gain be unity.53327 1+ Pp 1. Pp' required here is Pp = 0. Assume C A = 10 pF.43762z + 0. the continuoustime pole.5. our specification is now simplified to find the pole location for a continuoustime filter having a 3dB frequency equal to 0.Pp Therefore.0. the desired discretetime transfer function. H(l) = I) resulting in Hrz) = 0.I Equating these coefficients with those of (10. Solution First note that having a zero gain at 50 kHz is equivalent to placing a zero at 1. Now. pair such that V.53327 or equivalently.87522z .21t rad/sample) in the Z domain to n = tan ( 0.
Setting the numerator of (10040) to zero gives the following approximate equation for the zero frequency: jro T = z .15) and (10. C. we have Vo(z) H(z) _ (~}ZI/'_Z1I2)+(~}112 = Zll2 _ Z1I2 V.16) into (10. I CA CA (10040) 3 A troT ) = C3 j ( 1+· 2C )mT+C C A The procedure just used is quite useful when finding a continuoustime transfer function that approximates a discretetime transfer function.(z) + 3 _Z1l2 C CA (10.c o(OOT) .2C + C. it is not necessary to prewarp the specifications using the bilinear transform.• 412 Chapter 10 • SwitchedCapacitorCircuits C I = 4.39) j 2+C 2 C 2 ( C3) sin (OOT) + C cos (OOT) A A 00T «I This transfer function is exact. Making the approximation be simplified as troT) allows (10.39) to v o(e V.2. Rather. some approximations can be used to derive equations for the capacitor ratios given the desired zero and pole. using (10.(C + C. sI CA 2 CA 3 2 JroT ) (10.38) Substituting (10.376 pF C. I (10041) 1+ 2C I Similarly.33).752 pF where a differential input can realize the negative capacitance.(e J . sm (OOT) +C. For designs where the zero and pole frequencies are substantially less than the clock frequency (unlike the previous example.752 pF C 3 = 8.38) gives lroT) Vo(e V.I2}T+C. which had a zero at onehalf the clock frequency). As in Example 10. = 8./C C. setting the denominator to zero gives the following approximate equation for the pole frequency: .(e J . which are both assumed to be real and positive.
. + . . we see that the lowfrequency gain is given by C. 1O.. For unity gain. = 1.3 FirstOrder Filters 413 ( 10042) EXAMPLE 10. Solution Using (10042) and solving for C 3/C A . .. • $... are always switched to the opamp's virtual ground and true ground at the same time. Specifically./C]. 10. V/z) $..4 Find the capacitance values C 1 needed for a firstorder lowpass switchedcapacitor filter that has C.. From (10040) with C. Switch Sharing Careful examination of the switchedcapacitor filter shown in Fig... one pair of these switches can be eliminated and the two top plates of C.:rr. = 1. Fig. then we have C. and C 3 can be connected together. this means we need C..032 pF as well. as shown in Fig. = 0 and a pole at the l/64th sampling frequency using the approximate equations. The lowfrequency gain should be unity.~ ~$.. 10. and C. we have C3 CA = wp T lwpT/2 = 21t/64 121t/128 = 0.10.16.032 pF.15(a) reveals that some of the switches are redundant. the top plate of both C. c.16 A firstorder switchedcapacitor filter with switch sharing. = 0.1032 (lOA3) If we choose C A = 10 pF.. c. Vo(z) $. $. Therefore. .
the differential output signal.44) where k. which might lead one to believe that it would consume twice the amount of integrated area. the increased area penalty is not that high. To see this distortion improvement. 2k 1v 1. Secondly. If the nonlinearity is memoryless. Vdm. for simplicity. to maintain the same dynamic range due to (kT)/C noise. Having balanced circuits implies that it is more likely noise will occur as a commonmode signal due to the symmetry of the circuit. First. note that the input and output signal swings have now been doubled in size. 10. In this case.17.17 Demonstrating that evenorder distortion terms cancel in fully differential circuits if the distortion is symmetrical around the commonmode voltage. Fully differential signals imply that the difference between two lines represents the signal component. most modern switchedcapacitor circuits are realized using fully differential structures. Thus. consider the block diagram shown in Fig. Fig. the commonmode voltage is assumed to be zero. we see that only one opamp is needed although it does require extra commonmode feedback circuitry. while for differential signals it is 4 V. then the maximum peaktopeak signal swing of singleended signals is 2 V. 10. v. For example. and oddorder distortion terms (which are typically smaller than the secondorder term). where the two nonlinear elements are identical and. Here. 10. the differential signal will have only oddorder distortion terms (which are often much smaller).414 Chapter 10 • SwitchedCapacitor Circuits Fully Differential Filters While the circuits seen so far have all been shown with singleended signals. the v. Fully differential circuits should also be balanced. Fortunately. A fully differential realization of the firstorder filter is shown in Fig. in most analog applications it is desirable to keep the signals fully differential. With these two important advantages. implying that the differential signals operate symmetrically around a de commonmode voltage (typically. the commonmode voltage is assumed to be zero. are constant terms. consists of only the linear term. then the outputs can be found as a Taylor series expansion given by (10. and thus any noise which appears as a commonmode signal on those two lines does not affect the signal. . analog ground or halfway between the powersupply voltages).18_ Note here that the fully differential version is essentially two copies of the singleended version. if singleended signals are restricted to ± I V. Fully differential circuits have the additional benefit that if each singleended signal is distorted symmetrically around the commonmode voltage.
as follows: 4.4 BIQUAD FILTERS Similar to the firstorder case. the switch size widths may also be reduced to meet the same settlingtime requirement. the signal power goes up by a factorof four. or <1>. 10.10. However. good switchedcapacitor biquad filter structures can be obtained by emulating wellknown continuoustime filter structures. Ha(s). capacitors in the fully differential version can be half the size of those in the singleended case.resultingin a signaltonoise ratioequal to thatof a singleended circuit having capacitors twice as large. Fully differential circuits would have twice the noise power of singleendedcircuitshaving the same size capacitors due to there being two capacitive networks generating noise." Since smaller capacitors can be used. or <1>. When the signal voltage doubles. also as in the firstorder case. once a filter structure is obtained. . This exact transfer function. + + + Vo(z) C3 C. However. LowQ Biquad Filter A directform continuoustime biquad structure can be obtained by rewriting the general biquad transfer function. C3 CA + V. is then used when determining capacitor ratios during the design phase. the fully differential circuit has more switches and wiring so this circuit will be somewhat larger than its singleended counterpart.4 Biquad Filters 415 C.2. However. C.18 A fully differential firstorder switchedcapacitar filter. its precise frequency response is determined through the use of discretetime analysis using the signalflowgraph technique discussed in Section 10. or a close approximation to it. Fig. 10.Cz) <1>. or <1>. recall that the fully differential circuit has the advantages of rejecting much more commonmode noise signals as well as having better distortion performance. Halvingthe capacitorsize of the differential circuitwould result in another doubling in noise power.
10. 1978]. the input capacitor K. is the major signal path when realizing bandpass filters. allowing negative resistors to be used. the input capacitor K.19.48) A signal flow graph describing the preceding two equations is shown in Fig.19 A signalflowgraph representation of a general continuoustime biquad fitter. Here.  (10. Now.47) and (10. C A and C B . 1979]. whereas k o ' k j . respectively. The input capacitor KtC t is the major signal path when realizing lowpass filters. 10. Multiplying through by the denominators and dividing by S2. and k 2 are arbitrary coefficients that place this biquad's zeros (i. (10. A switchedcapacitor biquad based on this activeRC circuit can be realized as shown in Fig.C 2 is the major signal path when realizing highpass filters.C. the numerator's roots).e. (10. (00 and Q are the pole frequency and pole Q. have been set to unity. all positive resistors were replaced with delayfree feedin switchedcapacitor stages while the negative resistor was replaced with a delaying feedin stage. Note that for convenience the integrating capacitors. (10.46) can be expressed as two integratorbased equations. . whereas. lO':20 [Brackett.45) S2 Vin(S) + (~} + (O~ Here. Specifically.416 Chapter 10 • SwitchedCapacitor Circuits Vout(S) .21 [Martin. Note that this switchedcapacitor biquad circuit has redundant switches. an activeRC realization of this general biquad signal flow graph is shown in Fig. as switch sharing has not yet been applied.45) can be written as (10.. + k 2 s Fig_ 10. k.46) Finally.
the negative resistor could also be replaced with a delayfree feedin stage where the differential input wires are interchanged. .. Before proceeding. C. r. but in addition. settling time behavior would not suffer as there would be two delays around the twointegrator loop. what is important is that the twointegrator loop have a single delay .". the use of fully differential circuits could result in quite a few other circuits. CA =1 Q~~o CB Ve.4 Biquad filters 417 . . K3C. Such a circuit would have a delayfree loop around the two integrators and may have an excessive settling time behavior.10.r~/k. all the positive resistors could be replaced with delayfree feedin stages as before. .flY' k.(S) =1 wolk o . In summary. but coefficient sensitivity would be worse for filters having highQ poles. Fig.. it is worth mentioning that while this switchedcapacitor filter is a natural result when using singleended circuits. some of which could have poor performance properties. As another example.21 A lowO switchedcopocitor biquad filter [without switch sharingJ. r. For example. n 1/m o .. 10. 10.. all resistors might be replaced with delaying feedin stages where positive resistors are realized by interchanging the input wires of those stages. In this case. l' K. .C.20 An activeRC realization of a general continuoustime biquad filter. Fig.
The transfer function. 1 II Ksz &+1z' K. this relation can also be used during design of a desired transfer function. 10.+r 1 1 _Z1 Vo(z) • Fig. 10. = b i + b 2 + I Note that there is some flexibility in choosing the values of K i. K 3(1z') J .+K 3)z +(KiKsK22K3')z+K3 V.21.54) (10.50). resulting in the following design equations: K 3 = a.2. . K2 = 8 2 a o (10. Such an arrangement is referred to as using lossless discrete integrators (LOl) [Bruton.418 Chapter 10 • SwitchedCapacitor Circuits around the loop.(z) (I + K 6)Z2 + (K.2)z + I 2 (10. Assuming the desired discretetime biquad transfer function has been found using a digitalfilter design program.z+biZ+1 2 2 (10.52) (10.53) (10. . and is given by Hiz) = a 2z +aiz+a O b.I K. places no constraint on the size of the signal at the internal node. This single degree of freedom occurs because specifying the overall transfer function. Hiz). 10. K 4 .49) While the preceding relation is useful for analyzing the switchedcapacitor circuit shown. Htz).K 6 ..22.50) we can equate the individual coefficients of z in (10. V. find the signal levels that occur at nodes Vi(z) K. Thus.K s .49) and (10.51) (10. 1975]. 10. Using the approach presented in Section 10.K. the signal flow graph for the biquad circuit shown in Fig.21 can be found and is shown in Fig. and K.55) KiK s = a o + 8\ + 8 2 K 6 = b. for this signal flow graph is found to be given by Htz) es Vo(z) = _ (K.22 A signal flaw graph describing the switchedcapacitar circuit in Fig. V/z). one way to choose appropriate capacitor values is to initially let Ks = I and determine other initial component values.(z) K 6 K.
59) Substituting these equations into (10. " oooT oooT " (10.. we further have iooT) jooT Vo(e H(e )" . K4 . (10. we see the following approximations are valid for the feedback capacitor ratios.62) (10.21 and using (10.15) and (10.56) Such a choice usually results in a near optimal dynamically rangescaled circuit. + jK 2 sin(ooT) + (4K J + 2K 2)Sin2 (¥ ) (10.(e lw K4K./2)(ooT)2 K4K.(Z) K IK.60) and the desired continuoustime transfer function at the resonant frequency. then using that signal level information.+jK.Z1/2)ZII2 + (Z1/2 _ Z1/2)2 (10. = cos ( 00T) Jsm (00T) 2 2 (10. T) V. K" and K6 (the capacitor ratios that determine the pole locations). an estimate of the largest to smallest capacitance ratio can be made by using the resistor approximation (10. 10. Specifically.61) The coefficients of (10.58) . then the approach used in Example 10.4 Biquad Filters 419 and Vo(z).5). . as is outlined in [Martin. A closer matching between transfer functions can be obtained if one chooses capacitor ratios to match the real and imaginary parts of both the numerators and denominators of (10.2 can be taken. Comparing Fig. + jK 6 sin(ooT) + (4 KIK.10. perform dynamic range scaling to find the final component values. the time constants of the two discretetime integrators can be set equal by choosing (10.49) can be rewritten as Vo(z) Hrz) sa .5) for this switchedcapacitor circuit.20 and Fig.= V.57) Rewriting (10.Z1/2)Z 1/2 + K3(z 1/2 _ Z1/2)2 K4K.61) can be matched to the desired coefficients of the continuoustime transfer function. K4 " K.57) and rearranging gives Vo(eiWT) JwT) V. 10.(e For 00T « 1. we have z 1/2 = cos(00 + j sin(00 2T) 2T) and Z1/2 (10. Alternatively. Finally. + jK6(ooT) + (I + K6!2)(ooT)2 (10. + K6(ZII2 .60) ~ 2K6)Sin2(~T) K IK. If it is desired to design the SC biquad so that its transfer function matches that of a continuoustime transfer function as closely as possible. + K2(z 112 . 1980].63) K6 Q .(ooT)+(K 3+K.16) here for convenience.
the largest capacitors (that determine the pole locations) in the switchedcapacitor biquad circuit of Fig. the sampling rate. w o .n(S)wOVc'(S)] 1 s  (10. if Q> I. One way to obtain a highQ switchedcapacitor circuit that does not have such a high capacitance spread is to eliminate this damping resistance in the continuoustime filter counterpart. as shown in Fig. when Q» I. I IT. replacing resistors with appropriate switchedcapacitor feedin stages.63) the smallest capacitor would be K6C Z ' resulting in an approximate capacitance spread of QI (w oT).420 Chapter 10 • SwitchedCapacitor Circuits However.23 An alternate realization for a general continuoustime biquad filter. 10. resulting in woT« I (10. the final highQ switchedcapacitor biquad circuit is shown in Fig. 10. passes through the first integrator stage and can be realized through the use of a capacitor. was a direct result of having a large damping resistance value of QI W o in Fig. then the smallest capacitors are K4C 1 and KsC z• resulting in an approximate capacitance spread of II (w oT). However.24. Note that here the damping path. 10. 10. s/Q coefficient.64) Thus. C.65) and (10.46) as Vout(s) = [k.21 are the integrating capacitors. 10. is typically much larger that the approximated pole frequency. 10. Once again. 1980].20. then from (10.66) The signalflowgraph representation of these two equations is shown in Fig. HighQ Biquad Filter The resultant highcapacitance spread in the preceding lowQ circuit. s/Q vou'<S) k. if Q < I.s Fig.25 [Martin. Such an elimination can be accomplished by rewriting (10. and C 2 · Additionally. .23.sV.
C.K s) 2 (10.25 A highQ switchedccpocitor biquad filter (without switch sharing). Other possibilities for realizing different types of functions exist.(s) k. K3C2 Fig. the input capacitor K.. but with an additional period delay.2)z + (l .2K 3)z + (K 3 . 10. then a noninverting bandpass function would result.= V.C.fy Vout(s) Fig.K 6 ) . the transfer function for this circuit is found to be given by Vo(z) Hrz) sa .2.fV k.. is the major signal path when realizing bandpass filters.(Z) K 3z' + (K1K s'+ K.. K..10. K2C.24 An alternate realization of a general activeRC biquad filter.67) z + (K 4K s + K sK6 .4 Biquad Filters 421 . Using the signalflowgraph approach described in Section 10. and the input capacitor K3 C.'" C. For example. '" I~ . 10. The input capacitor K1C 1 is the major signal path when realizing lowpass filters.K.= 1 1/0 C2 = 1 walko V. is the major signal path when realizing highpass filters.K. If the phases on the input switches of such a switched capacitor were interchanged.K s . .l W o I ~ 1/w o . a nondelayed switched capacitor going from the input to the second integrator could also be used to realize an inverting bandpass function.
results in the following capacitor values.50) to simplifythe resulting equations. (10.71) (10. = l+bo+b J K.73) K4K. After the biquad has been designed.69) K.422 Chapter 10 • SwitchedCapacitar Circuits Matching the coefficients of (10.Q circuit were used instead.67) to the coefficients of a discretetime transfer function given by5 Htz) = the following equations result: z a. This will give a good dynamic range but not necessarily optimum.70) (10.74) after which all other ratios follow. . (10.4729 5.572z + 0.288(z .a o a. = 0.72) (10.68) K1K s = (10. EXAMPLE 10. we see that there is some freedom in determining the coefficients as there is one less equation than the number of coefficients.9429 Find the largest to smallest capacitor ratio if this transfer function is realized using the highQ biquad circuit. = KJ = a. Htz) = _ 0. = 0. it can be analyzed and the ratios adjusted to equalize the maximum signal strength at the two opamp outputs.1. Compare the results to those which would be obtained if the low. A reasonable first choice might be to take (10. (10.69) to (10. = I in both cases. Let C J = C. making use of (10. K4 = K. Note that (10.75) Solution For the highQ biquad circuit.z + aJz + ao z +bJz+b o .I) z' .68) is written in slightlydifferent form than (10.b o As for the lowQ biquad.6090 KJ = 0 K.K 6 = 1.72) and assuming K4 = K. .K.5 The following transfer function describes a bandpass filter having a peak gain of 5 near fsllO and a Q of about 10.
0606z' . the choice of the circuits of either Fig. To realize higherorder switchedcapacitor filters. However. = 1.5 Chorge Injection 423 K. one can cascade a number of biquad and/or firstorder stages.76) which makes applying equations (10.25 (with switch sharing) is nearly optimum.21 or Fig. one can use lowersensitivity techniques such as signalflowgraph simulations of the relationships between the state variables of passive doubly terminated LC ladder filters. 10. The exception to this is for phase equalizers.56) easier.1. the authors have found that for the great majority of filtering applications.Q circuit the smallest capacitor is K6 C 1 ' which makes the capacitance spread about 11 to 1. which primarily sets the accuracy of the poleQ factor. We obtain the following ratios assuming K. This extra zero does not change the magnitude response.3054(z . K. the chargeinjection . we first rewrite (10. comparators that make use of switches suffer from chargeinjection errors.10. Fortunately.77) (10. an extra zero at z = 0 was added to avoid negative capacitances.5 CHARGE INJECTION As seen in Chapter 7. Alternatively. 1994]. where often feedins approximating negative resistors are needed. =0 K6 = 0.1) z 1. by turning off certain switches first. a general stage capable of realizing any z transform is described in [Laker. 10.80) (10.75) as Hrz) = _ 0. In addition.3054 = 0 = 0. The interested reader is referred to [Gregorian.0606 Thus the capacitance ratio for this circuit is determined by K6 .667z + 1 (10.51) to (10. in this high. For example.79) (10. For the 10wQ biquad circuit design. K1 K. resulting in a spread of near 17.81) = 0 = 0. It should be noted here that worse capacitance spreads will occur for this lowQ circuit if the pole Q is higher and/or the sampling frequency is increased relative to the passband edge.0938 Recalling that C 1 = C. K6 = K5 = 0. 10.78) (10. 1986] for detailed descriptions on the design of highorder SC filters. = K5 : K. There are many other biquadratic stages than the two presented here.6274 (10.
.26 A firstorder switchedcapacitor circuit with a dock arrangement to reduce chorqeinjection effects.j.. As a result. we see that the charge is related to the gatesource voltage as well as to the threshold voltage.. This same result applies to switchedcapacitor circuits. the 0 4 is the same from one clock cycle to the next amount of charge injected by and can be considered as a de offset. Which clock signals should be advanced is most easily explained with the following example. its channel charge is found from (10. more important reason for using this clock arrangement is that the charge injections due to 0 3 . . we saw in Chapter 7 that the channel charge of an NMOS transistor in triode is given by (10. where switch sharing is used.. When OJ and 0 4 are on. a. switches 0 largeswing signals.. is on.82) Here. when these switches are turned on they need only pass a signal near the ground node (not railtorail signals as might occur at opamp outputs).. these two switches can be realized using single n channel transistors rather than full CMOS transmission gates 6 A second. ViCz) _ . First. is always connected to virtual ground. VGS = V DO' and since their source remains at zero volts. while those of 01' 0 6 are signal dependent. Thus.. the same cannot be said of 0 1 and 0 6 • For example... Ltl~+! L_+_"~ '>. 10. V o(z) Fig_ 10.. <1>" and <1>" turn off 0 3 and slightly early. 0 4 are not signal dependent.. when a.. Typically. <1>1.. 6. their threshold voltages also remain constant. Here.. and thus chargeinjection effects can be minimized by having some clock signals slightly advanced with respect to the remaining signals. since <1>...83) C3 c. 1 0 6 would be realized as CMOS transmission gates since they may need to pass .82) to be a" (10. Specifically.!...424 Chapter 10 • SWitchedCapacitor Circuits errors of the overall circuit are due to only those early switches.. are slightly advanced with respect to the remaining clock signals for the following reasons. is always connected to ground while <1>1. and <1>..26. Unfortunately.. Consider the firstorder switchedcapacitor filter shown in Fig.
= 0 and C 2 = CA = IOC 3 = 10 pF.0019)(2. 10. we estimate that half the channel charges of 0 3 and 0 4 are injected to the virtual ground node by the following reasoning. half of its channel charge is left between 0 3 and 0 4 and is passed into the virtual ground when IjJ'a goes high again. Solution From (10.8)(0. Such an approach will minimize distortion and gain error as well as keeping de offset low.5 Charge lnjection 425 Thus. Finally. As a result. a.6 Assuming an ideal opamp. assuming its substrate is set to a fixed voltage). the charge being transferred through this capacitor must equal the charge injected by both 0 3.pC 3 (10. realize all switches connected to ground or virtual ground as nchannel switches only. In summary. were turned off early. = 1. The charge transfer into C 3 is given by (10. Thus.8 V. 0CH' has a linear and nonlinear relationship to Vi and thus would cause a gain error and distortion if a. it is best not to add any unnecessary charge into the circuit so these switches are also not advanced. to reduce the effects of charge injection in switchedcapacitor circuits. 0 4 (assuming the input is at zero volts and therefore does not contribute charge). .5 x 10. we can write the following charge equation. Co. Assume that switches 0 3 . length of L = 0. all of the de feedback current is charge transferred through the switched capacitor C 3 . a.84) Note that the de feedback around the opamp will keep the virtual input of the opamp at zero volts.85) Now. As a result. but when IjJ'a goes low. estimate the amount of de offset in the output of thecircuit shown in Fig.0.8 urn. its source voltage settles to Vi and thus the transistor's threshold voltage changes in a nonlinear relationship (due to the bulk effect. we can calculate the amount of channel charge of 0 3 .9 X 10. and tum off the switches near the virtual ground node of the opamps first.pF/J.82). EXAMPLE 10.5 V are used. Also. and that power supplies of ±2.26 due to channelcharge injection (ignore overlap capacitance charge injection) when C. When IjJ'a turns off. the second charge escapes to ground. one portion of the channel charge is linearly related to Vi' However. 0 4 (when on) to be OCH3 = 0CH4 = (30)(0. half the channel charge of 0 4 goes into the virtual ground while half of its charge is placed at the node between 0 3 and 0 4 . When IjJ'a goes high.5 . 0 4 are nchannel devices with a threshold voltage of V'n = 0.10. 3 width of W = 30 urn . while and would also inject constant charge from one cycle to the next.8) = 77.lm' .
83). It should be mentioned here that if the de input offset voltage of the opamp was included in the analysis. the charge change due to the channel charge only caused by turning an n channel switch off is approximated by It>VI = For a specified 0CH 2C = WLC o.5 X 10. then we have (10. and C is the capacitor. it would be multiplied by the dc gain of the circuit similar to that which occurs in an activeRC circuit. This upper bound takes into account switch channel charge only and ignores charge injection due to overlap capacitance. C. we see that this output dc offset value is affected by the size of capacitors used (in particular. Chargeinjection is especially troublesome at higher frequencies. which can be used to find Oc. the time constant of the switchon resistance and the capacitor being charged or discharged must be smaller.pC = 78 mY IpF (10.89) may be rewritten I elk < I lOR on C (10. this necessitates larger switches for a given size capacitor and therefore greater chargeinjection. the sampling clock halfperiod must be greater than five time constants. Recalling (1. Ron is the on resistance of the nchannel switch. using (10. If one assumes that. ' and hence the output voltage from (10.89) where lelk = liT is the clock frequency.90) Also.87) Thus. we have (10. At higher frequencies. Equation (10.91) It>Virna" (10. Most SC circuits will have two series switches for each capacitor.88) where T is the sampling period. V eff 2C (10.108) from Chapter I.92) implies that . It is possible to derive a very simple formula that gives an approximate upper bound on the frequency of operation of an SC circuit for a specified maximum voltage change due to charge injection. for good settling.426 Chapter 10 • SwitchedCapacitor Circuits I Z(OCH' + 0CH4) = Oc.) as well as the switch sizes and powersupply voltage.85) 3 v oul = 77.
6 SWITCHEDCAPACITOR GAIN CIRCUITS Perhaps the most common nonfiltering analog function is a gain circuit where the output signal is a scaled version of the input.27(a). and 0. so it is somewhat optimistic and should be therefore considered an upper bound on the maximum clocking frequency. respectively. which must be less than 15. where the two resistors have been replaced by their switchedcapacitor equivalents. s give"'.8 um . 1O. 1O.94) ignores overlap capacitance. we shall see that it is possible to realize accurate gain circuits by making use of switchedcapacitor techniques. assuming the switch sizes are chosen optimally. 10.6 SwitchedCapacitor Gain Circuits 427 (10.3 um ? Solution Using (10. Notice the substantial increase in speed for SC circuits as the technology improves. Parallel ResistorCapacitor Circuit In activeRC circuits. f elk . (10. V elf 21~Vlma. a gain circuit can be realized as parallel combinations of resistors and capacitors in both the feedback and feedin paths. 40 MHz.10.94) and u.27(b) [Foxall. (10.7 Assuming the maximum voltage change due to clock feedthrough is I mV. 1980]. what are the maximum clocking frequencies considering only channel charge injection for technologies having minimum channel lengths of 0. and III MHz. as shown in Fig.91) and (10.5 um . = 0.90) gives f elk = !tnl~Vlma. straightforward analysis results in the transfer function for this switchedcapacitor gain circuit being given by . Substituting (10. EXAMPLE 10.2.92) C= WLC o . In this section.6 MHz. One of the first switchedcapacitor gain circuits uses a similar approach. Finally.93) into (10. 0. much higher switching frequencies are attainable. Using the signalflawgraph technique of Section 10. Thus..05 M'IV . the upper frequency limit to charge injection for SC circuits is inversely proportional to L' and is approximately independent of the size of capacitors or the powersupply voltages. as shown in Fig.93) 5L' a very simple expression. for the three different technologies. as technology improves.
In addition. the change in charge across C" /lQc" equals the change in charge across C" /lQc" and therefore. it does have the advantage that its output is a continuous waveform that does not incur any large slewrate requirement (as occurs in the resettable gain circuit discussed next). as shown in Fig.. and the charging current flows across C. (a) KC. Here.428 Chapter 10 • SwitchedCapacitar Circuits R. ' the output voltage is related to the input voltage by Vout/V. 1981].. 10. Resettoble Gain Circuit The next configuration continuously resets an integrating capacitor on each clock cycle. C" is cleared on each t\>" while on t\>.n = C.n(z) = K (10.28 [Gregorian.27 (a) An activeRC gain circuit.n(n) . (bl An equivalent switched Hrz) = v out(z) V. V. In this way.. at the end of t\>.94) Unfortunately./C. the voltage across the integrating capacitor. R.1141 + (b) Fig./K C.theinput voltage charges C. this circuit stores any opamp inputoffset voltage across the input and feedback capacitors. capacitor gain circuit. at the same time..). When the output is sampled by the succeeding circuit (during t\>. However. 10. this design will also amplify the IIf noise and offset voltage of the shown opamp by K. the effects of the inputoffset voltage of the opamp are cancelled from the output . .
A second reason (and often more important) is that when the offset voltage is eliminated.). are equal to the opamp offset voltage. During <1>2' both the voltages across C I and C. 1O. voltage.6 SwitchedCapacitar Gain Circuits 429 + Fig. Next. V'ff + V'ff  Vc a + [C'++ ± ':' Voff ~ + (a) (b) Fig. a highpass response from the opamp's input terminals to the output voltage.which is placed in series with one of the opamp inputs.l0. As we saw in Chapter 4. consider the gain circuit during <1>2 (i. and Ibj during valid output (<1>. when a circuit cancels de offset voltages.10. lIf noise is also reduced. 1O.29(a). and at the end of <1>1 the voltage across C I is given by V'ff + I C. The effect of the input offset voltage is being modelled as a voltage source. it will also be amplified when the input signal is amplified and therefore can be troublesome. the response from the overall circuits does not necessarily have a highpass response. in effect.. 10. V off . The elimination of the opamp's inputoffset voltage is important for two reasons. It should be noted here that although there is a highpass response from the opamp's input terminals to the output voltage. which results in the analysis being marginally simpler. during <1>1 the circuit is configured as shown in Fig.29(b). In this case. lIf noise is large at low frequencies and can be a dominant noise source in many MOS circuits. One reason is that if the offset voltage is not cancelled. it is placed in series with the positive input. However. Vott.e.29 The resettoble gain circuit (a) during reset (<1>2). To see this offset cancellation. . Thus. the circuit has. the lIf noise is also highpass filtered and hence reduced.28 A resettcble gain circuit where opamp offset voltage is cancelled. when it is being reset) as shown in Fig.
note that a programmable gain circuit is easily realized by replacing C I with a programmable capacitor array? (PCA) where the capacitor size is determined by digital signals. 10.Voff' Therefore we can write.(n) = (10.)v.Voff.430 Chapter 10 • SwitchedCapacitar Circuits vc. Note. C.30 An example output waveform for the resettable gain circuit. It normally consists of a number of binarilyweighted capacitors having one platecommon for all capacitors and the other plateof each capacitorconnected through digitallycontrolled switches to eithera second common node or ground. such a waveform requires a very high slewrate opamp for proper operation.n and a voltage near 0 Veach time the clock changes. since one side of C. the output voltage is independent of the opanip offset voltage. The difficulty in realizing this waveform is that the opamp output must slew between (C. which is at Voff' the output voltage is given by vout(n) = Voff + Vc.96) Since the voltage across C. (10.98) Thus. . onehalf period earlier was V off and !lac.95) and Vc. is given by Vc. vout A=~~=~~=~'. (10. that the output voltage is only valid during <1>1' and it is equal to Voff during <1>" as shown in Fig. however.(n) .IC.112) !lao . 7.30.n(n) ."""'of==J_ Time Fig.97) Finally.(n) = vou. A programmable capacitorarray is a capacitorwhose size can be digitally controlled.(n) = Vc (n . I0. while that for C. Finally.==. Clearly.(n) (10. = !lOCI' we have Vc. is connected to the virtual ground of the opamp.(n) = v.
Capacitor C.32(a). We have assumed capacitor C. This deglitching technique works well and should be used on almost all switchedcapacitor circuits that would otherwise have no feedback connection at some instant of time. consider the inverting circuit during the reset phase of <1>" as shown in Fig. The basic idea of the gain circuit is to couple the opamp's output to the inverting input during the reset phase with a capacitor that has been previously charged to the output voltage.10. 10. Depending an the inputstage clack Signals.32(b). was charged to the output voltage during the previous <1>1 clock phase. Finally. This capacitor would normally be small (around 0. we shall see that one property of this gain circuit is that the opamp's output need only change by the opamp' s offset voltage between clock phases. 10. The next clock phase of <I> 1 is shown in Fig. 1O. In addition.5 pF or less). Voff . it can also be shown (see [Martin. is an optional "deglitching" capacitor [Matsumoto. Thus. 1O.6 SwltchedCcpocitor Gain Circuits 431 CapacitiveReset Gain Circuit To eliminate the need for the opamp output to slew to approximately 0 Veach clock period yet still cancel the opamp's offset voltage. the gain can be either inverting {as shown] or non inverting (inputstage clocks shown in parentheses). Here we see that capacitors C 1 and C. .28. Such a result often allows the use of singlestage opamps that are very fast opamps. in the same manner as in the resettable gain circuit of Fig. 1987] used to provide continuoustime feedback during the nonoverlap clock times when all the switches are open. 10. While the inverting circuit creates its output as a delayfree version of the input. the errors due to finite gain. The capacitivereset gain circuit is shown in Fig. ~ To see how this capacitivereset gain circuit operates. it also reduces the effect of the opamp's IIf noise. a capacitivereset gain circuit can be used. This gain circuit can be either inverting or noninverting depending on the clock phases of the input stage. where we see that the output voltage is Fig. since the circuit is insensitive to the opamp's input offset voltage.31 A gain circuit using capacitive reset (C 4 is an optional deglitching capacitor). of the opamp are proportional to 1/ A' (rather than the usual 1/A).31. are charged to the opamp's inputoffset voltage. A. 1987]) that for lowfrequency inputs (or for inputs that are constant for at least two clock periods). the output for the noninverting case would be onehalf clock cycle behind the input signal.
(i.32(a). their charges cancel each other and no charge is dumped onto C 3 . Therefore. In addition.32 Capacitivereset gain circuit. Since the charges on C I and C. [o] During reset ($2) when the output remains near previous output level. Before proceeding. when going from phase <PI to <P. we see that during <PI ' capacitor C 3 is charged to the output voltage..432 Chapter 10 • SwitchedCapacitor Circuits V Off + I C2 (a) (b) Fig. independent of the offset voltage in the same manner as the resellable gain circuit. the voltage on C 3 remains equal to the previous output voltage as shown.33 A differentialtosingleended gain circuit using capacitive reset.32). . are equal (recall that the charge on C. It should be C3 Fig_ 10. lbl During valid output ($1) when no offset error is present.e.10. circuit (b) to (a) of Fig. was obtained during the charging of C I ). when one side of each of C I and C. it is of interest to note what happens to the charges on C I and C. in the circuit of Fig. 10. 10. are grounded.
it would only result in the output voltage moving slightly further away froni the previous output voltage during <1>2 but would not affect the output voltage during <1>1' Finally. A detailed description of CDS techniques is beyond the scope of this text.7 CORRELATED DOUBLESAMPUNG TECHNIQUES The preceding SC gain amplifier is an example of using correlated double sampling (CDS) to minimize errors due to finite offset voltages. to <1>1' errors due to them will be significantly reduced.10. IIf noise. 1991] uses an additional capacitor. and finite opamp gain. The basic methodology in all cases is similar: During a calibration phase. 10. Next.31. during the operation phase (when the output is being sampled). 1996]. 10.34. A wideband amplifier that uses CDS. C'1 In but with errors due to finite inputoffset voltage. The technique can also be used to realize accurate integrators. as shown in Fig. 10. Next. 1996] for more information.. a couple of examples will be briefly described and the interested reader can consult the tutorial [Ternes. 10. it has been used to realize highly accurate gain amplifiers.:::: V c. 10. sample and holds. and gain. At the same time. the finite opamp input voltage caused by these errors is sampled and stored across C 1 and C z . Ki. during <1>1' this input error voltage is subtracted from the signal (applied to the opamp input) at that time. this capacitivereset gain circuit can also realize a differentialtosingleended gain stage. is connected in series with the oparnps inverting input and greatly minimizes the effects of these errors (by a factor of the inverse of the opamp' s gain over what would otherwise occur at frequencies substantially less than the . C.35 [Nagaraj. 1987]. but with superior highfrequency operation.. during <1>" C. this error voltage is subtracted from the signal voltage by appropriate switching of the capacitors. To date. is shown in Fig. l/f noise. the finite input voltage of the opamp is sampled and stored across capacitors. 1986. During <1>" C. This circuit has a switchedcapacitor circuit connected to the positive input of the opamp that not only accepts differential inputs but also. the SC integrator shown in Fig. 19821. cancels the clock feedthrough of the switches [Martin. similar to the SC amplifier of Fig. to a firstorder approximation. This technique is generally applicable to SC circuits of many different types [Ternes. rather. are used to have V o ut . The measured commonmode input rejection ratio for this circuit was 50 dB where a 5 urn technology was used together with a clock rate of 5 MHz [Martin. Note that the shown circuit indicates that the switches connected around the virtual grounds are disconnected slightly sooner than other switches to reduce nonlinearities due to charge injection.7 Correlated DoubleSampling Techniques 433 noted here that even if the two charges did not precisely cancel. to sample the opamp input error voltages during <1>. Assuming that the input voltage and the opamp input error voltages did not change appreciably from <1>.33. and integrators. and C. For example.
voltagecontrolled oscillator. sampling frequency). 10.34 An SC amplifier with CDS to minimize errors due to input.8 OTHER SWITCHEDCAPACITOR CIRCUITS In this section. for example. 1If noise. where accurate integrators are required in the first stage [Hurst. peak detector. C.L~i~_+Vout Fig. When CDS sampling is used.35 An SC integrator with CDS to minimize errors due to inputoffset voltages. 1989. Vout Fig_ 10. can also be used for gain amplifiers.offset voltages. c. 1989] to reduce inputoffset voltages and especially IIf noise. Specifically. and finite gain. V in o~. This technique has proven to be very useful in applications such as oversampling AID converters. often only a couple of stages will have lowfrequency gain from the opamp input terminals to the filter outputs and will require CDS circuitry.434 Chapter 10 • SwitchedCapacitar Circuits ~. Rebeschini. This might mean the use of nchannel input transistors rather than pchannel input transistors. Other integrators can be more simply realized. we look at an amplitude modulator. Similar architectures. fullwave rectifier. and sinusoidal oscillator. with an openloop capacitor in series with the opamp input during the phase when the output is sampled.. and finite gain. 1If noise. . we present a variety of other switchedcapacitor circuits useful for nonlinear applications.L c. . 10. When this technique is used in highorder SC filters. the opamps should be designed to minimize thermal noise rather than IIf noise.
The penalty paid here is that rather than Y(co) having power located only around ±coca' there will also be significant power around odd multiples of ±coca since a squarewave signal has power at odd harmonics of the fundamental. this approach simply requires a squarewave signal at the carrier frequency determining whether m(t) or m(t) is passed to the output. FullWave Rectifier A fullwave recti tier produces as its output the absolute value of the input. <l>ca goes high and the output is equal to a scaled version of the input. as shown in Fig. in many cases it is difficult to realize a sinusoidal signal as well as a linear multiplier.8 Other SwttchedCcpccttor Circuits 435 Amplitude Modulator Amplitude modulators are used to shift a signal along the frequency axis. the modulator is realized by making use of the capacitivereset gain stage of Fig.100) Since the Fourier transform of cos( cocat) is 1l8(co . one can show that the spectrum of y(t) is equal to Yuo) = M(co+coca)+M(coCOca) I I 2 2 (10. In other words. but if the input is negative the output equals an inverted version of the input. the clock phases of <l>A' <l>B switch. When <l>ca goes low. coca' we multiply mit) by a sinusoidal signal of frequency. These extra images can typically be tolerated through the use of additional filtering stages. Thus. to shift an information signal. in which case the output signal is simply y(t) = mit) x Sq(t) = ±m(t) (10. It is possible to realize a fullwave rectifier by making use of an amplitude modulator where.101) Thus.36. As a result. 10.37. <l>A = <1>2 and <l>B = <1>\.102) where Sq(t) is a square wave operating at the carrier frequency whose amplitude has been normalized to 1.coca) + 1l8(co + COca)' and multiplication in the time domain is equivalent to convolution in the frequency domain. many modulators make use of a squarewave carrier sig nal. by a carrier frequency. Here. instead of a squarewave carrier signal being used. if the input is positive the output equals the input. and the circnit produces an inverting output of (C\/C 2)V in .10. as shown in Fig.31. <l>ca goes low and the output equals an . which results in a noninverting output of (C\/C 2)Vin . the output of a comparator controls the polarity of the output signal. If the input signal is below ground. 10. y(1) = mit) x cos(cocat) (10. A squarewave modulator can be realized using switchedcapacitor techniques. coca' or mathematically. 10. If the input signal is above ground. For example. Note that the polarity of the output signal is determined by changing the clock phases of the inputtransistor pair throngh the use of <l>A and <l>B' which are controlled by the squarewave carrier clock signal <l>ca' When <l>ca is high. mit). the output spectrum only has power around ±coca' However.
a latched comparator is used to determine when v in > v ou'._ _..... Modulator of Fig... 'ilB 'ilA = ('il. Two methods for realizing peak detectors are shown in Fig. 10.. 'ilea) + ('il.L C. 10. . 10. While peak detectors will normally have some decaying circuitry associated with them (or a circuit to reset the peak occasionally)..436 Chapter 10 • SwitchedCapacitar Circuits 'il. When such a condition occurs. .36 (a) A switchedeapacitar squarewave modulator where the input clack phases are controlled by the modulating square wave ~M .36. >~~__~ V out 'il. In Fig. .38(a).. 'ilea) 'ilB = ('il..38. 1986]. the comparator output must change synchronously with the sampling instances.. 1_ _. . here we shall just look at the peak detector circuit itself.. Dh1. _.37 A fullwove detector based an the squarewave modulator circuit of fig.... 'ilea) (a) ~ • 'ilea .J (b) Fig. 10. For proper operation.... V out 'ilea Fig.+I>. 'ilea) + ('il. (bl A possible circuit realization for ~A and 'ilB. 10.....36.. 1O... the comparator output goes high and the switch Q 1 turns on.. inverted scaled version of input.. 'ilA Vin ... Circuits to achieve this operation are given in [Gregorian.. Peak Detectors Peak detectors produce as their output the maximum value of an input signal over some time period..
is not conducting. Note that this circuit has a high input impedance as the input signal is applied to the noninverting terminal of an opamp. Ib) continuous time approach. 10.10. As we shall see in Chapter 16. this circuit can be reasonably fast since latched comparators can be made to operate quickly and there is no opamp settling involved (only the RC time constant of Q I and C H ) .39 [Martin.C will be charged up to a voltage of V 55. However. When v ln > V out ' the opamp output will start to go high. The comparator is latched here to maintain its speed as well as ensuring that the comparator output is either high or low. never becomes lower than the output voltage when Q. While the feedback loop is on.. resulting in a charge . thus turning on Q. However. This slewing time can be minimized by adding circuitry to ensure that the gate of Q. forcing v oul = v in . The circuit of Fig. VoltageControlled Oscillatar A voltagecontrolled oscillator (VCO) is an oscillator whose frequency can be adjusted through the use of a controlling voltage. The basic principle and typical waveforms of the relaxation oscillator are shown in Fig. since it places Q.38 Twopeak detectors: (a) latchedcomporator approach. 10. is now at a level quite a bit higher than zero. this opampbased circuit will typically be slower than the comparatorbased circuit of Fig.38(b) requires an opamp (with proper compensation). Comp Voul + Opamp Q2 You! Yin t (a) H t (b) H Fig. 1981] and operate as follows. the VCO described here generates an output square wave that places the oscillator alternatively in one of two states and is referred to as a relaxation oscillator.8 <I> Other SwitchedCapacitor Circuits 437 + v.38(a) since one needs to wait for the opamp output to slew and then settle. 10. and hence turning on the feedback loop. Assume that You! has just toggled low to V 55 and node v. a VCO is an integral part of a phaselocked loop (PLL). 1O. Note that this circuit requires that the input signal directly drives C H through QI' and hence buffering may be required. On <I> \' k. the high loop gain will force You! = v in with a high accuracy. in a feedback connection. As we shall see.
as 'I>.39 A switchedccpocitor relaxation oscillator. C Vx (a) Vx Time ou Time  I' .I Tos c (b) Fig.438 Chapter 10 • SWitchedCapacitor Circuits value given by (10. 10. . the charge on k2C will be transferred to C (while the voltage across unswitched k 1C again remains unchanged) and the output will fall by an amount equal to Ok C .103) = k.CV ss Note that the voltage across the unswitched capacitor k 1C remains unchanged at V ss. goes high. Next.
1O. = C = . Assuming k. Mathematically. (10. After this time. Here. we will be back at our starting point.' . we have a 50 percent duty cycle with (10. while capacitor k. C does not affect the operation of the circuit. such that many small steps occur over onehalf Tose period.8 ~aC ak. then extra charge packets are added into the integrator with the opposite sign as those for k.105) and node Vx drops by and since this charge is drawn across C.C. and the circuit reaches V x = 0 sooner. the comparator output will toggle to V OD' and at this point a large amount of charge will pass through k. we make the assumption that k. plus the number of steps during positive sloping v x. Just after this positive step.V s s C (10. »k" kin and V DD = V ss . as shown in Fig.10. This large charge value is equal to so.C.C Other SwitchedCapacitor Circuits 439 sv. To derive a formula for the oscillation period Tose. kinC.109) This fixedfrequency oscillator can be made voltage controlled by adding an extra feedin capacitor to the oscillator. and the entire operation will repeat indefinitely. Once v x goes below zero. C and C have formed a noninverting discretetime integrator. at which point a large positive voltage step will occur. we have Tos c T Assuming V DD = Vss .C(VDD(V S S ) ) ~ac = ~ak. we can now write that the total number of clock cycles. and the circuit reaches V x = 0 later. = (10.» k. extra charge packets are added into the integrator with the same sign as those for k.C (10. Tose/T.12) to show that the frequency of oscillation for the . . With this assumption. it is left as an exercise to the reader (Problem 10.106) as shown in Fig.C = k. 10040. equals the number of steps during negative sloping v.V DD (since You' now equals VDD) until Vx = 0.108) or equivalently. k. then an amount equal to sv.39(b). In effect. If Vin is negative.107) (10.104) This operation will continue until v x reaches zero volts.C while the voltage across it changes from V ss to V DD.= k. Vx will step up in increments of k. when V in is positive.
440 Chapter 10 • SwitchedCapacitor Circuits <\>2 _~. when a button is pressed on a touchtone telephone. the signal sent down the telephone line is simply the sum of two sinusoidal signals at certain frequencies (the signal is known as a dualtone multifrequency (DTMF) signal). A switchedcapacitor implementation of this sinusoidal oscillator is shown in Fig.40 is given by (10. 10. + Comp Fig. Assuming some startup circuit is used to force oscillations to exist.40 A voltcqecontrolled oscillator (VCO! based on the relaxation oscillator of Fig.l0. Vst is low and the extra capacitors C. we see that a sinusoidal wave at v out results in a square wave at V1 which has a large component at 10 .41. 10. For example. switchedcapacitor sinusoidal oscillators could be used to generate the necessary touchtone signals. The startup circuit is used to sense when an ac signal is present at v out . One method of generating a sinusoidal oscillator is shown in Fig.39. ami C 6 form a positive feedback . where the highQ bandpass filter has been realized using the circuit of Fig.25. 10. When no ac signal is detected. r~ <\>1 o+r+v. voltagecontrolled oscillator of Fig. 1985]. V out ' The oscillation frequency is set by the center frequency of the bandpass filter. The comparator generates signals X and X with the result that the switchedinput associated with Vref is either positive or negative.110) Sinusoidal Oscillator In many applications. 10. while the sinusoidal amplitude is set by the center frequency gain of the filter and the peak values of the squarewave signal. The signal V I is filtered by the bandpass filter and thus maintains the sinusoidal signal.42 [Fleischer. it is useful to realize an oscillator which produces a nearly sinusoidal output. a highQ bandpass filter with center freqnency 10 is used together with a hard limiter. Thus. 10. Here.
Brackett and A. 10. . 168176. Bruton.1 ~~ 0 sinusoidol oscillotor. For examples of other nonfiltering uses of switchedcapacitor circuits. "MOS SwitchedCapacitor Ladder Filters. v st goes high and the positive feedback loop is broken. S. 10. CAS22. ~. A sinusoidal oscillator that makes use of a bandpass filter. no..41 v.. pp. Vol. SC13. . no. 1978. Circuits and Systems. Once an ac signal is detected. R. Vol. 3. 806814.42 A switchedcopccitor implementotion of loop which causes oscillations to build up. O. December 1978. VrelF Y. R. Matrix Publishers..11+. as discussed previously. Champaign. Allstot. + V out ~ Period T = 111 0 Fig. March 1975. x X Fig. vout '" C. L. Sedra. . the interested reader is referred to [Gregorian." IEEE Trans.. 575. pp. Illinois. Filter Theory and Design: Active and Passive.10.9 References HighQ bandpass filter with fcenter freq10 ~ 441 Period T Y. Brodersen.. 1986]. p.9 REFERENCES D. Gray. T. thereby allowing oscillations to continue. 6. P. • +V ref V out c~ StLart_upY" circuit C." IEEE 1. 10. and P... "LowSensitivity Digital Ladder Filters. of SolidState Circuits.
"A SwitchedCapacitor Oscillator with Precision Amplitude Control and Guaranteed Startup. 2. MarchiApri11981. K. of IEEE Int. J. of Solid State Circuits. CAS25. Fried. B. K. l . 1980. Circuits and Systems. no. Martin and A. Vol. 6. D. March 1978. Moms. C. Martin. J. SC20. pp." filed March 1978. Ganesan. Vol. Jacobs. S. J. C. R." IEEE 1. Martin and S. F. L. Caves. M. Vol." Proc. 237244. Laker and W. "SC Building Blocks with Reduced Sensitivity to Finite Amplifier Gain. patent no. R. 412414. and J. Design ofAnalog Integrated Circuits and Systems. pp." IEEE J. Symp. Gregorian and G. Fleischer. no. "A SwitchedCapacitor Bandsplit Filter Using Double Polysilicon OxideIsolated CMOS:' 1980 lSSCC Dig. Vol. 1991. Larson and G." IEEE Trans. of Technical Papers. 334338. 1088161. Vol. pp. June 1980. no. and G. Rahim. "SwitchedCapacitor Circuit Design. CAS27. Tokyo. Issued in Canada October 21.442 Chapter 10 • SwitchedCapacitor Circuits J. Broderson. "Analog SampleData Filters. February 1980." Microelectronics 1. McGraw Hill. 1982.. S. 254257. 641647." Electron Lett. August 1972. 1979 into Symp." Proc. Laker. Gregorian. C. "DeltaSigma AID with Reduced Sensitivity to OpAmp Noise and Gain. February 1987. January 1982. "Offset. VoL SC12. R. Gray. August 1981. Hurst and R. . Copeland. R.ation Oscillator. Ternes. H. April 1985. W. Gray. Hosticka. SC7. 94t966. in Canada.1994. W." IEEE Trans. W. Sansen. G. on Circuits and Systems (IEEE & IECE). . SC22. 469478. C. R. Foxall. Brodersen. D. December 1978. K. Martin. Rosenbaum. 4. 10141021. Rep. Issued in England June 10. Symp. of SolidStale Circuits. "Improvements in Sampled Analog Filter. M. New York. "StraysInsensitive SwitchedCapacitor Filters Based on Bilinear zTransfonn. 12. 13. pp. Rosenbaum. on Circuits and Systems. Martin and A. 365366. 1986. pp. Analog MOS Integrated Circuits for Signal Processing. July 1979. Martin. December 1977." Electron. Aitken. R. "Exact Design of SwitchedCapacitor Bandpass Filters Using Coup1edBiquad Structures. VoL 71. on Circuits and Systems. "A Differential SwitchedCapacitor Amplifier. 8. "HighResolution SwitchedCapacitor D/A Converter. no. "MOS SwitchedCapacitor Ladder Filters. the United States and Japan." IEEE 1. R.. pp. CAS27. no. "SampledData Filters Using Switched Capacitors as Resistor Equivalents. Vol. and P. CYB 2019151B.. Allstot.and ClockFeedthroughCornpensated SC Fillers. "MOS Sampled Data Recursive Filters Using SwitchedCapacitor Integrators. and K. 104106. K. 15. Sedra. Bandwidth. A. pp. and S. ofIEEE Int. Martin. L pp. Sedra. pp. on Circuits and Systems." Proc." IEEE 1. pp. 9091. Ternes. no. K. of SolidState Circuits." IEEE Proceedings. T. of SolidStare Circuits. "Improved Circuits for the Realization of Switched Capacitor Filters. Vol. Ki and G. December 1977. TRtE 817806. and P. K. M. Levinson. P. pp.." Proc. 302304. P. Lee. Augus11983. Gregorian. 592600. K. 15611564. "A VoltageControlled SwitchedCapacitor Relax. D. C. Y. E. C. no. 756760. A. of IEEE Int. June 1979. Circuits and Systems. Ozcolak." IEEE Trans. no. 6. New York. K. of SolidState Circuits. K. SC12. Also published as BNR Tech. VoL 18. T. C. 1989. R. April 1980. Ternes. 1013. L. no. Vol. Vol. R. A. 3940. Lett. John Wiley & Sons.. pp. E. "Improved Circuits for the Realization of SwitchedCapacitor Filters. L. A. Martin. and Offset Voltage. and G. pp. Sellars. Martin. no. pp. Temes. 1987. L." IEEE J. pp."IEEE J. 600608. 4. Circuits and SYStems. Whitbread. Symp. SC16. pp.. S. K. Ternes. pp. Vol. (~f SolidState Circuits. "New ClockFeedthrough Cancellation Technique for Analogue MOS SwitchedCapacitor Circuits. pp. R.
Young. 1990. Ignoring the effect of parasitic capacitances. "SC Circuits with Reduced Sensitivity to Amplifier Gain.2 10.4 Repeat Problem 10. "A Monolithic DualTone Multifrequency Receiver. 618621. H. 220237. on Circuits and Systems. "Autozeroing. Gray. New Jersey. Symp. no. "Frequencz Filterung durch Netzwerke mit Periodis Gesteurten Schaltern. Englewood Cliffs.(z) Fig. and K. 23. K. 6. Vol. PIO. 1966. SC14.(n) V. of SolidState Circuits. J. pp. December 1978. M. F. of IEEE Int. M. pp. Circuits and Systems.10." Proc. Rebeschini et al. R." IEEE Trans.1 Assuming logic signals have infinitely fast fall and rise times but are delayed by I ns through a logic gate. 10. Symp. Vol. on SolidState Circuits. Watanabe." IEEE Proceedings. G. and D. S. Landsburg. and Chopper Stabilization." IEEE Int. Svmp. 156157. M.10 Problems 443 K. "SwitchedCapacitor Building Blocks fOT Adaptive Systems. Schaumann.z is applied to the input. Sedra. 8. pp. 428~29." Analys und Synthese von Netrwerken. P10. and G. R. of JEEE Int. Prentice Hall. pp. on Circuits and Systems. 1996. Nagaraj et al. February 1977. "Analog NMOS SampledData Recursive Filters. Ghausi. Jacobs. Hodges. A. ]989. 1O." Proc. draw the output waveforms of the two phase clock generators shown in Fig. find the discretetime transfer function of the switchedcapacitor circuit shown in Fig. no. W." IEEE J. 6. S. I. "A HighResolution CMOS SigmaDelta AID Converter with 320 kHz Output Rate. April 1987. Vol. CAS28. B. 991997. Correlated Double Sampling. Assume the delay blocks add delays of 10 ns each and a clock frequency of 10 MB. pp.5 is given by . Matsumoto and K. Tanungsheft. Design of Analog Filters. Enz. 576584.10 PROBLEMS 10." Electron. Poschenrieder. Laker. P. to be published.3 10.2 v. "SpikeFree SwitchedCapacitor Circuits. A.2. 246249.. Martin and A. R. the transfer function for the discretetime integrator of Fig. G. Stuttgart. Ternes and C.3(b).2 but include the effect of parasitic capacitances. pp. 10. no. June 1981. pp. 1986. C. Show that when an opamp has a finite gain of A. Lett. White. 10.
10040. 10.15(a) to realize a discretetime transfer function having a de gain of one. design a bandpass filter with a Q = 20 (in the continuoustime domain) and a peak gain of one near lsi 100. = 2 pF. What is the magnitude and phase of the gain at de. PIO.12 Verify that Eq.6 Repeat Example 10. C. (10. What is the gain (in dB) at 25 kHz? 10.104) gives the frequency of oscil1ation for the veo of Fig. 10. C. 10. c. and compare it to that which would be obtained if the lowQ circuit were used instead.8 Find the discretetime transfer function of the switched capacitor circuit shown in Fig. Let C] = C. Assume that C A = 50 pF.11 Sketch a typical output waveform for the capacitivereset gain circuit of Fig.53327 .10 Using the bilinear transform. Fig.8. 1O.444 Chapter 10 • SwitchedCapacitor Circuits Also show that this transfer function has a de gain of A and a pole that is located slightly to the left of I by an amount approximately equal to (C]/C.3 but assume the discretetime zero is at z = 0 and the pole remains at z = 0. = I in both cases. 10. and a 3dB frequency of I kHz when a clock frequency of 50 kHz is used. 10.31 if the opamp has an input offset of 100 mV and a gain of 10 is desired. the circuit is a resonator). 10.5 10. Note that with this change.S Show that when K6 = 0 in the biquad circuit of Fig. Find the largest to smal1est capacitor ratio if this transfer function is realized using the highQ biquad circuit. and CA = 20 pF. 10.16 when C] = 0 pF. C 3 = 2 pF.e. lsi 4 and Is/2 ? 10. What is the new gain at 50 kllz? Find the capacitances needed for the firstorder filter shown in Fig.7 Find the transfer function of the circuit shown in Fig. C] is no longer required at the sacrifice of a nonzero gain being obtained at 50 kHz. a zero at 0. 10. they lie precisely on the unit circle (i.21.. PIO. if the poles are complex.9 .) (l/A).
5 to 10 times the Nyquist rate (i. it is useful to make the distinction between two main types of data converters. analog filtering is used.1. For example. In most cases. Nyquist rate converters operate at 1. Bin is defined to be an Nbit digital signal (or word) such that Bin = b . l' I + b . However.1 IDEAL D/ A CONVERTER Consider the block diagram of an Nbit DIA converter shown in Fig.2 2 + . 11. it should be noted that. In AID converters. Before proceeding.. fundamental aspects of analogtodigital (AID) and digitaltoanalog (D/A) converters are presented without regard for their internal architecture or circuit design. Oversampling Converters Oversampling converters are those converters that operate much faster than the input signal's Nyquist rate (typically 20 to 512 times faster) and increase the output's signaltonoise ratio (SNR) by filtering out quantization noise that is not in the signal's bandwidth. Most often.CHAPTER Data Converter Fundamentals In this chapter. This distinction is made here since much of the descriptions that follow refer more closely to Nyquistrate converters than to oversampling converters.. NyquistRate Converters We loosely define Nyquistrate data converters as those converters that generate a series of output values in which each value has a oneroone correspondence with a single input value. this filtering is performed digitally. whereas in DIA converters.1) 445 .Nyquistrate converters are seldom used at the Nyquist rate due to the difficulty in realizing practical antialiasing and reconstruction filters. Here. 3 to 20 times the input signal's bandwidth). oversampling converters use noise shaping to place much of the quantization noise outside the input signal's bandwidth (see Chapter 14). + b N2 N (11. converters are treated in this chapter as black boxes such that only their inputoutput relationships are discussed. 11. Internal architectures and circuits techniques for realizing data converters are discussed in following chapters.e. where each level is a result of a single Bbit input word. In effect.. a Nyquistrate DlA converter would generate a series of analog output levels.
+b N2 N ) = VretB.446 Chapter 11 • Data Converter Fundamentals D/A 11~Vout Fig. 11.e. a multiplying D/A converter is realized by simply allowing the reference signal.. I LSB = 2 . as the most significant bit (MSB) and b N as the least significant bit (LSB).3) the definition of a new "unit. Vret. mathematically..to be a varying input signal along with the digital input.For simplicity.2).el are voltagesignals. The analog output signal.. although only a finite number of analog values occur at the output. resulting in a unipolar D/A converter. N (11. b j is a binary digit).. In contrast. sign magnitude.n (11. or. Signed codes are discussed in Section 11.2.4.2) It is useful to define VLSB to be the voltage change when one LSB changes. Bin' Such an arrangement results in Vout being proportional to the multiplication of the input signals..r ) ." Also useful (particularly in measuring errors) namely. we assume that both Vout and V. Note here that. where b. The relationship between these three signals for a unipolar D/A converter is given by Vout = Vrel(bt2t +b.!. such as currentorcharge. find VLSB . VLS B ss v. Extending the following concepts to the signed case is straightforward but requires knowledge of the type of digital representation used (i. A unipolar DIA converter produces an output signal of only one polarity.VLSB' Finally. Vret . Furthermore. EXAMPLE 11. or 2's complement).1 Vref ' A block diagram representing a D(A converter. offset binary. 11. LSB units. although. the output signals are welldefined values. which are in fact unitless.e. in general. Vrel . equals 1 orO (i.. as we can see from (11.el( I . we have assumed here that Bin represents a positive value.1 An 8bit DI A converter has Vret = 5 V. Bin and Vrel. Bin. they may be other physical quantities. What is the output voltage when Bin = 10110100° Also. We also define b.4) The transfer curve for an ideal 2bit D/A converter is shown in Fig. Also note that the N maximum value of Vout is not Vrel but rather V.r' + . signed converters produce output signals of either positive or negative polarity. Vout' is related to the digital signal. or equivalently. . through an analog reference signal. N 2 IS (11. for an ideal D/A converter. depending on a sign bit (usually btl.
. v. < V LSB 2 I (11. Solution We can find the decimal equivalent of Bin using (11.7) Then. ' . 11. + bNT = Vin ± Vx where I V LSB 2 ::.6 = 0.2 Ideal AID Converter 447 v. 11.703125 (11. we define VLSB to be the signal change corresponding to a single LSB change as in the 0/A case.3 A block diagram representing an AID converter. we find Vou' = VrelBin = 3.6) (11.2 Inputoutput transfer curve for an ideal 20bit OfA converter. v. using (11.1) Bin = T' + 2. v.11. 11.: 11 (100) t V lSB = ! = 1 LSB 4 Fig.3.. where Bour is the digital output word while Vin and Vret are the analog input and reference signals.3 + 24 + 2. For an AID converter..8) ND Fig. Also.5) (11. 1 N) Vref(b 1T + b. 3/4 1/2 1/4 000 01 10 . respectively.T' + .... the following equation relates these signals.: V ref .2).2 IDEAL AID CONVERTER The block diagram representation for an AID converter is shown in Fig.516 V and VLSB = 5/256 = 19S1nV 11.
5.4 for a 2bit converter. it should be noted that the relation shown in (11. In this section.8) holds only if the input signal remains within I LSB of the two last transition voltages. 0 2 Note that there is now a range of valid input values that produce the same digital output word.4 Inputoutput transfer curve for bit AID converter. quantization errors will occur if a obit DJA convener is used to convert a IObit digital signal. a transfer curve for an AID converter can be sketched as shown in Fig. VOl is shown in Fig. For example. 11 10 01 = 1/4 = 1 LSB Yin 00 . 11. Since we have (11.4. Also. so that the midpoints of the staircase curve fall precisely on the equivalent D/ A transfer curve. where both Nbit converters are ideal. Of course. the quantizer is said to be overloaded since the magnitude of the quantization error would be larger than VLSB/2 . the quantization error occurs in the conversion from a ]Obit digital signal to a obit digital signal. but in this case. Vin should remain less than 718 V rei and greater than 118 V re l .2. This signal ambiguity produces what is known as quantization error. for the 2bit transfer curve shown in Fig. 11. we model these errors as being equivalent to an additive noise source and then find the power of this noise source. quantization errors occur even in ideal AID converters. 11.448 Chapter 11 • Data Converter Fundamentals V LS B v.3 QUANTIZATION NOISE As mentioned in Section 11.9) 1. 11. . 1 As in the DIA case. Here. we define the transition voltages at Vij . Specifically.4 as the voltage (normalized with respect to V rei) for the transition from 00 to 0 I. Otherwise. Consider the setup shown in Fig. Finally. Note that the transitions along the V in axis are offset by 112 VLBB. note that no quantization error occurs in the case of a DIA converter since the output signals are well defined. 11."~++f1++t~ o t 1/4 Vee! V01/Vrel Fig. I 1. where the subscript ij indicates the upper Bout value of the transition..".
Taking thedifference between these two signals gives us the noise signal.10) shows that the quantized signal. 11. Ven' plus some additive quantization noise signal. Clearlyt the average of Va is zero.U v. 11.5 A circuit to investigate quantization noise behavior.10) Although this rearrangement is trivial. Note that (11. . VI' appearing as a staircase. 1 V LSB 2 +i+t+t++++TtWrHrt\+'t (Time) +''+t (Time) ++ T Fig.5.10) is exact because no approximations have been made here. 11. V I' can be modelled as the input signal. 11. Note that the quantization signal. Deterministic Approach To gain an understanding of some of the properties of the quantization noise signal. let us assume the input signal. is given by I fT/2 Va<rms) = [ Vadl T TI2 2 JII2 = I [T fTI2 T/2 V2 LSB (_I)' dlJ1I2 T  = [V~~B(~ITI2 ]n T 3_ T / l12 (lUI) . Va' is limited to tV LSB/2 and will be so limited for all input signals (not just ramps).11. However. The quantization noise modelling becomes approximate once some assumptions are made about the statistical properties of Va. we can rearrange this equation as VI = V e + Va n (11. Va. 11.6 Applying a ramp signal to the circuit in Fig. as shown in Fig. Va(rms).5 is a ramp. we will investigate its behavior when the input is a particular function. Va' which is a result of quantization error. in Fig. the rms value of the noise signal. Va.3 Quantization Noise 449 Quantization noise Fig. assuming no overloading occurs. Specifically. Such an input signal n results in the output from the D/A. .6. Ve . it has important implications because (11.
VQ( aV9 )' is found to be zero as follows: V Q( aV9 ) = I ~ I _ xfQ(x) dx = . the rms value of the quantization error is given by VQ(rms) = [I~ X2fe(X)dX](12 ~ = [_I_(f~. we assume that the input signal is varying rapidly such that the quantization error signal. However. we see that the rms power of the quantization noise source is proportional to the size of VLSB' which is determined by the number of bits. will be a constant value. in the converter..sa VLSB 2 2 Fig.SS~22X2dX)~(12 VLSB 'S8 ~ = V LSB J12 (11.7.l3) In a similar fashion. a J=======+L. The average value of the quantization error.t12 Thus. V Q. Recalling that the size of VLSB is halved for each additional bit and assuming that V ref remains constant. Assumed probability density function for the quantiza VQ . fQ(x). V LSB ! Height = _1_ so that r: fo(x) dx x V. given an input signal waveform.l4) that the noise power decreases by 6 dB for each additional bit in the AID converter. In a stochastic approach.14) which is the same result as (11. 11. the rms quantization noise power equals VLSB/ J12 when the quantization noise signal is uniformly distributed over the interval ±V LSB/2 . as shown in Fig. In general..7 tion error. is a random variable uniformly distributed between ±V LSB/2. (11. which is found using the deterministic ramp input signal. The probability density function for such an error signal.. Thus. a stochastic approach is typically used. 11.12). ss / 2 LSB /2 X dx ) = 0 (1l. N.00 V LSB (Iv V .450 Chapter 1 1 • Data Converter Fundamentals V Otrms i VLSB = ["1""::. The fact that these two results are identical should come as no surprise since randomly chosen samples from the sawtooth waveform in the deterministic case would also have a uniformly distributed probability density function. . Stochastic Approach The preceding deterministic approach was presented as a simple example to see some properties of the quantization noise signal. we see from (ll.12) . to deal with the more general input case.
16) gives the best possible SNR for an Nbit AID converter.15) For example.16) = 2010 g(A2 SNR = 6. . Note that (11. the idealized SNR decreases from this best possible value for reduced input signal levels. the SNR is given by (11. which results in SNR = 2010g(Vinirm'l) VQums) = 20 log Vrel/ (2 J2 ) ) (V / ( J12 ) LSB N ) _ (11.3 Quantization Noise 451 formula can be derived giving the best possible signaltonoise ratio (SNR) for a given number of bits in an ideal AID converter. we use (11. a sinusoidal signal has 1. Alternatively. the ac power of the sinusoidal wave is Vrel/(2'/i). Fig. For example. a random signal uniformly distributed between 0 and Vrel) and considering only the ac power of the signal.5 V were applied to the input. Solution First. However. However. 11.02N + 1. a lObit AID converter has a best possible SNR of about 60 dB. assuming Vin is a sawtooth of height Vrel (or equivalently. where the design of oversampling converters is presented.8 shows a plot of the idealized SNR for a lObit NO converter versus the sinusoidal input signal amplitude.2 A IOOm V pp sinusoidal signal is applied to an ideal 12bit AID converter for which Vrel = 5 V. a more common SNR formula is to assume Vin is a sinusoidal waveform between 0 and Vret : Thus.16) to find the maximum SNR if a fullscale sinusoidal waveform of ±2. it should be noted that these SNR values could be improved through the use of oversampling techniques if the input signal's bandwidth is lower than the Nyquist rate. For example.11. Find the SNR of the digitized output signal. EXAMPLE 11.76 dB In other words. Oversampling will be discussed in detail in Chapter 14.76 dB more ac power than a random signal uniformly distributed between the same peak levels.
452 Chapter 1 1 • Data Converter Fundamentals 60 SNR (dB) 50 40 30 20 10 Best possible SNR OI+:l. where the MSB is complemented. the signmagnitude representation for 5 is 0101.F1++++1~. as shown in Table 11. 11. Some common signed digital representations are sign magnitude. the analog signal is bounded by ±0. such that its fullscale range is the same magnitude as in the unipolar case.76 = 74 dB (11.18) 11. Sign Magnitude For negative numbers in the signmagnitude case.4 SIGNED CODES In many applications. note that this approach results in two representations for the number 0. Typically.02 X 12 + 1. and 2's complement.(dB) so 50 40 30 20 10 0 Fig.5V ref ..8 Idealized SNR versus sinusoidal input signal amplitude for a lObit AID converter. the SNR of the digitized output is SNR = 74 . except that the MSB is complemented.1 that all positive number representations are the same except for the offsetbinary case. Note from Table 11.1 for the 4bit case. and thus only 2 N .. . For example.6 dB (11.17) However. since the input is only a ±100mV sinusoidal waveform that is 28 dB below full scale. whereas for 5 it is IIOL However.28 = 4. it is necessary to create a converter that operates with both positive and negative analog signals. l's complement. offset binary. resulting in the need for both positive and negative digital representations. The OdB input signal amplitude corresponds to a pecktopeck voltage equaling Vrel. V. all the bits are the same as for the positive number representation.1 numbers are represented. SNR m ax = 6.
For example.2) is easily modified to the signed case. since 4 13 = 5 + 2 . or equivalently.I. and thus only 2 .bit case is Ihe same as the unipolar code for the number 13. and all sixteen numbers are uniquely represented. The offsetbinary code for 5 is the same as the unipolar code for 3. as in the unipolar case.11. Also. the decimal counts N N are from _2 I to 2 . which is 0011. this system can N be thought of as simply a unipolar representation counting from 0 to 2 .I. Offset Binary The offsetbinary representation is obtained by assigning 0000 to the most negative number and then counting up. In other words. the offsetbinary code for the number 5 in the 4. negative numbers are represented as the complemenI of all the bits for the equivalent positive number.1 Number Signed Codes 453 Some 4·bit signed digital representarions Normalized number Sign magnitude I's complement OfTset binary 2's complement +7 +6 +S +4 +3 +2 +1 +0 (0) I 2 3 4 S 6 7 8 +7/8 +6/8 +S/8 +4/8 +3/8 +2/8 +1/8 +0 HJ) 118 2/8 3/8 4/8 S/8 6/8 7/8 8/8 0111 OliO 0101 0100 0011 0010 0001 0000 ( 1000) 1001 1010 lOll 1100 1101 1110 IIII 0111 OliO 0101 0100 0011 0010 0001 0000 (1111) 1110 1101 1100 lOll 1010 1001 1000 1111 1110 1101 1100 lOll 1010 1001 1000 0111 OliO 0101 0100 0011 0010 0001 0000 0111 OlIO 0101 0100 0011 0010 0001 0000 IIII 1110 1101 1100 1011 1010 1001 1000 1'5 Complement In l 'scomplement representation. It should be noted that the 1'scomplement case N also has two representations for 0.. Finally.19) VO 1 = V..ef(b1r +b.el (11. 5 is once again 0101.5V.2' + .5V. with offsetbinary representation as l N) 0. but where the N decimal numbers represented are offset by 2 I. For example. the unipolar relationship for a D/A converter given in (11. here.ef' .4 Table 11. Note that the offsetbinary code does not suffer from redundancy. whereas 5 is now 1010. which is 1101.I numbers are represented. this code has the advantage that it is closely related to the unipolar case through a simple offset. +bNr U Note here that the output signal is now bounded by ±0.
21) Thus. 11. the final result of 6/8 is correct. 5 becomes 0101 in 2's complement (the same as in sign magnitude and in l's complement). the subtraction of two numbers. Before proceeding. subtraction requires only a small amount of extra hardware.454 Chapter 11 • Data Canverter Fundamentals 2'5 Complement Finally. the final result is correct although an intermediate result is incorrect. we simply carry on and add 3/8 to find the final answer. 2' scomplement codes are the most popular representation for signed numbers when arithmetic operations are to be performed.5 PERFORMANCE UMITATIONS In this section.3 Show that. Thus. Finally. Adding a single LSB is easily accomplished in hardware by setting the carryin bit high in the overall adder.20) which corresponds to 7/8 (note that this temporary result is two steps past 7/8 when thinking of a 2'scomplement code as being circular). (11. The main advantage of 2'scomplement coding is that addition of both positive and negative numbers is performed using straightforward addition.B. definitions are required for determining the transfer responses of both D/A and AID converters.. For these reasons. the 2'scomplement representation is obtained from the offsetbinary number by simply complementing the MSB. Solution The addition of 2/8 and 7/8 is given by 0010 +0111 = 1001 (11. some commonly used terms describing the performance of data converters are defined. 1001 + 1101 = 0110 as we just saw. although a temporary overflow occurred. 7/8. The transfer response of a D/A . and no extra hardware is required. no overflow hardware is required as long as the final result is within the digital code range (even if intermediate results go well out of range). Also. EXAMPLE 11. forming the I'scomplement equivalent) and then adding this result to A at the same time as adding a single LSB in order to create the 2'scomplement equivalent of B. whereas 5 is now lOll. when adding 2/8. For the 4bit example. can be easily performed by complementing all the bits for B (i. if many numbers are being added using 2'scomplement codes.e. A . and' 3/8 together as 2'scomplement numbers. It should be mentioned that the 2'scomplement code for negative numbers can also be obtained by adding I LSB to the equivalent I' scomplement code. Although this intermediate result is incorrect since overflow occurred.
O! I = .. Accuracy The absolute accuracy of a converter is defined to be the difference between the expected and actual transfer responses. O! from 1/2 LSB..(Vl. Eoff(O/A) = YOU! V I L$B 0 . .23) The gain error is defined to be the difference at the fullscale value between the ideal and actual curves when the offset error has been reduced to zero. the gain error. V. Offset and Gain Error In a D/A converter... O!)   2) (11... 0 For an AID converter.L~ V LS B 2 (11. and we use that approach here.n(O/A)..(2 (2 N N I) (11. gain. for an AID converter.25) Graphical illustrations of gain and offset errors are shown in Fig. The absolute accuracy includes the offset. AID converter errors are often measured in terms of the analog transition point values. For a D/A converter. Resolution is not necessarily an indication of the accuracy of the converter. Similarly.5 Performance Limitations 455 converter is defined to be the analog levels that occur for each of the digital input words.. Similarly.j. ... Egain(A/D) given by E gain(A/D)  . E off ' is defined to be the output that occurs for the input code that should produce zero output. since transitions are easier to measure than midpoint values. Ega. in units of LSBs.9.11. or mathematically. an Nbit resolution N implies that the converter can resolve 2 distinct analog levels. the offset error is defined as the deviation of Vo.n(O/A) V = (V OU ! I yOU! V I J..22) where the offset error is in units of LSBs. is given by Ega.. 11. Thus. is LSB 1. Resolution The resolution of a converter is defined to be the number of distinct analog levels corresponding to the different digital words... 0 (11.24) (in units of LSB s). . and linearity errors. the offset error.VLS B VLS B v. .. or mathematically. but instead it usually refers to the number of digital input or output bits. EofftA/O) Vo. the transfer response of an AID converter can be defined as the midpoints of the quantization intervals for each of the digital output words. However.. the equivalent gain error.. 1 LSB 0 .
Differential Nonlinearity (DNL) Error In an ideal converter.. each output level is I LSB from adjacent levels. 11. Accuracy can be expressed as a percentage error of fullscale value. 10 01 11 (100) t Fig. we define INL values for each digital word (and thus these values can be plotted for a single converter). whereas others sometimes define the term "INL" as the maximum magnitude of the INL values (or equivalently. as the relative accuracy). once gain and offset errors have been removed)... 11..10. whereas a converter with a maximum differential nonlinearity of 0. in a D/A converter. However. what straight line should be used? A conservative measure of nonlinearity is to use the endpoints of the converter's transfer response to define the straight line. the transition values are precisely I LSB apart. 3/4 1/2 . each analog step size is equal to 1 LSB. Integral Nonlinearity (INL) Error After both the offset and gain errors have been removed.5 LSB has its step . The term relative accuracy is sometimes used and is defined to be the accuracy after the offset and gain errors have been removed. Thus. Differential nonlinearity (DNL) is defined as the variation in analog step sizes away from I LSB (typically.: v. Gain error 1/4 Offset error o O'i'o<:. For example. as the effective number of bits. These two definitions are illustrated in Fig. the integral nonlinearity (INL) error is defined to be the deviation from a straight line. or as a fraction of an LSB..456 Chapter 1 1 • Data Converter Fundamentals v. a 12bit accuracy implies that the converter's error is less than the fullscale value divided by 2 ' 2 Note that a converter may have l2bit resolution with only IObit accuracy. An accuMcy greater than the resolution means that the converter's transfer response is very precisely controlled (better than the number of bits of resolution).9 Illustrating offset and gain errors for a 2bit D/A converter.. It is also referred to as the maximum integral nonlinearity error (described shortly) and we will refer to it as such. In other words.t~B. in this book. One should be aware that. whereas in an AID. or lObit resolution with l2bit accuracy. An alternative definition is to find the bestfit straight line such that the maximum difference (or perhaps the mean squared error) is minimized. an ideal converter has its maximum differential nonlinearity of 0 for all digital values.
Monotonicity A monotonic O/A converter is one in which the ontput always increases as the inpnt increases. On the other hand.5 LSB. we define ON!. 01 10 11 (100) Bi.5 LSB. Once again. the conversion time is the time taken for the converter to complete a single measurement including acquisition time of the input signal. then a D/A converter is guaranteed to be monotonic. as in the INL case. . In other words. many monotonic converters may have a maximum ON!. values. the maximum sampling rate is the speed at which samples can be continuously converted and is typically the inverse of the conversion time. error is less than 0.. However. the siope of the 0/A converter's transfer response is of only one sign.11. the equivalent term for AID converters is missing codes. yet they still maintain a high sampling rate.1 0 integral nonlinearity error in a 2bit D/A con sizes varying from 0. a converter is guaranteed to be monotonic if the maximum INL is less than 0. If the maximum ONL error is less than I LSB. D/A Settling Time and Sampling Rate In a O/A converter. greater than 1 LSB. The sampling rate is the rate at which samples can be continuously converted and is typically the inverse of the settling time. An NO converter is guaranteed not to have any missing codes if the maximum ONL error is less than I LSB or if the maximum IN!. Missing Codes Although monotonicity is appropriate for 0/A converters.5 LSB. one should be aware that some converters have a large latency between the input and the output due to pipelining or multiplexing. 3/4 1/2 Integral nonlinearity error (bestfit) . the settling time is defined as the time it takes for the converter to settle to within some specified amount of the final value (usually 0. 1J.'Integral nonlinearity error (endpoint) 1/4 o 00 verter. Similarly.: v..5 LSB). For example. a sampling rate of 500 kHz) yet a latency from input to output of 24 us. values for each digital word. AID Conversion Time and Sampling Rate In an AID converter.e. Fig. However. a pipelined 12bit AID converter may have a conversion time of 2 !ls (i.5 Performance limitations 457 v.5 LSB to 1. whereas others sometimes refer to ONL as the maximum magnitude of the ON!.
signed. AID converter with frequency lin' Mathematically. Dynamic Range The dynamic range of a converter is usually specified as the ratio of the rms value of the maximum amplitude input sinusoidal signal to the rms output noise plus the distortion measured when the same sinusoid is present at the output. Hence. For an AID converter. However. The rms output noise plus distortion is obtained by first eliminating the sinusoid from the measured output. applied to an Nbit. at. V less than I VLSB ' we see that L\. Also.458 Chapter 1 I • Data Canverter Fundamentals SamplingTime Uncertainty Both AID and 0/A converters have limited accuracy when their sampling instances are ill defined. de inputs may show full 8bit performance even at the maximum sample rate of 200 sample/s. for sinusoidal waveforms. For example. At the zero crossing. it is a more realistic way of measuring the performance of a converter than extrapolating the nonlinearity performance found using de inputs. Dynamic range can also be expressed as an effective number of bits using the relationship presented in (11. 200MHz. will require . To quantify this sampling time uncertainty. also known as aperture jitter. 40 MHz.26) Since the rate of change (or slope) of Vin at the peak of a sinusoidal waveform is small. if an 8bit. a highfrequency. an 8bit converter sampling a fullscale 25DMHz sinusoidal signal must keep its samplingtime uncertainty under sps to maintain 8bit accuracy. In a 0/A converter. AID converter has a bandlimited preamplifier or a slewrate limited sample and hold. consider a fullscale signal.28) For example. sinusoidal input.16). It should be noted that this approach often results in a dynamic range measurement that is a function of the frequency of the sinusoidal input. or a leastmeansquared fit can be used to find the amplitude and phase of a sinusoid at the input signal's frequency and then subtracting the bestfit sinusoid from the output signal. Vref 2 sm(2ltl inl) . sampling time uncertainty is less of a problem near the peak values. the maximum rate of change for this waveform occurs at the zero crossing and can be found by differentiating V. Vin. we find that If L\.n with respect to time and setting t = D. IMHz signal. say. However. a similar approach can be taken by using an FFT and eliminating the fundamental of the output. = 2 NIt Iin (11. (11.t represents some samplingtime uncertainty.n v. the output sinusoid can be eliminated by using a spectrum analyzer and ignoring the power at that particular frequency.. the same 5ps time accuracy is required for a 16bit converter operating on a fullscale.t < ltl. and if we want to keep L\.
Thus.25) we have EgafO(O/A) = ( 3.022 LSB off each value.011 : 0. Solution We first note that I LSB corresponds to Vre.. most Ibit oversampling converters have this desirable property since they do not rely on component matching and their distortion level is often a result of weak nonlinear effects at the input stage.1 1.5 (11.49 1 0. Find the effective number of bits of ab.31) . which is often a desirable property to have.= 0.011 = . as the input signal level is decreased.507 : 1. For example.495 : 2.04) = 1. the distortion level decreases as the input signal level is decreased.I) = 0.(2' .5 Performance Limitations 459 the input stage to track a rapidly varying signal and may result in only 6bit performance.5 (11. Finally.501 : 1. . we see that the offset error is given by EOff(O/A) 0. it should be mentioned that the distortion level (or nonlinearity performance) of many converters remains at a fixed level and is not a function of the input signalleve!.002: 1. Find the effective number of bits of relative accuracy. This behavior occurs because the distortion level is often determined by component matching and thus is fixed once the converter is realized. in some converters. However.lz' = 0.5 7 (11.011) ..4 Consider a 3bit O/A converter in which V re. the new value for 1. Find the INL (endpoint) and ONL errors (in units ofLSBs). = 4 V. For example.:. whereas the gain error is eliminated by subtracting off scaled values of the gain error. Find the offset and gain errors in units of LSBs.996: 2. For INL and ONL errors.993 0.022 + (2)(0.30) 2. EXAMPLE 11. 4.491} 1.002 . and since 0..5 V corresponds to I LSB. with the following measured voltage values: {0.olute accuracy. we first need to remove both offset and gain errors in the measured 01A values.0. from (11. The offset error is removed by subtracting 0. the signaltodistortion ratio decreases. Since the offset voltage is II mY.996 : 3.022 LSB 0.002 (scaled to I LSB) is given by 1.04 LSB 0. 3.5 V. 2.29) For the gain error. 1.
5mY value to effective bits in the same manner as in part 3.007 LSB.O: 0.993: 2.5 x 10 6J = 63 dB (11.e! = 4 Y.004 : 0.76 = 10.007 : 0.993 : 4.007 : 0.33).004 : 0. gainfree.460 Chapter 1 1 • Data Converter Fundamentals Thus. which.004 : O} For DNL errors.002 : 0. giving us INL errors: {O : 0. scaled values are given by {O. scaled values to give DNL errors: {0.003 : 0.2 effective bits 6. what is the effective number of bits for the converter? Solution Using (l1.35) .007 : 0. For relative accuracy. 3.003 : 0. we use the INL errors found in part 2.76 In this case.32) which results in an absolute accuracy of Nabs = 8. If the fundamental has a normalized power of I W while the remaining power is 0. resulting in a relative accuracy of N. To relate this IImY value to effective bits. we find the largest deviation between the measured values and ideal values. For absolute accuracy.33) = IOIOg[ 1 0.002 : 0. II mY should correspond to I LSB when V. we have the relationship (11.004 : 7.02N eff + 1. we calculate the INL errors as the difference between these values and the ideal values. EXAMPLE 11. occurs at 0 Y and is II mY.5 bits.5 Il W .1.5 A fullscale sinusoidal waveform is applied to a 12bit AID converter.34) Substituting this SNR value into (11.0} Since these results are in units of LSBs.2 bits.998 : 1.997 : 3.997 : 6. We relate this 3.l6). we find the difference between adjacent offsetfree. the signaltonoise ratio is found to be SNR (11. whose maximum magnitude is 0. the offsetfree. we have SNR = 6. we find Neff = 63 .e' = 10.004 : 0. or equivalently.004} 3.5 mY.005 : 0. in this case. gainfree. and the output is digitally analyzed. In other words.02 (11. 4.
1986. Prentice Hall.3. the Netherlands. New Jersey. Starting with two 4bit 2'scomplement words.7 have? How many bits of relative accuracy does it have? A IObit AID converter has a reference voltage. when a sinusoidal input of I V pp is applied? What size input would result in an SNR of a dBO Find the equivalent of (11.5.) that would accomplish such an addition. +5. and 7 are added together while any overflow effects are ignored. by using 4bit 2'scomplement words. we want to add +5 and +7 to obtain the correct answer of + 12 with a 5bit word.3 11.Ol V} {Ol H 1. 11.95. Grebene.97 V} {II H3. AnalogDigital Conversion Handbook.4 11.OI. Kluwer Academic Publishers. A.2.19) for 2'scomplement coding. the correct final sum is obtained when the numbers +5. xnor.5 11. V ref .6. Integrated AnalogtoDigital and DigitaltoAnalog Converters. van de Plasse he.7 Problems 461 11. Show how an extra bit can be added at the left of each of the 4bit words such that numbers up to ± 15 can be represented. 1984.8 11. How many bits of absolute accuracy does the converter in Problem 11. John Wiley & Sons.08).7 11.02 V} {IOH 1. Show that. tuned to 10.24 V at 25°C.e. unipolar D/A converter with VLS B = 1 mY. New York. Find the maximum allowable temperature coefficient in terms of (~V)/oC for the reference voltage if the reference voltage is allowed to cause a maximum error of (±l/2) LSB over the temperature range of 0 to 50°C.00. gain error. nor. nand. In units of LSBs. R.02 V} 11.10 .7 PROBLEMS 11. maximum DNL.2 For an ideal IObit. show a simple logic circuit (i.03. Englewood Cliffs.6 REFERENCES Analog Devices.) The following measurements are found from a 3bit unipolar D/A converter with V ref = 8 V: (D. find the offset error. Consider the following measured voltage values for a 2bit D/A with a reference voltage of 4 V: {OOHO.6 11.11. 1.02. what is the largest output voltage? What is the SNR for an ideal 12bit unipolar AID converter with V ref = 3 V..02.7. What is the representation of +8 and 8 in 5bit 2's complement? Assuming a circuit added only one of these two numbers to an arbitrary 5bit word.2. Bipolar and MOS Analog Integrated Circuit Design. Dordrecht.9 11. and maximum INL. 1994. This approach is called sign extension and can be used to increase the word size of any number. (Hint: Note that the 4 LSBs in +8 and 8 are all a and thus do not need to be added.96. B. etc.1 11.
worst absolute and relative accuracies.12 In units of LSB. Restate the relative accuracy in terms of an Nbit accuracy.5LSB absolute accuracy.462 Chapter 11 • Data Converter Fundamentals 11. and worst differential nonlinearity. What samplingtime uncertainty can be tolerated for a l6bit AID converter operating on an input signal from 020 kHz? . find the offset error. Find the maximum magnitude of quantization error for a l2bit AID converter having V ref equal to 5 V and 0. gain error.11 11.
which is due to the parallel combination of pchannel and nchannel transistors. 12. depending on the digital input word. 12.1. 1978]. when only nchannel pass transistors are used. transmission gates might be used rather than nchannel switches. Nyquistrate O/A converters can be roughly categorized into four main types: decoderbased. the resistorstring D/A was used to realize an AID converterin the reference. a transmissiongate implementation can operate closer to the positive voltage supply. the transistortree decoder can be laid out quite compactly since no contacts are required in the tree. and only one. a transmissiongate approach has extra drain and source capacitance to ground.1 DECODERBASED CONVERTERS Perhaps the most straightforward approach for realizing an Nbit O/A converter is N to create 2 reference signals and pass the appropriate signal to the output. Oversampling 01 A converters are discussed separately in Chapter 14 due to their importance and because they are best described using many signal processing concepts. lowimpedance path between the resistor string and the input of the buffer.1 The switch network was connected in a treelike decoder. However. Notice that there will be one. and that path is determined by the digital input word. 1. Also. thermometercode. binaryweighted. and hybrid. but this extra capacitance is offset by the reduced switch resistance. We refer to such 01A converters as decoderbased converters. an nchannelonly approach is not much different in speed than a CMOS transmissiongate implementation.CHAPTER NyquistRate OfA Converters In this chapter. 463 . Resistor String Converters One of the first integrated MOS 8bit 01 A converters was based on selecting one tap of a segmented resistor string by a switch network [Harnade. a variety of methods are discussed for realizing integrated Nyquistrate digitaltoanalog converters (OAC). Bin' In a CMOS implementation. as in the 3bit O/A converter shown in Fig. In addition. In fact.
neighbor tap. in a multiplying 01A.. L Bin = b. L b3 L L b3 b. A useful technique for estimating the settlingtime behavior in RC type circuits (i.464 Chapter 12 • NyquistRate D/A Canverters v.1 Resistorstring 3bit D/A converter with a transmissiongate.e. circuits that have only realaxis poles) is the opencircuit timeconstant approach [Sedra.. Also. 1991]. L b. treelike decoder. the accuracy of this O/A depends on the matching precision of R in the resistor string. the delay through the resistor string would also be a major source of delay since Vr ef would become a second input signal.2' + b323 = Fig. the use of polysilicon resistors that have a resistivity of around 2030 (ohms per square) can result in up to 10 bits of accuracy. L b3 L b3 L b. independent voltage sources are replaced with ground (independent current sources are opened).. . the dominant highfrequency time constant is estimated as the sum of the individual time constants due to each of the capacitances when all other capacitances are set to zero (i. Although this resistormatching precision depends on the type of resistors used. Specifically. L v.e.z:' + b. To find the individual time constant for a given capacitance. R b3 L R R R 2 resistors N L b3 b. 12. the 01A converter has guaranteed monotonicity since any tap on the resistor string must have a lower voltage than its upper. and the resistance seen by that capacitor is determined. With a resistorstring approach. The delay through the switch network is the major limitation on speed. if we assume the buffer's offset voltage does not depend on its input voltage. However. replaced with open circuits).: + (Buffer) R R R R L b3 b3 L b. L b.
we have v out = (I _ e'I'h))V p  Thus. 12. RCO + 2 + . the dominant highfrequency time constant. for a large n. is estimated as ~ :.3.12. EXAMPLE 12. In a higherspeed implementation.2 Estimating the time constant for n resistors and capacitors in series.1 Show that an estimate of the time constant for a network of n resistors. and a single bus is connected to a single resistorstring node.999 Vp. 12.. 12. with capacitive loading C at each node (see Fig. This approach takes more area for the decoder and also results in a large capacitive loading on the N single bus because the 2 transistors' junctions are connected to the bus.1 DecoderBased Converters 465 iT···TJL t = a = = e r = RC[~) Fig.. However. r.1 percent of its final value? Solution The opencircuit time constant due to the first capacitor on the left is simply RC. the dominant time constant can be estimated by Using this time constant to estimate the output voltage charging behavior. is given by t = RC(n 2/2). as shown in Fig. for You' to equal 0. logic can be used for the decoder. + n) The sum from I to n can be shown to be equal to n(n + 1)/2 and. if the digital decoder is pipelined. each of size R in series.2). The second capacitor from the left has an individual time constant of 2RC and so on. Thus. the DfA can be moderately fast. . thus. How much settling time is required for the output to settle to 0.we find that a time of about 7 t is needed.
Thus. for a lObit converter. Fig. this approach would have a capacitive load of 64 junctions. Unfortunately. One of these bit lines is then connected to the output buffer by the bitline decoder. the most significant bits. Notice that the total number of transistor junctions on the output line is because a set of transistors is connected directly to the output line and now 2 another set is connected to the chosen bit line. Folded ResistorString Converters To reduce the amount of digital decoding and large capacitive loading.3..3 Resistorstring 3bit D/A converter with digital decoding. fiN . 12. This operation connects a block of four adjacent resistor nodes to the fourbit lines. all the bit lines must be pulled to new voltage levelsinot just the one bit line connected to the output buffer. cc '0 b. 1988].12. a folded resistorstring D/A can be used. which reduces the total decoding area. (b" b}. when a word line goes high. This approach makes the decoding very similar to that for a digital memory. ~ o 2 (all equal sizes) Nresistors 0 s b.024 junctions when we use the digitaldecoding approach shown in Fig. determine the single word line to be selected (all others will remain low).466 Chapter 12 • NyquistRate D/A Converters v. as opposed to 1. as shown in Fig. b. To convert a digital input in this 4bit example.4 [Abrial. 12. the increase in speed is not equal to this large ratio since.
the output is determined by the lower LSBs where extra logic must take into account that sometimes the top intermediate buffer has the higher voltage.5 [Holloway. lowpower applications. This approach requires only 2 x 2 /2 resistors. A 4bit folded resistorstring D/A converter. whereas at other times it has the lower N voltage.12. the three MSBs determine which two adjacent nodes of the first resistor string are connected to the two intermediate buffers. voltageinsensitive offset voltages.. a second tapped resistor string is connected between buffers whose inputs are two adjacent nodes of the first resistor string. In the shown 6bit example. b2 o Ql o '0 B '" v.4 b. Finally. 12.. The second resistor string linearly interpolates between the two adjacent voltages from the first resistor string. as shown in Fig. 2 to 1 of 4 decoder '" Output line b.. 1984].12.. Multiple RString Converters In this variation. the opamps must be fast and low noise.: ~' ' L '. o 0 <1> ~ 2" Resistors (all equal sizes) . making it suitable for higherresolution. However. which can be achieved using a . assuming the opamps have matched. This approach also has guaranteed monotonicity.1 DecoderBased Converters 467 Word lines b. Fig.
since the second resistor string forms the lower LSB . What is the matching requirement of the second resistor string. However. BiCMOS process. D/A converter must match to 0. the matching requirements of the second resistor string are not nearly as severe as those for the first string.5 Multiple Rstring 6bit D/ A converter.2 Assume that the first resistor string of a lObit. 2 X 2 N/ 2 Resistors (all equal sizes) Fig. and that the first string realizes the top 4 bits. multipleRstring.. EXAMPLE 12. Another point to note here is that. which realizes the lower 6 bits? Solution Errors in the first resistor string correspond directly to errors in the overall D/A output. 12. since the second resistor string is used to decode only the lowerorder bits.1 percent. V 0"..468 Chapter 12 • NyquistRate D/ A Converters Vre l + +1:!:' >'_.
12. 12. If it is obtained off chip.2 BINARYSCALED CONVERTERS The most popular approach for realizing at least >. but binaryweighted arrays of charge are also commonly used.ome portion of Of A converters is to combine an appropriate set of signals that are all related in a binary fashion. where a negative output can be realized by changing the clock phases of the input switches so an inverting amplifier is realized l Martin. followed by charge redistribution and current mode. In this section. ~. the cost is significantly higher.2 BinaryScaled Converters 469 bits (6 bits.6.12. the bottom of the resistor string can be connected to V re l . high causes a negative output. and the circuit needed to realize a dual power supply with exactly matched voltages is nontrivial since any error in matching will result in an offset error.6% (12. YOU! or V O Ul Fig. errors in the matching of these resistors cause an error only in the LSB portion of the output voltage. 1987 j. the second resistor string need match only to 2'xO.1) Signed Outputs In applications where negative output voltages are required. 12. This binary array of signals might be currents (in resistor or current approaches). As a result. . Many papers on Of A converters assume that V re l is available but do not explain how it was obtained. resistor approaches are first discussed. One possibility is to use a switchedcapacitor gain amplifier. in this case).I% = 1. Another possibility is to sense the center tap of the resistor string and adjust V rei to get the center tap voltage equal to zero volts. This requires a negative power supply.6 Using an SC gain amplifier to realize a signed output from a unipolar (positive) DAC output. as shown in Fig. o.
it does have N some disadvantages. we have YOU! = RFV. This large current ratio requires that the switches also be scaled so that equal voltage drops appear across them for widely varying current levels. (12.. as shown in Fig. The basic architecture for a 4bit converter is shown in Fig. as discussed on page 474. note that the voltage node. Here.470 Chapter 12 • NyquistRote D/A Converters BinaryWeighted Resistor Converters Binaryweighted resistor converters are popular for a bipolar technology so that bipolar differential pairs can be used for current switches. ReducedResistonceRatio Ladders To reduce the large resistor ratios in a binaryweighted array. VA' is equal to onefourth the reference voltage. it comes from ground.3) Although this approach does not require many resistors or switches. 12. Finally. ) = (~V.12.8. The resistor and current ratios are on the order of 2 . V.:~:~. 12.7 Binoryweiqhted dbit resistor D/A converter. Therefore. Also note that an additional 4R resistor was added (to ground) such that resistance seen to the right of the 3 R resistor equals >... then the current to the i th resistor comes from the virtual ground of the opamp. signals in portions of the array can be scaled by introducing a series resistor.2) where Bin (12. depending on N. this approach is prone to glitches for highspeed operation.0 Vout 2R 4R 8R 16R = v ref Fig.e. monotonicity is not guaranteed..ef' as a result of inserting the series resistor of value 3 R.7... is a I. If b..e}n = 3 b ]2I + b 2 2 2 + b 3 2.(:~.+ . . otherwise. Also. which may be large..
12. = 2R R4 = 2R II 2R = R R. N.: 4R 2R 4R = ~ v ref R Fig. Note. R2RBased Converters A very popular architecture for D/A converters uses R2R ladders. t. R. t. Straightforward analysis shows that this converter has the same relationship to the binary digital signals as in the previous binaryweighted case.9 R2R resistance . Thus. 12.8 Reducedresistcncerotio 4·bit D/A converter.2 BtnorySccled Converters 471 b. Consider the R2R ladder network shown in Fig. ~ = t. however. t. R R t. described next. independent of the number of bits. These ladders are useful for realizing binaryweighted currents with a small number of components and with a resistance ratio of only 2. Analysis gives R.12. v. R. one arrives at a structure commonly referred to as an R2R ladder. R R4 R' 4 2R 2R 2R ~ = I. 2R ~ = 13 2R ~ = 14 = Fig. R3 = R + R = 2R = 2R II R. t. ladder. but with onefourth the resistance ratio.. R'i Rs R. note that. t.' = 2 R for all i. Finally.9. by repeating this procedure recursively to a binaryweighted ladder.4) and so on. This result gives the following current relationships: Ri v. the current ratio has remained unchanged. 12. = R 4 (12.
we see that I.8) and (12. ..5) Also. + 1. the voltage at node 2 is onehalf the voltage at node I.9) However. giving I. 4R (12. v. 12.. (12..) As a result.r :: b3 .r R b.r :: b.: v. where equal currents flow through all the switches. to improve matching properties.... = 8R and so on.6) At node 3./2  Fig. For this R2R based circuit.10 4bit R2R based D/A converter.. v. as already mentioned..10. (The resistors of size 2R are made out of two resistors of size R. although the resistance ratio has been reduced.7) Thus.: :: q. However. = V re. 12.. ~Vref 2R R ~~ 2R R ~~ 2R ~~ 2R 2R +I.. 12. . this configuration is typically slower since the internal nodes . = 2R v. and thus the switch sizes are usually scaled in size to accommodate the widely varying current levels. this R2R approach usually gives both a smaller size and a better accuracy than a binarysized approach. :: b. A 4bit D/A converter that uses an R2R ladder is shown in Fig.472 Chapter 12 • NyquistRate D/A Converters I. therefore I.. the R2R ladder can be used to obtain binaryweighted currents while using only a singlesize resistor...11.:   (12. the current ratio through the switches is still large. One approach to reduce this current ratio is shown in Fig./(2R) (12. the voltage divides in half once again.
As in the SC gain amplifier.12. the shown circuit is insensitive to opamp inputoffset voltage.: C2 Fig. Ilf noise.11 R2R ladder D/A converter with equal currents through the switches. as shown in Fig.2 BinaryScaled Converters 473 of the R2R ladder now exhibit some voltage swings (as opposed to the configuration in Fig.12 Binaryarroy chorgeredistribution D/A converter. and finiteamplifier gain. and a deglitching capacitor should be used. carefully generated clock waveforms are required to minimize the voltage dependency of clock feedthrough. 12. as in the SC gain amplifier. 12..12. an additional sign bit can be realized by interchanging the clock phases (shown in parentheses) for the input switches. It should be mentioned here that.. Also. 2) ~ 4C b2 2C b3 C b J 1 J 4 J {$2' ~ I $2 v.10 where internal nodes all remain at fixed voltages). . I v ss Fig. the digital codes should be R 2R 2R R. 12. R R R >.. 12. v. ChargeRedistribution SwitchedCapacitor Converters The basic idea here is to simply replace the input capacitor of an SC gain amplifier by a programmable capacitor array (PCA) of binaryweighted capacitors. Also. BC 'F b.
.3. CurrentMode Converters Currentmode D/A converters are very similar to resistorbased converters. as shown in Fig. This glitch phenomenon is illustrated in Fig. which is highly unlikely since the branches have different currents. as discussed next. a glitch occurs at the output unless these two delays are ex.14). but this approach slows down the circuit. However. 0. Implementations of currentmode D/A converters are more fully discussed in Section 12. ..13. Another approach is to use a sample and hold on the output signal. when the digital input code changes from aIII . if the LSB switches tum off slightly after the MSB current. all of the N . the current will temporarily go to its maximum value. and the upper portion of each current source always remains at ground potential. Alternatively..474 Chapter 12 • NyquistRate D/A Converters changed only when the input side of the capacitors are connected to ground.. 12. The basic idea is to switch currents to either the output or to ground. the most popular way to reduce glitches is to modify some or all of the digital word from a binary code to a thermometer code. causing the current to temporarily fall to zero.I LSBs tum off and the MSB turns on. I to 1000 .. and thus the switching time is dependent on the sign bit. . ><..14. it is possible that the currents due to the LSB switches will turn off slightly before the MSB current. Glitches are mainly the result of different delays occurring when switching different signals. directly related to switching signals.. The glitch disturbance can be reduced by limiting the bandwidth (by placing a capacitor across the resistor R t in Fig. the output current is converted to a voltage through the use of R F . In either case. {b I' b" .13 Binaryweighted currentmode D/A converter.<l V o ut 5V Fig. where thermometer codes are introduced. Here. 12.12. Finally.actly matched. which requires some extra digital complexity. For example. Glikhes Glitches are a major limitation during highspeed operation for converters that have digital logic. but are intended for higherspeed applications. 12... b N } .
A thermometer code differs from a binary one in that a N N thermometer code has 2 . For example. 12. as shown in Fig. 12. Here. One method to realize a OfA converter with the use of a thermometercode input N is to build 2 . Clearly. Typically. a thermometerbased converter does have advantages over its binary counterpart.12.12.1. ond 12 represents the sum of the N .I equalsized resistors and switches attached to the virtual ground of an opamp.1 Thermametercede representafians far 3bi! binary values Binary Decimal Thermometer Code b.15. in a thermometercode representation. 0 0 0 0 0 I d. as we will see. such as low ONL errors. guaranteed monotonicity. Note that monotonicity is guaranteed here since. 0 0 0 0 I 1 I b2 0 0 I b. and reduced glitching noise. 0 0 0 0 I d5 0 0 0 I d. causing a glitch of zero current. 0 0 0 0 0 0 0 I d2 0 0 0 0 0 0 I I d.I digital inputs to represent 2 different digital values.3 ThermometerCode Converters 475 >''_ V out Fig. The codes for the remaining values in this 3bit example are shown in Table 12. represents the MSB current.1 LSB currents. with a 3bit binary input. 0 0 I d7 0 I 0 I 2 3 4 5 6 7 I 0 0 I I I 1 I I I I I I I I I I I I I I 1 I I I I .14 Glitches. the decimal value 4 is binary coded as 100 while its thermometer equivalent is 000 1111. However. 1. a thermometer code is not a minimal representation since a binary code requires N only N digital inputs to represent 2 input values. Table 12. 0 I 0 I 0 I 0 I d.3 THERMOMETERCODE CONVERTERS Another method for realizing a OfA converter is to digitally recode the input value to a thermometercode equivalent. the MSB Current turns off slightly early. the number of Is represents the decimal value.
. b. The same argument can be used to show that the total area required by the transistor switches is the same since transistors are usually sizescaled in binaryweigl1ted designs to account for the various current densities. one more digital value in the thermometer code goes high. This is not necessarily the case for a binaryarray 01A converter since mismatches between elements may cause the output to go lower even though the digital input value is increased. 2R. 12. and since resistors are created on an integrated circuit using area that is proportional to their size. as compared to binaryarray approaches. since banks of resistors are never exchanged at slightly different times when the output should change by only I LSB. It is also of interest to note that the use of a thermometer code does not increase the size of the analog circuitry compared to a binaryweighted approach.15 A 3bit thermometerbased D/A converter. All transistor switches in a thermometercode approach are of equal sizes since they all pass equal currents. resulting in the largest ONL at this location. each approach requires the same area (ignoring interconnect). 12. causing additional current to be drawn out of the virtual ground and forces the opamp output to go some amount higher (never lower). and 4R are needed for a total resistance of 7 R. Finally. 12. the resistor values of R. it should be mentioned that a thermometercode chargeredistribution O/A can also be realized. b. This total value is the same as for the 3bit thermometercode approach shown in Fig.476 Chapter 12 • NyquistRate D/A Converters when the binary input changes to the next higher number. as shown in Fig. Perhaps more importantly. It should be noted that this mismatch effect is usually the largest in a binaryarray converter when the MSB is changed. b.15. Binarytothermometer code conversion )+0 VO U 1 Fig.16. In a 3bit binaryweighted approach. a O/A converter based on a thermometer code greatly minimizes glitches. It should also be mentioned here that latches can be used in the binarytothermometer code conversion such that no glitches occur in the digital thermometercode words and pipelining can be also used to maintain a high throughput speed.
Vout' .3 ThermometerCode Converters 477 c 21 Top capacitors are connected to groun d Bottom capacitors a re connected to Vref 0 0 /' I I $.17. 12. 1986. c /' I I ~2 c I I o o o ~c. 1986. Current is switched to the output when both row and column lines for a cell are high. 1 Voul "'o o 0 0 o o o c I I /' c I I "'  ~ Fig. 12. has been the basis for a variety of designs (see. rather than an output opamp.16 Thermometercode chorgeredistribution D/A converter.12. for example. Also. Chi. shown in Fig. in highspeed applications. thermometercode decoders are used for both the row and column decoders. Note that cascade current sources are used here to reduce currentsource variation due to voltage changes in the output signal. resulting in inherent monotonicity and good DNL errors. [Miki. and Letham. the output feeds directly into an offchip 50Q or 75Q resistor. ThermometerCode CurrentMode D/ A Converters A thermometercodebased currentmode D/A converter. 1987])_ Here.
Vout is shorted to ground. the drainsource voltage across the current source. To avoid the use of two logic driving levels. the drain of Q. is pulled low and the circuit takes longer to respond.17 switch. SingleSupply PositiveOutput Converters The architecture for a fast singlesupply positiveoutput D/A (often used in video RAMs. 12. 1988]. If both logic levels are high simultaneously. If both logic levels are low at the same time.12. . Here. whereas 0 3 and 0 4 implement a cascode current source.18 [Colles. as described in the next approach. and if. '8 e Q) 1. when the current is steered to the output through O 2 . Vout Column decoder Q. (Note that the opamp input connections appear reversed but are correct due to signal inversion by Q4. which are known as RAMDACs) is shown in Fig. 0 3 .rather than to the inversion of the bit signal. For example. remains mostly constant if Vout stays near zero. to maintain accurate current matching that is independent of Vout . a matched feedback loop is used to set up accurate known currentsource biasing. should be connected to a de bias voltage. one side of each differential currentsteering pair is connected to Vbias . and Q 2 form the current Fig. Q . such that Q.478 Chapter 12 • NyquistRate D/A Converters + You! 000 000 All current sources are of equal value. the gate of Q. Note the need here for precisely timed edges of d..Src array Bias voltages ~oj II: ~ ~oj Thermometercode currentmode D/A converter.) Also. remains in the active region.
. it is worth mentioning that the values of Id . the voltage swing at the common connections of the current switches (for example. Since the accuracy requirements are reduced for the remaining bits. this common connection should be at a voltage where the output transistors are just turned off when the current is steered to ground. and can therefore be clocked at the maximum rate without the need for precisely timed edges. . the switching feedthrough from the digital input connected to the grounding transistor (for example. To accomplish this high degree of matching. independent of transistor mismatches and charge injection. It should also be noted that when a switch is turning on or off. we want to set all the currents I d .18 A singlesupply positiveoutput D/A converter. ThermometerCode Converters 479 v. to the same value as I d " and so on.) actually enhances the switching. O 2 and 0 3 effectively fonn a cascode current source when they drive current to the output. but do need to accurately match each other. once calibration is accomplished on Id I' the same current source.: 50 n Fig. The basic idea for realizing 63 accurately matched current sources for the 6 MSBs is illustrated in Fig. Id 2 . Iref • is used to set the next current source. through the use of the shift register. to the same precise value. Finally. To maximize speed in this converter. Thus. a binary array was used in their implementation. each current source Id i is periodically calibrated with the use of a single reference current source. 0. and d. Here. d.12. need not precisely equal Ire. fo v.: Q3 + d. 1988]. I ret. To keep this swing small. This approach was used to design a 16bit audiofrequency D/A converter.3 Q.. In other words. where the 6 MSB were realized using a thermometer code. 12. R re ! fo v.: v. 12. Dynamically Matched Current Sources The use of dynamic techniques with current switching is a method for realizing very wellmatched current sources (up to 16bit accuracy) for audiofrequency D/A converters [Schouwenaars. note that this design does not use two logic driving signals. Before proceeding to see how this calibration is accomplished. 0" 0" and 0 3 ) should be small.19.
' A major limitation in matching the 64 current sources is due to the differences in clock feedthrough and charge injection of the switches SI' Since mismatches will always exist between different switches. The method for calibrating and using one of the current sources is shown in Fig. Finally.9I ref was added in parallel to Of' so that 0 [ needs only to source a current near 0. a large.20. even though only 63 are required for the 6 MSB. the current source is connected to the reference current I re f . During regular system use. the current source 0. the best way to keep all current sources equal is to minimize the total amount of clock feedthrough and charge injection. lowtransconductance device can be used (a W/L = 1/8 might be used). During calibration. so that I d 1 equals I ref . Id l remains nearly equal to I ref. note that 64 current sources are calibrated. This extra current source is needed so that the 0/A converter can continuously operate.480 Chapter 12 • NyquistRate D/A Converters Shift register o o 1 0 o o Switch network To D/A Fig..assuming the drainsource voltage of O. These nonideal effects can be minimized by having the capacitance C gs and bias voltage V GS large. Also. the gate voltage (and therefore current) is determined by the voltage stored on the parasitic capacitance. each current source must be recalibrated before the leakage currents (on the order of 10 pAJIlm 2 of junction area) on C gs cause the current source to deviate . any common errors in the calibration stage are not a problem. doesn't change and the clock feedthrough and charge injection of Sf are small. This places whatever voltage is necessary across the parasitic c. 12. Cg. while O[ is configured in a diodeconnected mode. even when one of the current sources is being calibrated. Therefore. (A large VGS voltage implies that a small voltage difference will cause a smaller current deviation. for I d [ . When Sf is opened.19 Dynamically matching current sources for 6 MSB.1 Ire!' With such an arrangement.) To accomplish these requirements. 12.
4 Hybrid Converters 481 I ref I I I ! 8. No mention is made on the upper limit of the clocking frequency. having a large GS and VGS has the added benefit of extending this calibration interval (every 1.0025 percent distortion. 1988] achieves 0. Regular usage by 0. and only dissipated 20 mW. Hybrid designs are an extremely popular approach for designing converters because they combine the advantages of different approaches. a.. (i. e 12. I d 1 .gl ref  Calibration Fig.. I dl 8. it is quite common to use a thermometercode approach for the top few MSBs while using a binaryscaled technique for the lower LSBs.4 HYBRID CONVERTERS Combining the techniques discussed in Sections 12. in the LSBs where glitching and accuracy requirements are much reduced. Fortunately.e.112. to keep it constant independent of the actual current and to keep it matched to its value during regular use) and to speed up the circuit by decreasing the effect of parasitic capacitances on the large I ref bus. However.. Many other additional details are described in [Schouwenaars. 12. Id l a. valuable circuit area is saved with a binaryscaled approach. Q.12. 1988]). C gg . 94 db SIN. 1988]. 92 dB S/(N+O)..3 for realizing different portions of a 0/A converter results in hybrid designs. The clocking frequency is limited to 44 kHz by the digital audio application. This section discusses some useful hybrid designs. 10"' 82 . dummy switches are connected to S 1 to help minimize clock feedthrough by partially cancelling the charge injected. lout I re . The converter in [Schouwenaars. . ~l z . In this way. The converter could also be run using only a 3V power supply..+. during calibration. a pchannelinput commongate amplifier is added to the diodeconnected loop. Also. For example. glitching is significantly reduced and accuracy is high for the MSB where it is needed most.5LSB. This is typically done in dyngmic switchedcurrent circuits to control the drainsource voltage of 0 .20 Dynamically setting a current source.. 8. .gl ref =!=   C gg ~ I Q..7 ms in [Schouwenaars. For example.
CAB: 128C Cc : 256C CB 8 127 : 256C R 127 R126 8 126 ><>0 Vout 5 125 R. .482 Chapter 12 • NyquistRate D/ A Converters ResistorCapacitor Hybrid Converters It is possible to combine tapped resistor strings with switchedcapacitor techniques in a number of different ways. S. In one approach. .. 1989]. 12. an SC binaryweighted DI A converter has its capacitors connected to adjacent nodes of a resistorstring DI A converter.Jf BusB BusA $AO C AO : C $.21 [Yang. Here. For example. (hi or $Si  So 1( 7 bits 1( 8 bits Fig. r R. if v. the top 7 bits determine which pair of voltages across a single resistor is passed on to the 8bit capacitor array. as shown in Fig.21 One example of a 15bit resistorcapacitar hybrid D/A converter. $. S. S. 12. R.
As discussed in Section 12.oVout + Vref vs~ 2 MSBs \. Grebene. High bits are switched to the output. the two MSB currents are obtained in one segment from three equal current sources using thermometer coding. without trimming. In this approach.3. assuming the capacitor array is accurate to only 8 bits. 1979.4 Hybrid Converters 483 the top 7 bits are OOOOOOl. one additional current source from the MSB R/2 + >.22. Schouwenaars.. 1984. The capacitor array then performs an 8bit interpolation between the pair of voltages by connecting the capacitors associated with a I to the higher voltage and the capacitors associated with a 0 to the lower voltage.22 A 6bit segmented D/A converter. and S.. A 6bit segmented D/A converter is shown in Fig. then switches S. For the four LSBs. would be closed. whereas low bits are switched to ground. 12._~ Y _/ 4bit binary LSB segment Fig. while the other S. Segmented Converters Segmented converters have probably become the most popular design approach for D/A converters [Schoeff.12. 1989J has ISbit monotonicity. 12. . 1988J. This approach gives guaranteed monotonicity. The converter in [Yang. the use of a thermometer code for the MSB currents greatly minimizes glitches. switches would remain open. and IOOkHz sampling frequencies for a verylowpower lOmW realization.
24. of SolidState Circuits. of SolidState Circuits. L. J. Vol. December 1986. 23. 12. pp. and C. of SolidState Circuits. A. "A Trimlcss 16bit Digital Potentiometer. 22. John Wiley & Sons. pp. 19. "A HighPerformance CMOS 70MHz Palette/DAC. W. S. Assume that an 8bit resistorstring OfA converter with digital decoding (see Fig. pp. A. D. T." IEEE J. 13581369. Ternes. pp. 21." IEEE J. "A SelfCalibration Technique for Monolithic HighResolution D/A Converters. H. 22.484 Chapter 12 • NyquistRate D/A Converters segment is diverted where it is divided into binaryweighted currents. C. pp. Y. "An 80MHz 8bit CMOS D/A Converter. February 1987. pp. J. which are also switched to either ground or the output." IEEE J. of SolidState Circuits. 24. Groeneveld. C.1. Although this fourLSB segment is not guaranteed to be monotonic. J. New York. Martin. 12. Miki et al. its accuracy requirements are very relaxed. P. Vol. 21. Microelectronic Circuits. pp." IEEE J. J. Vol. Schouwenaars. J. December 1984. 1991. Chi ct al. Groeneveld. Hamade. of SolidStare Circuits. "A LowPower Stereo 16·bit CMOS D/A Converter for Digital Audio. H. W. H. 989996. December 1989. since it is used only for the LSBs. December 1978. Martin. Saunders College Publishing/HRW. 4. S. 12901297. Vol. 785791. 90491 I." IEEE J. H. Bastiaansen. of SolidState Circuits. W. Urquhart. that its pass transistors have an on resistance of 400 n. A. Bipolar and MOS Analog Integrated Circuit Design. "A 27MHz DigitaltoAnalog Video Processor.1988. A." IEEE Inti. Vol. 14. K. R. Vol. Holloway. December 1987. and H. Vol. December 1988. 1. Schoeff. "An Inherently Monotonic 12bit DAC." IEEE J. D. 14581461. Vol. December 1988. 104106.3) has a total resistorstring resistance of 400 n. pp. K. "HighResolution LowPower CMOS D/A Converter.6 PROBLEMS 12.2 Derive an expression for the number of switches in a general Nbit resistorstring Of A converter similar to that shown in Fig. "A SingleChip AllMaS 8bit AID Converter. W. and G. "A Differential SwitchedCapacitor Amplifier. H." IEEE J. 12. Abrial et al. pp. B. 1984. "TTL to CMOS Voltage Level Translator.794. S. of SolidState Circuits. Vol.1 12. Letham et al. P. Smith. SolidState Circuits Conf. 6667. Ozcolak. of SolidState Circuits. Yang and K. granted December 27. H. pp. Colles. December 1986. February 1984. W. "A CMOS Triple lOOMbit/s Video D/A Converter with Shift Register and Color Map. Tenneer. 23." IEEE J. Lee. Sedra and K. L. 983988. Tenneer." IEEE J." IEEE J." patent no. Saul and 1. of Solid Stare Circuits. of SolidState Circuits. Grebene. New York. 12. 10411047.5 REFERENCES A. Vol. A. 6268. J. 3rd ed. December 1979. A. of SolidState Circuits.282. 15171522. K." IEEE J. A. and that the drainsource capacitances to . pp. Schouwenaars. Vol. "Techniques and Technology for HighSpeed D/A Conversion. 13. pp. A. October 1989.
= 5 Y. what percentage matching accuracy is required for each of the o. as shown in Fig. What is the resistor ratio between the largest and smallest resistors? What is the ratio between the currents through the switches for b. and all nodes have a capacitance of 0. 12. 12. respectively. R = 10 kQ. 12. and 1111. R.1 pF. that must be linear to 10 bits. 12.1 percent whereas the second string must match to 1.15LSB and a gain error of 0.7 Consider an 8bit Df A converter built using binaryweighted capacitors. For Vr e . What is the improvement in the resistance ratio compared to using all binaryscaledresistances? 12. and b. 12.12 Show that the Df A converter circuit shown in Fig. 12.. show that no accuracy is lost.1O. how much offsets in the opamps can be tolerated? 12.. 1000. and b.11 operates correctly.. P12. Ignoring all other effects and using the opencircuit timeconstantapproach. What would be the worstcase differential nonlinearity in units of LSBs. where I = I rnA. and at what transition does it occur? 12.5 For a binaryweighted IObit resistor DfA converter (see Fig. find the output levels for the inputs b.01 R 0 12.b.2LSB.1Oare MOSFETS and are scaled so that each has 100 mY across the drain source when on (including 84 .11 For the 4bit R2RIadder DfA converter shown in Fig. as well as between b. What is this circuit's resistance spread? 12.6 It is desired to realize a binaryweighted 4bit resistor DfA converter.7. 12.13 Consider the Df A converter shown in Fig.12. where a single series resistor is applied to an Nblt converter. but add resistors between b.6 percent since the converters realize the top 4 bits and lower 6 bits. and where N is an even number. 12. what is the output error (in LSBs) when R A = 2.VLSS.01 R s? What is the output error when Rc = 2.7). . assume that R F is chosen such that the output goes from 0 to Vref . = 2 kQ and R = 10 kQ. Ignoring R F. and b lO? 12. Ignoring all other nonidealities except for resistance mismatch error.4 (Assume N is even). 12.8 Consider the reducedresistanceratio approach shown in Fig.8).9 Draw the circuit for a reducedresistanceratio 8bit DfA converter (see Fig.11. 12. resistor? 12.1 percent. PI2.4 Assume that the first resistor string of a 10bit multipleRstring DfA converter must match to 0.10 Assuming all the switches in Fig. what is the resistance spread? Now drawa similar circuit.6 Problems 485 ground of its pass transistors are 0. estimate the worstcase settling time to 0. which always remains on). and b. where a resistor is inserted between b.5 pF to ground. where capacitor tolerances are ±0. If this converter is perfectly linear but is found to have an offset error of 0.5 percent.b 3b4 equal to 0000.3 Derive an expression for the number of switches in an Nbit folded resistorstring DfA converter similar to that shown in Fig. 12. Estimate the speed of this circuit if the opamp has infinite bandwidth. b. resistors relative to the b.8.
16 For the circuit in Fig. b. Repeat this sketch if the code signals are overlapping.e.5 V when the MSB is changed. Assuming all the transistors are ideal.12. 12. 12. = RA 2R R Rs .18. find W /L for the OJ needed to set VG5 = 3 V when I'ef = 50 u. v.17 if the design does not incorporate the 0.: Fig. If switch SJ causes a random charge injection voltage of I mY.18 Repeat Problem 12.17..14 a. v.r = Rc b. d..486 Chapter 12 • NyquistRate D/A Converters b. Assume the code signals have logic swings from 0 to 5 V and that the threshold voltage for the transistors equals I V. what is the expected percentage of random variation of the current being held on OJ? 12. P12. whereas binaryweighting is used for the remaining 8 bits? 12. 12. What is the glitch voltage reduced to if a thermometercode approach is used for the top 4 bits.: 2R RD 2R = 5. 12. is IV. 0" and OJ when the code signals. sketch a typical waveform that would occur on the node connecting OJ. and /lnCox = 92 /lA/V'. if OJ must be the source for all of I ref). and that Vb. Assume here that the code signal has a logic swing of 0 to 5 V. and are nonoverlapping.r = b.a.17 A D/A converter is realized using dynamically matched current sources.el extra current source (i.A. .9I. 12.10 = A 12bit binaryweighted D/A converter produces a glitch voltage of 0.20.. VI = I V. as shown in Fig. d. that the threshold voltage for the transistors equals 1 V. goes lowtohigh and hightolow...15 For the circuit in Fig. sketch a typical waveform that would occur on the node connecting 0" 0" and 0 3 when the code signal. 2R R 2R R .
1 INTEGRATING CONVERTERS Integrating AID converters is a popular approach for realizing highaccuracy data conversion on very slowmoving signals.5 LSB offset present in the AID transfer characteristic.1. 13. medium speed. Such a simplification is made so as not to complicate the concepts presented. Before proceeding. it should be noted that when discussing the design of AID converters. A simplified diagram for a dualslope integrating converter is shown in Fig. LowtoMedium Accuracy Successive approximation Flash Twostep Interpolating Folding Algorithmic Pipelined Timeinterleaved 487 . These types of converters have very low offset and gain errors in addition to being highly linear.CHAPTER NyquistRate AID Converters Architectures for realizing analogtodigital converters (ADC) can be roughly divided into three categories (Table 13. In this chapter. Medium Accuracy N (13.1 Different AID converter orchiteclures Medium Speed. Thus. A further advantage of integrating converters is the small amount of circuitry required in their implementation.2): Phase (I) Phase (I) is a fixed time interval of length T 1 determined by running the N counter for 2 clock cycles.1)lowtomedium speed. High Accuracy Integrating Oversampling High Speed.1) LowtoMedium Speed. (I) and (II). 13. design details are discussed for these different approaches except for oversampling converters. Oversampling converters are best described using many signal processing concepts and are therefore discussed separately in Chapter 14. in the following manner (Fig. Dualslope refers to this converter performing its conversion in two phases. and high speed. we usually ignore the 0. 13. One application that has traditionally made use of integrating converters is measurement instruments such as voltage or current meters. we have T 1 = 2 T elk Table 13.
During this interval. C]. the value of V.n_ 1 V (13. the counter is reset and switch 8.To obtain the digital output value.. Phase (I) Phase (II) (Constant slope) ( T.2) R. T 2' as shown in Fig. Control jogic b. ramps up proportional to the magnitude of Yin' Assuming V.. is initially equal to zero (due to a pulse on 8 2 ) . (Three values for three inputs) Fig. Phase (II) Phase (II) occurs for a variable amount of time.V ) = _... the counter simply counts until Vx is less than zero. (. at the end of phase (I). is connected to V ref' resulting in a constant slope for the decaying voltage at Vx. 0 . R. at which point that count value equals the digitized value of the input v.J = + r.I. 13. Time ( ) ( ) T.488 Chapter 13 • NyquistRate AID Converters 8. b.. Fig.) comoaratoj.n_ d. is equal to Yin T / R. 13. Ciock felk.2 for three different input voltages. 13. Thus. switch 8.C. .. (V in is held constant during conversion.. 1_JL. is connected to Yin such that V.2 Operation of the integrating converter for three different input voltages. we have the following relationship for V x: V (I) = _ x f __.C.1 Integrating (dual slope] AID converter. C. where T el k is the period for one clock cycle. At the beginning of this phase.. Counter b. v.
V T = _r_e (t _ T ) + _'"_' R.8) as expected.C. If instead of dualslope. Yin v. (13.5) Since Vx equals zero when t = T. can be defined to be N (13. I f t v. two phases).r'+b.6) and thus T. we find Bou.eIT. the digital output does not depend on the time constant.2 2 + .C.3) Bout = b. we see that by going to a dualslope conversion (i.1) and (13..) . However. once with the input connected to ground and then with the input connected to the signal to be converted. In a quadslope conversion. +R. RIC. = e.C.13. V (13. R. in a dualslope converter. 'R.C. C l ' Although a dualslope converter does not suffer from gain error..7) with (13.ef' In this case.. R.4). should be chosen such that a reasonable large peak value of Vx is obtained without clipping to reduce noise effects. + T 2 ' we can write 0= V.r(N')+bN2and we have (13..8). VI" Thus. Thus . and this error would be a function of the timeconstant value.C. is related to T. the value of this time constant need only be stable during a single conversion for proper operation. we find the equation for Vx during phase (II) to be given by V xCt) = . (13. the counter output.. the number of clock cycles to perform a conversion is 2 N+ '. VI'T. Bout. a dualslope conversion is performed twice. Such an offset error can be calibrated out by going to a quadslope conversion.1 Integrating Converters 489 signal. For example. then a gain error would most likely occur. A subtraction of the two output words causes the offset error to be reduced to zero. it can have an offset error due to opamp offset and other factors.R.z' + b.. From (13.TdT+Vx(T.7) Combining (13.4) To see why this count gives the correct value. a singleslope conversion was used. assuming the digital output count is normalized so that the largest count is unity.e. and C. the worstcase conversion speed occurs when Yin equals V. The conversion speed for these types of converters is quite slow. by the following relationship: (13.r'+···+b N_. R. + bN_1 2(N') + bN2N = . In fact.
C. To quantify the filtering effect. as expected.10) where A and <\> are arbitrary magnitude and phase values. . = 1/(60 Hz).) (13. 180 Hz. if the input signal. find the attenuation of a noise signal around I kHz superimposed on the input signal. 13.) = A sin(l20ltt + <\» (13. In addition.r(V.(T. choosing T. as shown in Fig.(V. 120 Hz.. In fact. we have V (T. I) dr x 0 (13. the worstcase conversion rate is around 7. we have an effective input filter. other frequencies are also attenuated but not fully suppressed as are the harmonics of 60 Hz. 16.n I6o H. equal to an integer multiple of 16. we note that this converter effectively "integrates and dumps" the input signal.12) Note that higher frequencies are attenuated more and that full suppression is achieved at harmonics of 60 Hz. or mathematically. etc.C.). V. Also. Find the required RC time constant and clock rate.)I (ltIT.11) can be shown to equal zero when T. EXAMPLE 13. 0 R. V'n' is a de level with power line noise of 60 Hz superimposed on it. Note that for this same value of T" the harmonics of 60 Hz are also suppressed (i.67 ms).2). remains correct so that the conversion is performed without error.n) dt = _ f. 490 Chapter 13 • NyquistRate AID Converters for a l6bit converter with a clock frequency equal to I MHz.C. However. it should be mentioned that by a careful choice for T" certain frequency components superimposed on the input signal can be significantly attenuated. 240 Hz. is an integer multiple of 1/(60 Hz) (i..e. For example.n. In this way. Now substituting this relationship for V'n into (13. the peak value.67 ms filters out the power line noise. being given by IH(f)1 = !Sin(ltIT.11) R. we write V'n as Yin = Vin(ideal) + V in(60 Hz) (13. resulting in a filter transfer function. 0 R.9) where Vin(ideal) is the desired de level and Vin( 60 Hz) is the interfering 60 Hz noise. Here we have assumed that T.e. being 4 V. To see why this filtering effect occurs.6 Hz.1 It is desired to build a 16bit twoslope integrating AID such that a maxi mum input signal of V'n = 3 V results in the peak voltage of V. input noise signals at 50 Hz and harmonics should be significantly attenuated.) = _r(V.Since the Fourier transform of a square pulse is a "sintxj/x" type response. the lasllerm in (13..). V'n(60 H. H(f).3. Such an integratingthenreset behavior results in the impulse response of this converter being a square pulse of length T r.'deaI J) dT. Finally.
16) Finally.C. and T.nT.17) which implies the attenuation is 36 dB. V. Vx is given by V. = 1/(60 Hz).14) To find the RC time constant needed.1 Integrating Converters 491 o IH(f)1 ¥ 20 dB/decade slope (dB) 10 20 30 10 Fig. V =x R.3 60 100 20180240300 Frequency (Hz) (Log scale) Magnitude response of the effective input filter for an integratingtype con verter with T. we require a clock frequency of lelk =  I Telk T. attenuation is reduced halfway between harmonics.13) Thus. (13. we note that at the end of phase (I).12).13.28 MHz (13. (13.C.3 x 10'3 It x 975 Hz x 20 ms (13. the attenuation of a IkHz signal is infinite since it is a harmonic of 50 kHz. we choose T. = 20 ms results in R. However. for a 16bit converter. so we find the gain for an input signal at 975 Hz to be IH(I)I = ISin(1t x 975 Hz x 20 ms)1 = 16.n = 3 Y. = 1 = 20 ms 50 2" = = 3. = 15 ms (13. 13. . as seen in (13. Solution Since 50 Hz and harmonics are to be rejected.15) and using the values of Vx = 4 Y.
As an example of a binary search.492 Chapter 13 • NyquistRate AID Converters 13. 13.2 SUCCESSIVEAPPROXIMATION CONVERTERS Successiveapproximation AID converters are one of the most popular approaches for realizing AID converters due to their reasonably quick conversion time. if the first . knowledge of the search algorithm referred to as a "binary search" is helpful. Signed input Sample V i n. V D/ A = 0. "Is the number greater than 64?" If the answer is yes. yet moderate circuit complexity.4 Flow graph for the successiveapproximation approach. consider the game of guessing a random number from I to 128 where one can ask only questions that have a "yes/no" response. To understand the basic operation of successiveapproximation converters. = No b. = 0 No Fig. then the second question asks whether the number is greater than 32. . The first question might be. However. then the second question asks whether the number is greater than 96. answer is no.
. Successiveapproximation converters apply a binary search algorithm to determine the closest digital word to match an input signal. At the end of the conversion. followed by b. and so on until all N bits are determined. the D/A converter typically determines the accuracy and speed of the AID converter. is determined.4.2 Consider the case where Vee' = 8 V.5 1+. 13.13.L.1 (SAR) and control logic b..5. In general. The successiveapproximation register (SAR) and control logic are entirely digital and perform the necessary binary search.V ref OfA converterbased successiveapproximation converter. after possibly the reset period. 13.L. b. . a binary search divides the search space in two each time. Thus. and a 3bit conversion is performed. the next bit. the MSB. Specifically. In the second period. Vin = 2. in the first period.5 V LSB of the input signal. the signed output is in offsetbinary coding andthe input signal is assumed to be within ±O. Note that a sample and hold is required at the input so that the value to be converted does not change during the conversion time. Here. N + Bout '~ Fig.. EXAMPLE 13. a successiveapproximation converter requires N clock cycles to complete an Nbit conversion. the digital value in the SAR results in the voltage V D/A being within 0.5 Vee"~ The flow graph for a unipolar conversion is only slightly different and is left as an exercise for the reader. b" is determined. With this type of architecture. 13... Find intermediate D/A values and the final output.831 V. The third question divides the search space in two once again and the process is repeated until the random number is determined. in its most straightforward implementation. and the desired data can be found in N steps for a N set of organized data of size 2 . A flow graph for a signed conversion using a successiveapproximation approach is shown in Fig.2 SuccessiveApproximation Converters 493 >.. DACBosed Successive Approximation The block diagram for a unipolar successiveapproximation AID converter that uses a DAC is shown in Fig. Successiveapproximation register b D/A converter ~%...
13. This causes V" which was originally zero.n while the comparator is being reset to its threshold voltage through 52' In this step. is set toO. Since V. and the MSB capacitor is left connected to Vre. 1975]. If V. (This step is sometimes merged with the first bit time during bit cycling).5 VLSB because we have not accounted for the 0. In cycle 3: Bout = 011 so that VOlA = 3. V is always compared to ground. Although the final quantization error is 0. the comparator is taken out of reset by opening 52' and then all the capacitors are switched to ground. VLSB = 1. can be applied to the capacitor array during bit cycling.n is greater than Vre. the 16C capacitor in this example) is switched to Vre. with a smaller capacitor being switched each time. Since V. In cycle 2: Bout = 010 so that VO/A = 2. thereby holding the input signal.0 V. Finally.0 V.5 LSB offset as discussed at the beginning of this chapter.6.7 and operates as follows: 1.494 Chapter 13 • NyquistRate AID Converters Solution In this case. The unipolar case is shown in Fig. V. . This process is repeated N times. b. all the capacitors are charged to V.e. the largest capacitor (i. Unipolar ChargeRedistribution AID The straightforward approach of using a separate OfA converter and setting it equal to the input voltage (within one LSB) can be modified to the flow graph shown in Fig. Vin> on the capacitor array. is negative. With such a converter. V. it is greater than ±0. then V. OfA converter.n < VOlA' b. the error signal V equals the difference between the input signal.. is considered to be a 1. 5 t is switched so that V re. . Bit cycling: Next./ 2 ).n. now goes to (V.n + Vre.n<V o/A. One of the first switchedcapacitor analog systems using this approach is a chargeredistribution MOS AID converter [Mccreary. Otherwise./ 2. In cycle 1: Bout = 100 so that VOlA = 4. Sample mode: In the first step. 3.0 V . Also b. Hold mode: Next. Therefore.n > VOlA' b. Here. Since V.n> and the OfA output. the MSB capacitor is reconnected to ground and b t is taken to be O. which is 010. is set toO. until the conversion is finished. and the goal is to set this error difference with one LSB of zero.0 V. and the difference portion of the comparator are all combined into a single circuit. is set to I.. note that the capacitor array is performing the sampleandhold operation. as seen at the top of the flow graph. 2.831 VLSB. the sample and hold. VOlA' As a result. the resulting output is the last value of Bout. to change to V. 13.
I)C. 13. To get an exact division by two. it does attenuate the voltage VxA signed AID conversion can be realized by adding aV ref input. If Vx is less than zero at the first step. not to the comparator side.2 SuccessiveApproximation Converters 495 Signed input Sample V = Yin' = No i7i+1 No Fig. .Although parasitic capacitance at Vx does not cause any conversion errors with an ideal comparator. to minimize the parasitic capacitance at node Vx. if Vx is greater than zero. Also. use V ref and test for Vx greater than zero when deciding whether to leave the capacitors connected to V ref or not at each bit cycling. then proceed as in the unipolar case using Vref' Otherwise. note that an additional unit capacitor of size NC N C has been added so that the total capacitance is 2 rather than (2 .13.6 Flow graph for a modified successive approximation (divided remainder). the capacitor bottom plates should be connected to the Vref side.
13. Vin o? Vref Fig.7 A 5bit unipolar chargeredistribution AID converter.496 Chapter 13 • NyquistRate AID Converters 52 C + >4. Bit cycling S. SAR 53 1. Sample mode 5.: Vx = V In +2  v.. 2C~b.. . + S2 SAR 3.. Hold mode v. 52 16C~ 8C~ 4C~b.+ S3 2. c b.. C~b. b 2 >4+SAR = e = z = b z =.
b 1 is switched.984 V (13.3 Find intermediate node voltages at Vx during the operation of the 5bit chargeredistribution converter shown in Fig. b. all capacitors are switched and the charge on Vx is shared between the 32C total converter capacitance and the parasitic 8C capacitance.x 5 = 0. back to ground. . b.22) which is also less than zero. we have Vx 4 = 0.984 + 40 x 5 = 0. Vx = 0 during sample mode. is switched. 13.23 V and V. resulting in I V x = 0. so b. is left connected to Vref · Next.el. b. = 0. and Vx is set back to 0. Next. = O.984+x5V = 0. Finally. so b.484 + .484 V  (13. and we have 8 Vx = 0.ef = 5 V. Next. resulting in Vx = 0. and this switch is left connected to V.984 + . Therefore.13. Thus.23) which is also less than zero. is next switched.19) Since this result is greater than zero.234 + .n = 0. Assume a parasitic capacitance of 8 C exists on the node at Vx  Solution First. so b.7 when V.x 5 = 0.984 V by switching b.109 V 40 (13.234 V 2 40 (13. resulting in Vx = 0.016 V 16 40 (13. the output is given by Bout = 00111 and voltage Vx is within a V LSB of ground (V LSB = 5/32 V).016 V 40 (13. and switch b. b.2 SuccessiveApproximation Converters 497 EXAMPLE 13. = I. switch b 1 is reversed back to ground and Vx returns to 0. = I.18) During the first bit cycling. is switched.n = 1. b.x 5 V = 1.984 V.21) Since this result is less than zero. is switched. resulting in Vx 32 =  32 + 8 X V. When b. during hold mode.20) It is also greater than zero. = I.
Since the resistor string is monotonic. if V.n has been attenuated by a factor of two.. Once conversion is completed. to change to V. the sign of the input signal is determined by looking at the comparator output. which makes noise more of a problem for highresolution AIDs. some digital recoding may. 13. is larger than zero.e1/4 (which is a negative value). Starting with the largest capacitor. 13. the largest capacitor is now connected to V.V. except the largest one. All of the capacitors are connected to the bus having the lower voltage. is less than zero. any error in the MSB capacitor now causes both an offset and a signdependent gain error. when V. are charged to V in while the comparator is being reset to its threshold voltage.n is positive and b 1 is set to 1. 3. the comparator is first taken out of reset. Otherwise. Bit cycling: Next. are switched to ground. 2. Also. to become V. this type of converter is guaranteed monotonic if the capacitor array is monotonic. Specifically. At the end of this step. This causes V" which was originally zero. the switch is left as is and b. it is switched back and b.e. For the signed case. and then all the capacitors. is a 1.n is between ±V. V.e.n/2. a successiveapproximation conversion is performed to find the two adjacent resistor nodes that have voltages larger and smaller than V. similar to the hybrid OJA converter [Fotouhi. Referring to Fig. all the capacitors. ResistorCapacitor Hybrid A combination of the resistorstring and capacitorarray approaches in a hybrid AID converter. and assuming V. starting with b. the l6C capacitor in this example) is switched to ground if. the largest capacitor is switched to ground. starting with b. and only if.eI/2. except for the largest capacitor. is larger than zero (i. Hold mode: Next.n' One bus will be connected to one node while the other is connected to the other node..498 Chapter 13 • NyquistRate AID Canverters Signed ChargeRedistribution AID with a Single Reference Voltoge The same structure as the unipolar case can be used to realize a signed ND conversion while using only a single V. is shown in Fig. until conversion is completed. Next. a capacitor is switched to the adjacent resistorstring node having a larger voltage.el if a slightly modified switching arrangement is used. A successive approximation using the capacitorarray network is then done.9. The latter causes integral nonlinearity errors. then V. This approach for realizing signed AIDs has the disadvantage that V. b 1 is set to 0. causing V.eI/2. if V. and conversion proceeds as in the unipolar case..be required to obtain the desired output code. is a O.n while the comparator is being reset.. the conversion proceeds as follows: 1. 1979]. The first step is to charge all the capacitors to V. Sample mode: In the first step. If the comparator output is a l .8.n/2 . However. . and conversion proceeds as in the unipolar case.n is less than zero). the largest capacitor (i.
C_ T _+ 53 >+..n 16C e IIb 8C + 3./2 16C 5... Hold Mode . SAR ~ 1. .. 13. C + 53 >..2 SuccessiveApproximation Converters 499 5.. (Case where Vi' < 0) Fig. = V.. Bit cycling SAR I ~ ~++l 5. . SAR 2.8 A 5bit signed chargeredistribution AID converter..13.. C_ V V T b. Sample mode v.
and then storing the correction terms in a data register as DVej. ChargeRedistribution with Error Correction With the best matching accuracy of onchip elements being about 0. During a regular successive approximation operation. In this approach. for example. 13. 1984]. whenever a particular capacitor is used. 13.500 Vref Chapter 13 • NyquistRote AID Converters 2C C + Fig. Although this combination of an MSB capacitor array and an LSB resistor string is not inherently monotonic. its error is cancelled by adding the value stored in the data register to that stored in an accumulator register. the MSB array is realized using binaryweighted capacitors that determine. One errorcorrection technique that has been used to obtain 16bit linear converters is shown in Fig. starling with the largest capacitor. the first 10 bits.9 Resistoreapacitor hybrid AID converter.1 percent. Calibration is done by measuring the errors of each capacitor.10 [Lee. it can be easily autocalibrated at startup by adding a second resistor string referred to as a caldac. For a 16bit converter. calculating the correction terms required. one is limited to successiveapproximation converters having IObit accuracy specifications without some sort of calibration. which con . the final 6 bits are determined using an additional capacitor and a resistor string referred to as a subdac.
However.l2) + DoC. It is connected to ground and all of the other capacitors are connected to Vre. the resulting voltage. With the above switch operation.l 2. when DoC. As a result. C. varies from its ideal value.24) where DoC.10 A chargeredistribution AID converter with error correction. alone is switched to Vref.2 SuccessiveApproximation Converters 501 Comparator + ••• Accumulator register Successiveapproximation register register Data Subdac Control ••• Fig. can be written as C. equals zero.13. 13. (13. tains the sum of the correction terms for all of the other capacitors currently connected to V ref' No correction terms are measured for the resistor subdac. However. is switched to Vref. Here. 13. in practice C. its accuracy is not critical since it only determines the remaining LSBs. is not zero. while the comparator is reset. and thus.II(a) occurs after the switches are reversed. the remaining capacitance equals (C tota. A digital representation of Vel' defined as DVe" is obtained by doing a successive approximation using the caldac shown in . Vx ' is twice the error voltage. the ideal value of C. Defining C tota' to be the sum of all the capacitors in the array. is the capacitance error (either positive or negative). the simplified model shown in Fig. C.DoC./2) . to make the total capacitance correct. and C.. all of the other capacitors are switched to ground. The error terms are found starting with the MSB capacitor. " (C tota. Next. defined as Ve" that would be introduced during a normal successive approximation when C. Vx would remain zero if DoC. is Ctota. the comparator is taken out of reset mode.
the comparator is taken out of reset mode. To obtain the similar correction term for C" defined as OV e" the model in Fig. = (OVx'OV e]) 2 (13. _N' SN are connected to Vref' Next.11 Equivalent models for determining capacitance errors.. are left connected to ground. 13. 1 OV e. that even if equals zero.~ OVei) J= I (13. Note. Ib) During calibration for C.e.C. Specifically.e.C. the error voltage that would be due only to C. OVxi is found by connecting all capacitors smaller than C. 13.11(b) is used. = C = (2'] e. Mathematically. are switched to ground. and all larger capacitors to ground while the comparator is reset. zc. _ N. . since dCI is assumed to be part of C J • NB' Therefore.10 and then dividing the resulting digital value by 2 to obtain OVe. the measured value of Vx will be equivalent to OV el. . all capacitors smaller than C.NB C 3• NB = (4'] C e. = ~(OV xi . set to Vret and the others grounded). C i is switched to Vre/o and all capacitors larger than C. SN switches are all reversed (i. 10) During calibration for C.c. to V ret' and connecting C... switch grounded while the comparator is reset. C. (8) v. IO la . the b. and b. OVel' is stored in the data register for use during regular conversion. OV e. and the remaining switches b. Fig. (b) Fig. . This digital correction term. the b.: (C~la}e. but then subtracting off OVel using digital circuitry.26) and stored in the ith word of the data register. however. b. OVx' is then found using the caldac and successive approximation.25) A similar procedure is used for the other capacitors.: C. . Next. the switch procedure is to always leave the b. 13.O la C'. can be calculated by digitizing Vx' as before. Here. switch is grounded. is finally calculated using the formula ov.502 Chapter 13 • NyquistRate AID Converters v.
the individual time constant due to the capacitance 2C equals (R s l + R + Rs . Although this circuit is easily simulated using Spice to find its settling time. 1990]). Following such R" 2 N . otherwise. it should be mentioned that similar error correction techniques have also been described to account for capacitor inaccuracies (for example. 13. appropriate correction voltages are either added or subtracted using the caldac and C NS capacitor. 1991] can be used to obtain an estimate of the highfrequency time constant by summing individual time constants due to each capacitor. If the ith bit is determined to be a 0. R. Rs I ' and R S2 represent the switchon resistances of the bit line. as shown in Fig.13.L R 2 N 'c r 2C C R . To estimate this time. As in Section 12. DV ei is added to the digital accumulator that is driving the caldac.e. 13. normal successive approximation is performed using the subdac to determine the final LSBs. then the digital accumulator returns to its previous value. respectively.1. connected to Vrei)' In other words. Finally. Finally. [Tan. 5 I and 52 switches.. the opencircuit time constant approach [Sedra. when the ith bit is being tested.12 pling time. however. it maintains its new accumulated value. For example. Speed Estimate for ChargeRedistribution Converters The major limitation on speed with charge redistribution converters is often due to the RC time constants of the capacitor array and switches. Simplified model of a capacitor array during Ihe sam . normal successive approximation is performed with the MSB capacitor array.2 SuccessiveApproximation Converters 503 During a regular conversion.. With this approach...1C . it is useful to have a rough estimate of the charging time to speed up the design process.12. a digital addition must be performed during each bit cycle. The proper correction voltage is determined through the use of a digital accumulator that stores the sum of all digital errors of those MSB capacitors deemed to be a I (i. Here. R R Fig. )2C . consider the simplified model of a capacitor array being reset. and a small amount of digital RAM is required (10 bytes in the case of a lObit MSB array).
RatioIndependent Algorithmic Converter The block diagram for an algorithmic converter is shown in Fig.15. The operation of the multiplybytwo gain amp is shown in Fig.. So while (13.12 is equal to Teq = (Rs! + R + R. 13. we need e . the size of the switches going to the larger capacitors may be increased to reduce their on resistance).Th eq <~ 1 2 where T is the charging time.13. an algorithmic converter doubles the error voltage while leaving the reference voltage unchanged. 13. Fortunately.12. 1977. the opencircuit time constant for the circuit shown in Fig. This converter requires a small amount of analog circuitry because it repeatedly uses the same circuitry to perform its conversion cyclically in time. Li. . both charges are recombined into the first capacitor which is then connected between the opamp input and output.3 ALGORITHMIC (OR CYCuq AID CONVERTER An algorithmic converter operates in much the same way as a successiveapproximation converter.)2 C N For better than 0. Finally.69(N+I)T eq (13. 1984]. 13.5L5B accuracy. Although this gainamp circuitry is shown using singleended circuits for simplicity. it is possible to realize the gain amp so that it does not rely on any capacitor matching if four clock cycles are taken for the multiplybytwo operation. although this result is not the same for all chargeredistribution AID converters (for example. During the second sampling. the final design should be simulated using accurate transistor models.504 Chapter 13 • NyquistRate AID Converters an approach.29) gives results about 30 percent higher than those obtained by simulating the actual RC network shown in Fig. The flow graph for a signed algoritJunic conversion is shown in Fig. After the second sampling. the basic approach can be modified for most chargeredistribution AID converters.29) It has been observed that (13. the charge from the first capacitor is stored on a second capacitor whose size is unimportant. The basic idea of this gain amp is to sample the input signal twice using the same capacitor. fully differential circuits are normally used. This equation can be simplified to T>Teq(N+I) In(2) = 0.14 [McCharles. whereas a successiveapproximation converter halves the reference voltage in each cycle. However. 13.29) can be used to roughly determine the maximum sampling rate. One of the difficulties in realizing a highprecision algorithmic converter is building an accurate multiplybytwo gain amp. 13. 13.
13.~ S/H Cmp >1. Oul Vin 00 . V.+1 Shift register X2 Gain amp S/H Fig.13. 1 No V>O i ? i+ 1 No i> N Fig.3 Algorithmic (or Cyclic) AID Converter 505 Signed input Sample V .14 Algorithmic converter. 13.13 Flow groph for the olgorithmic opprooch..n' i .. ..
Combine Q . I + C2 v. Cmp V out = 2 Verr 4. C><l10 + C. Q. again. on C2 . 13.. Fig.506 Chapter 13 • NyquistRate AID Converters C. Transfer charge Q . Sample remainder and cancel inputoffset voltage. Cmp 1. to output. '' 2.15 Multiplybytwo gain circuitry for an algorithmic converter that does not depend on capacitor matching. C. ~t:2~~ e V" ocp l C. after storing charge Q . Q. from C. I Cmp Q2 '' 3. . to C2 . I Q. and Q 2 on C " and connect C. Sample input signal with C.
15. 1987. resulting in Vco ~ Voft and its change in charge being (13.Q C1 ~ CI(VWVoft(Voft» ~ CIVe" All this charge is placed on C" resulting in (13. 1987. is discharged to the same value it had in phase 1. we have VCI ~ 0 .4 Consider the multiplybytwo gain circuitry shown in Fig.33) VC' ~ OV O ~ Voft ft At the end of phase two. Voft 13.13. Finally. find the values of Vc p VCl' and Vout at the end of each of the phases shown. Halla. C" and the offset value. VCI ~ Ve" .31) (13. Vcz remains unchanged since one side of it has been opened.37) and the output voltage being the desired result of Vout ~ 2 Vew Note that this final result is independent of the sizes of C I.Voft (13.4 FlASH (OR PARALLEL) CONVERTERS Flash converters are the standard approach for realizing veryhighspeed converters.32) (13. as seen in some recent publications [Peetz.Voft ~ Voft impl ying that its charge change was L\.Voft and Vout ~ Voff as in phase one.4 Flash (or Parallel) Converters 507 EXAMPLE 13. resulting in Vout = Voff (13. Also.)V e w At the end of phase three.30) and the voltages across the two capacitors are Vel = VerrV off (13. Yoshii. at the end of phase four. Vout is connected to the negative opamp input. Solution During phase one. 1986.34) (13. Assuming the opamp has an input offset designated as Voft. and . the opamp output. 13. C.36) All of this charge is placed back on C I ' resulting in VCI ~ 2 Vw .35) and Vou' ~ (C1/C.
as shown in Fig.16. which typically take up a large area and are very power hungryespecially when they are Vref  R 2 Vin Over range R V'7 R V'6 R v: (2 N 1) to N R V" encoder N digital outputs R R V'3 V'2 R V" R/2 Comparators Fig. Flash AIDs are fast but they require a large number of comparators.and will have a 0 output. Note that the top and bottom resistors in the resistor string have been chosen to create the 0. resulting in simpler encoding.5 LSB offset in an AID converter. 1991].16 A 3·bit flash AID converter. Any comparator connected to a resistor string node where Vri is larger than Vin will have a I output while those connected to nodes with Vri less than Vin will have 0 outputs. 13. The NAND gate that has a 0 input connected to its inverting input and a I input connected to its non inverting input detects the transition of the comparator outputs from Is to Os. 13. which occurs during a bubble error (see the next subsection) and. perhaps. Each comparator is also connected to a different node of a resistor string. lt also allows for error detection by checking for more than one 0 output.508 Chapter 13 • NyquistRote AID Converters . Gendai. All other NANDgate outputs will be I. The input signal in a flash converter is fed to 2 N comparators in parallel. error correction. Such an output code word is commonly referred to as a thermometer code since it looks quite similar to the mercury bar in a thermometer. .
the difference between Vri and V.n' Since the inverter's input was at its bistable point. the inverter operates as a single stage opamp with only one pole (no nondominant poles). the inverter is free to fall either high or low depending on its input voltage. the other side of C is pulled to the input voltage. however. At the same time. the inverter is set to its bistable operating point. When <I> is high. Vi". clocked fast. where its input voltage equals its output voltage (i. in the case of a single CMOS inverter. However.17 [Dingwall. it should be mentioned that this simple comparator suffers from poor power supply rejection. the other side of C is charged to V d .n will determine which direction the inverter's output will fall.. Since the inverter side of the capacitor is floating. its threshold voltage). 13. Such a large capacitive load often limits the speed of the flash converter and usually requires a strong and powerhungry buffer to drive Vin . ResistorString Bowing The input currents of bipolar comparators cause errors in the voltages of the nodes of the resistor string. C must keep its original charge. Using fully differential inverters helps alleviate this shortcoming. These errors usually necessitate the bias current in the resistor string being two orders of magnitude greater than the input . With this inverter set to its threshold voltage. Input Capacitive Loading The large number of comparators connected to Vin results in a large parasitic load at the node Vin. One way to realize a small clocked CMOS comparator is by using a CMOS inverter. which is often a critical design specification in fast converters. a ring oscillator is formed. so stability is guaranteed.17 A clacked CMOS comparator. 1979]. Issues in Designing Flash AID Converters We discuss here some important design issues that should be addressed when building highspeed flash AID converters.4 Resistor string Flash (or Parallel) Converters 509 C CMOS inverter Latch To decoding logic Fig. We shall see that this large capacitive loading can be reduced by going to an interpolating architecture. and therefore the inverter's input will change by the voltage difference between V ri and v. as shown in Fig. Normally with an odd number of inverters.13.13. When <I> goes low.e.
This powersupply noise can easily couple through the circuitry or substrate. If this signal is being encoded by an 8bit AID converter with Vret = 2 V (i. To minimize this problem. Also. then it would only take 5 ps to change through I LSB.n should be routed together with the delays matched [Gendai. the differential internal nodes might be shorted together temporarily just after latch time. . on an integrated circuit having a clock signal in the tens of MHz. the converter will have more than I LSB error. analog power supplies should be separated from digital power supplies including having analog power to the comparator preamps while using digital power to the latch stages. Bubble Error Removal The outputs of the comparators should be a thermometer code with a single transition. highspeed sampleandhold circuits can be more difficult to realize than the flash converter itself. noise. Substrate and PowerSupply Noise For V ref = 2 V and an 8bit converter. This time can be minimized by keeping the time constants of the internal nodes of the latch as small as possible. If there is clock skew between comparators greater than this. only 7. Comparator LatchtoTrack Delay Another consideration that is often overlooked is the time it takes a comparator latch to come from latch mode to track mode when a small input signal of the opposite polarity from the previous period is present. Signal and/or Clock Delay Even very small differences in the arrival of clock or input signals at the different comparators can cause errors. It should also be noted that the delay differences may not be caused just by routing differences. This time is roughly about the same time it takes a signal to propagate 500 urn in metal interconnect. resulting in errors.e. the clocks must be shielded from the substrate and from analog circuitry. It is also necessary to make sure the powersupply bypassing circuitry doesn't form a resonant circuit with the bonding wiresinclude small resistors in series with the bypass capacitors. the clock and V. One means of easing this problem is to precede the converter by a sampleandhold circuit. Also. In some cases. To see this. This signal has a maximum slope of 1570 V/lts at the zero crossing. or by phase differences between the comparator preamplifiers at high frequencies. consider a 250MHz. sometimes a lone I will occur within the string of Os (or a 0 within the string of Is) due to comparator metastability. This is sometimes achieved by keeping the gain of the latches small.. these errors are greatest at the center node of the resistor string and thus considerable improvement can be obtained by using additional circuitry to force the center tap voltage to be correct. it is difficult to keep powersupply noise below a few tenths of a volt. perhaps only two to four.510 Chapter 13 • NyquistRate AID Converters currents of the comparators. Onchip powersupply bypassing is a necessity. the sinusoid covers the whole range). but could also be caused by different capacitive loads. Typically. However. In addition. However. However. IV peakinput sinusoid.8 mV of noise injection would cause a I LSB error. running differential clocks closely together will help prevent the signals being coupled into the substrate or through the air. 1991].
An alternate approach to reduce the effect of distant bubble errors is to create two encoders (one AND type and one OR type) rather than a single encoder [Ito. Another digital approach for reducing the effect of bubble errors is to allow bubble errors in the lower 2 LSBs but have the remaining MSBs determined by looking for transitions between every fourth comparator [Gendai. These bubbles usually occur near the transition point of the thermometer code. An alternate method to remove bubble errors that does not increase the power dissipation is shown in Fig. which may cause a large decoding error. the final output is taken as the average of the two encoder outputs. Here. 13.18 [Steyaert. 1992]. (2N_l) to N encoder N digital outputs Fig. as shown as shown in Fig. these bubbles can usually be removed with little extra complexity by replacing the twoinput NAND gates shown in Fig. this same voting scheme can be implemented entirely in digital form. etc. this circuit will not eliminate the problem of a stray 0 being two places away from the transition point. 13. 1994]. the power dissipation is not increased because the added transistors make use of existing current in the slave latch. 13. the errors in two different encoders tend to be equal in magnitude but opposite in sign. there must now be two Is immediately above a 0 in determining the transition point in the thermometer code. 1993].18 Using threeinput NAND gates to remove single bubble errors. When an unexpected output pattern occurs at the NAND outputs. 13. In this case. These extra transistors make the value stored in a slave latch not just a function of its master latch. 1991]. limited bandwidth. the values from the adjacent master latches overrule the center master latch. Thus. which is performed by adding the two outputs and dropping the LSB (to divide by two). which are driven by the comparator master latches [van Valburg. If a bubble occurs. With this approach. bubble errors that occur within four places of the transition point do not cause any large errors. but different from the center master latch. the outputs from the two adjacent master latches are the same. . However. but also a function of the two adjgcent master latches. extra transistors have been added to the inputs of the slave latches.13. Alternatively.19. With this modification. Note that with this approach. Fortunately.16 with threeinput NAND gates.4 Flash (or ParallelJ Converters 511 cross talk.
..To it 1...19 Bubbleerror voting circuit that does not increase the power dissipation.512 Chapter 13 • NyquistRate AID Converters ... this will cause major errors due to the unmatched impedances at the comparator inputs (one input goes to the resistor Vref Continuoustime preamp ..To i+1..i=r 1. / Track and latch Fig. Flashback is caused by latched comparators.._ .... . Flashback An additional source of error is flashback... comparator comparator comparator comparator o Q DO Comparator master latch To i1 comparator From i1 comparator Slave latch From i1 comparator To i1 comparator Fig_ 13... which are almost always used....From. .. or viceversa.. When clocked comparators are switched from track to latch mode...... there is major charge glitch at the inputs to the latch.. . If there is no preamplifier. _ y... 13.20 Clocked compo rotor with 0 preamplifier to reduce f1oshbock..From 1'...1.
13. a lowgain preamp. Notice that it has a buffer. most modern comparators have one or two stages of continuoustime buffering and/or preamplification. Specifically. and unless these are matched to the routing of the clock signals. b..21 An Bbit twostep AID converter. although their throughput approaches that of flash converters. To determine the remaining LSBs. the quantization error is found by reconverting the 4bit digital signal to an analog value using the 4bit 01A and subtracting that v. these different delays may not be tolerable.5 TwoStep AID Converters 513 stringthe other to the input signal). a commonly used comparator is shown in Fig.. 13.. b.n reaching the various comparators. The block diagram for a twostep converter is shown in Fig.. Also notice that in the positive feedback latch the feedback is taken from the emitterfoIlower outputs. b. twostep converters do have a larger latency delay.5 TWOSTEP AID CONVERTERS Twostep (or subranging) converters are currently the most popular approach for highspeed mediumaccuracy AID converters. Another technique sometimes used to minimize the effects of flashback is to match the input impedances as much as is possible. have less capacitive loading. For example. and the voltages the comparators need to resolve are less stringent Than for flash equivalents." now being connected to it.21.. and another buffer before the trackandlatch circuitry. twostep converters require less silicon area. 13. . The operation of this twostep converter is as foIlows. Unfortunately.20. dissipate less power. with the nodes of the comparators that were originaIly connected to V. The 4bit MSB AID determines the first four MSBs. 4bit D/A Gain amp 4bit LSB AID First 4 bits (b. which minimizes the capacitances of the internal nodes of the latch. 13. it does result in different delays for V. b a) Fig. b. To minimize this effect. b.. it is possible to implement a second matched resistor string. For example. However.) Lower 4 bits (b. 13.n' This approach matches impedances and also minimizes the resistorstring bowing due to the comparator input currents. and the end nodes of the string connected together to V. This popularity is due to several advantages they have over their flash counterparts. Vin 4bit MSB AID V.
Defining V LSB = V.22.514 Chapter 13 • NyquistRate AID Converters value from the input signal. only 32 comparators are required for a twostep AID converter.e1/28 (i. always relative to 8bit accuracy). Digital Error Correction The block diagram for a twostep converter with digital error correction is shown in Fig. we have for an 8tH 2 1.. the first S/H I is critical and its performance often limits the overall linearity. However. 4bit DtA (Bbit accurate) (Sbit accurate) S bits (Bbit accurate) 4bit M8B AID '. its purpose is to allow the first S/H I to sample a new input signal before the gain amplifier has finished settling. 13. To see how this correction works and why a secondstage 5bit converter is needed (rather than 4bit). However. 13.22 An 8bit twostep AID converter with digital error correction. To ease the requirements in the circuitry for finding the remaining LSBs.1 8tH._. with error correction. The reason for digital error correction is to significantly ease the requirements placed on the 4bit MSB AID converter. consider the quantization error that occurs in an ideal converter. . digital error correction is commonly used and is discussed next. and the LSBs are determined using the 4bit LSB AID. (Bbit accurate) 8tH 3 (4bit accurate) Digital delay Error correction 4 bits ~ r''. Although the second sample and hold (S/H 2 ) is not necessary. rather than requiring 256 comparators as in an 8bit flash converter. Sbi! L8B AID (Sbit accurate) B bits Fig.e. this first ND converter needs to be at least 8bit accurate. this straightforward approacb would require all components to be at least 8bit accurate.. Gain amPr_. However. To significantly ease the accuracy requirements of the 4bit MSB AID converter.. Without error correction. the requirements on this MSB AID converter are that it need only be 4bit accurate. With this approach. the quantization error is first multiplied by 16 using the gain amplifier.
. to determine V. EXAMPLE 13. Thus. and the subtraction circuit. accurate (to 0. we find V.39) In other words..40) Thus in the ideal case.38) However. For a more detailed treatment of a twostep NO converter. a 5bit LSB converter must be used. where I I VLsa<V <V L a 2 q 2 s ( 13. from the relation V. Finally.5 V in the case ..5 For the twostep 8bit AID converter shown in Fig. otherwise Vq may go out of range. Therefore. Vi' is found by properly combining the digital equivalents of V I and In summary. the reader is referred to aIDbit 75 MHz implementation (with integrated S/H). . However. what is the maximum voltage range at Vq when the converter's fullscale input is ±2. for the non ideal case where the 4bit MSB flash converter has an absolute accuracy of 8V Ls a.22. for a nonideal 8bit converter with an absolute accuracy of 0. Besides the difficulty in realizing the SIH circuits. the quantization error. 1990J. Vq.5 LSB accuracy at the 8bit level are SlHs I and 2. the value of Vq can be determined (to 8bit accuracy) using a 4bit AID converter since Vq must be within 16V Ls a. in the case of a nonideal 4bit MSB converter. we have (keeping the 8bit definition of Vi salV.5 LSB at the 5bit level) gain amplifier." we see that the digital value of Vq has been found to within O. 13. we have (13.+V q where 8VLsa<Vq<8VLsa (13.41) Specifically.etBout = V. the maximum quantization signal is now twice that of the ideal case. In fact. described in [Petschacher. the MSB NO need only be accurate to 1/24 = 1116. Similarly. is now bounded within 32V Ls a.1 3.VI = v.5 LSB. another major limitation is the difficulty of designing a highspeed. for an ideal 4bit NO converter. due to difficulties in realizing highspeed circuits with gain.5 TwoStep AID Converters 515 ideal 8bit converter. The only components that need 0.5Vrss and the digital value of V I is known to the same accuracy since we assumed the 0/A converter to be 8bit accurate (and the digital word applied to the O/A converter is known). v. the O/A. often fewer bits are determined in the first stage of a twostep converter to reduce the amplification required. Note that the gain amplifier of 8 is used to amplify the quantization error back to maximum signal levels to ease the requirements of the 5bit LSB converter. (13.
Note that the input range of the LSB converter is 8 x 332 mV = 2.6 INTERPOLATING AID CONVERTERS Interpolating converters make use of input amplifiers.516 Chapter 13 • NyquistRote AID Converters where the 4bit MSB AID converter is (a) 8bit accurate and (b) 4bit accurate? Assume all other components are ideal. Solution With a fullscale peaktopeak input voltage of 5 V applied to an 8bit AID converter. VI and V2 . These input amplifiers behave as linear amplifiers near their threshold voltages but are allowed to saturate once their differential inputs become moderately large.7 V (a little more than half of the input range of the overall converter).5 mV 2 5 (13. After the gain of 8.9 V (the same as the input range of the overall converter). the interpolating architecture has also been used quite successfully by itself [Goodenough. van Valburg.5 volts). here the latch threshold is near the midpoint of the two logic levels (or about 2. the interpolated signals need only cross the latch threshold at the correct points. As can be seen in the figure. 618 mV.24. 312 mV. 1993]. we have VLSB = . (b) In the case of a 4bit accurate MSB converter. As a result. then Vq becomes bounded between ±8. While this approach is often combined with a "folding" architecture [van de Grift. To further understand this interpolation approach. more reference levels have been created between VI and V. Also. 1989.5V LSB (i. so more gain could be used in this case. as well as their interpolated values are shown in Fig. It should be noted here that for good linearity. 13. with the input comparators having a maximum gain of about 10. Vq is bounded between ±16V LSB' implying that the maximum range of Vq is 32 VLSB.40) the maximum voltage range of Vq is 16VLSB' or equivalently. 1992]. we have from (13.8 = 19. Also. 13. the latch for VI is first triggered. followed by V2. 332 mY. or equivalently. 13.. As Vin increases. and so on until V2 • As a result. One way to create such correct crossing . the maximum range of Vq would now be 17VLSB • or equivalently. the number of input amplifiers attached to Yin is significantly reduced by interpolating between adjacent outputs of these amplifiers.42) For an ideal 4bit AID converter.5V LSB ' In other words. the input range of the LSB converter becomes 8 x 618 mV = 4. Steyaert. the logic levels are assumed to be zero and five volts. 8bit accurate)..23. 1987. noncritical latches need only determine the sign of the amplifier outputs since the differences between the input signal and threshold voltages have been amplified. while the rest of the interpolated signals responses are of secondary importance. some possible signals for the inputamplifier outputs. (a) If we go to the trouble to make the 4bit AID converter have an absolute accuracy of 0. as shown in Fig.e.
75 1. V 1 and V 2/ and their interpolated signals. b.0 (Volts) Fig.75 V + R R R V. V 2C' V 2 (Votts) Latch threshold o o 0.13. V 2 b. .24 Possible transfer responses for the inputcomparator output signals.136 Vre f V in = Interpoloting AID Converters 517 1 V V4 + R R R R V3 R 0.25 0. Digital logic R b.25 V R ~ + Input amplifiers Fig. b3 b4 R R V" V 2b V" 0. R R R R R R 0.5 V in 0. 13. V 1J V 2 a .5 V + R R V.23 A 4bit interpolating AID converter (interpoloting factor of 4).
two stages of interpolation using capacitors to interpolate resulted in a lObit 20MHz AID lowpower converter [Kusumoto. 1993]. What reduction in input capacitance of the converter would be expected over a traditional flash architecture? Solution If interpolating by three.5 V R R R R R/4 R/4 + V. resulting in a lDOMHz 8bit AID converter realized with a t. and a lower number of accurate reference voltages that need to be created. I. 1988]. As mentioned earlier. assuming the inputamplifier outputs are low impedance [van de Plassche. are linear between their own thresholds. 0. I'b such that . For fast operation. 13. it is desired to create two new currents. as shown in Fig. show how one can interpolate two current outputs.25 < Vin < 0. 13.518 Chapter 13 • NyquistRote AID Converters V in V. current mirrors were used to interpolate eight times between comparators.6 Using current mirrors. Vin • Such a reduction results in a lower input capacitance (which is quite high for a flash converter). In Fig. 1993]. the main benefit of an interpolating architecture is the reduction in the number of differential pairs attached to the input signal.24. 13. 0.. These series resistors equalize the impedances seen by each latch comparator looking back into the resistive string. Finally.. Since the latch comparators have similar input capacitances associated with them. EXAMPLE 13.25 Adding series resistors to equalize delay times to the latch comparators. a slightly reduced power dissipation. it should be mentioned that circuit techniques other than resistive strings can be used to realize this interpolative approach. 1I and I" by three. it is important that the delays to each of the latches are made to equal each other as much as possible. this linear region corresponds to 0.sum CMOS process.5. points is to ensure that VI and V.25. In another implementation. the delays can be made nearly equal by adding extra series resistors. In [Steyaert.25 V R R + Fig.
However. Thus. whereas a twostep converter requires an accurate D/A converter.7 FOLDING AID CONVERTERS We just saw that the number of input amplifiers can be reduced through the use of an N interpolating architecture.27. As an example. " 9 I" " 12b " I. the number of latch comparators remains at 2 for an Nbit converter. However. The MSB converter determines whether the input signal. The operation of this converter is as follows.13. These four currents can be converted back to voltages to send to the latches. this converter would require onethird the number of input amplifiers in relation to a traditional flash converter.e. 1/2 and 3/4. we see that the folding rate here is four.7 Folding AID Converters 519 I.n is swept over its input range. A folding NO converter is similar in operation to a twostep (or subranging) converter in that a group of LSBs are found separately from a group of MSBs. Since we are interpolating by three here.44) These output currents can be realized as shown in Fig. the input capacitance for this interpolated approach would be onethird of that for a flash. these bits are usually . 13. I 3 2 3 2 3 I 3 (13. between a and 1/4. a folding converter determines the LSB set more directly through the use of analog preprocessing while the MSB set is determined at the same time.. Alternatively.43) (13. the currents can be directly sent to latches which make use of current inputs. I'b = II + I.26. 13. 1/4 and 1/2. 13. " 9 (Relative width sizing shown) (All lengths same) Fig. V.n' is in one of four voltage regions (i. This large number of latch comparators can be significantly reduced through the use of z folding architecture. 13. This folding rate determines how many bits are required in the MSB converter. =II+I. Defining the folding rate to be the number of output transitions for a single folding block as V. Although the MSB converter is shown separately. or 3/4 and I).26 interpolating by three between two current outputs. consider the 4bit folding converter shown in Fig.
..!. Illl. 0001.. [The MSB converter would usually be realized by combining some folding block signals. that the four LSB latches are also used for different MSB regions and the thermometer code is inverted when V. as V. folding reduces the number of latch comparators needed as compared to a flash converter.MSBAID converter V re f = 1 V b.. 16 latches would be required whereas only eight are needed in the 4bit folding example of Fig. 0000.n continues to increase to 1/2. HLatch f B:.27 A 4bit folding AID converter with a folding rate of four. 13.!. V I to V4 produce a thermometer code for each of the four MSB regions. HLatch Folding block . For example. = {1:. Folding block responses I Folding block V. 16 ~ 16 16 11 16 15 16 r p_ ~ b b b b 10 14} 16' 16' 16' 16 16 10 16 14 16 v: Threshold ~ V. the thermometer code changes as 0000. however. Folding HLatch block f lh8Th:ffi~O 3. b..b1 V . in a flash 4bit converter.~ ~ 13 v. 1000. In summary. However..16' 16' 16' 16 +V _ V. Specifically. 13.0 ~~.n is between either 1/4 and 1/2 or 3/4 and I. as V. Olll.. ~:} V. 1100. 3 7 V _ {~ L 22 15} .520 Chapter 13 • NyquistRate AID Converters 2bit .27. For example. To determine the 2 LSBs. 0011.b b b b f "08 . Folding HLatch block . Note.{. four . the code changes as 1110.~ ~ 16 _ 16' 16' 16' 13} • v: 16 16 16 16 Fig.b b b b f Digital logic f< f< b. Also. note that latch comparators can be used for the LSB set since the transitions are amplified by the folding blocks..1 determined by combining appropriate signals within the folding blocks. V..n increases from a to 1/4.
remains low whenever Yin is less than Vr3 or greater than V r4 . (0) A possible single<>nded circuit realization. goes high when Vin is between V'3 and V'4' Such behaviors for v. otherwise. the savings can be greater (see Problem 13.28(b). Some points worth mentioning here are that for fullscale input signals. note that v. The output signal VO U! is related to the voltages Va and Vb in an "or" type fashion. The folding blocks can be realized using crosscoupled differential pairs. 13.21).7 Folding AID Converters 521 (a) v.13.as shown. However. 13. Here. 13.28 A folding block with a folding·rote of four. latches are used for the MSB converter and the other four are shown explicitly. In fact. Va remains low whenever Vin is greater than V'2 or less than Vr l • Also.: lL. V'3 (b) v~ Fig. and v«. the frequency of the folding block's output signal is equal to the multiplication of the frequency of the input signal times the folding rate. VO U ! is high. and Vb give rise to the folding output for Vout. as seen in the simplified bipolar circuit shown in Fig. (b) inputoutput response. With regard to the behavior of v. This multiplying effect limits . In other words. In general. the cross coupling of adjacent differential pairs causes Va to go high when Vin is between V" and V'2' while v.++'Lj+"_v in v. four sets of differentialpair transistors are connected in such a way as to realize the input output response shown in Fig. the output signal from a folding block is at a much higher frequency than the input signal.28. Vout is low only if both Va and Vb are low.
) :U :th~e~~ld 13 9 16 16 10 16 14 16 13} 16' 16' 16' 16 A 4bit folding AID converter with a folding rate of four and on interpolotebytwo. Folding block f& & & & HLatch lR 3V] Digital logic ~ b ~ 88Th~e:~ld 3 16 7 16 11 16 15 16 V. Foldingblock responses V re f = 1 V  1 V.0 4 8 12 1 D. not cross coupled. With an interpolatebytwo ~ 2bit MSBAID converter b. and differential circuits are almost always used in practical implementations. folding converters also make use of an interpolating architecture. flash converters have similar input stages of differential pairs of transistors for each comparator. In fact. v~'lCX: 1 16 5 16 some foldingblock signals." .29 {2. but they are. it can be N shown that the number of transistors driven by the input signal equals 2 the same number as for a flash converter. a large input capacitance similar to that for a flash converter is also present with the folding circuit shown. 13. V.Fig. and the input signal goes to one side of each differential pair. To reduce this large input capacitance. Folding fblock V _ .522 Chapter 13 • NyquistRate AID Converters the practical folding rate used in highspeed converters. V.~ ~eshold 16 16 __ 16 (Volts) V. f R >OR Vm o_~~V. (The MSB converter would usually be realized by combining . ~ ~ AAAA io YLatch fV. = {371115} 16' 16' 16' 16 V3 HLatch fR _tA8_:h~e~~ld 2 16 V3  6 16 L. b. Another point to note here is that while the folding approach reduces the number of latch comparators. of course. it should be mentioned that the circuit shown is a singleended version. Since the number of differential pairs in each folding block equals the folding rate. Latch (VOltsl. V. Also.
since the final bit .8 x 2 mm' active area.27. the first stage finds the mostsignificant bit. 13.e. Other examples of folding converters are given in [van de Grift. 13. The MSBs were realized by taking appropriate outputs from selected differential pairs and summing them separately to realize additional folding amplifiers with reduced folding rates. Unfortunately. EXAMPLE 13. Thus.19. Note that a new inverted signal V4 is required to connect the top folding block to the bottom one.8 bits effective resolution. the resulting architecture would be that shown in Fig. 13. 1992]. show how the two MSBs can be derived using internal signals from the folding blocks.8 Wand requiring only 1. and so on. 13. b. can be used directly as the second bit. Each adjacent folding block was offset by 1/32 V.30. the M SB is easily obtained by using the collector current of the transistor connected to Vz in the top folding block. where each stage finds a single bit. Looking at Fig. As a result. folding converters have been used in the internal operation of a twostep converter [Vorenkamp. which are needed to determine the second bit. a straightforward implementation of this approach would be too slow. producing V]. no extra circuitry is required in a differential version since it can be accomplished by simply crosscoupling the differential output wires. zero crossings every 11256 V were obtained (i. as shown in Fig. (8/16) Vref in the top folding block. Similarly. the top two bits. Although the creation of this inverted signal is needed in a singleended version. 1987. giving zero crossings at each 1/32 V. b.8 Pipelined AID Converters 523 technique applied to the 4bit example. the signal V. b 2 .8 PIPELINED AID CONVERTERS The twostage architecture described in Section 13. can be determined using the top folding block. In addition. as seen in Fig. Specifically.. b I and b 2 . four folding blocks each with a folding rate of eight were used. b 2 • In fact. 1992].7 In Fig. in order to realize a veryhighspeed 8bit converter. 13.13. Solution The MSB. 1993]. and Colleran..5 can be generalized to multiple stages. then the difference between reference voltages of adjacent inputs of a folding block was 1/8 V. 13. 13.29. while dissipating only 0. is determined by the input signal being above or below Vref/2.27. as shown in Fig. the top folding block uses references 4/16 and 12/16. the second stage finds the next bit. The converter also included circuitry to prevent bubble errors. By interpolating between each adjacent folding block using four 8tap resistor strings. b. Assuming V ref = IV. we see that the input is compared to the appropriate signal. The final AID converter could be clocked at 650 MHz and could resolve a 150MHz sinusoid with 7. In [van Valburg. an 8bit converter with 32 latch comparators connected to the interpolating resistor strings).27.
but the complexity is only proportional to N. R. The block diagram of a DAPRX is shown in Fig... if desired..32. 13. 8 16 16 16 V" o+'>. In some pipelined implementations.. each DAPRX contains an SIH to store the input signaL This SIH allows the preceding DAPRX to be immediately used to process its next input signal before the succeeding DAPRX has finished. 13. and Bout = O.  . then V out = 2 Vrel/2. it does not sit idle while the remaining lower bits are found. 1981]. and Bout = I. Also. a new sample can be entered in the pipeline each clock cycle. Although it takes N clock cycles to process each input signal (i. 13.l Fig.. but immediately starts work on the next input sample. the processing rate is one sample/cycle.+.. Thus. For a multibit per stage pipelined converter.n > 0. The major limitation on the accuracy in pipelined convert v.. 13. In this case. digital error correction can be added similar to that for a twostage AID converter.33. v. Specifically. Otherwise. the input voltage is compared to 0 V. +_.e. as long as the preceding DAPRX's digital output is also stored.30 Using the V 1 folding black to also determine the top two MSBs. A better approach is to also incorporate pipelining such that once the first stage completes its work.. Each digital approximator (DAPRX) performs the basic operation required in the algorithmic algorithm.524 Chapter 13 • NyquistRate AID Converters R. A block diagram of a pipelined AID converter is shown in Fig. L... the DAPRX can be realized as shown in Fig. the latency is N). = b.n + V rel/2.31 [Martin. Q.. It should be mentioned here that the S/H can be incorporated into the gain of two amplifiers. would not be available until residual errors ripple through the entire converter. more than one bit is converted per stage. V out = 2 V. b.__ V. This makes pipelined AID converters a good choice where small area is important. Vb Q. which is less than other architectures also processing one sample/cycle. If V. for a signed conversion.
8 Pipelined AID Converters 525 b. Some examples of pipelined NO converters are given in [Martin..31 A pipelined AID converter. bi S/H I_~ Cmp V ref/ 4 0<:>. D. The SIH is also a critical component. 13. Lin.13. where accuracy requirements are most stringent.digital approximator) Fig. e. Vref/4 Fig.32 A Ibit digitol opproximotor (DAPRXI. ' I • • • 0. For this reason. '" ~ ( D N2 D N2 '" '" ~ z I i • i • • 0. Current state of the art is 12 to 15 bits for pipelined converters with error correction at I to 2 MHz. Also. 13. D. 1988. 1993]. ers is the gain amplifier. Song. presently most pipelined AID converters are switchedcapacitor implementations. r I ON DN $ t °Nl I °N_l b. and Karanicolas. . The speed is expected to go up substantially in the near future.• I 1bit DAPRX 0. I I 0. the gain is often taken smaller for the first stages (perhaps even equal to unity). which makes the realization of a highspeed gain amplifier considerably easier. 1981. 1bit DAPRX '~y ~) Analog pipeline (DAPRX ..I. 1991. especially for multibit implementations. t 1bit DAPRX t 1bit DAPRX t r. Sutarja. • . especially in the first few stages. D. 1988.
1980]. 13. .34. Gll to Gl4 are delayed with respect to each other by the period of Glo ' such that each converter will 8/H $2 Nbi! ND $0 8/H $3 Nbi! ND Digital Yin output 8/H 8/H Nbit ND 8/H Nbit ND Fig.34 A fourchannel timeinterleaved AID converter. 13.9 TIMEINTERLEAVED AID CONVERTERS Veryhighspeed AID conversions can be realized by operating many AIDs in parallel [Black.526 Chapter 13 • NyquistRate AID Converters 8/H Vi kbit ND k bits Fig. 13. 13.33 A multibit digital approximator (DAPRX). The system architecture for a fourchannel AID is shown in Fig. Here. Glo is a clock at four times the rate of Gll to Gl4' Additionally.
It is also essential that the channels are extremely well matched. pp. Gray. Castello. Gray. Fotouhi and D. February 1991." IEEE J. pp. 19. 6869. of SolidState Circuits. 100 mY. Vol. and R. 14. Y. W. Lee. "Interpolators Put IObit 75MHz AID Converters on 8bit Digital Process." IEEE J. and D. and K.1989. ofSolidState Circuits. HS. Prentice Hall. A. R. pp." IEEE J. pp. "A lOb 20MHz 30mW Pipelined Interpolating CMOS ADC. SolidState Circuits Conf. 10221029. and A. 100101. lOOMs/s Pipelined AID Converter. December 1979. Lin. SolidState Circuits Conf. "A SelfCalibrating I5bit CMOS AID Converter. Kim. consider a de input signal in a fourchannel timeinterleaved converter where one converter has a de offset of. pp. pp. pp. P. H. M. December 14. A. C. Ito et al. pp. "TimeInterleaved Converter Arrays. Vol. Kawata." IEEE Int. "A lOb 20MsJs 3VSupply CMOS AID Converter for Integration Into System VLSIs. February 1994. Englewood Cliffs. H. V in' sampled at the rate of <\>0' In this way. San Francisco. S. G. Karanicolas.10 References 527 get successive samples of the input signal. Jr. R. San Francisco. 2930." IEEE Int. T. such as GaAs. Li. W. AnalogDigital Conversion Handbook. Y. SolidState Circuits Conf. pp. Hodges. SolidState Circuits Conf. 813~819.13. Gendai. San Francisco. An example of a I GHz 6bit AID converter using time interleaving and GaAs S/H circuits is described in [Poulton. Hirase. M. Phan. . YoM." IEEE 1. . Vol." IEEE Int. 15. For example. sometimes the input S/H is realized in a different technology. A. and P. San Francisco. Colleran. Thus. Vol. A. 926931. Black. afSolidState Circuits. December 1979. SolidState Circuits Conf." IEEE J. Gray. Vol. K. 14. while the remaining S/H circuits could be realized in silicon. the input S/H making use of <\>0 is critical. pp. Such nonideal behavior can be disastrous for many applications since the tone may reside well within the frequency of interest. New Jersey. 172173. 6263. "A 15b IMs/s Digitally SelfCalibrated Pipeline ADe. 13. "A tob. 6061. A. T. 920925. R. 1986. "A 13b 2. as mismatches will produce tones at Is/m when there are m channels. J. D. February 1993.5MHz SelfCalibrated Pipelined AID Converter in 3 11m CMOS. N. W." IEEE J. December 1991. L. Dingwall. Such a system will produce every fourth digital word different from the other three and hence a tone at I s/4. 26. pp. Hotta et aL "A 12mW 6b Video Frequency ADe. the four AID converters operate at onequarter the rate of the input sampling frequency." Electronic Design. Bacrania. say. Goodenough. 828836." IEEE Int. M." IEEE Int. Lee. San Francisco. of SolidState Circuits. B. 4849. F. where four bipolar converters operating at 250 MHz were used. Kusumoto et al. 628636. February 1987. Hodges.10 REFERENCES Analog Devices. With this approach. Abidi. of SolidState Circuits. Vol. B. "HighResolution AID Conversion in MOSILSI. "Monolithic Expandable 6bit 20MHz CMOS/80S NO Converter. SolidState Circuits Conf." IEEE Tnt. Chin. Hodges. "A RatioIndependent Algorithmic AnalogToDigital Conversion Technique.. pp. "An 8b SODMHz ADC. Komatsu. 1987]. New York. while the remaining four S/H converters can have considerable jitter since the signal is already sampled at that point. F. and M. and P. February 1993. December 1984. 19. December 1984. pp. P. December 1980. of SolidState Circuits. February 1993. A.
should be chosen such that the opamp output never exceeds 10 volts when a v < Vin < 10 V? 13. Philadelphia. 2 L pp. A..3 Derive the equivalent of (13. J. of SolidState Circuits. J.128.. "A HighSpeed." IEEE J. December 1975. 22.1. I. December 1988." IEEE J. December 1988. W. McCreary ct al. S. W. 962970. and J. pp. and a clock frequency of I MHz is used.. 25. where V. Vol. Black. February 1977. of SolidState Circuits." IEEE 1. February 1987. pp. van Val burg and R. 944953. "A Pipelined 13bit. Salcrore. of SolidState Circuits. Hamilton. 371379. Vol.1 when the opamp has an inputoffset voltage of VOff l and the comparator has an inputoffset voltage of Voff 2 · . pp. "An 8bit Video ADC Incorporating Folding and Interpolation Techniques. van de Plassche and P. R. van der Veen. December 1987. Part J. Operation without a Sample and Hold." IEEE 1. "A 12bit lMsample/s Capacitor ErrorAveraging Pipe lined AID Converter. 23. R. Craninckx. pp. Hodges. pp. B. pp. and K." IEEE J. M. and T..528 Chapter 13 • NyquistRote AID Converters K. 13. 9971002. and J. A. 13161323." IEEE J. November 1981. Baltus. 5V AnalogtoDigital Converter. Vol. New York.8) for Fig. A. 1991. of SolidState Circuits. "AllMOS Charge Redistribution AID Conversion Technique SolidState Circuits." IEEE Int.11 PROBLEMS 13. Vol. pp. S.." IEEE J. December 1988. pp. C. 3rd ed. C. of SolidState Circuits. R. as shown in Fig. HighAccuracy Pipelined AJO Converter. V. and D. J. Petschacher et al. H. J. = 100 pF. December 1987.I333. Gray. Roovers. SolidState Circuits Conf. December 1990. Corcoran. Microelectronic Circuits." IEEE J. pp. L.1.2 Consider an 18bit integrating AID converter. December 1990. "Error Correction Techniques for HighPerformance Differential AID Converters." IEEE J. Tan er al. SolidState Circuits Conf. San Francisco. R. P. Kang. "A 100MHz 8bit CMOS Interpolating AID Converter. (~f SolidState Circuits. J. 10. 13391346. "An 8b 650MHz Folding ADC. "A IGHz 6bit ADC System. F." IEEE 15th Asilomar Con! on Circuits. 28. pp. 13341344. SolidState Circuits Conf. of B.1 What is the worstcase conversion time for an 18bit dualslope integrating AID converter when the clock rate is 5 MHz? 13. pp. Vol. Vol. McCharies.el equals 10 volts. J. Saunders College Publishing/HRW. E.1. M. Smith. Vol. May 1993. Sedra and K. "A 10h 75MSPS Suhranging AID Converter with Integrated Sample and Hold. Martin. Y."IEEE Int. of SolidState Circuits. of SolidState Circuits. KS. and M. pp. San Diego. 9697. "A lOb 50MS/s Pipelined ADC. Poulton. Tornpsett. Peetz. Verdaasdonk. 23." IEEE Custom Integrated Circuits Conf. "An Algorithmic AnalogToDigital Converter. K. Vol. Sutarja and P. R. R. "An 8b 350MHz Flash ADc'''IEEE lilt. and Computers. R. "An 8bit 250 Megasample Per Second AnalogToDigital Converter. J. Song. 3233. 22." IEEE J. P. of SolidState Circuits. Vol. Vorenkamp. Rutten. February 1992. M. Systems. Yoshii et al. "An 8bit lOGMHz FullNyquist AnalogtoDigital Convener. 16621666. Lakshmikumar. J. D. van de Plassche.4. 13. 13181326. December 1986. W. 23. Jr. Hornak. 27. New Jersey. C. What value of R. 250ks/s. van de Grift. Steyaert. 25. 1324. 13. BS. Vol. and J. M. December 1992.
. as shown in Fig. what is the attenuation of an input signal at 60 Hz ? Repeat Problem 13.13.18.16 Show that the circuit shown in Fig. that occurs when using the MSBI capacitor during a normal conversion equals 0. Repeat Problem 13.13 13. 13. assuming that a parasitic capacitance of 8 C is connected between the node at Vx and ground. Find the sequence of the voltage level for V x if the input signal is 3. Find the sequence of the D/A converter's output levels for an input of 3. Is the final digital result affected? Show a method for modifying the unipolar chargeredistribution AID converter shown in Fig.2 when the integrating opamp has an inputoffset voltage of 20 mY? What inputsignal frequencies are completely attenuated by a dualslope 16bit integrating AID having a clock frequency of I MHz? For this same converter.5V LSB are correctly realized.11 13. where V. Ve2. the MSB (i.11 (b) if the MSB. 13.5 (Vx2 . Draw a block diagram similar to that for Fig.7.22 for a IObit twostep AID converter where the first stage determines 4 bits. 13. b 1 ) capacitor equals 31..I (i.25 results in all time constants being equal when each of the latches has the same input capacitance and the amplifiers have zero output impedance. and there is a parasitic capacitance to ground of 10 pF on node Vx? For the same circuit.8. 13.7 100 kHz.5 with the converter's clock frequency being equal to 13. where ~nCox = 2 ~pCox = 100 ~A/V2 .5 pF. Indicate the accuracy needed in all the blocks.5 What is the offset error (in LSBs) of the converter described in Problem 13.11 (a) if the total array capacitance equals 64 pF.1 1 Problems 529 13. 13.4 13.9 13. what value of error voltage Vx2 would be measured in Fig.e. What is the final digital.10 13. show that the error voltage.5. 13.333 volts.8 converted tQ a 2's complement code? What value of error voltage Vxl would be measured in Fig.6 13. How is the digital code obtained from the signed charge redistribution AID converter shown in Fig. estimate the settling time needed for a 12bit chargeredistribution AID converter where the total array capacitance equals 128 pF.17 Consider the clocked comparator shown in Fig.8 13. Vel' that occurs when using the MSB capacitor during a normal conversion equals 0.5 Vxl ' For the same circuit as described in Problem 13.e.4 pF? Show that the error voltage.333 volts when V re.12 13. = 8 Y.7 such that the threshold offsets of 0.Vel)' Assuming switch resistances are all about I kQ. 13. output? Consider a 4bit unipolar chargeredistribution AID converter. 13.e' = 8 Y. 13. Consider a 4bit unipolar DACbased successiveapproximation AID converter. as shown in Fig. b 2) capacitor equals 16.14 13. 13.12. 13.15 13.
6.21 13. but instead allow the input signal to be applied to the array of comparators.19 13. In fact.34. what reduction of input capacitance over a flash converter would be achieved with an 8bit folding/ interpolating AID converter having four folding blocks. In an Nbit folding AID converter (with n£ interpolation). what is' the product of the folding rate times the number of folding blocks? Find an expression for the number of latches in an Nbit folding AID conF verter where the folding rate is FR = 2 . .530 Chapter 13 • NyquistRate AID Converters IV"I = IV. 2 What is the minimum region of VU that V1 and V should be linear over? i Many veryhighspeed AID converters do not use a sample and hold since it would limit their speed. it w