This action might not be possible to undo. Are you sure you want to continue?
Los Angeles
Comparison of Digital Offset
Compensation in Comparators
A thesis submitted in partial satisfaction
of the requirements for the degree Master of Science
in Electrical Engineering
by
Koon Lun Jackie Wong
2002
ii
The thesis of Koon Lun Jackie Wong is approved.
________________________________
Behzad Razavi
________________________________
Ingrid Verbauwhede
________________________________
C.K. Ken Yang, Committee Chair
University of California, Los Angeles
2002
iii
Table of Contents
COMPARISON OF DIGITAL OFFSET COMPENSATION IN COMPARATORS1
CHAPTER 1 INTRODUCTION..................................................................................... 1
1.1 GENERAL PURPOSES OF COMPARATORS..................................................................... 1
1.2 REQUIREMENTS ON COMPARATORS............................................................................ 1
1.3 INTRODUCTION TO OFFSET COMPENSATION............................................................... 6
CHAPTER 2 CORE COMPARATOR DESIGN........................................................... 9
2.1 ACCURACY............................................................................................................... 10
2.1.1 Device Mismatch in Differential Pair .............................................................. 10
2.1.2 Total Input Referred Offset of Comparator...................................................... 12
2.2 SUPPLY SENSITIVITY................................................................................................ 24
2.2.1 Supply Sensitivity due to each transistor.......................................................... 24
2.2.2 Overall Supply Sensitivity of Core Comparator .............................................. 26
2.3 SPEED....................................................................................................................... 27
2.3.1 Evaluation Phase.............................................................................................. 27
2.3.2 Reset Phase ...................................................................................................... 34
2.4 INPUT CAPACITANCE................................................................................................ 40
2.5 POWER CONSUMPTION ............................................................................................. 41
2.6 DESIGN OF NEXT STAGE (SR LATCH)....................................................................... 41
CHAPTER 3 DIGITAL OFFSET COMPENSATION............................................... 43
3.1 FOUR DIFFERENT ARCHITECTURES .......................................................................... 44
3.1.1 Architecture Comp1 ......................................................................................... 44
3.1.2 Architecture Comp2 ......................................................................................... 45
3.1.3 Architecture Comp3 ......................................................................................... 46
3.1.4 Architecture Comp4 ......................................................................................... 47
3.2 CHARACTERISTICS OF DIGITAL OFFSET COMPENSATION.......................................... 48
3.2.1 Offset Magnitude of Digital Compensation ..................................................... 48
3.2.2 Linearity of Digital Offset Compensation........................................................ 52
3.2.3 WorstCase Overall Offset after compensation ............................................... 55
3.3 SUPPLY SENSITIVITY................................................................................................ 56
3.4 SPEED....................................................................................................................... 59
3.4.1 Comparison on Speed of Different Architectures ............................................ 60
3.4.2 Speed Penalty of Digital Offset Compensation................................................ 63
3.4.3 Comparison on Linear and Nonlinear scaling ............................................... 65
3.5 INPUT CAPACITANCE................................................................................................ 67
3.6 POWER CONSUMPTION ............................................................................................. 67
3.6.1 Power of Comparators..................................................................................... 67
3.6.2 Power of Clocking............................................................................................ 70
iv
3.6.3 Total Power...................................................................................................... 71
3.7 QUICK SUMMARY OF COMPARISON.......................................................................... 73
CHAPTER 4 CIRCUIT PERFORMANCE ................................................................. 74
4.1 ACCURACY............................................................................................................... 74
4.1.1 Measured Internal Offset Due to Device Mismatches ..................................... 74
4.1.2 Measured Digital Offset Compensation........................................................... 77
4.1.3 Linearity ........................................................................................................... 82
4.1.4 Worstcase Overall Offset ................................................................................ 85
CHAPTER 5 APPLICATIONS OF COMPARATORS.............................................. 89
5.1 APPLICATION OF COMPARATORS ON MULTIPHASE FLASH ADC .............................. 89
CHAPTER 6 CONCLUSION........................................................................................ 93
v
List of Figures
Figure 1 Ideal input/output characteristic of a comparator ................................................. 2
Figure 2 Positive feedback realization ................................................................................ 2
Figure 3 Block diagram of flash ADC architecture ............................................................ 4
Figure 4 Schematic of (a) an amplifier (b) a comparator.................................................... 5
Figure 5 A comparator with analog offset compensation ................................................... 6
Figure 6 Timing Diagrams of φ
1
, φ
2
, φ
3
, V
X
, and V
Y
............................................................ 7
Figure 7 Core Comparator................................................................................................. 10
Figure 8 Model of Device Mismatch in Differential Pair ................................................. 12
Figure 9 Core comparator model for offset calculations................................................... 12
Figure 10 Current factor mismatch of M
1
......................................................................... 14
Figure 11 common mode analyses of M
1,2
........................................................................ 15
Figure 12 Threshold mismatch of M
3
............................................................................... 17
Figure 13 common mode analyses for M
3
........................................................................ 18
Figure 14 Current factor mismatch of M
3
......................................................................... 20
Figure 15 Input referred offset voltage due to each transistor .......................................... 23
Figure 16 Supply Sensitivity on Offset due to ∆β
1
, ∆β
2
, and ∆V
th2
.................................. 25
Figure 17 Overall Supply Sensitivity on Offset ................................................................ 27
Figure 18 Reset Response of sim2, sim3, sim10, and sim11............................................ 38
Figure 19 Simplified SR Latch.......................................................................................... 42
Figure 20 Schematic of Comp1......................................................................................... 44
Figure 21 Schematic of Comp2......................................................................................... 45
Figure 22 Schematic of Comp3......................................................................................... 46
Figure 23 Schematic of Comp4......................................................................................... 47
Figure 24 Digital Offset of Comp1 ................................................................................... 50
Figure 25 Digital Offset of Comp2 ................................................................................... 50
Figure 26 Digital Offset of Comp3 ................................................................................... 51
Figure 27 Digital Offset of Comp4 ................................................................................... 51
Figure 28 Digital Offset DNL of Comp1.......................................................................... 53
Figure 29 Digital Offset DNL of Comp2.......................................................................... 53
Figure 30 Digital Offset DNL of Comp3.......................................................................... 54
Figure 31 Digital Offset DNL of Comp4.......................................................................... 54
Figure 32 Worstcase overall offset .................................................................................. 56
Figure 33 Supply Sensitivity on Offset of Comp1............................................................ 57
Figure 34 Supply Sensitivity on Offset of Comp2............................................................ 57
Figure 35 Supply Sensitivity on Offset of Comp3............................................................ 57
Figure 36 Supply Sensitivity on Offset of Comp4............................................................ 58
Figure 37 Illustration of input transconductance loss ....................................................... 63
Figure 38 Schematic of Comp1 with 3bit linear scaling.................................................. 65
Figure 39 Power Consumptions with Digital Offset Compensation Off .......................... 69
Figure 40 Power Consumptions with Digital Offset Compensation On........................... 69
vi
Figure 41 Total Power Consumption with Digital Compensation Off ............................. 71
Figure 42 Total Power Consumption with Digital Compensation On.............................. 72
Figure 43 Measured Internal Offset of Comp1................................................................. 75
Figure 44 Measured Internal Offset of Comp2................................................................. 75
Figure 45 Measured Internal Offset of Comp3................................................................. 76
Figure 46 Measured Internal Offset of Comp4................................................................. 76
Figure 47 Measured Digital Offset of Comp1 .................................................................. 79
Figure 48 Measured Digital Offset of Comp2 .................................................................. 79
Figure 49 Measured Digital Offset of Comp3 .................................................................. 80
Figure 50 Measured Digital Offset of Comp4 .................................................................. 80
Figure 51 Measured DNL of Comp1 ................................................................................ 83
Figure 52 Measured DNL of Comp2 ................................................................................ 83
Figure 53 Measured DNL of Comp3 ................................................................................ 84
Figure 54 Measured DNL of Comp4 ................................................................................ 84
Figure 55 Measured Offset of Comp1 after Digital Compensation.................................. 86
Figure 56 Measured Offset of Comp2 after Digital Compensation.................................. 86
Figure 57 Measured Offset of Comp3 after Digital Compensation.................................. 87
Figure 58 Measured Offset of Comp4 after Digital Compensation.................................. 87
Figure 59 Comparison on worstcase offset...................................................................... 88
Figure 60 Block Diagram of Multiphase Flash ADC ....................................................... 89
Figure 61 Speed of 6bit pphase Flash ADC................................................................... 92
List of Tables
Table 1 Simulation results on evaluation with varying comparator transistor size .......... 33
Table 2 Simulation results on reset device........................................................................ 37
Table 3 Evaluation and Reset with vary Vcm (see Table 1,Table 2 for term definition) . 39
Table 4 Power Consumption of Core Comparator............................................................ 41
Table 5 Worstcase Supply Sensitivity of Comp1 − Comp4 ............................................ 59
Table 6 Speed Comparisons with Digital Offset Compensation Off ................................ 60
Table 7 Speed Comparisons with Digital Offset Compensation On................................. 61
Table 8 Maximum Sampling rate of different architecture............................................... 62
Table 9 Speed Comparisons on linear and nonlinear scaling of Comp1 ......................... 65
Table 10 Power of Clocking.............................................................................................. 70
Table 11 Performances Rating of Comparators ................................................................ 73
vii
ABSTRACT OF THE THESIS
Comparison of Digital Offset
Compensation in Comparators
by
Koon Lun Jackie Wong
Master of Science in Electrical Engineering
University of California, Los Angeles, 2002
Professor C.K. Ken Yang, Chair
Digital offset compensation is an efficient technique for designing high speed, high
accuracy, low input capacitance, and low power comparators. Low input capacitance and
low power allow higher order of parallelism, while digital offset compensation allows
high accuracy. A 4bit digital offset compensation can reduce 140mV input referred
offset due to device mismatches to 13mV. For comparison, four different architectures of
digital offset compensation are fabricated in 0.18µm 1.8V CMOS technology, and a set
of performance metrics for a comparator is developed to compare the tradeoffs between
these four architectures.
1
Comparison of Digital Offset Compensation in
Comparators
Chapter 1 Introduction
1.1 General Purposes of Comparators
Modern integrated circuits (IC) design almost always involves strong well defined
digital signals; however, incoming data is often analog signals or corrupted digital signals,
which are caused by limited bandwidth of transmission line, noise coupling, capacitive
and inductive effects from the printed circuit board (PCB), chip package, wire bond, etc.
In order to convert the weak corrupted signals to full swing digital signals, a comparison
with a fixed reference value is performed. A comparator outputs a digital 0 if the signal is
below the reference or a digital 1 if the signal is above the reference.
Comparators are commonly found in modern IC design. Since most IC designs
are synchronous system, comparators are usually triggered by clock. Clocked
comparators are commonly found in AnalogtoDigital Converter (ADC) and based band
receivers. Moreover, since comparators have large voltage gain, they are often used as
sense amplifiers in SRAM and DRAM. Sometimes, in high performance circuits,
comparators are used as a storage element, for instance a latch.
1.2 Requirements on Comparators
In applications like flash ADC and oversampled receiver, a comparator requires
high gain, high sampling rate, high accuracy, low power consumption, and low input
2
capacitance. In addition, comparators are required to be triggered by clock, if the systems
are synchronous. The requirements of comparators are discussed one by one below.
Figure 1 Ideal input/output characteristic of a comparator
The first requirement of a comparator is having high gain. An ideal comparator
has input/output characteristic as shown in Figure 1. In real implementation, high gain
amplifier is used to approximate this input/output characteristic. To achieve virtually
infinite gain, positive feedback is often employed in comparator design. A simple
realization of positive feedback system could be two backtoback inverters, as shown in
Figure 2. The output (V
1
– V
2
) of this circuit increases exponentially with time. This will
be discussed in detail in Chapter 2.
Figure 2 Positive feedback realization
The second requirement of a comparator is having high sampling rate. As
synchronous system is running faster and faster, we require clocked comparator to run at
a higher sampling rate as well. A common clocked architecture that can achieve high
sampling rate has two phases of operation: evaluation phase and reset phase. In
V
in1
−V
in2
V
out
V
in1
V
in2
V
out
V
1
V
2
3
evaluation phase, positive feedback is enabled to achieve high gain. In reset phase,
positive feedback is disabled and the comparator clears its previous sample. For fast
operation, reset must be completed quickly and the positive feedback should be enabled
quickly and have short regeneration time constant.
The third requirement of a comparator is having high accuracy, for example ½
LSB of an ADC or minimum signal magnitude of a receiver. Errors that cause inaccuracy
usually are offsets, noise, and residual value from prior comparison. Offsets are often the
largest errors in comparator design. Offsets can be classified into systematic and random
offsets. Systematic offsets can be minimized by symmetric design and careful layout.
Random offsets are caused by device mismatches in layout, and the variance of mismatch
is inversely proportional to the area of devices size (W×L) [1]. Thus, to reduce random
offsets, we should make devices bigger. However, as modern CMOS technology scales
down for higher switching speeds and higher transistor density, offset requirements
become more and more difficult to fulfill. The second error that causes inaccuracy is
noise. Noise includes thermal noise, flicker noise, supply noise, and sampling noise.
Thermal noise is white Gaussian noise from resistors and transistors. Flicker noise is
often referred to 1/f noise of a transistor. Supply noise does not affect the output directly,
because comparator is a fully differential circuit. However, due to large device
mismatches, supply noise may momentarily change the input referred offset, and thus
degrade the accuracy. Sampling noise is caused by the fast transition of clock from reset
phase to evaluation phase. Fortunately, sampling noise is often negligible even with
4
sampling rates of several GSamples/s
1
. The third error that causes inaccuracy is the
residual value from prior comparison. During reset phase, the comparator clears the
previous data. However, if the reset is not completed before the next evaluation phase
comes, small residual charge on output will get amplified exponentially because of
positive feedback. The imbalanced output thus creates input referred offset, degrading the
comparator accuracy. Since the residual charge depends on the previous sample, this
error is sometimes called InterSymbol Interference (ISI).
Figure 3 Block diagram of flash ADC architecture
The forth requirement of a comparator is having low power consumption. The
power consumption of a comparator must be low because frequently a large number of
1
Analysis of sampling noise is not part of this research.
V
FS
•
•
COMP
COMP
COMP
COMP
V
in
clk
2
N
D
E
C
O
D
E
R
N
Digital Output
5
comparators operating in parallel are used in a flash ADC architecture or in an over
sampled receiver. A block diagram of a simple flash ADC is shown in Figure 3. The
basic concept of a flash ADC is to use 2
N
comparators to compare the input signal with
reference voltages that are generated by dividing the full scale voltage V
FS
by 2
N
resistors.
Decoder then converts the comparators output to binary code. Hence a Nbit flash ADC
requires 2
N
comparators. As a result, the power consumption of a flash ADC doubles as
the number of bits of resolution increases by one.
Figure 4 Schematic of (a) an amplifier (b) a comparator
The last requirement of a comparator is having low input capacitance since low
input capacitance limits the input bandwidth. Similar to power consumption, total input
capacitance of a Nbit flash ADC is simply 2
N
× input capacitance of a comparator. For a
typical amplifier (Figure 4a) and a typical comparator (Figure 4b), input capacitance is
directly proportional to the size of input devices M
1,2
. In favor of input capacitance, we
should use small input devices M
1,2
. However, in favor of offset, we should use big input
M
1
M
2
M
4
V
DD
V
b
V
in1
V
in2
M
3
V
out1
V
out2
M
1
M
2
M
4
V
DD
V
in1
V
in2
V
out1
V
out2
M
3
Rst
M
5
(a) (b)
6
devices. This contradiction leads to direct tradeoffs between accuracy and input
bandwidth. Therefore, offset compensation is introduced to reduce input referred offset
while keeping input devices small.
1.3 Introduction to Offset Compensation
The ultimate goal of offset compensation in comparators is to reduce the input
referred offset. Offset compensation can be done in analog method or in digital method.
Figure 5 A comparator with analog offset compensation
Traditionally, analog offset compensation is used, and it utilizes capacitors to
store offsets. Figure 5 shows an example of comparator with analog offset compensation
[2]. The comparator has regenerative amplifier M
1
– M
4
, reset S
5
– S
7
, and sampling
network S
1
– S
4
and C
1
,C
2
. shows the timing diagram of φ
1
, φ
2
, φ
3
, and V
X
, V
Y
.
M
3
M
1
M
2
M
4
S
7
S
6
S
5
C
2
C
1
S
2
S
4
S
1
S
3
φ
3
V
DD
φ
1
φ
1
φ
2
φ
2
φ
1
φ
1
+
V
out
−
V
out
+
V
in
+
V
ref
−
V
in
−
V
ref
Q P
X Y
7
Figure 6 Timing Diagrams of φ
1
, φ
2
, φ
3
, V
X
, and V
Y
The operation of this comparator is the following: 1) The comparator is in reset phase, φ
1
= H, φ
2
= L, φ
3
= H, S
3
– S
7
are on. Nodes P and Q are charged to +V
ref
and –V
ref
respectively, and the offset of the comparator is stored in C
1
and C
2
. 2) At t
1
, φ
1
switches
to low, S
3
– S
6
turn off, so reset ends. 3) At t
2
, φ
2
switches to high, S
1
and S
2
turn on to
track the inputs. 4) At t
3
, φ
3
switches to low, S
7
turns off, and regeneration starts. In this
example, we decouple the relationship between input capacitance and offsets. During
tracking mode in step 3, inputs see C
1,2
in series with gates of M
1,2
, which results a
capacitance as small as gate capacitance of M
1,2
. Meanwhile, offset of the comparator is
given in [2]:
1
2
1
;
7
7 1
−
= ∆ + =
R g
R g
A V
A
V
V
mP
mN
d
d
OS
OS
,where V
OS1
is the inputreferred offset without
offset compensation, A
d
is the differential voltage gain form the gates of M
1
and M
2
to
their drains, and ∆V is the offset due to charge injection mismatch between S
5
and S
6
. g
mN
and g
mP
are the NMOS and PMOS transconductance respectively, and R
7
is the small
signal onresistance of S
7
. One potential problem for this architecture is that it may
t
1
t
2
t
3
time
φ
1
φ
2
φ
3
V
X
, V
Y
8
require large C
1,2
to reduce the charge injection mismatch between S
5
and S
6
. Large C
1
and C
2
increase the settling time during reset and thus slow down the operating frequency.
Generally analog offset compensation requires a capacitor to store the offset in every
cycle, so the comparator is in closed loop in around half a cycle. The maximum speed of
a comparator is eventually limited by the closed loop response. This restriction is much
more relaxed in digital offset compensation.
In digital offset compensation, offsets of a comparator can be tuned by changing
the digital inputs. Offsets are then stored in static memory when the system is initialized.
Hence, the comparator can remain in open loop most of the time, and thus its inherent
maximum speed can possibly be achieved.
This project focuses on digital offset compensation techniques and how they
affect the other requirements of gain, sampling rate, etc. Four different digital offset
compensation architectures are compared. Chapter 2 begins by discussing the design
issues of a core comparator. This core comparator will also be the baseline to which each
of compensation technique is compared for the penalty of inserting digital compensation.
Comparisons on digital offset compensation in chapter 3 will be based on performance
parameters and terminology presented in chapter 2. A test chip is fabricated in 0.18um
CMOS technology, and measured results will be given in chapter 4. Applications of
comparators will be discussed in chapter 5.
9
Chapter 2 Core Comparator Design
This project starts with a basic design of comparators. While there are many
architectures, we chose the comparator as shown in Figure 7 for its power efficiency [3].
This comparator has two operation modes, evaluation phase and reset phase. In
evaluation phase, clk is logical high. Current source M
clk
turns on, and the input devices
M
1,2
sense the differential input. The differential current of M
1,2
imbalances the backto
back inverters, which form a positive feedback system. The imbalance charge on V
out1
,
V
out2
is then regenerated to full swing. In reset phase, M
clk
turns off and all RST
16
turn on.
The reset devices RST
16
eliminate all imbalance charge, so the previous data is cleared.
At this time, the comparator goes back to initial state and is ready to amplify the signal
when evaluation phase comes again.
Four digital offset compensation techniques are explored based on the same basic
comparator structure. Then we can examine not only tradeoffs among different
compensation architectures but also tradeoffs between with and without digital offset
compensation. For each compensation architecture, we base our comparison on the same
set of performance metric: accuracy, supply sensitivity, speed, input capacitance, and
power. This chapter looks at each of these metrics for the core comparator. A brief
discussion on SR latch, which receives the output of comparator and provides constant
logical output over one cycle, will be given at the end of this chapter.
10
Figure 7 Core Comparator
2.1 Accuracy
A very important requirement of a comparator is small input referred offset
voltage. Any input offset voltage in comparator will directly add on the signal; as a result,
the accuracy of the comparator will be decreased. Offsets can be systematic or random.
Systematic offset can be minimized by differentially symmetric design and careful layout.
Random offset arises if there are device mismatches. In this section, we will describe the
model for device mismatch in differential pair and total input referred offset of the
comparator.
2.1.1 Device Mismatch in Differential Pair
Matching properties of CMOS transistor are categorized into threshold mismatch,
RST
2
4
2
M
5
4
2
V
DD
RST
1
4
2
RST
5
4
2
RST
6
4
2
M
6
4
2
M
3
4
2
M
4
4
2
RST
4
4
2
RST
3
4
2
M
1
8
2
M
2
8
2
M
clk
16
2
V
out1
V
out2
V
in1
V
in2
clk
clk
clk
clk
invbot
1
invbot
2
11
∆V
th
, and current factor mismatch, ∆β, according to [1]. The magnitude of these two
quantities can be approximated for a give gate oxide thickness and transistor size. For
instance, in 0.18µm technology, oxide thickness is around 4nm. In our comparator design,
drawn size of input transistor is W/L = 8λ/2λ = 0.96µm/0.24µm. Note that effective
channel length for the drawn length of 0.24µm is 0.18µm. The standard deviation of the
random mismatches can be approximated by [1],
eff
Vth
th
WL
A
V
2
2
) ( = σ
eff
WL
A
2
2
2
) (
β
β
β σ
= ,
where σ(V
th
) and σ(β) are standard deviation of ∆V
th
and ∆β respectively, A
Vth
2
and A
β
2
are area proportionality constant which could be found from a lookup graph for a given
oxide thickness. It is found that A
Vth
= 4mVµm, A
β
= 1%µm, σ(V
th
) = 9.62mV and
σ(β)
β
= 2.41%. Adapting to this methodology and assuming worstcase conditions, we will
model the threshold mismatch as an ideal voltage source on transistor gate with
magnitude ∆V
th
= 6σ(V
th
), and current factor mismatch as error in channel width,
∆W
W
=
6
σ(β)
β
. This simple model is illustrated in Figure 8.
12
Figure 8 Model of Device Mismatch in Differential Pair
2.1.2 Total Input Referred Offset of Comparator
With a mismatch model for a differential pair, we can replace all pairs in our core
comparator with this model to find the total input referred offset. In order to obtain the
worstcase offset, the placements of the voltage sources and scaled transistors are
specially chosen. As shown in Figure 8, transistors labeled with “OS” are replaced by the
mismatch model. For clarity, all reset devices RST
16
are not shown.
Figure 9 Core comparator model for offset calculations
The mismatches of three differential pairs contribute offset of the comparator. In
this section, I will discuss the affects of each offset source carefully, and simulation
W−∆W
L
W
L
+ −
∆V
th
V
in1
V
in2
V
DD
M
1
(OS)
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
(OS)
W
36
L
M
4
W
36
L
invbot
1
invbot
2
M
5
W
36
L
(OS)M
6
W
36
L
V
out1
V
out2
V
in1
V
in2
clk
13
results are presented at the end of this section to confirm the theoretical results.
Offset due to threshold mismatch of M
1
, ∆V
th1
:
∆V
th1
is modeled as a voltage source on the gate of transistor M
1
. Since M
1
is the
input device of the comparator, the input referred offset voltage due to threshold
mismatch of M
1
is just ∆V
th1
itself. This magnitude is always constant under any bias
conditions.
Offset due to current factor mismatch of M
1
, ∆β
1
:
∆β
1
is modeled as a channel width mismatch ∆W, i.e.
∆β
β
=
∆W
W
To calculate the
input referred offset due to ∆W, I will calculate the differential current that ∆W generates,
as illustrated in Figure 10a, and then compare the current with that of generated by
equivalent ideal voltage source at the input, as shown in Figure 10b.
14
Figure 10 Current factor mismatch of M
1
Before analyzing two configurations, it is important to know that transistors M
1,2
are in
saturation because in the beginning of evaluation mode node invbot1, invbot2 are
precharged to V
DD
. However, Mclk is in triode region because V
gs,Mclk
= V
DD
, V
ds,Mclk
=
V
cm
− V
gs1,2
, which could be quite low. Analyzing Figure 10a, we could find:
2
1 1
2
1 1
2
1 2
2
1 1
2
1 1
) (
2
1
) (
2
1
) (
2
1
) ( 1
2
1
) (
2
1
th gs n diff
th gs n th gs ox n
th gs n th gs ox n
V V
W
W
k i
V V k V V
L
W
C I
V V
W
W
k V V
L
W W
C I
−

.

\
 ∆
=
− = −

.

\

=
−

.

\
 ∆
+ = −

.

\
 ∆ −
=
µ
µ
From Figure 10b, we have:
) ( ,
1 1 1 1 th gs n m eq m diff
V V k g where V g i − = ∆ =
Equation 1 ) (
2
1
1 ,
1
th gs to due eq
V V
W
W
V −
∆
= ∆ ⇒
∆β
V
DD
M
1
(OS)
W−∆W
L
M
2
W
L
M
clk
W
clk
L
M
3
M
4
invbot
1
invbot
2
M
5
M
6
V
in1
V
in2
clk
V
DD
M
1
W
L
M
2
W
L
M
clk
W
clk
L
M
3
M
4
invbot
1
invbot
2
M
5
M
6
V
in1
V
in2
clk
+ −
I
1
I
2
I
1
I
2
∆V
eq
(a) (b)
15
Although this is a valid equation, this gives no insight on how it behaves for a given input
common mode voltage, which could be determined and controlled easily. Thus, it is
desirable to relate V
gs1
with input V
cm
.
Figure 11 common mode analyses of M
1,2
If we look at only common mode voltage, the input differential pair can be
combined into a single transistor twice as wide as original. Thus, circuit in Figure 11a can
be transformed to Figure 11b. M
clk
is in triode region, so it is modeled as a resistor, and
M
1,2
are in saturation because their drains are closed to V
DD
at the beginning of
evaluation mode. Hence we can write:
1
2
1 12
1
,
2
1 1
1
2
1 1
1 , 2
1 1
) (
) (
) (
) (
) (
) (
2
1
2
gs
th DD clk
th gs
gs
th DD clk n
th gs n
gs th gs n clk cm
clk
gs cm
clk
clk ds
th gs n
V
V V W
V V W
V
V V k
V V k
V V V k R V
R
V V
R
V
V V k I
+
−
−
= +
−
−
= + − =
−
= =

.

\

− =
V
DD
M
1
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
M
4
invbot
1
invbot
2
M
5
M
6
V
cm
V
cm
clk
V
DD
M
12
2W
12
L
R
clk
M
34
invbot
12
M
56
V
cm
+
V
ds,clk
_
(a) (b)
I
16
This is a quadratic equation, so we can solve for (V
gs1
−V
th
) after subtracting both sides by
V
th
:
Equation 2


.

\

−
−
−
+
−
= − 1
) (
) ( 4
1
2
) (
12
12
1
th DD clk
th cm th DD clk
th gs
V V W
V V W
W
V V W
V V
Therefore, we can substitute Equation 2 back to Equation 1 to get the input referred offset
due to current factor mismatch of M
1
in terms of input V
cm
.
1
, β ∆
∆
to due eq
V is, thus,
approximately square root of (V
cm
− V
th
) dependence.
Offset due to threshold mismatch of M
3
, ∆V
th2
:
At the beginning of evaluation phase, invbot
1,2
will drop from V
DD
. By the time
that invbot
1,2
drops to V
DD
−V
thn
, transistors M
3,4
will turn on. However, M
14
are still in
saturation. M
3,4
act as cascode devices, and thus, ∆V
th2
does not create any offset at the
beginning of evaluation phase.
As invbot
1,2
continue to drop and input devices M
1,2
enter triode region, ∆V
th2
influences the differential current and thus creates offset. Let us analyze the differential
current as in the previous case. Here, I assume that out1, out2 are still closed to V
DD
, and
M
5,6
are still off. This assumption is reasonable because by the time that M
5,6
are on, the
signal is amplified, and hence the influence of ∆V
th2
becomes relatively small.
17
Figure 12 Threshold mismatch of M
3
In Figure 12a, since M
1,2
enter triode region, they are modeled as resistors. As a
result, M
3,4
is a degenerated differential pair. The differential current is:
) (
1
), ( ,
1
,
1 1
1 3 3 3
1 3
3
, 3 2 , 3
th gs n
th gs n m
m
m
eff m th eff m diff
V V k
R and V V k g
R g
g
g where V g i
−
= − =
+
= ∆ =
In Figure 12b, differential current due to equivalent offset voltage is:
1 1 1 1
,
ds n m eq m diff
V k g where V g i = ∆ =
Using these two equations, we can find the input referred offset. However, the
mathematics becomes complicated very quickly. To simplify the calculation, we note that
3
1 3
3
1
1
1
m
m
m
g
R g
g
R
≤
+
≤
We can use this to calculate the upper and lower bounds of input referred offset. Since
upper bound gives the worst case offset, only upper bound calculation is shown here. As
a result, the upper bound of input referred offset due to ∆V
th2
is
V
DD
M
1
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
(OS)
W
36
L
M
4
W
36
L
invbot
1
invbot
2
M
5
M
6
V
out1
V
out2
V
in1
V
in2
clk
+ −
∆V
th2
V
DD
M
1
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
W
36
L
M
4
W
36
L
invbot
1
invbot
2
M
5
M
6
V
out1
V
out2
V
in1
V
in2
clk
+ −
∆V
eq
(a) (b)
18
Equation 3
2
1 12
3 36
2
1
3
,
) (
2
th
ds
th gs
th
m
m
V to due eq
V
V W
V V W
V
g
g
V
th
∆
−
= ∆ ≤ ∆
∆
Again, we want to relate the above equation with input common mode voltage, so we do
a common mode analysis.
Figure 13 common mode analyses for M
3
Assuming out1, out2 are closed to V
DD
, we can find V
ds1
:
Equation 4 ) ( ) (
1 3 1 gs cm gs DD ds
V V V V V − − − =
From current equations, we have:
Equation 5
2
3 3 1
2
3 3
1
) ( ) (
th gs n clk gs cm th gs n
clk
gs cm
V V k R V V V V k
R
V V
I − = − ⇒ − =
−
=
Substituting the above back to V
ds1
, and substituting V
ds1
into Equation 3, input referred
offset voltage becomes:
V
DD
M
1
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
W
36
L
M
4
W
36
L
invbot
1
invbot
2
M
5
M
6
V
out1
V
out2
V
cm
V
cm
clk
V
DD
M
12
2W
12
L
R
clk
invbot
12
M
56
V
out12
V
cm
+
V
ds,clk
_
(b)
M
34
2W
36
L
(a)
I
19
Equation 6
2
12
36
2
3 3 3
3
,
) (
2
th
OD n clk OD th DD
OD
V to due eq
V
W
W
V k R V V V
V
V
th
∆
− − −
≤ ∆
∆
, where
th gs OD
V V V − =
3 3
is the overdrive voltage of M
3.
The exact relationship between V
OD3
and V
cm
could be found by writing the drain current
of transistor M
1
and substituting into Equation 5. Instead of the complete equations, to
understand how ∆V
eq,due to ∆Vth2
and V
cm
are related, we can pay attention on the
denominator of Equation 6. The denominator is simply a constant (V
DD
–V
th
) subtract
(V
OD3
+R
clk
k
n3
V
OD3
2
). We can expect that (V
OD3
+R
clk
k
n3
V
OD3
2
) increase with V
cm
by
inspecting Equation 5. The denominator will eventually reduce to zero if we allow V
cm
to
increase beyond V
DD
. In other words, ∆V
eq,due to ∆Vth2
will increase to infinity in the same
way as hyperbola. However, in the limited range of V
cm
, we can only see a small portion
of hyperbolic curve as shown in simulation results in Figure 15.
Offset due to current factor mismatch of M
3
, ∆β
2
:
As in the previous case, we treat transistors M
1,2
as resistors, and we can write the
differential current due to ∆β
2
as:
20
Figure 14 Current factor mismatch of M
3
( ) ( )
( ) ( ) ( )


.

\
 ∆
+ ∆ +


.

\
 ∆
+ ∆ − − −
∆
=
− − − ∆ −


.

\
 ∆
+ =
36
2
3
36
3 3
2
3
36
3
2
3
2
3 3
36
3
1 1 2
2
1
1
2
1
W
W
V
W
W
V V V V V
W
W
k
V V V V V
W
W
k i
gs gs th gs th gs n
th gs th gs gs n diff
where ∆V
gs3
is the small change in V
gs3
due to introducing
36
W
W ∆
in M
3
.
We can neglect the products of ∆ terms because they are relatively small, and the
differential current is equal to the difference of current through M
1,2
, which is modeled as
R
1
. Assuming the gate voltages of transistors M
3,4
are the same, we can write:
( ) ( )
1
3
3 3
2
3
36
3
2
2
1
R
V
V V V V V
W
W
k i
gs
gs th gs th gs n diff
∆
=
∆ − − −
∆
≈
Equation 7
( )
( )
( )
3 1
2
3
36
3
3 3 1
2
3
36
3
1
2
1
1
2
1
m
th gs n
th gs n
th gs n
diff
g R
V V
W
W
k
V V k R
V V
W
W
k
i
+
−
∆
=
− +
−
∆
≈ ⇒
V
DD
M
1
W
12
L
M
2
W
12
L
M
clk
W
clk
L
M
3
(OS)
W
36
−∆W
L
M
4
W
36
L
invbot
1
invbot
2
M
5
M
6
V
out1
V
out2
V
in1
V
in2
clk
V
DD
M
clk
W
clk
L
M
3
(OS)
W
36
−∆W
L
M
4
W
36
L
invbot
1
invbot
2
M
5
M
6
V
out1
V
out2
clk
R
1
R
1
(a) (b)
21
The expression in Equation 7 makes sense because it simply states that the small change
in drain current due to ∆β
2
is the increase in current for a nondegenerated transistor
divided by (1+degeneration loop gain). Again to simplify the calculation, we calculate the
upper bound of input referred offset voltage.
( )
2
3
36
3 1
2
1
th gs n eq m diff
V V
W
W
k V g i −
∆
≤ ∆ =
Equation 8
( )
1 1
2
3
36
3
,
2
1
2
ds n
th gs n
to due eq
V k
V V
W
W
k
V
−
∆
≤ ∆
∆β
Equivalently, we can express this in terms of V
OD3
as in the previous case by using
Equation 4 & Equation 5.
Equation 9
( )
2
3 3 3
2
3
36 12
36
,
2
1
2
OD n clk OD th DD
OD
to due eq
V k R V V V
V
W
W
W
W
V
− − −
∆
≤ ∆
∆β
,where
th gs OD
V V V − =
3 3
As you can see, the denominator is exactly the same as that of ∆V
eq,due to ∆Vth2
. Therefore,
∆V
eq,due to ∆β2
has a hyperbolic increasing characteristic too. Although the numerator of
∆V
eq,due to ∆β2
increases faster than that of ∆V
eq,due to ∆Vth2
, the overall rate of change is
dominated by the denominator. As a result, ∆V
eq,due to ∆β2
is similar to ∆V
eq,due to ∆Vth2
as
shown in simulation results in Figure 15.
Offset due to threshold mismatch of M
5
, ∆V
th3
and current factor mismatch of M
5
, ∆β
3
:
It can be seen that threshold mismatch and current factor mismatch of M
5
have
22
little influence on input referred offset voltage. It is true because by the time that M
5,6
turn on, the differential signal is already amplified to a large amplitude compared to the
mismatches. In other words, the gain from input to output is large, offset due to M
5,6
on
the output is divided by a large gain caused by positive feedback; as a result, the input
referred offset voltage due to M
5,6
is very small. The simulations show consistent results
with the theory.
Total input referred offset voltage:
The device mismatches are statistical numbers, and they are modeled as Gaussian
distribution. As a result, the total input referred offset is found by summing the variance
of the 6 mismatches above. That is
Equation 10
2
3
2
3
2
2
2
2
2
1
2
1 β β β
σ σ σ σ σ σ σ
∆ ∆ ∆ ∆ ∆ ∆
+ + + + + =
Vth Vth Vth total
For convenience, the last two terms, σ
∆Vth3
and σ
∆β3
, can usually be neglected because
they are relatively small.
Simulations on input referred offset voltages over different V
cm
:
The simulation results on input referred offset voltage show that the equations
above can predict the offset. Also, the variations on offset with varying V
CM
are also
consistent with the theory. Figure 15 shows the 3σ offset due to each transistor.
Obviously, the dominant sources of input referred offsets are due to transistor M
14
, and
offsets due to M
5,6
are negligible. The overall offset is again calculated by summing the
23
variances as in Equation 10. For example, at V
cm
= 1.4V, standard deviations of input
referred offset due to each differential pair are σ
∆Vth1
= 10.1mV, σ
∆β1
= 10.3mV, σ
∆Vth2
=
9.5mV, σ
∆β2
= 8.1mV, σ
∆Vth3
= 1.9mV, σ
∆β3
= 0.7mV. Using Equation 10, the standard
deviation of total input referred offset, σ
total
= 19.2mV, and the worst case total input
referred offset is 6σ
total
= 115mV.
0.8 1 1.2 1.4 1.6 1.8
0
10
20
30
40
50
60
Input Vcm
I
n
p
u
t
R
e
f
e
r
r
e
d
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to Device Mismatch of Core Comparator
vt1
vt2
vt3
beta1
beta2
beta3
Figure 15 Input referred offset voltage due to each transistor
24
2.2 Supply Sensitivity
In the previous section, we found that input referred offset changes with V
CM
. In
addition, we found that as supply voltage changes, the input referred offset changes as
well. In most digital system, supply voltage is noisy because of the digital switching
property. As a result, it is important to know the supply sensitivity on offset. In order to
find the supply sensitivity, we need to find the supply sensitivities due to each transistor
and then combine the results to obtain the overall supply sensitivity as in the case of input
referred offset. Thus, the first section will discuss the supply sensitivity on offset due to
each transistor. The second section will combine the results and obtain the overall supply
sensitivity on offset.
2.2.1 Supply Sensitivity due to each transistor
As in the offset calculations in 2.1.2, the comparator is broken into 3 differential pairs
and each pair has threshold mismatch, ∆V
th
, and current factor mismatch, ∆β. Supply
Sensitivity on offset due to each differential pair has been found in simulations. Since
offset due to ∆V
th1
, which is simply equal to input referred offset, does not change with
supply and offset due to ∆V
th3
and ∆β
3
are much smaller than other offsets, supply
sensitivity due to ∆V
th1
, ∆V
th3
, and ∆β
3
are not shown in Figure 16.
25
0.8 1 1.2 1.4 1.6 1.8
10
15
20
25
30
35
40
45
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to beta1 mismatch
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6 1.8
−4
−3
−2
−1
0
1
2
3
4
Input Vcm (V)
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to beta1 mismatch
+10% Sup
−10% Sup
(a) (b)
0.8 1 1.2 1.4 1.6 1.8
0
10
20
30
40
50
60
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to beta2 mismatch
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6 1.8
−4
−2
0
2
4
6
8
Input Vcm (V)
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to beta2 mismatch
+10% Sup
−10% Sup
(c) (d)
0.8 1 1.2 1.4 1.6 1.8
0
20
40
60
80
100
Input Vcm (V)
I
n
p
u
t
R
e
f
e
r
r
e
d
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Offset due to vt2 mismatch
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6 1.8
−20
−10
0
10
20
30
Input Vcm (V)
C
h
a
n
g
e
i
n
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Offset due to vt2 mismatch
+10% Sup
−10% Sup
(e) (f)
Figure 16 Supply Sensitivity on Offset due to ∆β
1
, ∆β
2
, and ∆V
th2
26
In Figure 16, all offset values are 3σ standard deviation. In the plots on the left i.e.
(a), (c), and (e), “Normal” represents the offsets at normal supply 1.8V, which is exact
equal to the data in Figure 15. “10% Sup” represents the offsets when supply is 10%
higher than normal, which is 1.98V. “–10% Sup” represents the offsets when supply is
10% lower than normal, which is 1.62V. The plots in the right column i.e. (b), (d), and (f),
show the change in offset, ∆σ, from normal operating supply. Note that offset due to ∆β
1
has positive supply sensitivity, which means positive change of supply causes positive
change in offset, while offsets due to ∆β
3
and ∆V
th2
have negative supply sensitivity.
2.2.2 Overall Supply Sensitivity of Core Comparator
We can use change in offset, ∆σ, in 2.2.1 to calculate the overall supply
sensitivity on input referred offset. Since all offsets are statistical values, the overall
change in offset, ∆σ
total
, is calculated by using Equation 10. And the worstcase overall
supply sensitivity is 6∆σ
total
as shown in Figure 17. Figure 17a shows 6∆σ
total
in mV,
while Figure 17b shows
6∆σ
total
6σ
total
in percentage. In moderate V
CM
(1.2V – 1.4V) the
worstcase change in offset due to 10% supply change is about 10% also.
Before we finish this section, please keep in mind that Figure 17 shows the worst
case values. Offset of a comparator is a random variable, and so is supply sensitivity on
offset. In addition, notice that supply sensitivities on offset due to ∆β
1
and due to ∆V
th2
oppose to each other. This means that it is possible to obtain a high input referred offset
while supply sensitivity on offset is small, because the two opposing sources cancel with
27
each other.
0.8 1 1.2 1.4 1.6 1.8
0
10
20
30
40
50
60
Input Vcm (V)
T
o
t
a
l
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Supply Sensitivity on Offset
+10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6 1.8
0
5
10
15
20
25
30
35
Input Vcm (V)
P
e
r
c
e
n
t
a
g
e
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
%
)
Supply Sensitivity on Offset in Percentage
+10% Sup
−10% Sup
(a) (b)
Figure 17 Overall Supply Sensitivity on Offset
2.3 Speed
A second important requirement of a comparator is high sampling rate. Since the
comparator spends half of the cycle on evaluation and half of the cycle on reset, the
maximum sampling rate of a comparator depends on the speed of both evaluation and
reset. To do a complete analysis, the speed of evaluation and the speed of reset are
examined separately. First, analysis of evaluation phase will be performed and a set of
formula will be developed to represent how fast the evaluation is. Second, a criterion is
developed to assure proper reset. The effects on both evaluation and reset phase of
different input common mode bias, V
CM
, are discussed last.
2.3.1 Evaluation Phase
In evaluation phase, clock is logical high. All reset devices, RST
16
, are off, and
tail current M
clk
is on. Input differential pair will steer the current according to the
28
difference of inputs. In order to create a lot of gain within a short amount of time,
positive feedback is utilized. Unlike traditional operation amplifier, which has finite gain,
positive feedback system provides infinite gain. Positive feedback is realized by two
backtoback inverters. Here, characterizations on evaluation phase will be given, and
then the choices of transistor sizes will be briefly discussed. For your convenience,
Figure 7 is shown again in this section.
Figure 7 Core Comparator
Characterizations on Evaluation phase:
The whole evaluation phase can basically divided into three time intervals. In the
first time interval, the comparator changes from reset phase to evaluation phase. The
second time interval begins when V
invbot1,2
drop to V
DD
− V
thn
, turning on M
3,4
. And the
RST
2
4
2
M
5
4
2
V
DD
RST
1
4
2
RST
5
4
2
RST
6
4
2
M
6
4
2
M
3
4
2
M
4
4
2
RST
4
4
2
RST
3
4
2
M
1
8
2
M
2
8
2
M
clk
16
2
V
out1
V
out2
V
in1
V
in2
clk
clk
clk
clk
invbot
1
invbot
2
29
last time interval starts when V
out1,2
drop to V
DD
− V
thp
, turning on M
5,6
. Let us look at the
behavior of the comparator starting from the first time interval.
During reset phase, nodes invbot
1,2
are tied to V
DD
; thus, transistors M
36
are all off.
As a result, when the comparator changes from reset phase to evaluation phase, M
36
are
initially off. In this period, the only active devices are input differential pair M
1,2
and
current source M
clk
. Since M
36
are off, transistors M
1,2
see only capacitance on their drain,
C
invbot1,2
. The transfer function from input, in
1,2
, to invbot
1,2
, differential wise, can be
written as:
Equation 11
2 , 1
2 , 1
,
2 , 1
1
) (
invbot
m
diff in
invbot
sC
g
V
V
s H = = , where g
m1,2
is the transconductance of M
1,2
.
If we look at it more carefully, H
1
(s) is actually an integrator. This is desirable since it
gives infinite gain at DC while averaging or filtering out the high frequency noise
depending on viewing the problem in time domain or in frequency domain.
The second interval starts when M
3,4
turn on, i.e. V
invbot1,2
≅ V
DD
− V
thn
. Cross
coupled transistors M
3,4
provides positive feedback response. The response of positive
feedback is well known [4]. The differential output will be exponentially increasing with
time (often referred to as regeneration):
Equation 12
t
C
g
initial out out
out
m
e V t V
4 , 3
,
) ( = ,
where C
out
/g
m3,4
is regeneration time constant.
The third time interval is similar to the second time interval. As V
out1
, V
out2
drop to
V
DD
− V
thp
, M
5,6
turn on. The positive feedback, as a result, becomes stronger and
30
differential output becomes:
Equation 13
t
C
g g
initial out out
out
m m
e V t V
6 , 5 4 , 3
,
) (
+
=
Equation 13 is valid until M
36
enter triode region. As M
36
enter triode region,
g
m3,4
+ g
m5,6
decreases. Regeneration will eventually stop and V
out
saturates at V
DD
.
It is however not convenient to go through all three equations to calculate the
exact output. As a result, we developed a simplified equation to characterize the
evaluation phase.
Equation 14
τ
delay
t t
in out
e V t V
−
= ) ( ,
where
out
m m
C
g g
6 , 5 4 , 3
+
= τ and t
delay
captures the initial integrator response. The implicit
meaning of t
delay
is that we treat initial integrator response, which is much slower than the
regeneration response, as a delay on start of regeneration. Equation 14 enables us to
compare the evaluation speed of different comparators.
Choice of transistor sizes
In order to choose the transistor sizes such that the comparator gives fastest
evaluation, we should maximize integrating factor and minimize regeneration time
constant. This section will discuss the tradeoffs of sizing the transistors.
First, it is desirable to minimize regeneration time constant, since smaller
regeneration time constant results in larger gain in fixed amount of time. Let us first
concentrate on the effects of M
36
. According to [5], having the width ratio of M
3,4
and
31
M
5,6
equal to 1.0 gives the best regeneration. As you notice, the P:N ratio is smaller than
normal inverter P:N ratio, which is normally 23. In comparator both NMOS and PMOS
provide positive feedback, while PMOS has larger parasitic; thus, it is natural to size
down PMOS. If loading capacitance is large, increasing the width of M
36
will increase
out
m m
C
g g
6 , 5 4 , 3
+
, so regeneration is faster. On the other hand, if loading capacitance is so
small that the gate capacitance of M
36
dominates, increasing the width of M
36
will not
change
out
m m
C
g g
6 , 5 4 , 3
+
because both g
m3,4
+ g
m5,6
and C
out
increase at the same time. Under
small loading capacitance condition, although regeneration time constant does not depend
on the width of M
36
, it is not a good idea to choose arbitrarily large M
36
because M
3,4
add parasitic capacitance on node invbot
1,2
, which lowers down the integrating factor and
prevents the common mode of invbot
1,2
from dropping down and thus delays the start of
regeneration. Another way to decrease the regeneration time constant is to increase the
current and thus increase the width of M
clk
. As a result, there is tradeoff between power
and speed.
Secondly, we consider increasing the integrating factor
2 , 1
2 , 1
invbot
m
C
g
. It is obvious that
we should minimize C
invbot1,2
. However, when we employ digital offset compensation,
C
invbot1,2
often increases. This will be discussed in more detail when we consider the
speed penalty of digital offset compensation in Chapter 3. Another way to increase the
integrating factor is to increase input g
m
. We can increase either the width of input
devices M
1,2
or the width of current source M
clk
. The former is a tradeoff with input
32
capacitance, while the latter is a tradeoff with power. From equation,
D ox m
I
L
W
C g
2 , 1
2 , 1
2µ = we find that the rates of increase in g
m1,2
should be the same for
sizing M
1,2
and for sizing M
clk
. However, since M
clk
is often in triode region, sizing M
1,2
increases not only W
1,2
/L but also I
D
because smaller V
gs1,2
results in larger V
ds,clk
.
Therefore, sizing input devices M
1,2
gives us more advantages. Note that sizing input
devices M
1,2
also gives advantages in term of input offset voltage.
Simulation Results on Sizing Transistors
The evaluation speed has been simulated to confirm the intuitive understanding
explained above. [5] states that the comparator gives the best performance by having the
ratio between M
3,4
and M
5,6
equal to 1, so the width of M
36
are always the same in all
simulations below. The three remaining parameters are width of transistors M
clk
, M
1,2
,
and M
36
. To compare the speed, we calculate the regeneration time constant τ, and t
delay
(see Equation 14 for definition). To show the combined effect, we also calculate the time
from clock transition to the time that differential output reaches 1.2V, denoted as
t
(@Vout=1.2V)
. An output of 1.2V is chosen because it is large enough to toggle the output
stage, for example inverter or SR latch. We rank the comparators using T
(@Vout=1.2V)
. In
the table shown below, columns M
clk
, M
1,2
, and M
36
are the ratio of their width to the
minimum transistor width (W
min
/L) = 4λ/2λ = 0.48µm/0.24µm. For example, M
clk
= 2×
means that size of M
clk
= 2W
min
/L = 8λ/2λ = 0.96µm/0.24µm. Note that L=0.24µm has
effective length L
eff
= 0.18µm.
Sim M
clk
M
1,2
M
36 τ(ps) t
delay
(ps) T
(@ Vout=1.2V)
(ps) Ranks
33
1 1× 1× 1× 40.4 74.0 263 8
2 2× 1× 1× 37.8 57.2 234 6
3 1× 2× 1× 37.2 55.6 227 5
4 1× 1× 2× 42.0 98.7 307 10
5 2× 2× 1× 34.3 38.3 196 1
6 1× 2× 2× 36.2 79.2 255 7
7 2× 1× 2× 38.9 75.6 265 9
8 2× 2× 2× 32.8 54.9 211 2
9 4× 1× 1× 37.2 45.3 219 4
10 1× 4× 1× 38.6 40.8 217 3
11 1× 1× 4× 52.5 130 425 11
Table 1 Simulation results on evaluation with varying comparator transistor size
As shown in the table, sim5, which doubles both M
clk
and M
1,2
, gives the fastest
response. This makes sense because we simultaneously increase positive feedback
g
m3,4
+g
m5,6
and input g
m1,2
, which is directly proportional to the integrating factor. One
would think that doubling all devices M
clk
, M1,2, and M
36
would be fastest. However,
sim8 is only second fastest. Although sim8 actually has a faster τ than sim5, sim8 has
more delay on t
delay
, resulting in a slower overall response.
The next two fastest are sim10 and sim9. The larger M
1,2
have a slight advantage
as discussed earlier. These two simulations are similar for the next two in the rank, sim3
and sim2.
The 7
th
in the rank is sim6. Again, increasing M
36
gives better τ than rank #36 do,
but it adds too much capacitance on node invbot
1,2
, which slow down the integration. The
other interesting result is that sim1 is ranked 8
th
, which tells us using all minimum size
does not necessarily give the slowest response. Sim7, sim4, and sim11 are slowest. These
three simulations show that increasing size of M
36
is not a good idea. Note that the
output loading effect is already taken into account in the simulations above. The details
34
of output loading will be discussed in section 2.6.
Once the comparator is optimized for the evaluation phase, we should design an
appropriate reset so that it can work correctly and efficiently.
2.3.2 Reset Phase
Reset is as important as regeneration for accurate operation. In order to reset a
comparator that has positive feedback, we must break its positive feedback loop and reset
it as fast as its regeneration. However, if the reset is incomplete and there is any residual
charge on V
out1
, V
out2
, positive feedback will amplify the residual charge exponentially
when evaluation phase comes again. As a result, a small residual charge can create large
input referred offset. In this project, differential output needs to be less than 0.5mV at the
end of reset phase to achieve the required accuracy. In this section, the design of reset
transistors is presented; tradeoffs between reset and evaluation will also be discussed.
Design of Reset Transistors:
During clock is logical low, the tail current source M
clk
is off. If no reset device is
added, the comparator will still stay in its state forever because of the positive feedback.
In order to break the positive feedback, we must place some transistors to break the back
toback inverter. All possible reset transistors RST
16
are shown in Figure 7. For your
convenience, Figure 7 is shown here again.
35
Figure 7 Core Comparator
The most important reset is RST
5
, which shorts the two outputs together. Without
RST
5
, the reset response is very poor. However, RST
5
alone is not enough because as
long as all 4 feedback devices are on, there is fighting between reset and regeneration. In
order to break the positive feedback, RST
1,2
and RST
3,4
are utilized.
Both RST
1,2
and RST
3,4
have their tradeoffs. First, RST
1,2
can only shut off
PMOS; as a result, there is still a slight fighting between reset and regeneration due to
NMOS M
3,4
. More importantly, since RST
1,2
are connected to out1,out2, the parasitic of
RST
1,2
will degrade the regeneration time constant. Second, RST
3,4
are indirect resets,
because they serve as reversing the current of NMOS M
3,4
. Once current is reversed, M
3,4
not only stop regenerating, but also help reset the comparator. In small signal analysis, a
crosscoupled NMOS pair under reversed current condition has effective resistance equal
RST
2
4
2
M
5
4
2
V
DD
RST
1
4
2
RST
5
4
2
RST
6
4
2
M
6
4
2
M
3
4
2
M
4
4
2
RST
4
4
2
RST
3
4
2
M
1
8
2
M
2
8
2
M
clk
16
2
V
out1
V
out2
V
in1
V
in2
clk
clk
clk
clk
invbot
1
invbot
2
36
to 1/g
m
. This 1/g
m3,4
will help cancel the −2/g
m5,6
from positive feedback PMOS M
5,6
,
leaving RST
5
to eliminate the rest of the negative resistance. Since RST
3,4
are indirect
resets, in the early part of the reset phase, it cannot reset the comparator as quickly as
RST
1,2
. On the other hand, RST
3,4
completely break the positive feedback, so it can
remove small output residue more quickly and more accurately than RST
1,2
. This
behavior can be seen in simulations in the next section. RST
3,4
do not degrade the
regeneration time constant, yet they degrade the integrating factor of a comparator.
The last reset is RST
6
. In digital offset compensated comparator, capacitance on
node invbot
1,2
is usually large; as a result, RST
6
is introduced to further reset the charge
on node invbot
1,2
.
Simulation Results on Reset Devices:
Simulations are performed with varying reset devices size to see the performance
change, including evaluation and reset. We simulate on different sizes of RST
1,2
, RST
3,4
,
RST
5
, and RST6. As in the evaluation section, one unit size is W
min
/L = 4λ/2λ =
0.48µm/0.24µm, and the device sizes are multiple of unit size. Simulation condition is
V
cm
=1.2V, M
clk
=4×, M
1,2
=2×, and M
3,4
=1×. This configuration is the same for all digital
offset compensated comparators so that we are able to perform a fair comparison later.
For comparison, we calculate all evaluation metrics, τ, t
delay
, and T
(@Vout=1.2V)
(see
Table 1 for definition). Three new measurements are maximum frequency in evaluation
phase, f
max,eva
= 1/(2 T
(@Vout=1.2V)
), reset time, t
reset
, that is the time required to reset a
comparator whose differential output decreases from full V
DD
to 0.5mV, and maximum
frequency based on reset time, f
max,rst
= 1/(2t
reset
).
37
Evaluation Phase Reset Phase
Sim Rst
5
Rst
1,2
Rst
3,4
Rst
6
τ(ps) t
delay
(ps) T
(@Vout=1.2V)
(ps)
f
max,eva
(GHz)
Rank t
reset
(ps)
f
max,rst
(GHz)
Rank
1 1× 0× 0× 0× 30.5 15.7 157 3.19 1 836 0.60 11
2 1× 1× 0× 0× 33.0 19.3 171 2.92 5 332 1.51 9
3 1× 0× 1× 0× 30.6 21.2 162 3.08 2 305 1.64 8
4 1× 1× 1× 0× 32.9 24.6 176 2.84 7 174 2.88 2
5 1× 1× 1× 1× 32.9 29.0 181 2.77 8 175 2.85 3
6 2× 0× 0× 0× 32.3 20.7 170 2.95 4 650 0.77 10
7 2× 1× 0× 0× 34.7 24.3 184 2.72 9 269 1.86 6
8 2× 0× 1× 0× 32.3 26.5 176 2.85 6 234 2.14 4
9 2× 1× 1× 0× 34.7 27.9 187 2.67 11 149 3.36 1
10 1× 2× 0× 0× 35.3 24.0 186 2.68 10 266 1.88 5
11 1× 0× 2× 0× 30.6 26.0 167 2.99 3 281 1.78 7
Table 2 Simulation results on reset device
Let us analyze the results shown in Table 2 from top to bottom. Sim1 is a
comparator with only RST
5
, the middle reset that ties both outputs together. As expected,
it gives the fastest evaluation but the slowest reset. Next, adding RST
1,2
in sim2 will
speed up the reset, almost 3 times as fast as original. Also as expected, adding RST
1,2
slightly degrades the regeneration time constant because it adds capacitance on the output
nodes. Sim3 has a highly desirable result. By adding RST
3,4
, the comparator resets faster
than that in sim2 while degradation of evaluation is minimum, i.e. the 2
nd
fastest in
evaluation. Since RST
3,4
do not add parasitic capacitance on out1,out2, the regeneration
time constant is almost the same as that in sim1. Although integrating factor is reduced,
which can be seen by comparing t
delay
, the overall evaluation performance is not heavily
degraded because the comparator spends only a short time on integration.
Sim4 uses both RST
1,2
and RST
3,4
; hence, reset response is much faster, the 2
nd
fastest. Among all comparators shown in this table, sim4 is the best since both evaluation
and reset achieve 2.8Ghz. In next simulation, further adding reset RST
6
seems to give
38
adverse results, where both evaluation and reset is slower than those in sim4. However,
note that RST
6
may become more useful when digital offset compensation is added to the
comparator. The effect of RST
6
will be discussed more in Reset Penalty in Chapter 3.
Sim69 have similar behavior as sim14 do. Generally, sim69 have slower
evaluation but faster reset because of the doubled RST
5
. In sim10 and sim11, we see that
doubling RST
1,2
or doubling RST
3,4
alone can never be as efficient as having RST
1,2
and
RST
3,4
simultaneously (sim4).
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Time, ns
D
i
f
f
e
r
e
n
t
i
a
l
O
u
t
p
u
t
,
m
V
Reset Response of a comparator
←sim2
←sim3
sim10→
sim11→
Figure 18 Reset Response of sim2, sim3, sim10, and sim11
Interestingly sim3 resets faster than sim2, but sim11 resets slower than sim10.
Figure 18 illustrates the reason. RST
1,2
(sim2 & sim10) can reset the comparator quickly
at the beginning; however, the fighting between reset and regeneration exists, and thus it
takes a long time to eliminate small residue charge. On the other hand, RST
3,4
(sim3 &
39
sim11) mainly reverse the current of M
3,4
; hence, there is a delay before the positive
feedback is broken. After the feedback is broken, comparator is completely reset at a
rapid rate.
In conclusion, sim4, which has RST
5
, RST
1,2
, and RST
3,4
, gives the best tradeoff
between evaluation and reset. This configuration can break the positive feedback quickly
while it does not heavily degrade the evaluation.
Effects on evaluation and reset with varying Vcm:
The comparator shown in Figure 7 works only in a certain range of input common
mode voltage, V
cm
. For the lower bound, the input common mode voltage must be high
enough to turn on both input devices M
1,2
and current source M
clk
. (V
cm
> V
th1,2
= 0.4V)
For the upper bound, the input common mode voltage is limited by the power supply on
chip (V
cm
< V
DD
= 1.8V). It is found that the comparator achieves the best performance in
intermediate V
cm
. The simulation results are shown below.
Evaluation Phase Reset Phase
V
cm
(V)
τ(ps) t
delay
(ps)
T
(@Vout=1.2V)
(ps)
f
max,reg
(GHz)
t
reset
(ps) f
max,rst
(GHz)
0.8 39.5 33.9 216 2.31 168 2.97
1.0 34.5 24.8 184 2.72 171 2.92
1.2 32.9 24.6 176 2.84 174 2.88
1.4 32.2 29.7 178 2.81 176 2.84
1.6 31.7 35.6 182 2.75 178 2.82
1.8 31.4 45.4 190 2.63 179 2.80
Table 3 Evaluation and Reset with vary Vcm (see Table 1,Table 2 for term definition)
At low V
cm
the regeneration is slow as expected because low V
cm
results in low
V
ds,Mclk
thus low tail current. As V
cm
increases, tail current increases, so regeneration time
constant decreases. However, at high V
cm
, t
delay
becomes worse since input devices M
1,2
40
enter triode region, which decreases input g
m
and thus the integrating factor. In short, τ
becomes worse in low V
cm
, and t
delay
becomes worse in high V
cm
. Intermediate V
cm
therefore gives the fastest evaluation.
For reset phase, high V
cm
leads to slightly slower reset. A high common mode
input tries to pull down invbot
1,2
harder, which opposes the pull up of the reset devices.
Comparing the variation of f
max
in evaluation phase and reset phase, we can see
that within the possible V
cm
bounds (0.4V < V
cm
< 1.8V), the comparator still provides a
good performance in the range of 1.0V ≤ V
cm
≤ 1.6V.
2.4 Input Capacitance
In applications, like oversampler and flash ADC, a bank of comparators is
typically placed in parallel. Total input capacitance, in these cases, may become
enormous because it is simply equal to the input capacitance of a single comparator
multiplied by number of comparators in parallel. Therefore, it is desirable to minimize
the input capacitance of a comparator. Unfortunately, the input capacitance of a simple
comparator, like Figure 7, is the gate capacitance of input devices M
1,2
, which must be
sized to fulfill the input referred offset requirement. As a result, there is a direct tradeoff
between input capacitance and offset. One of the methods to decouple the relationship
between input capacitance and offset is digital offset compensation. The input
capacitance requirement will be revisit in Chapter 3 where digital offset compensation is
introduced.
41
2.5 Power Consumption
Power consumption is also a big issue when numerous comparators are used in
applications, like oversampling receiver and flash ADC. Again, the total power
consumption simply gets multiplied by the number of comparators. To reduce the power
consumption, load capacitance and current must be minimized. Assuming that load
capacitance is already minimized by proper sizing and careful layout, we can only reduce
current by minimizing tail current transistor M
clk
. As current has direct relationship with
speed, there is obviously tradeoff between power consumption and speed. Fortunately,
power consumption of a comparator is typically much less than normal operation
amplifier because positive feedback saturates the backtoback inverters and shuts off the
current when evaluation is finished. Moreover, according to [3], comparator shown in
Figure 7 has a better power efficiency among other architecture. Simulation results on
power measurements are shown in Table 4. As you can see, power consumption increases
with input common mode voltage because M
clk
is usually in triode region and V
ds,clk
varies
with V
cm
.
V
CM
(V) 0.8 1.0 1.2 1.4 1.6 1.8
Power (µW) 79.41 87.76 94.25 100.4 106.0 112.2
Table 4 Power Consumption of Core Comparator
2.6 Design of Next Stage (SR Latch)
In order to provide a constant logical output over one period, we must place a SR
latch after the comparator. Since comparator outputs provide full swing signal in
42
evaluation phase and are pull up to V
DD
in reset phase, a NAND based SR latch is well
suited. However, a NAND based SR latch may not give satisfying performance at high
speed. Hence, a simplified SR latch as shown in Figure 19 has been designed.
Figure 19 Simplified SR Latch
During evaluation phase, full swing differential signal from comparator is converted to
single ended digital signal at SRoutb. During reset phase, V
in1
, V
in2
are pull up to V
DD
,
turning off M
SR1,SR2
. Thus, Node SRoutb stays constant until the next evaluation phase
comes again. This behavior is exactly same as a NAND based SR latch. The advantage of
this circuit is its high speed and low input capacitance, which directly affects comparator
regeneration time constant and power consumption. Although this SR latch has
systematic offset and large random offset due to small transistor size, fortunately
comparator has large gain, so input referred offset due to SR latch is well below 2mV
according to simulation. For fair comparison, all digital offset compensated comparators
in the next chapter are followed by this SR latch. Inverters are then used to buffer up to
drive the output.
M
SR1
4
2
M
SR2
4
2
V
DD
V
DD
M
SR3
4
2
M
SR4
4
2
V
in1
V
in2
Output
SRoutb
43
Chapter 3 Digital Offset Compensation
The most important feature of digital offset compensation in comparator is that
offsets are measured digitally and are stored in static memory. Once offsets are stored,
the comparator can remain in open loop system, and thus, inherent speed of a comparator
can possibly be achieved.
In this project, four architectures on digital offset compensation are considered.
This project will compare the characteristics of these four architectures, and tradeoffs
between them. We compare all four architectures by measuring the performance metrics,
which were characterized for the core comparator in chapter 2. In this chapter, four
architectures are first presented, and their basic operating principles are explained.
Section 3.2 – 3.6 will compare performance metrics: input referred offset, supply
sensitivity, speed, input capacitance, and power consumption respectively. The last
section will give a summary of comparison of all four architecture.
44
3.1 Four Different Architectures
3.1.1 Architecture Comp1
Figure 20 Schematic of Comp1
The first architecture, Comp1, is shown in Figure 20. Extra devices M
CM16
and
M
OS16
are placed in parallel with input devices to steer small amount of current. This
current will provide an offset to compensate for the internal offset due to device
mismatches. Node V
CM
is connected to the common mode voltage of inputs V
in1
and V
in2
.
Since internal offset varies with common mode as you can see in Figure 15, an offset
compensation that varies with V
CM
can increase the correction precision. Nodes D
14
are
controlled digitally. Turning on only D
1
provides the least offset correction, so we call it
RST
2
4
2
RST
1
4
2
M
cm4
4
6
M
CM3
4
6
M
6
4
2
M
1
8
2
M
5
4
2
M
2
8
2
M
clk
16
2
RST
6
6
2
M
3
4
2
M
4
4
2
RST
5
4
2
V
in1
V
in2
clk
RST
4
6
2
RST
3
6
2
clk
V
DD
clk clk
V
out1
V
out2
Invbot
2
Invbot
1
M
CM1
4
6
M
OS1A
4
6
M
OS1B
4
6
M
CM2
4
6
M
OS2
4
6
M
OS3
4
6
D
1 D
2
D
3
M
cm6
4
6
M
cm5
4
6
M
OS4
4
6
M
OS5
4
6
M
OS6A
4
6
M
OS6B
4
6
V
CM
V
CM
D
4
45
Least Significant Bit (LSB) correction. Turning on subsequent bits (D
2
, D
3
) increases the
correction in a binary fashion. If negative offset compensation is needed, D
4
will be
turned on and D
13
will be turned on appropriately to control the magnitude of the
negative offset. The LSB control devices, D
1
, is not half the size of D
2
device because it
is desirable to minimize the parasitic capacitance of M
CM16
and M
OS16
and not to slow
down the speed of the comparator. The performance and compensation nonlinearity of
Comp1 will be discussed in the next section.
3.1.2 Architecture Comp2
Figure 21 Schematic of Comp2
The second architecture, Comp2, is similar to Comp1. Schematic of Comp2 is
shown in Figure 21 [6]. The problem of Comp1 is its large parasitic capacitance due to
digital offset compensation. Each branch consists of 2 NMOS and the capacitance
RST
2
4
2
RST
1
4
2
M
6
4
2
M
1
8
2
M
5
4
2
M
2
8
2
M
clk
16
2
RST
6
6
2
M
3
4
2
M
4
4
2
RST
5
4
2
V
in1 V
in2
clk
RST
4
6
2
RST
3
6
2
clk
V
DD
clk clk
V
out1
V
out2
Invbot
2
Invbot
1
M
OS0
4
8
M
OS1
4
8
M
OS2
8
8
M
OS3
16
8
M
OS4
32
8
D
1b
D
2b
D
3b
V
CM
V
CM
D
4b
46
between the NMOS slows the comparison speed. In Comp2, one branch is a single
NMOS. Therefore, using linear scaling on M
OS14
in Comp2 does not degrade the speed
as severely as Comp1 does. M
OS14
are binary weighted, so additional coding on D
14
is
not needed. The supply of inverters is V
CM
, so the compensation magnitude also varies
with input common mode. Dummy device M
OS0
is added to balance the capacitance on
nodes invbot
1,2
, so no systematic offset is introduced when M
OS16
are off.
3.1.3 Architecture Comp3
Figure 22 Schematic of Comp3
The third architecture, Comp3, produces digital offset by controlling tail current
[7]. In Figure 22, tail current is split to M
clkL
and M
clkR
. Additional currents sources M
clk0
4
and M
OS04
are digitally controlled by D
14
. M
clk14
, and M
OS14
is binary weighted.
Dummy current source M
clk0
and M
OS0
is again for balancing the comparator. A small
RST
2
4
2
RST
1
4
2
M
6
4
2
M
1
8
2
M
5
4
2
M
2
8
2
M
clkL
8
2
RST
6
6
2
M
3
4
2
M
4
4
2
RST
5
4
2
V
in1
V
in2
clk
RST
4
6
2
RST
3
6
2
clk
V
DD
clk clk
V
out1
V
out2
Invbot
2
Invbot
1
M
7
4
4
V
DD
M
clkR
8
2
M
OS0
4
2
M
clk0
4
2
M
OS1
4
2
M
clk1
4
2
M
OS2
8
2
M
clk2
8
2
M
OS3
16
2
M
clk3
16
2
M
clk4
32
2
M
OS4
32
2
D
1
D
2
D
3
D
4
47
NMOS M
7
has three purposes. First, it reduces offset due to mismatch of M
clkL
and M
clkR
.
Second, the offsets created by digital compensation devices M
clk14
and M
OS14
are
reduced, so minimum channel length can be used to create the appropriate range of offset,
unlike Comp1 and Comp2, whose digital compensation parts have longer channel length.
Third, M
7
promotes current steering of differential pair M
1,2
. If M
7
is not present, M
1
sees
only M
clkL
, which is model as resistor because M
clkL
is in triode region. As a result, M
1
is
degenerated by R
MclkL
. On the other hand, if M
7
is present, M
1
is degenerated by
R
MclkL
//(R
M7
/2) so input g
m
is larger.
3.1.4 Architecture Comp4
Figure 23 Schematic of Comp4
The last architecture, Comp4, is shown in Figure 23 used by [8]. Comp4 varies
capacitances of invbot
1,2
; an imbalance current flowing into PMOS capacitors M
C04
produces offset. During digital signals D
1B4B
are high, PMOS M
C14
are off, so nodes
RST
2
4
2
RST
1
4
2
M
6
4
2
M
1
8
2
M
5
4
2
M
2
8
2
M
clk
16
2
RST
6
6
2
M
3
4
2
M
4
4
2
RST
5
4
2
V
in1
V
in2
clk
RST
4
6
2
RST
3
6
2
clk
V
DD
clk clk
V
out1
V
out2
Invbot
2
Invbot
1
M
C0
4
2
M
R
16
2
V
DD
D
1B
D
2B
D
3B
M
C1
4
2
M
C2
8
2
M
C3
16
2
×1 ×2 ×4
D
4B
M
R
16
2
×8 ×1
M
C4
32
2
RST
7
4
6
V
DD
48
invbot
1,2
see only source/drain overlap capacitances. If digital signal D
1B
, for example,
switches to low, PMOS M
C1
turns on, so invbot
2
sees source/drain overlap capacitance
plus channel capacitance due to M
C1
. A slight capacitance difference between invbot
1
and
invbot
2
results in a small current imbalance. As a result, by controlling the difference of
capacitance between invbot
1
and invbot
2
, offset of the comparator can be controlled.
PMOS M
R
, acting as a resistor, is placed in series with PMOS capacitance M
C04
. The
series resistors reduce the effective capacitance, so the digital offset precision can be
adjusted. M
R
is carefully sized so that the correction range of the digital offset
compensation just covers the maximum offset due to internal device mismatches.
3.2 Characteristics of Digital Offset Compensation
The goal of digital offset compensation is to create an offset that cancels the
internal offset due to device mismatches, so the overall offset of the comparator reduces
to zero ideally. This section discusses the offset magnitude for each comparator. However,
if the digital offset steps are not uniform, the overall offset after compensation will be
degraded. In other words, linearity among offset magnitude directly affects the worst
case overall offset. Linearity of offset compensation is secondly presented, and the worst
case overall offset after compensation is shown last.
3.2.1 Offset Magnitude of Digital Compensation
All four comparator Comp14 have 4bit (16level) offset correction. Simulations
have been performed to examine the characteristics of offset correction of each
comparator. Simulation results are shown in Figure 24 – Figure 27. “Device Mismatch”
49
represents 6σ of offset due to internal device mismatch of a core comparator. “Digital
OS” represents 16level offset correction of the comparators.
Figure 24 shows the digital offset for Comp1. Comp1 loses one digital level on
D
4
D
3
D
2
D
1
= 1111 because this digital value provides zero offset as shown in the
schematic in Figure 20. The variation of digital offset with V
CM
is similar to that of
internal device mismatch shown in dotted line in the figure. This property provides a
better correction over wide range of V
CM
.
Figure 25 shows the digital offset magnitude of Comp2. Comp2 provides 16level
correction. Each level is close to a constant value over high V
CM
. As you can see from the
distribution, the 16 levels divides 6σ internal offset quite evenly. The linearity is
expected to be the best and will be discussed in the next section in detail.
Figure 26 shows the digital offset of Comp3. Comp3 splits the tail current, so
mismatch between two tail currents contributes offset of the comparator. As a result, the
internal device mismatch is larger than Comp1, Comp2, and Comp4. The digital offsets
created by M
clk14
in Figure 22 increase fairly quickly with V
CM
, making a wide spread in
high V
CM
. The worstcase overall offset after compensation is, thus, degraded. In addition,
compression of the offset step size at high digital offset settings can be easily observed in
Comp3. The first positive LSB creates the largest step. As the digital value increases, the
offset difference between two levels diminishes because V
ds,clk
decreases with more M
OS1
4
turned on. Since V
ds,clk
is reduced, the offsets created by digital controlled branches
reduces as well.
50
0.8 1 1.2 1.4 1.6
−150
−100
−50
0
50
100
150
Input Vcm
I
n
p
u
t
r
e
f
e
r
r
e
d
o
f
f
s
e
t
(
m
v
,
d
i
f
f
e
r
e
n
t
i
a
l
)
Comp1, Digital Controlled Offset
Device Mismatch
Digital OS
Figure 24 Digital Offset of Comp1
0.8 1 1.2 1.4 1.6
−150
−100
−50
0
50
100
150
Input Vcm
I
n
p
u
t
r
e
f
e
r
r
e
d
o
f
f
s
e
t
(
m
v
,
d
i
f
f
e
r
e
n
t
i
a
l
)
Comp2, Digital Controlled Offset
Device Mismatch
Digital OS
Figure 25 Digital Offset of Comp2
51
0.8 1 1.2 1.4 1.6
−400
−300
−200
−100
0
100
200
300
400
Input Vcm
I
n
p
u
t
r
e
f
e
r
r
e
d
o
f
f
s
e
t
(
m
v
,
d
i
f
f
e
r
e
n
t
i
a
l
)
Comp3, Digital Controlled Offset
Device Mismatch
Digital OS
Figure 26 Digital Offset of Comp3
0.8 1 1.2 1.4 1.6
−200
−150
−100
−50
0
50
100
150
200
Input Vcm
I
n
p
u
t
r
e
f
e
r
r
e
d
o
f
f
s
e
t
(
m
v
,
d
i
f
f
e
r
e
n
t
i
a
l
)
Comp4, Digital Controlled Offset
Device Mismatch
Digital OS
Figure 27 Digital Offset of Comp4
52
As shown in Figure 27, the digital offsets of Comp4 increase gradually with V
CM
.
This characteristic is similar to that of Comp1. Some compression of the step size has
been observed.
3.2.2 Linearity of Digital Offset Compensation
All 4 architectures have equal number (4bit) of digital offset correction. The
nonlinear offset compensation will degrade the effect number of bit correction; as a result,
the accuracy will be degraded. This section compares the differential nonlinearity (DNL)
of each comparator.
Digital offset DNL of Comp1 is shown in Figure 28. The maximum DNL is
approximately 0.5 LSB. There is a clear “zig zag” pattern in the DNL profile. This
pattern is created by the nonlinear scaling on the digital controlled branches. We
observed that the LSB creates a larger offset then it should; thus, a large positive DNL in
one digital setting is followed by an equal magnitude but negative DNL in the subsequent
digital setting. Fortunately, the “zig zag” pattern creates less than 0.5 LSB DNL.
Figure 29 shows digital offset DNL of Comp2. It can be observed that as more
switches are asserted, the step size slightly decreases. As a result, Comp2 also has minor
compression of the offset step size, and it causes about 0.5 LSB DNL.
Digital offset DNL of Comp3 is shown in Figure 30. The DNL of Comp3 is the
worst among 4 architectures. The maximum DNL is as high as 1 LSB, reducing the
effective number of bits to less than 3 bits of correction. The compression described
earlier is particularly noticeable. Digital Offset
DNL of Comp4 is shown in Figure 31. Comp4 loses about 0.8 LSB DNL.
53
Figure 28 Digital Offset DNL of Comp1
Figure 29 Digital Offset DNL of Comp2
−10 −5 0 5 10
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
Comp1, Digital Offset DNL
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Digital Level, W
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
−10 −5 0 5 10
−0.4
−0.2
0
0.2
0.4
0.6
Comp2, Digital Offset DNL
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Digital Level, W
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
54
Figure 30 Digital Offset DNL of Comp3
Figure 31 Digital Offset DNL of Comp4
−10 −5 0 5 10
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
Comp3, Digital Offset DNL
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Digital Level, W
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
−10 −5 0 5 10
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
Comp4, Digital Offset DNL
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Digital Level, W
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
55
3.2.3 WorstCase Overall Offset after compensation
Ideally, overall offset of a comparator after digital offset compensation is equal to
maximum offset of the core comparator divided by 2
(Number of bits correction)
. In the previous
section, we know that effective number of bits should replace the actual number of bit to
capture the nonlinearity. In addition to nonlinearity, we found that the maximum offset
of the comparator should really be replaced by the offset correction range of the
particular architecture. In other words, the worstcase overall offset is approximated by
bits of number Effective
Range Correction Offset
2
. In simulation, the worstcase overall offset is calculated by
dividing the biggest step between two digital levels in Figure 24 – Figure 27 by 2 because
the worst situation is when internal offset lies at the middle of two digital offset levels.
The simulated results are shown in Figure 32.
Comp4 has larger worstcase overall offset then Comp1 and Comp2 because
Comp4 has not only worse DNL profile but also larger correction range (±220mV), while
the correction range of Comp1 and Comp2 is only ±150mV. The large worstcase overall
offset of Comp3 clearly shows that knowing only DNL is not sufficient. Even though
DNL of Comp3 is only two times larger than that of Comp1 and Comp2, the actual
worstcase offset of Comp3 is four times larger, because Comp3 has worse internal offset
to start, and thus has larger offset correction range. From this comparison of the worst
case overall offset, we conclude that Comp1 and Comp2 have the best compensation
offset and Comp3 is the worst.
56
Figure 32 Worstcase overall offset
3.3 Supply Sensitivity
As discussed in section 2.2, the input referred offset due to device mismatches
changes with supply voltage. Similarly, the digital offset changes with supply as well.
The overall supply sensitivity of an architecture is thus calculated by combining the
supply sensitivity of internal offset in section 2.2 and the supply sensitivity on digital
offset. In this section, simulations are performed to find the supply sensitivity on digital
offset of each architecture. The worstcase supply sensitivity of each comparator will be
obtained in the end of this section.
0.8 1 1.2 1.4 1.6
0
10
20
30
40
50
60
70
Input Vcm
W
o
r
s
t
−
c
a
s
e
o
f
f
s
e
t
(
m
v
,
d
i
f
f
e
r
e
n
t
i
a
l
)
Worst−case overall offset
Comp1
Comp2
Comp3
Comp4
57
0.8 1 1.2 1.4 1.6
70
80
90
100
110
120
130
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp1
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6
−10
−5
0
5
10
15
Input Vcm
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp1
10% Sup
−10% Sup
(a) (b)
Figure 33 Supply Sensitivity on Offset of Comp1
0.8 1 1.2 1.4 1.6
50
60
70
80
90
100
110
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp2
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6
−20
−10
0
10
20
30
Input Vcm
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp2
10% Sup
−10% Sup
(a) (b)
Figure 34 Supply Sensitivity on Offset of Comp2
0.8 1 1.2 1.4 1.6
0
100
200
300
400
500
600
700
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp3
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6
−100
−50
0
50
100
150
Input Vcm
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp3
10% Sup
−10% Sup
(a) (b)
Figure 35 Supply Sensitivity on Offset of Comp3
58
0.8 1 1.2 1.4 1.6
40
60
80
100
120
140
160
Input Vcm (V)
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp4
Noraml
10% Sup
−10% Sup
0.8 1 1.2 1.4 1.6
−20
−15
−10
−5
0
5
10
15
Input Vcm
C
h
a
n
g
e
i
n
O
f
f
s
e
t
(
m
V
,
d
i
f
f
)
Digital Offset of Comp4
10% Sup
−10% Sup
(a) (b)
Figure 36 Supply Sensitivity on Offset of Comp4
In Figure 33 – Figure 36, the plots on the left (a) show maximum digital offsets of
Comp1 – Comp4 when supply is “Normal”(1.8V), 10% higher (1.98V) “10% Sup”, and
10% lower (1.62V) “–10% Sup”. The plots on the right (b) show the change in offset,
∆V
DigiOS
, from normal supply, which is the supply sensitivity on offset in mV.
Having both supply sensitivities on offset due to internal mismatch and due to
digital offset compensation, the overall supply sensitivity on offset can be found for each
comparator. However, the calculation on overall supply sensitivity is not straight forward,
because all sensitivities are not independent random variables. Supply sensitivity due to
digital offset compensation, ∆V
DigiOS
, depends on the total internal offset of the
comparator, because digital value is set to compensate the internal offset at the beginning.
Thus, it is reasonable to state that ∆V
DigiOS
is proportional to internal offset, 6σ
total
. On the
other hand, the supply sensitivity on internal offset ∆σ
total
must also depend on total
internal offset 6σ
total
. Thus, supply sensitivity on digital offset ∆V
DigiOS
and supply
sensitivity on internal offset ∆σ
total
are correlated. Furthermore, we know ∆σ
total
is not
directly proportional to total input offset 6σ
total
because some mismatches have positive
59
supply sensitivity while the others have negative supply sensitivity. This causes a
possibility that high internal offsets, 6σ
total
, may have low supply sensitivity, ∆σ
total
. All
these situations complicate the calculation of overall supply sensitivity of Comp1 −
Comp4.
To develop special treatments on accounting the correlation between variables
seems to be out of scope of this project. A rough approximation on worstcase overall
supply sensitivity is thus given here. In this approximation, we pretend that ∆V
DigiOS
and
∆σ
total
are independent. With this assumption, we can calculate worstcase supply
sensitivity, ∆V
OS,SUP
, by:
( ) ( )
2 2
, total DigiOS SUP OS
V V σ ∆ + ∆ = ∆
Table 5 shows the results of ∆V
OS,SUP
at V
CM
=1.2V for all 4 comparators.
Comp1 Comp2 Comp3 Comp4
Supply
Sensitivity,
∆V
OS,SUP
*
13mV 18mV 22mV 16mV
*Worstcase supply sensitivity (±10% Change in Supply) measured at V
CM
= 1.2V
Table 5 Worstcase Supply Sensitivity of Comp1 − Comp4
3.4 Speed
As described in section 2.3, speed of the core comparator is determined by the
speed of two phases, evaluation phase and reset phase. In evaluation phase, regeneration
time constant τ, t
delay
(Equation 14), and t
(@Vout=1.2V)
(Table 1) characterize the evaluation
speed. In reset phase, reset time, t
reset
, that is time required to reset a comparator whose
differential output decreases from full V
DD
to 0.5mV determine the reset speed. In this
60
section, the same measurements are repeated for each of the four comparators. The first
subsection compares the speed of different architectures. The second subsection discusses
the penalty on digital offset compensation. The last subsection compares the linear and
nonlinear scaling on digital compensation devices.
3.4.1 Comparison on Speed of Different Architectures
In each of the four architectures, the extra devices for compensation impact the
speed. Moreover, the comparator speed changes with the digital offset compensation
settings. Therefore, in this section, speed of 4 comparators with zero digital offset will be
first compared to the original speed of the core comparator. The effects of different
digital settings will be presented next.
Digital Offset Compensation Off
Evaluation Phase Reset Phase
Architecture
τ(ps) t
delay
(ps) T
(@Vout=1.2V)
(ps) f
max,eva
(GHz) t
reset
(ps) f
max,rst
(GHz)
Core Comp 32.9 24.6 176 2.84 174 2.88
Comp1 36.8 38.6 211 2.37 201 2.49
Comp2 33.1 47.8 200 2.50 181 2.77
Comp3 33.9 53.2 210 2.38 173 2.89
Comp4 33.5 58.8 211 2.37 199 2.51
Table 6 Speed Comparisons with Digital Offset Compensation Off
Turning digital offset compensation off means setting digital offset be zero. In
order words, D
4
D
3
D
2
D
1
=0000 or D
4B
D
3B
D
2B
D
1B
=1111 in the case of Comp4. In Table 6,
data for “Core Comp” is repeated from the speed of core comparator with the following
configuration: V
cm
=1.2V, M
clk
=4×, M
1,2
=2×, M
3,4
=1×, RST
5
=1×, RST
1,2
=1×, RST
3,4
=1×,
and RST
6
=0×. For evaluation phase, digital offset compensation architectures impact the
61
speed of core comparator by 15%. This is expected because the digital compensation
devices contribute parasitic capacitance and slow down the comparison. Among four
architectures, Comp2 is fastest with digital offset compensation off. Reset devices are
intentionally made stronger, specifically, RST
3,4
=1.5×, RST
6
=1.5× and additional reset
like RST
7
and M
7
(see schematic of Comp14). The reset speed of Comp1 – Comp4 is
optimized under the condition when digital offset compensation is on. The reset devices
are carefully sized so that the reset speed and evaluation speed is similar, as shown in
Table 7 in the next subsection. Hence when digital offset compensation is off, the reset
speed is faster then the evaluation speed. Also, we know the reset speed with digital
offset compensation off is so fast that it will not be the limiting factor of the speed of the
comparator.
Digital Offset Compensation On
Evaluation Phase Reset Phase
Architecture
τ(ps) t
delay
(ps) T
(@Vout=1.2V)
(ps) f
max,eva
(GHz) t
reset
(ps) f
max,rst
(GHz)
Core Comp 32.9 24.6 176 2.84 174 2.88
Comp1 35.8 72.4 238 2.10 218 2.29
Comp2 34.5 65.1 224 2.23 229 2.19
Comp3 32.7 37.8 189 2.65 191 2.62
Comp4 36.6 66.8 232 2.15 231 2.17
Table 7 Speed Comparisons with Digital Offset Compensation On
When digital offset compensation is turned on, all digital compensation devices
are on. Since the speed of a comparator depends on input magnitude, we must make sure
that the input magnitude in this section is the same as that of last section. To do so, we
must force the comparators to have zero input referred offsets. Therefore, while we turn
on digital compensation devices, dummy devices, which include M
OS0
(Comp2 and
62
Comp3) and M
C0
(Comp4), are turned on at the same time to balance the comparator. In
short, digital settings will be D
4
D
3
D
2
D
1
=1111 for Comp1, 2, and 3 or D
4B
D
3B
D
2B
D
1B
=0000 for Comp4, and dummy devices are turned on as if they were connected to
D
1
or D
1B
.
With digital offset compensation, more parasitic capacitance is added to the
comparator, so the evaluation speed of Comp1, Comp2, and Comp4 slow down by 24%
compared to the core comparator. However, Comp3 is only 6.7% slower than the core
comparator because Comp3 increases the total tail current. Reset speed is designed to be
closed to the evaluation speed for optimizing the sampling rate.
With the sampling rate under conditions of offset compensation on and off, we
found that the maximum overall sampling rate of Comp1, Comp2, and Comp4 is limited
by compensation on condition, whereas overall sampling rate of Comp3 is limited by
compensation off condition. The maximum overall sampling rates of all architectures are
listed in Table 8. The percentage reduction on sampling rate compared to CoreComp is
listed in the last column. Overall, digital offset compensation reduces the sampling rate of
a comparator by 15% – 25%.
Architecture Sampling Rate
(GHz)
Sampling Rate
Reduction (%)
Core Comp 2.84 0%
Comp1 2.10 –26%
Comp2 2.19 –23%
Comp3 2.38 –16%
Comp4 2.15 –24%
Table 8 Maximum Sampling rate of different architecture
63
3.4.2 Speed Penalty of Digital Offset Compensation
This section only applies on Comp1, Comp2, and Comp4; Comp3 is actually
faster when digital offset compensation is on because of its split current architecture. The
speed penalty of Comp1, Comp2, and Comp4 is caused by several factors. The dominant
factor is the extra parasitic capacitances due to digital compensation devices, which have
been discussed in the last subsection. Another factor is the decrease in input
transconductance, g
m,in
, of Comp1,2,4 with increasing digital offset. The decreasing g
m,in
degrades the integrating factor, and thus the evaluation response is degraded. We will
carefully examine why input transconductance reduces in this section.
Loss in Input Transconductance, g
m,in
Figure 37 Illustration of input transconductance loss
In Comp1, Comp2, and Comp4, the common idea is to add some devices to
influence the current steering of input devices M
1,2
. Let us take a simple differential pair
and add an extra device to draw a constant current on one side, as shown in Figure 37.
Assume the current through the extra device is a fraction of I
SS
, say αI
SS
, where α ≤
1
2
.
For comparator, the only important operating point is where the differential output
current crosses zero, i.e. I
1
= I
2
. In addition, total tail current is I
SS
. Hence, I
M2
= 0.5I
SS
,
M
1
W
L
M
2
W
L
V
CM
+
∆V
in
2
V
CM
–
∆V
in
2
M
OS
I
M1
I
M2 αI
SS
I
1
I
2
V
CM
I
SS
64
and I
M1
= (0.5 – α) I
SS
. Small differential voltage ∆V
in
is applied to the inputs, creating
small differential current i
diff
.

.

\
 ∆
− − 
.

\
 ∆
+ = − =
2 2
2 1 2 1
in
m
in
m SS diff
V
g
V
g I i i i α
( )
2
2 1
in
m m SS diff
V
g g I i
∆
+ + = α
We can then find g
m1
and g
m2
by substituting I
M1
and I
M2
.
( ) ( )
2
5 . 0 2 5 . 0 2
in
SS OX n SS OX n SS diff
V
I
L
W
C I
L
W
C I i
∆


.

\

+ − + = µ α µ α
Equation 15
( )
( )
in SS OX n SS diff
V I
L
W
C I i ∆


.

\

+ −
+ = 5 . 0 2
2
1 2 1
µ
α
α
If α = 0, then
in SS D m diff
V I I g i ∆ = = ) 5 . 0 (
2 , 1
, which is the case without digital offset
compensation. In Equation 15 the first term αI
SS
is the offset created by M
OS
, and the
fraction
( )
2
1 2 1 + − α
is the factor of loss in input transconductance, g
m,in
. If α is small,
we can approximate the fraction
( )
2
1 2 1 + − α
with first order Taylor series, which gives

.

\

− α
2
1
1 . This means that if a fraction α of I
SS
is used in digital offset compensation, the
input transconductance is lost by
1
2
α. This also tells us that a comparator with larger
offset will have a slower speed, even though parasitic is not taken into account.
Furthermore, the input referred noise will increase as digital offset increases.
65
3.4.3 Comparison on Linear and Nonlinear scaling
When Comp1 was being designed, we found that a linear 4bit scaling on digital
offset compensation severely degraded the comparator performance. In this section, we
will compare Comp1 with 3bit linear scaling as shown in Figure 38, with 4bit linear
scaling (schematic is same as Figure 38 except that one more bit correction is needed),
and with 4bit nonlinear scaling as shown in Figure 20. Hence, we know how well the 4
bit nonlinear scaling improves the performance.
Figure 38 Schematic of Comp1 with 3bit linear scaling
Evaluation Phase Reset Phase
Architecture
τ(ps) t
delay
(ps) T
(@Vout=1.2V)
(ps) f
max,eva
(GHz) t
reset
(ps) f
max,rst
(GHz)
3bit Linear 34.7 73.0 233 2.15 216 2.32
4bit Linear 42.8 106.9 310 1.62 383 1.31
4bit Non
linear 35.8 72.4 238 2.10 218 2.29
Table 9 Speed Comparisons on linear and nonlinear scaling of Comp1
RST
2
4
2
RST
1
4
2
M
6
4
2
M
1
8
2
M
5
4
2
M
2
8
2
M
clk
16
2
RST
6
4
2
M
3
4
2
M
4
4
2
RST
5
4
2
V
in1
V
in2
clk
RST
4
4
2
RST
3
4
2
clk
V
DD
clk clk
V
out1
V
out2
Invbot
2
Invbot
1
×2 ×1 ×1
×1 ×1 ×2
V
CM
D
1
D
2
×4
×4
D
3
V
CM
66
From Table 9, 4bit linear scaling version performs poorly in both evaluation
phase and reset phase. Both speeds are almost half of the speeds that the 3bit version has.
In the 4bit nonlinear version, the performance is very closed to that of the 3bit linear
version. Moreover, we expect that the power consumption of the 4bit nonlinear version
is similar to that of the 3bit linear version as well. With the speed and power benefit, we
decided to use the 4bit nonlinear version and sacrifice 0.5LSB nonlinearity as shown in
Figure 28.
After comparing the speeds for digital compensation both off and on and
understanding the origin of speed penalty of digital offset compensation, we know that
digital offset compensation could reduce the speed by 15% – 25%. We can improve the
speed by changing the digital coding scheme. In the current setting, we control the whole
(both left and right) digital compensation in a single binary array, and the worst case is
during compensating for −1LSB offset, which corresponds to turning on all compensation
devices. As a result, all parasitic capacitances due to digital compensation are added to
the comparator and large portion of total current is used for offset compensation. On the
other hand, if we choose to control the left and right digital compensation separately,
which means we need digital signal D
3L
D
2L
D
1L
for left and another D
3R
D
2R
D
1R
for right
hand side, the worstcase becomes turning on all devices on one side only. Since we
reduce the number of active devices by half, we halve not only parasitic capacitance but
also the current flowing through digital compensation devices. The loss in input
transconductance is also reduced, so the speed of the comparator can be improved.
67
3.5 Input Capacitance
As shown in schematics Figure 20 − Figure 23, all four comparators do not
increase input capacitance. However, Comp1 and Comp2 need an extra terminal V
CM
.
Depending on applications, an extra driver may be needed to generate V
CM
. Fortunately,
V
CM
is a DC value or a low frequency signal. Hence, extra driver can be simple.
In applications of high order parallelism, the V
CM
driver is usually shared among all
comparators. The little extra hardware on V
CM
driver and the small input capacitance
make the digital offset compensation attractive in applications with high order parallelism.
3.6 Power Consumption
Similar to the speed issue, power consumption of each comparator is more than
that of core comparator, since digital offset compensation devices add parasitic
capacitance on the comparator. In the first subsection, power consumption of each
comparator is compared with that of core comparator. As in the speed section, we
separate our discussion into 2 cases. The first case is when digital offset compensation is
off, and the second case is when digital offset compensation is on. Clock loading and
power consumed on driving clock is discussed in the second subsection. The total power
of comparator and clocking will be discussed in the last subsection.
3.6.1 Power of Comparators
Digital Offset Compensation Off
When digital offset compensation is off, the comparator’s switched
68
capacitance does not include the channel capacitance; only source/drain overlap
capacitances are added to the comparator. The power consumption is, thus, closed to the
power consumption of the core comparator. Figure 39 shows power consumption of all
comparators, under the condition of digital offset compensation off, operating at 1.5GHz,
1.8V supply. Comp2 and Comp3 have similar power consumptions, which are closed to
that of core comparator. However, Comp4 dissipates more power because both source
and drain overlap capacitances are added on node invbot
1,2
. Comp1 has the largest power
consumption because M
CM16
are always on, and thus capacitances Cgd
Mcm16
, Cgs
Mcm16
,
and Cgd
Mos16
are added to invbot
1,2
. As a result, power consumption of Comp1 is largest.
Digital Offset Compensation On
When digital offset compensation is on, more capacitances are added on the
comparator. The power consumption thus increases. Figure 40 shows the power
consumption of all comparators operating at 1.5GHz, 1.8V supply. Comp4 is
interestingly the lowest power consuming. The reason is that Comp4 uses the smallest
size devices for digital offset compensation, its overlap capacitance plus the gate
capacitance is thus the smallest. Comp3 is the second least power consuming, because
again the digital compensation devices are smaller than that of Comp1 and Comp2.
Comp1 and Comp2 have comparable power consumptions. Note that by adding digital
offset compensation, the power consumption is at least double to that of core comparator.
69
0.8 1 1.2 1.4 1.6 1.8
50
100
150
200
250
300
Input Vcm (V)
P
o
w
e
r
(
u
W
)
Power Consumption with Digital Compensation Off
CoreComp
Comp1
Comp2
Comp3
Comp4
Figure 39 Power Consumptions with Digital Offset Compensation Off
0.8 1 1.2 1.4 1.6 1.8
50
100
150
200
250
300
350
Vcm (V)
P
o
w
e
r
(
u
W
)
Power Consumption with Digital Compensation On
CoreComp
Comp1
Comp2
Comp3
Comp4
Figure 40 Power Consumptions with Digital Offset Compensation On
70
By noticing the increase in power consumption when digital compensation is on,
we again suggest to control the left part and right part of digital compensation separately.
As we explained at the end of speed section, by turning on only left or right devices, we
halved the extra parasitic capacitance, and thus the power consumption can be greatly
reduced.
3.6.2 Power of Clocking
Power of clocking is mainly due to charging and discharging the clock load
capacitance. Thus, to find the power consumed on driving the clock, we can simply find
the clock load capacitance. Table 10 shows the clock load capacitance of each
comparator, and the corresponding clocking power. Power calculation is based on 1.8V
supply operating at 1.5GHz. It is obvious that Comp1, Comp2, and Comp4 have the same
clock load capacitance. Comp3 has large clock load capacitance because of its digital
offset compensation structure.
Core Comp Comp1 Comp2 Comp3 Comp4
Clock Load
Capacitance
10.9fF 12.5fF 12.5fF 37.6fF 12.5fF
Clocking
Power
52.9µW 60.8µW 60.8µW 183µW 60.8µW
Table 10 Power of Clocking
71
3.6.3 Total Power
The total power is calculated by summing the power of comparator itself and
power of clocking. Figure 41 shows the total power consumption when digital
compensation is off; Figure 42 shows the total power consumption when digital
compensation is on. Again, operating condition is 1.8V supply, 1.5GHz clock. Since
clocking power of Comp3 is much larger than others, Comp3 becomes the most power
consuming comparator among four architectures. Comp2 is the least power consuming
when digital compensation is off, and Comp4 is the least power consuming when digital
compensation is on. Overall, digital offset compensation increases the power
consumption by 60% to 160%, greatly depending on the choice of architecture.
0.8 1 1.2 1.4 1.6 1.8
100
150
200
250
300
350
Input Vcm (V)
T
o
t
a
l
p
o
w
e
r
(
u
W
)
Total Power Consumption with Digital Compensation Off
CoreComp
Comp1
Comp2
Comp3
Comp4
Figure 41 Total Power Consumption with Digital Compensation Off
72
0.8 1 1.2 1.4 1.6 1.8
100
150
200
250
300
350
400
450
500
Vcm (V)
T
o
t
a
l
P
o
w
e
r
(
u
W
)
Total Power Consumption with Digital Compensation On
CoreComp
Comp1
Comp2
Comp3
Comp4
Figure 42 Total Power Consumption with Digital Compensation On
73
3.7 Quick Summary of Comparison
In summary, we have compared the performances of 4 digital offset compensation
architectures. Offset compensation ability, supply sensitivity, speed, input capacitance,
and power have been compared in detail. Table 11 shows the summary of the
performances. Comp1 and Comp2 are suitable in high accuracy applications, while
Comp4 is suitable in low power system.
Performance Core Comp Comp1 Comp2 Comp3 Comp4
Worstcase
Offset
60 – 140mV 8 – 14mV 8 – 13mV 7 – 65mV 9 – 21mV
Effective
number of bit
correction
N/A 3.5bit 3.5bit 3bit 3.2bit
Worstcase
Supply
Sensitivity on
Offset*
10mV 13mV 18mV 22mV 16mV
Sampling
Rate
(%Reduction)
2.84GHz 2.10GHz
(–26%)
2.19GHz
(–23%)
2.38GHz
(–16%)
2.15GHz
(–24%)
Input
Capacitance
1fF 1fF 1fF 1fF 1fF
Power**
(% Increase)
142–175µW 213–390µW
(50–120%)
238–400µW
(67–129%)
328–460µW
(130–160%)
168–280µW
(18–60%)
*Worstcase supply sensitivity (±10% change in supply) measured at V
CM
= 1.2V
** Power consumption in V
CM
range 0.8V ≤ V
CM
≤ 1.6V
Table 11 Performances Rating of Comparators
74
Chapter 4 Circuit Performance
All four architectures have been fabricated in 0.18µm 1.8V CMOS technology. In
the test chip, each architecture is duplicated 20 times. As a result, there are 20 Comp1, 20
Comp2, 20 Comp3, and 20 Comp4 in the same chip. Thus, we are able to collect
statistical data from the chip. Since this project emphasizes on offset compensation, only
offset of the comparators have been measured.
4.1 Accuracy
In each of the following subsections, we will present the measurements of internal
offset, digital offset, linearity of digital offset, and worstcase overall offset respectively.
4.1.1 Measured Internal Offset Due to Device Mismatches
As you can see from the schematics, Comp1, Comp2, and Comp4 share the same
core comparator, while Comp3 has split tail current architecture. Therefore, Comp1,
Comp2, and Comp4 have similar internal offset, while Comp3 has larger internal offset.
75
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−200
−150
−100
−50
0
50
100
150
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp1 Internal Offset measurements
Data Points
Average
+/− 3 sigma
Theoretical bounds
Figure 43 Measured Internal Offset of Comp1
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−150
−100
−50
0
50
100
150
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp2 Internal Offset measurements
Data Points
Average
+/− 3 sigma
Theoretical bounds
Figure 44 Measured Internal Offset of Comp2
76
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−400
−300
−200
−100
0
100
200
300
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp3 Internal Offset measurements
Data Points
Average
+/− 3 sigma
Theoretical bounds
Figure 45 Measured Internal Offset of Comp3
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−250
−200
−150
−100
−50
0
50
100
150
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp4 Internal Offset measurements
Data Points
Average
+/− 3 sigma
Theoretical bounds
Figure 46 Measured Internal Offset of Comp4
77
In the figures above, “Data points” represent the offset of each duplicated
comparator. Thus, there should be 20 data points at the same V
CM
. “Average” represents
the average value of all data points at that V
CM
. “+/− 3sigma” is the ±3 × (standard
deviation σ) calculated statistically from data points. “Theoretical bounds” is ±3 ×
(standard deviation σ) obtained from simulations. In all four figures above, we can see
that the internal offset tends to negative. This negative trend is mainly due to layout
asymmetry of the comparator itself. If you neglect the offset due to layout asymmetry, the
range of “+/− 3sigma,” which is obtained from real circuits, is closed to the range of
“Theoretical bounds,” which are obtained from simulations. This verifies that the analysis
in chapter 2 accurately predicts the offset of the comparator.
4.1.2 Measured Digital Offset Compensation
Since there is inaccuracy in the simulation model, the performance of the real
circuit implementation deviates from the simulations presented in Chapter 3. The errors
on estimating parasitic capacitance in simulations are typically high. The incorrect
parasitic capacitance model will lead to large performance impact in digital offset
compensation. This will be discussed in detail for each comparator.
Figure 47 shows the measured digital offset of Comp1. It is obvious that the
correction range obtained in measurements is larger than that in simulations. We found
that the simulations overestimated the parasitic capacitance. As a result, all transistors in
real implementation have more drive strength than those in simulations. Consequently,
the digital offset magnitude of Comp1 in real circuits, which is shown in Figure 47,
78
covers a larger range than shown in the simulations of Figure 24. In addition to error in
correction range, simulated digital offsets increase fairly linearly with V
CM
, but measured
digital offsets are fairly constant over wide range of V
CM
. The intuitive understanding on
the structure of Comp1 actually predicts that the digital offset is quite insensitive to the
change in V
CM
. Comp1 stacks 2 transistors in series as if degenerating the top transistor
M
CM16
by the bottom transistor M
OS16
(see schematic Figure 20). As a result, the current
flowing through each branch is regulated by the small feedback mechanism. The created
offset is also regulated, and thus, the offset magnitude does not change rapidly over wide
range of V
CM
. This effect clearly shows up in Figure 47.
In addition, the drawback of Comp1 is its nonlinearly scaling devices on digital
offset compensation. It is expected that the LSB, D
1
has different characteristic from
other bits do. Figure 47 shows that the offsets created by LSB, corresponding to all odd
digital levels, approach more to a constant than the offsets created by 2
nd
LSB,
corresponding to all even digital levels. It is because LSB is created by M
CM1
and M
OS1AB
,
which form larger degeneration; thus the current flowing through the LSB branch is less
sensitive to V
CM
. The different behaviors between the 1
st
LSB and the 2
nd
LSB degrade
the linearity of the digital offset compensation. The linearity will be discussed in next
section.
79
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−200
−150
−100
−50
0
50
100
150
200
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp1 Measured Digital OS compensations
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
Figure 47 Measured Digital Offset of Comp1
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−400
−300
−200
−100
0
100
200
300
400
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp2 Measured Digital OS compensations
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
−8
Figure 48 Measured Digital Offset of Comp2
80
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−600
−400
−200
0
200
400
600
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp3 Measured Digital OS compensations
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
−8
Figure 49 Measured Digital Offset of Comp3
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−40
−30
−20
−10
0
10
20
30
40
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp4 Measured Digital OS compensations
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
−8
Figure 50 Measured Digital Offset of Comp4
81
Figure 48 shows the measured digital offset of Comp2. The difference between
Comp1 and Comp2 is especially clear with measurements. Comp2 creates offset similar
to a β mismatch of M
1,2
. Notice the similarity of “beta1” in Figure 15 with Figure 48.
Note that simulation shown in Figure 25 incorrectly predicts that digital offset stays
constant in high V
CM
. The stronger drive strength in actual devices shows up clearly in
measured digital offset of Comp2 in Figure 48. In high V
CM
, the real measured digital
offset is larger than the simulated digital offset by more than 100%.
Figure 49 shows the measured digital offset of Comp3. The measured circuit
performance of Comp3 deviates the least from simulation results. The digital offset in
real implementation is only slightly larger than that in simulation. The large nonlinearity
also clearly shows up in real circuits.
Figure 50 shows the measured digital offset of Comp4. The inaccurate parasitic
capacitance model affects the performance of Comp4 the most. All capacitances due to
M
C04
are smaller in the fabricated chip; thus, smaller offsets are resulted. In Figure 50,
the maximum digital offset created by Comp4 is only about 40mV, while simulation
expects the maximum digital offset of more than 200mV. Because of the small magnitude
of digital offset, the finite precision of the equipments leads to difficulties in offset
measurements. Figure 50 shows the measured digital offset of Comp4 with large
measurement uncertainty. By carefully inspecting all 16 digital offset levels, level 3 (3
LSB) and level 4 (4 LSB) cross over with each other. We suspect that the dummy
capacitor M
C0
in Figure 23 does not match with other capacitors in layout. The same
problem occurs in –4 and –5, which is caused by the same transition from 3LSB to 4LSB.
82
4.1.3 Linearity
Linearity will directly affect the effective number of bits correction. DNL of each
comparator is calculated from the digital offset measurements in the previous section, and
the DNL profiles are shown in Figure 51 − Figure 54.
The measured DNL of Comp1 increases to 1 LSB. However, if V
CM
is below 1.4V,
the DNL is less than 0.8 LSB. This suggests that it is better to operate Comp1 at low or
moderate V
CM
. Note that the “zig zag” pattern shows up in measurement as well.
Unlike digital offset measurements, measured DNL of Comp2 is much more
similar to the simulation results. From Figure 52, we confirm that Comp2 has DNL
approximately 0.5 LSB, and is the best among four comparators.
Comp3 has the worst DNL profile, as predicted in simulations. In real circuits, the
worst DNL is almost 1.5 LSB. Simulations can also predict the compression of the step
size of offset compensation. The measured DNL profile of Comp3 is also very similar to
the simulation results.
With a lot of difficulties in precise measurements, the measured DNL profile of
Comp4 is not very meaningful. Thus, we will not have further discussion on this.
83
−8 −6 −4 −2 0 2 4 6 8
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
Digital Level, W
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Comp1 Measured Digital Offset DNL
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
Figure 51 Measured DNL of Comp1
−8 −6 −4 −2 0 2 4 6 8
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
Digital Level, W
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Comp2 Measured Digital Offset DNL
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
Figure 52 Measured DNL of Comp2
84
−8 −6 −4 −2 0 2 4 6 8
−1
−0.5
0
0.5
1
1.5
Digital Level, W
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Comp3 Measured Digital Offset DNL
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
Figure 53 Measured DNL of Comp3
−8 −6 −4 −2 0 2 4 6 8
−2
−1.5
−1
−0.5
0
0.5
1
1.5
Digital Level, W
O
f
f
s
e
t
D
N
L
(
L
S
B
)
Comp4 Measured Digital Offset DNL
vcm=0.8
vcm=1.0
vcm=1.2
vcm=1.4
vcm=1.6
Figure 54 Measured DNL of Comp4
85
4.1.4 Worstcase Overall Offset
When four comparators have similar range of digital offset compensation, DNL
and worstcase overall offset give the same results. However, since four comparators in
this test chip have different ranges of corrections, worstcase overall offset is eventually
the most important metric and it tells which comparator has higher accuracy.
In Figure 55 – Figure 58, “Worstcase offset” is the worst possible offset of a
comparator, and it is calculated by finding the biggest separation between two digital
levels in measured digital offset from Figure 47 – Figure 50. “Data Points” are the actual
offset of the duplicated comparators on chip after digital offset compensation. As a result,
all “Data Points” are bounded by the “Worstcase offset.”
In Figure 58, there are only 3 “Data Points” for offset of Comp4, because Comp4
has very limited correction range, and most duplicated comparators have offset larger
than its correction range. We can find only 3 comparators that have small enough offset
to compensate.
Finally, Figure 59 shows the worstcase offsets of all four comparators in one plot.
Since Comp4 has too narrow correction range, we will neglect Comp4. Comp1 provides
lowest offset in this test chip. Because of the inaccurate capacitance model in simulations,
Comp2 has larger worstcase offset than expected. Comp3 still performs the worst in
offset compensation.
86
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−25
−20
−15
−10
−5
0
5
10
15
20
25
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp1 Measured Offset after Digital compensation
Worst−case Offset
Data Points
Figure 55 Measured Offset of Comp1 after Digital Compensation
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−40
−30
−20
−10
0
10
20
30
40
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp2 Measured Offset after Digital compensation
Worst−case Offset
Data Points
Figure 56 Measured Offset of Comp2 after Digital Compensation
87
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−80
−60
−40
−20
0
20
40
60
80
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp3 Measured Offset after Digital compensation
Worst−case Offset
Data Points
Figure 57 Measured Offset of Comp3 after Digital Compensation
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
−8
−6
−4
−2
0
2
4
6
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Comp4 Measured Offset after Digital compensation
Worst−case Offset
Data Points
Figure 58 Measured Offset of Comp4 after Digital Compensation
88
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
0
10
20
30
40
50
60
70
80
Vcm (V)
M
e
a
s
u
r
e
d
O
f
f
s
e
t
,
(
m
V
,
d
i
f
f
)
Measured Worst−case Overall offset
Comp1
Comp2
Comp3
Comp4
Figure 59 Comparison on worstcase offset
89
Chapter 5 Applications of Comparators
The comparators designed in this project are optimized for high order parallelism.
For example, flash ADC or oversampler usually require a large number of comparators
in parallel in the first stage. Thus, the comparators should have small input capacitance,
low power consumption. For ADC design, comparator must fulfill the accuracy
requirement as well. In the coming section, a brief ADC design example is shown for
illustrating the application of comparators with digital offset compensation.
5.1 Application of Comparators on Multiphase Flash ADC
Figure 60 Block Diagram of Multiphase Flash ADC
To illustrate the application of comparators on Flash ADC architecture, we are
going to design a N bit multiphase flash ADC. In a singlephase flash ADC, we need to
•
•
φ
1
Nbit
ADC
N
φ
2
Nbit
ADC
N
φ
P
Nbit
ADC
N
V
in
V
FS
•
•
COMP
COMP
COMP
COMP
V
in
clk
2
N
90
place 2
N
comparators in parallel in the first stage. To push the speed performance, we
place, for example, p singlephase flash ADC in parallel. Each flash ADC is triggered by
different phase, φ
1
, φ
2
,…φ
P
. The block diagram is shown in Figure 60.
First of all, we need to design a comparator with required accuracy. Since we
know we are going to place a large number of comparators in parallel in the first stage,
we use small transistor size for input device M
1,2
. With a designed input device size, say
minimum size or 2× minimum size, we know the maximum offsets due to device
mismatch by using techniques developed in chapter 2. By applying digital offset
compensation, we can reduce the input referred offset to fulfill the required accuracy. In
short,
s correction bits of number Effective
V
V
mismatch OS
overall OS
,
,
=
Effective number of bits corrections depends on DNL of offset compensation, which is
explained in chapter 3. After number of bits corrections on offset is designed, we can
design appropriate reset devices. The design of a comparator ends at this point. We can
then obtain the performance metrics of the comparator, especially speed of comparator
f
comp
, by simulations.
After the design of the comparator is done, we can obtain the sampling frequency
by modeling the sampling action as a simple R
in
C
in
circuit, where R
in
= 25Ω for end
termination configuration, and C
in
is the sum of capacitances due to pads, channel, and
input capacitance of comparators. Since there are 2
N
comparators in a singlephase flash
ADC and there are p flash ADC in parallel, we have total (2
N
)p comparators connected to
91
the input. Thus,
Equation 16 C
in,total
= C
pad
+ (2
N
)(p)C
in,comp
,
where C
pad
includes any fixed capacitances due to pads, channels, etc., and C
in,comp
is the
input capacitance of the comparator. For proper operation, we need to let input voltage
settle within 0.5 LSB =
V
FS
2
N+1 , where V
FS
is fullscale voltage of ADC. The settling time,
which is equal to the sampling time T
SAMP
, can be calculated by
( )
in in SAMP
N
C R
T
C R N T e
in in
SAMP
1 2 ln
2
1
1
+ = ⇒ ≤
+
−
As a result, sampling frequency is
Equation 17
( )
in in SAMP
SAMP
C R N T
f
1 2 ln
1 1
+
= =
Meanwhile, comparators can only operate up to its maximum speed, f
comp
. Thus the
maximum operating frequency of pphase flash ADC, f
ADC
, = p×f
comp
. Both f
ADC
and f
SAMP
depend on p, and they set the speed bounds of the ADC, as shown in Figure 61.
When p < p
o
, f
ADC
limits the speed of the ADC; when p > p
o
, f
SAMP
limits the
maximum speed. The optimum speed is where f
ADC
= f
SAMP
. This sets a quadratic equation
for p.
( )
in in
comp SAMP ADC
C R N
pf f f
1 2 ln
1
+
= ⇒ =
Equation 18 ( ) ( )
( )
0
1 2 ln
1
2
2
,
=
+
− +
comp in
pad comp in
N
f R N
p C p C
92
Speed of 6bit pphase Flash ADC
po
0
2
4
6
8
10
12
14
0 2 4 6
Number of parallel ADC, p
S
p
e
e
d
(
G
S
/
s
e
c
)
fadc
fsamp
Figure 61 Speed of 6bit pphase Flash ADC
Hence, we can always solve for Equation 18 to obtain the optimum speed of a pphase
flash ADC. The optimum speed can tell us the fundamental speed limit of a pphase flash
ADC architecture. This is just a simple example, as we can still increase the performance
by using a multistage ADC to decrease the total input capacitance, or by using distributed
capacitance technique to increase the input sampling bandwidth. More design issues on
those techniques seem out of scope of this paper.
93
Chapter 6 Conclusion
This project can be mainly divided into 3 big sections. The 3 sections are
characterization of core comparator (Chapter 2), comparison of comparators with digital
offset compensation (Chapter 3), and chip performance (Chapter 4).
In the first section, (Chapter 2), core comparator is characterized. The
performance metrics of a comparator are input referred offset, supply sensitivity, speed,
input capacitance, and power. A set of formulas is developed to calculate input referred
offset, and we identify the 6 different sources that contribute to offsets, and we
understand how each source varies with V
CM
. We are able to roughly estimate the supply
sensitivity on offset, so we know the fundamental limit of the accuracy of a comparator.
We know how to size the transistors to achieve higher speed on both evaluation and reset.
In addition, this architecture has small input capacitance and power consumption [2].
With these metrics, we can compare comparators with different architectures,
comparators with different offset compensation, and the tradeoffs of using digital offset
compensation.
In the second section (Chapter 3), we compare four comparators with different
digital offset compensation. Based on the performance metrics developed in chapter 2,
we created Table 11 to summarize the comparison of digital offset compensation. Comp2
has the best offset compensation ability because of its linearity, while Comp4 is a good
alternative because of its low power consumption. In general, digital offset compensation
can reduce the input referred offset from 140mV to 13mV. Effective number of bits
94
correction can be ranged from 3 – 3.5 bit from a 4bit architecture. Input capacitance is
less than 1fF. By adding digital offset compensation, the sampling rate is only reduced by
15 – 25%, and power consumption increases by 60 – 160%.
In the third section (Chapter 4), all four comparators are implemented in 0.18µm,
1.8V CMOS technology. Since this project emphasizes on offset compensation, only
offset measurements are performed. We verified that the analysis for internal offset could
predict the offset of a comparator. We found that simulations overestimated the parasitic
capacitance; thus, transistors have more drive strength. As a result, Comp1, Comp2, and
Comp3 have offset correction range larger than that obtained from simulations; however,
Comp4 has offset correction range less than expected. In addition, Comp2 gives the best
DNL (0.5LSB), and Comp3 gives the worst DNL (1.5LSB).
In the end of this project, we also give a simple example to illustrate how to apply
comparators with digital offset compensation in real implementation. We have developed
a method to design transistor size of comparators and number of bit corrections for
comparators. Moreover, we are able to find the optimum speed of a pphase flash ADC.
With this example, we showed that comparators with digital offset compensation have
high potential on applications with high order parallelism.
95
Reference
[1] Pelgrom, M.J.M., Duinmaijer, A.C.J. and Welbers, A.P.G. “Matching properties of
MOS transistors,” IEEE Journal of SolidState Circuits, vol. SC24, pp.14331440, 1989.
[2] Razavi, B.; Wooley, B.A., "A 12b 5Msample/s twostep CMOS A/D converter,"
IEEE Journal of SolidState Circuits, vol.27, (no.12), Dec. 1992. p.166778.
[3] Dobberpuhl, D.W., "Circuits and technology for Digital's StrongARM and ALPHA
microprocessors [CMOS technology]," Seventeenth Conference on Advanced Research
in VLSI, IEEE Comput. Soc, 1997. p.211. ix+322 pp.
[4] Razavi, B., “Principles of Data Conversion system Design,” IEEE Press, pp. 17781,
1995.
[5] Sakurai, T., "Optimization of CMOS arbiter and synchronizer circuits with
submicrometer MOSFETs," IEEE Journal of SolidState Circuits, vol.23, (no.4), Aug.
1988. p.9016.
[6] Ellersick, W.; Yang, C.K. K.; Horowitz, M.; Dally, W., "GAD: A 12GS/s CMOS 4
bit A/D converter for an equalized multilevel link," 1999 Symposium on VLSI Circuits
Digest of Papers, June 1999, pp. 4952.
[7] Weinlader, D.; Ho, R.; Yang, C.K. K.; Horowitz, M., "An eight channel 36
GSample/s CMOS timing analyzer," 2000 ISSCC Digest of Technical Papers, Feb 2000,
pp. 1701.
[8] Lee, M.J.E.; Dally, W.; Chiang, P., "A 90 mW 4 Gb/s equalized I/O circuit with
input offset cancellation," 2000 ISSCC Digest of Technical Papers, Feb 2000, pp. 2523.
The thesis of Koon Lun Jackie Wong is approved.
________________________________ Behzad Razavi
________________________________ Ingrid Verbauwhede
________________________________ C.K. Ken Yang, Committee Chair
University of California, Los Angeles
2002
ii
Table of Contents COMPARISON OF DIGITAL OFFSET COMPENSATION IN COMPARATORS1 CHAPTER 1 INTRODUCTION ..................................................................................... 1 1.1 GENERAL PURPOSES OF COMPARATORS ..................................................................... 1 1.2 REQUIREMENTS ON COMPARATORS............................................................................ 1 1.3 INTRODUCTION TO OFFSET COMPENSATION ............................................................... 6 CHAPTER 2 CORE COMPARATOR DESIGN........................................................... 9 2.1 ACCURACY ............................................................................................................... 10 2.1.1 Device Mismatch in Differential Pair .............................................................. 10 2.1.2 Total Input Referred Offset of Comparator...................................................... 12 2.2 SUPPLY SENSITIVITY ................................................................................................ 24 2.2.1 Supply Sensitivity due to each transistor.......................................................... 24 2.2.2 Overall Supply Sensitivity of Core Comparator .............................................. 26 2.3 SPEED ....................................................................................................................... 27 2.3.1 Evaluation Phase.............................................................................................. 27 2.3.2 Reset Phase ...................................................................................................... 34 2.4 INPUT CAPACITANCE ................................................................................................ 40 2.5 POWER CONSUMPTION ............................................................................................. 41 2.6 DESIGN OF NEXT STAGE (SR LATCH)....................................................................... 41 CHAPTER 3 DIGITAL OFFSET COMPENSATION ............................................... 43 3.1 FOUR DIFFERENT ARCHITECTURES .......................................................................... 44 3.1.1 Architecture Comp1 ......................................................................................... 44 3.1.2 Architecture Comp2 ......................................................................................... 45 3.1.3 Architecture Comp3 ......................................................................................... 46 3.1.4 Architecture Comp4 ......................................................................................... 47 3.2 CHARACTERISTICS OF DIGITAL OFFSET COMPENSATION.......................................... 48 3.2.1 Offset Magnitude of Digital Compensation ..................................................... 48 3.2.2 Linearity of Digital Offset Compensation ........................................................ 52 3.2.3 WorstCase Overall Offset after compensation ............................................... 55 3.3 SUPPLY SENSITIVITY ................................................................................................ 56 3.4 SPEED ....................................................................................................................... 59 3.4.1 Comparison on Speed of Different Architectures ............................................ 60 3.4.2 Speed Penalty of Digital Offset Compensation ................................................ 63 3.4.3 Comparison on Linear and Nonlinear scaling ............................................... 65 3.5 INPUT CAPACITANCE ................................................................................................ 67 3.6 POWER CONSUMPTION ............................................................................................. 67 3.6.1 Power of Comparators ..................................................................................... 67 3.6.2 Power of Clocking............................................................................................ 70 iii
3.6.3 Total Power ...................................................................................................... 71 3.7 QUICK SUMMARY OF COMPARISON .......................................................................... 73 CHAPTER 4 CIRCUIT PERFORMANCE ................................................................. 74 4.1 ACCURACY ............................................................................................................... 74 4.1.1 Measured Internal Offset Due to Device Mismatches ..................................... 74 4.1.2 Measured Digital Offset Compensation........................................................... 77 4.1.3 Linearity ........................................................................................................... 82 4.1.4 Worstcase Overall Offset ................................................................................ 85 CHAPTER 5 APPLICATIONS OF COMPARATORS.............................................. 89 5.1 APPLICATION OF COMPARATORS ON MULTIPHASE FLASH ADC .............................. 89 CHAPTER 6 CONCLUSION ........................................................................................ 93
iv
List of Figures Figure 1 Ideal input/output characteristic of a comparator ................................................. 2 Figure 2 Positive feedback realization ................................................................................ 2 Figure 3 Block diagram of flash ADC architecture ............................................................ 4 Figure 4 Schematic of (a) an amplifier (b) a comparator.................................................... 5 Figure 5 A comparator with analog offset compensation ................................................... 6 Figure 6 Timing Diagrams of φ1, φ2, φ3, VX, and VY ............................................................ 7 Figure 7 Core Comparator................................................................................................. 10 Figure 8 Model of Device Mismatch in Differential Pair ................................................. 12 Figure 9 Core comparator model for offset calculations................................................... 12 Figure 10 Current factor mismatch of M1 ......................................................................... 14 Figure 11 common mode analyses of M1,2 ........................................................................ 15 Figure 12 Threshold mismatch of M3 ............................................................................... 17 Figure 13 common mode analyses for M3 ........................................................................ 18 Figure 14 Current factor mismatch of M3 ......................................................................... 20 Figure 15 Input referred offset voltage due to each transistor .......................................... 23 Figure 16 Supply Sensitivity on Offset due to ∆β1, ∆β2, and ∆Vth2 .................................. 25 Figure 17 Overall Supply Sensitivity on Offset ................................................................ 27 Figure 18 Reset Response of sim2, sim3, sim10, and sim11 ............................................ 38 Figure 19 Simplified SR Latch.......................................................................................... 42 Figure 20 Schematic of Comp1......................................................................................... 44 Figure 21 Schematic of Comp2......................................................................................... 45 Figure 22 Schematic of Comp3......................................................................................... 46 Figure 23 Schematic of Comp4......................................................................................... 47 Figure 24 Digital Offset of Comp1 ................................................................................... 50 Figure 25 Digital Offset of Comp2 ................................................................................... 50 Figure 26 Digital Offset of Comp3 ................................................................................... 51 Figure 27 Digital Offset of Comp4 ................................................................................... 51 Figure 28 Digital Offset DNL of Comp1 .......................................................................... 53 Figure 29 Digital Offset DNL of Comp2 .......................................................................... 53 Figure 30 Digital Offset DNL of Comp3 .......................................................................... 54 Figure 31 Digital Offset DNL of Comp4 .......................................................................... 54 Figure 32 Worstcase overall offset .................................................................................. 56 Figure 33 Supply Sensitivity on Offset of Comp1............................................................ 57 Figure 34 Supply Sensitivity on Offset of Comp2............................................................ 57 Figure 35 Supply Sensitivity on Offset of Comp3............................................................ 57 Figure 36 Supply Sensitivity on Offset of Comp4............................................................ 58 Figure 37 Illustration of input transconductance loss ....................................................... 63 Figure 38 Schematic of Comp1 with 3bit linear scaling.................................................. 65 Figure 39 Power Consumptions with Digital Offset Compensation Off .......................... 69 Figure 40 Power Consumptions with Digital Offset Compensation On........................... 69 v
Figure 41 Total Power Consumption with Digital Compensation Off ............................. 71 Figure 42 Total Power Consumption with Digital Compensation On .............................. 72 Figure 43 Measured Internal Offset of Comp1 ................................................................. 75 Figure 44 Measured Internal Offset of Comp2 ................................................................. 75 Figure 45 Measured Internal Offset of Comp3 ................................................................. 76 Figure 46 Measured Internal Offset of Comp4 ................................................................. 76 Figure 47 Measured Digital Offset of Comp1 .................................................................. 79 Figure 48 Measured Digital Offset of Comp2 .................................................................. 79 Figure 49 Measured Digital Offset of Comp3 .................................................................. 80 Figure 50 Measured Digital Offset of Comp4 .................................................................. 80 Figure 51 Measured DNL of Comp1 ................................................................................ 83 Figure 52 Measured DNL of Comp2 ................................................................................ 83 Figure 53 Measured DNL of Comp3 ................................................................................ 84 Figure 54 Measured DNL of Comp4 ................................................................................ 84 Figure 55 Measured Offset of Comp1 after Digital Compensation .................................. 86 Figure 56 Measured Offset of Comp2 after Digital Compensation .................................. 86 Figure 57 Measured Offset of Comp3 after Digital Compensation .................................. 87 Figure 58 Measured Offset of Comp4 after Digital Compensation .................................. 87 Figure 59 Comparison on worstcase offset...................................................................... 88 Figure 60 Block Diagram of Multiphase Flash ADC ....................................................... 89 Figure 61 Speed of 6bit pphase Flash ADC ................................................................... 92
List of Tables Table 1 Simulation results on evaluation with varying comparator transistor size .......... 33 Table 2 Simulation results on reset device........................................................................ 37 Table 3 Evaluation and Reset with vary Vcm (see Table 1,Table 2 for term definition) . 39 Table 4 Power Consumption of Core Comparator............................................................ 41 Table 5 Worstcase Supply Sensitivity of Comp1 − Comp4 ............................................ 59 Table 6 Speed Comparisons with Digital Offset Compensation Off ................................ 60 Table 7 Speed Comparisons with Digital Offset Compensation On................................. 61 Table 8 Maximum Sampling rate of different architecture............................................... 62 Table 9 Speed Comparisons on linear and nonlinear scaling of Comp1 ......................... 65 Table 10 Power of Clocking.............................................................................................. 70 Table 11 Performances Rating of Comparators ................................................................ 73
vi
ABSTRACT OF THE THESIS Comparison of Digital Offset Compensation in Comparators by Koon Lun Jackie Wong Master of Science in Electrical Engineering University of California. and low power comparators. 2002 Professor C. four different architectures of digital offset compensation are fabricated in 0. Low input capacitance and low power allow higher order of parallelism.8V CMOS technology. For comparison. vii . Chair Digital offset compensation is an efficient technique for designing high speed. Ken Yang. while digital offset compensation allows high accuracy.K. and a set of performance metrics for a comparator is developed to compare the tradeoffs between these four architectures. low input capacitance. A 4bit digital offset compensation can reduce 140mV input referred offset due to device mismatches to 13mV.18µm 1. Los Angeles. high accuracy.
for instance a latch. Since most IC designs are synchronous system.Comparison of Digital Offset Compensation in Comparators Chapter 1 Introduction 1. A comparator outputs a digital 0 if the signal is below the reference or a digital 1 if the signal is above the reference. wire bond. comparators are used as a storage element.1 General Purposes of Comparators Modern integrated circuits (IC) design almost always involves strong well defined digital signals. high sampling rate. chip package. etc. which are caused by limited bandwidth of transmission line. however. high accuracy. in high performance circuits. a comparator requires high gain. comparators are usually triggered by clock. 1. and low input 1 . Sometimes. Moreover. a comparison with a fixed reference value is performed. incoming data is often analog signals or corrupted digital signals. noise coupling. they are often used as sense amplifiers in SRAM and DRAM. capacitive and inductive effects from the printed circuit board (PCB). low power consumption. Comparators are commonly found in modern IC design. In order to convert the weak corrupted signals to full swing digital signals. since comparators have large voltage gain.2 Requirements on Comparators In applications like flash ADC and oversampled receiver. Clocked comparators are commonly found in AnalogtoDigital Converter (ADC) and based band receivers.
A common clocked architecture that can achieve high sampling rate has two phases of operation: evaluation phase and reset phase. A simple realization of positive feedback system could be two backtoback inverters. In real implementation. In 2 . we require clocked comparator to run at a higher sampling rate as well. As synchronous system is running faster and faster. if the systems are synchronous. The output (V1 – V2) of this circuit increases exponentially with time. An ideal comparator has input/output characteristic as shown in Figure 1. positive feedback is often employed in comparator design. To achieve virtually infinite gain. Vout Vin1 Vout Vin2 Vin1−Vin2 Figure 1 Ideal input/output characteristic of a comparator The first requirement of a comparator is having high gain. as shown in Figure 2. The requirements of comparators are discussed one by one below. V1 V2 Figure 2 Positive feedback realization The second requirement of a comparator is having high sampling rate.capacitance. comparators are required to be triggered by clock. high gain amplifier is used to approximate this input/output characteristic. In addition. This will be discussed in detail in Chapter 2.
Systematic offsets can be minimized by symmetric design and careful layout. Thus. Supply noise does not affect the output directly. and the variance of mismatch is inversely proportional to the area of devices size (W×L) [1]. flicker noise. positive feedback is disabled and the comparator clears its previous sample. because comparator is a fully differential circuit. sampling noise is often negligible even with 3 . Sampling noise is caused by the fast transition of clock from reset phase to evaluation phase. and sampling noise.evaluation phase. offset requirements become more and more difficult to fulfill. The second error that causes inaccuracy is noise. Offsets are often the largest errors in comparator design. Errors that cause inaccuracy usually are offsets. positive feedback is enabled to achieve high gain. Offsets can be classified into systematic and random offsets. In reset phase. and residual value from prior comparison. to reduce random offsets. due to large device mismatches. Fortunately. Thermal noise is white Gaussian noise from resistors and transistors. However. supply noise may momentarily change the input referred offset. The third requirement of a comparator is having high accuracy. However. Noise includes thermal noise. Random offsets are caused by device mismatches in layout. we should make devices bigger. reset must be completed quickly and the positive feedback should be enabled quickly and have short regeneration time constant. for example ½ LSB of an ADC or minimum signal magnitude of a receiver. For fast operation. and thus degrade the accuracy. supply noise. Flicker noise is often referred to 1/f noise of a transistor. as modern CMOS technology scales down for higher switching speeds and higher transistor density. noise.
degrading the comparator accuracy. The power consumption of a comparator must be low because frequently a large number of 1 Analysis of sampling noise is not part of this research. 4 . Since the residual charge depends on the previous sample. The third error that causes inaccuracy is the residual value from prior comparison. VFS Vin COMP COMP COMP DECODER Digital Output N • • COMP clk 2N Figure 3 Block diagram of flash ADC architecture The forth requirement of a comparator is having low power consumption.sampling rates of several GSamples/s1. if the reset is not completed before the next evaluation phase comes. this error is sometimes called InterSymbol Interference (ISI). During reset phase. However. small residual charge on output will get amplified exponentially because of positive feedback. the comparator clears the previous data. The imbalanced output thus creates input referred offset.
As a result. input capacitance is directly proportional to the size of input devices M1. Hence a Nbit flash ADC requires 2N comparators. we should use big input 5 . A block diagram of a simple flash ADC is shown in Figure 3. we should use small input devices M1. However. For a typical amplifier (Figure 4a) and a typical comparator (Figure 4b).comparators operating in parallel are used in a flash ADC architecture or in an oversampled receiver.2. the power consumption of a flash ADC doubles as the number of bits of resolution increases by one. In favor of input capacitance. VDD VDD Vb Vout1 M3 M4 M3 M4 Vout2 M1 M2 Vout1 M5 M1 Rst M2 Vout2 Vin1 Vin2 Vin1 Vin2 (a) (b) Figure 4 Schematic of (a) an amplifier (b) a comparator The last requirement of a comparator is having low input capacitance since low input capacitance limits the input bandwidth. The basic concept of a flash ADC is to use 2N comparators to compare the input signal with reference voltages that are generated by dividing the full scale voltage VFS by 2N resistors. Decoder then converts the comparators output to binary code. in favor of offset. total input capacitance of a Nbit flash ADC is simply 2N × input capacitance of a comparator. Similar to power consumption.2.
Figure 5 shows an example of comparator with analog offset compensation [2]. reset S5 – S7. The comparator has regenerative amplifier M1 – M4.3 Introduction to Offset Compensation The ultimate goal of offset compensation in comparators is to reduce the input referred offset. VDD M3 + M4 − Vout φ2 φ1 X Y Vout φ3 φ1 φ2 + Vin − S1 S3 P C1 S5 M1 S7 M2 S6 C2 + Vref S2 Q S4 Vin − Vref φ1 φ1 Figure 5 A comparator with analog offset compensation Traditionally. φ3.C2. and sampling network S1 – S4 and C1. and it utilizes capacitors to store offsets. VY. φ2. Therefore. 1. Offset compensation can be done in analog method or in digital method. offset compensation is introduced to reduce input referred offset while keeping input devices small. 6 .devices. analog offset compensation is used. shows the timing diagram of φ1. and VX. This contradiction leads to direct tradeoffs between accuracy and input bandwidth.
VY t1 t2 t3 time Figure 6 Timing Diagrams of φ1.where VOS1 is the inputreferred offset without 1 Ad g mP R7 − 1 2 offset compensation. Ad is the differential voltage gain form the gates of M1 and M2 to their drains.2. gmN and gmP are the NMOS and PMOS transconductance respectively. φ1 = H. S1 and S2 turn on to track the inputs. 3) At t2. Meanwhile.2. and VY The operation of this comparator is the following: 1) The comparator is in reset phase. S7 turns off. 4) At t3. φ3 switches to low. and ∆V is the offset due to charge injection mismatch between S5 and S6. In this example. φ2 switches to high.φ1 φ2 φ3 VX. VX. inputs see C1. S3 – S6 turn off. and regeneration starts. S3 – S7 are on. φ2. During tracking mode in step 3. and the offset of the comparator is stored in C1 and C2. φ3. which results a capacitance as small as gate capacitance of M1. offset of the comparator is given in [2]: VOS = VOS 1 g mN R7 + ∆V . 2) At t1. Nodes P and Q are charged to +Vref and –Vref respectively. One potential problem for this architecture is that it may 7 . and R7 is the smallsignal onresistance of S7. φ2 = L. so reset ends. φ1 switches to low. Ad = . φ3 = H. we decouple the relationship between input capacitance and offsets.2 in series with gates of M1.
Chapter 2 begins by discussing the design issues of a core comparator. and measured results will be given in chapter 4. so the comparator is in closed loop in around half a cycle.2 to reduce the charge injection mismatch between S5 and S6. This project focuses on digital offset compensation techniques and how they affect the other requirements of gain. Large C1 and C2 increase the settling time during reset and thus slow down the operating frequency. 8 . offsets of a comparator can be tuned by changing the digital inputs. A test chip is fabricated in 0. Generally analog offset compensation requires a capacitor to store the offset in every cycle.18um CMOS technology. Four different digital offset compensation architectures are compared. etc. Hence. the comparator can remain in open loop most of the time. Comparisons on digital offset compensation in chapter 3 will be based on performance parameters and terminology presented in chapter 2. sampling rate. Offsets are then stored in static memory when the system is initialized. The maximum speed of a comparator is eventually limited by the closed loop response. This restriction is much more relaxed in digital offset compensation. Applications of comparators will be discussed in chapter 5. In digital offset compensation. and thus its inherent maximum speed can possibly be achieved. This core comparator will also be the baseline to which each of compensation technique is compared for the penalty of inserting digital compensation.require large C1.
evaluation phase and reset phase. and the input devices M1.2 imbalances the backtoback inverters. which receives the output of comparator and provides constant logical output over one cycle. This comparator has two operation modes. supply sensitivity. we chose the comparator as shown in Figure 7 for its power efficiency [3].Chapter 2 Core Comparator Design This project starts with a basic design of comparators. so the previous data is cleared. will be given at the end of this chapter. For each compensation architecture. Mclk turns off and all RST16 turn on. While there are many architectures. speed. At this time. Four digital offset compensation techniques are explored based on the same basic comparator structure. A brief discussion on SR latch. Then we can examine not only tradeoffs among different compensation architectures but also tradeoffs between with and without digital offset compensation.2 sense the differential input. Current source Mclk turns on. In evaluation phase. we base our comparison on the same set of performance metric: accuracy. Vout2 is then regenerated to full swing. The differential current of M1. The imbalance charge on Vout1. the comparator goes back to initial state and is ready to amplify the signal when evaluation phase comes again. In reset phase. This chapter looks at each of these metrics for the core comparator. clk is logical high. which form a positive feedback system. 9 . The reset devices RST16 eliminate all imbalance charge. and power. input capacitance.
Any input offset voltage in comparator will directly add on the signal. we will describe the model for device mismatch in differential pair and total input referred offset of the comparator. Random offset arises if there are device mismatches. Offsets can be systematic or random. 2. 10 . the accuracy of the comparator will be decreased. Systematic offset can be minimized by differentially symmetric design and careful layout. In this section.1.1 Device Mismatch in Differential Pair Matching properties of CMOS transistor are categorized into threshold mismatch.1 Accuracy A very important requirement of a comparator is small input referred offset voltage.VDD clk RST3 4 2 M5 4 2 RST1 4 2 clk RST2 4 2 M6 4 2 RST4 4 2 clk RST5 Vout1 M3 4 2 invbot1 Vin1 M1 8 2 RST6 4 2 Vout2 M4 4 2 4 2 invbot2 M2 8 2 Vin2 clk Mclk 16 2 Figure 7 Core Comparator 2. as a result.
β 11 .96µm/0. Note that effective channel length for the drawn length of 0. according to [1]. Adapting to this methodology and assuming worstcase conditions. and current factor mismatch as error in channel width. oxide thickness is around 4nm. Aβ = 1%µm. In our comparator design.24µm is 0.18µm technology. ∆β. This simple model is illustrated in Figure 8.62mV and 2 σ(β) β = 2. and current factor mismatch. σ 2 (Vth ) = 2 AVth WLeff Aβ σ 2 (β ) = . drawn size of input transistor is W/L = 8λ/2λ = 0. 2 WLeff β where σ(Vth) and σ(β) are standard deviation of ∆Vth and ∆β respectively. W = 6 σ(β) .18µm. The magnitude of these two quantities can be approximated for a give gate oxide thickness and transistor size. For instance. It is found that AVth = 4mVµm. The standard deviation of the random mismatches can be approximated by [1]. AVth2 and Aβ2 are area proportionality constant which could be found from a lookup graph for a given oxide thickness.∆Vth. we will model the threshold mismatch as an ideal voltage source on transistor gate with ∆W magnitude ∆Vth = 6σ(Vth).24µm.41%. in 0. σ(Vth) = 9.
all reset devices RST16 are not shown. we can replace all pairs in our core comparator with this model to find the total input referred offset. the placements of the voltage sources and scaled transistors are specially chosen. and simulation 12 . For clarity. As shown in Figure 8. In this section.1. In order to obtain the worstcase offset. I will discuss the affects of each offset source carefully.2 Total Input Referred Offset of Comparator With a mismatch model for a differential pair. VDD M5 W36 L (OS)M6 W36 L Vout1 Vout2 M3(OS) W36 L invbot1 M1(OS) W12 L Mclk Wclk L M4 W36 L invbot2 M2 W12 L Vin1 Vin2 clk Figure 9 Core comparator model for offset calculations The mismatches of three differential pairs contribute offset of the comparator. transistors labeled with “OS” are replaced by the mismatch model.Vin1 +− ∆Vth W−∆W L W L Vin2 Figure 8 Model of Device Mismatch in Differential Pair 2.
∆β1: ∆β1 is modeled as a channel width mismatch ∆W.results are presented at the end of this section to confirm the theoretical results. Offset due to current factor mismatch of M1. Offset due to threshold mismatch of M1. the input referred offset voltage due to threshold mismatch of M1 is just ∆Vth1 itself. ∆Vth1: ∆Vth1 is modeled as a voltage source on the gate of transistor M1. This magnitude is always constant under any bias conditions. ∆β ∆W = W To calculate the β input referred offset due to ∆W. and then compare the current with that of generated by equivalent ideal voltage source at the input.e. Since M1 is the input device of the comparator. 13 . as illustrated in Figure 10a. I will calculate the differential current that ∆W generates. i. as shown in Figure 10b.
2 are in saturation because in the beginning of evaluation mode node invbot1. Vds. However. we have: idiff = g m1 ∆Veq . Mclk is in triode region because Vgs. due to ∆β1 = 1 ∆W (V gs1 − Vth ) 2 W 14 . invbot2 are precharged to VDD. which could be quite low.VDD M5 M6 M5 VDD M6 M3 invbot1 I1 M1(OS) W−∆W L Mclk Wclk L M4 I2 M2 W L invbot2 invbot1 M3 I1 M1 W L Mclk Wclk L M4 I2 M2 W L invbot2 Vin1 Vin2 Vin1 +− Vin2 ∆Veq clk clk (a) Figure 10 Current factor mismatch of M1 (b) Before analyzing two configurations. Analyzing Figure 10a.2. it is important to know that transistors M1. we could find: 1 1 ∆W W − ∆W 2 2 µ n C ox (V gs1 − Vth ) = k n1 1 + (V gs1 − Vth ) 2 L 2 W 1 1 W I 2 = µ n C ox (V gs1 − Vth ) 2 = k n1 (V gs1 − Vth ) 2 2 2 L I1 = idiff = 1 ∆W 2 k n1 (V gs1 − Vth ) 2 W From Figure 10b. where g m1 = k n1 (V gs1 − Vth ) Equation 1 ⇒ ∆Veq .Mclk = Vcm − Vgs1.Mclk = VDD.
2 (b) If we look at only common mode voltage. VDD M5 M6 VDD M56 M3 invbot1 M4 invbot2 invbot12 M34 I M12 2W12 L + Vds. Hence we can write: Vcm − Vgs1 1 V I = 2 k n1 (Vgs1 − Vth ) 2 = ds . so it is modeled as a resistor.clk (VDD − Vth ) + Vgs1 = W12 (Vgs1 − Vth ) 2 Wclk (VDD − Vth ) + Vgs1 15 . which could be determined and controlled easily. it is desirable to relate Vgs1 with input Vcm. Thus. circuit in Figure 11a can be transformed to Figure 11b.clk = Rclk 2 Rclk Vcm = Rclk k n1 (Vgs1 − Vth ) + Vgs1 = 2 k n1 (Vgs1 − Vth ) 2 k n . and M1. the input differential pair can be combined into a single transistor twice as wide as original.2 are in saturation because their drains are closed to VDD at the beginning of evaluation mode. Thus. Mclk is in triode region. this gives no insight on how it behaves for a given input common mode voltage.clk _ Vcm M1 W12 L Mclk Wclk L M2 W12 L Vcm Vcm clk Rclk (a) Figure 11 common mode analyses of M1.Although this is a valid equation.
and M5. ∆Vth2 influences the differential current and thus creates offset. Here. ∆Vth2 does not create any offset at the beginning of evaluation phase. ∆Veq .2 continue to drop and input devices M1. 16 . thus. This assumption is reasonable because by the time that M5.2 will drop from VDD. By the time that invbot1. I assume that out1. M14 are still in saturation.4 act as cascode devices. out2 are still closed to VDD. the signal is amplified. As invbot1. M3. ∆Vth2: At the beginning of evaluation phase. However.2 enter triode region. invbot1.6 are on. and hence the influence of ∆Vth2 becomes relatively small.4 will turn on.2 drops to VDD −Vthn. and thus. Offset due to threshold mismatch of M3. due to ∆β1 is. so we can solve for (Vgs1 −Vth) after subtracting both sides by Vth: Equation 2 V gs1 − Vth = 4W12 (Vcm − Vth ) Wclk (VDD − Vth ) 1+ − 1 2W12 Wclk (VDD − Vth ) Therefore. approximately square root of (Vcm − Vth) dependence. transistors M3.This is a quadratic equation. Let us analyze the differential current as in the previous case. we can substitute Equation 2 back to Equation 1 to get the input referred offset due to current factor mismatch of M1 in terms of input Vcm.6 are still off.
4 is a degenerated differential pair. As a result. since M1. As a result.2 enter triode region. where g m1 = k n1Vds1 Using these two equations. To simplify the calculation. and R1 = 1 + g m 3 R1 k n1 (V gs1 − Vth ) In Figure 12b. only upper bound calculation is shown here. the mathematics becomes complicated very quickly. the upper bound of input referred offset due to ∆Vth2 is 17 . we can find the input referred offset.VDD VDD M5 Vout1 ∆Vth2 +− invbot1 M3(OS) W36 L M1 W12 L Mclk Wclk L M6 Vout2 M4 W36 L invbot2 M2 W12 L invbot1 M5 M6 Vout1 M3 W36 L M1 W12 L Mclk Wclk L M4 W36 L invbot2 M2 W12 L Vout2 Vin1 Vin2 Vin1 +− Vin2 ∆Veq clk clk (a) Figure 12 Threshold mismatch of M3 (b) In Figure 12a. However. we note that g m3 1 ≤ ≤ g m3 R1 1 + g m 3 R1 We can use this to calculate the upper and lower bounds of input referred offset. M3. The differential current is: idiff = g m 3. where g m 3. g m 3 = k n 3 (V gs 3 − Vth ).eff = g m3 1 .eff ∆Vth 2 . differential current due to equivalent offset voltage is: idiff = g m1 ∆Veq . they are modeled as resistors. Since upper bound gives the worst case offset.
out2 are closed to VDD.clk _ clk Rclk (a) Figure 13 common mode analyses for M3 (b) Assuming out1. we can find Vds1: Equation 4 Vds1 = (VDD − Vgs 3 ) − (Vcm − Vgs1 ) From current equations. input referred offset voltage becomes: 18 .Equation 3 ∆Veq . and substituting Vds1 into Equation 3. so we do a common mode analysis. we have: I= Vcm − V gs1 Rclk = k n 3 (V gs 3 − Vth ) 2 ⇒ Vcm − V gs1 = Rclk k n 3 (V gs 3 − Vth ) 2 Equation 5 Substituting the above back to Vds1. we want to relate the above equation with input common mode voltage. VDD M5 M6 VDD M56 Vout1 M3 W36 L invbot1 M1 W12 L Mclk Wclk L M4 W36 L invbot2 M2 W12 L Vout2 Vout12 M34 2W36 L invbot12 I M12 2W12 L Vcm Vcm Vcm + Vds.due to ∆Vth 2 ≤ W36 (V gs 3 − Vth ) g m3 ∆Vth 2 = ∆Vth 2 g m1 W12Vds1 Again.
due to ∆Vth2 will increase to infinity in the same way as hyperbola. Instead of the complete equations. ∆β2: As in the previous case. and we can write the differential current due to ∆β2 as: 19 . we can only see a small portion of hyperbolic curve as shown in simulation results in Figure 15.Equation 6 ∆Veq . we treat transistors M1.due to ∆Vth 2 ≤ VOD 3 (VDD − Vth ) − VOD 3 − Rclk k n 3VOD 3 2 W36 ∆Vth 2 . in the limited range of Vcm. Offset due to current factor mismatch of M3. to understand how ∆Veq.2 as resistors.due to ∆Vth2 and Vcm are related. The denominator is simply a constant (VDD –Vth) subtract (VOD3+Rclkkn3VOD32). However. we can pay attention on the denominator of Equation 6. where W12 VOD 3 = V gs 3 − Vth is the overdrive voltage of M3. ∆Veq. The exact relationship between VOD3 and Vcm could be found by writing the drain current of transistor M1 and substituting into Equation 5. We can expect that (VOD3+Rclkkn3VOD32) increase with Vcm by inspecting Equation 5. In other words. The denominator will eventually reduce to zero if we allow Vcm to increase beyond VDD.
Assuming the gate voltages of transistors M3.4 are the same.VDD M5 M6 M5 VDD M6 Vout1 M3(OS) W36−∆W L invbot1 M1 W12 L Mclk Wclk L M4 W36 L invbot2 M2 W12 L Vout2 Vout1 M3(OS) W36−∆W L invbot1 M4 W36 L invbot2 R1 Mclk Wclk L R1 Vout2 Vin1 Vin2 clk clk (a) Figure 14 Current factor mismatch of M3 (b) idiff = = 1 ∆W (Vgs 3 − ∆V gs 3 − Vth )2 − (Vgs 3 − Vth )2 k n 3 1 + 2 W36 1 ∆W (Vgs3 − Vth )2 − 2(Vgs3 − Vth )∆Vgs3 1 + ∆W + (∆Vgs3 )2 1 + ∆W k n3 W W 2 W36 36 36 where ∆Vgs3 is the small change in Vgs3 due to introducing ∆W in M3. which is modeled as R1. W36 We can neglect the products of ∆ terms because they are relatively small. we can write: idiff ≈ 1 ∆W (Vgs3 − Vth )2 − 2(Vgs3 − Vth )∆Vgs3 = ∆Vgs3 k n3 2 W36 R1 Equation 7 ⇒ idiff 1 ∆W (Vgs3 − Vth )2 1 k n3 ∆W (Vgs3 − Vth )2 k n3 W36 2 W36 2 = ≈ 1 + R1 g m 3 1 + R1k n 3 (Vgs 3 − Vth ) 20 . and the differential current is equal to the difference of current through M1.2.
due to ∆Vth2.due to ∆Vth2 as shown in simulation results in Figure 15. we calculate the upper bound of input referred offset voltage. due to ∆β 2 Equivalently.where ≤ 2 W12 W36 (VDD − Vth ) − VOD 3 − Rclk k n 3VOD 3 2 2 Equation 9 VOD 3 = V gs 3 − Vth As you can see.due to ∆β 2 VOD 3 1 W36 ∆W . Offset due to threshold mismatch of M5. ∆Veq. Although the numerator of ∆Veq. As a result.due to ∆β2 is similar to ∆Veq. the overall rate of change is dominated by the denominator.due to ∆β2 increases faster than that of ∆Veq.The expression in Equation 7 makes sense because it simply states that the small change in drain current due to ∆β2 is the increase in current for a nondegenerated transistor divided by (1+degeneration loop gain). ∆Veq.due to ∆Vth2. ∆Veq .due to ∆β2 has a hyperbolic increasing characteristic too. ∆Vth3 and current factor mismatch of M5. Again to simplify the calculation. Therefore. we can express this in terms of VOD3 as in the previous case by using Equation 4 & Equation 5. idiff = g m1∆Veq ≤ ∆W 1 (Vgs3 − Vth )2 k n3 W36 2 ∆W 1 (Vgs3 − Vth )2 k n3 W36 2 ≤ k n1Vds1 Equation 8 ∆Veq . the denominator is exactly the same as that of ∆Veq. ∆β3: It can be seen that threshold mismatch and current factor mismatch of M5 have 21 .
little influence on input referred offset voltage. the differential signal is already amplified to a large amplitude compared to the mismatches. and offsets due to M5.6 is very small. The overall offset is again calculated by summing the 22 . the last two terms. Total input referred offset voltage: The device mismatches are statistical numbers. Figure 15 shows the 3σ offset due to each transistor. Also. Simulations on input referred offset voltages over different Vcm: The simulation results on input referred offset voltage show that the equations above can predict the offset. In other words. can usually be neglected because they are relatively small.6 turn on. As a result. the variations on offset with varying VCM are also consistent with the theory. the gain from input to output is large.6 are negligible. as a result. the dominant sources of input referred offsets are due to transistor M14. It is true because by the time that M5. Obviously. σ∆Vth3 and σ∆β3.6 on the output is divided by a large gain caused by positive feedback. offset due to M5. the input referred offset voltage due to M5. The simulations show consistent results with the theory. That is Equation 10 σ total = σ ∆Vth1 2 + σ ∆β 1 2 + σ ∆Vth 2 2 + σ ∆β 2 2 + σ ∆Vth 3 2 + σ ∆β 3 2 For convenience. the total input referred offset is found by summing the variance of the 6 mismatches above. and they are modeled as Gaussian distribution.
1mV. σ∆Vth2 = 9. σtotal = 19.2 1. σ∆Vth3 = 1. For example. σ∆β1 = 10.8 1 1. diff) 50 40 30 20 10 0 0.6 1.4V.variances as in Equation 10. the standard deviation of total input referred offset. σ∆β2 = 8.1mV.8 Input Vcm Figure 15 Input referred offset voltage due to each transistor 23 . standard deviations of input referred offset due to each differential pair are σ∆Vth1 = 10. Offset due to Device Mismatch of Core Comparator 60 vt1 vt2 vt3 beta1 beta2 beta3 Input Referred Offset(mV.9mV.7mV.5mV.3mV.2mV. σ∆β3 = 0. at Vcm = 1. and the worst case total input referred offset is 6σtotal = 115mV.4 1. Using Equation 10.
2. The second section will combine the results and obtain the overall supply sensitivity on offset. ∆Vth.2 Supply Sensitivity In the previous section. Supply Sensitivity on offset due to each differential pair has been found in simulations. we need to find the supply sensitivities due to each transistor and then combine the results to obtain the overall supply sensitivity as in the case of input referred offset. ∆β. As a result. supply sensitivity due to ∆Vth1. In order to find the supply sensitivity. which is simply equal to input referred offset. 24 . 2.2. it is important to know the supply sensitivity on offset. ∆Vth3. we found that as supply voltage changes. does not change with supply and offset due to ∆Vth3 and ∆β3 are much smaller than other offsets. we found that input referred offset changes with VCM. and current factor mismatch. supply voltage is noisy because of the digital switching property. Thus. Since offset due to ∆Vth1. the first section will discuss the supply sensitivity on offset due to each transistor. the input referred offset changes as well.2.1. In addition. In most digital system. the comparator is broken into 3 differential pairs and each pair has threshold mismatch.1 Supply Sensitivity due to each transistor As in the offset calculations in 2. and ∆β3 are not shown in Figure 16.
4 Input Vcm (V) 1.2 1.Offset due to beta1 mismatch 45 4 3 Offset due to beta1 mismatch Change in Offset (mV.8 1 1.4 Input Vcm (V) −20 0.6 1.6 1.8 10 40 0 20 −10 0 0.8 1 1.4 Input Vcm (V) +10% Sup −10% Sup 1.8 (c) Offset due to vt2 mismatch 100 30 Noraml 10% Sup −10% Sup (d) Offset due to vt2 mismatch +10% Sup −10% Sup 20 Input Referred Offset(mV.6 1.8 1 1.4 Input Vcm (V) Noraml 10% Sup −10% Sup 1.8 (a) Offset due to beta2 mismatch 60 8 (b) Offset due to beta2 mismatch +10% Sup −10% Sup Offset(mV.6 1.8 1 1.8 Noraml 10% Sup −10% Sup 1 1. ∆β2.6 1.8 Change in Offset (mV.2 1.2 1.2 1.diff) 40 30 20 10 0 0.2 1.8 (e) (f) Figure 16 Supply Sensitivity on Offset due to ∆β1.2 1.6 1.4 Input Vcm (V) 1.8 1 1. (mV. and ∆Vth2 25 .8 2 1 0 −1 −2 −3 −4 0.4 Input Vcm (V) 1. diff) 80 60 Change in Offset. diff) 50 6 4 2 0 −2 −4 0. diff) 1. diff) 40 Offset(mV.diff) 35 30 25 20 15 10 0.
“10% Sup” represents the offsets when supply is 10% higher than normal. which is exact equal to the data in Figure 15.98V.2. Offset of a comparator is a random variable.62V. ∆σ. show the change in offset. In the plots on the left i. while Figure 17b shows 6∆σtotal in percentage.2V – 1. This means that it is possible to obtain a high input referred offset while supply sensitivity on offset is small. “–10% Sup” represents the offsets when supply is 10% lower than normal. because the two opposing sources cancel with 26 . “Normal” represents the offsets at normal supply 1.2 Overall Supply Sensitivity of Core Comparator We can use change in offset. is calculated by using Equation 10. and so is supply sensitivity on offset. in 2. please keep in mind that Figure 17 shows the worstcase values.In Figure 16. which is 1. Since all offsets are statistical values.2. and (f). (c).4V) the 6σtotal worstcase change in offset due to 10% supply change is about 10% also. while offsets due to ∆β3 and ∆Vth2 have negative supply sensitivity. all offset values are 3σ standard deviation. from normal operating supply. Note that offset due to ∆β1 has positive supply sensitivity. In addition. (a).1 to calculate the overall supply sensitivity on input referred offset. which means positive change of supply causes positive change in offset. (b). Figure 17a shows 6∆σtotal in mV. the overall change in offset. which is 1. 2.e. notice that supply sensitivities on offset due to ∆β1 and due to ∆Vth2 oppose to each other. ∆σtotal. and (e).8V. In moderate VCM (1. Before we finish this section. The plots in the right column i. And the worstcase overall supply sensitivity is 6∆σtotal as shown in Figure 17.e. (d). ∆σ.
are discussed last.8 1 1.each other.1 Evaluation Phase In evaluation phase.4 Input Vcm (V) +10% Sup −10% Sup 1. and tail current Mclk is on. 2. are off.6 1. The effects on both evaluation and reset phase of different input common mode bias.8 1 1. To do a complete analysis.8 (a) (b) Figure 17 Overall Supply Sensitivity on Offset 2. Second. VCM.4 Input Vcm (V) 1.2 1. the speed of evaluation and the speed of reset are examined separately.diff) 50 40 30 20 10 0 0. the maximum sampling rate of a comparator depends on the speed of both evaluation and reset.8 +10% Sup −10% Sup 30 25 20 15 10 5 0 0.3. a criterion is developed to assure proper reset. First. RST16. analysis of evaluation phase will be performed and a set of formula will be developed to represent how fast the evaluation is. Since the comparator spends half of the cycle on evaluation and half of the cycle on reset. Input differential pair will steer the current according to the 27 .2 1. All reset devices. Supply Sensitivity on Offset 60 35 Supply Sensitivity on Offset in Percentage Percentage Change in Offset (%) Total Change in Offset (mV.6 1.3 Speed A second important requirement of a comparator is high sampling rate. clock is logical high.
Here.difference of inputs. which has finite gain. The second time interval begins when Vinvbot1.4. Figure 7 is shown again in this section. VDD clk RST3 4 2 M5 4 2 RST1 4 2 clk RST2 4 2 M6 4 2 RST4 4 2 clk RST5 Vout1 M3 4 2 invbot1 Vin1 M1 8 2 RST6 4 2 Vout2 M4 4 2 4 2 invbot2 M2 8 2 Vin2 clk Mclk 16 2 Figure 7 Core Comparator Characterizations on Evaluation phase: The whole evaluation phase can basically divided into three time intervals. characterizations on evaluation phase will be given. and then the choices of transistor sizes will be briefly discussed. turning on M3. the comparator changes from reset phase to evaluation phase.2 drop to VDD − Vthn. For your convenience. Positive feedback is realized by two backtoback inverters. And the 28 . positive feedback system provides infinite gain. In the first time interval. Unlike traditional operation amplifier. positive feedback is utilized. In order to create a lot of gain within a short amount of time.
The transfer function from input. 2 sCinvbot1.4 is regeneration time constant.2. Let us look at the behavior of the comparator starting from the first time interval.initial e Cout . Since M36 are off. M5.2. thus. diff = g m1. If we look at it more carefully. 2 Equation 11 . to invbot1. During reset phase. where gm1. when the comparator changes from reset phase to evaluation phase. In this period. M36 are initially off. turning on M5. Vout2 drop to VDD − Vthp. The response of positive feedback is well known [4].2 are tied to VDD. As Vout1. The third time interval is similar to the second time interval.2 is the transconductance of M1. Crosscoupled transistors M3. Cinvbot1. transistors M36 are all off.6 turn on.2. the only active devices are input differential pair M1. The positive feedback. As a result. This is desirable since it gives infinite gain at DC while averaging or filtering out the high frequency noise depending on viewing the problem in time domain or in frequency domain.6. becomes stronger and 29 . can be written as: H1 ( s ) = Vinvbot1.2 ≅ VDD − Vthn. H1(s) is actually an integrator. differential wise. transistors M1. 2 Vin .2 see only capacitance on their drain. 4 t Equation 12 Vout (t ) = Vout . nodes invbot1.e. where Cout/gm3. The second interval starts when M3.4 turn on.2 drop to VDD − Vthp. in1. i. as a result.last time interval starts when Vout1.4 provides positive feedback response.2. The differential output will be exponentially increasing with time (often referred to as regeneration): g m 3.2 and current source Mclk. Vinvbot1.
The implicit meaning of tdelay is that we treat initial integrator response. Choice of transistor sizes In order to choose the transistor sizes such that the comparator gives fastest evaluation. gm3. 6 t Equation 13 Vout (t ) = Vout .4 + gm5. Regeneration will eventually stop and Vout saturates at VDD. It is however not convenient to go through all three equations to calculate the exact output. which is much slower than the regeneration response.initial e Cout Equation 13 is valid until M36 enter triode region. According to [5]. As M36 enter triode region. we developed a simplified equation to characterize the evaluation phase. where τ = g m 3.differential output becomes: g m 3. Equation 14 enables us to compare the evaluation speed of different comparators. t −t delay Equation 14 Vout (t ) = Vin e τ .4 and 30 . 6 C out and tdelay captures the initial integrator response. having the width ratio of M3. This section will discuss the tradeoffs of sizing the transistors. 4 + g m 5 . as a delay on start of regeneration. since smaller regeneration time constant results in larger gain in fixed amount of time. 4 + g m 5. Let us first concentrate on the effects of M36. we should maximize integrating factor and minimize regeneration time constant. As a result. it is desirable to minimize regeneration time constant. First.6 decreases.
M5. increasing the width of M36 will increase g m 3. 2 C invbot1.2 or the width of current source Mclk. Under small loading capacitance condition.2. Another way to increase the integrating factor is to increase input gm. The former is a tradeoff with input 31 . Cinvbot1.2 from dropping down and thus delays the start of regeneration.6 and Cout increase at the same time. while PMOS has larger parasitic. thus. This will be discussed in more detail when we consider the speed penalty of digital offset compensation in Chapter 3. when we employ digital offset compensation. If loading capacitance is large. 4 + g m 5 .4 add parasitic capacitance on node invbot1. However. Another way to decrease the regeneration time constant is to increase the current and thus increase the width of Mclk. so regeneration is faster. As you notice. On the other hand. Secondly.4 + gm5. the P:N ratio is smaller than normal inverter P:N ratio. which lowers down the integrating factor and prevents the common mode of invbot1. It is obvious that we should minimize Cinvbot1. We can increase either the width of input devices M1. which is normally 23.6 equal to 1. 2 .0 gives the best regeneration. there is tradeoff between power and speed. In comparator both NMOS and PMOS provide positive feedback. if loading capacitance is so small that the gate capacitance of M36 dominates.2 often increases. 6 C out because both gm3. it is not a good idea to choose arbitrarily large M36 because M3. we consider increasing the integrating factor g m1. it is natural to size down PMOS.2. As a result. although regeneration time constant does not depend on the width of M36. 4 + g m 5 . 6 C out . increasing the width of M36 will not change g m 3.
2V). sizing input devices M1. while the latter is a tradeoff with power. To compare the speed.6 equal to 1.4 and M5. columns Mclk. for example inverter or SR latch.18µm. Note that sizing input devices M1.2 also gives advantages in term of input offset voltage. so the width of M36 are always the same in all simulations below. sizing M1. we calculate the regeneration time constant τ.2 should be the same for sizing M1. Sim Mclk M1. and tdelay (see Equation 14 for definition). We rank the comparators using T(@Vout=1.clk.2.48µm/0.24µm has effective length Leff = 0.2 results in larger Vds. In the table shown below. Therefore. To show the combined effect. The three remaining parameters are width of transistors Mclk.2. From equation. For example. Note that L=0. [5] states that the comparator gives the best performance by having the ratio between M3.capacitance. g m1. and M36.2 and for sizing Mclk.24µm.2 M36 τ(ps) tdelay(ps) T(@ Vout=1. and M36 are the ratio of their width to the minimum transistor width (Wmin/L) = 4λ/2λ = 0. An output of 1.2 increases not only W1. 2 L I D we find that the rates of increase in gm1. we also calculate the time from clock transition to the time that differential output reaches 1. since Mclk is often in triode region.2V)(ps) Ranks 32 .2V. M1. M1.2 gives us more advantages. Simulation Results on Sizing Transistors The evaluation speed has been simulated to confirm the intuitive understanding explained above.2V).24µm.2V is chosen because it is large enough to toggle the output stage. 2 = 2µC ox W1. However.2/L but also ID because smaller Vgs1.96µm/0. Mclk = 2× means that size of Mclk = 2Wmin/L = 8λ/2λ = 0. denoted as t(@Vout=1.
Note that the output loading effect is already taken into account in the simulations above.9 45.0 34. Sim7. sim5.3 36. The larger M1. The 7th in the rank is sim6. which slow down the integration. which tells us using all minimum size does not necessarily give the slowest response.2. M1.6 52.2 38.2 have a slight advantage as discussed earlier. gives the fastest response.3 79. However. and M36 would be fastest. sim8 is only second fastest. This makes sense because we simultaneously increase positive feedback gm3.8 37. sim8 has more delay on tdelay. increasing M36 gives better τ than rank #36 do. The other interesting result is that sim1 is ranked 8th.2 55.0 57.2.2 38.7 38. sim4.2 42. and sim11 are slowest. These two simulations are similar for the next two in the rank. The next two fastest are sim10 and sim9. but it adds too much capacitance on node invbot1. The details 33 .2.3 40. sim3 and sim2.1 2 3 4 5 6 7 8 9 10 11 1× 2× 1× 1× 2× 1× 2× 2× 4× 1× 1× 1× 1× 2× 1× 2× 2× 1× 2× 1× 4× 1× 1× 1× 1× 2× 1× 2× 2× 2× 1× 1× 4× 40.9 32.6 and input gm1.6 98.4+gm5.8 130 263 234 227 307 196 255 265 211 219 217 425 8 6 5 10 1 7 9 2 4 3 11 Table 1 Simulation results on evaluation with varying comparator transistor size As shown in the table. Although sim8 actually has a faster τ than sim5. Again. One would think that doubling all devices Mclk.2.5 74. which is directly proportional to the integrating factor. resulting in a slower overall response. These three simulations show that increasing size of M36 is not a good idea.2 75.6 54.4 37.8 37. which doubles both Mclk and M1.
we should design an appropriate reset so that it can work correctly and efficiently. differential output needs to be less than 0. if the reset is incomplete and there is any residual charge on Vout1. Figure 7 is shown here again. tradeoffs between reset and evaluation will also be discussed. we must place some transistors to break the backtoback inverter. In order to break the positive feedback.of output loading will be discussed in section 2. In this section. the tail current source Mclk is off. If no reset device is added. All possible reset transistors RST16 are shown in Figure 7. As a result. the design of reset transistors is presented. a small residual charge can create large input referred offset. In order to reset a comparator that has positive feedback.2 Reset Phase Reset is as important as regeneration for accurate operation. Once the comparator is optimized for the evaluation phase.6. 2. the comparator will still stay in its state forever because of the positive feedback. In this project. we must break its positive feedback loop and reset it as fast as its regeneration.3. 34 .5mV at the end of reset phase to achieve the required accuracy. Vout2. However. positive feedback will amplify the residual charge exponentially when evaluation phase comes again. For your convenience. Design of Reset Transistors: During clock is logical low.
4 have their tradeoffs. Both RST1. there is fighting between reset and regeneration. First.2 and RST3. More importantly.4.2 are connected to out1. In small signal analysis. but also help reset the comparator. the parasitic of RST1. which shorts the two outputs together.VDD clk RST3 4 2 M5 4 2 RST1 4 2 clk RST2 4 2 M6 4 2 RST4 4 2 clk RST5 Vout1 M3 4 2 invbot1 Vin1 M1 8 2 RST6 4 2 Vout2 M4 4 2 4 2 invbot2 M2 8 2 Vin2 clk Mclk 16 2 Figure 7 Core Comparator The most important reset is RST5. a crosscoupled NMOS pair under reversed current condition has effective resistance equal 35 . as a result.2 can only shut off PMOS.4 are utilized. RST3. the reset response is very poor.2 will degrade the regeneration time constant.4 not only stop regenerating.out2. RST1. since RST1. RST1. there is still a slight fighting between reset and regeneration due to NMOS M3. Second.2 and RST3. M3. Without RST5. RST5 alone is not enough because as long as all 4 feedback devices are on. Once current is reversed. However.4.4 are indirect resets. because they serve as reversing the current of NMOS M3. In order to break the positive feedback.
fmax. RST3. RST5.2V) (see Table 1 for definition).5mV. and RST6.2 is usually large. that is the time required to reset a comparator whose differential output decreases from full VDD to 0. and T(@Vout=1. so it can remove small output residue more quickly and more accurately than RST1.4 completely break the positive feedback. As in the evaluation section.2V)). τ. yet they degrade the integrating factor of a comparator. Simulation Results on Reset Devices: Simulations are performed with varying reset devices size to see the performance change. and M3.6 from positive feedback PMOS M5. In digital offset compensated comparator.48µm/0. as a result. tdelay. we calculate all evaluation metrics. in the early part of the reset phase. We simulate on different sizes of RST1. 36 . On the other hand.rst = 1/(2treset). and maximum frequency based on reset time.4 will help cancel the −2/gm5. This configuration is the same for all digital offset compensated comparators so that we are able to perform a fair comparison later. leaving RST5 to eliminate the rest of the negative resistance.to 1/gm. Three new measurements are maximum frequency in evaluation phase. including evaluation and reset. RST6 is introduced to further reset the charge on node invbot1.2.4. This behavior can be seen in simulations in the next section. reset time. For comparison.6.2. RST3. Simulation condition is Vcm=1. M1. treset.eva = 1/(2 T(@Vout=1.2=2×. it cannot reset the comparator as quickly as RST1. one unit size is Wmin/L = 4λ/2λ = 0. The last reset is RST6. capacitance on node invbot1.4=1×. Since RST3.4 do not degrade the regeneration time constant. fmax. Mclk=4×. and the device sizes are multiple of unit size.2.2.24µm. This 1/gm3.4 are indirect resets. RST3.2V.
Also as expected.Sim Rst5 Rst1. Sim1 is a comparator with only RST5.rst Rank (GHz) 0.68 2. Although integrating factor is reduced.4. By adding RST3. the comparator resets faster than that in sim2 while degradation of evaluation is minimum.67 2.85 2.0 157 171 162 176 181 170 184 176 187 186 167 3.78 11 9 8 2 3 10 6 4 1 5 7 1 2 3 4 5 6 7 8 9 10 11 1× 1× 1× 1× 1× 2× 2× 2× 2× 1× 1× 0× 1× 0× 1× 1× 0× 1× 0× 1× 2× 0× 0× 0× 1× 1× 1× 0× 0× 1× 1× 0× 2× 0× 0× 0× 0× 1× 0× 0× 0× 0× 0× 0× 836 332 305 174 175 650 269 234 149 266 281 Table 2 Simulation results on reset device Let us analyze the results shown in Table 2 from top to bottom.3 26.3 34.5 33. Next.99 Rank treset (ps) 1 5 2 7 8 4 9 6 11 10 3 Reset Phase fmax. almost 3 times as fast as original.77 2.6 Evaluation Phase tdelay(ps) T(@Vout=1.5 27.0 30.3 30. hence.9 32. Sim3 has a highly desirable result. Sim4 uses both RST1.85 0.88 2. the 2nd fastest in evaluation.77 1.out2. Since RST3. adding RST1.7 19.3 21.7 24.14 3. sim4 is the best since both evaluation and reset achieve 2.9 24.92 3. further adding reset RST6 seems to give 37 .4 Rst6 τ(ps) 30.7 32.6 29. the 2nd fastest.95 2.60 1.3 34. In next simulation.2V) fmax.0 20. the middle reset that ties both outputs together. i.51 1.4.2 Rst3.86 2.84 2.2 in sim2 will speed up the reset. reset response is much faster. the regeneration time constant is almost the same as that in sim1.4 do not add parasitic capacitance on out1.7 35.2 slightly degrades the regeneration time constant because it adds capacitance on the output nodes.64 2.08 2.9 32. adding RST1.2 and RST3.eva (ps) (GHz) 15. which can be seen by comparing tdelay.19 2. it gives the fastest evaluation but the slowest reset. the overall evaluation performance is not heavily degraded because the comparator spends only a short time on integration.0 26.36 1.72 2. As expected.e. Among all comparators shown in this table.88 1.6 32.8Ghz.2 24.
adverse results. however.2 0. but sim11 resets slower than sim10.6 Time.2 1 0.55 0. Generally. Sim69 have similar behavior as sim14 do.2 0. sim10.4 0.4 simultaneously (sim4).3 0.45 0.8 0.2 0 −0.2 and RST3. note that RST6 may become more useful when digital offset compensation is added to the comparator.6 0.4 (sim3 & 38 . RST1.8 1. ns Figure 18 Reset Response of sim2.4 alone can never be as efficient as having RST1. and thus it takes a long time to eliminate small residue charge. the fighting between reset and regeneration exists. and sim11 Interestingly sim3 resets faster than sim2. RST3. On the other hand.5 0. In sim10 and sim11. sim69 have slower evaluation but faster reset because of the doubled RST5. we see that doubling RST1.25 sim10→ 0. sim3. However.4 0. where both evaluation and reset is slower than those in sim4. Reset Response of a comparator 1.35 0.4 1. Figure 18 illustrates the reason.2 (sim2 & sim10) can reset the comparator quickly at the beginning. The effect of RST6 will be discussed more in Reset Penalty in Chapter 3. mV 1.6 ←sim2 ←sim3 sim11→ Differential Output.2 or doubling RST3.
For the lower bound.82 2.8V).2 39 .88 2.81 2.72 2.4 1.84 2. However. RST1.80 Table 3 Evaluation and Reset with vary Vcm (see Table 1. This configuration can break the positive feedback quickly while it does not heavily degrade the evaluation.8 24. In conclusion. and RST3. The simulation results are shown below.4V) For the upper bound.sim11) mainly reverse the current of M3.4. Vcm.6 29.92 2.9 24.2 and current source Mclk. sim4. Effects on evaluation and reset with varying Vcm: The comparator shown in Figure 7 works only in a certain range of input common mode voltage.5 32.4 216 184 176 178 182 190 fmax.4 Evaluation Phase T(@Vout=1.2 31.reg (GHz) 2.9 32. Vcm (V) 0.8 τ(ps) 39. hence. gives the best tradeoff between evaluation and reset.2V) tdelay(ps) (ps) 33. comparator is completely reset at a rapid rate.Table 2 for term definition) At low Vcm the regeneration is slow as expected because low Vcm results in low Vds. tail current increases. tdelay becomes worse since input devices M1.Mclk thus low tail current. It is found that the comparator achieves the best performance in intermediate Vcm. the input common mode voltage is limited by the power supply on chip (Vcm < VDD = 1. at high Vcm.0 1.5 34.rst treset (ps) (GHz) 168 171 174 176 178 179 2. the input common mode voltage must be high enough to turn on both input devices M1.7 31. so regeneration time constant decreases.75 2. there is a delay before the positive feedback is broken.31 2.7 35.4. (Vcm > Vth1.2.97 2.84 2. As Vcm increases. which has RST5.6 45.2 = 0.6 1.8 1. After the feedback is broken.63 Reset Phase fmax.2 1.
2. In short. in these cases.2 harder. Intermediate Vcm therefore gives the fastest evaluation. Total input capacitance. As a result. 40 . which must be sized to fulfill the input referred offset requirement.enter triode region. like Figure 7.6V. is the gate capacitance of input devices M1. The input capacitance requirement will be revisit in Chapter 3 where digital offset compensation is introduced. One of the methods to decouple the relationship between input capacitance and offset is digital offset compensation. the comparator still provides a good performance in the range of 1.2. high Vcm leads to slightly slower reset. A high common mode input tries to pull down invbot1.4 Input Capacitance In applications.4V < Vcm < 1. there is a direct tradeoff between input capacitance and offset. like oversampler and flash ADC.0V ≤ Vcm ≤ 1. a bank of comparators is typically placed in parallel. we can see that within the possible Vcm bounds (0. and tdelay becomes worse in high Vcm. it is desirable to minimize the input capacitance of a comparator. τ becomes worse in low Vcm. may become enormous because it is simply equal to the input capacitance of a single comparator multiplied by number of comparators in parallel. Comparing the variation of fmax in evaluation phase and reset phase. the input capacitance of a simple comparator.8V). which decreases input gm and thus the integrating factor. Therefore. which opposes the pull up of the reset devices. Unfortunately. For reset phase.
8 79. Since comparator outputs provide full swing signal in 41 . As current has direct relationship with speed. we can only reduce current by minimizing tail current transistor Mclk. the total power consumption simply gets multiplied by the number of comparators. like oversampling receiver and flash ADC.41 1.5 Power Consumption Power consumption is also a big issue when numerous comparators are used in applications.0 1. Simulation results on power measurements are shown in Table 4. Fortunately. we must place a SR latch after the comparator.2 Table 4 Power Consumption of Core Comparator 2.0 87. power consumption of a comparator is typically much less than normal operation amplifier because positive feedback saturates the backtoback inverters and shuts off the current when evaluation is finished.76 1.4 1. there is obviously tradeoff between power consumption and speed. Assuming that load capacitance is already minimized by proper sizing and careful layout.4 100.6 Design of Next Stage (SR Latch) In order to provide a constant logical output over one period. Again.2 94.2.25 1.6 106. power consumption increases with input common mode voltage because Mclk is usually in triode region and Vds. comparator shown in Figure 7 has a better power efficiency among other architecture.8 112. VCM (V) Power (µW) 0.clk varies with Vcm. according to [3]. load capacitance and current must be minimized. Moreover. To reduce the power consumption. As you can see.
evaluation phase and are pull up to VDD in reset phase. Vin2 are pull up to VDD. Vin1. Thus. Hence. which directly affects comparator regeneration time constant and power consumption. a simplified SR latch as shown in Figure 19 has been designed. full swing differential signal from comparator is converted to single ended digital signal at SRoutb. fortunately comparator has large gain. Although this SR latch has systematic offset and large random offset due to small transistor size. Inverters are then used to buffer up to drive the output. However. VDD MSR1 4 2 VDD MSR2 4 2 SRoutb Vin1 Vin2 MSR3 4 2 Output MSR4 4 2 Figure 19 Simplified SR Latch During evaluation phase. all digital offset compensated comparators in the next chapter are followed by this SR latch. a NAND based SR latch may not give satisfying performance at high speed. This behavior is exactly same as a NAND based SR latch. 42 . The advantage of this circuit is its high speed and low input capacitance. so input referred offset due to SR latch is well below 2mV according to simulation.SR2. During reset phase. Node SRoutb stays constant until the next evaluation phase comes again. turning off MSR1. a NAND based SR latch is well suited. For fair comparison.
supply sensitivity. the comparator can remain in open loop system. and tradeoffs between them. The last section will give a summary of comparison of all four architecture. Section 3. In this project. Once offsets are stored. and power consumption respectively. which were characterized for the core comparator in chapter 2. We compare all four architectures by measuring the performance metrics.6 will compare performance metrics: input referred offset. four architectures on digital offset compensation are considered. input capacitance. and thus. 43 . This project will compare the characteristics of these four architectures.Chapter 3 Digital Offset Compensation The most important feature of digital offset compensation in comparator is that offsets are measured digitally and are stored in static memory.2 – 3. inherent speed of a comparator can possibly be achieved. and their basic operating principles are explained. speed. four architectures are first presented. In this chapter.
is shown in Figure 20. Comp1. Nodes D14 are controlled digitally. an offset compensation that varies with VCM can increase the correction precision. Since internal offset varies with common mode as you can see in Figure 15. Node VCM is connected to the common mode voltage of inputs Vin1 and Vin2.3.1. so we call it 44 .1 Four Different Architectures 3. This current will provide an offset to compensate for the internal offset due to device mismatches. Turning on only D1 provides the least offset correction.1 Architecture Comp1 VDD clk clk RST3 6 2 M5 RST1 4 4 2 2 RST5 4 2 RST2 M6 4 4 2 2 RST4 6 2 clk Vout1 M3 4 2 M1 8 2 clk Vout2 M4 4 2 Invbot1 MCM1 4 6 MOS1A 4 6 MOS1B 4 6 MCM2 4 6 MOS2 4 6 MCM3 4 6 Vin1 MOS3 4 6 Invbot2 Mcm4 4 Vin2 6 MOS4 4 6 Mcm5 4 6 MOS5 4 6 Mcm6 4 6 MOS6A 4 6 MOS6B 4 6 6 RST6 2 Mclk 16 2 VCM M2 8 2 VCM D1 D2 D3 D4 Figure 20 Schematic of Comp1 The first architecture. Extra devices MCM16 and MOS16 are placed in parallel with input devices to steer small amount of current.
D1. 3. is not half the size of D2 device because it is desirable to minimize the parasitic capacitance of MCM16 and MOS16 and not to slow down the speed of the comparator. If negative offset compensation is needed. Turning on subsequent bits (D2. is similar to Comp1. D3) increases the correction in a binary fashion.Least Significant Bit (LSB) correction. Each branch consists of 2 NMOS and the capacitance 45 . Comp2. D4 will be turned on and D13 will be turned on appropriately to control the magnitude of the negative offset. The performance and compensation nonlinearity of Comp1 will be discussed in the next section.1. The LSB control devices.2 Architecture Comp2 VDD clk clk RST3 6 2 M5 RST1 4 4 2 2 RST5 4 2 RST2 M6 4 4 2 2 RST4 6 2 clk Vout1 M3 4 2 MOS0 4 8 MOS1 4 8 MOS2 8 8 MOS3 Invbot1 16 Vin1 8 M1 8 2 Vout2 M4 4 2 6 RST6 2 Mclk 16 2 M2 8 2 Invbot2 Vin2 32 8 MOS4 VCM D3b D2b D1b clk VCM D4b Figure 21 Schematic of Comp2 The second architecture. Schematic of Comp2 is shown in Figure 21 [6]. The problem of Comp1 is its large parasitic capacitance due to digital offset compensation.
Additional currents sources Mclk04 and MOS04 are digitally controlled by D14. A small 46 . so additional coding on D14 is not needed. so the compensation magnitude also varies with input common mode. The supply of inverters is VCM.between the NMOS slows the comparison speed.2. 3. tail current is split to MclkL and MclkR. and MOS14 is binary weighted. so no systematic offset is introduced when MOS16 are off.3 Architecture Comp3 VDD clk clk RST3 6 2 M5 4 2 RST1 4 2 RST5 4 2 RST2 4 2 M6 4 2 RST4 6 2 clk Vout1 M3 4 2 Invbot1 Vout2 M4 4 2 D1 D2 D3 Vin1 M1 8 2 6 RST6 2 VDD 4 M7 4 M2 8 2 Invbot2 Vin2 clk MOS0 4 2 Mclk0 4 2 MOS1 4 2 Mclk1 4 2 MOS2 8 2 Mclk2 8 2 MOS3 16 2 Mclk3 16 2 MOS4 32 2 MclkR 8 2 Mclk4 32 2 D4 MclkL 8 2 Figure 22 Schematic of Comp3 The third architecture. Dummy current source Mclk0 and MOS0 is again for balancing the comparator. using linear scaling on MOS14 in Comp2 does not degrade the speed as severely as Comp1 does. Mclk14.1. Comp3. Therefore. one branch is a single NMOS. Dummy device MOS0 is added to balance the capacitance on nodes invbot1. In Figure 22. produces digital offset by controlling tail current [7]. In Comp2. MOS14 are binary weighted.
M7 promotes current steering of differential pair M1.4 Architecture Comp4 VDD clk clk RST3 6 2 M5 4 2 RST1 4 2 RST5 4 2 RST2 4 2 M6 4 2 RST4 6 2 clk Vout1 MC4 32 2 Invbot1 ×8 MR 16 2 M3 4 2 Vout2 M4 4 2 M2 8 2 Invbot2 MC0 4 2 MC1 4 2 MC2 8 2 MC3 16 2 RST6 RST7 4 6 6 2 Vin1 M1 8 2 VDD Mclk 16 2 Vin2 clk MR 16 2 ×1 ×1 ×2 ×4 D4B VDD D1B D2B D3B Figure 23 Schematic of Comp4 The last architecture. M1 is degenerated by RMclkL//(RM7/2) so input gm is larger. First. M1 sees only MclkL.NMOS M7 has three purposes. an imbalance current flowing into PMOS capacitors MC04 produces offset.2. which is model as resistor because MclkL is in triode region. so minimum channel length can be used to create the appropriate range of offset. 3. whose digital compensation parts have longer channel length. it reduces offset due to mismatch of MclkL and MclkR. Comp4.1. unlike Comp1 and Comp2. On the other hand. the offsets created by digital compensation devices Mclk14 and MOS14 are reduced. If M7 is not present. During digital signals D1B4B are high. if M7 is present. Second. As a result. PMOS MC14 are off. so nodes 47 .2. is shown in Figure 23 used by [8]. Third. Comp4 varies capacitances of invbot1. M1 is degenerated by RMclkL.
In other words. linearity among offset magnitude directly affects the worstcase overall offset. 3. by controlling the difference of capacitance between invbot1 and invbot2.2. so the overall offset of the comparator reduces to zero ideally. PMOS MR. if the digital offset steps are not uniform.2 Characteristics of Digital Offset Compensation The goal of digital offset compensation is to create an offset that cancels the internal offset due to device mismatches.invbot1. 3. However.1 Offset Magnitude of Digital Compensation All four comparator Comp14 have 4bit (16level) offset correction. MR is carefully sized so that the correction range of the digital offset compensation just covers the maximum offset due to internal device mismatches. switches to low. If digital signal D1B.2 see only source/drain overlap capacitances. so invbot2 sees source/drain overlap capacitance plus channel capacitance due to MC1. This section discusses the offset magnitude for each comparator. and the worstcase overall offset after compensation is shown last. The series resistors reduce the effective capacitance. As a result. A slight capacitance difference between invbot1 and invbot2 results in a small current imbalance. offset of the comparator can be controlled. is placed in series with PMOS capacitance MC04. Simulation results are shown in Figure 24 – Figure 27. Simulations have been performed to examine the characteristics of offset correction of each comparator. “Device Mismatch” 48 . PMOS MC1 turns on. Linearity of offset compensation is secondly presented. for example. so the digital offset precision can be adjusted. the overall offset after compensation will be degraded. acting as a resistor.
Comp3 splits the tail current.represents 6σ of offset due to internal device mismatch of a core comparator. Comp1 loses one digital level on D4D3D2D1 = 1111 because this digital value provides zero offset as shown in the schematic in Figure 20. Each level is close to a constant value over high VCM. In addition. The digital offsets created by Mclk14 in Figure 22 increase fairly quickly with VCM. Comp2. Since Vds. the offsets created by digital controlled branches reduces as well. Comp2 provides 16level correction. The worstcase overall offset after compensation is. degraded. so mismatch between two tail currents contributes offset of the comparator. compression of the offset step size at high digital offset settings can be easily observed in Comp3. 49 . The linearity is expected to be the best and will be discussed in the next section in detail. The first positive LSB creates the largest step. As you can see from the distribution. As a result. thus. The variation of digital offset with VCM is similar to that of internal device mismatch shown in dotted line in the figure. the offset difference between two levels diminishes because Vds. “Digital OS” represents 16level offset correction of the comparators. making a wide spread in high VCM. and Comp4. the internal device mismatch is larger than Comp1.clk decreases with more MOS14 turned on. the 16 levels divides 6σ internal offset quite evenly.clk is reduced. As the digital value increases. This property provides a better correction over wide range of VCM. Figure 25 shows the digital offset magnitude of Comp2. Figure 26 shows the digital offset of Comp3. Figure 24 shows the digital offset for Comp1.
8 Device Mismatch Digital OS 1 1.4 1.6 Input Vcm Figure 25 Digital Offset of Comp2 50 .6 Input Vcm Figure 24 Digital Offset of Comp1 Input referred offset(mv. differential) Comp1.4 1.8 1 1.Input referred offset(mv. Digital Controlled Offset 150 100 50 0 −50 Device Mismatch Digital OS −100 −150 0.2 1.2 1. differential) Comp2. Digital Controlled Offset 150 100 50 0 −50 −100 −150 0.
4 1. Digital Controlled Offset 200 150 100 50 0 −50 −100 −150 −200 0. differential) Comp3.4 1.2 1.6 Input Vcm Figure 27 Digital Offset of Comp4 51 . differential) Comp4.Input referred offset(mv.8 1 Device Mismatch Digital OS 1. Digital Controlled Offset 400 300 200 100 0 −100 −200 −300 −400 0.2 1.6 Input Vcm Figure 26 Digital Offset of Comp3 Input referred offset(mv.8 1 Device Mismatch Digital OS 1.
This characteristic is similar to that of Comp1. the step size slightly decreases. the “zig zag” pattern creates less than 0. It can be observed that as more switches are asserted. thus.5 LSB. Digital offset DNL of Comp3 is shown in Figure 30. 52 . The DNL of Comp3 is the worst among 4 architectures. the digital offsets of Comp4 increase gradually with VCM. This section compares the differential nonlinearity (DNL) of each comparator. Comp4 loses about 0. Comp2 also has minor compression of the offset step size. the accuracy will be degraded.5 LSB DNL. Fortunately. We observed that the LSB creates a larger offset then it should. 3. As a result. The maximum DNL is as high as 1 LSB.2 Linearity of Digital Offset Compensation All 4 architectures have equal number (4bit) of digital offset correction. The nonlinear offset compensation will degrade the effect number of bit correction.As shown in Figure 27. There is a clear “zig zag” pattern in the DNL profile.5 LSB DNL. and it causes about 0. Digital offset DNL of Comp1 is shown in Figure 28. This pattern is created by the nonlinear scaling on the digital controlled branches. The maximum DNL is approximately 0. The compression described earlier is particularly noticeable. reducing the effective number of bits to less than 3 bits of correction. as a result. Some compression of the step size has been observed. a large positive DNL in one digital setting is followed by an equal magnitude but negative DNL in the subsequent digital setting. Figure 29 shows digital offset DNL of Comp2. Digital Offset DNL of Comp4 is shown in Figure 31.8 LSB DNL.2.
2 −0.8 vcm=1. Digital Offset DNL 0. W Figure 29 Digital Offset DNL of Comp2 53 .4 −0.Comp1.8 −10 −5 0 5 10 Digital Level.2 vcm=1.4 Offset DNL (LSB) 0.4 vcm=1.8 vcm=1.6 −0.6 Offset DNL (LSB) 0.0 vcm=1.2 vcm=1.4 vcm=0.2 −0.2 0 −0. W Figure 28 Digital Offset DNL of Comp1 Comp2.2 0 −0.0 vcm=1.6 vcm=0.6 0.6 0.4 −10 −5 0 5 10 Digital Level. Digital Offset DNL 0.4 vcm=1.
4 vcm=1. Digital Offset DNL 0.Comp3.2 −0.4 vcm=1.8 0.8 vcm=1.0 vcm=1.8 −10 −5 0 5 10 Digital Level. Digital Offset DNL 1. W Figure 31 Digital Offset DNL of Comp4 54 .6 vcm=0.2 vcm=1. W Figure 30 Digital Offset DNL of Comp3 Comp4.6 0.4 −0.2 0 −0.4 −0.6 Offset DNL (LSB) 0.0 vcm=1.4 0.4 0.2 0 −0.6 −0.6 −10 −5 0 5 10 Digital Level.6 Offset DNL (LSB) 0.8 0.8 vcm=1.2 vcm=1.2 1 vcm=0.2 −0.
and thus has larger offset correction range. because Comp3 has worse internal offset to start. Comp4 has larger worstcase overall offset then Comp1 and Comp2 because Comp4 has not only worse DNL profile but also larger correction range (±220mV). From this comparison of the worstcase overall offset.3 WorstCase Overall Offset after compensation Ideally. the actual worstcase offset of Comp3 is four times larger. In other words. 55 . while the correction range of Comp1 and Comp2 is only ±150mV. the worstcase overall offset is calculated by 2 Effective number of bits dividing the biggest step between two digital levels in Figure 24 – Figure 27 by 2 because the worst situation is when internal offset lies at the middle of two digital offset levels.2. overall offset of a comparator after digital offset compensation is equal to maximum offset of the core comparator divided by 2(Number of bits correction). The large worstcase overall offset of Comp3 clearly shows that knowing only DNL is not sufficient. we conclude that Comp1 and Comp2 have the best compensation offset and Comp3 is the worst. Even though DNL of Comp3 is only two times larger than that of Comp1 and Comp2. we know that effective number of bits should replace the actual number of bit to capture the nonlinearity. we found that the maximum offset of the comparator should really be replaced by the offset correction range of the particular architecture. In addition to nonlinearity. The simulated results are shown in Figure 32. In simulation.3. In the previous section. the worstcase overall offset is approximated by Offset Correction Range .
The worstcase supply sensitivity of each comparator will be obtained in the end of this section. In this section.2. The overall supply sensitivity of an architecture is thus calculated by combining the supply sensitivity of internal offset in section 2. Similarly.4 1.Worst−case overall offset Worst−case offset(mv.2 1. simulations are performed to find the supply sensitivity on digital offset of each architecture. the input referred offset due to device mismatches changes with supply voltage.8 1 1.3 Supply Sensitivity As discussed in section 2. 56 . differential) 70 60 50 40 30 20 10 0 0.6 Comp1 Comp2 Comp3 Comp4 Input Vcm Figure 32 Worstcase overall offset 3.2 and the supply sensitivity on digital offset. the digital offset changes with supply as well.
8 1 1. diff) Noraml 10% Sup −10% Sup 10% Sup −10% Sup 10 110 100 90 80 70 0.4 1.diff) 90 80 70 60 50 0.2 Input Vcm (V) 1.4 1.6 50 0 −50 −100 0.Digital Offset of Comp1 130 120 Offset (mV.2 Input Vcm (V) 1.8 1 1.6 (a) (b) Figure 34 Supply Sensitivity on Offset of Comp2 Digital Offset of Comp3 700 600 Offset (mV.2 Input Vcm 1. diff) 1.6 20 Offset (mV.4 1.8 10 0 −10 1 −20 0.6 (a) (b) Figure 35 Supply Sensitivity on Offset of Comp3 57 .6 −10 0.2 Input Vcm 1.4 1.2 Input Vcm 1.4 1.4 1.6 (a) (b) Figure 33 Supply Sensitivity on Offset of Comp1 Digital Offset of Comp2 110 100 Noraml 10% Sup −10% Sup 30 Digital Offset of Comp2 10% Sup −10% Sup Change in Offset (mV.8 5 0 −5 1 1.diff) Digital Offset of Comp3 150 Change in Offset (mV.diff) Digital Offset of Comp1 15 Change in Offset (mV.8 1 1.8 1 1.2 Input Vcm (V) 1. diff) Noraml 10% Sup −10% Sup 10% Sup −10% Sup 100 500 400 300 200 100 0 0.
from normal supply.62V) “–10% Sup”.8V). because all sensitivities are not independent random variables.6 (a) (b) Figure 36 Supply Sensitivity on Offset of Comp4 In Figure 33 – Figure 36. Thus. the plots on the left (a) show maximum digital offsets of Comp1 – Comp4 when supply is “Normal”(1. Supply sensitivity due to digital offset compensation. because digital value is set to compensate the internal offset at the beginning.8 1 1. ∆VDigiOS. The plots on the right (b) show the change in offset. the overall supply sensitivity on offset can be found for each comparator.98V) “10% Sup”. Furthermore. 6σtotal. the calculation on overall supply sensitivity is not straight forward.2 Input Vcm (V) 1. which is the supply sensitivity on offset in mV. depends on the total internal offset of the comparator.4 1. 10% higher (1. the supply sensitivity on internal offset ∆σtotal must also depend on total internal offset 6σtotal.diff) Digital Offset of Comp4 15 Change in Offset (mV. diff) Noraml 10% Sup −10% Sup 10 5 0 −5 −10 −15 10% Sup −10% Sup 120 100 80 60 40 0. it is reasonable to state that ∆VDigiOS is proportional to internal offset.6 −20 0. ∆VDigiOS.Digital Offset of Comp4 160 140 Offset (mV.2 Input Vcm 1. Thus. However.8 1 1.4 1. On the other hand. supply sensitivity on digital offset ∆VDigiOS and supply sensitivity on internal offset ∆σtotal are correlated. and 10% lower (1. Having both supply sensitivities on offset due to internal mismatch and due to digital offset compensation. we know ∆σtotal is not directly proportional to total input offset 6σtotal because some mismatches have positive 58 .
2V for all 4 comparators. In this approximation. that is time required to reset a comparator whose differential output decreases from full VDD to 0. With this assumption. evaluation phase and reset phase. tdelay (Equation 14).4 Speed As described in section 2. we pretend that ∆VDigiOS and ∆σtotal are independent. 6σtotal. ∆VOS. reset time. To develop special treatments on accounting the correlation between variables seems to be out of scope of this project.SUP. treset. and t(@Vout=1. SUP = (∆V DigiOS ) + (∆σ ) 2 total 2 Table 5 shows the results of ∆VOS.2V) (Table 1) characterize the evaluation speed. speed of the core comparator is determined by the speed of two phases.3. regeneration time constant τ. A rough approximation on worstcase overall supply sensitivity is thus given here. In this 59 . may have low supply sensitivity.SUP* *Worstcase supply sensitivity (±10% Change in Supply) measured at VCM = 1. All these situations complicate the calculation of overall supply sensitivity of Comp1 − Comp4. ∆VOS. we can calculate worstcase supply sensitivity.supply sensitivity while the others have negative supply sensitivity. Comp1 Comp2 Comp3 Comp4 13mV 18mV 22mV 16mV Supply Sensitivity.5mV determine the reset speed. This causes a possibility that high internal offsets. In reset phase.2V Table 5 Worstcase Supply Sensitivity of Comp1 − Comp4 3. by: ∆VOS . In evaluation phase. ∆σtotal.SUP at VCM=1.
89 2. data for “Core Comp” is repeated from the speed of core comparator with the following configuration: Vcm=1. For evaluation phase.rst (GHz) 174 201 181 173 199 2.2V.section.9 33.49 2. in this section.1 Comparison on Speed of Different Architectures In each of the four architectures. and RST6=0×. The last subsection compares the linear and nonlinear scaling on digital compensation devices.8 176 211 200 210 211 2.5 24.77 2. RST1.2 58. Mclk=4×. the extra devices for compensation impact the speed. In order words.2V) (ps) fmax.1 33. Therefore.88 2.9 36.37 2. M3.84 2. the same measurements are repeated for each of the four comparators.38 2. M1.4=1×.4.6 47.8 33. The first subsection compares the speed of different architectures.2=2×. In Table 6. RST5=1×.6 38. D4D3 D2D1=0000 or D4BD3B D2BD1B=1111 in the case of Comp4.37 Reset Phase treset (ps) fmax. the comparator speed changes with the digital offset compensation settings. Moreover.4=1×. digital offset compensation architectures impact the 60 .51 Table 6 Speed Comparisons with Digital Offset Compensation Off Turning digital offset compensation off means setting digital offset be zero. RST3.8 53.50 2.2=1×. Digital Offset Compensation Off Architecture τ(ps) Core Comp Comp1 Comp2 Comp3 Comp4 Evaluation Phase tdelay(ps) T(@Vout=1. The second subsection discusses the penalty on digital offset compensation. 3. The effects of different digital settings will be presented next. speed of 4 comparators with zero digital offset will be first compared to the original speed of the core comparator.eva (GHz) 32.
4 65. specifically. Among four architectures. while we turn on digital compensation devices.6 24.1 37.23 2. dummy devices.62 2. all digital compensation devices are on.rst (GHz) 174 218 229 191 231 2. RST3. Comp2 is fastest with digital offset compensation off.8 176 238 224 189 232 2.8 66. we must force the comparators to have zero input referred offsets.9 35.84 2. Since the speed of a comparator depends on input magnitude.15 Reset Phase treset (ps) fmax. To do so. Digital Offset Compensation On Architecture τ(ps) Core Comp Comp1 Comp2 Comp3 Comp4 Evaluation Phase T(@Vout=1. which include MOS0 (Comp2 and 61 .2V) (ps) fmax. Hence when digital offset compensation is off. the reset speed is faster then the evaluation speed. Also.10 2. we know the reset speed with digital offset compensation off is so fast that it will not be the limiting factor of the speed of the comparator. The reset speed of Comp1 – Comp4 is optimized under the condition when digital offset compensation is on.8 34. RST6=1.5 32.5× and additional reset like RST7 and M7 (see schematic of Comp14). Therefore.7 36.65 2.17 Table 7 Speed Comparisons with Digital Offset Compensation On When digital offset compensation is turned on.speed of core comparator by 15%.4=1. as shown in Table 7 in the next subsection.6 72. Reset devices are intentionally made stronger.eva (GHz) tdelay(ps) 32. The reset devices are carefully sized so that the reset speed and evaluation speed is similar.19 2.88 2. This is expected because the digital compensation devices contribute parasitic capacitance and slow down the comparison. we must make sure that the input magnitude in this section is the same as that of last section.29 2.5×.
With the sampling rate under conditions of offset compensation on and off. Reset speed is designed to be closed to the evaluation speed for optimizing the sampling rate. we found that the maximum overall sampling rate of Comp1. 2. and dummy devices are turned on as if they were connected to D1 or D1B. With digital offset compensation. and 3 or D4BD3B D2BD1B=0000 for Comp4. and Comp4 slow down by 24% compared to the core comparator.15 Sampling Rate Reduction (%) 0% –26% –23% –16% –24% Table 8 Maximum Sampling rate of different architecture 62 . Architecture Core Comp Comp1 Comp2 Comp3 Comp4 Sampling Rate (GHz) 2.Comp3) and MC0 (Comp4).7% slower than the core comparator because Comp3 increases the total tail current. The percentage reduction on sampling rate compared to CoreComp is listed in the last column. digital offset compensation reduces the sampling rate of a comparator by 15% – 25%.84 2. The maximum overall sampling rates of all architectures are listed in Table 8. Comp2.10 2. Overall. are turned on at the same time to balance the comparator. whereas overall sampling rate of Comp3 is limited by compensation off condition. However. In short. so the evaluation speed of Comp1. more parasitic capacitance is added to the comparator. Comp3 is only 6. and Comp4 is limited by compensation on condition.19 2.38 2. Comp2. digital settings will be D4D3 D2D1=1111 for Comp1.
The dominant factor is the extra parasitic capacitances due to digital compensation devices.in degrades the integrating factor. of Comp1. say αISS. I1 = I2. Loss in Input Transconductance. the common idea is to add some devices to influence the current steering of input devices M1. the only important operating point is where the differential output current crosses zero.in. Another factor is the decrease in input transconductance. The decreasing gm. Comp2.2. 1 Assume the current through the extra device is a fraction of ISS.5ISS. 63 .e. gm. which have been discussed in the last subsection. total tail current is ISS. Let us take a simple differential pair and add an extra device to draw a constant current on one side. and Comp4. IM2 = 0.in I1 I2 IM2 M2 W L ISS αISS VCM MOS VCM + 2 ∆Vin IM1 M1 W L ∆Vin VCM – 2 Figure 37 Illustration of input transconductance loss In Comp1. and Comp4. Hence. The speed penalty of Comp1.2 Speed Penalty of Digital Offset Compensation This section only applies on Comp1. Comp2. as shown in Figure 37. where α ≤ 2 . and Comp4 is caused by several factors.4. We will carefully examine why input transconductance reduces in this section. and thus the evaluation response is degraded. Comp2. gm.3. For comparator. i. Comp3 is actually faster when digital offset compensation is on because of its split current architecture.2.4 with increasing digital offset. In addition.
5 − α )I SS + 2µ n COX W (0. 64 . If α is small.5 – α) ISS. g 2 m. the 2 1 input transconductance is lost by 2 α.5 I SS )∆Vin . W (0. then idiff = g m1. we can approximate the fraction ( 1 − 2α + 1) with first order Taylor series. In Equation 15 the first term αISS is the offset created by MOS.and IM1 = (0. 2 ( I D = 0. ∆Vin ∆Vin idiff = i1 − i2 = αI SS + g m1 − − g m2 2 2 idiff = αI SS + ( g m1 + g m 2 ) ∆Vin 2 We can then find gm1 and gm2 by substituting IM1 and IM2. Furthermore. which is the case without digital offset compensation. creating small differential current idiff. Small differential voltage ∆Vin is applied to the inputs. This means that if a fraction α of ISS is used in digital offset compensation. even though parasitic is not taken into account.in. which gives 2 1 1 − α . This also tells us that a comparator with larger offset will have a slower speed. the input referred noise will increase as digital offset increases. and the fraction ( 1 − 2α + 1) is the factor of loss in input transconductance.5I SS ) ∆Vin idiff = αI SS + 2µ n C OX 2 L L Equation 15 idiff = αI SS + ( 1 − 2α + 1) 2 W (0.5I SS ) ∆Vin 2µ n C OX L If α = 0.
10 Reset Phase treset (ps) fmax. with 4bit linear scaling (schematic is same as Figure 38 except that one more bit correction is needed). we know how well the 4bit nonlinear scaling improves the performance.8 73.3.4.9 72.eva (GHz) tdelay(ps) 34.15 1.0 106.8 35.4 233 310 238 2. we will compare Comp1 with 3bit linear scaling as shown in Figure 38.7 42.2V) (ps) fmax.62 2.31 2.3 Comparison on Linear and Nonlinear scaling When Comp1 was being designed. and with 4bit nonlinear scaling as shown in Figure 20.rst (GHz) 216 383 218 2. Hence. VDD clk clk RST3 4 2 M5 4 2 RST1 4 2 RST5 4 2 RST2 4 2 M6 4 2 RST4 4 2 clk Vout1 M3 4 2 Vout2 M4 4 2 VCM ×1 ×1 ×1 ×1 ×2 ×2 Invbot1 Vin1 M1 8 2 clk 4 RST6 2 Mclk 16 2 M2 8 2 Invbot2 Vin2 ×4 ×4 VCM D3 D1 D2 Figure 38 Schematic of Comp1 with 3bit linear scaling Evaluation Phase T(@Vout=1. In this section.32 1.29 Architecture τ(ps) 3bit Linear 4bit Linear 4bit Nonlinear Table 9 Speed Comparisons on linear and nonlinear scaling of Comp1 65 . we found that a linear 4bit scaling on digital offset compensation severely degraded the comparator performance.
In the current setting. we expect that the power consumption of the 4bit nonlinear version is similar to that of the 3bit linear version as well. all parasitic capacitances due to digital compensation are added to the comparator and large portion of total current is used for offset compensation. we decided to use the 4bit nonlinear version and sacrifice 0. we control the whole (both left and right) digital compensation in a single binary array. so the speed of the comparator can be improved. Moreover. We can improve the speed by changing the digital coding scheme.From Table 9. the performance is very closed to that of the 3bit linear version. 66 . and the worst case is during compensating for −1LSB offset. With the speed and power benefit.5LSB nonlinearity as shown in Figure 28. if we choose to control the left and right digital compensation separately. The loss in input transconductance is also reduced. we know that digital offset compensation could reduce the speed by 15% – 25%. the worstcase becomes turning on all devices on one side only. which means we need digital signal D3L D2L D1L for left and another D3R D2R D1R for right hand side. 4bit linear scaling version performs poorly in both evaluation phase and reset phase. Both speeds are almost half of the speeds that the 3bit version has. which corresponds to turning on all compensation devices. As a result. Since we reduce the number of active devices by half. After comparing the speeds for digital compensation both off and on and understanding the origin of speed penalty of digital offset compensation. On the other hand. In the 4bit nonlinear version. we halve not only parasitic capacitance but also the current flowing through digital compensation devices.
However. all four comparators do not increase input capacitance. Hence. 3.6 Power Consumption Similar to the speed issue. 3. and the second case is when digital offset compensation is on.5 Input Capacitance As shown in schematics Figure 20 − Figure 23.6. since digital offset compensation devices add parasitic capacitance on the comparator. In applications of high order parallelism. The total power of comparator and clocking will be discussed in the last subsection. In the first subsection. VCM is a DC value or a low frequency signal. Fortunately. the VCM driver is usually shared among all comparators. Clock loading and power consumed on driving clock is discussed in the second subsection. we separate our discussion into 2 cases. The first case is when digital offset compensation is off. As in the speed section.1 Power of Comparators Digital Offset Compensation Off When digital offset compensation is off. extra driver can be simple. Depending on applications. The little extra hardware on VCM driver and the small input capacitance make the digital offset compensation attractive in applications with high order parallelism. power consumption of each comparator is compared with that of core comparator.3. the comparator’s switched 67 . power consumption of each comparator is more than that of core comparator. Comp1 and Comp2 need an extra terminal VCM. an extra driver may be needed to generate VCM.
because again the digital compensation devices are smaller than that of Comp1 and Comp2.2. which are closed to that of core comparator.5GHz. CgsMcm16. and thus capacitances CgdMcm16. Digital Offset Compensation On When digital offset compensation is on.capacitance does not include the channel capacitance.8V supply. Comp1 and Comp2 have comparable power consumptions. Comp4 is interestingly the lowest power consuming. closed to the power consumption of the core comparator. The power consumption is. under the condition of digital offset compensation off. and CgdMos16 are added to invbot1. more capacitances are added on the comparator. As a result.5GHz. Comp4 dissipates more power because both source and drain overlap capacitances are added on node invbot1. its overlap capacitance plus the gate capacitance is thus the smallest. 1. 1. The power consumption thus increases. only source/drain overlap capacitances are added to the comparator. Figure 40 shows the power consumption of all comparators operating at 1. Note that by adding digital offset compensation. thus. power consumption of Comp1 is largest. Comp1 has the largest power consumption because MCM16 are always on.8V supply. operating at 1. the power consumption is at least double to that of core comparator. However. Comp2 and Comp3 have similar power consumptions. Figure 39 shows power consumption of all comparators.2. Comp3 is the second least power consuming. The reason is that Comp4 uses the smallest size devices for digital offset compensation. 68 .
2 1.6 1.4 1.Power Consumption with Digital Compensation Off 300 CoreComp Comp1 Comp2 Comp3 Comp4 250 Power (uW) 200 150 100 50 0.4 1.8 Vcm (V) Figure 40 Power Consumptions with Digital Offset Compensation On 69 .6 1.8 1 1.2 1.8 CoreComp Comp1 Comp2 Comp3 Comp4 Power (uW) 1 1.8 Input Vcm (V) Figure 39 Power Consumptions with Digital Offset Compensation Off Power Consumption with Digital Compensation On 350 300 250 200 150 100 50 0.
5fF 37. Clock Load Capacitance Clocking Power Core Comp Comp1 Comp2 Comp3 Comp4 10.6fF 12.5fF 52. to find the power consumed on driving the clock. we halved the extra parasitic capacitance. Power calculation is based on 1.8µW Table 10 Power of Clocking 70 . Comp2.6.8µW 183µW 60. we again suggest to control the left part and right part of digital compensation separately. 3.5GHz.2 Power of Clocking Power of clocking is mainly due to charging and discharging the clock load capacitance. and Comp4 have the same clock load capacitance. we can simply find the clock load capacitance.9fF 12. As we explained at the end of speed section. and thus the power consumption can be greatly reduced.By noticing the increase in power consumption when digital compensation is on.5fF 12. It is obvious that Comp1.9µW 60. and the corresponding clocking power. by turning on only left or right devices. Table 10 shows the clock load capacitance of each comparator. Comp3 has large clock load capacitance because of its digital offset compensation structure. Thus.8µW 60.8V supply operating at 1.
6. Since clocking power of Comp3 is much larger than others. digital offset compensation increases the power consumption by 60% to 160%.4 1. Total Power Consumption with Digital Compensation Off 350 CoreComp Comp1 Comp2 Comp3 Comp4 300 Total power (uW) 250 200 150 100 0. 1. and Comp4 is the least power consuming when digital compensation is on. Comp2 is the least power consuming when digital compensation is off.8V supply.8 Input Vcm (V) Figure 41 Total Power Consumption with Digital Compensation Off 71 .5GHz clock.6 1. operating condition is 1. Overall. Again. Comp3 becomes the most power consuming comparator among four architectures.3. Figure 41 shows the total power consumption when digital compensation is off.3 Total Power The total power is calculated by summing the power of comparator itself and power of clocking.8 1 1. Figure 42 shows the total power consumption when digital compensation is on.2 1. greatly depending on the choice of architecture.
2 1.4 1.6 1.8 Vcm (V) Figure 42 Total Power Consumption with Digital Compensation On 72 .Total Power Consumption with Digital Compensation On 500 450 CoreComp Comp1 Comp2 Comp3 Comp4 Total Power (uW) 400 350 300 250 200 150 100 0.8 1 1.
and power have been compared in detail.5bit 13mV Comp2 8 – 13mV 3. speed. Table 11 shows the summary of the performances. Offset compensation ability. Performance Worstcase Offset Effective number of bit correction Worstcase Supply Sensitivity on Offset* Sampling Rate (%Reduction) Input Capacitance Power** (% Increase) Core Comp Comp1 60 – 140mV 8 – 14mV N/A 10mV 3.19GHz (–23%) 1fF 2. Comp1 and Comp2 are suitable in high accuracy applications.7 Quick Summary of Comparison In summary. we have compared the performances of 4 digital offset compensation architectures.2V ** Power consumption in VCM range 0.2bit 16mV 2.38GHz (–16%) 1fF 2.3. while Comp4 is suitable in low power system.6V Table 11 Performances Rating of Comparators 73 .8V ≤ VCM ≤ 1.15GHz (–24%) 1fF 142–175µW 213–390µW 238–400µW 328–460µW 168–280µW (50–120%) (67–129%) (130–160%) (18–60%) *Worstcase supply sensitivity (±10% change in supply) measured at VCM = 1.5bit 18mV Comp3 7 – 65mV 3bit 22mV Comp4 9 – 21mV 3.10GHz (–26%) 1fF 2.84GHz 1fF 2. supply sensitivity. input capacitance.
20 Comp3. while Comp3 has larger internal offset.1 Measured Internal Offset Due to Device Mismatches As you can see from the schematics. and 20 Comp4 in the same chip. and Comp4 have similar internal offset. In the test chip. As a result.Chapter 4 Circuit Performance All four architectures have been fabricated in 0. Comp2.1. while Comp3 has split tail current architecture. and worstcase overall offset respectively.1 Accuracy In each of the following subsections. there are 20 Comp1.8V CMOS technology. we will present the measurements of internal offset. each architecture is duplicated 20 times. linearity of digital offset. Therefore. Comp2. 20 Comp2. Comp1. and Comp4 share the same core comparator. Thus. Since this project emphasizes on offset compensation. Comp1. digital offset. 4. 4. we are able to collect statistical data from the chip.18µm 1. only offset of the comparators have been measured. 74 .
Comp1 Internal Offset measurements 150 100
Measured Offset, (mV, diff)
Data Points Average +/− 3 sigma Theoretical bounds
50 0 −50 −100 −150 −200 0.8
0.9
1
1.1
1.2 1.3 Vcm (V)
1.4
1.5
1.6
Figure 43 Measured Internal Offset of Comp1
Comp2 Internal Offset measurements 150 Data Points Average +/− 3 sigma Theoretical bounds
100
Measured Offset, (mV, diff)
50
0
−50
−100
−150 0.8
0.9
1
1.1
1.2 1.3 Vcm (V)
1.4
1.5
1.6
Figure 44 Measured Internal Offset of Comp2
75
Comp3 Internal Offset measurements 300 200 Data Points Average +/− 3 sigma Theoretical bounds
Measured Offset, (mV, diff)
100 0 −100 −200 −300 −400 0.8
0.9
1
1.1
1.2 1.3 Vcm (V)
1.4
1.5
1.6
Figure 45 Measured Internal Offset of Comp3
Comp4 Internal Offset measurements 150 100 Data Points Average +/− 3 sigma Theoretical bounds
Measured Offset, (mV, diff)
50 0 −50 −100 −150 −200 −250 0.8
0.9
1
1.1
1.2 1.3 Vcm (V)
1.4
1.5
1.6
Figure 46 Measured Internal Offset of Comp4
76
In the figures above, “Data points” represent the offset of each duplicated comparator. Thus, there should be 20 data points at the same VCM. “Average” represents the average value of all data points at that VCM. “+/− 3sigma” is the ±3 × (standard deviation σ) calculated statistically from data points. “Theoretical bounds” is ±3 × (standard deviation σ) obtained from simulations. In all four figures above, we can see that the internal offset tends to negative. This negative trend is mainly due to layout asymmetry of the comparator itself. If you neglect the offset due to layout asymmetry, the range of “+/− 3sigma,” which is obtained from real circuits, is closed to the range of “Theoretical bounds,” which are obtained from simulations. This verifies that the analysis in chapter 2 accurately predicts the offset of the comparator.
4.1.2 Measured Digital Offset Compensation
Since there is inaccuracy in the simulation model, the performance of the real circuit implementation deviates from the simulations presented in Chapter 3. The errors on estimating parasitic capacitance in simulations are typically high. The incorrect parasitic capacitance model will lead to large performance impact in digital offset compensation. This will be discussed in detail for each comparator. Figure 47 shows the measured digital offset of Comp1. It is obvious that the correction range obtained in measurements is larger than that in simulations. We found that the simulations overestimated the parasitic capacitance. As a result, all transistors in real implementation have more drive strength than those in simulations. Consequently, the digital offset magnitude of Comp1 in real circuits, which is shown in Figure 47,
77
In addition. 78 . corresponding to all odd digital levels. Figure 47 shows that the offsets created by LSB. simulated digital offsets increase fairly linearly with VCM. In addition to error in correction range. thus the current flowing through the LSB branch is less sensitive to VCM. the drawback of Comp1 is its nonlinearly scaling devices on digital offset compensation. the offset magnitude does not change rapidly over wide range of VCM. The different behaviors between the 1st LSB and the 2nd LSB degrade the linearity of the digital offset compensation. but measured digital offsets are fairly constant over wide range of VCM. approach more to a constant than the offsets created by 2nd LSB. and thus.covers a larger range than shown in the simulations of Figure 24. It is because LSB is created by MCM1 and MOS1AB. It is expected that the LSB. corresponding to all even digital levels. The intuitive understanding on the structure of Comp1 actually predicts that the digital offset is quite insensitive to the change in VCM. the current flowing through each branch is regulated by the small feedback mechanism. The linearity will be discussed in next section. This effect clearly shows up in Figure 47. Comp1 stacks 2 transistors in series as if degenerating the top transistor MCM16 by the bottom transistor MOS16 (see schematic Figure 20). which form larger degeneration. D1 has different characteristic from other bits do. The created offset is also regulated. As a result.
2 1.6 Vcm (V) Figure 48 Measured Digital Offset of Comp2 79 . (mV.8 0. diff) 200 100 0 −100 −200 −300 −400 0.4 1.1 1.2 1.4 1.8 0.9 1 1.6 Vcm (V) Figure 47 Measured Digital Offset of Comp1 Comp2 Measured Digital OS compensations 400 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 −7 −8 300 Measured Offset.3 1.9 1 1. (mV. diff) 100 50 0 −50 −100 −150 −200 0.1 1.3 1.5 1.5 1.Comp1 Measured Digital OS compensations 200 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 −7 150 Measured Offset.
9 1 1.4 1.5 1. diff) 20 10 0 −10 −20 −30 −40 0.6 Vcm (V) Figure 49 Measured Digital Offset of Comp3 Comp4 Measured Digital OS compensations 40 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 −7 −8 30 Measured Offset.5 1.4 1. (mV. (mV.2 1.8 0. diff) 200 0 −200 −400 −600 0.3 1.1 1.Comp3 Measured Digital OS compensations 600 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 −7 −8 400 Measured Offset.1 1.9 1 1.3 1.6 Vcm (V) Figure 50 Measured Digital Offset of Comp4 80 .8 0.2 1.
while simulation expects the maximum digital offset of more than 200mV.2. the maximum digital offset created by Comp4 is only about 40mV. The large nonlinearity also clearly shows up in real circuits. the real measured digital offset is larger than the simulated digital offset by more than 100%. Figure 49 shows the measured digital offset of Comp3. level 3 (3 LSB) and level 4 (4 LSB) cross over with each other. Comp2 creates offset similar to a β mismatch of M1. By carefully inspecting all 16 digital offset levels. Note that simulation shown in Figure 25 incorrectly predicts that digital offset stays constant in high VCM. The same problem occurs in –4 and –5. The inaccurate parasitic capacitance model affects the performance of Comp4 the most. The measured circuit performance of Comp3 deviates the least from simulation results. the finite precision of the equipments leads to difficulties in offset measurements. Notice the similarity of “beta1” in Figure 15 with Figure 48.Figure 48 shows the measured digital offset of Comp2. Figure 50 shows the measured digital offset of Comp4 with large measurement uncertainty. In Figure 50. The stronger drive strength in actual devices shows up clearly in measured digital offset of Comp2 in Figure 48. which is caused by the same transition from 3LSB to 4LSB. In high VCM. The difference between Comp1 and Comp2 is especially clear with measurements. smaller offsets are resulted. All capacitances due to MC04 are smaller in the fabricated chip. Figure 50 shows the measured digital offset of Comp4. Because of the small magnitude of digital offset. The digital offset in real implementation is only slightly larger than that in simulation. 81 . thus. We suspect that the dummy capacitor MC0 in Figure 23 does not match with other capacitors in layout.
Note that the “zig zag” pattern shows up in measurement as well. From Figure 52.1. 82 . Simulations can also predict the compression of the step size of offset compensation. DNL of each comparator is calculated from the digital offset measurements in the previous section. With a lot of difficulties in precise measurements. we will not have further discussion on this. if VCM is below 1.8 LSB.4V. Thus. the measured DNL profile of Comp4 is not very meaningful. This suggests that it is better to operate Comp1 at low or moderate VCM.3 Linearity Linearity will directly affect the effective number of bits correction. the DNL is less than 0.5 LSB. However. In real circuits. we confirm that Comp2 has DNL approximately 0. Comp3 has the worst DNL profile.4. the worst DNL is almost 1. Unlike digital offset measurements. The measured DNL profile of Comp3 is also very similar to the simulation results. measured DNL of Comp2 is much more similar to the simulation results. and is the best among four comparators. and the DNL profiles are shown in Figure 51 − Figure 54.5 LSB. as predicted in simulations. The measured DNL of Comp1 increases to 1 LSB.
6 0.4 vcm=1.2 0 −0.2 −0.6 −6 −4 −2 0 2 4 6 8 Digital Level.2 vcm=1.4 vcm=1.4 Offset DNL (LSB) 0.6 −0.8 −1 −8 vcm=0.6 −0.4 −0.8 vcm=1.2 Offset DNL (LSB) 0 −0. W Figure 51 Measured DNL of Comp1 Comp2 Measured Digital Offset DNL 0.4 0.0 vcm=1.2 −0. W Figure 52 Measured DNL of Comp2 83 .Comp1 Measured Digital Offset DNL 0.8 0.8 vcm=1.2 vcm=1.6 0.6 −6 −4 −2 0 2 4 6 8 −0.4 vcm=0.8 −8 Digital Level.0 vcm=1.
5 1 0.4 vcm=1.4 vcm=1.5 Offset DNL (LSB) 0 −0.6 −6 −4 −2 0 2 4 6 8 −1 −8 Digital Level.Comp3 Measured Digital Offset DNL 1.5 −1 vcm=0.8 vcm=1.5 0 −0.2 vcm=1. W Figure 53 Measured DNL of Comp3 Comp4 Measured Digital Offset DNL 1.5 vcm=0.6 −6 −4 −2 0 2 4 6 8 −1. W Figure 54 Measured DNL of Comp4 84 .5 −2 −8 Digital Level.8 vcm=1.0 vcm=1.2 vcm=1.0 vcm=1.5 1 Offset DNL (LSB) 0.
worstcase overall offset is eventually the most important metric and it tells which comparator has higher accuracy. We can find only 3 comparators that have small enough offset to compensate.4. Because of the inaccurate capacitance model in simulations. “Worstcase offset” is the worst possible offset of a comparator. As a result. because Comp4 has very limited correction range. since four comparators in this test chip have different ranges of corrections. Figure 59 shows the worstcase offsets of all four comparators in one plot. Comp2 has larger worstcase offset than expected. all “Data Points” are bounded by the “Worstcase offset. we will neglect Comp4. Since Comp4 has too narrow correction range.” In Figure 58. Comp3 still performs the worst in offset compensation. and it is calculated by finding the biggest separation between two digital levels in measured digital offset from Figure 47 – Figure 50. Comp1 provides lowest offset in this test chip.4 Worstcase Overall Offset When four comparators have similar range of digital offset compensation. However. Finally. DNL and worstcase overall offset give the same results. In Figure 55 – Figure 58. “Data Points” are the actual offset of the duplicated comparators on chip after digital offset compensation. and most duplicated comparators have offset larger than its correction range.1. there are only 3 “Data Points” for offset of Comp4. 85 .
6 Vcm (V) Figure 55 Measured Offset of Comp1 after Digital Compensation Comp2 Measured Offset after Digital compensation 40 Worst−case Offset Data Points 30 Measured Offset.3 1.9 1 1.2 1. (mV.1 1.Comp1 Measured Offset after Digital compensation 25 20 15 Worst−case Offset Data Points Measured Offset.5 1. diff) 20 10 0 −10 −20 −30 −40 0.6 Vcm (V) Figure 56 Measured Offset of Comp2 after Digital Compensation 86 .9 1 1. (mV.2 1.3 1.4 1.8 0. diff) 10 5 0 −5 −10 −15 −20 −25 0.1 1.8 0.5 1.4 1.
9 1 1.5 1.2 1. diff) 2 0 −2 −4 −6 −8 0.4 1.9 1 1.3 1.6 Vcm (V) Figure 58 Measured Offset of Comp4 after Digital Compensation 87 .4 1.1 1.6 Vcm (V) Figure 57 Measured Offset of Comp3 after Digital Compensation Comp4 Measured Offset after Digital compensation 6 Worst−case Offset Data Points 4 Measured Offset. (mV.2 1.1 1.8 0.3 1. (mV. diff) 40 20 0 −20 −40 −60 −80 0.5 1.Comp3 Measured Offset after Digital compensation 80 Worst−case Offset Data Points 60 Measured Offset.8 0.
diff) 60 50 40 30 20 10 0 0.4 1.9 1 1.5 1.8 0.1 1.3 1.Measured Worst−case Overall offset 80 70 Comp1 Comp2 Comp3 Comp4 Measured Offset.2 1.6 Vcm (V) Figure 59 Comparison on worstcase offset 88 . (mV.
Chapter 5 Applications of Comparators The comparators designed in this project are optimized for high order parallelism. Thus. we are going to design a N bit multiphase flash ADC. a brief ADC design example is shown for illustrating the application of comparators with digital offset compensation. For ADC design. In a singlephase flash ADC. we need to 89 . 5. flash ADC or oversampler usually require a large number of comparators in parallel in the first stage. the comparators should have small input capacitance. comparator must fulfill the accuracy requirement as well. low power consumption. In the coming section.1 Application of Comparators on Multiphase Flash ADC VFS Vin Nbit ADC φ1 N Vin COMP COMP Nbit ADC φ2 N COMP 2N • • Nbit ADC N • • COMP clk φP Figure 60 Block Diagram of Multiphase Flash ADC To illustrate the application of comparators on Flash ADC architecture. For example.
especially speed of comparator fcomp.overall = VOS . φ2. Since there are 2N comparators in a singlephase flash ADC and there are p flash ADC in parallel. and input capacitance of comparators. Each flash ADC is triggered by different phase. for example. p singlephase flash ADC in parallel. With a designed input device size. we can obtain the sampling frequency by modeling the sampling action as a simple RinCin circuit.place 2N comparators in parallel in the first stage.mismatch Effective number of bits corrections Effective number of bits corrections depends on DNL of offset compensation. we know the maximum offsets due to device mismatch by using techniques developed in chapter 2. we use small transistor size for input device M1. we have total (2N)p comparators connected to 90 . which is explained in chapter 3. After the design of the comparator is done. we need to design a comparator with required accuracy. channel. The block diagram is shown in Figure 60. The design of a comparator ends at this point. VOS . First of all. and Cin is the sum of capacitances due to pads. say minimum size or 2× minimum size. we place. By applying digital offset compensation. where Rin = 25Ω for end termination configuration. we can design appropriate reset devices. We can then obtain the performance metrics of the comparator. we can reduce the input referred offset to fulfill the required accuracy.2. Since we know we are going to place a large number of comparators in parallel in the first stage. by simulations. In short. To push the speed performance. After number of bits corrections on offset is designed.…φP. φ1.
fcomp. When p < po. The optimum speed is where fADC = fSAMP. fADC limits the speed of the ADC. Thus. fSAMP limits the maximum speed. etc.comp .total = Cpad + (2N)(p)Cin.comp p 2 + (C pad ) p − ) 1 =0 ln 2( N + 1)Rin f comp 91 . and Cin. fADC. as shown in Figure 61.5 LSB = 2N+1 . The settling time. sampling frequency is Equation 17 f SAMP = 1 TSAMP = 1 ln 2( N + 1)Rin C in Meanwhile. Both fADC and fSAMP depend on p.comp is the input capacitance of the comparator. comparators can only operate up to its maximum speed. where Cpad includes any fixed capacitances due to pads. can be calculated by e − TSAMP Rin Cin ≤ 1 2 N +1 ⇒ TSAMP = ln 2( N + 1)Rin C in As a result. = p×fcomp. For proper operation. f ADC = f SAMP ⇒ pf comp = 1 ln 2(N + 1)Rin C in Equation 18 (2 N C in . This sets a quadratic equation for p. Equation 16 Cin. which is equal to the sampling time TSAMP. we need to let input voltage VFS settle within 0. where VFS is fullscale voltage of ADC. channels. Thus the maximum operating frequency of pphase flash ADC. when p > po..the input. and they set the speed bounds of the ADC.
or by using distributed capacitance technique to increase the input sampling bandwidth. p Figure 61 Speed of 6bit pphase Flash ADC Hence. as we can still increase the performance by using a multistage ADC to decrease the total input capacitance. More design issues on those techniques seem out of scope of this paper. we can always solve for Equation 18 to obtain the optimum speed of a pphase flash ADC.Speed of 6bit pphase Flash ADC 14 12 Speed (GS/sec) 10 8 6 4 2 0 0 2 po 4 6 fadc fsamp Number of parallel ADC. 92 . The optimum speed can tell us the fundamental speed limit of a pphase flash ADC architecture. This is just a simple example.
we can compare comparators with different architectures. supply sensitivity. and we identify the 6 different sources that contribute to offsets. so we know the fundamental limit of the accuracy of a comparator. and power. In general. while Comp4 is a good alternative because of its low power consumption. We know how to size the transistors to achieve higher speed on both evaluation and reset. comparators with different offset compensation. In the second section (Chapter 3). Effective number of bits 93 . The 3 sections are characterization of core comparator (Chapter 2).Chapter 6 Conclusion This project can be mainly divided into 3 big sections. We are able to roughly estimate the supply sensitivity on offset. A set of formulas is developed to calculate input referred offset. With these metrics. and we understand how each source varies with VCM. input capacitance. (Chapter 2). In addition. Based on the performance metrics developed in chapter 2. we compare four comparators with different digital offset compensation. In the first section. speed. and chip performance (Chapter 4). this architecture has small input capacitance and power consumption [2]. core comparator is characterized. The performance metrics of a comparator are input referred offset. we created Table 11 to summarize the comparison of digital offset compensation. digital offset compensation can reduce the input referred offset from 140mV to 13mV. comparison of comparators with digital offset compensation (Chapter 3). Comp2 has the best offset compensation ability because of its linearity. and the tradeoffs of using digital offset compensation.
5LSB). and Comp3 have offset correction range larger than that obtained from simulations. We found that simulations overestimated the parasitic capacitance. Moreover. Input capacitance is less than 1fF. however. Comp4 has offset correction range less than expected. We verified that the analysis for internal offset could predict the offset of a comparator. we are able to find the optimum speed of a pphase flash ADC. the sampling rate is only reduced by 15 – 25%. Comp2. In the third section (Chapter 4). We have developed a method to design transistor size of comparators and number of bit corrections for comparators. transistors have more drive strength. and Comp3 gives the worst DNL (1. 1. In addition. In the end of this project.8V CMOS technology. 94 . we showed that comparators with digital offset compensation have high potential on applications with high order parallelism. Since this project emphasizes on offset compensation. we also give a simple example to illustrate how to apply comparators with digital offset compensation in real implementation. all four comparators are implemented in 0. By adding digital offset compensation. As a result. Comp1.5 bit from a 4bit architecture. With this example. thus. only offset measurements are performed. Comp2 gives the best DNL (0.correction can be ranged from 3 – 3.5LSB).18µm. and power consumption increases by 60 – 160%.
K.. and Welbers. T. A. W. 1989.Reference [1] Pelgrom. C. pp. ix+322 pp. vol. Wooley. D. A.A.. 1997. W.9016. "Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs. Feb 2000.4).P.12).. "A 12b 5Msample/s twostep CMOS A/D converter. Ho. B. M. vol. vol. 95 . Soc. [6] Ellersick.211." 1999 Symposium on VLSI Circuits Digest of Papers. p. pp. 2523. B. “Matching properties of MOS transistors. pp. "Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology].23. Horowitz." 2000 ISSCC Digest of Technical Papers. Yang.. "An eight channel 36 GSample/s CMOS timing analyzer.. Dally. "A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation. M.. R. [2] Razavi. 4952.” IEEE Press. Feb 2000.27. B. K.. 1701. (no.. p. “Principles of Data Conversion system Design. M. Dally.K." IEEE Journal of SolidState Circuits. [8] Lee.M." IEEE Journal of SolidState Circuits. "GAD: A 12GS/s CMOS 4bit A/D converter for an equalized multilevel link.. Dec. Horowitz. W.. [7] Weinlader.. C. pp. (no.E. IEEE Comput.J.K. [5] Sakurai. [4] Razavi.G.W." 2000 ISSCC Digest of Technical Papers.14331440. Duinmaijer.” IEEE Journal of SolidState Circuits. 1988... SC24. p... 1995. [3] Dobberpuhl." Seventeenth Conference on Advanced Research in VLSI.J.. Aug. 1992. P. Chiang. Yang. pp.166778.. D.C. June 1999. 17781.J. M.
This action might not be possible to undo. Are you sure you want to continue?
We've moved you to where you read on your other device.
Get the full title to continue reading from where you left off, or restart the preview.