1d
1d
Y YB
2
V
Ref
+
V
Ref

V
Ref

2C
2C
C
C
1d
1d
Y YB
V
Ref
+
Y YB
V
Ref

1
V
Ref
+
V
Ref

Y YB
+

2
2C
2C
C
C
1
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4003
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98db AnalogDigital Converter
a
1
z  1
b
1
a
2
z  1
b
2
a
3
z  1
a
4
z  1
1bit
A/D
1bit
D/A
E
y
4
Y
y
3
y
2
y
1
X
Fig. 10.1006
where a
1
= 1/3, a
2
= 3/25, a
3
= 1/10, a
4
= 1/10, b
1
= 6/5, b
2
= 1 and = 1/6
Advantages:
The modulator combines the advantages of both DFB and DFF type modulators:
Only four op amps are required. The 1st integrators output swing is between V
REF
for large input signal amplitudes (0.6V
REF
), even if the integrator gain is large (0.5).
A local resonator is formed by the feedback around the last two integrators to further
suppress the quantization noise.
The modulator is fully pipelined for fast settling.
A.L. Coban and P.E. Allen, A 1.5V, 1mW Audio Modulator with 98dB Dynamic Range, Proc. of 1999 Int. SolidState Circuits Conf., Feb.
1999, pp. 5051.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4004
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Integrator power dissipation vs. integrator gain
DR = 98 dB
BW = 20 kHz
C
s
= 5 pF
0.5 m CMOS
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4005
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98db AnalogDigital Converter  Continued
Modulator power dissipation vs. oversampling ratio
Suppy
Voltage (V)
DR = 98 dB
BW = 20 kHz
Integrator gain = 1/3
0.5m CMOS
OSR = 64
OSR = 32
OSR = 16
OSR = 8
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4006
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Circuit Implementation:
Capacitor Values
Capacitor Integrator 1 Integrator 2 Integrator 3 Integrator 4
C
s
5.00pF 0.15pF 0.30pF 0.10pF
C
i
15.00pF 1.25pF 3.00pF 1.00pF
C
a
  0.05pF 
C
b1
   0.12pF
C
b2
   0.10pF
Fig.10.925
1
1d
2
2d
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4007
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Microphotograph of the modulator.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4008
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Measured SNR and SNDR versus input level of the modulator.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4009
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Measured baseband spectrum for a 7.5dBr 1kHz input.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40010
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Measured baseband spectrum for a 80dBr 1kHz input.
80 dBr, 1 kHz signal
VREF = 1.5 V (diff.)
2048point FFT
frequency, (kHz)
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40011
CMOS Analog Circuit Design P.E. Allen  2010
1.5V, 1mW, 98dB AnalogDigital Converter  Continued
Measured 4thOrder Modulator Characteristics:
Table 5.4
Measured fourthorder deltasigma modulator characteristics
Technology : 0.5 m triplemetal singlepoly nwell CMOS process
Supply voltage 1.5 V
Die area 1.02 mm x 0.52 mm
Supply current 660 A
analog part 630 A
digital part 30 A
Reference voltage 0.75V
Clock frequency 2.8224MHz
Oversampling ratio 64
Signal bandwidth 20kHz
Peak SNR 89 dB
Peak SNDR 87 dB
Peak S/D 101dB
HD @ 5dBv 2kHz input 105dBv
DR 98 dB
3
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40012
CMOS Analog Circuit Design P.E. Allen  2010
DECIMATION AND FILTERING
DeltaSigma ADC Block Diagram
The decimator and filter
are implemented digitally
and consume most of the
area and the power.
Function of the decimator
and filter are;
1.) To attenuate the
quantization noise above the baseband
2.) Bandlimit the input signal
3.) Suppress outofband spurious signals and circuit noise
Most of the ADC applications demand decimation filters with linear phase
characteristics leading to the use of finite impulse response (FIR) filters.
FIR filters:
For a specified ripple and attenuation,
Number of filter coefficients
f
s
f
t
where f
s
is the input rate to the filter (clock frequency of the quantizer) and f
t
is the
transition bandwidth.
Fig.10.907
Modulator
(Analog)
Decimator
(Digital)
Lowpass Filter
(Digital)
f
S f
D
<f
S
Analog
Input
x(t)
f
B
2f
B
Digital
PCM
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40013
CMOS Analog Circuit Design P.E. Allen  2010
A MultiStage Decimation Filter
To reduce the number of stages, the decimation filters are implemented in several stages.
Typical multistage decimation filter:
Fig.10.926
L+1th
order
f
s
f
s
/D 2f
N
f
N
Firsthalf
band filter
Secondhalf
band filter
f
N
Droop
correction
1.) For modulators with (1z
1
)
L
noise shaping comb filters are very efficient.
Comb filters are suitable for reducing the sampling rate to four times the Nyquist
rate.
Designed to supress the quantization noise that would otherwise alias into the
signal band upon sampling at an intermediate rate of f
s1
.
2.) The remaining filtering is performed by in stages by FIR or IIR filters.
Supresses outofband components of the signal
3.) Droop correction  may be required depending upon the ADC specifications
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40014
CMOS Analog Circuit Design P.E. Allen  2010
Comb Filters
A comb filter that computes a running average of the last D input samples is given as
y[n] =
1
D
i=0
D1
x[ni]
where D is the decimation factor given as
D =
f
s
f
s1
The corresponding zdomain expression is,
H
D
(z) =
i=1
D
z
i
=
1
D
1z
D
1z
1
The frequency response is obtained by evaluating H
D
(z) for z = e
j2fT
s
,
H
D
(f) =
1
D
sinfDT
s
sinfT
s
e
j2fT
s
/D
where T
s
is the input sampling period (=1/f
s
). Note that the phase response is linear.
For an Lth order modulator with a noise shaping function of (1z
1
)
L
, the required
number of comb filter stages is L+1. The magnitude of such a filter is,
H
D
(f) =
1
D
sinfDT
s
sinfT
s
K
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40015
CMOS Analog Circuit Design P.E. Allen  2010
Magnitude Response of a Cascaded Comb Filter
K = 1,2 and 3
Fig.10.927
100
80
60
40
20
0
Frequency
K = 1
K= 2
0 f
b
4 f
s
D
3 f
s
D
2 f
s
D
f
s
D
K = 3

H
D
(
f
)

d
B
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40016
CMOS Analog Circuit Design P.E. Allen  2010
Implementation of a Cascaded Comb Filter
Implementation:
Fig.10.928

+
z
1

+
z
1

+
z
1
f
s
/D
K = L +1 Integrators
Numerator Section
z
1
+

z
1
+

z
1
+

X
Y
K = L +1 Differentiators
Denominator Section
Comments:
1.) The L+1 integrators operating at the sampling frequency, f
s
, realize the denominator
of H
D
(z).
2.) The L+1 differentiators operating at the output rate of f
s1
(= f
s
/D) realize the
numerator of H
D
(z).
3.) Placing the integrator delays in the feedforward path reduces the critical path from
L+1 adder delays to a single adder delay.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40017
CMOS Analog Circuit Design P.E. Allen  2010
Implementation of Digital Filters
S.R. Norsworthy, R. Schreier, and G.C. Temes, DeltaSigma Data ConvertersTheory, Design, and Simulation, IEEE Press, NY, Chapter 13, 1997.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40018
CMOS Analog Circuit Design P.E. Allen  2010
Digital Lowpass Filter
Example of a typical digital filter used in removal of the quantization noise at higher
frequencies
110
80
50
20
10
4000
Frequency (Hz)
M
a
g
n
i
t
u
d
e
(
d
B
)
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40019
CMOS Analog Circuit Design P.E. Allen  2010
Illustration of the DeltaSigma ADC in Time and Frequency Domain
MODULATOR
DECIMATOR
LOWPASS
FILTER
analog
input
f
D
f
S
2
fB
digital
PCM
fB
Time Time
Frequency Frequency
Frequency
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40020
CMOS Analog Circuit Design P.E. Allen  2010
BANDPASS DELTASIGMA MODULATORS
Bandpass Modulators
Block diagram of a bandpass modulator:
Components:
Resonator  a bandpass filter of order
2N, N= 1, 2,....
Coarse quantizer (1 bit or multibit)
The noiseshaping of the bandpass oversampled ADC has the following interesting
characteristics:
Center frequency = f
s
(2N1)/4
Bandwidth = BW = f
s
/M
Illustration of the Frequency Spectrum
(N=1):
Application of the bandpass ADC is
for systems with narrowband signals (IF frequencies)
Fig.10.927A

+
Resonator A/D
D/A
x
u
v
y
Quantizer
f
S
Frequency 3f
s
4
f
s
4
f
s
BW BW
dB
Attenuation
0
Fig. 1132
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40021
CMOS Analog Circuit Design P.E. Allen  2010
A FirstOrder AX Bandpass Modulator
Bandpass Resonator:
V(z) = z
1
[X(z)  z
1
V(z)] = z
1
X(z)  z
2
V(z)
V(z) (1+z
2
) = z
1
X(z) 
V(z)
X(z)
=
z
1
1+z
2
Modulator:
Y(z) = Q(z) + [X(z)  Y(z)]
\

(
!

\
z
1
1+z
2

Y(z) =
\

(
!

\
1+z
2
1+z
1
z
2
Q(z) +
\

(
!

\
z
1
1+z
1
z
2
X(z)
NTF
Q
(z) =
\

(
!

\
1+z
2
1+z
1
z
2
The NTF
Q
(z) has two zeros on the jc axis.
z
1
z
1
X(z) V(z)
+

Fig. 10.927C
Fig.10.927B

+ z
1 +
X(z)
Q(z)
Y(z)
1+z
2
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40022
CMOS Analog Circuit Design P.E. Allen  2010
Resonator Design
Resonators can be designed by applying a lowpass to bandpass transform as follows:
z
1
X(z) V(z)
+
+
Fig. 10.927D
z
2
X(z) V(z)
+
+
Replace z
1
by z
2
1  z
1
z
1
1 + z
2
z
2
Result:
Simple way to design the resonator
Inherits the stability of a lowpass modulator
Center frequency located at f
s
/4
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40023
CMOS Analog Circuit Design P.E. Allen  2010
FourthOrder Bandpass Modulator
Block diagram:
X(z) Y(z)
+

Fig. 10.927E
1 + z
2
z
2
0.5
+
+
1 + z
2
z
2
0.5
Comments:
Designed by applying a lowpass to bandpass transform to a secondorder lowpass
modulator
The stabilty and SNR characteristics are the same as those of a secondorder lowpass
modulator
The zdomain output is given as,
Y(z) = z
4
X(z) + (1+z
2
)
2
Q(z)
The zeros are located at z = j which corresponds to notches at f
s
/4.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40024
CMOS Analog Circuit Design P.E. Allen  2010
Resonator Circuit Implementation
Block diagram of z
2
/(1+z
2
):
z
1
z
1
X(z) V(z)
+
+
Fig. 10.927F
Fully differential switchcapacitor implementation:
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40025
CMOS Analog Circuit Design P.E. Allen  2010
Power Spectral Density of the Previous FourthOrder Bandpass Modulator
Simulated result:
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40026
CMOS Analog Circuit Design P.E. Allen  2010
DELTASIGMA DIGITALTOANALOG CONVERTERS
Principles
The principles of oversampling and noise shaping are also widely used in the
implementation of DACs.
Simplified block diagram of a deltasigma DAC:
Digital
deltasigma
modulator
Interpolat
ion filter
Analog
lowpass
filter
DAC
Nbit
Mf
N
Nbit
f
N
1bit
Mf
N
Mf
N
Input
Digital Section
Analog Section
Output
Fig10.929
Operation:
1.) A digital signal with Nbits with a data rate of f
N
is sampled at a higher rate of Mf
N
by
means of an interpolator.
2.) Interpolation is achieved by inserting 0s between each input word with a rate of
Mf
N
and then filtering with a lowpass filter.
3.) The MSB of the digital filter is applied to a DAC which is applied to an analog
lowpass filter to achieve the analog output.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40027
CMOS Analog Circuit Design P.E. Allen  2010
Block Diagram of a DAC
Analog
Output 
+
Interpol
ation
Digital
Filter
Digital Code
Conversion
0100000000000000 =1
1011111111111111 = 1
V
Ref
V
Ref
Digital
Input
f
N
f
S
=Mf
N
f
S
f
S
f
S
Analog
Lowpass
Filter
MSB
DAC
f
S f
S
Fig10.931
y(k)
Operation:
1.) Interpolate a digital word at the conversion rate of the converter (f
N
) up to the sample
frequency, f
s
.
2.) The word length is then reduced to one bit with a digital sigmadelta modulator.
3.) The one bit PDM signal is converted to an analog signal by switching between two
reference voltages.
4.) The highfrequency quantization noise is removed with an analog lowpass filter
yielding the required analog output signal.
Sources of error:
Device mismatch (causes harmonic distortion rather than DNL or INL)
Component noise
Device nonlinearities
Clock jitter sensitivity
Inband quantization error from the  modulator
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40028
CMOS Analog Circuit Design P.E. Allen  2010
Frequency Viewpoint of the DAC
Frequency spectra at different points of the deltasigma ADC:
Frequency 0
Interpolation
filter output
Deltasigma
modulator
output
Lowpass
filter
output
Input
Magnitude
Quantization noise after
filtering
0.5f
N
0.5f
N
f
N
(M1)f
N
Mf
N
Frequency
Mf
N
0 0.5f
N
0.5f
N
Frequency
Mf
N
0 0.5f
N
0.5f
N
Frequency
Mf
N
0 0.5f
N
0.5f
N
Fig10.933
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40029
CMOS Analog Circuit Design P.E. Allen  2010
A ThirdOrder, Modulator for a DAC
A digital equivalent of the thirdorder MASH modulator is shown below.
X
Y
X+Y
Latch
Over
flow
X+Y
Latch
Over
flow
X+Y
Latch
Over
flow
z
1
z
1
+ +
+ +
Clk
Clk
Clk
8state
Output
Digital
Inputs
07052101
The mbit accumulators consist of an mbit adder and mbit latches.
The 8state digital output is converted to an analog through means of an analog filter.
Spectral outputs:
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40030
CMOS Analog Circuit Design P.E. Allen  2010
1BitDAC for the DigitaltoAnalog Converter  The Analog Part
The MSB output from the digital filter is used to drive a 1bit DAC.
Possible architectures:
V
Ref
1
y(k)
2
y(k)
V
Ref
1
y(k)
C R
Analog
lowpass
filter
with 3dB
frequency
of 0.5f
N
Analog
Output
R
C
2
y(k)
Analog
lowpass
filter with
3dB
frequency
of 0.5f
N
Analog
Output
I
Ref
I
Ref
Voltagedriven DAC with a
passive lowpass filter stage.
Currentdriven DAC with a
passive lowpass filter stage.
Fig10.932
A multibit output would consist of more parallel, controlled current sources and sinks.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40031
CMOS Analog Circuit Design P.E. Allen  2010
SwitchedCapacitor DAC and Filter
Typically, the DAC and the first stage of the lowpass filter are implemented using
switchedcapacitor techniques.
V
Ref
1
y(k)
V
Ref
1
y(k)
2
+

1
C
1
C
2
R
To analog
lowpass
filter
Fig10.934
It is necessary to follow the switchedcapacitor filter by a continuous time lowpass filter
to provide the necessary attenuation of the quantization noise.
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40032
CMOS Analog Circuit Design P.E. Allen  2010
SUMMARY
Comparison of the Various Types of ADCs
A/D Converter Type Maximum
Practical Number
of Bits (1)
Speed
(Expressed in terms
of T a clock period)
Area Dependence
on the number of
bits, N, or other
ADC parameters
Dual Slope
1214 bits
2(2
NT
)
Independent
Successive Approximation
with selfcorrection
1215 bits NT N
1Bit Pipeline 10 bits T (After NT delay ) N
Algorithmic 12 bits NT Independent
Flash 6 bits T
2
N
Twostep, flash 1012 bits 2T
2
N/2
Mulitplebit, Mpipe 1214 bits MT
2
N/M
 Oversampled (1bit, L
loops and M= oversampling
ratio = f
clock
/2f
b
) 1517 bits MT L
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40033
CMOS Analog Circuit Design P.E. Allen  2010
Comparison of Recent ADCs
Resolution versus conversion rate:
5
10
15
20
25
O
u
t
p
u
t
w
o
r
d
l
e
n
g
t
h
Conversion rate, (samples/sec.)
1 10
2 10
4
10
6
10
8
10
10
Figure 10.101
Flash
Pipelined
Algorithmic
Dualslope
Deltasigma
Successive approximation
Folding/Interpolating
Bandpass deltasigma
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40034
CMOS Analog Circuit Design P.E. Allen  2010
Comparison of Recent ADCs  Continued
Power dissipation versus conversion rate:
Figure 10.102
0.01
0.1
1
10
100
1000
1 100 10
4
10
6
10
8
10
10
P
o
w
e
r
D
i
s
s
i
p
a
t
i
o
n
(
m
W
)
Conversion Rate (Samples/second)
Flash
Pipelined
Deltasigma
Successive approximation
Folding/Interpolating
Bandpass deltasigma
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40035
CMOS Analog Circuit Design P.E. Allen  2010
References for Previous Figures
[1] A 12b, 60MSample/s Cascaded Folding and Interpolating ADC. Vorenkamp, P., IEEE JSC, vol. 32, no. 12, Dec 97 1876
1886
[2] A 15b, 5Msample/s LowSpurious CMOS ADC. Kwak, S. U., IEEE JSC, vol. 32, no. 12, Dec 97 18661875
[3] Error Suppressing Encode Logic of FCDL in a 6b Flash A/D Converter. Ono, K., IEEE JSC, vol. 32, no.9, Sep 97 1460
1464
[4] A Cascaded SigmaDelta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR. Brooks, T. L., IEEE
JSC, vol.32, no.12, Dec 97 18961906
[5] A 10b, 100 MS/s CMOS A/D Converter. Kwang Young Kim, IEEE JSC, vol. 32, no. 3, Mar 97 302311
[6] A 1.95V, 0.34mW, 12b SigmaDelta Modulator Stabilized by Local Feedback Loops. Au, S., IEEE JSC, vol. 32, no. 3,
Mar 97 321328
[7] A 250mW, 8b, 52Msamples/s ParallelPipelined A/D Converter with Reduced Number of Amplifiers. Nagaraj, K., IEEE J
SC, vol. 32, no. 3, Mar 97 312320
[8] A DSPBased Hearing Instrument IC. Neuteboom, H., IEEE JSC, vol. 32, no. 11, Nov 97 17901806
[9] An Embedded 240mW 10b 50MS/s CMOS ADC in 1mm
2
. Bult, K., IEEE JSC, vol. 32, no. 12, Dec 97 18871895
[10] LowVoltage DoubleSampled Converters. Senderowicz, D., IEEE JSC, vol. 32, no.12, Dec 97 19071919
[11] Quadrature Bandpass Modulation for Digital Radio. Jantzi, S. A., IEEE JSC, vol. 32, no. 12, Dec 97 19351950
[12] A TwoPath Bandpass Modulator for Digital IF Extraction at 20 MHz. Ong, A. K., IEEE JSC, vol. 32, no. 12, Dec 97
19201934
[13] A 240Mbps, 1W CMOS EPRML ReadChannel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter.
Matsuura, T., IEEE JSC, vol. 33, no. 11, Nov 98 18401850
[14] A 13Bit, 1.4 MS/s SigmaDelta Modulator for RF Baseband Channel Applications. Feldman, A. R., IEEE JSC, vol. 33,
no. 10, Oct 98 14621469
[15] Design and Implementation of an Untrimmed MOSFETOnly 10Bit A/D Converter with 79dB THD. Hammerschmied,
C. M., IEEE JSC, vol. 33, no. 8, Aug 98 11481157
[16] A 15b Resolution 2MHz Nyquist Rate ADC in a 1m CMOS Technology. Marques, A. M., IEEE JSC, vol. 33, no.
7, Jul 98 10651075
[17] A 950MHz IF SecondOrder Integrated LC Bandpass DeltaSigma Modulator. Gao, W., IEEE JSC, vol. 33, no. 5, May
98 723732
[18] A 200MSPS 6Bit Flash ADC in 0.6m CMOS. Dalton, D., IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 45, no. 11, Nov 98 14331444
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40036
CMOS Analog Circuit Design P.E. Allen  2010
References  Continued
[19] A 5V SingleChip DeltaSigma Audio A/D Converter with 111 dB Dynamic Range. Fujimori, I., IEEE JSC, vol. 32, no.
3, Mar 97 329336
[20] A 256 x 256 CMOS Imaging Array with Wide Dynamic Range Pixels and ColumnParallel Digital Output. Decker, S.,
IEEE JSC, vol. 33, no.12, Dec 98 20812091
[21] A 400 Msample/s, 6b CMOS Folding and Interpolating ADC. Flynn, M., IEEE JSC, vol. 33, no.12, Dec 98 19321938
[22] An Analog Background Calibration Technique for TimeInterleaved AnalogtoDigital Converters. Dyer, K. C., IEEE JSC,
vol. 33, no.12, Dec 98 19121919
[23] A CMOS 6b, 400Msample/s ADC with Error Correction. Tsukamoto, S., IEEE JSC, vol. 33, no.12, Dec 98 19391947
[24] A Continuously Calibrated 12b, 10MS/s, 3.3V ADC. Ingino, J. M., IEEE JSC, vol. 33, no.12, Dec 98 19201931
[25] A DeltaSigma PLL for 14b, 50 ksamples/s FrequencytoDigital Conversion of a 10 MHz FM Signal. Galton, I., IEEE J
SC, vol. 33, no.12, Dec 98 20422053
[26] A Digital Background Calibration Technique for TimeInterleaved AnalogtoDigital Converters. Fu, D., IEEE JSC, vol. 33
no.12, Dec 98 19041911
[27] An IEEE 1451 Standard Transducer Interface Chip with 12b ADC, Two 12b DACs, 10kB Flash EEPROM, and 8b
Microcontroller. Cummins, T., IEEE JSC, vol. 33, no.12, Dec 98 21122120
[28] A SingleEnded 12bit 20 Msample/s SelfCalibrating Pipeline A/D Converter. Opris, I. E., IEEE JSC, vol. 33, no.12, Dec
98 18981903
[29] A 900mV LowPower A/D Converter with 77dB Dynamic Range. Peluso, V., IEEE JSC, vol. 33, no.12, Dec 98
18871897
[30] ThirdOrder Modulator Using SecondOrder NoiseShaping Dynamic Element Matching. Yasuda, A., IEEE JSC, vol.
33, no.12, Dec 98 18791886
[31] R, G, B Acquisition Interface with LineLocked Clock Generator for Flat Panel Display. Marie, H., IEEE JSC, vol. 33,
no.7, Jul 98 10091013
[32] A 25 MS/s 8b  10 MS/s 10b CMOS Data Acquisition IC for Digital Storage Oscilloscopes. Kusayanagi, N., IEEE JSC,
vol. 33, no.3, Mar 98 492496
[33] A Multimode Digital Detector Readout for SolidState Medical Imaging Detectors. Boles, C. D., IEEE JSC, vol. 33, no.5,
May 98 733742
[34] CMOS ChargeTransfer Preamplifier for OffsetFluctuation Cancellation in Low Power A/D Converters. Kotani, K., IEEE J
SC, vol. 33, no.5, May 98 762769
[35] Design Techniques for a LowPower LowCost CMOS A/D Converter. Chang, DongYoung, IEEE JSC, vol. 33, no.8,
Aug 98 12441248
Lecture 400 Oversampling ADCs Part II (3/29/10) Page 40037
CMOS Analog Circuit Design P.E. Allen  2010
CONCLUDING THOUGHTS
What is analog circuit design?
The complex process of creating circuit solutions using analog circuit techniques.
What is the analog integrated circuit design process?
The even more complex process of combining analog design with IC technology
which includes electrical, physical and test design.
What are the key principles, concepts and techniques for analog IC design?
Key principles Fundamental laws
Key concepts Important relationships and
ideas
How can the analog IC designer enhance
creativity and solve new problems in todays
industrial environment?
Learn the key principles, concepts and techniques of
analog circuit design
Learn from mistakes
Learn the technology
Always try to understand the concept and operation
of the circuit, never rely on a computer or someone else for this understanding
Technology changes but principles, concepts and
techniques remain the same.
Key techniques Tools that allow
simplification or insight