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External Interrupts on the ATMEGA

Okay, now why are they of importance to us ? A lot of stuff generates signals in the form of voltages or voltage changes to indicate decided events. For example, a device might have one line which goes low for a few clock cycles and then high again to indicate that it has completed its task.We can therefore use this line as an external interrupt line to schedule further tasks. The ATMEGA16/32 has 3 external interrupt lines : INTO,INT1 and INT2, on pins PD2,PD3 and PB2. Interrupts on INT0 and INT1 can be 1. level-triggered(meaning that the interrupt is triggered when the signal goes low i.e. 0V for some time OR 2. edge-triggered(meaning that the interrupt is triggered when the signal changes from high to low or low to high) ====> INT2 can only be used as an edge-triggered interrupt. Setting up the interrupts :: Control Registers MCUCR : MCU Control Register

Bits 3,2,1,0 are the ones which are of importance to us. Bits 3,2 are used for sensing an external interrupt on line INT1. Bits 1,0 are used for sensing an external interrupt on line INT0. The table for setting up these bits is as follows :

The table for INT0 is similar to the one above. It is to be noted that if an edge triggered interrupt is selected, the edge (change) must last for at least one cycle for it to be detected. Similarly, if a low level triggered interrupt is selected, the low signal level must be held till the instruction being executed currently by the MCU is completed. MCUCSR : MCU Control and Status Register

Bit 6 is the only one of importance here, and controls the INT2 line. If this bit is set to 1, a rising edge generates an interrupt and if it is set to 0, a falling edge generates an interrupt. The pulses here also must be longer than one clock cycle. Also, the ISC2 bit must be set following a specific method,since an interrupt can occur even while changing the ISC2 bit. The procedure is something like this : 1.Disable INT2 by clearing its Interrupt Enable bit in the GICR Register. 2.The ISC2 bit can be changed. 3.The INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.

GICR : General Interrupt Control Register

Bit 7,6,5 enable the INT1, INT0 and INT2 lines respectively if set to one. GIFR : General Interrupt Flag Register

Bit 7,6,5 manage the status of the Interrupt requests. The flag is set for each of these when the respective line is triggered, and cleared when the corresponding interrupt service routine is executed.Alternatively, we can clear the flags manually by writing it to 1.