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Processor definition
For the purpose of this discussion, the term processor means any system comprised of 1 or more central processing units (CPUs). A CPU is a device capable of executing a program contained in main storage. A CPC is a central processor complex. An instruction-stream engine is simply an I-stream. CPC is synonymous with processor, while an I-stream is a CPU. z/TPF may utilize any of the z/Architecture® processors when a non-loosely coupled system is desired. A loosely coupled z/TPF system may use any extended architecture processors that have been equipped with the required RPQs. (See z/TPF and z/TPFDF Migration Guide for a summary of supported processors.) As many as 32 processors can may be connected together using the loosely coupled (LC) facility of the HPO feature. Each processor runs a separate image of z/TPF, but all processors share the same database. SeeLoosely coupled complexes for an additional explanation of LC. Some multiprocessor models are partitionable. Such a processor may be used either as a single integrated processor, or as independent processors. The number and types of channels and control units, and the number and types of I/O devices, are determined during the design of the system. SIP provides the CONFIG and IODEV macros to describe the processor and channel characteristics, respectively. The following parameters of the SIP CONFIG (processor configuration) macro relate to processor support. (For more information about the CONFIG macro, see CONFIG.) y APRNT±address of the system printer for use during the IPL sequence. y VM±whether or not the z/TPF system, normally a test system, is to be run under the control of the VM program product (for example, z/VM®). y SYSID±the symbolic z/TPF processor ID(s). y PROC1±PROC32: These parameters are coded only when an LC system is required. Each parameter specifies the serial number and the model number for a processor in an LC complex. Note: 1. Many of the required initialization parameters in this section are associated with a SIP parameter. SIP parameters are indicated where appropriate, with the SIP parameter given in parentheses preceding or following the macro name. For example: SIP Input = (SYSID) CONFIG, or CONFIG (SYSID) Means: SYSID is a parameter used within the SIP macro CONFIG. 2. For users of the LC facility, multiple symbolic processor IDs are specified via the SYSID parameter, one for each of the processors in the LC complex. In addition to the hardware TOD clock, z/TPF provides for software clocks which are available to application programs. For users of MDBF in the HPO feature each subsystem is allowed to have its own version of these software clocks. Each subsystem's clock values are calculated using the hardware TOD clock. Non-MDBF users are treated similarly to a BSS in an MDBF system.

Keypoint record B (CTKB) contains the subsystem's local standard time (LST). It allows separate settings for all individual cores of the processor and also the CPU's overclocking capabilities by altering internal settings. Therefore Black Edition CPUs are especially . Support for the generation of multiple subsystems. SIP macro parameters that relate to the software system clocks (CLOCKS) are as follows: GDIF System clock LST minus GMT. AMD Overdrive This tool grants access to real-time adjustments of many system attributes and thus it allows for example easy. one for each subsystem. and the subsystem's perpetual minutes clock. AMD-V AMD Virtualization is the virtualization extension for AMD's x86 processors. Precycle above 1052 state means the value to be used by the subsystem prior to cycling the subsystem above 1052 state at which time the system operator can change the value using commands. The MDBF user will have to code multiple CLOCKS macros. DELTIM Initial system time difference from the system clock. SDEF. the subsystem's GMT. including the basic subsystem (BSS). see SAMD features Advanced Clock Calibration ACC is a feature offered by AMD's SB710 and SB710 Southbridges and processors with a K10 architecture. 2. There can be a maximum of 64 subsystems. Furthermore AMD Overdrive also offers benchmarking and stability testing features. This technique of providing different user values by subsystem in a MDBF generation is the standard one used by SIP as is the concept of only coding one version of a given macro in a non-MDBF environment. is provided by the multiple database function (MDBF) of the HPO feature. on-the-fly overclocking. Increasing the multiplier is an easy way to increase the frequency a processor is running at. each with its own database (DASD devices).These software clocks are located in low memory. Generation of an MDBF system is indicated by coding the SSDEF SIP macro. The non-MDBF user only codes one CLOCKS macro. Note: 1. (For more information about the SSDEF macro.) Black Edition The processors that carry the Black Edition tag differ from the other AMD CPUs because of their open multiplier. Keypoint record A (CTKA) contains the subsystem's local standard time difference from Greenwich Mean Time (GMT). DATE Precycle above 1052 state date of the system clock. LST Precycle above 1052 state LST of system clock in EBCDIC. Besides that it is said to be possible to unlock deactivated cache and cores of certain processors although this is not officially supported or recommended by AMD. There is a copy of these keypoints for each subsystem defined at system generation.

is a security system that prevents so called buffer overflow attacks. also known as NX Bit. HT has several areas of application.. but it is also part of AMD's Direct Connect Architecture. . EVP The Enhanced Virus Protection. Cool'n'Quiet Cool'n'Quiet is a feature of AMD CPUs that automatically reduces the frequency and the voltage of a CPU in order to lower the power consumption and the temperature.popular among overclockers. If a system supports EVP the processor prevents that malicious software can insert code into the memory area of other programs and execute it there. Hyper Transport Hyper Transport is a bidirectional serial/parallel point-to-point link with a high bandwidth and a low-latency. In certain processor architectures AMD uses Hyper Transport as a replacement of the Front Side Bus.