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MCS@51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Commercial/Express 8031AH18051AH18051AHP 8032N+18052N-I 8751W8751H-8 8751BW8752BI-I

s High Performance HMOS Process s Internal Timers/Event Counters s 2-Level interrupt Priority Structure s 32 1/0 Lines (Four 8-Bit Ports) s 64K External Program Memory Space s Security Feature Protects EPROM Parts

s Boolean Processor s Bit-Addressable RAM s Programmable Full Duplex Serial

Channel
s 111 Instructions (64 Single-Cycle) s s Extended Temperature Range

64K External Data Memory Space (–40”C to +85”C)

Against Software Piracy

The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing. The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The 8751 H-8 is identical to the 8751 H but only operates up to 8 MHz. The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this Protection Feature, program verification has been disabled and external memory accesses have been limited to 4K. The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless and-EPROM versions of each product. Device 8031AH 8051AH 6051AHP 8751 H 8751 H-8 6751 BH 8032AH 6052AH 8752BH Intsrnal Memory Program none 4K X 8 ROM 4K X 6 ROM 4K X 8 EPROM 4K X 8 EPROM 4K X 8 EPROM none 8K X 8 ROM 8K X 8 EPROM Data 128 X 8 RAM 128 X 8 RAM 128 X 8 RAM 128 X 8 RAM 128 X 6 RAM 128 X 8 RAM 256 X 6 RAM 256 X 8 RAM 256 X 8 RAM Timera/ Event Counters 2 x 18-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 2 x 16-Bit 3 x 16-Bit 3 x 16-Bit 3 x 16-Bit Interrupts 5 5 5 5 5 5 6 6 6

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Intel Corporationassumes no responsibility the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent for licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel. O INTEL CORPORATION, 1994 October 1994 Order Numben 272318-002

MCS” 51 CONTROLLER

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Figure 1. MCSI@ Controller Block Diagram 51

PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devices are manufactured on P414.1, an HMOS II process. The 8751H/8751 H-8 devices are manufactured on P421.X, an HMOS-E process. The 8751BH and 8752BH devices are manufactured on P422. Additional process and reliability information is availQ able in Intel’s Componentsuality and Reliability Handbook, Order No, 210997.

4 :>!: neaslvsd** fTXD) P3. See the Intel Pac/raging Handbook (Order Number 240800) for a description of Intel’s thermal impedance test methodology.6 P1.5 P1.1 AD1 PO. :ji.6 ::8:. Values will change depending on operating conditions and application.’ P1.5 A13 I P2.5 ~ P3.3 P1.:.2 INT1 P3.3 A03 PO.1 INTO P3.2 (INT1) P3.1 P1.7 XTAL2 XTAL1 I’__”ll 1 2 3 4 5 6 7 6 9 10 11 12 13 14 15 16 17 16 19 PI.1:..2 AlO 3 P2 1 A9 X P20 A8 T2 T2EX ‘1 ‘ss+!-29 26 27 26 25 24 23 22 21 EPROM only q “*Do not connect PI.4 A12 1 P2.3 Al 1 > P2.7 A15 2 P2.3 8X5X 272318-2 DIP reserved pins.7 . and 38”/22” for N.1 (INTo) P3. fTo) P3.O :ji: .MCS@ 51 CONTROLLER PACKAGES Part 8051AH 8031AH 8052AH 8032AH 6752BH* 8751H 8751 H-8 8051AHP 8751 BH Prefix P D N Package Type 40-Pin Plastic DIP 40-Pin CERDIP 44-Pin PLCC ‘ja Ojc 45°chV 4!5”CIW 46°C/W 16“C/W 15“CAIV 18°CfW D P D P N 40-Pin CERDIP 40-Pin Plastic DIP 40-Pin CERDIP 40-Pin Plastic DIP 44-Pin PLCC 45”CIW 45”CIW 45°c/w 36”CIW 47”C1W 45“CIW 16°CfW 15“cf w 12°cf w 16”Cf W NOTE: *8752BHis 36”/10” for D. All thermal impedance data is approximate for static air conditions at IW of power dissipation.: RST io.2 P1. PLCC Figure 2.4 P1.’ ADO PO. :!.7 RST RU2 P3. ~“52’80320NL’ L{ ~ 40 39 38 37 36 35 34 33 Vcc P’.6 t% P3.4 AD4 PO.2 A02 PO.6A14 3 P2. :j:. (Rxo) P3.7A07 3 EIJvpp” Z ALEIPROG” 3%FFI 3 P2.3 TOP3 4 11 P3.5 AD5 P06 AD’ 3 PO. MCS@51 Controller Connections 3 .. P*.O TXD P3.

and may be used for external timing or clocking purposes. This pin is also the program pulse input (PROG) during programming of the EPROM parts. As inputs. Note. Port O is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. and in that state can be used as high-impedance inputs. In this application it uses strong internal pullups when emitting 1‘s and can source and sink 8 LS TTL inputs. . Port 1 pins P1. Vss: Circuit ground. ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. Port Opins that have 1‘s written to them float.O and P1.6 P3. Porl 2 pins that have 1‘s written to them are pulled high by the internal pullUPS.Port 2 emits the contents of the P2 Special Function Register. In the 8032AH.0 P3. Port 1 also receives the low-order address bytes during programming of the EPROM parts and during program verification of the ROM and EPROM parts. As inputs.effectively limiting external Data and Code space to 4K each during external accesses.5 P3.7 Alternative Function RXD (serial input port) TXD (serial output port) INTO(external interrupt O) INT1 (external interrupt 1) TO(Timer Oexternal input) T1 (Timer 1 external input) WR (external data memory write strobe) ~ (external data memory read strobe) I Port Pin P1. that one ALE pulse is skipped during each access to external Data Memory. As inputs. and outputs the code bytes during program verification of the ROM and EPROM parts.and in that state can be used as inputs. Port 1 pins that have 1‘s written to them are pulled high by the internal pullUPS.2 P3. In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency. As an output port each pin can sink 8 LS TTL inputs.and in that state can be used as inputs. External pullups are required during program verification. 8052AH and 8752BH. as listed below: Port Pin P3. Port 1: Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port O also receives the code bytes during programming of the EPROM parts. Port O:Port O is an 8-bit open drain bidirectional 1/0 port.4 P3.0 P1.4 through P2. Port 2 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups.1 I Alternative Function T2 (Timer/Counter 2 External Input) T2EX (Timer/Counter 2 Capture/Reload Trigger) I RST: Reset input.1 also serve the T2 and T2EX functions. During accesses to external Data Memory that use 8-bit addresses (MOVX @Ri).and in that state can be used as inputs. Port 2 also receives the high-order address bits during programming of the EPROM parts and during program verification of the ROM and EPROM parts. however. The protection feature of the 8051AHP causes bits P2.1 P3. The Port 3 output buffers can sink/ source 4 LS TTL inputs. Port 3 pins that have 1‘s written to them are pulled high by the internal pullUPS. Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups. respectively. In this application it uses strong internal pullups when emitting 1‘s. Port 2: Port 2 is an 8-bit bidirectional l/O port with internal pullups. The Port 2 output buffers can sink/ source 4 LS TTL inputs.7 to be forced to O.MCS” 51 CONTROLLER w PIN DESCRIPTIONS Vcc: Supply voltage. A high on this pin for two machine cycles while the oscillator is running resets the device. The Port 1 output buffers can sink/ source 4 LS TTL inputs. Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). Port 3: Port 3 is an 8-bit bidirectional l/O port with internal pullups. Port 3 also serves the functions of various special features of the MCS 51 Family.3 P3.

XTAL1 should be grounded. Package types and EXPRESSversions are identified by a one.5V * 0. C2 I To drive the device from an external clock source. except that two PSEN activations are skipped during each access to external Data Memory ~/Vpp: External Access enable ~ must be strapped to VSS in order to enable any MCS 51 device to fetch code from external Program memory locations starting at OOOOH to FFFFH. El XTAL2 n XTAL1 cl Vss = 272318-4 Figure 4. For the extended temperature range option. C2 = 30 PF +10 PF for Crystals For Ceramic Resonators contact resonatormanufacturer. With the extended temperature range option. and an extended temperature range with or without burn-in. There are no requirements on the duty cycle of the external clock signal. operational characteristics are guaranteed over a range of –40”C to + 85”C. ~ must up be strapped to VCCfor internal program execution. PSEN is activated twice each machine cycle. this data sheet specifies the parameters which deviate from their commercial temperature range limits.or two-letter prefix to the part number. however. These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. Either a quartz crystal or ceramic resonator may be used. 230659. since the input to the internal clocking circuitry is through a divide-by-two flip-flop. XTAL2: Output from the inverting oscillator amplifier. Figure 3. I 5 . The optional burn-in is dynamic. Oscillator Connections XTAL1: Input to the inverting oscillator amplifier. respectively. Method 1015. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output. following guidelines in MIL-STD-883. the device will not fetch code from any location in external Program Memory. operational characteristics are guaranteed over the temperature range of O“C to + 70”C. The EXPRESS program includes the commercial standard temperature range with burn-in.MCS” 51 CONTROLLER w PSEN: Program Store Enable is the read strobe to external Program Memory. but minimum and maximum high and low times specified on the data sheet must be observed. while XTAL2 is driven. EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 Vss 272318-3 Cl. With the commercial standard temperature range. as shown in Figure 3. When the device is executing code from external Program Memory. External Drive Configuration EXPRESS Version The Intel EXPRESS system offers enhancements to the operational specifications of the MCS 51 family of microcontrollers. Note. of an inverting amplifier which can be configured for use as an on-chip oscillator. The prefixes are listed in Table 1. “Oscillators for MicrocontrolIers. This pin also receives the programming supply voltage (VPP) during programming of the EPROM parts.25V. that if the Security Bit in the EPROM devices is programmed.” Order No. as shown in Figure 4. for a minimum time of 160 hours at 125°C with VCC = 5. More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155.

To access Data Memory above 4K. 6 . Note that the VIH and IIH specifications for the ~ pin differ significantly between the devices. DESIGN CONSIDERATIONS If an 8751 BH or 8752BH is replacing an 8751 H in a future design. q The 8051AHP cannot access external Program or Data memory above 4K. it is suggested that an opaque label be placed over the window when the die is exposed to ambient light.@DPTR MOVX (6JDPTR. the MOVX @Ri.A or MOVX A. This means that the following instructions that use the Data Pointer only read/write data at address locations below OFFFH: MOVX A.MCS@51 CONTROLLER Table 1. the user should carefully compare both data sheets for DC or AC Characteristic differences. EXPRESS Prefix Identification Prefix P D N TD TP TN LD LP Package Type Plastic Cerdip PLCC Cerdip Plastic PLCC Cerdip Plastic Temperature Range Commercial Commercial Commercial Extended Extended Extended Extended Extended Burn-In No No No No No No Yes Yes NOTE: Contactdistributoror localsalesofficeto matchEXPRESS prefixwith properdevice. those locations will not be accessed. A When the Data Pointer contains an address above the 4K limit. For this reason. Exposure to light when the EPROM device is in operation may cause logic errors.@Ri instructions must be used.

..5 Max 0.2.4 –500 –15 –lo –lo 0.0 2.5V to + 7V .4 2.MCS” 51 CONTROLLER ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias –40”C to + 85°C Storage Temperature .5 3.5V –0.2 mA !OL = 2. .45 v v v v v v pA mA mA mA mA loL = 1.45V VIN = Vss VIN = Vss Units v v v v XTAL1 = Vss Test Conditions 7 . and RST) Logical O Input Current (~) 8751H and 8751H-8 8751BH 8752BH 2.3. . . RST) Input High Voltage to XTAL2. –65°C to + 150°C –0. ALE. .6 mA ioL = 3.5 Msx +70 +65 5.5 Pin of Min –0.5V to + 21..2. .OV –0.60 0. The specificationsare subject to change without notice. . . 13. PSEN)* 8751 H. . tO + NOTICE:This is a productiondata sheet. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliabili~. .5 Vcc + 0. 1. . .5W OPERATING CONDITIONS Symbol TA Vcc Fosc Description Ambient Temperature Under Bias Min o –40 4.5 o 2. It is valid for the devices indicated in the revision history.5 5. .5 4.45V VIN = 0. 8751 H-8 All Others VOH VOH1 IIL IILI Output High Voltage (Ports 1.5V 0. 8751 BH/6752BH Voltage on Any Other Pinto Vss Power Dissipation.2 mA IOH = –80 PA IOH = –400 pA VIN = 0. PSEN) Output High Voltage (Port Oin External Bus Mode) Logical O Input Current (Ports 1.3.45 0.4 mA IOL = 3. 3)* Output Low Voltage (Port O.7 Vcc + 0. *WARNING:Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.5 12 Units “c “c v MHz Commercial Express SupplyVoltage OscillatorFrequency DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Symbol VIL VIL1 VIH VIH1 VIH2 VoL VoLl Parameter Input Low Voltage (Except ~ 6751H and 8751H-8) Input Low Voltage to ~ Pin of 6751H and 8751H-8 Input High Voltage (Except XTAL2. . .2. . .5V .8 0. These are stress ratings orr~.45 0. RST Input High Voltage to ~ pin of 6751BH and 8752BH Output Low Voltage (Ports 1. Voltage on EA/Vpp Pin to Vss 8751 H .ALE. .

r. Capacitive loading on PortsO and 2 may csuse spurious noise pulses to be superimposed on the VOLS of ALE/PROG and Ports 1 and 3. .In suchcasesit maybe desirableto qualifyALEwitha SchmittTrigger. ALE/PROGrefersto a pin on the 8751BH. 3.—.. and 3: Maximum total toL for all outputpins: 71 mA If loL exceedsthe test condition.-.MCS” 51 CONTROLLER DC CHARACTERISTICS _r (Over Operating Conditions) All oarameter values armlv to all devices unless otherwise indicated (Continued) ~—. 2..4V 4. 8 . Symbol 11L2 ILI Parameter Logical OInput Current (XTAL2) Input Leakage Current (Porf O) 8751 H and 8751 H-8 All Others Logical 1 Input Current (~) 8751H and 8751H-8 Min Max –3.ALErefersto a timingsignalthat is outputon the ALE/PROG pin. m = Vcc Test freq = 1 MHz Clo NOTES: 1.5V < VIN < 5.VOLmayexceedthe relatedspecification.. 2.loL mustbe externallylimitedas follows: c 10 mA MaximumloL per port pin: Maximum per 8-bitpori loL 26 mA Porto: 15 mA Ports1.-.In the worst cases(capacitiveloading > 100 pF).2 * 1or) t 10 Units mA pA pA Teat Conditions VIN = 0.or usean address pin latchwith a Schmi~TriggerSTROBE input. The noise is dueto externalbuscapacitance discharging the PortOand Port2 pinswhenthesepins into make 1-to-O transitionsduringbus operations. the noise pulse on the ALE/PROG mayexceed0. Understeadystate(non-transient) onditions.8V. insare not guaranteed sinkcurrentgreater P to than the listedtest conditions.—.5V) All Outputs Disconnected.5V VIN < (Vcc – 1.45< VIN < VCC 0.45< VIN < VCC IIH 8751 BH/8752BH IIH1 Icc Input Current to RST to Activate Reset Power Supply Current: 8031AH/8051 AH/8051AHP 8032AH/8052AH/8751 BH/8752BH 8751H/8751 H-8 Pin Capacitance 500 1 500 125 175 250 10 pA mA pA mA mA mA pF VIN= 2.45V 0.

. Load Capacitance for Port O.. I AVUV I ns -- 9 .–. and PSEN = 100 pF...– I Aaaress 10valla Ua[a m o 63 75 287 302 20 6TCLCL– 100 6TCLCL– 100 5TCLCL– 165 TCLCL–8 5TCLCL–1 50 5TCLCL–1 15 20 58 190 215 100 125 0 TCLCL–20 12 MHz Oscillator Max Min 127 43 48 183 233 TCLCL–25 3TCLCL–60 3TCLCL–35 3TCLCL– 150 3TCLCL– 125 Min Variable Oscillator Max 12. . . or ALE P: PSEN Q: Output data R: ~ signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example.0 3. ..MCS@51 CONTROLLER L: ~level LOW.ALE/PROG. n. TAVLL = Time from Address Valid to ALE Low.ec WR Pulse Width Data Hold after ~ Data Float after ~ ALE Low to Valid Data In .— . Load Capacitance for All Other Outputs = 80 pF) EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol 1/TCLCL TLHLL TAVLL TLLAX TLLIV Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instr In 8751 H All Others ALE LOW to PSEN LOW PSEN Pulse Width 8751H All Others PSEN Low to Valid Instr In 8751H All Others Input Instr Hold after PSEN Input Instr Float after PSEN PSEN to Address Valid Address to Valid Instr In 8751 H All Others PSEN Low to Address Float ~ ~ Pulse Width Low to Valid Data In o 97 I I 517 . -—. depending on their positions. .5 Units MHz ns ns ns 4TCLCL– 150 4TCLCL– 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns rm 2TCLCL–40 TCLCL–40 TCLCL–35 TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV -. . TLLPL = Time from ALE Low to PSEN Low. stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. 103 Y I ~LUL— .. The other characters. . A: Address C: Clock D: Input Data H: Logic level HIGH 1:Instruction (program memory contents) AC CHARACTERISTICS (Under Operating Conditions.. EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. DUD I I 400 400 252 0 2TCLCL–70 8TCLCL–1 50 nl-n. The first character is always a ‘T’ (stands for time). .

use the 8751 H formula for variable oscillators.MCS@51 CONTROLLER EXTERNAL Symbol TLLWL TAVWL TQVWX PROGRAM MEMORY CHARACTERISTICS cillator Max (Continued) ALE Low to RD or WR Low Address to ~ or WR Low ‘arame’erI---%# 200 203 Variable Oscillator Min Max 3TCLCL+ 50 Units ns ns ns ns ns ns 300 3TCLCL–50 4TCLCL– 130 TCLCL–70 TCLCL–60 7TCLCL– 150 TCLCL–50 Data Valid to WR Transition 8751H All Others Data Valid to WR High Data Hold after WR RD Low to Address Float RD or WR High to ALE High 8751H All Others I 13 23 433 33 TQVWH TWHQX TRLAZ TWHLH 20 33 43 133 123 I TCLCL–50 TCLCL–40 I 20 TCLCL+ 50 TCLCL+40 I ns ns ns I NOTE: “The 8751H-8 is identicalto the 8751Hbut only o~eratesutI to 8 MHz.Whencalculatingthe AC Characteristicsor the f 8751 H-8. 10 .

.O-P2.MCS@51 CONTROLLER EXTERNAL PROGRAM MEMORY READ CYCLE w--ALE TLHLL _ \ .7 OR A8-A15 b FROMDPH TLLWL b —TRLDV4 OATA IN TRLRH –— i ‘ TRHOX+ Y TWHLH \ / x A8-A15 FROMPCH 272318-6 EXTERNAL DATA MEMORY WRITE CYCLE ALE TLHLL— m ‘TLLwL~TwLwH * \ .~ -TAVLL+ + PSEN / TLLAX PORTO TPLPH TLLIV / \ PORT 2 x 1 AO -A15 x A8 -A15 272318-5 EXTERNAL DATA MEMORY READ CYCLE ALE +TLHLL+ PSEN ‘LLOv ~ — m + TAVLL + _TLLAX PORTO . TWHLH / \ / WT 1 x I TAVLL +TLLAX AO-A7 FROM RIOR OPL 7t=II TQVWX k I TQVWH OATAOUT 1 ‘ TWHQX : r PORTO M xx 1 AO-A7 FROMFCL PORT2 P2. PORT2 x r AO-A7 FROM RI OR OPL TAVOV P2.O-P2. TLLPL.7 OR A8-A15 FROMOPH x A8-A15 FROMPCH 272318-7 11 .

0 700 50 o Max Max 700 10TCLCL– 133 ns . INPUT DATA ~ + 4 SET RI 272318-8 12 .HI17REGISTER MODETIMINGWAVEFORMS INSTRUCTION I ALE O I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I n n n n n n n n n n n n n n n n n n I I-TXLXL-7 WI-TXHQX CLOCK I 1 2 x 3 x 4 x 5 x 6 x 7 / SET TI OUTPUT OATA o 1)( .M=” 51 CONTROLLER SERIAL PORT TIMING—SHIFT Test Conditions: Over ODeratina Conditions: Load Capacitance = 80 rJF Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid 12 MHz Oscillator VariableOscillator Min 12TCLCL 1OTCLCL– 133 2TCLCL–1 17 0 Unite ps ns ns ns Min 1.

5 3. OUTPUT WAVEFORM 2.s 0.4V for a Logic “1” and 0.45 0.8V for a Logic“O”.8 2. Timing measurements ara made at 2.4 2.OV for a Logic “1” and 0. .0 TEST POINTS >< 0.MCS@51 CONTROLLER EXTERNAL CLOCK DRIVE Symbol 1/TCLCL TCHCX TCLCX I TCLCH TCHCL I Parameter Oscillator Frequency (except 8751H-8) 8751H-8 High Time Low Time Rise Time Fall Time Min 3.5 — A ~ TCliCL -— + TCLCX — TCLCL w 272318-9 AC TESTING INPUT.45V for a Logic “O”.0 272318-10 AC Testing: Inputs are driven at 2.5 t TCHCX — a TCLCH _ — t 2.5 20 20 Max 12 8 Units MHz MHz ns ns 1 I I 20 20 I ns ns I EXTERNAL CLOCK DRIVE WAVEFORM — 2.

The other Porl 2 pins. the part must be running with a 4 to 6 MHz oscillator. and RST. . Waveforms and detailed timing specifications are shown in later sections of this data sheet. +5V Program Verification If the Security Bit has not been programmed.3 of Port 2.. External pullups are required on Port O for this operation. The setup. ALE/PROG is pulsed low for 50 ms to program the code byte into the addressed EPROM location.5V *ALEis pulsedlowfor 50 ms Note that the ~/VPP pin must not be allowed to go above the maximum specified VPP level of 21. Program Verification 14 .O-P2.0– w PGM DATA Vcc P2.5 x x x P2. ALE/PROG is pulsed. The address of the Program Memory location to be read is appiied to Port 1 and pins P2.3 8751H —FFH w + ‘=’’-”TCAREJ=E ‘LEl=$=~ . Programming onfiguration C 27231S-12 Figure6.3.7 is held at a logic low. and then ~/Vpp is returned to a logic high. The VPP source should be well regulated and free of glitches. while the code byte to be programmed into that location is applied to Port O. Even a narrow glitch above that voltage Ievei can cause permanent damage to the device.W. which is shown in Figure 6. and ~/Vpp should be held at the “Program” levels indicated in Table 3. Figure5. Normally ~~is held at a logic highflntil just before ALE/PROG is to be pulsed..5 5 F&vPP ENAS4E P2.S .. if desired. PSEN.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2. The setup is shown in Figure 5. Then EA/Vpp is raised to +21 V. is the same as for programming the EPROM except that pin P2. 4-SUN* n a mu DATA (USE 10K PULLUPS] W51H ALE VIH G U Vlli P2. VIH1 J4-6 MHZm VIH1 Vss PSEN 27231 a-1 I . CARE.O-P2. PROGRAMMING THE 8751H To be programmed. or may be used as an activeIow read strobe +5V ? Vcc AOOR —FFH U–All A&b? p? P2.7 XTAU XTAL1 Vss .5V for any amount of time. EPROM Programming Modea ALE m P2.6 0 0 1 P2. The other pins should be held at the “Verify” Ieveis indicated in Tabie 3.7 PSEN 0 0 0 o* 1 o* VPP 1 VPP 1 0 1 P2. either during or after the programming operation. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal registers. the onchip Program Memory can be read out for verification purposes. P2 7 XTAU RST h XTAL1 RST PSEN . The contents of the addressed location will come out on Port O.4 x x x 1 Security Set NOTE: “1” = logichighfor that pin “O” = logiclowfor that pin “X” = “don’t care” “VPP” = +21V *0. x X-9 VIL d ~~b P2.MCS@51 CONTROLLER EPROM CHARACTERISTICS Mode Program Verify RST 1 1 Table3.

4 {: VIM P2. and it cannot executeout of externalprogrammemory. at a distance of about 1 inch. it can be cleared only by full erasure of the Program Memory. The setup and procedure are the same as for normal EPROM programming. o PI m P2. thus clearing the Security Bit. should be sufficient.Port 1 and pins P2. Programming SecurityBit the The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2.3 may be in any state. the internal Program Memory can not be read out.O–P2. Porl O. It can then be reprogrammed.7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE Min 20. Figure7. VCC = 5V + 10%. Once the Security Bit has been programmed.0X P2. Exposing the EPROM to an ultraviolet lamp of 12. exposure to these light sources over an extended time (about 1 week in sunlight. or 3 years in room-level fluorescent lighting) could cause inadvertent erasure.3 P2. except that P2. Erasure leaves the array in an all 1‘s state.6 8751H ALE ‘x ALE/PROO + EAYPP — WH1 50 ma PULSE TO GND * 7 * 272318-13 Erasure Characteristics Erasure of the EPROM begins to occur when the device is exposed to light with wavelengths shorter than approximately 4. Since sunlight and fluorescent lighting have wavelengths in this range. VSS = OV Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after~ P2. The other pins should be held at the “Security” levels indicated in Table 3. the device can not be further programmed.5 P2.5 4 46TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 45 Max 21. The bit is programmed as shown in Figure 7. If an application subjects the device to this type of exposure.7 XTAU m XTAL1 Vss PSEN RST fi P2.000 Angstroms. it is suggested that an opaque label be placed over the window.5 30 6 Unita v mA MHz ps 55 48TCLCL 48TCLCL ps ms o 48TCLCL 15 . While it is programmed. restores the device’s full functionality.MCS@51 CONTROLLER EPROM Security X = OGN’T CARE” +5V f Vcc The security feature consists of a ‘locking” bit which when programmed denies electrical access by any external means to the on-chip Program Memory.6 is held at a logic high.Erasing the EPROM. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS TA = 21°C to 27”C.000 pW/cm2 rating for 20 to 30 minutes.

.vPP m HIGH — — TGLGH 21V * .MCS” 51 CONTROLLER GI-” ”nl r“”” ”mrnmrlmn.7 P3. b. “.5V \ TTL HIGH TTL HIGH TSHSN — P3.3 VERIFICATION ADDRESS $ J — ( PORTO { .0-P3.Lrl.. m“. TOVGL — TAVGL DATAIN — — \ ~ ‘ TGHSL —TGHOX TGHAX kLE/PROG TSHGL — r Fi. For programmingconditionssee Figure 5.O-PI. .. w I-8. ” ..-.7 (ENABLE) TELOV \ 1 ‘ 272318-14 For verificationconditionssee Figure 6.“4-s . .8.. 16 .” PROGRAMMING P1.

4 of Port 2.25V *ALE/PROG pulsedlowfor 100USfor programming.6 ALE/PROG ~25 875X. —. and ~/Vpp should be held at the “Program” levels indicated in Table 1. and RST. The setu’p is shown in Figure 8. ~ ~“ 1~ P3.7 1 1 1 1 0 0 NOTES: “1” = Validhighfor that pin “O” = Validlowfor that pin “vpp” = + 12. Programming EPROM the Table4. XTAL1 ‘ks P2. +5V Vcc Po 1~ RST E/vpp ~ +12. Then ~/Vpp is raised to Vpp.6 ~o XTAL2 4-6 MHz u lJ- T= = .7 1 0 1 1 1 0 P2. Waveforms and detailed timing specifications are shown in later sections of this data sheet.75V 100 p.) The address of an EPROM location to be programmed is applied to Porl 1 and pins P2.4 272318-15 Figure8. ALE/PROG is pulsed low to croaram the code bvte into the addressed EPROfl location.7 P2. EPROM Programming odeafor 875XBH M MODE Program Code Data Verify Code Data Program Encryption Tabie Use Addresses O-1FH ~= 1 Program Lock Bits (LBx) Read Signature x=2 — RST 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 ALE/ — PROG o* 1 o* o* o* 1 ml Vpp Vpp 1 Vpp Vpp Vpp 1 P2. while the code byte to be programmed into that location is applied to Port O.Quick-Pulse rogramming) is ( P 17 . PSEN. the 875XBH must be running with a 4 to 6 MHz oscillator. The Vpp source should be well regulated and free of glitches.inlA Programming the 8751BH/8752BH To be programmed.75V+ 0.O.O -P2.. Note that the ~/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. MCS” 51 CONTROLLER Normally ~&is held at a logic high until just before ALE/PROG is to be pulsed.6 0 0 0 1 1 0 P3. The voltage on the ~/Vpp pin must be at the valid EA/Vpp high level before a verify is attempted.6 1 1 0 1 0 0 P3. and then ~/Vpp is returned to a valid high voltage.7 ~1 P2. PULSESTO GND 1~ P3. ALE/PROG is pulsed low.P2. Even a narrow glitch above that voltage level can cause permanent damage to the device. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal registers. The other Port 2 and 3 pins.

which is shown in Figure 10. The features of the new programming method are a lower Vpp (12. verification of programming is by observing that their features are enabled. PROGWaveforma +~v 272318-16 AO-A7 1 4-6 MHz u L = ‘r-F’ Vcc Po P! PGM DATA RST rmpp P3. the entire array should be verified. the onchip Program Memory can be read out for verification purposes.O -P2. The address of the Program Memory location to be read is applied to Port 1 and pins P2. For example.MIN I “ 100JM *lops ALE/PROG : 0 1 Figure9. The user must know the Encryption Array contents to manually “unencrypt” the data during verify. the data present at Port O will be Code Data XNOR Encryption Data.6 ALE/PRW = 1 B75xBH 0 0 P3.75 volts as compared to 21 volts) and a shorter programming pulse. but with the setup as shown in Table 4. PROGRAM VERIFICATION If the Lock Bits have not been programmed.) The setup.75 f 0. or may be used as an active low read strob~. After programming. it is possible to program the entire 8 Kbytes of 875XBH EPROM memory in less than 25 seconds with this algorithm! To program the part using the new~rithm. External pullups are required on Port O for this operation. The other pins should be held at the “Verify” levels indicated in Table 1. The Program Lock features are programmed using the same method. (If the Encryption Array in the EPROM has been programmed. The only difference in programming Lock features is that the Lock features cannot be directly verified. 25 times as shown in Figure 9. Then.P2. if desired.7 is held at a logic low.Verifying EPROM the 18 .MCS@51 CONTROLLER QUICK-PULSE PROGRAMMING ALGORITHM The 875XBH can be programmed using the QuickPulse Programming Algorithm for microcontrollers. The contents of the addressed location will come out on Port O.7 (i-mm XTAL2 P2. ALEM ~25p”LsEs ~ n-------10 P. ALE/PROG is pulsed low for 100 pseconds.4. either during or after the programming operation. .25 Volts.6 0 XTAL1 Vss P2.O . Vpp must be 12.7 P2. Instead.4 A8-A12 F h 10kJl X8 272318-17 Figure10. is the same as for programming the EPROM except that pin P2. the byte just programmed may be verified.

6 and P3. It is recommended that whenever the Encryption Array is used. creating an Encrypted Verify byte. The values returned are: (030H) = 89H indicates manufactured by Intel (031H) = 51H indicates 8751BH 52H indicates 8752BH 19 . P = u MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. ENCRYPTION ARRAY Within the EPROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify. at least one of the Lock Bits be programmed as well. EA is sampled and latched on reset. will return the code in its original. the internally latched value of the ~ pin must agree with its external state. and further programming of the EPROM is disabled Same as above. To ensure proper functionality of the chip.MCS@51 CONTROLLER Table5. but Verify is also disabled IReservedfor Future Definition I P U I I P P = Programmed = Unprogrammed LOCK BITS Also included in the EPROM Program Lock scheme are two Lock Bits which function as shown in Table 5. (Code Verify WIIIstill be PROGRAM MEMORY LOCK The two-level Program Lock system consists of 2 Lock bits and a 32-byte Encryption Array which are used to protect the program memory against software piracy. READING THE SIGNATURE BYTES The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H. Erasing the EPROM also erases the Encryption Array and the Lock Bits. 5 address lines are used to select a byte of the Encryption Array. LockBitsandtheirFeatures LogicEnabled LB1 u Minimum Program Lock features enabled. except that P3. returning the part to full unlocked functionality. The algorithm. This byte is then exclusive-NORed (XNOR) with the code byte. with the array in the unprogrammed state (all 1s).7 need to be pulled to a logic low. unmodified form.

Erasure leaves the array in an all Is state. or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. should be sufficient. exposure to these light sources over an extended time (about 1 week in sunlight.5 Max 13.7 (ENABLE) High to Vpp Vpp Setup to PROG Low Vpp Hold After PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE PROG High to PROG Low 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 8 ps ps 110 48TCLCL 48TCLCL ps o 10 48TCLCL ps EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING ADDRESS VERIFICATION ADDRFSS TAvQV DATAIN ‘::=&z TDVGL TAVGL Pu& ~ . If an application subjects the device to this type of exposure.-TGHDX ~ TGHAX DATAOUT } TSHGL TGLGH ~wpp d TGHGL t TGHsL [A/HIGH TELQV L TEHQZ P2. Vss = OV) Symbol Vpp Ipp Parameter Programming Programming Supply Supply Voltage Current Min 12.7 272318-18 20 . EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (T.0 50 Units v mA MHz 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Oscillator Frequency Address Setup to PROG Low Address Hold After PROG Data Setup to PROG Low Data Hold After PROG P2. it is suggested that an opaque label be placed over the window.OV + 10%. Vcc = 5.000 pW/cm rating for 30 minutes. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at lease 15 W-see/cm. Since sunlight and fluorescent lighting have wavelengths in this range.MCS” 51 CONTROLLER ERASURE CHARACTERISTICS Erasure of the EPROM begins to occur when the 8752BH is exposed to light with wavelengths shorter than approximately 4.000 Angstroms. at a distance of about 1 inch.4 = 21°C to 27”C. Exposing the EPROM to an ultraviolet lamp of 12.

MCS@51 CONTROLLER DATA SHEET REVISION HISTORY Datasheets are changed as new device information becomes available. The following differences exist between this datasheet (272318-002) and the previous version (272318-001): 1. This datasheet (272318-001) replaces the following datasheets: MCS@51 Controllers (270048-007) 8051AHP (270279-004) 8751BH (270248-005) 8751 BH EXPRESS (270708-001) 8752BH (270429-004) 8752BH EXPRESS (270650-002) 21 . Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. Removed QP and QD (commercial with extended burn-in) from Table 1. EXPRESS Prefix Identification.