Intel 8086 Microprocessor Architecture

Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below). 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte 32-bit addresses are stored in "segment:offset" format as: address: low-order byte of segment address+1: high-order byte of segment address+2: low-order byte of offset address+3: high-order byte of offset Physical memory address pointed by segment:offset pair is calculated as: address = (<segment> * 16) + <offset> Architecture 8086 has two blocks BIU and EU. The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU Features It is a 16-bit up. 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Word size is 16 bits and double word size is 4 bytes. It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. Address ranges from 00000H to FFFFFH Memory is byte addressable - Every byte has a separate address. Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.

To differentiate between Pentium 4 CPUs running at the same attempted to improve performance primarily by increasing CPU frequency. and pin-less 775-land LGA package that required socket775 motherboards. To improve efficiency of very deep pipeline the Pentium 4 processors included new features: Trace Execution Cache.Data memory . Stack or Extra segments can be usually done by prefixing instructions with the DS:. as well as some Prescott processors.the 8086 processor can access data in any one out of 4 available segments.after RESET the processor always starts program execution at the FFFF0h address.20-stage pipeline (not counting decoder stages). Stack memory can be placed anywhere in memory. starting from Prescott core. and sometimes slower than the fastest Pentium III microprocessors. and Virtualization technology. Server-class CPUs that were built on NetBurst microarchitecture were branded Xeon and Xeon MP. they allow CPU core to reach higher frequencies. Because the first generation of Pentium 4 processors. Accessing data from the Data. while two other packages were designed for desktop systems only. and thus increase CPU performance. One of key elements in this approach was "Hyper-Pipelined Technology" . While longer pipelines are less efficient than shorter ones. which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). All Pentium 4s were manufactured in three types of packages . faster FSB frequency.Northwood microprocessors with 512 KB L2 cache (for frequencies 2 GHz and lower). * C . appended to CPU frequency: * A . which differed significantly from P6 micro-architecture used in Pentium II/Pentium III microprocessors. 478pin micro-PGA package that worked in socket 478 motherboards. SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). First Pentium 4 microprocessors. . * E . SSE3 instruction set. were assigned processor numbers that uniquely identified processor frequency and features.larger size of level 2 cache. Later generations of Pentium 4 CPUs. based on Willamette core. Intel used one letter suffix. * B .FFFFFh . Low-cost NeBurst microprocessors were manufactured under "Celeron" brand. or Prescott CPUs with 1 MB L2 cache (for frequencies higher than 2 GHz). The NetBurst microarchitecture used different approach .processors featuring Hyper-Threading technology and 800 MHz FSB. o Reserved locations: o o 0000h . FFFF0h . that was significantly longer than in previous generation of Pentium processors. and Hyper-Threading technology. and Quad Data Rate bus.03FFh are reserved for interrupt vectors. Socket 478 package was used by both desktop and mobile microprocessors. but it is not recommended for performance reasons (see "Data Memory" above). Code. Each interrupt vector is a 32-bit pointer in format segment:offset. CS:. "Pentium 4" brand was used only for high-performance single-core desktop and mobile microprocessors. The stack can be located at odd memory addresses. often at at the expense of efficiency. but having different features.423-pin PGA package for socket 423 motherboards.processors with 533 MHz FSB frequency. proved to be performing not significantly faster. Please see Intel desktop processor numbers page for more information. including P6. Pentium 4 CPUs are based on new NetBurst micro-architecture. The processor uses two memory accesses to read 16bit word located at odd byte boundaries. based on Willamette and Northwood cores. Intel Pentium 4 CPUs also included 144 new SIMD instructions called SSE2. Dual-core NetBurst-based microprocessors were branded Pentium D. As an overall CPU performance is proportional to its frequency and its efficiency. Intel added more efficiency improvements to subsequent Pentium 4 core generations . Enhanced Branch prediction. o Word data can be located at odd or even byte boundaries. Other features that were eventually added to the family are 64-bit instruction set. to achieve better performance levels many micro-architectures. strike a delicate balance between faster CPU frequencies and improved efficiency.Prescott CPUs with 1 MB L2 cache. were referenced by their speed. Reading word data from even byte boundaries requires only one memory access. Intel Pentium 4 Family Intel Pentium 4 is a family of high-performance microprocessors that succeeded Pentium III family.

Although these processors had the same power-saving features of Pentium 4-M microprocessors. lower power consumption than Willamette CPUs. More recent Prescott processors also supported EM64T (64-bit technology). Mobile Pentium 4-M processor family was replaced by mobile Pentium 4 family. To improve processors performance the sizes of level 1 data cache and level 2 cache were increased.6 GHz. Mobile Pentium 4-Ms also included speed-step technology and Deeper Sleep mode.20% speed boost over Willamette processors. besides that there were no major changes in microprocessor microarchitecture.Northwood . The processors had either 512 KB (Northwood core) or 1 MB (Prescott core) level 2 cache. Front-side bus frequency in first Northwood microprocessors didn't change. the part number specifies speed as 1. etc.was a die shrink of Willamette core. Based on 0. Desktop Pentium 4 Northwood Next Pentium 4 core . power consumption of these CPUs was significantly higher than the one of Mobile Pentium 4-M processors. Some Northwood mobile CPUs and all Prescott processors included Hyper-Threading technology.13 micron technology. Pentium 4 EE family was ultimately replaced by a family of dual-core processors branded as "Pentium Extreme Edition" Mobile Pentium 4-M The first Pentium 4 family of mobile microprocessors was Pentium 4-M. and. the power consumption of Prescott-based mobile Pentium 4 was so high. Extreme Edition CPUs incorporated such features as very large level 3 cache or increased Front-Side Bus frequency to achieve somewhat better performance than comparably clocked Pentium 4 processors. The mobile microprocessors were based on two Intel Pentium 4 cores . Pentium 4 Cedar Mill 3. Support for new SSE instructions was added to all Prescott-based Pentium 4 CPUs. Being socket-compatible with microprocessors from other Pentium 4 families. the last single-core Pentium 4 core.065 micron technology. The processor is not marked with specific speed. All processors in this family had 0.13 micron Northwood core. Desktop Pentium 4 Extreme Edition Started as a direct competitor to Athlon 64 FX family. Northwood microprocessors had lower voltage. Micro-architecture of this core didn't change from previous Prescott core. Intel Pentium 4-M microprocessors had lower core voltage and lower thermal design power than desktop Northwood month before Intel announced Pentium 4 brand name and six months before the Pentium 4 family was officially launched. Bigger L2 cache gave Northwood processors 5% . and different parts of the core were optimized .official price of all newly introduced Extreme Edition processors was $999 per piece. Over time the bus frequency was increased to 533 MHz. The only advantage of Cedar Mill processors over Prescott processors is their lower power consumption.branch prediction enhanced. In fact. as a result. data pre-fetching improved. Desktop Pentium 4 Prescott More than just a die shrink of the previous Northwood core. Prescott core was revamped with the goal of reaching higher frequencies and further increasing processor performance.X GHz. Execute disable bit and Virtualization features. To achieve higher frequencies the processor pipeline was increased to 31 stages. and finally to 800 MHz. Small increase in CPU performance came at a hefty price . was built on 0. therefore performance-wise they are as fast as Prescott CPUs. 400 Mhz effective Front Side Bus (100 MHz quad-pumped bus) and 512 KB level 2 cache.Desktop Pentium 4 Willamette This processor was manufactured in second half of May of 2000 . Pentium 4 Extreme Edition family comprises of the best performing Pentium 4 microprocessors. The microprocessors were manufactured in 478-pin micro-PGA package without integrated heatsink. For instance. The size of level 2 (L2) cache in this core was increased to 512 KB. and 533 MHz Front side Bus. .6 GHz has 30 Watt lower Thermal Design Power (TDP) than Pentium 4 Prescott 3.Northwood and Prescott. Mobile Pentium 4 Mobile Pentium 4 was the last generation of mobile microprocessors with NetBurstmicroarchitecure. Desktop Pentium 4 Cedar Mill Cedar Mill. that it hardly could be considered a "mobile" processor. execution time of a few instructions reduced.

However. RAM includes a pre-defined set of bytes that can store a limited amount of information. interpreting it and sending messages to the ALU or registers to carry out the instruction. lighter and improved hand held machinery. The microprocessors are considered as devices that make instant decisions and carry out multiple commands with the help of the decisions. video or audio. communications in the twenty first century has lead to various innovations in microprocessors. keyboard or scanner. The microprocessor stores volatile data used by programs in RAM. The central processing unit acts as the brain of a computer and consists of one or more microprocessors made up of several thousand transistors on a single integrated circuit. The microprocessor does enable to transfer data from one location to another. medicine. instructions. The ALU also gathers data from additional sources. Arithmetic Logic Unit The arithmetic logic unit gathers information as input from the CPU registers and operands and then does the arithmetic operations (addition. multiplication and division) and logic operations (AND. and performs a function on that data. memory and input/output devices. OR and XOR). if a user using a word processor presses "m" on the keyboard. or circuits that store bits. such as a mouse. the read only memory and secondly. For example. It is the size of a chip which contains billions of various transistors. the ALU tests conditions and prepares to take different actions based on results. detects abnormal conditions. such as a monitor or printer. but it does not lose information when a computer shuts down as does RAM. Microprocessors have improved our lifestyle due to new enabled.Functions of a Microprocessor Microprocessors are small chips that carry out all the roles of CPU. which together constitute the microprocessor. subtraction. The two memories are responsible for any microprocessor to function properly. It also decides where to keep information in memory and which devices to communicate with by interfacing with the ALU. The microprocessor works in conjunction with other parts of the computer to compute arithmetic and logic functions to handle tasks using an instruction set to perform all. The first ever microprocessor was introduced by Intel in the year 1971. It is a device that allows a computer to work. The other function of microprocessor is to conduct and carry out executions in all kinds of formats be it data. The processor was called Intel4004 and carried out most simple operations related to mathematics. . Basic operation of microprocessor A microprocessor manipulates data in a computer system. The register and coder do help the microprocessor to carry out the required duties and instructions. we have already entered the digital age whereby microprocessors sometimes do not exist. ROM as a program includes a finite set of instructions that is combined with a constant set of bytes. Firstly. It makes a decision based on the data. Memory The microprocessor accesses and stores binary instructions into memory. the microprocessors can conduct any operation or computation accurately at the earliest. During data processing. as readable information for the user. They have the power to calculate mathematical operations using algorithms. random access memory. Random access memory is a control memory that uses registers to temporarily store data. It performs in same distinct way whether incorporated on laptops or servers. such as the power source. The information that you require is shifted to the hard drive in split seconds. the microprocessor computes the information and then it sends the results to the output devices. The year after 1970s saw 4 bit and 8 bit microprocessors. such as adders and subtracters. The recent developments in the field of technology. Read-only memory stores data permanently on chips with instructions built in. Due to floating point processors. the microprocessor will accept that and send the letter "m" to the monitor. including number systems. The control unit can also shut down a computer if it or another device. It takes longer to access the information in ROM. Control Unit The control unit directs the flow of operations and data by selecting one program statement at a time. Input and Output The microprocessor accepts input from devices. timing and data routing circuits.

The real address mode and the protected virtual address mode. Address unit All memory and I/O read /write operations are performed by BU.5 MHZ (AMD and Harris later pushed the architecture to speeds as high as 20 and 25 MHz. This type of parallel operation is called pipelining. Floating point processors allow microprocessors to perform sophisticated computations quickly and accurately. 80386 Microprocessor The Intel 80386 (also called Intel386) is a microprocessor which has been used as the CPU of many personal computers since 1986. The 6 MHZ model operates at 0. 80286 microprocessor The Intel 80286 was introduced on February 1. The address unit computes address of memory or I/O devices. mouse. scanner. As explained in the real address mode the processor can address up to 1MB of the physical memory. Its initial releases were of 6 and 8 MHZ but they were subsequently scaled up to 12.4MIPS for the 33MHz model. which is to be sent by BU for read and write operation.9 MIPS. Microprocessors allow you to transfer information from a USB flash drive to your computer's hard drive in a matter of seconds.21 Million instructions per clock. Allmodern 16 bit CPU use pipelining. THE 80286 contains four processing units: 1. speaker or digital camera. using the binary system of encoding and decoding data. The function of IU is to decode the perfected instructions and to maintain a queue of 3 decoded instructions for execution. During its design phase the processor was code-named simply p3 . Modern processors have the ability to perform large arithmetic computations using floating point processors. the 10MHZ model at 1. the third generation processor in the x 86 lines but it is normally referred to as eitheri386 or just 386.) On average. There are two operating modes for 80286. The EU executes instruction. The virtual address mode is for multiuser and multitasking system. It was the first x86 processor to have 32 bit architecture. As explained earlier it is an advanced version of 8086 but with a different architectural philosophy. Instruction unit 3. The microprocessor sends and receives data through the system bus to communicate with the peripherals. depending on the size of the file being moved. Bus unit 2. In pipelining several execution units in a processor work simultaneously in parallel. It was widely used in IBM PC compatible computers during the mid-1980s to early 1990s.Information Exchange The system bus connects the microprocessor to the peripherals. 1982 (also called Intel 286 or iAPX 286) belongs to the family of 8086. The 80286 s performance was more than twice of its predecessors (the intel 8086 and 8088) per clock cycle. The instruction register and instruction decoder. All the four units work in parallel within the CPU. The 80386operated at 5 million instructions per second to 11. While the current instruction is being executed. printer. Significance A microprocessor helps to move data from one memory location to another. the BU prefetches instructions and keeps them in a queue of six bytes. respectively. Features A microprocessor performs mathematical functions using its arithmetic logic unit. Benefits Microprocessors make quick decisions and handle multiple instructions based on those quick decisions. Execution unit 4. such as a keyboard. Also users cannot interfere with the operating system.8 MIPS. It only communicates with one peripheral at a time so as to not mix up any information and send it to the wrong place. In this mode of operation the memory management unit can manage upto 1 GB of the virtual memory though the real memory may be much less. Here the complex mathematical operations took fewer clock cycles compared to the 8086. with a basic programming .5 MIPS. and the 12 MHZ model at 1. allowing the microprocessor to quickly perform user requested tasks. These features are called protection. (ALU). is a high performance 16 bit microprocessor. the 80286 had a speed of about 0. only 16 MB. Basically in this mode one user do not interfere with the other. The control unit controls the timing of the information exchange.

SL and DX. Instruction decode unit The code prefetch unit contains a 32 byte queue to store fetched instruction codes. 80186. code prefetch unit. The 80386 was widely used in powerful PCs before the 80486 was developed. As this is a 32 bit microprocessor ithas a circuitry of 275000 transistors. It is 3 to 5 times faster than 80386. six 16 bit segment registers. The 486 contains the following functional units: Segmentation unit Execution unit Control unit Paging unit Bus interface unit Cache unit Code prefetch unit Floating point unit. In the scale indexed addressing the contents of an indexed register are multiplied with a scaling factor and the result is added to the displacement to obtain the operand s offset. It has the provision for both memory segmentation and paging. base scale indexed. It executes many of its instructions inone clock cycle by using highly pipelined execution units. 486 was generally used in high end microcomputers and network environments. It contains a 32 bit CPU. It has the protection mechanism for this type of environment. indexed. also has a 32 bit instruction pointer. As explained earlier it has 32 bit register and has eight general purpose registers. based. immediate. 8K byte of code and data cache memory on the chip. base indexed. It has basically six functional units: bus interface unit. It contains an electronic circuitry of 1. The segmentation unit calculates linear address (the starting address of the segment plus the offset) from the logical address. unified instruction and data cache memory and memory management unit in a single IC. Therefore. instruction decode unit. register indirect. base indexed with displacement and base scale indexed with displacement addressing. the 486 is a high speed. The 80386 has 32 bit registers and is upward software compatible with the 8086. In summary. Basically this is available in two versions: DX and SX. The DX type version is a 32 bit processor housed in a 168 pin grid array package and can operate with the clock frequencies from 25 to 66 MHz as explained earlier. 66 and 100MHz. These versions operate from 20MHz to 33MHz. a floating-point math coprocessor. Basically we do not use 80486 but instead of that we usei486 because of a court ruling that prohibited trademarking numbers. Basically this microprocessor has three versions: 80386SX. six debug registers and a 32 bit status register. The control unit also contains a control ROM to store microcodes. The execution of the instructions is highly pipelined and the processor is designed to operate in a multiuser and multitasking environment. high performance 32-bit microprocessor. a math coprocessor is an external device. The address given in the program is called the logical address. 80286 microprocessors. It is compatible with 8086. The paging unit provides the paging facility within a segment. Its operating frequency for its different versions is 25. Therefore the execution time for many instructions is one clock period.2 million transistors. Successively newer implementations of this same architecture have become literally several hundred times faster than the original i386 chip during these years. In the real mode physical address space is 1Mbytes (20 address lines). the math instructions in 486 systems are executed three times faster than in 386 systems. A page is of fixed size 4KB each. Highly pipelined execution unit. In the early 1990s. It also provides 4-level of protection for isolating and protecting tasks and the operating system from each other. The 80386 has a segment descriptor register associated with each segment register. execution unit. In the 386 system. The 80386 has 11 addressing modes: register. It also contains amour-level protection mechanism on the chip itself. segmentation unit and the paging unit. It has a total of 129 instructions.model that has remained virtually unchanged for over 20 years. 33. The DX version has a 32 bit internal architecture and a 32 bit data bus whereas the SX and the SL version have a 32 bit internal architecture but a 16 bit wide data bus. It is designed to facilitate the execution of high level languages and suited for multiprocessing and multitasking systems. direct. The primary difference between these modes is the availability of the memory space and the addressing scheme. Intel dropped number-based naming altogether with the successor to the i486-the Pentium processor. Segment vary in size. The important additional features of the 486 processor in comparison with the 386 processor are as follows. The 486 processor includes: Built in math coprocessor. It was basically introduced in the year 1985. It is capable of addressing 4G bytes of physical memory and through its memory management unit it can address 64 terabytes of the virtual memory. It translates the linear address into the ROM existing in a computer is known as physical memory. 80486 Microprocessor Basically this is an upgraded advanced version of 80386 and it was released in the year 1989. The SL version consumes less power and is basically used in laptops and notebooks. scale indexed. which is extended to 4G bytes in the protected mode (32 address lines). The 80386 is a 32 bit microprocessor with a no multiplexed 32 bit address bus housed in a 132 pin grid array package.8088. The segmentation and the paging unit constitute memory management unit. . The processor can operate in two modes: Real and protected. 4GB is the maximum size of a segment.

BHE is low during T1 for read. T3 and T4. these lines are low. A16/S3: These are the time multiplexed address and status lines. Tw of any read cycle. . The signal is active low and tristated during hold.T3. The signal remains tristated during the hold acknowledge. The signal is active high. A18/S5. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. whenever a byte is to be transferred on higher byte of data bus.Pin Configuration of 8086 The following signal descriptions are common for both modes. READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. *Address remains on the lines during T1 state. AD15-AD0: These are the time multiplexed memory I/O address and data lines. The status line S6 is always low. BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in table. A17/S4. Tw and T4. while the data is available on the data bus during T2. * During memory or I/O operations. status information is available on those lines for T2. RD Read: This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. The status information is available during T2. * During T1 these are the most significant address lines for memory operations. T3. * During I/O operations. * The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.Tw and T4. It is low during T1 for the first pulses of the interrupt acknowledge cycle. * These lines float to tri-state off during the local bus hold acknowledge. T3. * The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig. RD is active low and shows the state for T2. A19/S6. write and interrupt acknowledge cycles. * The address bit is separated from the status bit using latches controlled by the ALE signal.

i. This is sampled during the last clock cycles of each instruction to determine the availability of the request. it will release the local bus during T4 provided: 1. S1. When it is low. the processor enters the interrupt acknowledge cycle. 2. the processor has accepted the interrupt. This can be internally masked by resulting the interrupt enable flag. It is active from the middle of T2 until the middle of T4. it indicates the CPU is having an I/O operation. when it goes low. and when it is high. If any interrupt request is pending. When the processor sends out data. This signal is active high and is never tristated. It is used to enable the transceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. HLDA. When the processor detects the HOLD line low. in the middle of the next clock cycle after completing the current bus cycle. this signal is low. it indicates that the CPU is having a memory operation. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles. The current cycle is not the first acknowledge of an interrupt acknowledge sequence. The current cycle is not operating over the lower byte of a word. 4. 3. HOLD. This is tristated during hold acknowledge cycle. The processor. HOLD is an asynchronous input. It s an asymmetric square wave with 33% duty cycle. issues the hold acknowledge signal on HLDA pin.e. M/IO Memory/IO: This is a status line logically equivalent to S2 in maximum mode. the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. and is connected to latch enable input of latches. S2. CLK. INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. LOCK: This output pin indicates that other system bus master will be prevented fromgaining the system bus. If the DMA request is made while the CPU is performing a memory or I/O cycle. and is should be externally synchronized. When the CPU is executing a critical instruction which requires the system bus. RQ/GT0. else the processor remains in an idle state. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. it indicates to the processor that another master is requesting the bus access. being carried out by the processor. If the TEST pin goes low. A Lock instruction is not being executed. ALE Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines. S0 Status Lines: These are the status lines which reflect the type of operation.Acknowledge: When the HOLD line goes high. This signal is active high and internally synchronized. after receiving the HOLD request.Clock Input: The clock input provides the basic timing for processor operation and bus control activity.INTR-Interrupt Request: This is a triggered input. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through the transceivers (bidirectional buffers). RQ/GT1 Request/Grant: These pins are used by the other local bus master in maximum mode. At the same time. DEN Data Enable: This signal indicates the availability of valid data over the address/data lines. TEST: This input is examined by a WAIT instruction. The request occurs on or before T2 state of the current cycle. Pin Configuration of 8088 . the processor floats the local bus and control lines. it lowers the HLDA signal. It is tristated during local bus hold acknowledge . to force the processor to release the local bus at the end of the processor current bus cycle. while the LOCK signal is low. The input is synchronized internally during each clock cycle on leading edge of clock. this signal is high and when the processor is receiving data. execution will continue.

Tw. depending on the state of the IO/M pin or S2. and is guaranteed to remain HIGH in T2 until the 8088 local bus has floated. T3 and Tw of any read cycle. A17/S4. This information indicates which segment register is presently being used for data accessing. This signal is active HIGH.Pin Configuration of 8088 AD7±AD0 . RD is active LOW during T2. INTR is internally synchronized. READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. This signal is used to read devices which reside on the 8088 local bus. these lines are LOW.ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2. During I/O operations. A19/S6. these are the four most significant address lines for memory operations. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. . S6 is always low. The 8088 READY input is not synchronized.READ: Read strobe indicates that the processor is performing a memory or I/O read cycle. A15±A8 are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''. A18/S5. If the TEST input is LOW.ADDRESS/STATUS: During T1. otherwise the processor waits in an ``idle'' state. A16/S3 .ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1±T4). RD . S4 and S3 are encoded as shown. status information is available on these lines during T2. A subroutine is vectored to via an interrupt vector lookup table located in system memory. T4) bus. Tw.INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. Correct operation is not guaranteed if the set up and hold times are not met. T3. TEST: input is examined by the ``wait for test'' instruction. These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''. T3. A15±A8 . This input is synchronized internally during each clock cycle on the leading edge of CLK. and T4. These lines do not have to be latched by ALE to remain valid. It can be internally masked by software resetting the interrupt enable bit. The RDY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. INTR . This signal is active HIGH. During memory and I/O operations. These lines float to 3-state OFF during local bus ``hold acknowledge''. This signal floats to 3-state OFF in ``hold acknowledge''. execution continues.

and Tw of each interrupt acknowledge cycle. WR is active for T2. the processor lowers HLDA. The combination of SSO. and floats to 3-state OFF in local bus ``hold acknowledge''. It restarts execution. CLK . RQ/GT has an internal pull-up resistor.STATUS LINE: is logically equivalent to SO in the maximum mode. R e LOW). Logically. as described in the instruction set description. A subroutine is vectored to via an interrupt vector lookup table located in system memory. For a read or INTA cycle. DEN is active LOW during each memory and I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I/O e HIGH. External synchronization should be provided if the system cannot otherwise guarantee the set up time. INTA . Each pin is bidirectional with RQ/GT0 having higher priority than RQ/ GT1.CLOCK: provides the basic timing for the processor and bus controller. in the middle of a T4 or Ti clock cycle. VCC: is the a5V g10% power supply pin.INTA: is used as a read strobe for interrupt acknowledge cycles.I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Me LOW). it will again drive the local bus and control lines. while for a write cycle. HOLD must be active HIGH. NMI is not mask able internally by software. Simultaneous with the issuance of HLDA the processor will floatthe local bus and control lines. Hold is not an asynchronous input. WR . it is active from the middle of T2 until the middle of T4.HOLD: indicates that another master is requesting a local bus ``hold''. IO/M and DT/R allows the system to completely decode the current bus cycle status. RESET: causes the processor to immediately terminate its present activity.WRITE: strobe indicates that the processor is performing a write memory or write I/O cycle. To be acknowledged. T3. . SSO . A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. HOLD. HOLD and HLDA have internal pull-up resistors.NMI . DEN floats to 3-state OFF during local bus ``hold acknowledge''. in the middle of a T4 or Ti clock cycle. HOLD. when RESET returns LOW. and when the processor needs to run another cycle. it is active from the beginning of T2 until the middle of T4. GND: are the ground pins. and for INTA cycles. HOLD and HLDA have internal pull-up resistors. It is used to distinguish a memory access from an I/O access. This input is internally synchronized. To be acknowledged. RQ/GT0. This signal floats to 3-state OFF in local ``hold acknowledge''.STATUS LINE: is an inverted maximum mode S2.STATUS LINE: is logically equivalent to SO in the maximum mode.ADDRESS LATCH ENABLE: is provided by the processor to latch the address into an address latch. The signal must be active HIGH for at least four clock cycles. IO/M . Note that ALE is never floated. depending on the state of the IO/M signal. it will again drive the local bus and control lines. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement.MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. ALE . DEN . It is asymmetric with a 33% duty cycle to provide optimized internal timing. IO/M floats to 3-state OFF in local bus ``hold acknowledge''. and when the processor needs to run another cycle. The combination of SSO. HOLD must be active HIGH. The two modes are discussed in the following sections. Hold is not an asynchronous input. MN/MX . and Tw of any write cycle. so may be left unconnected.NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. After HOLD is detected as being LOW. It is used to control the direction of data flow through the transceiver. SSO . It is a HIGH pulse active during clock low of T1 of any bus cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines.DATA ENABLE: is provided as an output enable for the data bus transceiver in a minimum system which uses the transceiver. the processor lowers HLDA. DT/R . T3. and its timing is the same as for IO/M (T e HIGH. RESET is internally synchronized. IO/M and DT/R allows the system to completely decode the current bus cycle status. It is active LOW. DT/R is equivalent to S1 in the maximum mode. It is active LOW during T2. The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement. HLDA .DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus transceiver. HLDA . RQ/GT1 .HOLD: indicates that another master is requesting a local bus ``hold''. After HOLD is detected as being LOW. External synchronization should be provided if the system cannot otherwise guarantee the set up time.

25 . 168-pin SDRAM DIMMs. As a matter of fact. DDR (Double Data Rate SDRAM) DDR basically doubles the rate of data transfer of standard SDRAM by transferring data on the up and down tick of a clock cycle. each bit in the DRAM must be refreshed at least once every 2 milliseconds or the data dissipates SDRAM (Synchronous DRAM) Almost all systems used to ship with 3. SRAM Static RAM (SRAM) stores binary bits in such a manner that the bits remain in RAM as long as power to the chip is not interrupted DRAM Dynamic RAM (DRAM). RDRAM is a serial memory technology that arrived in three flavors. is used to store the information that will never be changed/ cannot be changed by the user.3 volt. This does not get erased when the computer's power is lost. DDR memory operating at 333MHz actually operates at 166MHz * 2 (aka PC333 / PC2700) or 133MHz*2 (PC266 / PC2100). while older fast page mode DRAM and EDO max out at 50 MHz. but uses a similar parallel bus. Erasable-Programmable ROM (EPROM) can also be programmed and erased by the user using ultraviolet light and special circuitry external to the computer. The queue status is valid during the CLK cycle after which the queue operation is performed. This signal is active LOW. PC800 RDRAM has doubled the maximum throughput of old PC100 SDRAM.QUEUE STATUS: provide status to allow external tracking of the internal 8088 instruction queue. and PC800. making it easier to implement than RDRAM. but a higher latency. SDRAM is not an extension of older EDO DRAM but a new type of DRAM altogether. and it will be the sole choice of memory for Intel's Pentium 4. SDRAM started out running at 66 MHz. which contains the information that the computer is using at that moment. DDR is a 2. PC600. Rambus DRAM (RDRAM) Despite its higher price. new generations of memory such as DDR and RDRAM are required to get proper performance. Intel has given RDRAM its blessing for the consumer market. Flash ROM Advancements in EEPROM technology have produced Flash ROM devices that enable new BIOS information to be written (downloaded) into the ROM to update it. such as instructions to make the computer properly boot (startup). PC700. QS1. Basic Function of RAM RAM . and floats to 3-state off in ``hold acknowledge''. periodically to keep it from fading away. For example. requires that stored data be refreshed.5 volt technology that uses 184 pins in its DIMMs. It is incompatible with SDRAM random access memory. The download can come from an update disk or another computer. or rewritten. Electrically Erasable PROM (EEPROM) can be erased and reprogrammed by special circuitry within the computer. As processors get faster. QS0 only memory. until you close the file. This will get erased if the computer's power goes off. Basic Function of ROM ROM . Types of ROM Mask-Programmed ROM (MROM) Programmable ROM (PROM) programmed at the factory. The LOCK signal is activated by the ``LOCK'' prefix instruction and remains active until the completion of the next instruction. which is a different technology.LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW). SDRAM is able to scale to 133 MHz (PC133) officially. the text you type in a word document will be stored in RAM. RDRAM designs . can be custom-programmed by the user (once) using special circuitry. Then it will be stored in the hard drive. and unofficially up to 180MHz or higher. on the other hand.

5 volts. both use special snap-in sockets that support the module firmly. especially when paired with PC1066 RDRAM memory.3 volts. rather than using a pin and socket arrangement. . you just pop in a 512 MB DIMM if you've got an available slot. units mount vertically on the system available in 30. So far there aren't many DDR chipset that use dual-channels. You have to plan more when upgrading and purchasing RDRAM. such as those in Pentium 4 motherboards.and 72-pin versions. but if used in a motherboard with a dual-channel configuration (like with an NvidianForce chipset) you must pair them to get maximum performance. DIMMs (dual in-line memory modules) are 64-bit components. if you want to add 512 MB of DIMM memory to your machine. Typically. SDRAM DIMMs have 168-pins and run at 3. while DDR DIMMs have 184-pins and run at 2. are currently at the top of the heap in memory throughput.with multiple channels. RIMMs use only a 16-bit interface but run at higher speeds than DDR. However. DIMMs for SDRAM and DDR are different. Intel RDRAM chipsets require the use of RIMMs in pairs over a dual-channel 32-bit interface. To get maximum performance. and not physically compatible. SIMMs (single in-line memory modules) .

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