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Australasian Universities Power Engineering Conference (AUPEC 2004) 26-29 September 2004, Brisbane, Australia

Ariawan Tjondronugroho, Adnan Al-Anbuky, Simon Round, Richard Duke Department of Electrical and Computer Engineering, University of Canterbury, Christchurch, New Zealand

A variety of control strategies have been used to control single-phase inverters for various power electronics applications. Each control strategy has its own advantages and disadvantages. This paper presents a brief assessment of repetitive, sliding mode, current mode and multiple-loop control strategies, as applied to single-phase PWM inverters. Controller implementation has evolved with time from traditional analogue schemes to a range of digital control options. DSP and FPGA based digital controller implementations of the multiple-loop control strategy are examined in detail. Simulated and experimental measurements of the performance of these digital controllers are presented.

Single-phase Pulse Width Modulated (PWM) inverters have found widespread application in Uninterruptible Power Supplies (UPS) for telecommunication applications. The control strategy of a PWM inverter is one of the key aspects that influence its performance, size and cost. Many closed-loop control strategies with the purpose of improving the output signal quality of a single-phase PWM inverter have been proposed over past decades [1]-[11]. Traditional closed-loop analogue control systems have been implemented at the expense of high complexity and low efficiency due to the large number of components. Since the introduction of microprocessors, the control strategy of power converters has evolved very rapidly. Microprocessor based controllers have proven to be more flexible, reliable and cheaper than the analogue equivalent. However their computational power limits the possibility for implementing complex algorithms [1], [2]. With the computational power of Digital Signal Processors (DSP), complex algorithms can be easily implemented. Nowadays, digital control for power converter applications is becoming very widely used. More processing power can also be obtained by using fully programmable logic devices such as the Field Programmable Gate Array (FPGA). Many fully digital inverter controllers have been reported, each with their own advantages and disadvantages [1]-[8]. This paper presents a general evaluation of different types of closed-loop digital control systems for PWM

inverters. Four typical control strategies, namely repetitive, sliding mode, current mode and multiple-loop were evaluated. The efficiency of the controller is measured by means of output signal quality and the complexity of the control algorithms. The multiple-loop control is the most efficient controller. This strategy has been verified by both simulation and experiment, using DSP and FPGA technologies.

In order to produce a stable and reliable ac waveform, the output signal of an inverter must be regulated by a robust controller. A range of control strategies are available and these will be briefly explained and assessed.
2.1 Repetitive Control

Closed-loop regulation of a PWM inverter normally gives satisfactory results, but occasionally it suffers from periodic disturbances. Repetitive control utilises the repetitive nature of disturbances and provides a solution to remove periodic error that occurs in a dynamic system. Figure 1(a) shows a cascaded repetitive control structure. In this system, the repetitive controller is cascaded in between two negative feedback loops of the output voltage. Feedforward repetitive control is shown in Figure 1 (b). The purpose of the tracking controller is to improve the transient response of the system and make it insensitive to external disturbances [6].

relatively complicated, noise prone and expensive to build. (a). Cascaded Repetitive Control Analogue implementation of the sliding mode control is difficult and has limited control functions. However, digital implementation with finite sampling frequency would violate the basic assumption of infinite switching frequency on this controller [8]. A few fixed frequency discrete sliding mode control methods have been proposed [8], [11].
2.3 Current Mode Control

(b). Feedforward Repetitive Control Figure 1 Repetitive Control Structures Repetitive control can be viewed as a periodic waveform generator augmented within the control loop of a control system, which is closed-loop regulated by a feedback controller, so that the periodic errors can be eliminated [6]. The controller improves the accuracy of the steady state response of a control system when reference input signals and disturbances are periodic [10]. An advantage of the repetitive control structures is that only the output voltage is required as a feedback signal, which reduces the hardware cost. The major drawback from this type of controller is that it is only effective when the disturbance is a harmonic of the fundamental and in some cases it will actually amplify a non-harmonic disturbance [3]. A complex compensation network is required to ensure stability as well as the requirement of either a good knowledge or continuous automatic identification of the load [3]. Although the control action does not need to be very fast to achieve a high quality voltage output, its complexity makes it difficult to be implemented on a low-cost DSP or a microcontroller.
2.2 Sliding Mode Control

Current mode control evolved from voltage mode control, in which the output is regulated by comparing the output voltage with a sinusoidal reference. While good dynamic performance can be achieved, it is not enough for non-linear loads. Furthermore, the voltage mode control strategy suffers from system stability [9]. To overcome these problems, current mode control was developed and has proven to be effective for improving the system stability and dynamic responsibility [9]. The method consists of two major feedback loops: the inner current loop and the outer voltage loop as shown in Figure 2.

Figure 2 Current Mode Control In current mode control, typically the inductor current is sensed for the regulation of the current loop and output voltage is sensed for the voltage regulation. In the outer loop, the output voltage is compared with the sinusoidal reference signal and the error is fed through a controller to produce the current reference. In the inner loop, the current reference is compared with the sensed current to produce the current error. The inner current loop effectively removes the pole of the inductor from the output transfer function, which negates the necessity of compensating two poles on the outer voltage loop. Current mode control gives a much more stable system and allows the control loop to operate at much higher bandwidth compared to a system with only a single control loop. This is the most commonly used control strategy on power inverters due to its straightforward implementation, fast dynamic response and high stability. The only disadvantage of this method is when the inverter is designed for a wide range of resistive, inductive or non-linear loads, the controller must be

Sliding mode, also known as the bang-bang control, also senses the output voltage as a feedback signal to the controller. The advantages of sliding mode control are its stability and robustness against parameter variations and external disturbances. It also eliminates the converter non-idealities such as dead times, minimum on and off times and semiconductor voltage drops [11]. The main disadvantages of the sliding mode control are the significant frequency variations of the switching transistors with the operating point or load variation, and the difficulties to foldback or even limit the short circuit output current with sliding mode output voltage control [11]. It is possible to use this control strategy with a fixed-switching frequency which will then provide output current limiting. However the technique is

tuned for the nominal load, giving poor responses with load parameters far from nominal values [11].
2.4 Multiple-Loop Control

Additional feedforward loops can be added to the current mode control to improve the quality of the output signal. This type of control system is known as multiple-loop control. Depending on the number of extra loops, multi-loop control can be made simple or very complex. A paper presented by Jung and Tzou [1] introduced the output voltage and load current as feedforward signals. In this control scheme, the output voltage behaves like a back electromagnetic force (EMF) in a dc motor, which disturbs the current loop. Similarly, the load current also acts as a disturbance with respect to the outer voltage loop. Therefore, the output voltage on the feedforward path is used for back EMF compensation and the load current is used for compensating load disturbances. On the feedback path, the output voltage is sensed for ac voltage regulation and the inductor current is sensed for regulation of the current loop [1]. Figure 3 shows the structure of the control system.

are taken with a 25W resistor and a rectifier with RC load to simulate linear and non-linear loads respectively. A sudden step change from no-load to a 25W resistive load at 90 phase delay simulates the transient response of the digitally controlled inverter. A robust controller must be used to regulate the inverter in order to maintain a high quality output under these loading conditions.
Inside DSP or FPGA PWM Generator

Sine Table


Gate Driver

Full-Bridge PWM Inverter ADC Interface Board


Inside DSP

Figure 4 Test System of the Digitally Controlled Inverter

Figure 5 Inverter Circuit Diagram

3.2 Current-Loop Controller

Figure 3 Multiple-loop Control Because multiple-loop control is much simpler than some of the other controllers, yet capable of producing high quality output, this control scheme was chosen as a prototype for evaluation of DSP and FPGA based digital controllers.

The simplified model of the inner current-loop is shown in Figure 6. The current-loop gain Kc is designed using deadbeat control theory and can be expressed by the following equation [1]:

KC =

rL e


1- e



Two test systems configured as shown in Figure 4 were built to compare the difference in performance between DSP and FPGA based digital multiple-loop controllers. Both systems incorporate the same full-bridge singlephase PWM inverter (Figure 5). Bipolar PWM signals control the switching of four MOSFETs on the fullbridge. A 50 V voltage source serves as a dc bus and supplies power to the load through the inverter. The LC filter, which is used to regenerate the sinusoidal output consists of a 1.2 mH inductor with 0.1 W equivalent series resistor (ESR) and a 20.4 mF capacitor with 3.4 mW ESR. Three loading conditions are used to simulate the system performance. Two steady state measurements

where L is the inductance of the LC filter, rL is its ESR, and TC is the sampling period of the current-loop.

Figure 6 Simplified current-loop block diagram

3.3 Voltage-Loop Controller

Figure 7 shows the simplified model of the voltage-loop controller. Deadbeat effect was also used to calculate the

voltage-loop gain Kv and can be expressed by the following equation [1]:

KV =

C TV - C rC


where C is the capacitance of the LC filter, rC is its ESR, and TV is the sampling period of the voltage-loop.

the same task more quickly than the C software. Since the multiple-loop control algorithm is quite simple, the difference in output quality between the two implementations is negligible, and therefore C software is preferred as it is much easier to code. However the assembly software will be useful when dealing with more complex algorithms.

Figure 7 Simplified voltage-loop block diagram


Table 1 Difference in the time taken by the software written in C and assembly

The multiple-loop controller was implemented on a TMS320LF2407A DSP from Texas Instruments. This 16-bit high-speed digital processor is equipped with a large number of peripherals suitable for power electronics applications. These rich features include built-in 10-bit analogue to digital converter (ADC), multiplier circuitry, PWM generator, and programmable timers. Almost all instructions can be executed in one clock cycle of 33.3 ns (30 MHz), which enables fast computation of the control algorithms. In order to reduce sideband harmonics of the output voltage, the switching frequency of the PWM signal should be an integral multiple of the sampling frequency of the digital controller [1]. The inner current loop is set to sample at 20 kHz, whereas the outer voltage loop is set to 10 kHz. These two sampling routines are generated through software interrupts by the built-in programmable timers. The first Interrupt Service Routine (ISR) serves the ADC operation, computation of the current loop control and update of the PWM duty cycle, whereas the second ISR is used by the voltage loop control. The DSP generates the PWM signals by comparing the value computed by the current loop and the value of the 20 kHz timer. These signals are then passed through the dead band circuitry which prevents short circuits on the H-bridge. Due to the large amount of memory available, a complete sinusoidal cycle can be easily stored within the DSP, which minimises the time taken to get the voltage reference value at every sampling instant. The DSP has been programmed in both C and assembly language to compare the difference in performance between the two implementations. Table 1 shows the time taken by the DSP for doing the necessary tasks. As expected, the assembly software effectively completes

A Spartan-2E FPGA from Xilinx was used to implement the multiple-loop controller. Unlike the DSP where all the required peripherals are available, everything in the FPGA must be built from scratch by programming the available logic blocks. Very high speed integrated circuit Hardware Description Language (VHDL) was used to program these logic blocks into all the required modules. The FPGA is clocked at 50 MHz, slightly faster than the TMS320LF2407A DSP. The sampling frequencies of the control loops are equivalent to those used on the DSP to provide matching comparisons between the two technologies. Since the FPGA is purely digital, analogue signals cannot be fed into it directly. The ADC module of the TMS320C2812 DSP from Texas Instruments was used to capture the feedback signals. The digital signals are transmitted to the FPGA through the DSPs serial peripheral interface (SPI) port. SPI provides high speed data transmission between the two processors. The ADC sampling rate is generated by a software interrupt through the built-in programmable timer. On the FPGA side, SPI data is coming into the assigned port and being processed accordingly. An SPI controller is programmed in VHDL to handle the incoming transmission. The serial data is passed through a serial to parallel shift register to form three separate 16-bit numbers: an inductor current, a load current and an output voltage, which are ready to be used by the controller. One quarter of a cycle sinusoid is stored within the FPGA as a voltage reference. PWM signals as well as the required dead band are generated by a module also programmed in VHDL. The timing signals for operating the inner and outer loops are generated within the FPGA. In contrast to the DSP, the FPGA system completes all operations in just 3.44 ms, due to its parallel processing.

Operations ISR 1 ISR 2 Total

C 16.7 s 8.6 s 25.3 s

Assembly 7.4 s 5.8 s 13.2 s


Figure 8 shows the steady state response of the output voltage and current for an inverter loaded with a linear load. Both systems show very good sinusoidal outputs with a voltage THD measured at 0.8%. Figure 9 shows the comparisons between the simulation and the experimental results of the digitally controlled

inverter under a rectifier with RC load. The results show that although the load current is quite distorted, the inverter is able to maintain a reasonably high quality sinusoidal output voltage. Experimental voltage THD figures for the DSP and FPGA systems were measured at 4.5% and 3.7% respectively. The output voltage from the FPGA system is better because of its higher processing power.

(a). Simulation

(b). DSP Experiment

(c). FPGA Experiment

Figure 8 Comparisons of simulation, and DSP and FPGA experimental results for an inverter loaded with a linear load

(a). Simulation

(b). DSP Experiment

(c). FPGA Experiment

Figure 9 Comparisons of simulation, and DSP and FPGA experimental results for an inverter loaded with a rectifier and RC load

(a). Simulation

(b). DSP Experiment

(c). FPGA Experiment

Figure 10 Comparisons of simulation, and DSP and FPGA experimental results for an inverter loaded with a sudden step load at 90 phase delay

Figure 10 shows results under a sudden step change in linear load at the peak of the voltage waveform, where no significant change is observed on the voltage THD. It can be seen that both the DSP and FPGA systems are able to maintain a quality sinusoidal output waveform when nonlinear load is connected. Furthermore, the similarity between the simulation and experimental results verifies the theoretical analysis of the designed multiple-loop controller.

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This paper evaluates four control strategies of a singlephase PWM inverter namely the repetitive, slidingmode, current-mode and multiple-loop control. The multiple-loop control has been implemented on a DSP and an FPGA to verify the performance of the control strategy on two different platforms. The lack of a builtin analogue to digital converter in an FPGA causes the requirement for additional hardware and an extra couple of microseconds for data communications. However, this extra time can be compensated by the parallel processing capability and the faster clock frequency of the FPGA. The additional output voltage and load current as feedforward variables have improved the robustness of the control system. The two systems can achieve fast dynamic response with low THD under different load conditions

The authors wish to acknowledge the support of engineering staff at Eaton Powerware Ltd.

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