# CS220: Introduction to Computer Organization

Lab #1
Seven Segment Decoder 04 August 2011

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Introduction

A seven-segment display is a form of an electronic display device for displaying decimal or hexadecimal numerals. Seven-segment displays are widely used in digital clocks, electronic meters and other electronic devices for displaying numerical information.

2

Concept

As indicated by the name, a seven-segment display is composed of seven display elements. Controllable individually, they combine visually to produce simpliﬁed representations of the numeric alphabet. The seven segments are arranged as a rectangle, with two segments on each side, one on the top and bottom each, and the last one bisecting the rectangle horizontally at the middle. The segments are referred to by the letters A to G as shown in the ﬁgure, where an optional DP decimal point (also sometimes referred to as the eight segment) is used for the display of non-integer numbers.

Figure 1: The individual segments of a seven-segment display.

Figure 2: 7-segment display showing the 16 hexadecimal digits.

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and implement it on an FPGA using BSV (Bluespec Verilog). etc. 4 Decoder Design In this lab. typically all of the cathodes (negative terminals) or all of the anodes (positive terminals) of the segments are connected together and brought out to a common pin. A segment on a ’common anode’ device is visible when the input at its cathode is 0.I1 .I1 .I0 + I3 . In a simple LED package. we will design a seven-segment decoder. I2 . Using this information. A seven-segment decoder receives a 4-bit number and displays the alphanumeric representation of that number (0.I2 .I2 . From Table 1.I1 .I1 . 1. The ﬁnal truth table is given in Table 1. I1 and I0 denote the 4-bit binary input. which is the type of display that we will be working with. one can write expressions for A to G in terms of the inputs I3 .I2 .I2 .I1 .I1 2 . we can determine the truth table for a particular segment by assigning a value 0 to those inputs for which the segment must be visible. I1 and I0 .I0 + I3 .I0 + I3 . 2. assuming a ’common anode’ device. with I3 being the most signiﬁcant bit. The other terminals are used to control the segments via a seven-segment decoder.3 Implementation Seven-segment displays may use a liquid crystal display (LCD) or arrays of light-emitting diodes (LEDs).I1 .I2 .I1 . The decoder design depends on whether the display is a ’common anode’ device or a ’common cathode’ device. which connect directly to the corresponding pins of the display.) on a seven-segment display.I2 . these devices are referred to as ’common cathode’ or ’common anode’ devices respectively. Design for ’common cathode’ device can be implemented in a similar manner. I2 . and the ﬁnal expressions are given below: ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ A = I3 .I2 . and knowing the inputs for which a segment must be visible.I1 . A.I2 .I2 .I0 ¯ ¯ ¯ ¯ ¯ ¯ ¯ B = I3 .I0 + I3 . I3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 B 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 C 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 D 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 E 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 F 0 1 1 1 0 0 0 1 0 0 0 0 0 1 0 0 G 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Table 1: Truth table of a seven segment decoder for a ’common anode’ device I3 . The details of this are left to the reader as an exercise.I0 + I3 .I0 + I3 .I0 + I3 . The outputs of the decoder are labeled from A to G.

I0 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ D = I3 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ E = I3 .I1 .I2 .I1 ..I1 .¯ ¯ ¯ ¯ ¯ C = I3 .I1 .. (The counter must increment at every positive edge of the clock..I0 ¯ .I1 .I1 . (BSV3/FPGA3) Let XXXX.I0 5 Exercises (BSV1) Write BSV module to convert an input hexadecimal number to the seven segement pin assignments.I0 + I3 .-> C220 -> XXXX -> YYYY -> ZZZZ -> C200 -> .I1 .I0 + I3 . For this you may need to slow down the clock.I1 . Y Y Y Y and ZZZZ denote the last 4 digits of the roll numbers of your group members.I2 .I2 .I0 + I3 . (BSV2) Design a 2-bit Unsigned Up Counter in BSV.I1 .I1 .I2 . 3 .) (FPGA2) Display the counter on the LED output screen of the board.I1 + I3 .I2 .I2 .I2 .I1 .I2 .I0 + I3 . (FPGA1) Use the module designed above to display an input hexadecimal number on an LED of the FPGA board.I0 + I3 .I0 + I3 .I2 .I2 .I0 ¯ ¯ ¯ ¯ ¯ ¯ F = I3 ¯ ¯ ¯ ¯ ¯ ¯ G = I3 .I1 .I0 + I3 .I0 + I3 .I0 + I3 .I0 + I3 . (BSV4/FPGA4) [OPTIONAL] Connect the circuits designed in Exercise (BSV2/FPGA2) and Exercise (BSV3/FPGA3) to automatically change the LED display.I2 .I0 + I3 .I2 .I2 .I1 + I3 .I2 ..I2 .I0 + I3 . The display must keep changing as: .I2 .I2 .I1 .I1 + I3 .I1 ¯ .I1 . such that XXXX ≤ Y Y Y Y ≤ ZZZZ (Is there a chance that last 4 digits are same for two or more partners ?) Design a circuit that takes a two bit input and displays the following on the LEDs: Input 00 01 10 11 LED Display C220 XXXX YYYY ZZZZ Use the module designed in Exercise [BSV1] to drive the LED displays.I1 . Write a testbench to test your module.I1 .I2 .I2 .I2 .

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