Rev 0.6 / Dec.

2009 1
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
32Gb NAND Flash
H27UBG8T2A
Rev 0.6 / Dec. 2009 2
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Document Title
32Gbit (4096 M x 8 bit) NAND Flash Memory
Revision History
Revision
No.
History Draft Date Remark
0.0
Initial Draft.
May. 22. 2009 Preliminary
0.1
Update PKG outline.
Add Marking Information .
Jun. 17. 2009 Preliminary
0.2
Update PKG Information.
Update Multi Plane Cache Program.
Jul. 16. 2009 Preliminary
0.3
Correct Multi Plane Cache Program Operation Timings (Figure 22)
Correct Random Data Input Timings (Figure 24)
Update PKG Mechanical Data (Figure 2-1)
Correct Restriction read status in multi plane operation (Figure 63)
Aug. 31. 2009 Preliminary
0.4
Correct7.5 Restriction of Read Status Value in Multi Plane Operation
Correct7.6. Page Program Failure
Sep. 21. 2009 Preliminary
0.5 Correct4.3 Multi Plane Page Read Oct. 5. 2009 Preliminary
0.6
Change 52-VLGA Contact, X8 Device (Figure 2)
Update PKG Mechanical Data (Figure 2-1)
Update Pin Description of CE#
Change Endurance
Change AC Timing Characteristics (tRC, tRP, tWC, tWP, tCLS, tCS, tALS,
tDS, tREA, tADL)
Update Read ID table (3rd Byte)
Change Bad Block Management
Dec. 14. 2009 Preliminary
Rev 0.6 / Dec. 2009 3
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Product Feature
■ Multilevel Cell technology
■ Supply Voltage
- 3.3V device : Vcc = 2.7 V ~ 3.6 V
Vcc = 2.7 V ~ 3.6 V

■ Organization
- Page size : 8,640 Bytes(8192+448 bytes)
- Block size : 256 pages(2M+112K bytes)
- Plane size : 1,024 blocks
■ Page Read Time
- Random Access: 200 ㎲ (Max.)
- Sequential Access : 25 ㎱ (Min.)
■ Write Time
- Page program : 1600 ㎲ (Typ.)
- Block erase : 2.5 ㎳ (Typ.)

■ Operating Current
- Read
- Program
- Erase
- Standby
■ Hardware Data Protection
- Program/Erase locked during power transitions

■ Endurance
- 3,000 P/E cycles (with 24 bit/ 1,024byte ECC)

■ Data Retention
- 10 Years
■ Package
- TSOP (12x20)
- LGA (14x18)

■ Unique ID for copyright protection
Rev 0.6 / Dec. 2009 4
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1. SUMMARY DESCRIPTION
The product part NO.(H27UBG8T2A) is a single 3.3V 32Gbit NAND flash memory. The Device contains 2 planes in a single
die. Each plane is made up of the 1024 blocks. Each block consists of 256 programmable pages. Each page contains 8,640
bytes. The pages are subdivided into an 8192-bytes main data storage area with a spare 448-byte district.
Page program operation can be performed in typical 1,600us, and a single block can be erased in typical 2.5ms. On-chip
control logic unit automates erase and program operations to maximize cycle endurance. E/W endurance is stipulated at
3,000 cycles when using relevant ECC and Error management.
The H27UBG8T2A is a best solution for applications requiring large nonvolatile storage memory.
1.1. Product List
Table 1
PART NUMBER ORGANIZATION Vcc RANGE PACKAGE
H27UBG8T2A X8 2.7V ~ 3.6V
48 - TSOP1
52 - LGA
Rev 0.6 / Dec. 2009 5
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
NC
NC
NC
NC
NC
NC
R/B
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
12
13
37
36
25
48 1
24
NAND Flash
TSOP1
(x8)
25
48
24
D
A2
DÌE
A1
e
B
L
Į
E1
E
C
&3
A
1.2. Packaging Information

■ Figure 1. 48-TSOP1 Contact, x8 Device
48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol
millimeters
Min Typ Max
A 1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
■ Figure 1-1. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Rev 0.6 / Dec. 2009 6
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
/WE
/WP VSS
IO0
IO1
IO2 IO6
IO7
IO5
IO4 VSS
IO3
R/B
NC
NC
NC
NC
NC
NC VCC
NC
VSS
VSS
VCC
VCC
NC CLE
ALE
/CE
/RE
NC
NC NC
NC
NC
NC
NC
VSS
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
1 2 3 4 5 6 7 0 8
OA
OB
OC
OD
OE
OF
NC
NC
NC
■ Figure 2. 52-VLGA Contact, x8 Device
Rev 0.6 / Dec. 2009 7
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
52-VLGA, 14 x 18mm, Package Mechanical Data
Symbol
millimeters
Min Typ Max
A 17.90 18.00 18.10
A1 13.00
A2 12.00
B 13.90 14.00 14.10
B1 10.00
B2 6.00
C 1.00
C1 1.50
C2 2.00
D 1.00
D1 1.00
E 0.80 0.90 1.00
CP1 0.65 0.70 0.75
CP2 0.95 1.00 1.05
B
A A1 A2
cp1
E
cp2
C2
C
C1
B1
B2
D D1
0.1 M C AB
0.1 M C AB
■ Figure 2-1. 52-VLGA, 14 x 18mm, Package Outline (Top view through package)
Rev 0.6 / Dec. 2009 8
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
VCC
VSS
WP#
CLE
ALE
RE#
WE#
CE# I/O0~I/O7
R/B#
I/O7~I/O0 Data Input / Outputs
CLE Command Latch Enable
ALE Address Latch Enable
CE# Chip Enable
RE# Read Enable
R/B# Ready / Busy
WE# Write Enable
WP# Write Protect
VCC Power Supply
VSS Ground
NC No Connection
Pin Diagram
■ Figure 3. Pin Diagram
Pin Names
Rev 0.6 / Dec. 2009 9
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.3. PIN DESCRIPTION
Notes:
A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
Pin Name Description
I/O0-I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during read / write
operations. The I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE
COMMAND LATCH ENABLE
This input activates the latching of the I/O inputs inside the Command Register on the Rising edge of Write Enable
(WE#).
ALE
ADDRESS LATCH ENABLE
This input activates the latching of the I/O inputs inside the Address Register on the Rising edge of Write Enable (WE#).
CE#
CHIP ENABLE
This input controls the selection of the device. When the device is busy, CE# low does not deselect the memory. The
device goes into Stand-by mode when CE# goes High during 10us in Ready state. The CE# signal is ignored when
device is in Busy state, and will not enter Standby mode even if the CE# goes high.
WE#
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on the rise edge of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after
the falling edge of RE# which also increments the internal column address counter by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides a hardware protection against undesired write operations. Hardware Write Protection
is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the
memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power
up phases.
R/B#
READY / BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Vcc
SUPPLY VOLTAGE
The VCC supplies the power for all the operations. (Read, Write, and Erase).
Vss GROUND
NC NO CONNECTED
Rev 0.6 / Dec. 2009 10
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
X Decoder
Address
register
ALE
CLE
CE#
WE#
RE#
WP#
Command
Interface Logic
Program/Erase
Controller
HV generation
Y Decoder
Address
register
Command
register
IO Buffer & latch
X
D
E
C
O
D
E
R
NAND FLASH
Memory Array
1 Device =
(8,192 + 448) bytes x 256pages x 2048 blocks
= 36,238,786 kbits
Data Register & Sense Amp
Column Decoder
Vcc
Vss
Global data
buffer
Output Driver
A14-A32
A0-A13
I/O<7:0>
1.4. Block Diagram
■ Figure 4. Block diagram
Rev 0.6 / Dec. 2009 11
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.5. Array Organization
■ Figure 5. Array organization
1.6. Addressing
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22), and
block address (A23 ~ the last address).
Bus cycle I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
1
st
Cycle
A0 A1 A2 A3 A4 A5 A6 A7
2
nd
Cycle
A8 A9 A10 A11 A12 A13
L
(1)
L
(1)
3
rd
Cycle
A14 A15 A16 A17 A18 A19 A20 A21
4
th
Cycle
A22 A23 A24 A25 A26 A27 A28 A29
5
th
Cycle
A30 A31 A32
L
(1)
L
(1)
L
(1)
L
(1)
L
(1)
Rev 0.6 / Dec. 2009 12
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.7. Command Set
FUNCTION
1
st
Cycle
Number of
Address
cycles
Data
input
cycles
2
nd
Cycle
Number
of
Address
cycles
Data
input
cycles
3
rd
Cycle
Acceptable
command
during busy
PAGE READ 00h 5 - 30h - - - No
READ FOR COPY-BACK 00h 5 - 35h - - - No
RANDOM DATA OUTPUT
1)
05h 2 - E0h - - - No
SINGLE/multi plane CACHE READ
5)
31h - - - - - - No
SINGLE/multi plane CACHE READ END
5)
3Fh - - - - - - No
READ ID 90h 1 - - - - - No
READ STATUS REGISTER 70h - - - - - - Yes
PAGE PGM (start) / CACHE PGM
5)
(end)
80h 5 Yes 10h - - - No
RANDOM DATA INPUT
1)
85h 2 Yes - - - - No
COPY-BACK PGM 85h 5 option 10h - - - No
CACHE PGM (start)
5)
80h 5 Yes 15h - - - No
BLOCK ERASE 60h 3 - D0h - - - No
RESET FFh - - - - - Yes
multi plane PAGE READ 60h 3 - 60h 3 - 30h No
multi plane CACHE READ START
5)
60h 3 - 60h 3 - 30h/33h No
multi plane READ FOR COPY-BACK 60h 3 - 60h 3 - 35h No
multi plane BLOCK ERASE 60h 3 - 60h 3 - D0h No
multi plane DATA OUTPUT
1) 3)
00h 5 - 05h 2 - E0h No
multi plane READ STATUS REGISTER 78h 3 - - - - - Yes
multi plane PAGE PGM
/ multi plane CACHE PGM (end)
80h 5 Yes
11h~81h
2)
5 Yes 10h No
multi plane COPY-BACK PGM 85h 5 option
11h~81h
2)
5 option 10h No
multi plane CACHE PGM (start)
5)
80h 5 Yes
11h~81h
2)
5 Yes 15h No
Rev 0.6 / Dec. 2009 13
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Notes:
1. Random Data Input/Output must be performed in a selected page.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
3. Multi Plane Random data-out must be used after Multi Plane read operations (Multi Plane Page Read, Multi Plane
Cache Read and Multi Plane Read for Copy Back).
4. Do not change Plane address order when using all Multi Plane operations.
5. All cache operation (cache program, cache read) is available only within a block.
6. Interleave operation between two chips are allowed. Multi Plane Read Status (78h) can be used to check each chip
status. It is prohibited to use Read Status command (70h) in interleaved operation.
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi Plane page read, Multi Plane cache read, and Multi Plane read for copy-back must be used after Multi Plane
pro grammed page, Multi Plane cache program, and Multi Plane copy-back program.
1.8. Mode Selection
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to
avert unintended data out. In this time, only Reset, Read Status, and Multi Plane Read Status can be inputted to
the device.
CLE ALE CE# WE# RE# WP# MODE
H L L H X
Read Mode
Command Input
L H L H X Address Input ( 5 Cycles )
H L L H H
Write Mode
Command Input
L
H
1)
L H H Address Input ( 5 Cycles )
L L L H H Data Input
L
L
1)
L H X Sequential Read and Data Output
X X X
H
3)
H
3)
X During Read (Busy)
X
X
1)
X X X H During Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
X X H X X
OV/Vcc
2)
Stand-By
Rev 0.6 / Dec. 2009 14
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Start
Block No = 0
Read FFh
check column 8192
of the first page
Last Block
End
Entry Bad Block
Fail
Fail
Pass
Yes
Block No. = Block No. + 1
Pass
No
Read FFh
check col. 8192
of the last page
1.9. Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of either the 1st or
the last page does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted
as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original
information it is recommended to create a Bad Block table following the flowchart shown in Flow chart 1. The 1st block,
which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
■ Flow chart 1. Bad block management flow chart
Notes:
1. Do not try to erase the detected bad blocks, because the bad block information will be lost.
2. Do not perform program and erase operation in invalid block, it is impossible to guarantee the input data
and to ensure that the function is normal.
Rev 0.6 / Dec. 2009 15
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Block A Block B
Data Data
Failure
FFh FFh
Buffer memory
Controller
1 Page
st
1 Page
st
Nth Page Nth Page
(2)
(3)
1.10. Bad Block Replacement
This device may have the invalid blocks when shipped from factory. An invalid block is one that contains one or more bad
bits. Over the lifetime of the device additional Bad Blocks may develop. In this case, the block has to be replaced by
copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them
will give errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block. Bad block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer
to Table 2 and Figure 6 for the recommended procedure to follow if an error occurs during an operation.
Table 2. Block failure
■ Figure 6. Block replacement
Notes:
1. An error occurs on nth page of the Block A during Program or Erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth page of block A which is in controller buffer memory is copied into nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement
Read ECC
Rev 0.6 / Dec. 2009 16
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2. Electrical Characteristics
2.1. Valid Blocks
Notes:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
2. This single device has a maximum of 50 invalid blocks.
3. Invalid blocks are one that contains one or more bad bits. The device may contain bad blocks upon shipment.
2.2. Absolute Maximum Rating
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute
Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or any other conditions above those indicated in the Operating sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may
affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Symbol Min Typ Max Unit
Valid Block
Number
N
VB
1998 2048 Blocks
Symbol Parameter
Value
Unit
Min
T
A
Ambient Operating Temperature
(Commercial Temperature Range)
0 to 70 °C
Ambient Operating Temperature
(Extended Temperature Range)
-25 to 85 °C
Ambient Operating Temperature
(Industrial Temperature Range)
-40 to 85 °C
T
BIAS
Temperature Under Bias -50 to 125 °C
T
STG
Storage Temperature -65 to 150 °C
V
IO
Input or Output Voltage -0.6 to 4.6 V
V
CC
Supply Voltage -0.6 to 4.6 V
Rev 0.6 / Dec. 2009 17
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.3. DC and Operating Characteristics
Parameter Symbol
Test
Conditions
HY27UCG8T2A
Unit 3.3V
Min Typ Max
Power on reset current I
CC0
FFh command input
after power on
- -
50per
device

Operating
Current
Read I
CC1
t
RC
= t
RC
(min),
CE#=V
IL
,
I
OUT
=0 ㎃
- - 50

Program I
CC2
- - - 50

Erase I
CC3
- - - 50

Stand-by Current (TTL) I
CC4
CE#=V
IH
, WP#=0V/
V
CC
- - 1

Stand-by Current (CMOS) I
CC5
CE#=VCC-0.2,
WP#=0V/V
CC
- 10 50

Input Leakage Current I
LI
V
IN
=0 to V
CC
(MAX) - - ± 10 ㎂
Output Leakage Current I
LO
V
OUT
=0 to V
CC(MAX)
- - ± 10 ㎂
Input High Voltage V
IH
- Vccx0.8 - Vcc+0.3 V
Input Low Voltage V
IL
- -0.3 - 0.2x Vcc V
Output High Voltage V
OH
I
OH
=-200 ㎂ 2.4 - - V
Output Low Voltage V
OL
I
OL
=2.1 ㎃ - - 0.4 V
Output Low Current (R/B#) I
OL
(R/B#) V
OL
=0.4V 8 10 -

Rev 0.6 / Dec. 2009 18
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.4. AC Test Conditions
Notes:
1.These parameters are verified device characterization and are not 100% tested.
2.5. Pin Capacitance (T
A
=25°C, F=1.0㎒)
2.6. Program/ Read / Erase Characteristics
Notes:
1. Typical value is measured at V
CC
=3.3V, T
A
=25℃. Not 100% tested.
Parameter
Value
2.7V ≤ Vcc ≤ 3.6V
Input Pulse Levels 0 V to V
CC
Input Rise and Fall Times 5 ㎱
Input and Output Timing Levels Vcc /2
Output Load (2.7V-3.6V) 1 TTL GATE and CL=50㎊
Symbol Parameter
Test
Condition
Min Max Unit
C
IN
Input Capacitance V
IN =
0V - 10

C
I/O
Input/Output Capacitance V
IN =
0V - 10

Parameter Symbol Min Typ Max Unit
Program (following 10h) t
PROG
- 1600 5000

Cache Program (following 15h) t
CBSYW
- - 5000

multi plane Program / multi plane Cache
Program / multi plane Copy-Back Program
(following 11h)
t
DBSY
- 3 5 ㎲
Cache Read / multi plane Cache Read
(following 31h/3Fh)
t
CBSYR
- 3 200

Block Erase / multi plane Block Erase t
BERS
- 2.5 10

Number of partial Program Cycles in the
same page
NOP - - 1 cycles
Rev 0.6 / Dec. 2009 19
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.7. AC Timing Characteristics
Parameter Symbol
3.3V
Unit
Min Max
CLE setup time t
CLS
12

CLE Hold time t
CLH
5

CE# setup time t
CS
20

CE# hold time t
CH
5

WE# pulse width t
WP
12

ALE setup time t
ALS
12

ALE hold time t
ALH
5

Data setup time t
DS
12

Data hold time t
DH
5

Write cycle time t
WC
25

WE# high hold time t
WH
10

Data transfer from cell to register t
R
200

ALE to RE# delay t
AR
10

CLE to RE# delay t
CLR
10

Ready to RE# low t
RR
25

RE# pulse width t
RP
12

WE# high to busy t
WB
100

Read cycle time t
RC
25

RE# access time t
REA
20

RE# high to output high Z t
RHZ
100

CE# high to output high Z t
CHZ
50

RE# high to output hold t
RHOH
15

RE# low to output hold t
RLOH
5

RE# or CE# high to output hold t
COH
15

RE# high hold time t
REH
10

CE# low to RE# low t
CR
10

WE# high to RE# low t
WHR
80

Rev 0.6 / Dec. 2009 20
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Notes:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. Program / Erase Enable Operation: WP# high to WE# High.
Program / Erase Disable Operation: WP# Low to WE# High.
3. The transition of the corresponding control pins must occur only while WE# is held low.
4. t
ADL
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
RE# high to WE# low t
RHW
100

Output high Z to RE# low t
IR
0

Address to data loading time t
ADL
100

Device resetting time
(Read/Program/Erase)
t
RST
20/30/500

Write protection time t
WW
100

Rev 0.6 / Dec. 2009 21
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.8. Status Register Coding
Notes:
1. I/O0: This bit is only valid for Program and Erase operations. During Cache Program operations,
this bit is only valid when I/O5 is set to one.
2. I/O1: This bit is only valid for cache program operations. This bit is not valid until after the
second 15h command or the 10h command has been transferred in a Cache program sequence.
When Cache program is not supported, this bit is not used.
3. I/O5: If set to one, then there is no array operation in progress. If cleared to zero, then there is a
command being processed (I/O6 is cleared to zero) or an array operation in progress. When
overlapped interleaved operations or cache commands are not supported, this bit is not used.
4. I/O6: If set to one, then the device or interleaved address is ready for another command and
all other bits in the status value are valid. If cleared to zero, then the last command issued
is not yet complete and Status Register bits<5:0> are invalid value. When cache operations
are in use, then this bit indicates whether another command can be accepted, and I/O5
indicates whether the last operation is complete.
I/O
Page
Program
Block
Erase
Read
Cache
Read
Cache
Program
Coding
70h/ 78h
0 Pass/ Fail Pass/ Fail N/A N/A Pass/ Fail
N page
Pass : '0' Fail : '1'
1 N/A N/A N/A N/A Pass/ Fail
N-1 page
Pass : '0' Fail : '1'
2 N/A N/A N/A N/A N/A '0'
3 N/A N/A N/A N/A N/A '0'
4 N/A N/A N/A N/A N/A '0'
5 N/A N/A N/A Ready / Busy Ready / Busy
Ready / Busy
Busy : '0' Ready : '1'
6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy
Data Cache Ready /
Busy : '0' Ready : '1'
7 Write Protect Write Protect Write Protect Write Protect Write Protect
Protected : '0'
Not Protected : '1'
Rev 0.6 / Dec. 2009 22
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.9. Device Identifier Coding
2.10. Read ID Data Table
2.10.1. 3
rd
Byte of Device Identifier Description
Parameter Symbol
Device Identifier Byte Description
1
st
Manufacturer Code
2
nd
Device Identifier
3
rd
Internal chip number, cell Type, Number of Simultaneously
Programmed Pages, Interleaved Program, Write Cache.
4
th
Page size, Block size, Redundant area size
5
th
Plane Number, ECC Level
6
th
Technology (Design Rule), EDO, Interface
Part Number Voltage
Bus
Width
Manufacture
Code
Device
Code
3
rd
4
th
5
th
6
th
H27UBG8T2A 3.3V X8 ADh D7h 94h 9Ah 74h 42h
3
rd
cycle
Description
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Internal Chip Number
1
2
4
Reserved
0
0
1
1
0
1
0
1
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
Number of Simultaneously
Programmed Pages
1
2
4
8
0
0
1
1
0
1
0
1
Interleaved Program
between Multiple dice
Supported
Not Supported
0
1
Write Cache
Not Supported
Supported
0
1
Rev 0.6 / Dec. 2009 23
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.10.2. 4
th
Byte of Device Identifier Description
2.10.3. 5
th
Byte of Device Identifier Description
4
th
cycle
Description
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Page Size
(Without Spare Area)
2KB
4KB
8KB
Reserved
0
0
1
1
0
1
0
1
Block Size
(Without Spare area)
128KB
256KB
512KB
768KB
1MB
2MB
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size
128B
224B
448B
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
th
cycle
Description
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Plane Number
1
2
4
8
0
0
1
1
0
1
0
1
ECC Level
1bit/512Bytes
2bit/512Bytes
4bit/512Bytes
8bit/512Bytes
16bit/512Bytes
24bit/2048Bytes
24bit/1024Bytes
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved 0 0 0
Rev 0.6 / Dec. 2009 24
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.10.4. 6
th
Byte of Device Identifier Description
6
th
cycle
Description
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
NAND Technology
48nm
41nm
32nm
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EDO Support
Not Support
Support
0
1
NAND Interface
SDR
DDR
0
1
Reserved 0 0 0
Rev 0.6 / Dec. 2009 25
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
CLS
CS
WP
Command
CLE
CE#
WE#
ALE
I/Ox
DH DS
ALS
CLH
CH
: Don’t care
t t
t t
t
t
t t
ALH
t
3. Timing Diagram
Bus Operation
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
3.1. Command Latch Cycle Timings
■ Figure 7. Command latch timings
Note:
All command except Reset, Read Status, and Multi Plane Read Status is issued to command register on the rising edge
of WE#, when CLE is high, CE# and ALE is low, and device is not busy state
Rev 0.6 / Dec. 2009 26
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
WC
CLH
CH
WP
WH
DIN 1 DIN final
DH
DH
DH DS DS DS
WP
WP
CLE
ALE
CE#
I/Ox
WE#
ALS
DIN 0
t
t
t
t
t
t t
t
t
t
t
t
t
t
: Don’t care
tCLS
tCS
tWC
tALS tALS tALS tALS tALS tALH tALH tALH tALH tALH
tWC tWC tWC
tWP tWP
tWH
tWP tWP
tWH tWH tWH
tDS
Col.Add1
CLE
CE
WE
ALE
I/Ox Col.Add2 Row Add1 Row Add2 Row Add3
tDS
tDS tDS tDS
tDH tDH tDH tDH tDH
: Don’t care
3.2. Address Latch Cycle Timings
■ Figure 8. Address latch timings
3.3. Input Data Latch Cycle Timings
■ Figure 9. Input data cycle timings
Note:
Data Input cycle is accepted to data register on the rising edge of WE#, when CLE and CE# and ALE are low,
and device is not Busy state.
Rev 0.6 / Dec. 2009 27
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
RR
CHZ
RHZ
RHOH
Dout
CE#
RE#
I/Ox
R/B#
REA
Dout
RLOH
REA
RP REH
RC
t
t t
t
t
t
t
t
t
t
: Don’t care
CR
t
REH
REA
RC
RR
CHZ
RHZ
RHOH
Dout Dout
CE#
RE#
I/Ox
R/B#
Dout
REA
RHZ
REA
t
t
t
t
t
t
t
t
t
t
3.4. Data Output Cycle Timings (CLE=L, WE#=H, ALE=L, WP#=H)
■ Figure 10. Data output cycle timings
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( t
CHZ
, t
RHZ
)
2. t
RLOH
is valid when frequency is higher than 33MHz.
t
RHOH
starts to be valid when frequency is lower than 33MHz.
3.5. Data Output Cycle Timings (EDO type, CLE=L, WE#=H, ALE=L)
■ Figure 11. Data output cycle timings (EDO)
Notes:
1. Transition is measured +/-200mV from steady state voltage with load.
This parameter is sampled and not 100% tested. ( t
CHZ
, t
RHZ
)
2. t
RLOH
is valid when frequency is higher than 33MHz.
t
RHOH
starts to be valid when frequency is lower than 33MHz.
Rev 0.6 / Dec. 2009 28
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
t
CLS
t
CLH
t
CS
t
WP
t
CH
t
CR
t
CHZ
t
COH
t
WHR
t
ALH
t
AR
t
REA
t
RHZ
t
RHOH
t
DS
t
DH
t
ALH t
ALS
WC
t
WP
t
WH
t
: Don’t care
CLE
CE#
WE#
ALE
RE#
I/Ox 78h
Row.Add1 Row.Add2 Row.Add3 Status
CLE
CE#
RE#
I/Ox
WE#
70h Status output
CLS
t
CLH
t
CS
t
CLR
t
CH
t CR
t
CHZ
t
RHZ
t
RHOH
t
WP
t
WHR
t
DS
t
DH
t
IR
t
REA
t
: Don’t care
3.6. Read Status Cycle Timings
■ Figure 12. Read status timings
3.7. Multi Plane Read Status Timings
■ Figure 13. Multi plane read status timings
Rev 0.6 / Dec. 2009 29
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
CE#
CLE
ALE
WE#
RE#
I/Ox
00h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
30h
Dout
N
Dout
N+1
Dout
N+2
R/B#
t
AR
t
RC
t
R
t
WB
t
RR
t
WC
: Don’t care
t
RHZ
Dout
M
CE#
CLE
ALE
WE#
RE#
I/Ox
00h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
30h
Dout
N
Dout
N+1
Dout
N+2
R/B#
t
AR
t
RC
t
R
t
WB
t
RR
t
WC
: Don’t care
t
CLR
t
CHZ
t
COH
t
CS
t
CH
t
CLS
t
CLH
3.8. Page Read Operation Timings (Read One Page)
■ Figure 14. Page read operation timings
3.9. Page Read Operation Timings (Intercepted by CE#)
■ Figure 15. Page read operation timings
Rev 0.6 / Dec. 2009 30
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.10. Page Read Operation Timings with CE# don't care
■ Figure 16. Page read operation timings with CE# don't care
3.11. Random Data Output Timings
■ Figure 17. Random data output timings
Note:
Random data output is available within a page.
Rev 0.6 / Dec. 2009 31
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.12. Multi Plane Page Read Operation with Random Data output Timings
■ Figure 18. Multi plane page read operation timings with random data output
Notes:
1. Multi Plane Page addresses are required to be the same.
2. Multi Plane Random data-out must be used after multi plane read operations.
3. Multi Plane page read must be used after Multi plane programmed page, Multi Plane cache program,
and Multi Plane copy-back program.
Rev 0.6 / Dec. 2009 32
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.13. Cache Read Operation Timings
■ Figure 19. Cache read operation timings
Notes:
1. The column address will be reset to 0 by the 31h/3Fh command input.
2. Cache read operation is available only within a block.
Rev 0.6 / Dec. 2009 33
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.14. Multi Plane Cache Read Operation Timings
■ Figure 20. Multi plane cache read operation Timings
Notes:
1. The column address will be reset to 0 by the 31h/3Fh command input.
2. Cache read operation is available only within a block.
3. Make sure to terminate the operation with 3Fh command. If the page read operation is completed,
issue FFh reset before next operation.
4. Multi Plane Page addresses are required to be the same.
5. Multi Plane cache read must be used after Multi plane programmed page, multi plane cache program,
and multi plane copy-back program

Rev 0.6 / Dec. 2009 34
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Device
code
3rd
cyc.
4th
cyc.
90h
CE#
CLE
WE#
ALE
RE#
I/Ox 00h
ADh
AR
WHR
REA
5th
cyc.
6th
cyc.
Maker code
t
t
t
3.15. Read ID Operation Timings
■ Figure 21. Read ID operation timings
3.16. Page Program Operation Timings
■ Figure 22. Page program operation timings
Note:
t
ADL
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
Rev 0.6 / Dec. 2009 35
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
00h
85h 85h 11h 10h Data Data
35h

Data Output
Add. (5Cycles)
Add. (5Cycles) Add. (5Cycles)
A0 ~ A12 : Valid
A13 ~ A18 : Fixed ¨Low¨
A19 : Must be same with the source plane
A20 ~ A30 : Fixed ¨Low¨
A0 ~ A12 : Valid
A13 ~ A18 : Valid
A19 : Must be same with the source plane
A20 ~ A30 : Valid
Col. Add 1,2 & Row Add. 1,2,3
Source Address
Col. Add 1,2 & Row Add. 1,2,3 Col. Add 1,2 & Row Add. 1,2,3
up to 2112 Byte Data up to 2112 Byte Data
Destination Address Destination Address

Ì/Ox
R/B
Ì/Ox
R/B
tDBSY
tR
tPROG
3.17. Page Program Operation Timings with CE# don't care
■ Figure 23. Page program operation timings with CE# don't care
Note:
t
ADL
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
3.18. Random Data Input Timings
■ Figure 24. Random data input timings
Notes:
1. t
ADL
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
2. Random data input can be performed in a page.
Rev 0.6 / Dec. 2009 36
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.19. Multi Plane Page Program Operation Timings
■ Figure 25. Multi plane page program operation timing
Notes:
1. Any command between 11h and 81h is prohibited except 70h, 78h and FFh
2. t
ADL
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
3. Multi Plane Page addresses are required to be the same.
Rev 0.6 / Dec. 2009 37
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.20. Copy-Back Program Operation Timings with Random Date Input
■ Figure 26. Copyback program operation timing with random data input
Note:
Copy back operation is allowed only within the same memory plane.
3.21. Cache Program Operation Timings
■ Figure 27. Cache program operation timings
Note:
t
PROG
= Program time for the last page + Program time for the (last -1)th page - (command input cycle
time + address input cycle time + Last page data loading time
Rev 0.6 / Dec. 2009 38
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.22. Multi Plane Cache Program Operation Timings
■ Figure 28. Multi plane cache program operation timings
Notes:
1. t
PROG
= Program time for the last page + Program time for the (last -1)th page - (command input cycle
time + address input cycle time + Last page data loading time)
2. Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated, Issue
FFh reset before next operation.
3. Selected Page address except A22 within two blocks must be same.
Rev 0.6 / Dec. 2009 39
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3.23. Block Erase Operation Timings
■ Figure 29. Block erase operation timings
3.24. Multi Plane Erase Operation Timings
■ Figure 30. Multi plane erase operation timings
Rev 0.6 / Dec. 2009 40
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
FFh
t
RST
CE#
CLE
WE#
I/Ox
R/B#
t
WB
3.25. Reset Timings
■ Figure 31. Reset timings
Rev 0.6 / Dec. 2009 41
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
CLE
ALE
CE#
I/Ox
WE#
R/B#
RE#
00h Address (5 cycle) 30h Data Output (Serial Access)
t
R
4. DEVICE OPERATION
4.1. Page Read
This operation is initialized by 00h-30h to the command register along with followed by five address input cycles. The
8,640 bytes of data within the selected page are transferred to the data registers in less than 200㎲(t
R
). The system
controller may detect the completion of this data transfer 200㎲(t
R
) by analyzing the output of R/B# pin. Once the
data in a page is loaded into the data registers, they may be read out in 25㎱ cycle time by sequentially pulsing RE#.
The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected col-
umn address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command. The column address of next data, which is going to be out, may be changed to the address, which fol-
lows random data output command. Random data output can be operated multiple times, regardless of how many
times it is done in a page.
■ Figure 32. Page read
Random data output
Random data output operation changes the column address from which data is being read in the page register. Ran-
dom data output only is issued in Ready state. Refer to Figure 33.
Rev 0.6 / Dec. 2009 42
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
I/Ox
R/B#
RE#
00h Data
t
R
Output
Address
(5 cycle)
30h Data Output 05h
Address
(2 cycle)
E0h
30h 31h D0
...
Dn 31h D0
...
Dn 3Fh D0
...
Dn
CLE
WE#
RE#
I/Ox
R/B#
As defined for Read
t
R
t
CBSYR
Column 0
t
CBSYR
Column 0
t
CBSYR
Column 0
■ Figure 33. Random data output
4.2. Cache Read (available only within a block)
To improve page read throughput, cache read operation is used within a block. First step is same as normal page read,
issuing a page read sequence (00-30h). After random access (R/B# returns to high), 31h command is latched into the com-
mand register. Data is being transferred from the data register to the cache register. While cache register data is outputted,
next page is transferred from memory cell to data register. R/B# will stay low during present page random accessing and
previous page transferring to cache register. Because it is not necessary to output a whole page data before issuing another
31h command, if serial data output time exceeds random access time (t
R
), the random access time can be hidden. The sub-
sequent pages are issued additional 31h commands. To terminate cache read, 3Fh command should be issued. This com-
mand transfer data from data register to the cache register without issuing next page read. During the Cache Read
Operation, device doesn't allow any other command except Cache Read command (31h), Read Status (70h, 78h), Read
(00h), and Reset (FFh). To carry out other operations after cache operation, cache read must be ended by 3Fh command
or issue reset (FFh) before next operation.
■ Figure 34. Cache read
Rev 0.6 / Dec. 2009 43
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
60h
t
R
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
Block address : Block J Column address : Valid
Address
(3 Cycle)
60h 30h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K Column address : Valid
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
4.3. Multi Plane Page Read
Multi plane Page Read is an extension of Page Read, for a single plane with 8640byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 8640byte page resisters enables a random read of two
pages. Multi plane Page Read is initiated by repeating command 60h followed by three address cycles twice. In this case,
only same page can be selected from each plane.
After Read Confirm command (30h) the 17280bytes of data within the selected two pages are transferred to the data
registers in less than 200㎲ (t
R
). The system controller can detect the completion of data transfer (t
R
) by monitoring the
output of R/B# pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h
with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can
be read out using the identical command sequences. The restrictions for multi plane Page Read are shown in Figure 35.
multi plane Page Read must be used in the block which has been programmed with Multi plane Page Program.
■ Figure 35. Multi plane page read
4.4. Multi Plane Cache Read (available only within a block)
The device supports multi plane cache read, which enables high read throughput by reading two pages in
parallel. Figure 36 shows the command sequence for the multi plane cache read operation. Both confirm commands, 30h
and 33h, are valid for the first page read sequence.
Rev 0.6 / Dec. 2009 44
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
60h
t
R
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Valid
Address
(3 Cycle)
60h 33h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
t
CBSYR
I/Ox
R/B#
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “High”
Block address : Block K Column address : Valid
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h
E0h Data output
31h
■ Figure 36. Multi plane cache read
Notes:
1. Plane 0 and plane 1 should be selected within the same chip
2. Only one block should be selected from the each Plane.
3. Multi Plane cache read is available only within a block per plane.
4. Selected Page address except for A22 within two blocks must be same.
5. The operation has to be terminated with "3Fh" command.
4.5. Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad-
dress input of 00h. Six read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd, 4th,
5th, 6th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 37 shows the operation sequence, while 2.10 READ ID data tables explain the byte meaning.
Rev 0.6 / Dec. 2009 45
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
CLE
ALE
WE#
RE#
I/Ox
78h Row.Add1 Row.Add3 Row.Add2
Status
90h
CLE
WE#
ALE
RE#
I/Ox
00h
ADh D7h 74h 42h 9Ah
WHR
94h
t
70h Status
CLE
WE#
RE#
I/Ox
■ Figure 37. Read ID
4.6. Read Status Register
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing Read Status (70h) or Multi
Plane Read Status (78h) command to the command register, a read cycle outputs the content of the Status Register to
the I/O pins only if CE# and RE# are low, whichever occurs last. This two line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to 2.8. STATUS
REGISTER CODINGS for specific Status Register definitions and Figure 38, Figure 39 for Read Status. The command reg-
ister remains in Read Status mode until further commands are issued to it. Therefore, if the status register is read during
a random read cycle, the read command (00h) should be given before starting read cycles.
■ Figure 38. Read status
■ Figure 39. Multi plane read status
Rev 0.6 / Dec. 2009 46
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
80h Address 5 cycle Data Input Status 70h 10h
CLE
PROG
t
I/O 0 = 0 PROGRAM Pass
I/O 0 = 1 PROGRAM Fail
CE#
ALE
WE#
RE#
I/Ox
R/B#
4.7. Page Program
The device is programmed as a page unit. The number of consecutive partial page programming operation within the
same page without an intervening erase operation must not exceed 1 times. The program addressing should be done in
sequential order in a block. A page program cycle consists of a serial data loading period in which up to 8640bytes of data
may be loaded into the data register, followed by a non-volatile programming period where the loaded data is pro-
grammed into the appropriate cell. The serial data-loading period begins by inputting the Serial Data Input command
(80h), followed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do
not need to be loaded. The device supports random data input in a page. The column address of next data, which will be
entered, may be changed to the address which follows random data input command (85h). Random data input may be
operated multiple times, regardless of how many times it is done in a page. The Page Program Confirm command (10h)
initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state controller automatically executes the algorithms and timings necessary for
program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read
Status Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. The Write Status Bit (I/O 0) is valid, when all internal operations are complete (status bit I/O 6 = high).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the command
register. Figure 40 and Figure 41 details the sequence.
■ Figure 40. Page Program
Rev 0.6 / Dec. 2009 47
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
80h Address (5 cycle) 11h
t
DBSY
Data Input
A
81h Address (5 cycle) 10h
t
PROG
Data Input
I/Ox
R/B#
70h Status
1 plane address
st
2 plane address
nd
A
I/Ox
R/B#
I/Ox
R/B#
Column address
80h
Address
(5 Cycle)
Address
(2 Cycle)
Data
Input
85h
Data
Input
70h Status
10h
PROG
t
■ Figure 41. Random data input
4.8. Multi Plane Program
Device supports multiple plane program. It is possible to program in parallel 2 pages, one per each plane.
A multiple plane program cycle consists of a double serial data loading period in which up to 17,280bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the
five cycle address inputs and then serial data for the 1st page. Address for this page must be within first plane (A<22>=0).
The data of first page other than those to be programmed do not need to be loaded. The device supports random data input
exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the
device becomes busy for a short time (t
DBSY
). Once it has become ready again, 81h command must be issued, followed by
second page address (5 cycles) and its serial data input. Address for this page must be within second plane (A<22>=1). The
data of second page other than those to be programmed do not need to be loaded. Program Confirm command (10h) makes
parallel programming of both pages start. User can check operation status by R/B# pin or read status register command, as
if it were a normal page program; status register command is also available during Dummy Busy time (t
DBSY
). In case of fail
in first plane or second plane page program, fail bit of status register will be set: Pass/Fail status of each plane can be checked
by Multi Plane Read Status. Figure 42 details the sequence.
■ Figure 42. Multi plane page program
Notes:
1. Plane 0 and Plane 1 should be selected within the same chip
2. Only one block should be selected from the each Plane.
3. Selected Page address except for A22 within two blocks must be same.
4. Any command between 11h and 81h is prohibited except 70h/78h and FFh.
5. Read Status command can be 70h or 78h.
Rev 0.6 / Dec. 2009 48
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
4.9. Cache Program (available only within a block)
Cache Program is an extension of the standard page program, which is executed with 8,640 bytes cache registers and
same bytes data register. After the serial data input command (80h) is loaded to the command register, followed by 5
cycles of address, a full or partial page of data is latched into the cache register, and then the cache write command
(15h) is loaded to the command register. After that sequence, the data in the cache register is transferred into the data
register for cell programming. At this time, the device remains in busy state. After all data of the cache register is trans-
ferred into the data register, the device goes to the Ready state to load the next data into the cache register by issuing
another cache program command sequence (80h-15h).
There are some restrictions for cache program operation.
1. The cache program command is available only within a block.
2. User must give address and data after 80h command.
The Busy time of first sequence equals the time it takes to transfer the data of cache register to the data register. Cell
programming of the data of data register and loading of the next data into the cache register is consequently processed
as a pipeline method. On the second and cascading sequence, transfer from the cache register to the data register is
held off until cell programming of current data register contents has been done.
Read Status command (70h) may be issued to find out when the cache register is ready by polling the Cache-Busy sta-
tus bit (I/O 6). In addition, the status bit (I/O 5) can be used to determine when the cell programming of the current
data register contents is complete. Pass/fail status of only the previous page (I/O 1) is available upon the return to
Ready state.
The last page of the target programming sequence must be programmed with actual “Page Program” command (10h).
If single plane cache program begins, single plane sequence should be used until single plane cache program is ended.
Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit
changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming)
or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked. Refer to 2.8. Status Register
Coding and Figure 43 for more details.
Rev 0.6 / Dec. 2009 49
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
80h Address (5 cycle) 15h
t
CBSYW
Data Input
A
80h Address (5 cycle) 15h
t
CBSYW
Data Input
B
I/Ox
R/B#
80h Address (5 cycle) 10h
t
PROG
Data Input I/Ox
R/B#
70h Status
A
B
I/Ox
R/B#
R/B# Pin
Data Cache Ready /Bysy
(I/O6)
I/O 1 =>
I/O 0 =>
Invalid
Invalid
Page1
Invalid
Page1
Page2
Page N-2
Invalid
Invalid
Invalid
Page N-1
Page N
Data Cache Ready /Bysy
(I/O5)
70h
SR
OUT
70h
SR
OUT
80h-add-data-15h 80h-add-data-15h 70h
SR
OUT
80h-add-data-15h 70h
SR
OUT
80h-add-data-15h 70h
SR
OUT
70h
SR
OUT
Page 1 Page 2 Page N-1 Page N
Page 1 Page 2
Page N-1 Page N
During both I/O6 and I/O5 return to high, the Pass/Fail for previous page and current page
can be shown through I/O1 and I/O0 concurrently.
PROG
t CBSYW
t
CBSYW
t
CBSYW
t
Pass / Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation.
I/O 0 : Pass / Fail of the current page program operation.
I/O 1 : Pass / Fail of the previous page program operation.
The Pass / Fail status on I/O 0 and I/O 1 are valid under the following conditions.
Status on I/O 0 : Ready / Busy is Ready state.
The Ready/ Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
Status on I/O 1 : Data Cache Ready / Busy is Ready State.
The Data Cache Ready / Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.
■ Figure 43. Cache program
Rev 0.6 / Dec. 2009 50
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
4.10. Multi Plane Cache Program (available only within a block)
The device supports multi plane cache program, which enables high program throughput by programming two pages.
The serial data-loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data for the first page. Address for this page must be within first plane (A<22>=0). The
data of first page other than those to be programmed do not need to be loaded. The device supports random data
input exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data
input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be
issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within second
plane (A<22>=1). The data of second page other than those to be programmed do not need to be loaded. Cache
Program Confirm command (15h) makes parallel programming of both pages start. And last page inputs Program
confirm command (10h). the last page of the target programming sequence must be programmed with actual Page
Program command (10h). If the operation is terminated, Issue FFh reset before next operation. If multiplane
cache program begins, multiplane sequence should be used until multiplane cache program is ended.
Figure 44 shows the command sequence for Multi Plane Cache Program operation. After the "15h"or"10h"
command, the result per plane of the operation is shown through the "78h" Multi Plane Read Status command.
■ Figure 44. Multi plane cache program
Notes:
1. Plane 0 and Plane 1 should be selected within the same chip
2. Only one block should be selected from the each Plane.
3. Multi Plane cache program is available only within a block per Plane.
4. Selected Page address except for A22 within two blocks must be same.
5. The operation has to be terminated with “10h” command.”
6. Any command between 11h and 81h is prohibited except 70h/78h and FFh.
7. Read Status command can be 70h or 78h. Reading the Status per Plane is available only 78h.
80h
t
CBSYW
A
80h 81h
I/Ox
R/B#
A
Address
(5 Cycle)
Data
Input
11h
Address
(5 Cycle)
Data
Input
11h 81h
Address
(5 Cycle)
Data
Input
15h
t
DBSY
Address
(5 Cycle)
Data
Input
10h 78h
Address
(3 Cycle)
Status
per plane
Column address : Valid
Page address : Page M
Plane address : Fixed ‘Low’
Block address : block J
Column address : Valid
Page address : Page M
Plane address : Fixed ‘High’
Block address : block K
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘Low’
Block address : block J
Column address : Valid
Page address : Page M+n
Plane address : Fixed ‘High’
Block address : block K
I/Ox
R/B#
t
PROG
t
DBSY
Rev 0.6 / Dec. 2009 51
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
4.11. Copy-Back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page
without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated
and the rest of the block needs to be copied to the newly assigned free block. Copy-Back operation is a sequential exe-
cution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with
"35h" command and the address of the source page moves the whole 8,640-byte data into the internal data buffer. A
bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need
to be reloaded. Therefore, Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h)
with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued.
Once the program process starts, the Read Status Register command (70h) may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit
(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit (I/O 0) may be checked.
The command register remains in Read Status command mode until another valid command is written to the com-
mand register. During copy-back program, data modification is possible using random data input command (85h) as
shown in Figure 45.
■ Figure 45. Copyback program
00h
Address
(5 cycle)
35h Data output
t
R
85h
Address
(5 cycle)
Data
t
PROG
I/Ox
R/B#
Target Address
85h
Address
(2 cycle)
Data 10h 70h Status
Column
address 1,2
I/Ox
R/B#
Source Address
A
A
Rev 0.6 / Dec. 2009 52
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
60h
t
R
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘Low’
Block address : Block J Column address 1,2 : Valid
Address
(3 Cycle)
60h 35h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Valid
Page address : Page N
Plane address : Fixed ‘Low’
Block address : Block P Column address 1,2 : Valid
C
85h
Address
(5 Cycle)
Address
(2 Cycle)
Data 11h
I/Ox
R/B#
D Column address 1,2 : Valid
81h
Address
(5 Cycle)
Data 10h
Data 85h
Address
(2 Cycle)
85h Data
t
PROG
I/Ox
R/B#
C
Column address : Fixed “Low
Page address : Page M
Plane address : Fixed ‘High’
Block address : Block K Column address 1,2 : Valid
D
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
Column address : Valid
Page address : Page N
Plane address : Fixed ‘High’
Block address : Block Q
t
DBSY
4.12. Multi Plane Copy-Back Program
Multi plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 8,640 byte page registers.
Since the device is equipped with two memory planes, activating the two sets of 8,640-byte page registers enables a si-
multaneous programming of two pages. Figure 46 and Figure 47 show command sequence for the Multi Plane copy-back
operation. First case, Figure 46, shows random data input of two planes that started right after finishing random data out-
put of previous two planes. Second case, Figure 47, shows the random data input of each plane which started right after
finishing the random data output of each Plane.
■ Figure 46. Multi plane Copyback program
Rev 0.6 / Dec. 2009 53
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
60h
t
R
A
I/Ox
R/B#
A
Address
(3 Cycle)
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “Low”
Block address : Block J Column address 1,2 : Valid
Address
(3 Cycle)
60h 35h
Page address : Page M
Plane address : Fixed “High”
Block address : Block K
B
I/Ox
R/B#
00h
Address
(5 Cycle)
Address
(2 Cycle)
05h E0h Data output
I/Ox
R/B#
B
Column address : Valid
Page address : Page M
Plane address : Fixed “Low”
Block address : Block P Column address 1,2 : Valid
C
85h
Address
(5 Cycle)
Address
(2 Cycle)
Data Data
I/Ox
R/B#
C
Column address : Fixed “Low”
Page address : Page M
Plane address : Fixed “High”
Block address : Block K Column address 1,2 : Valid
D
00h
Address
(5 Cycle)
Address
(2 Cycle)
I/Ox
R/B#
D
Column address : Valid
Page address : Page M
Plane address : Fixed “High”
Block address : Block Q Column address 1,2 : Valid
81h
Address
(5 Cycle)
Data 10h
E0h 05h
Address
(2 Cycle)
85h Data
t
PROG
85h 11h
t
DBSY
Data output
■ Figure 47. Multi plane Copyback program
4.13. Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A22 to A32 is valid while A14 to A21 is ignored. The Erase Confirm command (D0h)
following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by
execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase
verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The system
controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O 6) of the Status
Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase op-
eration is completed, the Write Status Bit (I/O 0) may be checked. Figure 48 details the sequence.
Rev 0.6 / Dec. 2009 54
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
60h 70h
Address
(3 cycle)
D0h Status
t
BERS
I/Ox
R/B#
Row Add 1,2,3
60h 70h
Address
(3 cycle)
60h Status
t
BERS
Address
(3 cycle)
D0h
Page address : Fixed “Low”
Plane address : Fixed “Low”
Block address : Block N
I/Ox
R/B#
Page address : Fixed “Low”
Plane address : Fixed “High”
Block address : Block M
■ Figure 48. Block Erase
4.14. Multi Plane Block Erase.
Multiple plane erase, allows parallel erase of two blocks, one per each memory plane.
Block erase setup command (60h) must be repeated two times, each time followed by first block and second block ad-
dress respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multi plane erase
does not need any Dummy Busy Time between first and second block address insertion. Address limitation required for
Multiple Plane Program applies also to multiple plane erase, as well as operation progress can be checked like for Multiple
Plane Program. Refer to the detail sequence as shown below.
■ Figure 49. Multi plane Block Erase
4.15. Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high. Refer to 2.8.
Status Register Coding for device status after reset operation. If the device is already in reset state, the command reg-
ister will not accept a new reset command. The R/B# pin goes low for t
RST
after the Reset command is written. Refer
to Figure 50.
Rev 0.6 / Dec. 2009 55
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
I/Ox
R/B#
FFh
RST
t
■ Figure 50. Reset
Rev 0.6 / Dec. 2009 56
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Data out 00h Status
Row.
Add3
78h
Row.
Add2
Row.
Add1
00h 30h 00h 30h
Address
(5cycle)
Address
(5cycle)
00h Status
Row.
Add3
78h
Row.
Add2
Row.
Add1
Data out
Chip 2 Chip 1 Chip 1 Chip 1 Chip 2
Chip 2
I/Ox
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
5. INTERLEAVED OPERATION
Interleaving operations improve the system throughput compared to non-interleaving operations. In the stacked device
sharing a common CE# pin, interleaved operation is available. When both chip are ready state, input a command to the
chip #1. And then, while chip #1 is busy state, issue a command to the other chip. When performing interleaved opera-
tions, the operations shall be the same type. The functions that may be used in the interleaved operations are Page Read,
Page Program, Block Erase, Multi Plane Page Read, Multi Plane Page Program, and Multi Plane Block Erase. During inter-
leaved operations, 70h command is prohibited exceptionally. Each chip status can be checked by Multi Plane Read Status
Command (78h). The R/B# pin shows when both chip are Ready or Busy. While either chip is busy, R/B# pin is low. All
chips are Ready state and interleaved operations are complete, R/B# pin goes high. Cache function and Copyback func-
tion are impossible for interleaved operation.
5.1. Interleaved Page Read
Figure 51 shows how to perform interleaved PAGE READ operations. In Figure, the status register is monitored for oper-
ation completion with the Multi plane status read (78h) command. When the host has issued Page Read commands to
multiple die at the same time, the host shall issue Multi plane status read (78h) command before reading data from either
die. This ensures that only the die selected by the 78h command responds to a data output cycle after being put in data
output mode with a 00h command, and thus avoiding bus contention. The host can use 78h commands to read out data
from another die.
■ Figure 51. Interleaved page read
Note:
70h command is prohibited during interleaved operations.
Rev 0.6 / Dec. 2009 57
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
R/B#
(chip 1 internal)
I/Ox
80h
Address
(5cycle)
Data Input 10h 80h
Address
(5cycle)
Data Input 10h
Row
Add.1
Row
Add.2
Row
Add.3
Status 80h
Address
(5cycle)
Data Input 10h
Chip 1
Chip 2 Chip 1 Chip 1
R/B#
(chip 2 internal)
R/B#
(external)
78h
A
00h
Address
(5cycle)
78h
Row
Add.1
Row
Add.2
Row
Add.3
Status 05h
Address
(2cycle)
E0h
Chip 2
05h
Address
(2cycle)
E0h 00h
Address
(5cycle)
Data output
Chip 2. plane 0 Chip 2. plane 0 Chip 2. plane 1
Data output 00h
Address
(5cycle)
05h
Address
(2cycle)
E0h Data output
Chip 1. plane 0 Chip 1. plane 0 Chip 2. plane 1
A
60h 60h 60h 60h 30h 78h
00h 05h E0h
Address
(3cycle)
Address
(5cycle)
30h
Address
(3cycle)
Address
(3cycle)
Row
Add.1
Row
Add.2
Row
Add.3
Status
Address
(5cycle)
Address
(2cycle)
Data output
Chip 1 Chip 1 Chip 2 Chip 2 Chip 1 Chip 1, plane 0 Chip 1, plane 0 Chip 1, plane 0
I/Ox
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
I/Ox
R/B#
(chip 1 internal)
R/B#
(chip 2 internal)
R/B#
(external)
5.2. Interleaved Multi Plane Page Read
Figure 52 shows how to perform interleaved Multi Plane Page Read operations using the Multi plane read status (78h)
command to monitor the status register for operation completion. When the host has issued Multi Plane Page Read
commands to multiple die at the same time, the host shall issue Multi plane read status (78h) command before reading
data from either die. This ensures that only the die selected by the 78h command responds to a data output cycle after
being put in data output mode with a 00h command and 5 address cycles, and thus avoiding bus contention. The in-
terleaved Multi plane page read operation must meet two-plane addressing requirements.
■ Figure 52. Interleaved multi plane page read
Note:
70h command is prohibited during interleaved operations.
5.3. Interleaved Page Program
Figure 53 show how to perform interleaved PROGRAM PAGE operations. RANDOM DATA INPUT (85h) is permitted
during interleaved PROGRAM PAGE operations.
■ Figure 53. Interleaved page program
Note:
70h command is prohibited during interleaved operations.
Rev 0.6 / Dec. 2009 58
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
R/B#
(chip 1 internal)
I/Ox
R/B#
(chip 2 internal)
R/B#
(external)
R/B#
(chip 1 internal)
I/Ox
R/B#
(chip 2 internal)
R/B#
(external)
A
A
Row.
Add.1
Row.
Add.2
Row.
Add.3
78h 80h Status
Address.
(5cycle)
Data Input 11h 81h
Address.
(5cycle)
Data Input 10h
80h
Address.
(5cycle)
Data Input 11h 81h
Address.
(5cycle)
Data Input 10h
80h
Address.
(5cycle)
Data Input 11h 81h
Address.
(5cycle)
Data Input 10h
Chip 1 Chip 1 Chip 2 Chip 2
Chip 1 Chip 1 Chip 1
R/B#
(chip 1 internal)
I/Ox 60h
Chip 1 Chip 2 Chip 1
R/B#
(chip 2 internal)
R/B#
(external)
Address
(3cycle)
D0h 60h
Address
(3cycle)
D0h 60h
Address
(3cycle)
D0h 60h
Address
(3cycle)
D0h
Chip 2
5.4. Interleaved Multi Plane Page Program
Figure 54 shows how to perform interleaved Multi Plane Page Program operations. The interleaved TWO-PLANE PRO-
GRAM PAGE operation must meet two-plane addressing requirements. Random data input (85h) is permitted during in-
terleaved Multi plane page program operation.
■ Figure 54. Interleaved multi plane page program
Note:
70h command is prohibited during interleaved operations.
5.5. Interleaved Block Erase
Figure 55 shows how to perform interleaved Block Erase operation.
■ Figure 55. Interleaved block erase
Note:
70h command is prohibited during interleaved operations.
Rev 0.6 / Dec. 2009 59
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
R/B#
(chip 1 internal)
I/Ox
60h
Chip 1 Chip 1 Chip 2
R/B#
(chip 2 internal)
R/B#
(external)
Address
(3cycle)
60h
Address
(3cycle)
D0h
Chip 2
60h
Address
(3cycle)
60h
Address
(3cycle)
D0h 78h
Row.
Add 1.
60h
Address
(3cycle)
60h
Address
(3cycle)
D0h
Row.
Add 2.
Row.
Add. 3
Status
Chip 1 Chip 1 Chip 1
5.6. Interleaved Multi Plane Block Erase
Figure 56 shows how to perform two types of interleaved Multi Plane Block Erase operations. This operation must meet
two-plane addressing requirements.
■ Figure 56. Interleaved multi plane block erase
Note:
70h command is prohibited during interleaved operations.
Rev 0.6 / Dec. 2009 60
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
3V device = 2.7V
t
CS
FFh
2.7V
1 (max) ms


10
(max)
50
(min)
2
(max)
ms
Vcc ramp
starts
: Don’t care : Undefined
VCC
0V
CE#
WP#
CLE
WE#
ALE
RE#
I/Ox
R/B#
6. OTHER FEATURES
6.1. Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage de-
tector disables all functions whenever V
CC
is below about 2.0V (3.3V device). WP# pin provides hardware protection and is rec-
ommended to be kept at VIL during power-up and power-down.
The reset command (FFh) must be issued to all dies as the first command after device is power up. Each R/B# will be busy for
maximum of 2ms after reset command is issued. In this time, the acceptable command is 70h or 78h.
■ Figure 57. Data protection and power on / off
Rev 0.6 / Dec. 2009 61
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Rp value guidence
Rp (min) = =
where IL is the sum of the input current of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr
@ Vcc = 3.3V, Ta = 25°C, CL=50pF
Fig. Rp vs tr, tf & Rp vs ibusy
Vcc (Max.) - VOL (Max.) 3.2V
P$™,L IOL + ™,L
Rp
ibusy
Rp (ohm)
ibusy
i
b
u
s
y

[
A
]

t
r
,

t
f


[
s
]

tf
3.3 381
290
1.65
96
189
1.1
0.825
4.2 4.2 4.2 4.2
Busy
Ready Vcc
VOH
tr tf
VOL
VOL : 0.4V, VOH : 2.4V
Vcc
300n 3m
1k 2k 3k 4k
200n 2m
100n 1m
GND
Device
open drain output
R/B#
6.2. Ready / Busy
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back and
random read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program,
and erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver
thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is related to tR (R/B#) and current drain
during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Figure 58). Its value can be de-
termined by the following guidance.
■ Figure 58. Ready / Busy
Rev 0.6 / Dec. 2009 62
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
80h 10h
WE#
I/Ox
WP#
R/B#
WW
t
80h 10h
WE#
I/Ox
WP#
R/B#
WW
t
60h D0h
WE#
I/Ox
WP#
R/B#
WW
t
60h D0h
WE#
I/Ox
WP#
R/B#
WW
t
6.3. Write Protect Operation
The Erase and Program Operations are automatically reset when WP# goes Low (tWW = 100ns, min). The operations are
enabled and disabled as follows (Figure 59 ~ 62).
Figure 59. Enable Programming
Figure 62. Disable Erasing
Figure 60. Disable Programming
Figure 61. Enable Erasing
Rev 0.6 / Dec. 2009 63
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
7. Application Notes and Comments
7.1. Paired Page Address Information
Paired page address Paired page address
0 4 1 5
2 8 3 9
6 C 7 D
A 10 B 11
E 14 F 15
12 18 13 19
16 1C 17 1D
1A 20 1B 21
1E 24 1F 25
22 28 23 29
26 2C 27 2D
2A 30 2B 31
2E 34 2F 35
32 38 33 39
36 3C 37 3D
3A 40 3B 41
3E 44 3F 45
42 48 43 49
46 4C 47 4D
4A 50 4B 51
4E 54 4F 55
52 58 53 59
56 5C 57 5D
5A 60 5B 61
5E 64 5F 65
62 68 63 69
66 6C 67 6D
6A 70 6B 71
6E 74 6F 75
72 78 73 79
76 7C 77 7D
7A 80 7B 81
7E 84 7F 85
82 88 83 89
86 8C 87 8D
8A 90 8B 91
8E 94 8F 95
92 98 93 99
Rev 0.6 / Dec. 2009 64
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
96 9C 97 9D
9A A0 9B A1
9E A4 9F A5
A2 A8 A3 A9
A6 AC A7 AD
AA B0 AB B1
AE B4 AF B5
B2 B8 B3 B9
B6 BC B7 BD
BA C0 BB C1
BE C4 BF C5
C2 C8 C3 C9
C6 CC C7 CD
CA D0 CB D1
CE D4 CF D5
D2 D8 D3 D9
D6 DC D7 DD
DA E0 DB E1
DE E4 DF E5
E2 E8 E3 E9
E6 EC E7 ED
EA F0 EB F1
EE F4 EF F5
F2 F8 F3 F9
F6 FC F7 FD
FA FE FB FF
When program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also a
coupled row paired page data may be damaged. For example, during Page Program operation of page address 05h is
aborted by reset or power down, the data of 00h, 01h, 04h, and 05h page address may be spoiled.
Rev 0.6 / Dec. 2009 65
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
7.2. Extra Block Description
Device includes extra features like user OTP, Unique ID and Read ID2. User OTP, Unique ID can be programmed only
once and cannot be erased. The user OTP used one block which locates the second block of plane 0 (address<32:22>
= 0002h). Unique ID block has 64 pages, locates the first block of plane 0 and the first 64 pages of the block (ad-
dress<32:22> = 0000h, address<21:14> = 00h ~ 3Fh). Read ID2 can be only read, the size is one page. Physically,
ReadID2 area exists in plane1, but user block address does not care internally. To exit extra features, 07h or FFh com-
mand can be used.
7.3. Acceptable Command after 80h
After Program Start Command (80h) is inputted, do not input any command except 85h, 10h, 11h, 15h, and FFh. If a
command is inputted except these commands, the program operation cannot be executed.
7.4. Acceptable Command between Start command and Confirm command
Only Reset Command is available between start commands and confirm commands set (start command-address-confirm
command style) that is mentioned in 1.7 Command Set. If other command is inputted, the operation cannot be executed.
Do not input any commands except FFh. For instance, it is impossible to perform a normal Page Read operation, if any
command is inputted between Page Read Command Set (00h - 5 address cycle - 30h).
7.5. Restriction of Read Status Value in Multi Plane Operation
During Multi plane operation, only 70h, 78h, and FFh are available between 11h-81h. But, the pass/fail output information
of 70h and 78h is not valid. During this time, only ready / busy (I/O6 and I/O5) state can be checked. Refer to Figure 63.
Rev 0.6 / Dec. 2009 66
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
80h
I/Ox
R/B#
Address Data
I/O6 =>
I/O5 =>
I/O1 =>
I/O0 =>
Valid
Invalid
Invalid
Invalid
11h
70h
SR
out
81h Address Data 10h
70h
SR
out
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Valid
70h
SR
out
t
PROG
t
DBSY
IO 0 = 0, Pass
IO 0 = 1, Fail
■ Figure 63. Restriction read status in multi plane operation
7.6. Page Program Failure
If the Page Program operation for page address N is fail, remain data in data register may be different to input data by
host. Therefore, do not attempt to program the page address N in another block without the data input sequence. The
same input sequence of 80h command, address and data is necessary.
7.7. Restriction Multi Plane Operation
To prevent abnormal multi plane operation, do not input bad block address to all Multi Plane Operation. Otherwise, the
input data of valid block could be lost and the operation could be abnormally stopped.
Rev 0.6 / Dec. 2009 67
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
K O
H 2 7 U B G 8 T 2 A x x -
x
R
x
y w w x x
- hynix
- KOR
- H27UBG8T2Axx-xx
H : Hynix
27 : NAND Flash
U : Power Supply
BG : Density
8 : Bit Organiztion
T : Classification
2 : Mode
A : Version
x : Package Type
x : Package Material
: Hynix Symbol
: Origin Country
: Part Number
: U (2.7 V~ 3.6 V)
: 32 Gibit
: 8 (X8)
: Multi Level Cell + Single Die + Large Block
: 2(1nCE & 1R/nB; Sequential Row Read Disable)
: 2nd Generation
: T(48-TSOP1), Y(52-LGA)
: Blank(Normal), R(Lead & Halogen Free)
x : Bad Block
x : Operating Temperature
: B(Included Bad Block), S(1~5 Bad Block),
P(All Good Block)
: C(0୅~70୅), I (-40୅~85୅P
- y : Year (ex: 9 = year 2009, 0 = year 2010)
- ww : Work Week (ex:12 = work week 12)
- xx : Process Code
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
MARKING INFORMATION - VLGA/TSOP1

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash Document Title 32Gbit (4096 M x 8 bit) NAND Flash Memory

Revision History
Revision No.
0.0 0.1 0.2 Initial Draft. Update PKG outline. Add Marking Information . Update PKG Information. Update Multi Plane Cache Program. Correct Multi Plane Cache Program Operation Timings (Figure 22) 0.3 Correct Random Data Input Timings (Figure 24) Update PKG Mechanical Data (Figure 2-1) Correct Restriction read status in multi plane operation (Figure 63) 0.4 0.5 Correct7.5 Restriction of Read Status Value in Multi Plane Operation Correct7.6. Page Program Failure Correct4.3 Multi Plane Page Read Change 52-VLGA Contact, X8 Device (Figure 2) Update PKG Mechanical Data (Figure 2-1) Update Pin Description of CE# 0.6 Change Endurance Change AC Timing Characteristics (tRC, tRP, tWC, tWP, tCLS, tCS, tALS, tDS, tREA, tADL) Update Read ID table (3rd Byte) Change Bad Block Management Dec. 14. 2009 Preliminary Sep. 21. 2009 Oct. 5. 2009 Preliminary Preliminary Aug. 31. 2009 Preliminary

History

Draft Date
May. 22. 2009 Jun. 17. 2009 Jul. 16. 2009

Remark
Preliminary Preliminary Preliminary

Rev 0.6 / Dec. 2009

2

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash

Product Feature

Multilevel Cell technology

Endurance - 3,000 P/E cycles (with 24 bit/ 1,024byte ECC)

Supply Voltage - 3.3V device : Vcc = 2.7 V ~ 3.6 V Vcc = 2.7 V ~ 3.6 V

Data Retention - 10 Years

Organization - Page size : 8,640 Bytes(8192+448 bytes) - Block size : 256 pages(2M+112K bytes) - Plane size : 1,024 blocks

Package - TSOP (12x20) - LGA (14x18)

Page Read Time - Random Access: 200 ㎲ (Max.) - Sequential Access : 25 ㎱ (Min.)

Unique ID for copyright protection

Write Time - Page program : 1600 ㎲ (Typ.) - Block erase : 2.5 ㎳ (Typ.)

Operating Current
- Read

- Program - Erase - Standby

Hardware Data Protection - Program/Erase locked during power transitions

Rev 0.6 / Dec. 2009

3

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1.600us.6 / Dec.7V ~ 3.640 bytes.6V PACKAGE 48 .3V 32Gbit NAND flash memory. SUMMARY DESCRIPTION The product part NO. Page program operation can be performed in typical 1. Each block consists of 256 programmable pages.1. Product List Table 1 PART NUMBER H27UBG8T2A ORGANIZATION X8 Vcc RANGE 2. The H27UBG8T2A is a best solution for applications requiring large nonvolatile storage memory.(H27UBG8T2A) is a single 3. Each page contains 8.000 cycles when using relevant ECC and Error management. and a single block can be erased in typical 2. E/W endurance is stipulated at 3. Each plane is made up of the 1024 blocks.5ms. The Device contains 2 planes in a single die.LGA Rev 0.TSOP1 52 . 2009 4 . The pages are subdivided into an 8192-bytes main data storage area with a spare 448-byte district. On-chip control logic unit automates erase and program operations to maximize cycle endurance. 1.

12 x 20mm.100 11.48-lead Plastic Thin Small Outline. 12 x 20mm.680 5 Typ Max 1.980 0.6 / Dec.910 19. Package Outline Symbol A A1 A2 B C CP D E E1 e L alpha millimeters Min 0.150 1. 48-TSOP1 . Package Mechanical Data Rev 0.000 18.400 0.900 18.2. 48-TSOP1 Contact.120 20.500 0 12.300 0.000 20. x8 Device 1 48 NC NC NC NC NC NC R/B RE CE NC NC Vcc Vss NC NC CLE ALE WE WP NC NC NC NC NC 12 13 NAND Flash TSOP1 (x8) 37 36 24 25 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC Vcc Vss NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC ■ Figure 1-1.200 0.500 0.200 0.250 0.050 0. 2009 5 . Packaging Information ■ Figure 1.100 18.030 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1.170 0.48-lead Plastic Thin Small Outline.500 48-TSOP1 .100 12.

6 / Dec.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 2. 52-VLGA Contact. 2009 6 . x8 Device OA NC NC VSS CLE /CE VCC NC NC NC NC /WE /WP NC IO1 IO0 NC IO7 IO2 IO3 NC VSS VSS VCC NC NC IO4 VCC VCC IO6 IO5 NC NC R/B VSS NC NC /RE NC NC A B C D E F G H J K L OB NC ALE NC OC NC NC NC OD NC NC NC OE NC VSS M N OF NC NC 0 1 2 3 4 5 6 7 8 Rev 0.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash
■ Figure 2-1. 52-VLGA, 14 x 18mm, Package Outline (Top view through package)

Symbol A A1 A2 B B1 B2 C C1 C2 D D1 E CP1 CP2

millimeters
Min 17.90 Typ 18.00 13.00 12.00 13.90 14.00 10.00 6.00 1.00 1.50 2.00 1.00 1.00 0.80 0.65 0.95 0.90 0.70 1.00 1.00 0.75 1.05 14.10 Max 18.10

52-VLGA, 14 x 18mm, Package Mechanical Data

Rev 0.6 / Dec. 2009

7

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash Pin Diagram
■ Figure 3. Pin Diagram

VCC

CE# WE# RE# ALE CLE WP#

I/O0~I/O7 R/B#

VSS

Pin Names

I/O7~I/O0 CLE ALE CE# RE# R/B# WE# WP# VCC VSS NC

Data Input / Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Ready / Busy Write Enable Write Protect Power Supply Ground No Connection

Rev 0.6 / Dec. 2009

8

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1.3. PIN DESCRIPTION
Pin Name I/O0-I/O7 Description DATA INPUTS/OUTPUTS The I/O pins are used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during read / write operations. The I/O pins float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the I/O inputs inside the Command Register on the Rising edge of Write Enable (WE#). ADDRESS LATCH ENABLE This input activates the latching of the I/O inputs inside the Address Register on the Rising edge of Write Enable (WE#). CHIP ENABLE This input controls the selection of the device. When the device is busy, CE# low does not deselect the memory. The device goes into Stand-by mode when CE# goes High during 10us in Ready state. The CE# signal is ignored when device is in Busy state, and will not enter Standby mode even if the CE# goes high. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on the rise edge of WE#. READ ENABLE The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by one. WRITE PROTECT The WP# pin, when Low, provides a hardware protection against undesired write operations. Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up phases. READY / BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The VCC supplies the power for all the operations. (Read, Write, and Erase). GROUND NO CONNECTED

CLE ALE

CE#

WE# RE#

WP#

R/B# Vcc Vss NC

Notes:
A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

Rev 0.6 / Dec. 2009

9

192 + 448) bytes x 256pages x 2048 blocks = 36.786 kbits A14-A32 X Decoder Address register A0-A13 Y Decoder Address register Data Register & Sense Amp ALE CLE CE# RE# WE# WP# Column Decoder Command Interface Logic IO Buffer & latch Command register Global data buffer Output Driver I/O<7:0> Rev 0. Block Diagram ■ Figure 4.6 / Dec. 2009 10 .Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1.4. Block diagram Vcc Vss Program/Erase Controller HV generation X D E C O D E R NAND FLASH Memory Array 1 Device = (8.238.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1. 2009 11 . Rev 0. L must be set to Low. Array Organization ■ Figure 5. Array organization 1.6 / Dec. The Address consists of column address (A0~A13). Addressing Bus cycle 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle I/O0 A0 A8 A14 A22 A30 I/O1 A1 A9 A15 A23 A31 I/O2 A2 A10 A16 A24 A32 I/O3 A3 A11 A17 A25 L(1) I/O4 A4 A12 A18 A26 L(1) I/O5 A5 A13 A19 A27 L(1) I/O6 A6 L(1) A20 A28 L(1) I/O7 A7 L(1) A21 A29 L(1) Notes: 1.5. 3. plane address (A22).6. and block address (A23 ~ the last address). page address (A14 ~ A21). The device ignores any additional address input cycle than required. 2.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1. Command Set FUNCTION 1st Cycle 00h 00h 05h 31h 3Fh 90h 70h 80h 85h 85h 80h 60h FFh 60h 60h 60h 60h 00h 78h 80h 85h 80h Number of Address cycles 5 5 2 1 5 2 5 5 3 3 3 3 3 5 3 5 5 5 Data input cycles Yes Yes option Yes Yes option Yes 2nd Cycle 30h 35h E0h 10h 10h 15h D0h 60h 60h 60h 60h 05h 11h~81h2) 11h~81h2) 11h~81h2) 3 3 3 3 2 5 5 5 Number of Address cycles Data input cycles Yes option Yes 3rd Cycle 30h 30h/33h 35h D0h E0h 10h 10h 15h Acceptable command during busy No No No No No No Yes No No No No No Yes No No No No No Yes No No No PAGE READ READ FOR COPY-BACK RANDOM DATA OUTPUT1) SINGLE/multi plane CACHE READ5) SINGLE/multi plane CACHE READ END5) READ ID READ STATUS REGISTER PAGE PGM (start) / CACHE PGM 5)(end) RANDOM DATA INPUT 1) COPY-BACK PGM CACHE PGM (start) 5) BLOCK ERASE RESET multi plane PAGE READ multi plane CACHE READ START5) multi plane READ FOR COPY-BACK multi plane BLOCK ERASE multi plane DATA OUTPUT 1) 3) multi plane READ STATUS REGISTER multi plane PAGE PGM / multi plane CACHE PGM (end) multi plane COPY-BACK PGM multi plane CACHE PGM (start) 5) Rev 0.7.6 / Dec. 2009 12 .

4. Mode Selection CLE H ALE L CE# L WE# RE# H WP# X Read Mode L H L H X Address Input ( 5 Cycles ) MODE Command Input H L L H H Write Mode Command Input L H1) L H H Address Input ( 5 Cycles ) L L L H H Data Input L X X X X X L1) X X1) X X X L X X X X H H H3) X X X X H3) X X X X X X H H L OV/Vcc2) Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand-By Notes: 1. Multi Plane cache read. Read Status. 78h. 3. Interleave operation between two chips are allowed. and Multi Plane copy-back program. Multi Plane cache program. Any undefined command inputs are prohibited except for above command set. 6. and Multi Plane Read Status can be inputted to the device. and FFh. It is prohibited to use Read Status command (70h) in interleaved operation. 2.6 / Dec. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to avert unintended data out. All cache operation (cache program. Do not change Plane address order when using all Multi Plane operations. 2. 5. cache read) is available only within a block. 1. 3. 2009 13 .8. Multi Plane Read Status (78h) can be used to check each chip status. Any command between 11h and 81h is prohibited except 70h. 2. Multi Plane Random data-out must be used after Multi Plane read operations (Multi Plane Page Read. WP# should be biased to CMOS high or CMOS low for stand-by mode. Multi Plane Cache Read and Multi Plane Read for Copy Back). Multi Plane page read.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash Notes: 1. Random Data Input/Output must be performed in a selected page. L = Logic level LOW. Caution: 1. only Reset. X can be VIL or VIH. and Multi Plane read for copy-back must be used after Multi Plane pro grammed page. Rev 0. H = Logic level HIGH. In this time.

= Block No. which is placed on 00h block address. is guaranteed to be a valid block at the time of shipment. The devices are supplied with all the locations inside valid blocks erased (FFh). Bad block management flow chart Start Block No = 0 Read FFh check column 8192 of the first page Block No. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Flow chart 1. The Bad Block Information is written prior to shipping. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1. 8192 of the last page Pass Fail Fail Entry Bad Block No Last Block Yes End Notes: 1. 2.9. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. because the bad block information will be lost. The 1st block. Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. Do not try to erase the detected bad blocks. ■ Flow chart 1. Any block where the 1st Byte in the spare area of either the 1st or the last page does not contain FFh is a Bad Block. Do not perform program and erase operation in invalid block.6 / Dec. 2009 14 . + 1 Pass Read FFh check col. it is impossible to guarantee the input data and to ensure that the function is normal. Rev 0.

4.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 1. Table 2. Bad block table should be updated to prevent from erasing or programming Block A. An invalid block is one that contains one or more bad bits. Refer to Table 2 and Figure 6 for the recommended procedure to follow if an error occurs during an operation. Bad Block Replacement This device may have the invalid blocks when shipped from factory. 2. Rev 0.10. 2009 15 . Block failure Operation Erase Program Read ■ Figure 6. Bad block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Data in Block A is copied to same location in Block B which is valid block. Nth page of block A which is in controller buffer memory is copied into nth page of Block B. Block replacement Recommended Procedure Block Replacement Block Replacement ECC Block A 1 Page st Block B (2) 1 Page st Data Data Nth Page Failure (3) Nth Page FFh FFh Buffer memory Controller Notes: 1. An error occurs on nth page of the Block A during Program or Erase operation. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register.6 / Dec. the block has to be replaced by copying the data to a valid block. Over the lifetime of the device additional Bad Blocks may develop. In this case. 3. The failure of a page program operation does not affect the data in other pages in the same block.

stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. 2. Rev 0. 2. Refer also to the Hynix SURE Program and other relevant quality documents. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. 2.6 to 4. Electrical Characteristics 2. Absolute Maximum Rating Symbol Parameter Ambient Operating Temperature (Commercial Temperature Range) TA Ambient Operating Temperature (Extended Temperature Range) Ambient Operating Temperature (Industrial Temperature Range) TBIAS TSTG VIO VCC Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Value Min 0 to 70 -25 to 85 -40 to 85 -50 to 125 -65 to 150 -0.1.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2. 2009 16 .6 -0. This single device has a maximum of 50 invalid blocks. The 1st block is guaranteed to be a valid block at the time of shipment. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.2. Valid Blocks Symbol Valid Block Number NVB Min 1998 Typ Max 2048 Unit Blocks Notes: 1. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.6 / Dec. The device may contain bad blocks upon shipment. Invalid blocks are one that contains one or more bad bits.6 to 4.6 Unit °C °C °C °C °C V V Notes: 1. Except for the rating "Operating Temperature Range". 3.

3. IOUT=0 ㎃ Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Current (R/B#) ICC2 ICC3 ICC4 ICC5 ILI ILO VIH VIL VOH VOL IOL(R/B#) CE#=VIH.3 0. WP#=0V/ VCC CE#=VCC-0.8 -0.2x Vcc 0. CE#=VIL.3V Typ Max 50per device 50 ㎃ Unit Operating Current Read ICC1 - - ㎃ Rev 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2.3 2.2.1 ㎃ VOL=0.4 ㎃ ㎃ ㎃ ㎂ ㎂ ㎂ V V V V ㎃ 3. 2009 17 .4 8 10 10 50 50 1 50 ± 10 ± 10 Vcc+0.6 / Dec.4V Vccx0. WP#=0V/VCC VIN=0 to VCC(MAX) VOUT=0 to VCC(MAX) IOH=-200 ㎂ IOL=2. DC and Operating Characteristics HY27UCG8T2A Parameter Symbol Test Conditions Min Power on reset current ICC0 FFh command input after power on tRC= tRC(min).

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2. 2.5 - 200 10 1 ㎲ ㎳ cycles Notes: 1. Rev 0.6V 0 V to VCC 5㎱ Vcc /2 1 TTL GATE and CL=50㎊ Notes: 1.5.These parameters are verified device characterization and are not 100% tested.0㎒) Test Condition VIN = 0V VIN = 0V Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Min - Max 10 10 Unit ㎊ ㎊ 2. AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (2.3V. Program/ Read / Erase Characteristics Parameter Program (following 10h) Cache Program (following 15h) multi plane Program / multi plane Cache Program / multi plane Copy-Back Program (following 11h) Cache Read / multi plane Cache Read (following 31h/3Fh) Block Erase / multi plane Block Erase Number of partial Program Cycles in the same page Symbol tPROG tCBSYW tDBSY Min Typ 1600 3 Max 5000 5000 5 Unit ㎲ ㎲ ㎲ tCBSYR tBERS NOP - 3 2. Not 100% tested.7V-3.6. F=1.7V ≤ Vcc ≤ 3.4. Typical value is measured at VCC=3. Pin Capacitance (TA=25°C. 2009 18 . TA=25℃.6 / Dec.6V) Value 2.

2009 19 .6 / Dec.7.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2.3V Min 12 5 20 5 12 12 5 12 5 25 10 200 Max Unit ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎲ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ ㎱ Rev 0. AC Timing Characteristics Parameter CLE setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE# high hold time Data transfer from cell to register ALE to RE# delay CLE to RE# delay Ready to RE# low RE# pulse width WE# high to busy Read cycle time RE# access time RE# high to output high Z CE# high to output high Z RE# high to output hold RE# low to output hold RE# or CE# high to output hold RE# high hold time CE# low to RE# low WE# high to RE# low Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tR tAR tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tRHOH tRLOH tCOH tREH tCR tWHR 15 5 15 10 10 80 25 20 100 50 10 10 25 12 100 3.

2009 20 . Rev 0. The transition of the corresponding control pins must occur only while WE# is held low. the device goes into Busy for maximum 5us. If Reset Command (FFh) is written at Ready state. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. Program / Erase Disable Operation: WP# Low to WE# High. Program / Erase Enable Operation: WP# high to WE# High. 3. 2. 4.6 / Dec.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash RE# high to WE# low Output high Z to RE# low Address to data loading time Device resetting time (Read/Program/Erase) Write protection time tRHW tIR tADL tRST tWW 100 100 0 100 20/30/500 ㎱ ㎱ ㎱ ㎲ ㎱ Notes: 1.

then the device or interleaved address is ready for another command and all other bits in the status value are valid.6 / Dec. Rev 0.8. 2. If cleared to zero. I/O5: If set to one. 4. I/O0: This bit is only valid for Program and Erase operations.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2. I/O1: This bit is only valid for cache program operations. then there is no array operation in progress. When Cache program is not supported. this bit is not used. If cleared to zero. When overlapped interleaved operations or cache commands are not supported. then the last command issued is not yet complete and Status Register bits<5:0> are invalid value. During Cache Program operations. This bit is not valid until after the second 15h command or the 10h command has been transferred in a Cache program sequence. Status Register Coding I/O Page Program Pass/ Fail N/A N/A N/A N/A N/A Ready / Busy Write Protect Block Erase Pass/ Fail N/A N/A N/A N/A N/A Ready / Busy Write Protect Read Cache Read N/A N/A N/A N/A N/A Ready / Busy Ready / Busy Write Protect Cache Program Pass/ Fail Pass/ Fail N/A N/A N/A Ready / Busy Ready / Busy Write Protect Coding 70h/ 78h N page Pass : '0' Fail : '1' N-1 page Pass : '0' Fail : '1' '0' '0' '0' Ready / Busy Busy : '0' Ready : '1' Data Cache Ready / Busy : '0' Ready : '1' Protected : '0' Not Protected : '1' 0 1 2 3 4 5 6 7 N/A N/A N/A N/A N/A N/A Ready / Busy Write Protect Notes: 1. then this bit indicates whether another command can be accepted. I/O6: If set to one. and I/O5 indicates whether the last operation is complete. 2009 21 . this bit is not used. this bit is only valid when I/O5 is set to one. 3. then there is a command being processed (I/O6 is cleared to zero) or an array operation in progress. When cache operations are in use.

ECC Level Technology (Design Rule). Block size. Read ID Data Table Part Number H27UBG8T2A Voltage 3. Redundant area size Plane Number. Number of Simultaneously Programmed Pages. Page size. Write Cache.9. Device Identifier Coding Parameter Device Identifier Byte 1st 2nd 3rd 4th 5th 6th Symbol Description Manufacturer Code Device Identifier Internal chip number. EDO.10. 3rd Byte of Device Identifier Description 3rd cycle Description 1 2 4 Reserved 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Supported Not Supported Not Supported Supported 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 0 0 1 1 I/O 0 0 1 0 1 Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Interleaved Program between Multiple dice Write Cache Rev 0. Interface 2.3V Bus Width X8 Manufacture Code ADh Device Code D7h 3rd 94h 4th 9Ah 5th 74h 6th 42h 2.10.6 / Dec. cell Type. 2009 22 .1. Interleaved Program.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2.

10.3.6 / Dec. 4th Byte of Device Identifier Description 4th cycle Description 2KB 4KB 8KB Reserved 128KB 256KB 512KB 768KB 1MB 2MB Reserved Reserved 128B 224B 448B Reserved Reserved Reserved Reserved Reserved 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 0 0 1 1 I/O 0 0 1 0 1 Page Size (Without Spare Area) Block Size (Without Spare area) Redundant Area Size 2.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2.2.10. 5th Byte of Device Identifier Description 5th cycle 1 2 4 8 1bit/512Bytes 2bit/512Bytes 4bit/512Bytes 8bit/512Bytes 16bit/512Bytes 24bit/2048Bytes 24bit/1024Bytes Reserved 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 Description I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 0 0 1 1 I/O 2 0 1 0 1 I/O 1 I/O 0 Plane Number ECC Level Reserved Rev 0. 2009 23 .

6 / Dec. 2009 24 .Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 2.4.10. 6th Byte of Device Identifier Description 6th cycle Description 48nm 41nm 32nm Reserved Reserved Reserved Reserved Reserved Not Support Support SDR DDR 0 1 0 0 0 0 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 0 0 0 0 1 1 1 1 I/O 1 0 0 1 1 0 0 1 1 I/O 0 0 1 0 1 0 1 0 1 NAND Technology EDO Support NAND Interface Reserved Rev 0.

Data Output. and device is not busy state Rev 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3.6 / Dec. Address Input. CE# and ALE is low. when CLE is high. Command Latch Cycle Timings ■ Figure 7. 2009 25 .1. Data Input. Command latch timings CLE CE# WE# t CLS t CS t CLH t CH t WP ALE tALS t DS t ALH t DH I/Ox Command : Don’t care Note: All command except Reset. and Multi Plane Read Status is issued to command register on the rising edge of WE#. and Standby. Write Protect. 3. Timing Diagram Bus Operation There are six standard bus operations that control the device. Read Status. These are Command Input.

2009 26 .3. and device is not Busy state. Address Latch Cycle Timings ■ Figure 8.2. Input data cycle timings CLE tCLH CE# tCH ALE tALS tWC tWP t WH tDH t WP tDS t DH tWP tDS tDH WE# tDS I/Ox DIN 0 DIN 1 DIN final : Don’t care Note: Data Input cycle is accepted to data register on the rising edge of WE#.6 / Dec.Add2 Row Add1 Row Add2 Row Add3 : Don’t care 3. Input Data Latch Cycle Timings ■ Figure 9. Rev 0.Add1 Col. when CLE and CE# and ALE are low.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Address latch timings tCLS CLE tCS tWC tWC tWC tWC CE WE tWP tWH tALH tWP tWH tALH tWP tWH tALH tWP tWH tALH tALS tALS tALS tALS tALS tALH ALE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH I/Ox Col.

WE#=H. Rev 0. Transition is measured +/-200mV from steady state voltage with load. This parameter is sampled and not 100% tested. WE#=H. 3.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. ALE=L. ( tCHZ. Data Output Cycle Timings (CLE=L.4. Data output cycle timings (EDO) CE# t RP tRC tREH tCHZ RE# tREA t CR t RLOH t REA tRHZ tRHOH Dout I/Ox t RR Dout R/B# : Don’t care Notes: 1. Data Output Cycle Timings (EDO type. tRLOH is valid when frequency is higher than 33MHz. WP#=H) ■ Figure 10. 2009 27 .5. Data output cycle timings tRC CE# t REH RE# t REA tREA tRHZ tREA tRHZ tRHOH I/Ox t RR Dout tCHZ Dout Dout R/B# Notes: 1. tRHOH starts to be valid when frequency is lower than 33MHz. ALE=L) ■ Figure 11. Transition is measured +/-200mV from steady state voltage with load. tRHOH starts to be valid when frequency is lower than 33MHz. ( tCHZ. tRLOH is valid when frequency is higher than 33MHz. This parameter is sampled and not 100% tested. tRHZ) 2.6 / Dec. tRHZ) 2. CLE=L.

6. Read Status Cycle Timings ■ Figure 12. Multi Plane Read Status Timings ■ Figure 13.7. 2009 28 . Multi plane read status timings CLE CE# WE# ALE RE# I/Ox tCS t WC tWP tWH tALH tALS tALH tAR tCLS tCLH tCH tCR tWP tCHZ tCOH tDS tDH t WHR tREA tRHZ tRHOH 78h Row.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3.Add3 Status : Don’t care Rev 0. Read status timings CLE tCLS tCS tCLH tCH tCLR CE# tCR WE# tWP tWHR tREA tCHZ tRHZ tRHOH Status output RE# tDS I/Ox tDH 70h tIR : Don’t care 3.Add2 Row.6 / Dec.Add1 Row.

Page read operation timings t CH CE# CLE ALE WE# RE# I/Ox R/B# t CS t CLS t CLH t WC t WB tCLR tCHZ tAR tCOH tRC tRR 00h Col.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Add3 30h tR Dout N Dout N+1 Dout N+2 : Don’t care Rev 0. Add2 Row. Page read operation timings CE# CLE ALE WE# RE# I/Ox R/B# 00h Col. Add2 Row.9. Add1 Col. 2009 29 . Add1 Col. Add1 Row.8.6 / Dec. Page Read Operation Timings (Read One Page) ■ Figure 14. Add2 Row. Page Read Operation Timings (Intercepted by CE#) ■ Figure 15. Add3 t WC tWB tAR t RC tRHZ tRR 30h tR Dout N Dout N+1 Dout N+2 Dout M : Don’t care 3. Add2 Row. Add1 Row.

11. Random data output timings Note: Random data output is available within a page. 2009 30 .Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Rev 0. Random Data Output Timings ■ Figure 17. Page Read Operation Timings with CE# don't care ■ Figure 16. Page read operation timings with CE# don't care 3.10.6 / Dec.

12. Multi Plane Page Read Operation with Random Data output Timings ■ Figure 18. Multi Plane page read must be used after Multi plane programmed page. Multi Plane cache program. Multi plane page read operation timings with random data output Notes: 1. Multi Plane Random data-out must be used after multi plane read operations. 2009 31 .6 / Dec. and Multi Plane copy-back program. Multi Plane Page addresses are required to be the same. 2.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. 3. Rev 0.

Cache read operation timings Notes: 1. The column address will be reset to 0 by the 31h/3Fh command input.6 / Dec. 2009 32 . Rev 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Cache read operation is available only within a block.13. Cache Read Operation Timings ■ Figure 19. 2.

Multi plane cache read operation Timings Notes: 1.14.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. The column address will be reset to 0 by the 31h/3Fh command input. Make sure to terminate the operation with 3Fh command.6 / Dec. and multi plane copy-back program Rev 0. Multi Plane Cache Read Operation Timings ■ Figure 20. If the page read operation is completed. 2. 2009 33 . 3. Multi Plane cache read must be used after Multi plane programmed page. issue FFh reset before next operation. 4. Multi Plane Page addresses are required to be the same. multi plane cache program. 5. Cache read operation is available only within a block.

15. 6th cyc. 4th cyc.16. 2009 34 . Read ID Operation Timings ■ Figure 21.6 / Dec.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Rev 0. Page Program Operation Timings ■ Figure 22. Read ID operation timings CE# CLE WE# ALE RE# I/Ox tWHR t AR t REA 90h 00h ADh Maker code Device code 3rd cyc. 3. 5th cyc. Page program operation timings Note: tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.

Page program operation timings with CE# don't care Note: tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. 2. Random Data Input Timings ■ Figure 24. Page Program Operation Timings with CE# don't care ■ Figure 23. Rev 0.18. Random data input can be performed in a page.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. 2009 35 . Random data input timings Notes: 1.6 / Dec.17. 3.

19.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Multi Plane Page Program Operation Timings ■ Figure 25. 2009 36 . 78h and FFh 2.6 / Dec. Multi Plane Page addresses are required to be the same. Multi plane page program operation timing Notes: 1. Rev 0. 3. Any command between 11h and 81h is prohibited except 70h. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.

Copy-Back Program Operation Timings with Random Date Input ■ Figure 26.(command input cycle time + address input cycle time + Last page data loading time Rev 0. Copyback program operation timing with random data input Note: Copy back operation is allowed only within the same memory plane. Cache program operation timings Note: tPROG = Program time for the last page + Program time for the (last -1)th page .20. 2009 37 . 3.21. Cache Program Operation Timings ■ Figure 27.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3.6 / Dec.

22. Multi Plane Cache Program Operation Timings ■ Figure 28.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3. Issue FFh reset before next operation. If the operation is terminated.6 / Dec. 2009 38 . Multi plane cache program operation timings Notes: 1. 3. Rev 0. Selected Page address except A22 within two blocks must be same.(command input cycle time + address input cycle time + Last page data loading time) 2. tPROG = Program time for the last page + Program time for the (last -1)th page .command sequence. Make sure to terminate the operation with 80h-10h.

Multi plane erase operation timings Rev 0. 2009 39 . Block Erase Operation Timings ■ Figure 29.24.23. Multi Plane Erase Operation Timings ■ Figure 30.6 / Dec. Block erase operation timings 3.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3.

Reset Timings ■ Figure 31. 2009 40 .Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 3.25. Reset timings CE# CLE WE# I/Ox R/B# tWB FFh tRST Rev 0.6 / Dec.

The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected column address up to the last column address. Random data output can be operated multiple times.6 / Dec. The 8. they may be read out in 25㎱ cycle time by sequentially pulsing RE#. which is going to be out. Refer to Figure 33. ■ Figure 32. Once the data in a page is loaded into the data registers. may be changed to the address. which follows random data output command. regardless of how many times it is done in a page. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4.1. The system controller may detect the completion of this data transfer 200㎲(tR) by analyzing the output of R/B# pin.640 bytes of data within the selected page are transferred to the data registers in less than 200㎲(tR). Random data output only is issued in Ready state. 2009 41 . Rev 0. DEVICE OPERATION 4. Page read CLE CE# ALE WE# R/B# RE# tR I/Ox 00h Address (5 cycle) 30h Data Output (Serial Access) Random data output Random data output operation changes the column address from which data is being read in the page register. Page Read This operation is initialized by 00h-30h to the command register along with followed by five address input cycles.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 33. Cache read As defined for Read CLE WE# RE# I/Ox R/B# 30h tR 31h tCBSYR Column 0 D0 . device doesn't allow any other command except Cache Read command (31h). next page is transferred from memory cell to data register. Dn 31h tCBSYR D0 . and Reset (FFh). Read Status (70h.. 78h). Because it is not necessary to output a whole page data before issuing another 31h command.6 / Dec. cache read operation is used within a block. cache read must be ended by 3Fh command or issue reset (FFh) before next operation.. During the Cache Read Operation. Dn 3Fh tCBSYR D0 . After random access (R/B# returns to high). Random data output R/B# tR RE# I/Ox 00h Address (5 cycle) 30h Data Output 05h Address (2 cycle) E0h Data Output 4. Dn Column 0 Column 0 Rev 0... ■ Figure 34. First step is same as normal page read. While cache register data is outputted. 3Fh command should be issued.. Data is being transferred from the data register to the cache register. Read (00h). if serial data output time exceeds random access time (tR). To carry out other operations after cache operation. 31h command is latched into the command register.2.. issuing a page read sequence (00-30h). the random access time can be hidden. R/B# will stay low during present page random accessing and previous page transferring to cache register. 2009 42 . This command transfer data from data register to the cache register without issuing next page read. Cache Read (available only within a block) To improve page read throughput. The subsequent pages are issued additional 31h commands. To terminate cache read.

Figure 36 shows the command sequence for the multi plane cache read operation. multi plane Page Read must be used in the block which has been programmed with Multi plane Page Program. Multi plane page read Page address : Page M Plane address : Fixed “Low” Block address : Block J Page address : Page M Plane address : Fixed “High” Block address : Block K A I/Ox R/B# 60h Address (3 Cycle) 60h Address (3 Cycle) 30h tR A Column address : Fixed “Low Page address : Page M Plane address : Fixed ‘Low’ Block address : Block J Column address : Valid B Data output I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h B Column address : Fixed “Low Page address : Page M Plane address : Fixed ‘High’ Block address : Block K Column address : Valid I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data output 4. Once the data is loaded into the data registers. The restrictions for multi plane Page Read are shown in Figure 35. for a single plane with 8640byte page registers. only same page can be selected from each plane. Both confirm commands. The data output of second plane can be read out using the identical command sequences. 30h and 33h. which enables high read throughput by reading two pages in parallel. The system controller can detect the completion of data transfer (tR) by monitoring the output of R/B# pin. Multi plane Page Read is initiated by repeating command 60h followed by three address cycles twice. Multi Plane Cache Read (available only within a block) The device supports multi plane cache read. the data output of first plane can be read out by issuing command 00h with Five Address Cycles. are valid for the first page read sequence. Multi Plane Page Read Multi plane Page Read is an extension of Page Read.3. 2009 43 .6 / Dec. Rev 0. command 05h with two column address and finally E0h.4. activating the two sets of 8640byte page resisters enables a random read of two pages. In this case. ■ Figure 35.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4. After Read Confirm command (30h) the 17280bytes of data within the selected two pages are transferred to the data registers in less than 200㎲ (tR). Since the device is equipped with two memory planes.

Multi Plane cache read is available only within a block per plane. Multi plane cache read Page address : Page M Plane address : Fixed “Low” Block address : Block J Page address : Page M Plane address : Fixed “High” Block address : Block K A I/Ox R/B# 60h Address (3 Cycle) 60h Address (3 Cycle) 33h tR A Column address : Fixed “Low” Page address : Page M Plane address : Fixed “Low” Block address : Block J Column address : Valid B Data output I/Ox R/B# 31h tCBSYR 00h Address (5 Cycle) 05h Address (2 Cycle) E0h B Column address : Fixed “Low” Page address : Page M Plane address : Fixed “High” Block address : Block K Column address : Valid I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h Data output Notes: 1. initiated by writing 90h to the command register. 5. The operation has to be terminated with "3Fh" command. 5th. 6th cycle ID.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 36. Six read cycles sequentially output the manufacturer code (ADh). respectively. 3. Read ID The device contains a product identification mode. Figure 37 shows the operation sequence. Selected Page address except for A22 within two blocks must be same. Rev 0. followed by an address input of 00h. 4. 4th. 2009 44 .6 / Dec. while 2.5. 4. Plane 0 and plane 1 should be selected within the same chip 2. Only one block should be selected from the each Plane. The command register remains in Read ID mode until further commands are issued to it.10 READ ID data tables explain the byte meaning. and the device code and 3rd.

STATUS REGISTER CODINGS for specific Status Register definitions and Figure 38.6 / Dec. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired.Add3 Status 45 . After writing Read Status (70h) or Multi Plane Read Status (78h) command to the command register. program or erase operation is completed. and whether the program or erase operation is completed successfully. a read cycle outputs the content of the Status Register to the I/O pins only if CE# and RE# are low. Therefore. 2009 78h Row. Refer to 2.Add1 Row. The command register remains in Read Status mode until further commands are issued to it. Multi plane read status CLE ALE WE# RE# I/Ox Rev 0. Read Status Register The device contains a Status Register which may be read to find out whether read. ■ Figure 38. whichever occurs last. if the status register is read during a random read cycle.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 37.8.6. the read command (00h) should be given before starting read cycles. Read ID CLE WE# ALE RE# I/Ox tWHR 90h 00h ADh D7h 94h 9Ah 74h 42h 4.Add2 Row. Read status CLE WE# RE# I/Ox 70h Status ■ Figure 39. Figure 39 for Read Status.

A page program cycle consists of a serial data loading period in which up to 8640bytes of data may be loaded into the data register. Once the program process starts. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. Figure 40 and Figure 41 details the sequence. or the Status bit (I/ O 6) of the Status Register. which will be entered. when all internal operations are complete (status bit I/O 6 = high). The command register remains in Read Status command mode until another valid command is written to the command register.7. the Read Status Register command may be entered to read the status register. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 times.6 / Dec. The Page Program Confirm command (10h) initiates the programming process. may be changed to the address which follows random data input command (85h). Only the Read Status command and Reset command are valid while programming is in progress. The program addressing should be done in sequential order in a block. The system controller can detect the completion of a program cycle by monitoring the R/B# output. The serial data-loading period begins by inputting the Serial Data Input command (80h). The Write Status Bit (I/O 0) is valid. The device supports random data input in a page. Page Program The device is programmed as a page unit. followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The internal write state controller automatically executes the algorithms and timings necessary for program and verify. Writing 10h alone without previously entering the serial data will not initiate the programming process. Page Program CLE CE# ALE WE# RE# I/Ox R/B# 80h Address 5 cycle Data Input 10h tPROG I/O 0 = 0 PROGRAM Pass I/O 0 = 1 PROGRAM Fail 70h Status Rev 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4. regardless of how many times it is done in a page. ■ Figure 40. followed by the five cycle address inputs and then serial data. Random data input may be operated multiple times. The column address of next data. thereby freeing the system controller for other tasks. The bytes other than those to be programmed do not need to be loaded. 2009 46 .

Read Status command can be 70h or 78h. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). 5. Multi Plane Program Device supports multiple plane program. A multiple plane program cycle consists of a double serial data loading period in which up to 17. 3. The data of first page other than those to be programmed do not need to be loaded. The data of second page other than those to be programmed do not need to be loaded. Once it has become ready again. Address for this page must be within first plane (A<22>=0). Rev 0. User can check operation status by R/B# pin or read status register command.8. It is possible to program in parallel 2 pages. The serial data loading period begins by inputting the Serial Data Input command (80h). 2009 47 . Any command between 11h and 81h is prohibited except 70h/78h and FFh. followed by the five cycle address inputs and then serial data for the 1st page.280bytes of data may be loaded into the data register. status register command is also available during Dummy Busy time (tDBSY). followed by second page address (5 cycles) and its serial data input. one per each plane. Figure 42 details the sequence.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 41. The device supports random data input exactly like page program operation. Plane 0 and Plane 1 should be selected within the same chip Only one block should be selected from the each Plane. followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. ■ Figure 42. Multi plane page program 1 st plane address Data Input 11h t DBSY A I/Ox R/B# A 80h Address (5 cycle) 2 nd plane address 81h Address (5 cycle) Data Input 10h t PROG 70h Status I/Ox R/B# Notes: 1. 81h command must be issued. Program Confirm command (10h) makes parallel programming of both pages start. Random data input Column address I/Ox R/B# 80h Address (5 Cycle) Data Input 85h Address (2 Cycle) Data Input 10h t PROG 70h Status 4. 2.6 / Dec. Selected Page address except for A22 within two blocks must be same. fail bit of status register will be set: Pass/Fail status of each plane can be checked by Multi Plane Read Status. as if it were a normal page program. In case of fail in first plane or second plane page program. 4. Address for this page must be within second plane (A<22>=1).

transfer from the cache register to the data register is held off until cell programming of current data register contents has been done. After the serial data input command (80h) is loaded to the command register. Pass/fail status of only the previous page (I/O 1) is available upon the return to Ready state. the data in the cache register is transferred into the data register for cell programming. which is executed with 8. a full or partial page of data is latched into the cache register. Pass/fail status is available in two steps.640 bytes cache registers and same bytes data register. In addition. and then the cache write command (15h) is loaded to the command register. I/O 1 may be read together when I/O 0 is checked. User must give address and data after 80h command. There are some restrictions for cache program operation. On the second and cascading sequence. Status Register Coding and Figure 43 for more details. Rev 0. The last page of the target programming sequence must be programmed with actual “Page Program” command (10h). After all data of the cache register is transferred into the data register. the device goes to the Ready state to load the next data into the cache register by issuing another cache program command sequence (80h-15h). Cell programming of the data of data register and loading of the next data into the cache register is consequently processed as a pipeline method. At this time. the device remains in busy state. followed by 5 cycles of address. Cache Program (available only within a block) Cache Program is an extension of the standard page program.9. If single plane cache program begins. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1". Read Status command (70h) may be issued to find out when the cache register is ready by polling the Cache-Busy status bit (I/O 6).Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4. Refer to 2. and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". 2009 48 . 2. the status bit (I/O 5) can be used to determine when the cell programming of the current data register contents is complete.8. The Busy time of first sequence equals the time it takes to transfer the data of cache register to the data register.6 / Dec. After that sequence. 1. single plane sequence should be used until single plane cache program is ended. The cache program command is available only within a block.

Cache program A I/Ox R/B# A 80h Address (5 cycle) Data Input 15h t CBSYW B I/Ox R/B# B 80h Address (5 cycle) Data Input 15h t CBSYW I/Ox R/B# 80h Address (5 cycle) Data Input 10h t PROG 70h Status Pass / Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation. The Ready/ Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command. Rev 0.6 / Dec. I/O 0 : Pass / Fail of the current page program operation. the Pass/Fail for previous page and current page can be shown through I/O1 and I/O0 concurrently. The Pass / Fail status on I/O 0 and I/O 1 are valid under the following conditions. Status on I/O 0 : Ready / Busy is Ready state.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 43. Status on I/O 1 : Data Cache Ready / Busy is Ready State. The Data Cache Ready / Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command. 2009 49 . I/O 1 : Pass / Fail of the previous page program operation. I/O 1 => I/O 0 => 80h-add-data-15h Page 1 Invalid Invalid 70h tCBSYW SR OUT Page1 Invalid 80h-add-data-15h Page 2 tCBSYW Page1 Page2 70h SR OUT Page N-2 Invalid 80h-add-data-15h Page N-1 tCBSYW Invalid Invalid 80h-add-data-15h Page N tPROG Page N-1 Page N 70h SR OUT 70h SR OUT 70h SR OUT 70h SR OUT R/B# Pin Data Cache Ready /Bysy (I/O6) Data Cache Ready /Bysy (I/O5) Page 1 Page 2 Page N-1 Page N During both I/O6 and I/O5 return to high.

Selected Page address except for A22 within two blocks must be same. Reading the Status per Plane is available only 78h.” 6. ■ Figure 44. Multi Plane cache program is available only within a block per Plane.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4. followed by the five cycle address inputs and then serial data for the first page. Read Status command can be 70h or 78h. The data of first page other than those to be programmed do not need to be loaded. Once it has become ready again. 3. 2009 50 . If multiplane cache program begins.10. Cache Program Confirm command (15h) makes parallel programming of both pages start. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Address for this page must be within second plane (A<22>=1). Issue FFh reset before next operation. Rev 0. Plane 0 and Plane 1 should be selected within the same chip 2.6 / Dec. The serial data-loading period begins by inputting the Serial Data Input command (80h). Multi plane cache program Column address : Valid Page address : Page M Plane address : Fixed ‘Low’ Block address : block J Column address : Valid Page address : Page M Plane address : Fixed ‘High’ Block address : block K 81h Address (5 Cycle) Data Input 15h A I/Ox R/B# 80h Address (5 Cycle) Data Input 11h tDBSY Column address : Valid Page address : Page M+n Plane address : Fixed ‘Low’ Block address : block J 80h Address (5 Cycle) Data Input 11h 81h Column address : Valid Page address : Page M+n Plane address : Fixed ‘High’ Block address : block K Address (5 Cycle) Data Input 10h tCBSYW A I/Ox R/B# 78h Address (3 Cycle) Status per plane tDBSY tPROG Notes: 1. followed by 2nd page address (5 cycles) and its serial data input. the last page of the target programming sequence must be programmed with actual Page Program command (10h). Multi Plane Cache Program (available only within a block) The device supports multi plane cache program. multiplane sequence should be used until multiplane cache program is ended. 7. If the operation is terminated. 81h command must be issued. The data of second page other than those to be programmed do not need to be loaded. 5. And last page inputs Program confirm command (10h). Only one block should be selected from the each Plane. 4. the result per plane of the operation is shown through the "78h" Multi Plane Read Status command. Any command between 11h and 81h is prohibited except 70h/78h and FFh. Address for this page must be within first plane (A<22>=0). The device supports random data input exactly like page program operation. After the "15h"or"10h" command. The operation has to be terminated with “10h” command. Figure 44 shows the command sequence for Multi Plane Cache Program operation. which enables high program throughput by programming two pages.

data modification is possible using random data input command (85h) as shown in Figure 45.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4.640-byte data into the internal data buffer. During copy-back program. A bit error is checked by sequential reading the data output. Copy-Back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. When the Copy-Back Program is complete. the system performance is improved. 2009 51 . Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address.6 / Dec. The benefit is especially obvious when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned free block.11. Since the time-consuming re-loading cycles are removed. Once the program process starts. the Write Status Bit (I/O 0) may be checked. The command register remains in Read Status command mode until another valid command is written to the command register. In the case where there is no bit error. Therefore. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. Copyback program Source Address I/Ox R/B# 00h Address (5 cycle) 35h tR Column address 1. Actual programming operation begins after Program Confirm command (10h) is issued. the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B# output. the data do not need to be reloaded. A read operation with "35h" command and the address of the source page moves the whole 8. or the Status bit (I/O 6) of the Status Register.2 Address (2 cycle) Data output A A I/Ox R/B# 85h Target Address Address (5 cycle) Data 85h Data 10h t PROG 70h Status Rev 0. ■ Figure 45.

Multi Plane Copy-Back Program Multi plane Copy-Back Program is an extension of Copy-Back Program. for a single plane with 8.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 4. Figure 46.2 : Valid I/Ox R/B# 81h Address (5 Cycle) Data 85h Address (2 Cycle) Data 10h t PROG Rev 0. Figure 47.2 : Valid C Data output I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h C Column address : Valid Page address : Page N Plane address : Fixed ‘Low’ Block address : Block P Column address 1. Figure 46 and Figure 47 show command sequence for the Multi Plane copy-back operation. Second case. 2009 52 . Multi plane Copyback program Page address : Page M Plane address : Fixed “Low” Block address : Block J Page address : Page M Plane address : Fixed “High” Block address : Block K A I/Ox R/B# 60h Address (3 Cycle) 60h Address (3 Cycle) 35h tR A Column address : Fixed “Low Page address : Page M Plane address : Fixed ‘Low’ Block address : Block J Column address 1. shows random data input of two planes that started right after finishing random data output of previous two planes. activating the two sets of 8. Since the device is equipped with two memory planes.640-byte page registers enables a simultaneous programming of two pages.2 : Valid D 11h t DBSY I/Ox R/B# D 85h Address (5 Cycle) Data 85h Address (2 Cycle) Data Column address : Valid Page address : Page N Plane address : Fixed ‘High’ Block address : Block Q Column address 1.12. ■ Figure 46. First case.6 / Dec.640 byte page registers. shows the random data input of each plane which started right after finishing the random data output of each Plane.2 : Valid B Data output I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h B Column address : Fixed “Low Page address : Page M Plane address : Fixed ‘High’ Block address : Block K Column address 1.

The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h).2 : Valid I/Ox R/B# 81h Address (5 Cycle) Data 85h Address (2 Cycle) Data 10h t PROG 4. Rev 0. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE# after the erase confirm command input. 2009 53 . Only address A22 to A32 is valid while A14 to A21 is ignored. the Write Status Bit (I/O 0) may be checked. Multi plane Copyback program Page address : Page M Plane address : Fixed “Low” Block address : Block J Page address : Page M Plane address : Fixed “High” Block address : Block K A I/Ox R/B# 60h Address (3 Cycle) 60h Address (3 Cycle) 35h tR A Column address : Fixed “Low” Page address : Page M Plane address : Fixed “Low” Block address : Block J Column address 1.2 : Valid B Data output I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h B Column address : Valid Page address : Page M Plane address : Fixed “Low” Block address : Block P Column address 1. The system controller can detect the completion of an erase by monitoring the R/B# output. Once the erase process starts.2 : Valid D Data output I/Ox R/B# 00h Address (5 Cycle) 05h Address (2 Cycle) E0h D Column address : Valid Page address : Page M Plane address : Fixed “High” Block address : Block Q Column address 1.6 / Dec.2 : Valid C 11h t DBSY I/Ox R/B# 85h Address (5 Cycle) Data 85h Address (2 Cycle) Data C Column address : Fixed “Low” Page address : Page M Plane address : Fixed “High” Block address : Block K Column address 1. Only the Read Status command and Reset command are valid while erasing is in progress. Block Erase The Erase operation is done on a block basis. Figure 48 details the sequence. the Read Status Register command may be entered to read the status register.13.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 47. or the Status bit (I/O 6) of the Status Register. the internal write controller handles erase and erase verify. When the erase operation is completed.

as well as operation progress can be checked like for Multiple Plane Program. as the data will be partially programmed or erased. Rev 0. Multi plane Block Erase Page address : Fixed “Low” Plane address : Fixed “Low” Block address : Block N Page address : Fixed “Low” Plane address : Fixed “High” Block address : Block M I/Ox R/B# 60h Address (3 cycle) 60h Address (3 cycle) D0h t BERS 70h Status 4. allows parallel erase of two blocks. Multiple plane erase. Block erase setup command (60h) must be repeated two times. Refer to Figure 50. program or erase mode. the command register will not accept a new reset command.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 48. executed by writing FFh to the command register. 2009 54 . Address limitation required for Multiple Plane Program applies also to multiple plane erase.14.8.6 / Dec. Multi plane erase does not need any Dummy Busy Time between first and second block address insertion. Refer to 2. each time followed by first block and second block address respectively (3 cycles each). As for block erase. When the device is in Busy state during random read. Status Register Coding for device status after reset operation.15. one per each memory plane. Multi Plane Block Erase. the reset operation will abort these operations. If the device is already in reset state. ■ Figure 49.3 I/Ox R/B# 60h Address (3 cycle) D0h t BERS 70h Status 4. Refer to the detail sequence as shown below. Block Erase Row Add 1. The contents of memory cells being altered are no longer valid. and the Status Register is cleared to value E0h when WP# is high. Reset The device offers a reset feature. The R/B# pin goes low for tRST after the Reset command is written.2. The command register is cleared to wait for the next command. D0h command makes embedded operation start.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 50.6 / Dec. 2009 55 . Reset I/Ox R/B# FFh tRST Rev 0.

This ensures that only the die selected by the 78h command responds to a data output cycle after being put in data output mode with a 00h command. The R/B# pin shows when both chip are Ready or Busy. interleaved operation is available.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 5. Block Erase. Row. Page Program. When both chip are ready state. input a command to the chip #1. Each chip status can be checked by Multi Plane Read Status Command (78h).6 / Dec. While either chip is busy. Row. Multi Plane Page Read. The host can use 78h commands to read out data from another die. Interleaved page read I/Ox 00h Address (5cycle) Chip 1 30h 00h Address (5cycle) Chip 2 30h 78h Add1 Add2 Add3 Status 00h Chip 1 Row. Rev 0. Row. R/B# pin is low. 2009 56 . When the host has issued Page Read commands to multiple die at the same time. Cache function and Copyback function are impossible for interleaved operation. Row. Multi Plane Page Program. the status register is monitored for operation completion with the Multi plane status read (78h) command. All chips are Ready state and interleaved operations are complete. 70h command is prohibited exceptionally. INTERLEAVED OPERATION Interleaving operations improve the system throughput compared to non-interleaving operations. During interleaved operations. and thus avoiding bus contention. ■ Figure 51. Data out 78h Add1 Add2 Add3 Status 00h Chip 2 Row. In Figure. the operations shall be the same type. And then. Interleaved Page Read Figure 51 shows how to perform interleaved PAGE READ operations. the host shall issue Multi plane status read (78h) command before reading data from either die. 5. The functions that may be used in the interleaved operations are Page Read.1. issue a command to the other chip. while chip #1 is busy state. Data out Chip 2 Chip 1 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) Note: 70h command is prohibited during interleaved operations. When performing interleaved operations. and Multi Plane Block Erase. In the stacked device sharing a common CE# pin. R/B# pin goes high.

1 Add. Interleaved page program I/Ox 80h Address (5cycle) Chip 1 Data Input 10h 80h Address (5cycle) Data Input 10h 78h Row Add.3.1 Row Add. Rev 0.2. 5.2 Row Add. When the host has issued Multi Plane Page Read commands to multiple die at the same time. plane 0 Chip 2 Chip 2.2 Add.3 Address (5cycle) Address (2cycle) I/Ox 60h 60h 30h 60h 60h 30h 78h Status 00h 05h E0h Data output Chip 1. This ensures that only the die selected by the 78h command responds to a data output cycle after being put in data output mode with a 00h command and 5 address cycles. the host shall issue Multi plane read status (78h) command before reading data from either die. RANDOM DATA INPUT (85h) is permitted during interleaved PROGRAM PAGE operations. plane 0 Chip 2.3 Status 80h Address (5cycle) Data Input 10h Chip 2 Chip 1 Chip 1 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) Note: 70h command is prohibited during interleaved operations. Interleaved multi plane page read A Address (3cycle) Chip 1 Address (5cycle) Chip 1 Address (3cycle) Chip 2 Address (3cycle) Chip 2 Row Add. 2009 57 .1 Chip 1 Row Add. Interleaved Page Program Figure 53 show how to perform interleaved PROGRAM PAGE operations. plane 0 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) A 00h I/Ox Address (5cycle) 05h Address (2cycle) E0h Data output 78h Row Row Row Add.2 Row Add. ■ Figure 52.6 / Dec. plane 0 Chip 1. ■ Figure 53. plane 1 Note: 70h command is prohibited during interleaved operations. and thus avoiding bus contention. plane 0 Chip 1. plane 0 Chip 1. The interleaved Multi plane page read operation must meet two-plane addressing requirements.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 5. plane 0 Chip 2. Interleaved Multi Plane Page Read Figure 52 shows how to perform interleaved Multi Plane Page Read operations using the Multi plane read status (78h) command to monitor the status register for operation completion. plane 1 Chip 2.3 Status 00h Address (5cycle) 05h Address (2cycle) E0h Data output 00h Address (5cycle) 05h Address (2cycle) E0h Data output R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) Chip 1.

2 Add. ■ Figure 54.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 5. Interleaved Block Erase Figure 55 shows how to perform interleaved Block Erase operation.6 / Dec. Interleaved multi plane page program A I/Ox R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) A I/Ox R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) 78h Row. ■ Figure 55. 2009 58 . (5cycle) Data Input 10h 80h Address. Random data input (85h) is permitted during interleaved Multi plane page program operation.5. (5cycle) Data Input 11h 81h Address. (5cycle) Data Input 11h 81h Address. Interleaved block erase Address (3cycle) Chip 1 Address (3cycle) Chip 2 Address (3cycle) Chip 1 Address (3cycle) Chip 2 I/Ox 60h D0h 60h D0h 60h D0h 60h D0h R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) Note: 70h command is prohibited during interleaved operations. The interleaved TWO-PLANE PROGRAM PAGE operation must meet two-plane addressing requirements. Status Add. Rev 0.4. Add. Row. Data Input (5cycle) 11h 81h Address. 5. (5cycle) Data Input 10h Chip 1 Chip 1 Chip 2 Chip 2 80h Address.3 80h Address. Interleaved Multi Plane Page Program Figure 54 shows how to perform interleaved Multi Plane Page Program operations.1 Row. (5cycle) Data Input 10h Chip 1 Chip 1 Chip 1 Note: 70h command is prohibited during interleaved operations.

Interleaved multi plane block erase Address (3cycle) Address (3cycle) Address (3cycle) Address (3cycle) Row. Row. This operation must meet two-plane addressing requirements. ■ Figure 56. Add. 2009 59 . Rev 0.6 / Dec.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 5.6. Interleaved Multi Plane Block Erase Figure 56 shows how to perform two types of interleaved Multi Plane Block Erase operations. Add 1. Add 2. 3 Address (3cycle) Address (3cycle) I/Ox 60h 60h D0h 60h 60h D0h 78h Status 60h 60h D0h Chip 1 Chip 1 Chip 2 Chip 2 Chip 1 Chip 1 Chip 1 R/B# (chip 1 internal) R/B# (chip 2 internal) R/B# (external) Note: 70h command is prohibited during interleaved operations. Row.

OTHER FEATURES 6.7V 0V tCS CE# WP# CLE WE# ALE RE# I/Ox R/B# 1 ms (max) 10 (max) 50 (min) Vcc ramp starts FFh 2 ms (max) : Don’t care : Undefined Rev 0. Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VCC is below about 2.3V device).Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 6. The reset command (FFh) must be issued to all dies as the first command after device is power up. In this time. ■ Figure 57.1. 2009 60 . Data protection and power on / off 3V device = 2.6 / Dec.7V VCC 2. Each R/B# will be busy for maximum of 2ms after reset command is issued. WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. the acceptable command is 70h or 78h.0V (3.

4V VOL tf Busy tr VOH GND Device Fig. The R/B# pin is normally high and goes to low when the device is busy (after a reset. read.) .2 189 1. Ta = 25°C. tf [s] 200n 100n 96 4. CL=50pF 3.2 4. Ready / Busy The device has a Ready/Busy output that provides method of indicating the completion of a page program.1 0.VOL (Max. It returns to high when the internal controller has finished the operation. tf & Rp vs ibusy @ Vcc = 3. The pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied.65 290 3m 61 .825 2m 1m tf 4. and erase operation). Its value can be determined by the following guidance. VOH : 2. ■ Figure 58.6 / Dec. Ready / Busy Vcc Rp ibusy Ready Vcc R/B# open drain output VOL : 0.4V. Rp vs tr.3 381 tr. an appropriate value can be obtained with the following reference chart (Figure 58). copy-back and random read completion.2. erase. Because pull-up resistor value is related to tR (R/B#) and current drain during busy (Ibusy). program.2 1k 2k 3k Rp (ohm) 4k Rp value guidence Rp (min) = Vcc (Max.2V L where IL is the sum of the input current of all devices tied to the R/B# pin.3V.2 4. 2009 ibusy [A] 300n ibusy 1.) IOL + L = 3. Rp(max) is determined by maximum permissible limit of tr Rev 0.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 6.

Enable Erasing Figure 62. min). Enable Programming Figure 60. Disable Programming WE# t WW I/Ox WP# R/B# WE# t WW 60h D0h I/Ox WP# R/B# 60h D0h Figure 61. Disable Erasing Rev 0. Write Protect Operation The Erase and Program Operations are automatically reset when WP# goes Low (tWW = 100ns. WE# WE# t WW I/Ox t WW 80h 10h I/Ox WP# 80h 10h WP# R/B# R/B# Figure 59. The operations are enabled and disabled as follows (Figure 59 ~ 62).6 / Dec.3. 2009 62 .Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 6.

Paired Page Address Information Paired page address 0 2 6 A E 12 16 1A 1E 22 26 2A 2E 32 36 3A 3E 42 46 4A 4E 52 56 5A 5E 62 66 6A 6E 72 76 7A 7E 82 86 8A 8E 92 Rev 0.1.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 7. 2009 Paired page address 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C 80 84 88 8C 90 94 98 1 3 7 B F 13 17 1B 1F 23 27 2B 2F 33 37 3B 3F 43 47 4B 4F 53 57 5B 5F 63 67 6B 6F 73 77 7B 7F 83 87 8B 8F 93 5 9 D 11 15 19 1D 21 25 29 2D 31 35 39 3D 41 45 49 4D 51 55 59 5D 61 65 69 6D 71 75 79 7D 81 85 89 8D 91 95 99 63 .6 / Dec. Application Notes and Comments 7.

Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 96 9A 9E A2 A6 AA AE B2 B6 BA BE C2 C6 CA CE D2 D6 DA DE E2 E6 EA EE F2 F6 FA 9C A0 A4 A8 AC B0 B4 B8 BC C0 C4 C8 CC D0 D4 D8 DC E0 E4 E8 EC F0 F4 F8 FC FE 97 9B 9F A3 A7 AB AF B3 B7 BB BF C3 C7 CB CF D3 D7 DB DF E3 E7 EB EF F3 F7 FB 9D A1 A5 A9 AD B1 B5 B9 BD C1 C5 C9 CD D1 D5 D9 DD E1 E5 E9 ED F1 F5 F9 FD FF When program operation is abnormally aborted (ex. not only page data under program but also a coupled row paired page data may be damaged. Rev 0. power-down. reset). For example. during Page Program operation of page address 05h is aborted by reset or power down. 2009 64 .6 / Dec. the data of 00h. and 05h page address may be spoiled. 01h. 04h.

3. Extra Block Description Device includes extra features like user OTP. Unique ID can be programmed only once and cannot be erased. 7. User OTP. and FFh are available between 11h-81h. the pass/fail output information of 70h and 78h is not valid.5. the program operation cannot be executed. Acceptable Command between Start command and Confirm command Only Reset Command is available between start commands and confirm commands set (start command-address-confirm command style) that is mentioned in 1. If other command is inputted. To exit extra features.2. 07h or FFh command can be used. 11h.6 / Dec. only 70h. it is impossible to perform a normal Page Read operation. but user block address does not care internally. The user OTP used one block which locates the second block of plane 0 (address<32:22> = 0002h).Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash 7.30h). 78h. Do not input any commands except FFh. For instance. 7. Unique ID block has 64 pages.5 address cycle . only ready / busy (I/O6 and I/O5) state can be checked.7 Command Set. do not input any command except 85h. Physically. Unique ID and Read ID2. ReadID2 area exists in plane1. Read ID2 can be only read. 2009 65 . the operation cannot be executed. the size is one page. address<21:14> = 00h ~ 3Fh). Restriction of Read Status Value in Multi Plane Operation During Multi plane operation.4. if any command is inputted between Page Read Command Set (00h . But. Rev 0. 10h. locates the first block of plane 0 and the first 64 pages of the block (address<32:22> = 0000h. 15h. 7. Acceptable Command after 80h After Program Start Command (80h) is inputted. If a command is inputted except these commands. Refer to Figure 63. and FFh. During this time.

2009 66 . address and data is necessary. Otherwise. Restriction read status in multi plane operation I/O6 => I/O5 => I/O1 => I/O0 => I/Ox R/B# 80h Address Data 11h 70h Valid Invalid Invalid Invalid SR out 81h Address Data 10h Valid Invalid Invalid Invalid 70h SR out 70h Valid Invalid Invalid Valid SR out tDBSY tPROG IO 0 = 0. do not input bad block address to all Multi Plane Operation. do not attempt to program the page address N in another block without the data input sequence.6 / Dec.6. 7. The same input sequence of 80h command. Fail 7. Page Program Failure If the Page Program operation for page address N is fail. remain data in data register may be different to input data by host.7. the input data of valid block could be lost and the operation could be abnormally stopped.Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash ■ Figure 63. Therefore. Restriction Multi Plane Operation To prevent abnormal multi plane operation. Pass IO 0 = 1. Rev 0.

VLGA/TSOP1 K H 2 7 U B G 8 T 2 A x y x w w O x x R x x .7 V~ 3. I (-40 ~85 x : Operating Temperature : C(0 . 2009 : Fixed Item : Non-fixed Item 67 .6 V) : 32 Gibit : 8 (X8) : Multi Level Cell + Single Die + Large Block : 2(1nCE & 1R/nB.hynix .xx : Process Code Note .y : Year (ex: 9 = year 2009. Y(52-LGA) : Blank(Normal). P(All Good Block) ~70 ).Preliminary H27UBG8T2A Series 32Gb (4096M x 8bit) NAND Flash MARKING INFORMATION .ww : Work Week (ex:12 = work week 12) .H27UBG8T2Axx-xx H : Hynix 27 : NAND Flash U : Power Supply BG : Density 8 : Bit Organiztion T : Classification 2 : Mode A : Version x : Package Type x : Package Material x : Bad Block : Hynix Symbol : Origin Country : Part Number : U (2. S(1~5 Bad Block). 0 = year 2010) .Capital Letter . R(Lead & Halogen Free) : B(Included Bad Block).6 / Dec.Small Letter Rev 0. Sequential Row Read Disable) : 2nd Generation : T(48-TSOP1).KOR .

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