Soft-Commutated Cuk and SEPIC Converters as Power Factor Preregulators

J. A. Pomilio* and G. Spiazzi**
*Faculty of Electrical Engineering, State University of Campinas1 C.P. 6101, 13081-970 Campinas, Brazil; Tel: +55.192.393911 Fax: +55.192.391395 **Dept. of Electronics and Informatics, University of Padova Via Gradenigo 6/a, 35131 Padova, Italy; Tel: +39.49.8287517 Fax: +39.49.8287699 Abstract1: Cuk and SEPIC converters operating in Discontinuous Current Mode (DCM), used as Power Factor Preregulators (PFP), present some advantages over other topologies: sinusoidal current shaping using constant frequency and duty-cycle, low input current harmonic content, low input filter requirements, isolation between line and load, etc. The main drawbacks are the voltage and current stresses that devices are submitted to. In this paper, an auxiliary circuit is proposed which limits the overvoltage on the main switch and allows its zero-voltage turn off. Zero-current turn on is provided by the DCM operation. In this way switch commutations are soft, thus improving efficiency and reducing RF noise. Design criteria and experimental results are reported. INTRODUCTION Recently, power converters with high power factor and sinusoidal input current have gained considerable attention, due to international standards regarding the line pollution. Various topologies can be used to perform this task, the most diffused being the boost one. When output isolation is required as well as over-current and start-up protection, Cuk and SEPIC converters are good solutions. Moreover, when operating in Discontinuous Current Mode (DCM) [1-3], they offer other advantages: low harmonic input current without filtering, operation at constant frequency and duty-cycle, no need of current loop, soft turn-on of the main switch. The main drawbacks are the high current and voltage stresses on the switches. Voltage stresses can be further worsened by the effects of transformer leakage inductance, calling for devices with high-voltage capability. IGBTs can be used, which have less forward voltage drop and are cheaper than MOSFETs. But, because of the turn-off tail current, higher commutation losses can be expected, which limit the switching frequency. In [4], a lossless clamper circuit was used in order to limit the overvoltage due to the transformer leakage inductance. Here, an improved auxiliary circuit is presented, which allows zero-voltage turn-off of the transistor. This means that all commutations are soft, including that of the switches in the auxiliary circuit. The use of soft-switching techniques also limits the RF noise generated, which is a non negligible aspect in preregulators [5]. (b) Figure 1. Cuk (a) and SEPIC (b) converters as Power Factor Preregulators CUK AND SEPIC CONVERTERS AS POWER FACTOR PREREGULATORS In the following analysis, a switching frequency much higher than the line frequency is considered, so that the averaged signals over a switching period T can be considered in place of the istantaneous quantities, according to the time-averaging approach. Also, only DCM operation is considered. Cuk converter The converter shown in figure 1.a is the insulated version of the Cuk converter driven by a rectified sinusoidal voltage vg. All the converter components are rated on the switching frequency basis, except the output capacitor Co which must be big enough to filter the low frequency ripple, at twice the line frequency, caused by the input power variation when operating as PFP [1]. The capacitor voltages are: (1) v a (θ) = v g ( θ) = v i = Vi ⋅ sin( θ) , θ = ωi t

+ v L1 -

Ca i L1 + va S








L2 i L2 D Co RL VL +


L1 i L1 vi ii vg

(a) Ca
+ v a-


i L2 L2



+ VL -

Vb = VL


1J. A. Pomilio is doing a post-doctoral research at the University of Padova with a fellowship from the Fundação de Amparo à Pesquisa do Estado de São Paulo, Brazil

When operating in DCM, the current waveforms of both inductors look as shown in figure 2 [6]. The circuit behavior is as follows: when the switch is turned on, the freewheeling diode is reverse biased and the currents rise linearly (assuming small

6]: ic is - iLc Sc + vc - Cc Auxiliary Circuit i0 (a) L 1 i L1 + vi Sc Dc2 VL Vi 2 ⋅ Le Ke ≡ RL ⋅T M≡ δ = M ⋅ 2K e Voltage conversion ratio (5) Ci Ca +v a D c1 Lc Ld i L2 L2 D N:1 C o RL + V L - (6) The converter duty-cycle is given by: (7) S is - v s ic iLc + vc - Cc io which shows that. the converter parameters must satisfy the following inequality: Auxiliary Circuit (b) Figure 3. the voltage conversion ratio M depends on the load. After that. otherwise the converter operation changes: . The freewheeling diode D is off. At instant t0. the average input current is proportional to the input voltage. current iL1 cannot go negative for the presence of the diode bridge. it is important to note that current I' must be greater than zero. with the difference that the current iL2 is not affected by the transformer turns-ratio. Once the value of equivalent inductance Le is known. Cuk (a) and SEPIC (b) converters with auxiliary circuit for soft-commutation Ke < N2 2 ⋅ ( M ⋅ N + 1) 2 (8) Auxiliary circuit behavior Figure 4 shows the simulated converter waveforms during one switching period.high-frequency voltage ripple across capacitors). like any other converter operating in DCM. ensuring unity power factor. both switches are turned on under zero-current condition. both inductor currents decrease until their sum becomes zero. for constant switching frequency and duty-cycle. the input inductance L1 is obtained as follows: L1 = 2 Le δ ri (9) With reference to figure 2. During turn-off interval. that is: L1 > L2 ⋅ N M (10) i L1 (θ) = v g ( θ) ⋅ δ2 ⋅ T 2 ⋅ Le (3) SEPIC Converter For this converter. Let us define the following adimensional parameters [1. the voltage on Cc is equal to the reflected output voltage plus the overvoltage caused by the transformer leakage inductance. Inductor voltages and currents in DCM for the Cuk converter Limits for DCM operation.3. when the current in the primary side reverses. The same driving signal is applied to both switches. v L1 . they remain constant for the rest of the switching period. Figure 3 shows Cuk and SEPIC converters with the proposed auxiliary circuit. At the end of toff interval.i b L2 D Co V R L + L Figure 2. L 1 Ca i L1 + v i C i S vs D c2 Lc +v a D c1 Cb L2 i L2 -N I' S δ D δ* T Ld N:1 +V . whose scheme is reported in figure 1. This latter constrain imposes a minimum value for L1. and (10) which become respectively: where T is the switching period and Le = N 2 ⋅ L1 ⋅ L 2 L1 + N 2 ⋅ L 2 (4) This relation shows that. which allows zero-voltage turn-off of the main switch while limiting its overvoltage. the analysis is analogous to the Cuk one. The average input current is given by [2]: in fact. v L2 N vg 0 L1 ⋅ L 2 L1 + L 2 L2 L1 > M⋅N Le = (11) (12) AUXILIARY CIRCUIT FOR SOFT TURN-OFF -N V L i L1 I' 0 ∆i In the above PFPs the insulation transformer causes severe voltage spikes and ringing due to its leakage inductance. In order to ensure the DCM operation in all conditions. The equations are the same except (4).b. causing the freewheeling diode turn off. from the desired relative input current ripple ri (peak to peak).

flowing almost entirely through Sc. Voltage vc increases above the reflected output voltage in a resonant manner due to the oscillation between Ld and Cc. in which this situation occurs. The corresponding overvoltage depends on the inductor current value and the characteristic impedance of the resonant circuit. output diode turn on is delayed (interval t3-t4). and decreases linearly to zero (instant t2) with a slope equal to -va/Lc. can be estimated as: vc -V a iL1 V ˆ Vc = NVL + i δT ⋅ Z d Le Accordingly. the switch voltage stress is: (13) is ic (14) It is important to note that. diode Dc1 stops conduction and current iL1 flows through the transformer until the current in the freewheeling diode becomes zero (operation in discontinuous mode). Interval t5-t6. Knowing the voltage Vcmax(θ) across Cc before the switch turn-on.V +V cmax a N V +V L a Va V cmax vs Capacitor Cc The value of this capacitor is chosen considering the allowed switch voltage stress. The voltage reflected to the primary becomes zero and the voltage across the main switch drops to va. taking into account the effect of transformer leakage inductance. Thus. The inductor current iLc divides between Ca and Cc. Interval t6-T. When vc equals the output voltage reflected to the primary side. The equivalent circuit during interval t3-t4 is shown in figure 5. S. and the auxiliary one under zero-current condition. The maximum voltage across Cc. Equivalent circuit at turn off (interval t3-t4) The initial conditions are: . so no resonance occurs between the transformer leakage inductance and Cc (the output diode does not enter conduction). Cc and Lc resonate until the voltage across Cc reaches -va. Converter and auxiliary circuit waveforms during a switching period Interval t0-t1. Inductor Lc Inductance Lc is a critical parameter because it must be chosen in order to allow zeroing of its current during the minimum switches on time. Interval t4-t5. since both iL1 and iL2 are low.C c Le ie Cc + vc - . interval ta is given by: ˆ ˆ VS ≅ Vi + Vc iLc ta t0 t1 tb t2 t3 t4 t5 t6 T Figure 4. its voltage reaches the value -va and Dc1 starts conducting. and is given by: I o (θ) = v g (θ) Vc max (θ) ⋅ sin (ω c t 1 ) = ⋅ γ (θ)2 − 1 Zc Zc (19) As we can see. Zd = Ld Cc Lc . we must find the interval. in order to find the maximum value of interval ta+tb. we can write: tb = L c ⋅ I o (θ) v g ( θ) (18) where Io(θ) is the value of current iLc in the instant t1. Zc = Figure 5. The current flows through Dc1 to recharge capacitor Cc. but an approximate worst-case result can be obtained. ωe = Cc 1 L e . As the current during this small interval is almost constant. we must know the behavior of voltage Vcmax(θ). Interval t1-t3. Dc2. the main switch is turned off under zero-voltage condition. Capacitor Cc starts resonance with inductor Lc. At t3. The duration of this interval is one fourth of the resonant period. D starts to conduct (instant t4). let us define the following parameters: ta = where 1  1  ⋅ arcos  ωc  γ (θ) Vc max (θ) v g (θ) (16) γ (θ) = (17) At t1. This phenomenon does not affect the converter behavior as power factor preregulator but imposes an upper limit for the value of Cc. On the contrary. At t5. there is not enough energy to charge Cc to the value NVL. ωd = ωc = 1 Ld Cc 1 Lc Cc . Interval t3-t4. Thus.e. The output diode opens at zero current. Note that the auxiliary circuit does not cause increased voltage or current stresses in the main switch. during the line period. due to the charging process of Cc. For this purpose note that near the line voltage zero crossing. the total current carried by the main switch is lowered. At instant t1. i. SELECTION OF AUXILIARY CIRCUIT PARAMETERS Before to go into detail. the voltage varies linearly. The delay increases at light load and near the input voltage zero-crossing. with reference to figure 4: (15) ta + t b < δ ⋅ T It is not possible to obtain an exact analytical expression for this inductance. Ca and Dc1 (Ca>>Cc). This means an effective increase in the duty-cycle "seen" by the output. current iLc starts to decrease almost linearly to zero under the action of voltage va. During interval ta.

So. DESIGN PROCEDURE In the converter design procedure. versus input voltage angle. the typical variation of interval ta+tb. As far output capacitor is concerned. Vcmax N VL θ 1 θ θ2 In the following. there must be a lower limit for the duty-cycle in order to meet condition (15). with the condition θ=θ1. calculate L1 from (9). Taking the equality from (25). vc is maximum and is given by: Vc max (θ) ≅ N VL + v g (θ) Le δT ⋅ Z d (22) Figure 6 shows typical behavior of voltage Vcmax.relative input current ripple ri Power stage design N ⋅ VL   θ1 = arcsin    Vi ⋅ [δ ⋅ T ⋅ ω e ⋅ sin (α) − cos(α)] (21) For θ1<θ<π-θ1. the following input data are considered: .maximum and minimum load resistance RLmax.switching frequency f=1/T  .maximum switch voltage VS . calculate M from (5). If it is not satisfied.i e ( 0) = v g ( θ) Le ⋅ δT . normalized to the duty-cycle. we can find the required transformer turns ratio N. calculate Le from (6). find the value of Ke from (7) using the minimum load resistance and verify condition (8). RLmin . From the relation Vc MAX (θ1 ) = N VL   1   2 C c ⋅ arcos −  + γ (θ1 ) − 1  γ (θ1 )     2 (23) we find the value of angle θ1 below which Vcmax(θ) is given by (20): Note that.e. Figure 6. Note however. the freewheeling diode D starts conduction during the toff interval allowing resonance between Ld and Cc to occur. considering that the most critical situation occurs at angle θ1 and. from (20) the condition (24) is satisfied if: (26) δT ωe ⋅ sin( α) − cos(α) ≥ 1 This condition must be verified once capacitor Cc has been chosen. thus the minimum value of δ must be used in (23). 1) 2) 3) 4) Choose a suitable maximum value for the duty-cycle δmax. is shown in figure 7. normalized to the reflected output voltage.output voltage VL . a lower input current ripple must be considered. given the desired relative voltage ripple rv (peak to peak). Note that the worst case occurs just after θ1 (or before π-θ1). calculate L2 from (4). Using these results. at this point. we can write: . there is the total overvoltage across Cc. check condition (12). if it is not satisfied. the detailed power stage design procedure is outlined using the results derived in the previous paragraphs. Typical variation of interval ta+tb Capacitor Ca and Cb are selected taking into account the desired high frequency voltage ripple.peak input voltage Vi . i. At higher angles. a different value for δmax must be chosen. it must be rated at line frequency instead of switching frequency. since the overshoot is interrupted by the end of turn-off period (interval t4-t5 is less then one forth of resonant period). v c (0) = − v g ( θ) (20) Voltage vc reaches its maximum when ie zeroes: Thus. using (15÷19) and (22). Zero-Voltage turn-off condition From the analysis of the auxiliary circuit it is clear that the zero-voltage turn-off condition requires a voltage across Cc always greater than Va. This fact suggests a method for estimating Lc. that for angles θ slightly greater than θ1 the overvoltage on Cc is not maximum. calculate N taking the equality in (25). Typical variation of peak voltage across Cc ta+tb dT 5) 6) 7) 8) θ1 θ π−θ1 Figure 7. knowing Ke. the maximum value for the inductance Lc can be approximated by: Vc max (θ) = v g ( θ) ⋅ [δT ω e ⋅ sin (α) − cos(α)] Lc ≅ δ2 ⋅ T 2 where α = π + arctg( − δT ω e ) .: (24) Vc MAX ≥ v a (θ) = v g ( θ) For θ1<θ<π−θ1 a sufficient condition is that reflected output voltage is higher than maximum input voltage: (25) N ⋅ VL ≥ Vi For θ<θ1 and θ>π−θ1.

the choice of auxiliary circuit parameters can be summarized as follows: 1) from the maximum voltage stress allowed on the switch and (1314). They weight substantially on the converter efficiency.: 4 ms/div Auxiliary circuit design From the above considerations. f = 50kHz (T=20µs)  VS =800V Input current ripple: 30% Following the design procedure outlined above. The distortion in the current near the zero crossing is due to the limitation imposed by the inductance L1.Co = 1 ω i rv R L min (27) Figure 8. EXPERIMENTAL RESULTS A 250W converter prototype was built according to the following specifications: Vi = 120⋅√2 V VL = 50 V RLmax = 62. higher efficiency can be expected at higher power rating ii vi . Rectifier input current (2A/div. RLmin = 10 Ω. The zero-current turn-on and zero-voltage turn-off are clear. As the inductance is relatively high. 300 mA 30 mA 3 mA Figure 9.5 (Po = 250W) Minimum duty-cycle: δ = 0. the measured value is 0.2 µH Lc = 30 µH Ca = 500 nF Cb = 50 µF Co = 1000 µF Cc = 20 nF Figure 8 shows line current and voltage. 3) calculate θ1 from (21) at minimum duty-cycle. Figure 10 shows the behavior of the auxiliary circuit. 2) calculate the minimum duty-cycle in correspondence of maximum load resistance from (7). iC 0 vC 0 Figure 10. Note that the charge process happens at constant current and the inversion of the voltage obey a sinusoidal variation. 4) find the value of parameter γ(θ1) from (17) and (22). The expected ripple of 30% is got.: 4 µs/div Figure 11 shows the main switch current and voltage waveforms. The measured power factor at minimum load is 0. Horiz. At full power. The IGBT current tail is present and the use of zero-voltage turn-off contributes to reduce the losses [7].2 (Po = 40W) L1 = 1.9 mH L2 = 6. calculate the value of capacitance Cc and verify inequality (26). Filtered line current (2A/div) and voltage (100V/div) Horiz. the converter parameters are: Transformer turns ratio: 5:1 Measured transformer leakage inductance: Ld = 13µH.5 Ω. Figure 13 reports the calculated converter losses at nominal power: as we can see. Figure 12 shows the variation of the efficiency and power factor. 2ms/div)) and its spectrum (25 kHz/div) The next waveforms were taken at the peak of the input voltage. Nominal duty-cycle: δ = 0. Thus. but it is important to note that they are not proportional to output power. at low input voltage the current rate of change is limited. which increase the resistive losses. the auxiliary circuit losses are 24% of total ones. Figure 9 displays the rectifier input current showing its highfrequency components. The spectrum shows the high-frequency harmonics.99 at nominal load. The efficiency is relatively low specially because the high RMS currents present in the secondary side.99. 5) calculate the value of inductance Lc from (23) using the minimum duty-cycle. so that they represent the instantaneous highest values of voltage and current through the devices.98 and higher than 0. Capacitor Cc current (5 A/div) and voltage (200 V/div). Nevertheless a high power factor is obtained.

Spain. Washington. Simonetti.9 0. Malesani. J. of PESC '78. Gil and J.7 0. Jun. Proc. of PESC '92. In spite of some lowfrequency distortion in the line current. 463-468 [5] P. Gu: "Comparison of EMI Performance of PWM and Resonant Power Converters". Tenti: "Three-phase Power Factor Controller with Minimum Output Voltage Distortion". Spain. of PESC '93. Toledo.S. Keller and R. June 1993. the power factor is next to unity and the current harmonics are small. 19-25 Figure 13. Proc. Uceda: "Design Criteria for Sepic and Cuk Converters as Power Factor Preregulators in Discontinuous Conduction Mode".S. of IECON '92. June 1978. Cuk: "Input Current Shaper Using Cuk Converter". pp.: 4µs/div 1 0. dos Reis and J. of INTELEC '93. Caldeira. Efficiency 200 250 20% 9% 30% 15% 26% P-active (aux) P-passive (aux) P-transformer P-active P-passive [1] D. pp. Cobos. F. G. Sebastián. 134-140 [6] S. June 29 to July 3. R. Proc. 1993. 1992. Proc. Proc. pp. Seatle. pp. Dalal and W.iS CONCLUSIONS The use of the proposed auxiliary circuit. Paris. 532-539 [3] J. D. of PESC '92. Syracuse. of INTELEC '92. 283-288 [2] M. USA. Sommer: "Behavior of IGBT Modules in Zero-Voltage-Switch Applications". USA. output power. 105-123 [7] K. Oct. Brkovic and S. Sebastian. Ch. Proc.F. Rossetto. REFERENCES 0 vs 0 Figure 11. Sept.6 50 100 150 Output Power (W) Figure 12. Toledo. Converter losses distribution . Liu. allows a full soft-commutation converter. 1992. Proc. Uceda: "The Determination of the Boundaries Between Continuous and Discontinuous Conduction Modes in PWM DC-to-DC Converters Used as Power Factor PreRegulators".8 P. P. J. USA. France. maintaining a reasonably high efficiency. Converter efficiency and power factor vs. besides limiting the overvoltage. 1992. pp. A higher switching frequency is therefore possible also with IGBTs. Cuk: "Discontinuous Inductor Current Mode in the Optimum Topology Switching Converter". pp.L. Main switch current (5 A/div) and voltage (200 V/div) Horiz.A. pp.1061-1070 [4] L. J. L. 0. Spiazzi and P. Heumann.