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EE1.3 An introduction to semiconductor devices
Dr. K. Fobelets
1. History
Figure 1: 12AX7 vacuum tubes glow inside a modern guitar amplifier. Picture taken from
http://en.wikipedia.org/wiki/Image:Tubes.jpg by Chris Roddy.
Around 1904, the first computers were built using vacuum tube technology. They were bulky and didn’t come cheap.
Figure 1 shows 3 vacuum tubes in operation, they resemble incandescent light bulbs. In vacuum, electrons – small
negatively.charged particles – are created by thermionic emission (with enough heat energy, electrons can escape from
a metal – the cathode – into vacuum and be accelerated towards another contact – the anode – via an electrostatic
potential difference). The flow of electrons creates a current that is dependent on the voltage applied. This vacuum tube,
with only two contacts is called a diode. It allowed electrical current to flow in only one potential direction and thus it
behaved as a rectifier. No independent control could be exercised on the amount of electrons and thus the magnitude of
the current flowing. In 1908 an extra metal grid was introduced in the structure on which a voltage could be applied.
This voltage – a lot smaller than the anode voltage – could control the amount of electrons flowing from the cathode. As
thus, a system was created where a relatively small voltage could control the current flowing between two other
contacts  the amplifier was born.
Figure 2: Left: a picture of the first contact transistor (1947) and right: a colour enhanced SEM (secondary electron
microscope) cross section of an SOI (SilicononInsulator) chip (dielectric insulation removed) from IBM, showing 3
tiny transistors with their metal interconnections. Taken from:
http://sinclair.ece.uci.edu/Useful%20educational%20pictures/
Then in 1947, Brattain, Bardeen and Shockley at the Bell telephone Laboratories discovered something revolutionary in
the lab: amplification was demonstrated using two Au wires on a block of a semiconductor called germanium (Ge) – the
2
first solid state amplifier was invented! That this didn’t happen overnight can be read in e.g. Miracle Month on web
page: [http://www.pbs.org/transistor/background1/events/miraclemo.html]. Although a lot smaller than a vacuum tube
and operating at lower voltage and current levels, the picture of the first semiconductor transistor in figure 2 (left)
directly illuminates why this didn’t lead immediately to a microprocessor (Fig.2 right). A large amount of research on
the physics behind the operation of semiconductor devices and into fabrication techniques and tools had to be done
before the era of integrated circuits started in 1971. Figure 3 gives an idea of the time it has taken research and industry
to get to were we are today in the world of semiconductor technology.
Figure 3: A timeline on semiconductor research showing that it took more than 20 years of research to get from a
device concept to an integrated circuit.
The invention of the transistor was a major event that changed the course of history for electronics, where now
technology is pushed forward based on the requirements of computers (and computer games!). The first generation of
computers used vacuum tubes; the second generation of computers used a connection between discrete transistors and
passive components
1
(similar to the circuit you will built for the EE1 radio project at the end of the academic year); the
third generation of computers used integrated circuits; and the fourth generation of computers uses microprocessors.
The aim of this course is not to find out how to build the circuits (that is taught in the Analysis of Circuits and the
Analogue Electronics course), but it is to find out how the basic components of the circuits – the semiconductor devices
– work and what can be done to make them better (faster, smaller and operating at reduced power levels).
2. Why study semiconductor devices?
Present day devices are no longer just diodes or transistors, but are either large scale integrated circuits or special
purpose components whose design and performance are intimately connected with their physics and processing. For the
future engineer it is no longer enough to study the terminal electrical characteristics of the semiconductor device while
treating the device itself as a “black box”. Most of the sophistication of modern electronics is hidden in that box, and
more and more engineering and scientific effort will be required in device development, design, simulation, production
and testing in the future. The devices in fact become subsystems, ready for use for the system engineer. Even he, the
user of the devices, will not be able to get the most out of them or contribute towards design of more advanced devices
and systems without a good knowledge of the principles underlying their operation and the technology used in
manufacturing them.
This course therefore aims to give you the basic knowledge to understand simple semiconductor devices and to give
you a background that will enable you to understand more complicated structures.
1
Such as resistors, capacitor and inductors
Timeline
1930 1940 1960 1950 1970 2000
1928: Lilienfield – FET patent
1948: Shockley, Bardeen, Brattain –
BJT
1960: Kahng, Atalla – Si MOSFET
1962: Wanlass, Sah, Moore – CMOS
1964: Fairchild / RCA – 1
st
commercial
MOSFETs
1968: Noyce & Moore found Intel
1971: 1
st
microprocessor,
intel4004
2000: Nobel Prize for Physics
Jack S. Kilby – integrated circuit
Z. I. Alferov, H. Kroemer –
semiconductor heterostructures
3
3. The course aims
(1) To give insight into the structure of semiconductors
(2) To give insight into the physics of semiconductor diodes and transistors.
(3) To give models of device behaviour that can be used as a basis for understanding the functioning of other/new
semiconductor devices.
(4) To give insight into the fabrication methods of diodes and transistors.
4. Objectives
At the end of the course students should be able to:
(1) Discuss the characteristics of semiconductors, in particular Si, that make the material suitable for electronic devices
(2) Explain qualitatively the mechanisms of electronic conduction in semiconductors, and calculate relevant quantities
from given data.
(3) Calculate and explain the DC currentvoltage behaviour of diodes and transistors, given their geometry and material
properties.
(4) Explain the fabrication of simple diodes and transistors.
5. Recommended textbooks
As these course notes are summary notes, summarising the most important issues, the students are strongly
recommended to consult/buy one of the following books:
"Microelectronic Devices", K.D. Leaver, IC Press, 2nd ed.
(This book is written by the former lecturer of this course. The advantage of this book is that it focuses only on those
topics discussed in the first and second year devices course in the Electrical and Electronic Engineering Department and
that it is affordable. It is well worth buying as there is, in general, a rush on these books in the library near the end of the
year.)
"Solid State Electronic Devices", B.G. Streetman, Prentice Hall International Editions, 4th ed.
(Much of what will be discussed in the course is based on this book. It gives both mathematical as well as more intuitive
interpretations of the functioning of the devices discussed in the course. The advantage of this book is that it is closely
linked to the course contents but it contains much more info that is taught in the course. There should be an ample
supply of this book in the central library, but it is well worth buying if you have genuine interest in the topic. The first
chapters might also be helpful for a part of the Engineering materials course.)
6. Course synopsis
Introduction into semiconductor materials
A semiconductor is a material with a conductivity level between metals and insulators. Unlike metals, the charges in the
semiconductor are more tightly bound to the atoms and although some of these charges travel around in the
semiconductor, they are only quasifree as they feel the continuous influence of the surrounding lattice (atoms).
Semiconductors’ strength is based on the existence of 2 types of moving charges: negatively charged electrons and
positively charged holes. The energetic state of the charges is described using an “energy band model” which is based
on sound quantummechanical calculations but which will be introduced in a more informal way in this course. The
energy band diagram with its associated bandgap and position of the Fermi level will form the basis of understanding
the operation of semiconductor devices.
Two different types of currents, drift and diffusion, can occur in a semiconductor. Although these currents normally
occur at the same time in “real” devices, in this course we take the liberty to make approximations such that only one of
them will occur at any one time. The reasoning behind the approximations is based on the concept of majority and
minority carriers.
The MOS capacitor and MOSFET
Semiconductors become devices the moment they are combined with other types of semiconductors or metals. A
semiconductor with two metal contacts becomes a resistor or a Schottky diode depending on the material characteristics
of both the semiconductor and the metal. We will look into this kind of metalsemiconductor junctions.
Although in traditional textbooks it is common to start with discussing the functioning of a pndiode, in this course we
will first focus on what is called majority carrier devices – devices where only one type of carriers play an important
role in its operation. A metaloxidesemiconductor (MOS) contact can be used as a capacitor in integrated circuits but is
also used in MOS Field Effect Transistors (MOSFETs) to control the conduction in the channel without injecting
carriers. We will study the functioning of this device using energy band diagrams and investigate the parameters that
influence the operation of this device.
4
The pn junction and BJT
Diodes can be made from pn junctions – thus the same material but different doping types at each side. This is a device
where both majority and minority carriers play an important role. The current is governed by diffusion of minority
carriers rather than by drift of majority carriers as was the case in the MOSFET. We will explore the reason for the
rectifying behaviour of these pndiodes.
A more complicated npn or pnp junction is the basis for the bipolar junction transistor (BJT). Based on our knowledge
of pn junctions, the functioning of a BJT will be described. We will find out how current gain exist in this device and we
will find out why BJTs are used in highspeed analogue applications whilst MOSFETs govern the digital world.
7. Contents of the lecture notes
Chapter 1: Semiconductors and their characteristics
Chapter 2: Semiconductor junctions
Chapter 3: The MetalOxideSemiconductor Field Effect Transistor – MOSFET
Chapter 4: The Bipolar Junction Transistor – BJT
5
Chapter 1: Semiconductors and their characteristics
In this chapter we will explain what a semiconductor is and why these materials are interesting for the electronics
industry. The reader should be aware that the comprehensive explanation of the physics behind transport in
semiconductor devices is based on quantum mechanical calculations and statistics. In this lecture we will introduce
some quantum mechanical concepts using intuitive explanations rather than employing the full mathematical approach
in order to simplify the physics whilst still delivering the background to understand semiconductor devices. A slightly
deeper insight into the quantum mechanical background will be given in the course: EE1.5 Engineering Materials by Dr.
W.T. Pike
2
in the spring term.
1. Introduction
A semiconductor belongs to the group of materials called solids. A solid consist of atoms bonded together by coulomb
attraction. Each atom consist of a nucleus built from neutrons (no charge) and protons (positively charged), surrounded
by negatively charged electrons of which the amount is equal to the amount of protons in the nucleus. Thus the bonding
of two atoms is caused by the electrostatic force between the nucleus of one atom and the surrounding electrons of the
other atoms and vice verse. The Coulomb force, F between the charges is given by:
2
2 1
0
4
1
r
q q
F
πε
=
With q
i
(i=1,2) the 2 charges involved in the attraction or repulsion, r the distance between the charges and ε
0
the
permittivity of free space: ε
0
.= 8.854 10
12
F/m.
Bonding begins at a certain distance between the two atoms – the bond length (lattice constant) – where the energy of
the solid becomes minimised. Bringing the atoms closer together will dramatically increase the repulsive force between
the nuclei and between the surrounding electrons of each atom and is thus unfavourable.
Two extreme types of bonding exist: the ionic and the covalent bond. In the ionic bond one atom transfers one or more
of its electrons to the other atom. In a covalent bond the electrons are mutually shared. This is illustrated in figure 1.
Figure 1: A simplified cartoon of ionic and covalent bonding
Now take a look at the periodic table in figure 2. The elements in the periodic table are organised according to their
atomic number which is equal to their number of protons and thus electrons. This number increases by one with each
element listed, thus different elements have a different number of electrons. Quantum mechanics has shown that these
electrons cannot all have the same energy contents (see
2
). A more simplified view of an atom (element) was introduced
by Niels Bohr in 1913. This model shows the electrons in orbit around the nucleus on different “distances from the
nucleus” – shells. Each shell can only contain a certain maximum amount of electrons and the closer the shell to the
nucleus the stronger the bond between the nucleus and the electron. On the first shell (“closest to the nucleus”) only 2
electrons are allowed, on the 2
nd
8, on the 3
rd
18, etc. Although the Borh model with “distances from the nucleus” is not
completely correct, it is a useful tool to explain why certain bonds are made.
Take the last column of the periodic table (fig.2) with elements such as He
2
, Ne
2,8
, Ar
2,8,8
, Kr
2,8,18,8
, Xe
2,8,18,18,8
,…(noble
gases)
3
We know from chemistry that these elements are chemical inert (do not react, are very stable). On the other hand
we notice that the outer shell in these stable atoms (apart from He) has 8 electrons. As a rule of thumb, individual atoms
will react in such a way as to fill or empty the outer shell such that it obtains 8 electrons and thus takes the electron
configuration of a noble gas. These outer shell electrons are also called valence electrons.
2
See teaching on http://www.ee.ic.ac.uk/wtp/
3
The superscript on the elements give the number of electrons in each shell.
+
e

+
e

+
e

e

+ +
e

+
e

Ionic bond Covalent bond
+ +
+ + + +
6
Figure 2: Periodic table
To illustrate its influence on bonding, take Na (Sodium): Na
2,8,1
. In a bonding process it will be happy to lose one
electron to obtain the Ne configuration. Cl
2,8,7
on the other hand is happy to receive one electron. Thus Na and Cl made
an ionic bond. This type of bond works well with elements that do not have to lose or gain more than 2 max 3 electrons.
Once more electrons have to be transferred, large amounts of energy are needed that are not normally available at room
temperature. Therefore the elements in the middle of the periodic table such as C, Si, Ge, Ga, As,… prefer a covalent
bond where electrons are shared rather than transferred. A more quantitative measure of the ability to donate electrons is
called ionisation potential, or otherwise the electron affinity which gives the ability of an element to accept electrons.
These values are tabulated in textbooks and are the energy required respectively released by losing resp. gaining an
electron. This concept of electron affinity will be useful later in the course.
Historically we know that C, Si, Ge, GaAs are semiconductors. These solids are formed by covalent bonds. Si has 4
valence atoms and forms covalent bonds with the neighbouring Si to obtain the noble gas electron configuration, see
figure 3. The same happens with Ge. Ga has 5 valence electrons whilst Al has 3, the covalent bond of these elements
also leads to a shared 8electron configuration in the outer shell.
Figure 3: Left: a Si (silicon) atom with its 4 valence electrons. Middle: covalent bonding with its neighbours, allows
each Si atom in the lattice the noble gas configuration within the solid. Right: an alternative representation of the
covalent bonds in solids.
In order for the semiconductor to be of interest for mainstream Si technology (as required in the processors of your PC),
the Si lattice needs to be crystalline. This means that the position of the atoms must be periodic in the whole volume of
the material. It is impossible to fabricate semiconductor materials that are perfectly crystalline, nor perfectly pure
(lacking of any “foreign” atom). But material fabricants are making Si very close to perfect and this then allows
processors to become faster and cheaper. In this lecture course we will focus on devices made in Si only.
By sharing, atoms feel surrounded by 8 valence electrons
7
Whilst semiconductors are built of atoms with strong covalent bonding of the valence electrons, metal have a different
bonding structure which is more ionic in character. A metal can be regarded as made up of lattice ions surrounded by
highly mobile negative carriers, electrons
4
. Thus in a metal the electrons roam freely within the confines of the metal
boundary.
2. Conductivity in semiconductors
In metals the highly mobile electrons roam freely within the structure, in a semiconductor the electrons are “trapped” by
the covalent bonding process – the electrostatic forces between the atoms that form the lattice. Sufficient energy needs
to be applied to the lattice in order to break some of the bonds and thus release electrons from the nuclei. At absolute
zero temperature: T=0K and without any other excitation none of the electrons will be released from the covalent bonds
of the semiconductor lattice. However when we increase the temperature, the thermal energy is sufficient to release
some electrons. At room temperature there will be a sufficient amount of electrons freed from the bonds to enable
electrical conduction in the semiconductor, but still a lot less than in metals where the number of electrons involved in
the conduction is a lot higher and are more mobile than in semiconductors. Based on this knowledge an alternative
definition of a semiconductor can be given: a semiconductor is a solid material with an electrical conductivity
5
between
that of a metal and an insulator.
At T=0K do you expect the semiconductor to behave as a metal or as an insulator?
The conductivity of a semiconductor is dependent on the amount of charged carriers that can participate in conduction.
The charged carriers that can conduct are only those that are released from the covalent bonds in the lattice. Energy
supplied to the semiconductor, such as in the form of temperature, can release some electrons from the covalent bond.
These released charges are going to roam around the semiconductor in all directions (random motion) due to the thermal
energy available. Figure 4 gives a schematic picture of freed electrons in the lattice.
Figure 4: Thermal energy has broken 2 covalent bonds and two electrons are released to roam within the lattice. A
consequence of the freed electrons is that some atoms do not have the noble gas electron configuration any more.
As illustrated in Figure 4, the freed electrons leave behind “empty spaces”. The concerned atoms will strive to fill these
“empty spaces” with another electron in order to rebuild the 8valence electron configuration. The “empty spaces” are
called holes and since they will be filled by creating an empty space at another atom position, it looks as if the empty
space is travelling through the structure (since the hole is not bound to the atom – it can travel – and is thus free). Given
that the “empty space” is a lack of an electron it behaves as a positively charged carrier. Remember an electron is a
negatively charged carrier. Thus, thermal energy will generate free electrons and holes (empty spaces), a process that is
called generation of electronhole pairs. At the same time a certain amount of holes (empty spaces) will be filled with
electrons, a process called recombination of electrons and holes. The amount of free electrons per volume (density of
4
See e.g. “Lecture on electrical properties of materials” by L. Solymar and D. Walsh (Oxford University press  1975)
5
Conductivity is a parameter that indicates how much current will flow through the solid when a voltage is applied.
Electrons released from the covalent bond.
These atoms now miss an electron for a noble gas configuration.
8
carriers) generated via thermal energy is n
i
= 1.45 10
10
cm
3
for Si at room temperature. For another semiconductor it will
be a different value e.g. for Ge it is: n
i
= 2.4 10
13
cm
3
at room temperature.
What is the relationship between the amount of free electrons and free holes created by thermal energy only? (<,=,>)
This is a very interesting result as it concludes that in a semiconductor we have not one but two types of charged
carriers: the electron with its negative charge and the hole with a positive charge. The electron charge is q=e and the
hole charge is q=+e with e=1.6 10
19
C.
The picture we have sketched here to explain the existence of holes is indeed rather intuitive. Again quantum mechanics
is needed to, not only, show that free positively charged carriers – holes – exist in semiconductors but is also needed to
explain the specific character of these charges.
Can you suggest an experiment, using electric and magnetic fields, that can prove that positive charge exists in
semiconductors? Hint: remember the expression for a force, F on a charge, q in a static electromagnetic field:
( ) B v q qE F × + = with E: electric field, B: magnetic field and v velocity of the moving charge. Or take a look at
your Engineering Materials course.
Temperature is not a sufficient parameter in order to change the conduction of the semiconductor when one wants to use
it in microprocessors, in order to be useful for devices another method needs to be suggested. We know already that an
increase in free charges, electrons or holes, will increase the conductivity of the material. There exist another way to
increase the amount of charges – called doping. Doping is a selective process. This means that by using doping we can
increase the amount of one type of carriers e.g. electrons compared to the amount of the other carrier type, holes, in one
semiconductor.
Figure 5 left demonstrates a doping process in which a surplus amount of electrons is introduced: ntype doping. Fig.5
right shows the situation of ptype doping – a surplus of holes.
Figure 5: Left ntype doping by replacing an amount of Si atoms by atoms with 5 valence electrons. Right: ptype
doping by replacing an amount of Si atoms by atoms with only 3 valence electrons.
Using a process called ion implantation, foreign elements can be introduced that replace some of the Si atoms in the
lattice. These foreign elements have to sit on the exact lattice positions of the removed Si atoms. The foreign elements,
when chosen well, will go into covalent bonding with the surrounding Si lattice. For ntype doping, the foreign element
has 5 valence electron, typically P or Sb is used in Si. Only 4 of the 5 valence electrons of the foreign element will bond,
leaving one free electron. For ptype doping the foreign element should only have 3 valence electrons, typically B is
used in Si. Since the foreign element lacks 1 electron in the bond, it has generated a hole. The number of foreign
elements we can introduce in this way can be a lot higher than the amount of intrinsic carriers. Ntype doping levels of
up to 10
19
cm
3
and ptype of up to 10
20
cm
3
can be introduced without destroying the crystallinity of the Si lattice or the
Si electrooptical character of the lattice. It remains to be noted that for the doping induced carriers to be free, ionisation
of the foreign element needs to occur. Thus the temperature of the materials has to be well above absolute zero for
doping to be effective. At room temperature for P, Sb, B and As doping in Si we can assume, with negligible error, that
all doping atoms (foreign elements) are ionised and thus all extra introduced carriers free. Figure 6 gives the variation of
the carrier concentration (electrons) in donor doped Si to a level of N
D
=10
15
cm
3
as a function of temperature.
P has 1 more valence electron than Si.
A foreign element is introduced,
e.g. P
B has 1 valence electron less than Si.
A foreign element is introduced,
e.g. B
9
ntype doping changes the semiconductor into a material with a surplus of electrons compared to the amount of holes.
The semiconductor is then called an ntype semiconductor. If we call the density of electrons n and the density of holes
p then in an ntype semiconductor we find that n>p. The doping atoms (foreign elements) are called donors in this case.
ptype doping changes the semiconductor into a material with a surplus of holes compared to the amount of electrons.
The semiconductor is then called a ptype semiconductor. In a ptype semiconductor we find that p>n. In this case, the
doping atoms are called acceptors.
Figure 6: Free carrier concentration as a function of temperature for ntype Si.
Summary:
* Intrinsic (i.e. pure, undoped) semiconductors have a small amount of free carriers at room temperature and therefore
have a very low conductivity (e.g. diamond). The number of holes and electrons are equal in an intrinsic semiconductor
as the free carriers are generated by thermal energy and thus whilst and electron is created a holes occurs simultaneously
(electronhole pairs).
i i
p n = (1)
n
i
is the intrinsic number of electrons
p
i
is the intrinsic number of holes
* Extrinsic (i.e. doped) semiconductors have better conductivity.
dopants + intrinsic
= extrinsic
semiconductor semiconductor
Impurities, donors or acceptors, are introduced in the pure intrinsic semiconductor. Thermal energy frees electrons from
donor atoms, and holes from acceptor atoms.
Donor doping (donors donate an extra electron) creates an ntype material. The donor density notation is N
D
Acceptor doping creates a ptype material. The acceptor density notation is N
A
The density of dopants is normally higher than the intrinsic density of free carriers in the semiconductor. (e.g. for Si
n
i
=1.45 10
10
cm
3
whilst doping density introduced in the lattice is >10
15
cm
3
)
As a consequence of doping, the conductivity σ of the semiconductor can be changed. Note that the reciprocal of
conductivity is resistivity ρ=1/σ.
The conductivity is directly related to the amount of free carriers in a semiconductor, increasing the amount of free
carriers, increases the conductivity.
In an ntype semiconductor at room temperature the density of electrons will be equal to the doping density n=N
D
because N
D
>>n
i
. Therefore the conductivity of an ntype material is directly proportional to the donor doping density:
D
D
N
N n
∝
=
σ
(2)
Similar in ptype material p=N
A
because N
A
>>p
i
and thus:
A
A
N
N p
∝
=
σ
(3)
Since a surplus of one type of carriers can be established via doping in one semiconductor, additional nomenclature for
the different types of carriers within this semiconductor has been introduced. Within a doped semiconductor we call the
F
r
e
e
e
l
e
c
t
r
o
n
d
e
n
s
i
t
y
(
c
m

3
)
1000/T (K
1
)
10
11
10
13
10
15
10
17
0 2 4 6 8 10 12
At very high T, huge
electronhole pair
generation: n
i
>N
D
At moderate T, all
donor atoms ionised
n
i
<N
D
& n=N
D
At very low T, few
electronhole pairs
generated and donor
electrons stay bound
to donor atoms
10
carrier type with the larger density the majority carrier, whilst the carrier with the lower density is called the minority
carrier.
What is the name of the majority carrier in an ntype semiconductor?
There exist relationships between the majority and minority carrier concentration (density) in one semiconductor:
* ntype semiconductors
Majority carrier concentration,
D n
N n = (4)
Minority carrier concentration,
D
i
n
N
n
p
2
= (5)
Note the subscript n to indicate that we are looking at the carrier densities in an ntype material.
* ptype semiconductors
Majority carrier concentration,
A p
N p = (6)
Minority carrier concentration,
A
i
p
N
n
n
2
= (7)
*The majority and minority carrier concentrations within one semiconductor are related by:
2
2
i p p
i n n
n p n
n p n
=
=
(8)
Although these names, majority and minority carrier, seem pointless at the moment, they will be useful in the discussion
of devices where both electrons and holes play a role – the socalled bipolar devices.
Charge neutrality should of course still be maintained, therefore the total number of negative charge = total number of
positive charges:
+ −
+ = +
D A
N p N n
With n: density of free electrons, p density of free holes,
−
A
N ionised acceptor atoms (are negatively charged) and
+
D
N
ionised donor atoms (are positively charged). Note that the ionised doping atoms are fixed within the lattice and cannot
roam around the lattice. They do not contribute towards current.
Thought experiment
Assume we fabricate two resistors in Si using doping implantation. For resistor R
1
we implant the Si surface A with P to
a depth d with a density of doping atoms N
D1
. Resistor R
2
is implanted in the same volumes with a density of doping
atoms N
D2
. After defining two contacts to the implanted Si volumes, the resistance of R1 and R2 can be determined by
e.g. applying a voltage and measuring the current through the structure. The result of the measurements is given in
figure 7 below
Figure 7: Measured currentvoltage (IV) characteristics of the two resistors.
We note that the current through R
1
is smaller than through R
2
for the same voltage. If we take into account Ohms’ law
V=R I (see Course Analysis of circuits, by Dr. D. Haigh) then we can determine which of the two Si resistors has the
highest doping density.
I
V
R
1
I
V
R
2
11
Determine the relationship between the doping density of the two resistors of the experiment N
D1
<,=,> N
D2
.
It needs to be pointed out that Si doped resistors, as presented in the example above, is avoided in integrated circuits
notwithstanding their simplicity, because of the large area necessary to make such a resistor and because of its constant
value (if one gets it wrong, there is no easy solution). Integrated circuit design relies on active devices – the MOSFET to
function as a resistor. MOSFETs are small and the resistance offered by a MOSFET can be varied electrostatically.
3. Currents in semiconductors
The interest in semiconductors is based on their ability to generate currents in response to an applied voltage and that
somehow we can control these current by changing the material properties itself (e.g. doping) or indirectly by external
currents or voltages on a device made from a combination of materials with different properties. The relationship
between the current through and the voltage applied across the semiconductor (device) is not necessarily linear and
creates a lot more circuit potential when it is nonlinear.
In semiconductors two types of current can exist: drift and diffusion currents. It is the aim of this section to generate an
understanding into the physical principles behind the existence of the currents.
In previous section we have seen that at room temperature there exist an equal amount of free holes and electrons in an
intrinsic semiconductor, or there exist a surplus of one type of carriers – the majority carriers – in an extrinsic
semiconductor due to doping of the material. These free carriers – the ones that are not stuck in the covalent bonds – are
always whizzing around in the semiconductor in no particular direction due to the existence of thermal energy
T k
B
2
3
~
,
with k
B
= 1.38 10
23
J/K the Boltzman constant and T the temperature in K (equivalent to molecules in a gas). So
although the carriers are moving continuously, they move randomly and therefore do not generate a current. The random
motion can be seen as a process of acceleration of the carriers due to the thermal energy input, followed by interactions
of the carriers with the lattice which makes them lose energy and/or change direction. This is called elastic (only energy
contents is changed) or inelastic scattering (both energy and direction are changed).
3.1 Drift currents
If an electric (or magnetic) field is applied then the motion of the carriers is still under the influence of scattering
processes, and each individual carrier might not take necessarily the same path, but the average direction of movement
(velocity) of all the carriers is determined by the applied electric field. This motion of carriers under an applied electric
field is called drift. Figure 8 illustrates what is happening with 1 carrier.
Figure 8: Schematic illustration of the random motion of a carrier. When an electric field is applied the scattering
processes still occur but the average direction the charges go is determined by the direction of the electric field.
Determine the charge of the carrier ( or +) discussed in figure 8 based on its movement relative to the electric field.
The drift current caused by charged carriers under an electric field must be proportional to the amount of carriers
available and the speed with which these carriers move. The amount of carriers available is determined by their doping
density. In the following we will derive the velocity of the carriers in a semiconductor under an electric field – drift
velocity – based on classical formulae and quantum mechanical arguments.
Newton 2
nd
law gives the relationship between acceleration
dt
dv
and electric field E:
Path followed when no
electric field is applied
Scattering events
Path followed when an
electric field is applied
Scattering events
still occur but the
electric field pulls
the carrier to the
“left”.
E
12
(9)
This is a well known classical relationship but what is the mass m of a carrier? We know that the mass of a free electron
in vacuum is m
0
=0.91 10
30
kg. There is of course a difference between an electron in vacuum and an electron in a
semiconductor. The electron in a semiconductor is moving in the neighbourhood of other electrons and more
importantly in the neighbourhood of positively charged nuclei. Thus the speed with which the electron in a
semiconductor is travelling will be influenced by the electrostatic forces that act upon them. Of course in (9) this is not
taken into account and in principle makes it inappropriate for use in a situation of a semiconductor. However if we want
to avoid having to go through rigorous quantum mechanical calculations it would be preferable to stick to this well
known law. The carrier within a semiconductor is regarded as only quasi free as it still feels the interactions with the
lattice. These interactions are taken into account through a change in the carrier mass for both electrons and holes. As a
result (9) is still valid when the value for the mass m is replaced by
*
, 0 p n
m m m = with
0
m the free electron mass,
*
n
m
the effective mass of the electron, and
*
p
m the effective mass of the hole. This intuitive approach of introducing a
different mass for the carriers in a semiconductor can also be derived from quantum mechanics
6
. In the quantum
mechanical approach electrons and holes are regarded as having both a particle and a wave character (cfr light). One can
calculate the propagation of the electron wave through a semiconductor taking into account the periodic electrostatic
potential changes of the lattice that will be felt by the carrier wave (the KrönigPenney model). This model leads to two
important conclusions:
1) the electrons cannot have all possible energy values, because there exist a region of forbidden energies.
2) there exist two types of carriers:
a. electrons with a charge q=e and a mass
*
0 n n
m m m =
b. holes with a charge q=+e and a mass
*
0 p p
m m m =
The value of the effective mass for different semiconductors are different and can be found in tables in textbooks for
most of the available semiconductors. Table 1 give a short list of effective masses for different popular semiconductor.
Table 1: The average effective mass of electrons and holes in Si, Ge and GaAs
Effective mass
7
Si Ge GaAs
electrons 0.26 0.12 0.067
holes 0.33 0.16 0.26
Do electrons and holes in one semiconductor have the same mass?
If the carriers obey (9) then they would undergo a continuous acceleration in the direction of the electric field, but that is
not the case because the net acceleration of (9) is just balanced by deceleration due to scattering processes to create a
steady state condition. Remember that the carriers are still under the influence of the thermal energy and are still being
scattered. This is due to fact that the position of the atoms in the lattice is not constant, the atoms vibrate around a fixed
position due to the thermal energy, this gives temporal changes in the periodic potential of the lattice through which the
carriers are travelling. Moreover no lattice is perfectly pure and thus not perfectly periodic, imperfections increase the
number of scattering events. Since introducing doping atoms is actually disrupting the periodicity of the lattice, doping
atoms also increase the number of scattering events.
The deceleration of the carriers due to scattering processes can be mathematically expressed as:
(10)
The average time between the scattering events is given by τ – the mean free time.
Thus in steady state the average gain in velocity (acceleration) is equal to the average loss in velocity (deceleration),
therefore from (9) and (10)
8
we find the average net velocity of the carriers in a semiconductor under and electric field:
(11)
The material constant:
6
See the Engineering Materials course
7
Average effective mass over the degenerate bands
8
gain+loss=0
qE
dt
dv
m =
τ
v
dt
dv −
=
m
qE
v
τ
=
13
m
eτ
µ =
(12)
Is called the mobility (in cm
2
/Vs)and is a material and doping dependent positive value. Therefore the average net
velocity of the carriers in a semiconductor under and electric field – also called the drift velocity – is:
E v
p n p n , ,
µ ± = with + for holes and  for electrons. (13)
Sketch the direction of the electron velocity relative to the electric field for both electrons and holes. Which of the two
carrier types in silicon will have the highest velocity?
The expression of the drift velocity given in (13) is only valid for low electric fields, at higher electric fields the
characteristics of the scattering processes change and become field dependent such that the linear relationship between
drift velocity and electric field no longer exists.
Figure 9: Drift velocityelectric field curves. E
max
is the maximum electric field for which the linear relationship between
drift velocity and electric field as given by (13) is valid.
How can you derive the mobility from the vE graph given in Figure 9? Does GaAs have a higher mobility than Si?
Why? How do you expect the relationship between the hole mobility of Si and Ge to be (<,=,>)?
As we now know the velocity and the number of carriers, we can derive the expression of drift current in
semiconductors. The current density J due to the net drift of carriers is the number of carriers crossing a unit area per
unit time multiplied by the charge:
E en env qnv J
n n n n
µ = − = = is the current density (A/cm
2
) for electrons
E ep epv qpv J
p p p p
µ = = = is the current density (A/cm
2
) for holes
The total current is then:
( )E p n e J J J
p n p n tot
µ µ + = + = (14)
From Ohm’s law we know J=σ E, thus we find the expression for the total conductivity:
( )
p n p n tot
p n e µ µ σ σ σ + = + = (15)
The units for conductivity are (Ω cm)
1
. The reciprocal of the conductivity σ is the resistivity. ρ:
σ
ρ
1
=
.
We are now able to calculate the resistance of a volume of a certain semiconductor doped to a known level. The values
of the doping dependent mobilities can be found in textbooks for different semiconductors.
Calculate the resistance of a Si volume with the geometry: length in the direction of the current flow 100µm, width resp.
thickness (perpendicular to the direction of current flow) 50µm x 10nm. The donor doping density in the Si is 2 10
17
cm

3
. How would this resistance compare to that of the same volume of GaAs with the same doping density? Remember
that the resistance R is given by:
A
l
R
ρ
=
with l the length of the resistor (in the direction of current flow) and A the cross
sectional area.
v
E
Si
GaAs
E
max
14
Figure 10: The low field mobility as a function of doping concentration for different semiconductors. Taken from S.M.
Sze “Physics of Semiconductor Devices.
3.2 Diffusion currents
In the above section we have seen that the random motion of the charges can be changed by applying an electric field.
The charges still whiz around the lattice but the average velocity of the total amount of charges is determined by the
electric field and thus a current is generated – drift current. In semiconductors another type of current can occur, one that
is due to excess carriers.
As seen before generation of carriers via temperature is always in pairs of electrons and holes and thus the number of
electrons and holes caused by generation is equal (the intrinsic carrier concentration at a certain temperature). Assume
that a process exists that can create locally an excess of one type of carriers compared to the other. This would generate
a local gradient of carriers. The carriers are going to react as what you would expect from gas molecules. If at a corner
of the room a chemical (e.g. gas molecules different than nitrogen and oxygen that normally occur in air) the after a
while the observer can smell the gas at the other side of the room because the molecules have diffuse throughout the
room to cancel the gradient in its density. The same happens with excess carriers in a semiconductor, they will diffuse in
order to eliminate the excess. This diffusion is indeed not completely random any more as it moves the carriers on
average in the direction determined by the gradient. This process will cause diffusion currents. Figure 11 gives the
variation of the density of electrons as a function of space and time (in 1 dimension only).
Figure 11: Left: diffusion of an excess of electrons as a function of time and space. Right: Flux of electrons
draw only in the +x direction. When taking an infinitesimal small region, the graph is linear.
With reference to fig.11, when only diffusion is taking place, than the number of electrons will remain constant (thus the
area under each graph in fig.11 remains constant). When we wait long enough the variation of the electrons as a function
of space will be zero (no excess and thus also no gradient any more) but its value nonzero.
n(x)
x
t1
t2
t3
t3>t2>t1
n(x)
x
linear
t3
x x+∆x
e

flux
n
n+∆n
15
In real semiconductors however there are two kinds of carriers. This means that from time to time, with a characteristic
time τ
p
or τ
n
– the characteristic life time – the excess carriers are going to recombine with the other type of carriers
available. Recombination is the opposite of generation: during generation an electronhole pair is made, during
recombination an electronhole pair disappears. If recombination occurs during the diffusion process then the number of
excess carriers lowers and the area under the graphs in fig.11 will decrease as a function of increasing diffusion time.
Again these times τ
p
or τ
n
are average times (average over the huge amount of carriers available in a semiconductor).
This means that in reality some carriers will recombine sooner and some later than these given characteristic times.
However we will use the characteristic lifetime of the carriers to make approximations when discussing devices and
treat them as the cutoff value. When a carrier is travelling in a time span smaller than its life time, then in principle,
they do not recombine. The distance the carrier has travelled is then L
p
or L
n
– the diffusion length of the carrier.
The diffusion current will be proportional to the charge and the number of carriers that flow across a certain position x
as a function of time. This number will be directly proportional to the gradient of the excess carrier concentration. If we
look at an infinitesimal region (∆x) of space in fig.11 (right), then we find an infinitesimal variation of the carrier
concentration (∆n). This extremely small region is as good as linear and therefore we can easily calculate the gradient of
this region. At x we find a carrier concentration n and at x+∆x we find a carrier concentration n+∆n: thus the carrier
gradient is
( ) dx
dn
x
n
x x x
x x n x n
− =
∆
∆
− =
∆ + −
∆ + − ) ( ) (
(for ∆x→0)
Thus the gradient of the curve of the excess carrier concentration in each point x is its first derivative.
The diffusion current due to excess carriers is then
dx
x dn
eD
dx
x dn
eD
dx
x dn
qD J
n n n n
) ( ) ( ) (
=
−
− =
−
= for electrons (16)
dx
x dp
eD
dx
x dp
eD
dx
x dp
qD J
p p p p
) ( ) ( ) (
− =
−
+ =
−
= for holes (17)
D
n,p
is the proportionality constant and is called the diffusion constant. The diffusion constant stands in relation with the
mobility following the Einstein equation:
( ) K T V
e
kT
D
p n
p n
300 @ 026 . 0
,
,
= = =
µ
(18)
In order to be able to use equations (16) & (17) we need to know the variation of the excess carrier concentration as a
function of distance. Remember that when a semiconductor is uniformly doped, the density of mobile charges at room
temperature is equal to the density of the doping atoms (at room temperature), see eq. (4) & (6). This allows us to
calculate the drift currents given by eq. (14). Homogeneous doping does not create gradients and thus also no diffusion
currents. In the case an excess charge is introduced the number of charges are defined by the introduction process. What
remains to be determined is how recombination will change this number.
4. Mathematical description of the energy of electrons and holes
The optical and electrical properties of semiconductors are determined by the energy of the free carriers, both electrons
and holes. In order to build a robust mathematical picture of the energy relationships of the free carriers, one has to look
into the subject of quantum mechanics. This will not be done in this course but you will get a glimpse of quantum
mechanics in the spring term course: Engineering Materials, which will strengthen the more intuitive approach we give
here.
We have already seen that a Si atom has 14 electrons. All these electrons have certain energies in relation to their
“position”
9
from the nucleus (see Fig.12a). When we bring the Si atoms together into a Si lattice, we have seen that
covalent bonding will occur. Thus the 4 outer shell electrons of each neighbouring Si atom will be shared. We can
accept that under these interactions, the energy of the electrons has changed. This means that the energy of the single Si
atoms will be different from the energy of the Si atoms within a lattice. If we take 2 Si atoms, each one individually
surrounded by vacuum will have an energy value E
0
. When we bring the two close together, interactions cause covalent
bonding and each atom cannot have the same energy value E
0
any more. The coupled mode theory, formulised by
Feynman, calculates that the original energy level E
0
splits in two different levels E
1
and E
2
, one higher and one lower
than the original single atom energy (see Fig.12 b). But in a Si crystal we have 10
23
cm
3
atoms which will all interact
9
Bohr model.
16
with their neighbours. When N atoms are brought close together, then there are 4N valence electrons, thus the energy
levels will split again into 2N filled energy levels and 2N empty energy levels as shown in Fig. 12c.
Figure 12: a) (left) Energy of the 14 electrons in an isolated Si atom. b) (middle) Energy of the valence electrons when 2
Si atoms are covalently bonded. One sp3 energy configuration is completely filled the other one, called sp*3 is
completely empty (total number of levels are maintained but electrons are redistributed over levels). c) (right) N Si
atoms brought together increases the number of energy levels in sp3 to 2N and in sp*3 too. Each energy level (also
called a state) can only take two electrons).
Thus the covalent bonding of the valence electrons within the semiconductor lattice has created bands of allowed
energies. The valence band, which is an energy region with extremely closely spaced energy levels (states) is completely
filled with the valence electrons of all the atoms. On each level 2 electrons occur (Pauli’s exclusion principle). In energy
bands below the valence band are the other electrons that do not take part in the covalent bonding. The conduction band
is the higher lying energy band with closely spaced energy levels. This band is completely empty of electrons when the
covalent bonding is complete. In between these two regions that are filled with energy levels that can each carry 2
electrons, lies a region where no states (energy levels) occur. This means that there cannot exist an electron with an
energy within this region
10
. The region without energy levels is the forbidden band or bandgap. The difference
between the bottom of the conduction band and the top of the valence band is E
g
, a constant (at constant T) for each
semiconductor.
In the given situation with complete covalent bonds, the valence band energy levels are all completely filled up. If we
apply a voltage across the semiconductor and thus increase the energy of the electrons than these would have energies
within the bandgap. Since this is forbidden, no current can flow in this system. This is consistent with what we have
seen before because current can only be carried by free electrons (not bonded to the atom) which only occur when the
covalent bonding is not complete. Thus, in order to generate a current some of the electrons in the valence band should
“jump” to the conduction band, as there are a lot of free energy levels available.
How do electrons gain sufficient energy to cross the bandgap?
We have seen that at room temperature there will be a certain amount of electrons that break away from the covalent
bond. These electrons gain enough energy to occur in the conduction band. Of course when an electron jumps to the
conduction band it leaves and empty space on an energy level in the valence band, this space can be occupied by other
electrons gaining energy in the valence band or can be refilled with electrons falling back from the conduction band. In
the first case we see an “empty” space travelling. This will be the hole we have talked about before. Thus filled energy
levels in the conduction band (electrons) can travel and thus carry current. The same is valid for the empty spaces in the
valence band (holes) which can travel and carry current.
Another method to create free electrons (in conduction band) and free holes (in valence band) is by shining light with
the correct wavelength, λ, on the semiconductor. Photons (light particles) with an energy
g
E hf
h
E > = =
λ
will
transfer their energy to the valence electrons and create electronhole pairs.
10
For pure material and ignoring possible quantum mechanical tunnelling processes.
e
n
e
r
g
y
1s
2s
2p
3s
3p
outer shell electrons
∆E≈1eV
e
n
e
r
g
y
1s
2s
2p
3s
3
do not take part in
bonding
Completely filled
3s
3
Completely empty
sp3
sp*3
e
n
e
r
g
y
Conduction band
Valence band
No
energy
levels
17
Both methods given above create the same amount of free electrons as free holes via direct energy transfer to the
valence electrons. Note that these electrons are in a higher (excited) state and will try to return to their lowest possible
energy value. This means that generation (creation of electron hole pairs) and recombination (annihilation of electron
hole pairs = excited electrons fall back to the valence band) is a continuously ongoing process.
We have seen a 3
rd
method to increase the number of free carriers and that is implantation where a certain density of Si
atoms is replaced by group III or group V atoms (acceptor resp. donor doping). How these free electrons or holes into
the energy band formalism will be discussed later.
What is the amount of electrons in the conduction band of Si at absolute zero temperature T=0K?
Given the energy band diagram, we still need to find expressions that relate the density of free electrons (n) and free
holes (p) to certain energy levels.
In the above we have seen that electrons and holes occupy certain energy levels or states that are discrete but closely
spaced in energy (therefore we talk of an energy band). The number of available states for free electrons increases with
increasing energy above the bottom of the conduction band and the number of states for free holes increases with
decreasing energy below the top of the valence band. In the course Engineering Materials
11
you will see that the number
of states as a function of energy g(E) is proportional to E E g ∝ ) ( . We also know that free electrons and holes can
only have an energy value at which point there is an available energy level (state) and only 2 electrons or holes per level.
At room temperature there are of course a large amount of free electrons and holes and we require knowledge on
whether a state at a certain energy is filled or not by an electron or hole. Since there are a large number of carriers and
they are continuously moving, statistical methods need to be applied. The statistics is based on the knowledge that
electrons are indistinguishable, that they behave as waves in a crystal and that they obey the Pauli exclusion principle.
This has led to the FermiDirac statistics that expresses the probability of finding an electron at an available state at a
certain energy E and temperature T:
( )
(
¸
(
¸
−
+
=
kT
E E
E f
F
exp 1
1
) (
(19)
Where k is the Boltzmann constant: k=1.38 10
23
J/K and T is the absolute temperature in K.
f(E) is called the FermiDirac distribution function. The quantity E
F
is the Fermi level. At the Fermi level the probability
to find an electron is ½.
If f(E) gives the probability to find an electron then 1f(E) must give the probability to find a hole. Figure 13 gives the
FermiDirac distribution function for different temperatures.
Figure 13: The FermiDirac distribution function as a function of temperature.
What is the probability to find an electron at energies larger than E
F
at absolute zero temperature? What is the
probability of finding a hole at energies lower than E
F
at T=0K?
The FermiDirac distribution function can be used to calculate the number of free electrons and holes via:
( )
∫
∫
∞ −
+∞
− =
=
v
c
E
E
dE E g E f p
dE E g E f n
) ( ) ( 1
) ( ) (
(20)
11
Spring term course
f(E)
E
1/2
1
E
F
T=0K
T
1
T
2
>T
1
18
With E
c
the bottom of the conduction band and E
v
the top of the valence band. n is the density
12
of free electrons and p is
the density of free holes.
The result of the integration is
13
:
( )
( )

¹

\
 − −
=

¹

\
 − −
=
kT
E E
N p
kT
E E
N n
v F
V
F c
C
exp
exp
(21)
With N
C
and N
V
the effective density of states in the conduction resp. the valence band.
2
3
2
*
2
3
2
*
2
2
2
2


¹

\

=


¹

\

=
h
kT m
N
h
kT m
N
p
V
n
C
π
π
(22)
With
* *
&
p n
m m the effective mass of the electron, resp. the hole.
Before we go further with the discussion on the density of free carriers in a semiconductor, let’s interpret the concepts of
effective masses. The mass of an electron in vacuum is given by m
0
=9.11 10
31
kg. Thus in an electric field this electron
in vacuum will undergo a force given by the classical formula F=qE and since F=ma (a is acceleration) thus the speed
of the electron will be determined by its mass and the applied electric field. Can we apply the same classical formulae to
the electrons and holes that are whizzing around within the periodic lattice of the semiconductor? The answer is in
principle “no” since the electrons and holes moving inside a crystal will undergo additional forces from the surrounding
atoms in the lattice which will be superimposed onto the applied electric field. This is of course a tremendous setback
when we want to study transport of charged carriers in a semiconductor and in semiconductor devices. It was found
however that if one introduces the quantum mechanically derived masses of the free electrons and holes into the
classical formulae, that these describe the transport of free carriers in the semiconductor perfectly well. What is
happening is that all the additional forces that are imposed by the lattice on the free carriers in the semiconductor are
taken up in the value of the effective mass of the electrons and holes. Thus we can apply the classical formulae when we
use the quantum mechanical values of the mass for electrons and holes:
p p
n n
m m m
m m m
0
*
0
*
=
=
(23)
With m
n
and m
p
the quantum corrections on the mass. For Si for carriers not too far away from E
v
and E
c
the values are:
m
n
=0.26
m
p
=0.54
Thus in Si the holes are heavier than electrons.
Explain why the mobility of holes in Si is lower than the mobility of the electrons.
Back to the density of free carriers as a function of energy at room temperature.
When we have an intrinsic material (no doping) we have seen that the density of free electrons is equal to the density of
free holes. The Fermi level will then lie at some intrinsic level E
i
near the middle of the band and the electron and hole
concentrations are then given by:
( )
( )


¹

\

− = ⇒


¹

\

− = = ⇒

¹

\
 − −
=

¹

\
 − −
=
kT
E
N N n
kT
E
N N n p n
kT
E E
N p
kT
E E
N n
g
V C i
g
V C i i i
v i
V i
i c
C i
exp
2
exp
exp
exp
2
(24)
You can now derive that the intrinsic level E
i
is lying midgap. When the semiconductor is doped, the free carriers can
be expressed as a function of the distance between the intrinsic level and the Fermi level.
12
In units of cm
3
13
See Engineering Materials
19
( )
( )

¹

\
 −
=

¹

\
 −
=
kT
E E
n p
kT
E E
n n
F i
i
i F
i
exp
exp
(25)
From the above equations we see that the distance between the Fermi level and the conduction band decreases when the
number of free carriers due to doping is increasing. Similarly the Fermi level comes closer to the valence band when the
number of free holes is increasing as a result of doping. Based upon this we can plot the following graph (fig. 14) that
shows the band diagram, the density of states the FermiDirac distribution function and the density of free carriers in
three cases: intrinsic (no doping), and extrinsic (ndoping resp. pdoping).
Figure 14: a) intrinsic semiconductor. Fermi level lies ±midgap and the density of holes and electrons is equal (shaded
regions). b) ntype semiconductor. The Fermi level lies closer to the conduction band than the valence band and as a
consequence the integration of the product of the density of states and the FermiDirac function gives an increased
density of electrons and a decreased density of holes. c) ptype semiconductor. The Fermi level lies closer to the valence
band than the conduction band and as a consequence the integration of the product of the density of states and the
FermiDirac function gives an increased density of holes and a decreased density of electrons.
In the extrinsic semiconductor we see that the density of free electrons first increases as a function of energy and then
decreases exponentially as a function of energy. Thus a large amount of electrons can be found at energies close to the
conduction band edge (E
c
), but further away the number decreases rapidly. Similarly for holes, a large amount of holes
is available near the valence band edge (E
v
) and decreases rapidly for decreasing energies.
The comprehension of these graphs, especially the left hand side and right hand side graphs, are of ultimate importance
to understand the physics behind the currentvoltage characteristics of semiconductor devices. Make sure that you
understand the graph.
Draw the carrier concentration of two ptype semiconductors. One has a doping density N
A1
and the other N
A2
with
N
A2
>N
A1
. Plot both on adjacent graphs and ensure that the qualitative difference between the two graphs is clear. Which
case has the largest density of free holes deeper in the valence band?
E
F
E
1/2 F(E) 1
E E
E
c
E
v
g(E)
carrier
concentration
a) intrinsic
electrons
holes
E
F
E
1/2
F(E)
1
E E
E
c
E
v
g(E)
carrier
concentration
b) ntype
electrons
holes
E
F
E
1/2 F(E) 1
E E
E
c
E
v
g(E)
carrier
concentration
c) ptype
electrons
holes
Extrinsic
semiconductor
Intrinsic
semiconductor
g(E) Density of states
F(E) FermiDirac distribution function
T>0K
20
Based on what we have learned, decide, based on the energy band diagrams given below, which one is a metal, a
semiconductor and an insulator.
empty
filled
empty
filled
partially filled
filled
or
overlap
E
c
E
v
E
g
E
c
E
v
E
c
E
v
E
c
E
v
E
g
a) b) c)
5. Some important relationships concerning energy bands
The energy bands give in indication of the potential energy of the free electrons, thus E
c
is. the lowest potential energy a
free electron can have. We aim to find the variation of the potential energy E
c
as a function of an electric field E and an
electrostatic potential V.
An electric field applied in the x direction E(x), points from high electrostatic potential v+ → v to low electrostatic
potential. The electrostatic potential difference V (x) varies in the opposite direction following
14
:
E(x)=dV(x)/dx (26)
We know that the electrons will travel from v → v+ (electrostatic attraction), thus in the opposite direction of the
electric field. A travelling electron is converting its potential energy in kinetic energy and thus its potential energy
should lower from v to v+. This means that applying an electric field will cause a gradient in the energy bands such
that the electric field points in the direction of increasing potential energy (see Fig.15)
E(x)=dV(x)/dx=1/e dE
i
/dx (27)
The direction of the slope of the bands is easy to remember: electrons drift “downhill”, holes drift “uphill” like bubbles
of air in water.
Figure 15: The tilt of the energy bands under influence of an electric field. Free electron will move from right to left
(down the hill), free holes will move from left to right (up the hill). Note that the bandgap is unchanged under the
influence of an electric field and that the intrinsic level follows the gradient of the band edges.
Most semiconductor devices are constructed from a connection of different materials. The position where the materials
touch is called the junction
15
. Different materials have different characteristics because the energy of their free carriers
might be different, e.g. due to different doping densities (or because they have a different band gap). The question is
14
See Fields course and Analysis of Circuits
15
Also metallurgic junction
E
c
E
i
E
v
E(x)
x
Energy
E
g
E
g
21
how to draw the energy band diagram of a combination of materials. In order to do that, we need to “calibrate” the
energy of the electrons in the different materials to an universal energy level. This level will be the vacuum level. To do
this the photoelectric effect is used. The material placed in vacuum is irradiated with photons and for a certain energy of
the irradiation electrons will be freed into vacuum from the material. The minimum energy at which this happens is
called the workfunction φ of the material. The workfunction is the energy difference between the Fermi level and the
vacuum level and is a constant for each material dependent on doping density. Thus we can draw the energy band
diagrams of each material next to each other to form the junctions with respect to the vacuum level (see fig.16). Note
that the value of the workfunction in each material, far from the junction will not change with applied bias.
Figure 16: left: The energy band diagram of two semiconductors before forming a junction relative to the vacuum level.
Right: After forming the junction electron diffuse from higher energy levels to lower energy levels (occupying lowest
available states within the system). The Fermi levels align and thus a potential difference will occur across the junction.
Due to the difference in workfunction one material will have electrons at higher energy levels compared to the other
material. When the two are brought into contact electrons will diffuse to the available states at lower energies if
possible. During this process the Fermi levels align. When the Fermi levels are aligned, no more diffusion will occur.
Thus in a junction without external bias the Fermi level is constant throughout the structure otherwise there would
be further diffusion of carriers until the Fermi level is aligned. This process of diffusion has created a potential
difference across the junction that is directly proportional to the workfunction difference. The existence of this potential
difference results in an internal electric field and thus we should find that the band across the junction show a gradient.
This will be discussed in detail in the pndiode section.
That diffusion causes internal electric fields and thus gradients in the energy band diagrams can be demonstrated
based on the expressions for the current in semiconductors (see eq. 14, 16, 17).
dx
x dp
eD E x ep J
dx
x dn
eD E x en J
p p p
n n n
tot
tot
) (
) (
) (
) (
− =
+ =
µ
µ
(28)
The total electron and total hole current are caused by drift and diffusion. When no external bias is applied, then the total
current should be zero. Thus each carrier current component should be zero. Introducing this into (28) gives an
expression for an electric field E that is caused by a carrier gradient d[carrier]/dx:
dx
x dp
x p
D
E
dx
x dn
x n
D
E
p
p
n
n
) (
) (
) (
) (
µ
µ
=
− =
(29)
Using equation (25) and (27) in (29) (e.g. for a gradient in hole density) gives the Einstein equation:
e
kT D
=
µ
(30)
This equation relates mobility to diffusion constant.
E
F
E
n
e
r
g
E
F
E
vac
E
c
E
v
eφ
1
eφ
2
E
vac
eφ
1
eφ
2
E
vac
e(φ
2
φ
1
)
E
F
E
c
Potential difference
across the junction
E
v
22
Chapter 2: Semiconductor junctions
In this chapter we will explain what is happening to the carrier concentrations when two different materials are
connected together. This will be a connection between a metal and semiconductor or between two semiconductors made
from the same material (Si in this case) but doped differently. The latter is a pn junction that is the basis for a diode. In
the next step we will apply voltages across the junction and based on energy band diagrams the physics behind carrier
transport will be discussed. Once the physics is understood the equations for current as a function of applied voltage can
be derived.
In order to simplify the description of the device physics and the derivation of the currentvoltage characteristics we will
ignore recombination in what follows. This approximation is also called the SHORT diode approximation. The more
general case, were recombination will be taken into account, will be discussed in year 2
16
.
1. Metalsemiconductor junctions
In order to allow us to study junctions of dissimilar materials (e.g. metal and semiconductor) it is useful to know that the
Fermi level in different materials can be defined with respect to a reference level – the vacuum level. This constant is
the work function φ. The workfunction is derived from the fact that it takes a certain amount of energy to drag an
electron out of a metal or semiconductor into a vacuum. The extra energy required to remove an electron at the Fermi
energy to a point some distance (in energy) away from the metal (known as the vacuum level) is called the work
function φ. This energy can be supplied by placing the metal or semiconductor in a large electric field (field emission)
or by raising its temperature (thermionic emission) of by shining light onto the solid (photoelectric effect).
Vacuum Level
Metal
n type
semiconductor
Ø
m
E
F
m
E
F
s
E
c
E
v
Ø
s
χ
s
Figure 1: Definition of the energy bands of a metal and a semiconductor with respect to the vacuum level via the use of
the workfunction of each material. Note that no contact between the different materials has been made.
For a semiconductor, another useful quantity is the electron affinity, χ, which is the energy required to remove an
electron from the bottom of the conduction band and place it at the vacuum level. Clearly, for a metal (which has no
energy gap) the electron affinity and work function are the same!
We have seen that when two different conducting materials, initially uncharged, are brought into contact, the electrons
close to the junction redistribute themselves via diffusion
17
so that the Fermi energy is constant across the junction
(in the absence of an applied voltage). We have also seen that when diffusion happens, an internal electric field is
introduced and thus the bands bend in the region where the field exist.
In order to draw an energy band diagram we find the value of the workfunctions and then draw the different material in
the junction with respect to the vacuum level as given in Fig.1. When we bring these materials into contact, electrons
will diffuse from the material with the higher lying Fermi level to the material with the lower lying Fermi level in order
to align the Fermi levels for material in contact without applied external bias. In the case drawn in Fig.1 this means that
electrons will diffuse from the semiconductor to the metal. The diffusion of electrons from semiconductor to metal will
create an internal electric field across the junction that aims to induce a flow of electrons in the opposite direction to the
diffusion electrons (in order to make the net current zero as required in an unbiased junction). Thus in fig.1 the internal
electric field caused by diffusion is pointing from the semiconductor to the metal. As a consequence E
c
, E
i
and E
v
will
16
See EE2 Devices and Fields
17
Note that diffusion can happen because of concentration gradients but also because of gradients in energy in which
the electrons/holes are found.
23
all have a gradient such that potential energy is higher at the junction and decreases towards the semiconductor. This
results in an energy band diagram given in fig.2. The magnitude of the internal electric field is defined by the
workfunction difference between the metal and the semiconductor.
Figure 2: The metalsemiconductor junction of Fig.1 in contact. Diffusion of electrons from the semiconductor to the
metal has left the semiconductor near the junction with less electrons than in the bulk far from the junction.
Depending on the relationship between the workfunctions of the material that make the junction, the band bending at
the junction will be different and as a consequence we can expect the different metalsemiconductor junctions to react
differently in response to an applied voltage. In fact two categories of junctions exist: one that causes a decrease of the
majority carriers at the junction (as in fig.2) – called depletion – and one that causes an increase in majority carrier at
the junction – called accumulation. These two cases are referred respectively as a Schottky contact and an Ohmic
contact. We take a closer look into these junctions in the figure below.
Ohmic contact
In figure 3 we combine a metal with a workfunction φ
m
with a ntype semiconductor with a function φ
s
, with φ
m
< φ
s
.
Thus electrons will diffuse from the metal to the semiconductor. This causes an accumulation of majority carriers –
electrons – near the junction and the bands bend down towards the junction. This gives an ohmic contact on an ntype
semiconductor.
Figure 3: left: metal and semiconductor before contact draw with respect to the vacuum level (not drawn). Right:
metalsemiconductor junction in contact. Top: gives the charge accumulation near the junction, bottom: gives the
energy band diagram.
In order to find the characteristic of an ohmic contact an external voltage needs to be applied. Due the initial diffusion,
an internal electric field exists across the junction that is pointing from the metal to the semiconductor. When applying
an external bias, the electric field due to this bias will be superimposed on the internal electric field. If the external
electric field is in the same direction as the internal electric field, the bands will bend further down in energy near the
junction. When the external electric field is opposing the internal electric field, the band bending will decrease and with
sufficiently large external electric fields, turn around.
Thus the net electric field across the junction is the vector sum of the internal and external electric field. As a voltage is
applied externally and thus a net current can be flowing, the Fermi level will not be constant across the junction.
In Figure 4, the above metalsemiconductor junction is drawn under a positive and negative voltage on the metal. When
a positive voltage is applied on the metal, the Fermi level of the metal is decreasing with respect to the Fermi level in
the semiconductor. When a negative voltage is applied on the metal, the metal Fermi level is increasing compared to the
semiconductor Fermi level. The distance between the two Fermi levels is proportional to the applied voltage. In the case
of a positive voltage, the Fermi level of the metal comes lower in energy than the Fermi level of the semiconductor.
This means that the higher lying electrons (in energy) in the semiconductor “see” empty states at the other side of the
junction and thus a current can flow. In good ohmic contacts the work function different generates only a small amount
of band bending (metal is well chosen with a workfunction close to that of the semiconductor). Then a small voltage
will be sufficient for the higher lying electrons in the metal to cross the junction and generate current. This makes this
junction an ohmic contact where no severe inhibition of carrier flow occurs. When doping the semiconductor more
heavily ntype, the ohmic contact will improve.
E
c
E
F
E
v
E
metal semiconductor
metalsemiconductor junction
E
Fm
E
Fs
E
c
E
v
metal ntype
E
F
+
+


metal p
E
c
E
v
ohmic
contact
24
Figure 4: Top: the metalsemiconductor junctions under zero bias. For good ohmic contact the band bending should be
small. Left: a positive potential on the metal makes it easy for the electrons in the semiconductor to cross the junction to
the side to which they are attracted based on electrostatics
18
. Right: a positive potential on the metal decreases the
band bending such that electrons can easily cross the junction to the side to which they are attracted based on
electrostatics.
Note in fig.4 that the Fermi levels are no longer aligned and are now notated with m and s at opposite sides of the
junction. Far away from the junction these Fermi levels become the same as before the voltage was applied (EF lies at a
distance from the band determined by the doping density), within the region where an electric field exist (band bending)
the Fermi levels become quasi Fermi levels and do not retain the same meaning as E
F
before contact. As a result of the
uninhibited flow of carriers, the currentvoltage characteristic is linear and the relation between the current and the
voltage is given by Ohm’s law: V=RI with R the resistance of the contact. (see fig.5).
I
V
Figure 5: the currentvoltage characteristic of an ohmic contact. The slope gives the ohmic contact reistance.
Schottky contact
In figure 6 we combine a metal and an ntype semiconductor with φ
m
> φ
s
Thus electrons will diffuse from the
semiconductor to the metal and holes will diffuse from the metal to the semiconductor. This causes a depletion of
majority carriers – electrons – near the junction and the bands bend up towards the junction. This gives a Schottky
contact on an ntype semiconductor.
Figure 6: left: metal and semiconductor before contact draw with respect to the vacuum level (not drawn). Right:
metalsemiconductor junction in contact. Top: gives the charge accumulation near the junction, bottom: gives the
energy band diagram.
18
A positive potential attracts electrons and a negative potential attracts holes.
Ec
EF
Ev
Eint
+ 
Eext
Ec
EFs
Ev
Etot
eVext
Vext=0
Vext
Vext>0
+ 
Eext
Ec
EFs
Ev
Etot
eVext
Vext
Vext<0
e

roll down the hill
EFm
EFm
barrier cancels e

diffusion from m → s
e

roll down the hill
metal

semiconductor junction
E
F
m
E
F
s
E
c
E
v
metal
n
type
E
F


+
+
metal
n
E
c
E
v
Schottky
contact
25
Figure 7: The Schottky contact under biasing conditions. When a positive voltage is applied to the metal, the potential
barrier at the junction is lowered and more electrons can diffuse across the junction. When a negative potential is
applied on the metal, the potential barrier at the junction is increasing and the electrons in the metal do not have
enough energy to cross this barrier. Electron diffusion is cancelled and no current can flow.
Figure 7 shows the energy band diagram of the Schottky contact under different biasing conditions. The influence of the
voltage on the metal is to increase or decrease the potential barrier against carrier flow. Under “forward” bias the
potential barrier is decreased and carrier can diffuse across the junction whilst under “reverse” bias, the potential barrier
increases and stop carrier diffusion.
As a consequence the Schottky contact is a rectifier. This means that current is flowing in one bias direction, but is
blocked in the other bias direction. The currentvoltage characteristics of the Schottky contact is given in fig.8.
Currentvoltage characteristics:
I
V
Figure 8: The current voltage characteristic of a Schottky contact on an ntype semiconductor.
A better insight into the interpretation of potential barriers acting against current flow that would be expected based on
electrostatic principles only can be found using figure 9. In fig.9 ntype Schottky contact is drawn. One feature is that
near the junction the semiconductor is depleted of mobile carriers since all the electrons are repelled. When no external
bias is applied then the amount of carriers that can diffuse across the barrier is equal to the amount of carriers that is
drifting back as a consequence of the internal electric field. When this field across the junction is decreased, the barrier
decreases and the drift does not compensate the diffusion any more, thus a net current can flow. In the bulk of the
semiconductor the carrier concentration as a function of energy is plotted together with a decrease of the band bending
at the junction due to the applied external electric field (fig.9 right). We see that now a certain amount large amount of
carriers has a sufficiently high energy to cross the potential barrier. Note that underneath the E
c
line near the junction,
there are no states (forbidden gap) thus in a pure semiconductor no carriers can cross this region (in quantum
mechanics, when the width of this forbidden region is small, quantum mechanical tunnelling can occur
19
). Thus only the
carriers with an energy higher than the maximum of E
c
can diffuse across the junction and deliver current (see n
3
).
19
See Advanced electronic devices in the third year.
E
E
E
E
int
+ 
E
ext
E
c
E
F
E
v
E
tot
eV
ext
V
ext
=0
V
ext
V
ext
>0
+ 
E
ext
E
c
E
F
E
v
E
tot
eV
ext

V
ext
V
ext
<0
e(φ
m
φ
s
)
e(φ
m
φ
s
)eV
ext
e(φ
m
φ
s
)+eV
ext
26
2. Metaloxidesemiconductor junctions
An important junction, that makes the foundation of the MOSFET, is the metaloxidesemiconductor junction or MOS.
In this junction an insulator, SiO2 is sandwiched between the metal and the semiconductor. The oxide will be treated as
a perfect insulator and will thus stop any currents flowing through. The approach for drawing the energy band diagrams
is the same as for the previous junctions. First draw the energy band of each component separately with the Fermi level
referred to the vacuum level. When the different materials are brought into contact the Fermi levels must align. This
happens via a redistribution of the carriers but without any effective transport of carriers possible through the junction.
Again there will be a potential drop across the oxide and semiconductor that is caused by the depletion or accumulation
of the carriers near the oxidesemiconductor junction. This potential drop will be equal to the difference between the
semiconductor and metal workfunction. An example of a MOS with φ
s
>φ
m
and a ptype semiconductor is given in figure
10.
Figure 10: The energy band diagram of an MOS on a ptype semiconductor with dissimilar workfunctions. Left before
contact, right after contact.
Note: the work functions of the materials do not change upon contact. d is the depletion width caused by the work
function difference between the metal and the semiconductor.
To determine the depletion width, we take a look at the energy band diagram of the semiconductor only, given in fig.11.
Ec
EF
Ev
metal semiconductor
Energy
Ec
EFs
n1
n2
n3
Density of electrons at each energy
value. Lots of electrons close to Ec but
the number is exponentially
decreasing with increasing energy.
Potential barrier to electrons
intending to traverse to the
metal
EFm
V+
Forbidden band, no electrons can travel
through the wide forbidden band
distance
Only these electrons have
sufficient energy not to have to go
through the forbidden band. Few
electrons>small current.
metaloxidesemiconductor
E
F
m
E
F
s
E
c
s
E
vs
metal ptype
E
F
E
cs
E
vs
oxide
E
c
o
E
v o
d
E
co
E
v o
E
vac
qφ
m qφ
s
qφ
m
qφ
s
E
vac
Figure 9: Left energy band diagram under zero bias. Right energy band diagram under bias. The density of electrons as
a function of energy is also given
27
Figure 11: Energy band diagram of the semiconductor only. q=e.
Definition of parameters. E
i
is the intrinsic level and is defined via:
The intrinsic level will bend as a function of applied voltage. φ
F
is the Fermi potential (
( )
e
E E
F i
−
= in bulk) and φ
s
the
surface potential (
( )
e
E E
surface i bulk i
−
= ). The depletion width d will be a function of φ
s
(
A
s Si
eN
d
φ ε ε
0
2
= , see pn
junctions for a more detailed derivation of depletion widths). The surface potential is dependent on both the work
function difference and the applied voltage on the metal.
Note that the structure metalinsulatordoped semiconductor (which can be regarded as a conducting material) is
similar to a parallel plate capacitor (see Fields course). The metal on the MOS is regularly called the gate because of
its close relation with the MOSFET.
Voltage applied on MOS
E
F
E
cs
E
vs
E
co
E
vo
E
Fm
qV
+
+ +
m o s
V<0 E
hole accumulation
E
F
E
cs
E
vs
E
co
E
vo
E
Fm
qV
m o s
V>0 E
+ +
hole depletion
E
F
E
cs
E
vs
E
co
E
vo
E
Fm
qV
m o s
V>>0 E
strong inversion



+ +
V>V
th
Figure 12: The MOS on a ptype semiconductor under different biasing conditions and the definition of the result of the
biasing condition.
E
c
E
i
E
F
E
v
qφ
F
qφ
s
Oxidesemiconductor interface
( )
( ) kT E E
i
kT E E
i
F i
i F
e n p
e n n
/
/
−
−
=
=
28
With reference to fig.12: When a negative voltage is applied to the gate with respect to the semiconductor then the Fermi
level of the metal will shift up with respect to the Fermi level of the semiconductor. For convenience one can ground the
semiconductor contact. The electrostatic forces will attract the positively charged holes (of which there are plenty – majority
carriers) to the semiconductor/oxide interface. These holes are accumulating at the interface as they cannot pass through the
oxide. We find the condition of accumulation of majority carriers. The capacitance of this MOS capacitor is then determined
by the oxide thickness.
When a positive voltage is applied to the metal, the electrostatic forces aim to repel the holes – majority carriers – from the
oxide/semiconductor interface. This means that a region is generated that is deplete of mobile holes. The few holes that are in
this region are recombining with the few electrons – minority carriers. We will assume that this region is therefore
completely free of mobile charges. This region increases in with for more negative voltages. The bends are bending down as
a consequence of the applied external electric field. At a certain moment we reach a condition where the distance between the
Fermi level and the conduction band at the oxide/semiconductor interface is equal to the distance of the Fermi level to the
valence band far away from that interface (that is thus where the bulk conditions – the original material conditions – can be
found). The voltage applied to the gate that causes this feature to appear is called the threshold voltage. At that moment, the
density of previously called the minority carriers at the interface is equal to the density of the majority carriers in the bulk of
the material. Surely we cannot call the surface ptype any more, it has been converted into an ntype material near the
oxide/semiconductor interface. This is called inversion. At the point of inversion, the depletion width “d” has reached a
maximum value. The residual electric field is dropped across the inversion region and attracts minority carriers across the
depletion width in to the inversion region. In a MOS capacitor these minority carriers are those that are generated via
electronhole pair generation close to the depletion region edge and can be captured by the field and dragged across to the
inversion layer.
How does this influence the capacitance of the MOS?
We saw that under negative bias, holes are accumulated and the capacitance is determined by the oxide thickness. When we
apply a positive voltage, the region under the oxide is depleted of mobile carriers, thus becomes an insulator. Since the total
insulator thickness increases the MOS capacitance decreases. At the threshold voltage, the depletion width is maximum and
an highly conductive inversion layer is created between the oxide insulator and the maximum depletion width insulator and
thus we find a series connection of two capacitors. Measuring this capacitor would give the characteristic drawn in fig. 13.
Figure 13: The capacitancevoltage characteristic of a MOS on ptype semiconductor.
What remains is to define the threshold voltage, V
th
as the voltage at which point the electron (hole) concentration at the
silicon surface is equal to the hole (electron) concentration in the bulk. This situation is plotted for the ptype MOS in
Figure 14 (only semiconductor band bending shown).
Figure 14: The energy band diagram of the semiconductor from oxide into bulk at the point of threshold.
E
c
E
i
E
F
E
v
eφ
F
eφ
s
=2φ
F
Oxidesemiconductor interface at
threshold
C
V
accumulation
de
pl
eti
on
inversion
V
th
maximum
depletion width
reached
depletion
29
Then E
i
lies as far below E
F
at the surface as it lies above E
F
in the bulk this is expressed by:


¹

\

= =
i
A
F s
n
N
e
kT
inv
ln 2 2φ φ . (1)
Note that whilst the surface is inverted whenever φ
s
>φ
F
, we make the assumption that “real” inversion only happens
when the condition φ
s
=2φ
F
is fulfilled (called strong inversion). Note also that we assume that the oxide is completely
free of imbedded charges, the interface between oxide and semiconductor is perfect and that no current can flow through
the oxide. Thus threshold is reached when φ
s
=2φ
F
. From this knowledge one can derive the expression of the threshold
voltage as a function of material parameters (see 2
nd
year Devices).
F
ox
B
s m th
C
Q
V φ φ φ 2 ) ( +
−
+ − = (2)
The first term at the rhs takes into account the work function different between metal and semiconductor, the second
term takes into account the voltage drop across the depletion region and the last term is due to the inversion condition.
Give, in words, the definition of threshold voltage.
MOS capacitance
Assuming that there are no mobile carriers in the depletion width, we can see that the MOS acts as a parallel plate
capacitor with a capacitance value dependent width of the depletion region and thus on the gate voltage. The maximum
capacitance is for accumulation:
WL C
t
WL
C
ox
ox
ox
= =
ε ε
0
max
(3)
With ε
ox
= 4.0
W width, L length of gate
t
ox
oxide thickness
When the MOS cap. is in depletion the capacitance will decrease due to the increase of the depletion width (see Fields
course).
Maximum depletion occurs when inversion starts, thus:
A
i
A
Si
A
F Si
N e
n
N
kT
eN
d
2
0
0
max
ln
2
2 2

¹

\

= =
ε ε
φ ε ε
(4)
and the minimum capacitance will be a series connection of the oxide and depletion capacitance:
1
0
max
0
1
max
min
2
1 1
− −


¹

\

+


¹

\

+ =
Si SiO
ox
depl ox
d t
WL
C C
WL C
ε ε ε ε
(5)
With ε
Si
= 4.0, ε
0
=8.85 10
12
F/m
Draw the capacitancevoltage characteristics of two MOS capacitors on the same graph. The MOScaps have the same
area, the same oxide thickness, both on a ptype substrate but with different doping densities in the substrate. Point out
what is different and explain why.
3. Semiconductorsemiconductor junctions
Semiconductorsemiconductor junctions can be composed from 1 type of material with different doping type or
density, this is called a homojunction. They can also be composed from a combination of different materials with the
same or different doping type. This is then a heterojunction. Although heterojunctions have become increasingly
important in semiconductor technology, in this course we will only study homojunctions. For more info on
heterojunctions, see 3
rd
year course Advanced Electronic Devices.
Of the homojunctions, the pn junction, also called the pn diode is the most popular. The pn diode is the connection of
two solids of the same kind but with opposite doping type.
The pn diode
pn diodes are fabricated via the implantation of a ptype or an ntype substrate (in VLSI ptype Si substrates are
preferred due to the fact that an nMOSFET is defined on a ptype substrate (see later)) with the opposite carrier type.
The implantation dose is sufficiently higher than the original carrier concentration available. Then ohmic contact are
defined on each side. Note that in current VLSI all contacts will be made on the top separate by SiO
2
.
30
n n n
p
n
p
metal
metal
implantation
n
p
Figure 15: Left: Schematic of the fabrication process of a pn diode. Right: the circuit symbol for a pn diode.
When measuring a pn diode, we find that the currentvoltage characteristic is exponential (very similar to the Schottky
contact). Energy band diagrams are a good tool to explain this rectifying behaviour. Band diagrams are based on some
simple rules that give the relation between diffusion, internal electric fields and band bending – the latter results in a
creation of potential barriers against diffusion of carriers. Sketches of energy bands under an external potential are easy
to derive from the previous when knowing that external electric fields are superimposed on the internal field and thus
change the band bending. An increase in resultant field will lead to a reduction of diffusion, whilst a decrease will allow
more diffusion. Additionally, we can always rely on electrostatics to find out where the carriers want to go to and the
band bending will then indicate if this will be possible or not.
Band diagram of unbiased junction
When bringing an n and a p type material together there is of course a large concentration gradient across the junction:
in the n material there are many more electrons – majority carriers – than in the pmaterial where there are just a few –
minority carriers. And similar for the holes in p and n region.
Note on the distance between the Fermi level and the band edges. In general:
( ) ( )
( ) ( )
kT
E E
c i
kT
E E
c
kT
E E
v i
kT
E E
v
i F c F
F i F v
e N n e N n
e N p e N p
− −
− −
= =
= =
and
and
In ntype semiconductors n » p and since N
C
≈ N
V
this can only be the case if (E
C
E
F
) < (E
F
E
V
) ie E
F
is closer to
the conduction band. For ptype n « p and a similar argument shows that E
F
is closer to the valence band. V
0
is the
contact electrostatic potential or builtin voltage.
Due this massive concentration gradient a diffusion of electrons from n to p and of holes from p to n will occur. Since
there is no bias applied, the net current needs to be zero. We have seen that this causes an internal electric field to be
build up across the junction. The magnitude of the internal electric field will be such that it cancels the diffusion. The
electric field will send electrons back to the nregion and holes back to the pregion. The energy band diagram that
results is given in fig.16.
E
cp
E
F
E
vp
E
g
ptype ntype
E
cn
E
F
E
vn
E
cp
E
F
E
vp
E
g
ptype ntype
E
cn
E
F
E
vn
eV
0
W
0
Figure 16: The energy band diagram of a p and ntype semiconductor before contact (left) and after contact (right).
Note: E
F
constant across unbiased junction. The internal electric field causes a potential barrier with a potential
difference between n and p side equal to V
0
. W
0
is the depletion region.
Since an internal electric field occurs across the junction, charges must be associated to this field. These charges are the
result of the disappearance of mobile carriers from the junction region due to the steady state diffusion that is occurring.
The diffusion of holes from the ptype region leaves the ionised acceptor doping atoms behind. These are negatively
charged since they lost a hole, but also they are fixed in the Si lattice and cannot move. This means that these fixed
ionised charges cannot carry current! Similarly, diffusion of electrons from the ntype region across the junction leaves
behind positively charged donor atoms which are fixed in the lattice. Thus we have fixed charges at opposite sides of
the junctions of opposite character. The internal electric field will point from the positively charged region to the
negatively charge region (and thus uphill in the energy band diagram). The larger the internal field the larger the regions
with fixed ionised charges. This region with fixed ionised charges from which the free charges are removed is called the
depletion region or space charge region.
Thus at zero bias there is a steady flow of carriers due to diffusion and an opposite and equal amount of carriers flow due to
the internal electric field.
p n
31
Particle flow Current
hole diffusion
hole drift
electron diffusion
electron drift
The current due to drift of
carriers under Efield
exactly cancels diffusion
current under zero bias.
Drift current flows under the influence of an electric field (this field can also be internal). Diffusion current flow under
influence of a concentration gradient. Note that the electron currents are opposite the carrier flux as a consequence of the
negative charge of the electrons that is taken into account in the current versus field expression. To prove the “drift cancels
diffusion” reasoning above, take eq. (chapter 1, 28) and find that drift is equal and opposite to diffusion current:
J
h
= p e µ
h
E  e D
h
dp/dx = 0 under zero bias
J
n
= n e µ
e
E + e D
e
dn/dx = 0 under zero bias
drift diffusion
Space charge at junction
p n p n



+
+
+
W
0
builtin
Efield
ve acceptor
ions
+ve donor
ions
depletion region
Figure 17: Depletion region with a width W
0
build up around the junction and depletes a part of the ntype and ptype
material of moving carriers.
W
0
is the depletion width when no external bias is applied. This region is empty of mobile carriers but consists of fixed
ionised doping atoms
20
. These fixed ionised atoms generate an internal electric field. Thus carrier gradient causes
diffusion of mobile carriers which leaves behind fixed ions that induce an electric field that causes drift.
Because the charge density is uniform within each depletion region, we can expect that the electric field strength changes
linearly with distance from the depletion layer edge. Thus E(x) has its extreme at the junction itself.
Derivation of the builtin voltage across a junction, V
0
From the right diagram in figure 16 we can find an expression for the builtin voltage that is associated to the builtin electric
field: eV
0
= E
cp
– E
cn
. The builtin voltage is the difference between the position of the conduction band in the ptype
region and the conduction band in the ntype region. The position of the bands can be derived from the doping concentration
and the position of the Fermi level:
In ntype n
n
≅ N
c
exp (E
cn
E
F
)/kT but also n
n
= N
D
In ptype n
p
≅ N
c
exp (E
cp
E
F
)/kT and n
p
=
n
i
2
N
A
Combining these gives the builtin voltage:


¹

\

=


¹

\

=
2
0
ln ln
i
D A
p
n
n
N N
e
kT
n
n
e
kT
V
(6)
Figure 18: The variation of the builtin voltage V
0
as a function of doping density.
20
The consequence of this approximation will be discussed in the 2
nd
year
V0 (V)
0.7
0.9
10
15
2
i
D A
n
N N
10
10
32
Note:
Holes are majority carriers in ptype material : p
p
Electrons are minority carriers in ptype material : n
p
The subscript indicates the material type.
Calculate the builtin potential of a pn diode with N
D
=10
20
cm
3
and N
A
=10
20
cm
3
. How does this solution compare to
the bandgap of Si? n
i
=1.45 10
10
cm
3
, kT/e=0.026V at room temperature and E
g
(Si)=1.11eV. Sketch the energy band
diagram of this pn junction to help to explain your answer.
We have seen that at zero bias a depletion layer width consistent with the magnitude of the internal electric field is
builtup. When a voltage is applied externally, the external field will be superimposed on the internal field. The
assumption we make here is that we neglect that any of the externally applied voltage will drop across the neutral
regions (this are the n and pregion where no depletion occurred, so they are still the same as bulk). We have also
neglected that any voltage is dropped across the ohmic contacts that must exist at the edges of the neutral regions. This
is the same as assuming that the workfunction of the chosen metal is exactly the same as the workfunction of the
semiconductor and that no interfacial layer such as an oxide exists between metal and semiconductor. In many cases it
is acceptable to just add series resistances to the ideal ohmic contact to give a more realistic picture. Although these
assumptions will lead to valuable methods to extract useful expressions for depletion regions, electric fields and
currents, one should keep in mind that putting the voltage drop across the neutral regions to zero might have
consequences on the interpretation of the total picture behind the operation of semiconductor devices.
In what follows we will assume that the ohmic contacts are ideal and that the externally applied voltage will drop solely
across the depletion region – the resistance of the depletion region is many time higher (no free carriers) than the
resistance of the neutral regions (plenty of free carriers).
We can expect that when the externally applied electric field is opposite to the internal electric field then the depletion
width will decrease as the total field across the junction will have reduced – this is the case in forward bias. In contrast
when the external electric field adds to the internal electric field, the total electric field across the junction will increase
and thus the depletion width that supports this electric field will increase. This is schematically given in fig. 19.
Wo
W<Wo
ptype ntype
W>Wo
ptype
ptype
ntype
ntype
a)
b)
c)
Figure 19: The depletion layer width, W, at (a) zero bias (b) forward bias, and (c) reverse bias
Depletion layer width is calculated using electrostatic theory. w
n
is the depletion width extending in the ndoped region,
w
p
is the depletion width into the pdope region. The total depletion width is the sum of the two. V is the externally
applied voltage. Forward bias: V>0, reverse bias V<0. ε is the permittivity of silicon, value 11.7ε
o
In order to calculate the depletion width, the Poisson equation
21
needs to be solved in each region of the device. The
solution in each region will depend on integration constants that have to be determined via the boundary conditions:
 the electric field should be continuous across the junctions
 the electrostatic potential should be continuous
 charge neutrality should be maintained
Thus we start with the general expression of the Poisson equation which relates the gradient of the electric field to the
local space charge density at any point x :
21
See Fields course (Gauss law in 1D)
33
( )
− +
− + − =
A D
N N n p
e
dx
dE
ε
(7)
This equation has to be written in each part of the semiconductor junction (each part will have a different charge
density). This can be done by using information in fig.20. Note that each region will have homogeneous doping.
p n



+
+
+
W
0






+
+
+
0
W
n
W
p
x
Q

Q
+
Q: charge density
Q

=Q
+
eN
d
+
eN
a

Q(x)
E(x)
x
x
E
max
x
V(x)
density of mobile charge in
depletion layer negligible
fixed ionised charge
in depletion layer
Figure 20: Top: the pn junction with depletion region and neutral regions defined. Second down: the total number of
charges in each region of the diode. The total under of charges in the neutral regions is zero as holes, electrons and
ionised doping atoms cancel each other out. In the depletion region we have assumed no free carriers, so only the
doping atoms are left. These are different at the pside and the nside. Third down: the variation of the electric field. We
have assumed that the electric field is zero in the neutral regions. Bottom: the variation of the electrostatic potential.
The maximum potential at zero bias is the builtin voltage V
0
.
In the depletion region we neglect n and p (no mobile carriers), then we have two regions with constant space charge for
which we can write (abrupt junction) :
( )
( )
elsewhere 0
0 w  when
0 when
p
=
< < − =
< < =
−
+
dx
dE
x N
e
dx
dE
w x N
e
dx
dE
A
n D
ε
ε
(8)
Integrating the left and right hand sides of the equations and assuming that the complete electric field is dropped across
the depletion region (no potential drop across the neutral regions) gives:
( )
( ) 0 w  when dx ) (
0 when dx ) (
p
0
w  0
w
0
0
p
max
n
max
< <
∫
−
=
∫
< <
∫
=
∫
−
+
x N
e
x dE
w x N
e
x dE
A
E
n D
E
ε
ε
Thus
p A n D
w N
e
w N
e
E
ε ε
− = − =
max
(9)
For typical doping concentrations we find E
max
> 10
6
V.m
1
ie the fields within a pn junction are very large. The
34
above equation also shows us that:
p A n D
w N w N = . This is also a consequence of charge neutrality across the depletion
region. This is an important equation, it shows that the depletion region extends in the lowest doped region of the pn
diode. The variation of the electric field as a function of x is found by integrating the equations with undefined
boundaries and then determining the integration constant via the electric field value at the edges of the depletion region.
The boundary conditions are:
0 ) ( ) (
) 0 ( ) 0 (
= = = =
+ → = − →
p n
w x E w x E
x E x E
The solution is then:
( )
( ) 0 w  when ) w x ( ) (
0 when ) w  x ( ) (
p p
n
< < +
−
=
< < =
−
+
x N
e
x E
w x N
e
x E
A
n D
ε
ε
For the case of an abrupt junction the electric field E(x) decreases and increases linearly across the junction.
To find w
n
and w
p
in terms of the applied bias we need to integrate again after introducing the relationship of electric
field and electrostatic potential:
∫
= −
− =
−
n
p
w
w
dx x E V
dx
dV
x E
) (
) (
0
Thus the negative builtin voltage is simply the area underneath the E(x) triangle (see graphs previous page):
2
0
max 0
2
1
thus
then
and
since
2
1
2
1
depl
D A
D D
D A
A depl
n
p n depl
A p D n
depl n D depl
w
N N
N N e
V
N N
N w
w
w w w
N w N w
w w N
e
w E V
+
=
+
=
+ =
=
= − =
ε
ε
When a voltage is applied across the pn diode we assume that all the applied voltage is dropped across the high
resistance depletion layer, and the total voltage across the junction consists of the builtin voltage, V
0
, plus any applied
bias, V. The potential barrier ∆V then becomes:
ie ∆V = V
0
 V where V = applied bias
> 0 in forward bias
< 0 in reverse bias
Using this result with ionised charge equality across the junction, gives:
( )
( ) V V
N N N
N
q
w
V V
N N N
N
q
w
A D A
D r
p
D D A
A r
n
−
+
=
−
+
=
0
2
0
0
2
0
2
2
ε ε
ε ε
As expected w
n
and w
p
are voltage dependent and become smaller under forward bias (V>0) and larger under reverse
bias (V<0).
It turns out that many real junctions have very asymmetric doping levels. If we consider the two limiting cases when
N
A
is much bigger or much smaller than N
D
(this is called a onesided pnjunction) we find that :
If N
A
» N
D
then w
p
« w
n
in this limit w
dep
~ w
n
≅
) (
) ( 2
0 0
D
r
eN
V V − ε ε
If N
A
« N
D
then w
n
« w
p
and in this case w
dep
~ w
p
≅
) (
) ( 2
0 0
A
r
eN
V V − ε ε
Thus we conclude that the depletion extends in the lowest doped region. Thus if we have a heavily doped n
+
surface in
35
contact with a lowly doped p layer, then we can expect the depletion width to extend in the lowest doped region and the width
to be inversely proportional to the doping in this lowest doped region. Also note that the depletion width is dependent on the
builtin voltage (associated to the band bending across the junction). Now go back to the depletion width in a MOS capacitor
and see that the equation given is consistent with what we have derived for the onesided pnjunction above.
Derivation of currents in pn diodes
In order to derive the expression for the current in pn junctions we will make some assumptions:
There is no recombination of carriers in the neutral region
There is no recombination, nor generation of carries in the depletion region
The ohmic contacts are ideal
The density of injected minority carriers is far below the density of majority carriers
The externally applied voltage drops completely across the depletion region
* The pn junction under forward bias
W
n
W
p
ptype ntype
depletion regions
neutral region neutral region
+ +
+ +
+ +
+ +
+ +
 
 
 
 
 
fixed donor ions
fixed acceptor ions
E
c
E
v
E
F
e (V  V)
eV
+ +
+
free holes
free electrons
0
V
Figure 21: pn junction under forward bias and the change in the energy band diagram
Forward bias lowers the potential barrier across the junction, therefore more electrons will have an energy higher than
the barrier and cross from n to p and more holes will be able to overcome the barrier and flow from p to n. Remember
that the internal electric field was built up under zero bias in order to compensate for the diffusion of carriers from high
to low concentration (so electrons from n to p and holes from p to n). Now an external bias has been applied that lowers
the total field across the junction, this means that the resulting electric field is not sufficiently large any more to
compensate the diffusion of electrons and holes.
Another way to see is to refer back to fig. 9 in Chapter 1: the carriers that first participate in the current flow are those in
the top of the Fermitail. We can expect an exponential increase of the current due to the exponential increase in density
of carriers with sufficient energy to cross the potential barrier.
In forward bias majority carriers in each region are thus injected across the junction (and across the depletion region)
and end up as minority carriers at the other side of the junction. Note that there are a large amount of these carriers
available to carry the current. This injection of carriers creates an increased minority carrier concentration at the
depletion region edge in each region compared to the bulk value initially available. The ideal metal contacts at the other
hand keep the number of majority carriers and minority carriers exactly the same at what is found for the bulk condition
(thus completely determined by the doping density and the material). This means that minority carrier gradients have
been formed: a high density of electrons at the depletion region edge in the ptype material and a lower bulk value of
minority carriers at the metal contact. Similarly: a high density of holes at the depletion region edge in the ntype region
and a lower bulk value minority carrier concentration at the metal contact. This gradient of minority carriers is very
large and will define the currents that are flowing through the diode (this is because there were only a few minority
carriers available thus any added will make a difference).
Now what about the majority carriers?
Charge neutrality claims that if the minority carrier concentration increases at the depletion region edge, then so must
the majority carrier concentration. But while the increase of minority carrier concentration is important in comparison
with the concentration initially available, the same increase in majority carrier concentration (for the low injection
approximation) is negligible compared to the huge amount of majority carriers that are already available. Thus the
gradient caused is negligible and this implies that the majority carrier current can only be due the existence of a small
electric field in the neutral region. A small field will be able to carry a sufficiently large majority carrier current to the
depletion region edge due to the fact that there are many majority carriers available and
36
field electric carriers of density I × ∝
. As indicated before, neglecting the electric field in the neutral region for the
calculation of the depletion region width was useful but breaks down in the physical interpretation of where the
majority carrier supply is coming from. Notwithstanding this, the approximation leads to very reliable equations.
So whilst the very very small electric field cannot generate a sufficiently large magnitude of minority carrier current to
explain the experimental characteristics, the minority carrier gradient that is created by the injection of carriers across
the reduced potential barrier at the junction is large enough to determine the currents flowing. This minority carrier
current – due to diffusion – is the only way to derive the current for the pn diode based on the knowledge of the material
parameters (it is very difficult if not impossible to derive the small electric field that determines the majority carrier
current from the known parameters).
* The pn junction under reverse bias
E
c
E
v
E
F
eV + + +
free holes
free electrons
e (V + V)
0
W
n
W
p
ptype ntype
neutral region neutral region
+ + +
+ + +
+ + +
+ + +
+ + +
  
  
  
  
  
V
Figure 22: pn junction under reverse bias and the change in the energy band diagram
The reverse bias adds to the builtin voltage increasing the potential barriers, therefore there at no carriers with sufficient
energy to travel across the barrier. However there will be a leakage current due to the very small amount of minority
carriers available in the ptype region that can travel to the ntype region and vice verse. Thus the reverse bias current
will be determined by the amount of minority carriers available close to the depletion region edge. This concentration is
determined by generation in the neutral regions.
To derive the expression for the current we start with drawing the minority carrier concentration in the p and n region
under forward bias (the reverse bias current will result directly from this approach).
When looking at the energy band diagram given in fig. 21 we can derive that the minority carrier concentration that is
due to charge injection across the junction. Remember equation (6) for zero bias:
0
0
0
exp ln
p n p
p
n
n
kT
eV
n n
n
n
e
kT
V = 
¹

\

= →


¹

\

=
with n
p0
the minority carrier concentration in bulk.
Now the barrier has become VV0 thus the associated injected minority carrier concentration is:
( )

¹

\
 −
=
kT
V V e
n n
n p
0
exp '
(7)
under the assumption that the majority carrier concentration didn’t change
22
.
Combining equation (6) and (7) gives (and similar for the injected holes):

¹

\

=

¹

\

=
kT
eV
p p
kT
eV
n n
n n
p p
exp '
exp '
0
0
(8)
Or the injected minority carrier concentration at the depletion region edge of a short pn junction diode under bias
voltage V obeys the relation:
22
Good approximation for low levels of injection. Breaks down for high levels of injection as those occurring in power
devices.
37

¹

\

= =
kT
eV
p
p
n
n
n
n
p
p
exp
'
'
0 0
(9)
In figure 23 the variation of the minority carrier concentration as a function of distance in both regions of the short pn
junction under forward bias is given.
n
p
p
n
= minority electron concentration in
ptype contact at zero bias
= minority hole concentration in
ntype contact at zero bias
p'
n
n'
p
n
p
p
n
ntype
ptype depletion
layer
L
n
L
p
Figure 23: Linear variation of the minority carrier concentration as a function of distance of a short pn diode under
forward bias. Note that the lengths of the neutral regions are chosen to be the diffusion length of the minority carriers.
Any length larger than this diffusion length makes the short diode approximation invalid.
The linear variation of the minority carrier concentration is only valid when no recombination of minority carriers occurs
whilst they diffuse through the neutral regions. The maximum lengths of the neutral regions for which this
approximation is valid are the minority carrier diffusion lengths L
n
and L
p
. The physical interpretation of these lengths
are that they give the average distance an electron can travel in the ptype region without recombining (L
n
) and a hole
can travel in the ntype region without recombining (L
p
). The general expression for the diffusion length is given by:
τ D L =
with D the diffusion constant and τ the average lifetime (is the average time before recombination occurs).
In order to check the validity of the linear variation of the minority carriers we start from the time dependent variation of
the carriers in a semiconductor under influence of a current on (recombination ignored):
For holes this is:
x
x x J x J
e t
p p p
x x x
∆
∆ + −
=
∂
∂
∆ + →
) ( ) (
1
Or in words: the rate of hole buildup is equal to the increase of holes concentration in A x × ∆ per unit time for current
flowing in the x direction through a cross sectional area A.
When x ∆ becomes infinitesimal small and stating that the current is solely due to diffusion current, the continuity
equation becomes:
2
2
2
2
) , (
) , (
x
t x n
D
t
n
x
t x p
D
t
p
n
p
∂
∂
=
∂
∂
∂
∂
=
∂
∂
(10)
and similarly for electrons.
Under steady state injection (DC voltage applied), the time derivative is zero and thus the solution to the second order
differential equation for the minority carrier concentration must be linear. This proves the linear variation of the minority
carrier concentration when recombination is not taken into account.
Due to current continuity throughout the whole structure we can say that the total electron current is due to the diffusion
of electrons in the pdoped region and the total hole current is due to the diffusion of the holes in the ntype region. The
total current through the diode is the sum of the hole and the electron current.
The hole diffusion current is by definition given by the gradient of the holes in the ntype region:
( )
p
n n
h p
h p
L
p p
eAD I
dx
dp
dx
dp
eAD I
−
=
+ < − =
'
direction x in diffuse holes but 0 note
The electron diffusion current is given by the gradient of the electrons in the ptype region:
( )
n
p p
n n
n n
L
n n
eAD I
dx
dn
dx
dn
eAD I
−
=
> =
'
direction x  in diffuse electrons but 0 note
L
n
L
p
38
Thus the total currentvoltage equation is found using eq. (8):
current (leakage) saturation reverse
1
0
0


¹

\

+ =


¹

\

− =
+ =
n
p n
p
n p
kT
eV
tot
n p tot
L
n D
L
p D
eA I
e I I
I I I
(11)
The forward bias current is exponentially dependent on the applied voltage and the reverse leakage current is indeed
defined by the available minority carriers in the bulk.
Figure 24 gives an insight in the minority and majority carrier currents flowing in the diode.
Figure 24: The contribution of the minority and majority carrier current to the total current through the pn junction.
Majority carriers injected across the junction are resupplied via drift through the contact and diffuse to the other
contact through the minority carrier gradient region. The minority carrier gradients determine the total current
completely. The current remains constant in the space charge region because there is no recombination no generation
of carriers (assumption).
Derive the approximate expression of the current in a pn junction with a heavily doped pregion (the doping density in
the pregion is 103 times larger than in the nregion.
Small signal equivalent circuit of a pn diode.
pn diodes are devices with a nonlinear currentvoltage characteristic. In order to estimate their influence in circuits and
systems where DC or small AC signal are applied, the diode response needs to be linearised
23
. This can be done by
proposing an equivalent circuit for the diode (each little segment of the nonlinear curve for very small voltage variations
looks linear).
In this course we will derive the equivalent circuit of the pn diode based on the physical principles behind the flow of
carriers.
In fig. 25 a cross sectional view of a diode is given:
Figure 25: a cross sectional view of the pn diode consisting of two ohmic contacts, two doped semiconductor regions
with opposite doping and a depletion region with a voltage dependent width.
The influence of the contacts and the doped semiconductor regions can be represented via a series resistance across
which a certain amount of the applied voltage will be dropped. The value of the series resistance can be determined via
measurements.
The slope of the exponential currentvoltage characteristic is dependent on the chosen biasing condition. This slope can
23
via the traditional techniques that are taught in the Analysis of Circuit course
junction
Depletion region
current
p
+
region nregion
contact
contact
I
n
I
p
I
tot
Minority carrier diffusion currents
Majority carrier drift currents
Remain constant in
space charge region.
nSi pSi
depletion region contact contact
39
be represented via a differential conductance that is determined by:
dV
dI
g
d
=
Introducing the diode current expression, gives:
kT
eI
dV
kT
eV
dI
g
d
≈


¹

\

− 
¹

\

=
1 exp
0
for sufficient forward bias
As with the MOS capacitor, the depletion width sandwiched between two doped semiconductor regions behave as a
parallel plate capacitance. Moreover the depletion width will change quite dramatically in reverse bias as a function of
applied voltage. As a consequence this will be represented in the equivalent circuit via a capacitor given by:
A
V W
C
Si
j
) (
0
ε ε
=
With W the depletion width as a function of applied voltage and A the cross sectional area of the diode.
Not immediately obvious is the existence of another capacitance that is due to the minority carriers that are present in the
neutral region in forward bias and the fact the this concentration of charges is changing as a function of forward bias
voltage. As the forward bias voltage increases, the injected minority carrier concentration at the depletion region edge
increases and thus the total excess of minority carriers increases. This variation of the charge as a function of voltage is
of course also a capacitance.
( ) ( )
( )I
kT
e
dV D
dI L
dV D
dI L
dV
L n n d
dV
L p p d
e
dV
dQ
C
n p
n
n n
p
p p n p p p n n
d
τ τ + =
(
(
¸
(
¸
+ =
(
¸
(
¸
−
+
−
= =
2 2
1
' '
2
2
2
0 0
The depletion capacitance will be important in reverse bias, whilst the diffusion capacitance is important in forward bias.
The small signal equivalent circuit:
R
s
r = 1/g
d
d
C
Figure 26: small signal equivalent circuit of the pndiode. The capacitance C is the parallel connection of the diffusion
and depletion capacitance.
Some applications of p  n junction diodes
(i) rectification of a.c. signals  see Power Supply Experiment
(ii) Zener diodes for e.g. voltage regulators – see radio design in lab.
(iii) optoelectronic devices:
photodetectors
solar cells
LEDs
Lasers
40
Chapter 3: The MetalOxideSemiconductor Field Effect Transistor – MOSFET
In the previous chapter, we presented devices consisting of 2 contacts. In these devices the currentvoltage and
capacitancevoltage characteristics are fixed by the processing and material parameters. There is only 1 characteristic
(1 IV and 1 CV) associated to these devices. In transistors a third contact is introduced. This contact will control the
current that is flowing between the two other contacts. This third contact will allow onoff switching of electrical
signals – an electronic switch rather than a mechanical switch. And will allow amplification – a small signal on the
third (control) contact will result in a larger signal at the other contact. The third contact can control the current in the
two other contacts or via an electrostatic field (attraction and repulsion of free charged carriers without current
flowing) or via the injection of a small amount of current. The first gives a MOSFET and the second a BJT (bipolar
transistor (see later). Transistors are characterised by a set of currentvoltage graphs, one IV graph per control signal
value. This increased functionality of 3terminal devices has made them most popular in integrated circuits (ICs).
In order to understand the operation of the MOSFET, it is essential to understand the workings of a MOS capacitor
(see notes chapter 2, section 2 p.26). The MOS cap makes the control contact on a MOSFET.
1. Fabrication
Fabrication of Si MOSFETs is a massive industry with big companies such as Intel, IBM, AMD and Toshiba the main
drivers behind the technological field. Fabrication of MOSFETs (and other semiconductor devices) is based on the
repetition of 4 important fabrication steps within an ultra clean environment – clean room.
The 4 steps are:
 lithography (determination of protected and unprotected areas)
 etching (chemical and chemical/mechanical removal of material)
 oxidation at high temperatures (~1000°C) in pure O
2
 deposition of metals, insulators, ….)
All semiconductor devices consist of 3 types of materials: semiconductors (Si, Ge, GaAs,…), metals (Al, Ti, W,
Au…) and insulators (SiO
2
, Si
3
N
4
,…). The number of metal layers in an IC (e.g. the processor in your computers) is at
the moment as high as 10, each separated by insulators.
These IC’s, which consists of a billion transistors, are then packaged intro a chip carrier for protection and easy
connection to the external world.
Figure 1: Left a microscope picture of IBM's PPC 970 die (from
http://www.theinquirer.net/images/articles/ppc970.jpg) this IC consists of areas with memories, busses, etc. The
different colours are due to the different thicknesses and types of insulators, and due to metal pads. Right: What one
buys/sees after packaging – a “black” box.
In this course we’ll take a look at one MOSFET only and we will aim to understand the essential material needed and
the physical processes behind conduction.
41
SiO
2
~ 50 nm thick
Drain
Contact
Source
Contact
Gate
Contact
L = 0.1  10µm
ptype Si body
n+ Drain n+ Source
channel
Figure 2: A schematic crosssection of a MOSFET
The two contacts between which the currents are flowing are called the source (sourcing of carriers) and the drain
(draining of carriers) contact. These are Ohmic contacts made on heavily doped (indicated via the superscript + next to
the doping type) semiconductor to make an as ideal contact as possible. Any influence of the contact will be taken into
account via a resistance, if necessary. In this particular example the doping in the contacts is ntype and is opposite to
the doping in the substrate (body, bulk). The substrate is a ~500 µm thick Si wafer (polished disks of Si) on which the
surface is modified via the fabrication steps (processing steps) to make devices. The depth to which the substrate is
changed depends on the technology. For large gate lengths this depth will be down to 500nm, for short gate length (90
nm, 45 nm technology is the near future/current process) this depth reduces to 2050 nm.
In between the Ohmic contacts is the control contact – called the gate. The gate consists of a MOS capacitor thus a
thin high quality SiO
2
insulator on Si and a metal or heavily doped polySi on top of the oxide. The success of the
MOSFET is completely due to the success in fabricating extremely high quality gate oxides. In this course we will
assume that the oxide is a perfect insulator. The length of this gate is the distance between the source and drain contact
in fig.2. This length is parameter that has an important influence on the speed of the MOSFETs.
The structure given in fig.2 will results in an nchannel, enhancement mode MOSFET.
2. Functioning of MOSFETs
In a MOSFET the conduction between DRAIN and SOURCE is controlled by the voltage applied to the GATE. With
reference to fig.2 and based on the knowledge of the MOS capacitor the operation of the MOSFET can be explained as
follows: as the gate voltage increases from zero, holes (majority carriers in the bulk) are first repelled from the channel
region under the gate (depletion of majority carriers) thus a depletion region is built underneath the gate oxide between
the source and the drain. Further increase beyond the threshold voltage causes accumulation of electrons to the
surface, forming the conducting channel between source and drain. (inversion). Thus seen from gate into bulk, at
voltages larger than the threshold voltage first a region with free electrons is found, followed by a depletion region
without mobile carriers, followed by the ptype region of the substrate. Seen from source to drain, through the channel,
at inversion, an n+ region is followed by an n region and then by an n+ region. In contrast, at zero gate voltage an n+
region is followed by a p region followed by an n+ region. There clearly exist pn junctions between the source and
drain that disappear when the gate voltage becomes larger than the threshold voltage. Thus the influence of the gate
voltage on the sourcechannel and drainchannel pn junctions is to lower the potential barriers between contact and
channel.
Draw the energy band diagram of an n+ – p – n+ junction in Si and compare this to the energy band diagram of an n+
– n – n+ junction in Si. What happened to the potential barriers? To which gate bias condition refers each of the band
diagrams?
* Voltage conventions
Terminal voltages are usually by convention quoted relative to the source, e.g. V
DS
is the Drain voltage relative to
Source. V
DS
is conventionally POSITIVE in an nchannel transistor. The body, or substrate, is normally connected to
the source. This ensures that the drainbody pn junction is always reversebiased, thus isolating the drain from the
source in the absence of a positive gate voltage. The source is normally grounded. The gate voltage is also applied
between gate and source: V
GS
is the Gate voltage relative to Source.
There exist different types of MOSFETs depending on the type of carriers available in the channel and dependent on
the existence or not of a channel for zero gate voltage.
(i) p – channel – pMOS: inversion layer consists of holes and consequently current is carried by holes in the
channel
(ii) n – channel – nMOS: inversion layer consists of electrons and thus current carried by electrons in the
channel
of which, each type can be either
42
a) enhancement mode (normallyoff, will not conduct at V
GS
= 0)
b) depletion mode (normallyon, conducts at V
GS
= 0)
Draw a schematic cross section of a depletion mode pMOS and determine the sign of the threshold voltage.
Discussion of an nchannel enhancement mode MOSFET with no source drain bias applied.
V
DS
= 0
V
GS
Source Drain
SiO
2
t
ox
Gate
+

Figure 3: Enhancement mode nMOS with gate biasing but without drain biasing
With V
DS
= 0V no current flows in the structure when the gate oxide is ideal (no current through the gate contact).
The device behaves like a capacitor when the voltage V
GS
is varied. There are three different cases to consider:
i) When V
GS
< V
th
no conducting channel exists.
This is when the MOS capacitor is in depletion or accumulation. The smallsignal capacitance of the gate contact
depends on voltage V
GS
.
ii) When V
GS
= V
th
, an inversion layer is being formed. Then the MOS capacitance is at its minimum. Note that at
VGS=Vth the density of inversion charge in the channel is equal to the density of doping in the substrate. The charge
of carriers in channel and substrate after inversion is opposite.
iii) When V
GS
> V
th
the gate attracts more electrons to form a conducting channel (density of inversion charge is now
larger than the density of doping atoms in the substrate), which forms the lower "plate" of the capacitor. This is the
condition for strong inversion.
As in a parallel plate capacitor, increasing the amount of charges on the metal of the capacitor, increases the amount of
opposite charges at the opposite side of the insulator with the same amount. Thus increasing V
GS
beyond V
th
must
results in an extra charge. Remembering
dV
dQ
C =
with Q the number of charges and V the applied voltage gives the
number of charges on the gate electrode as:
( )
th GS
V V C Q − =
(1)
Assuming that the charge in the channel is zero when V
GS
=V
th
, a charge equal to Q must then be present in the
channel. This charge is carried by the electrons in the channel.
Figure 4: The influence of the gate voltage on the energy band diagram of an nMOS drawn from the source to the
drain through the channel region under the gate oxide. With increasing gate voltage, the channel region turns ntype
and the potential barrier at the contactchannel interfaces lowers.
Distance from source to drain
Energy
E
F
source channel drain
V
GS
E
c
E
v
43
Derivation of the Drain Current Equation for nchannel MOSFET
V
DS
V
GS
Source Drain
SiO
2
t
ox
Gate
x
z
y into
paper
x=0
x=L
Figure 5: Enhancement mode nMOS with gate biasing and drain biasing
As shown previously, the inversion charge at the Si/SiO
2
interface is given by:
( )
th GS ox C
V V C Q − − =
when V
DS
= 0 (2)
Q
C
is the charge per unit area carried by electrons in the channel (therefore the negative sign). The area is the area of
the gate (gate length x gate width).
C
ox
is the capacitance per unit area and is called the oxide capacitance.
thickness oxide the with
0
ox
ox
ox
ox
t
t
C
ε ε
=
But when V
DS
>0, the voltage across the gate/oxide/channel sandwich varies at different points in the channel between
the source and drain. If the potential at a point x along the channel relative to the source is V(x) then the voltage there
across the oxide capacitance is V
GS
 V(x). Thus the voltage across the gate oxide at the source side is VGS and the
voltage across the gate oxide at the drain side is V
GS
V
DS
=V
GD
which smaller than V
GS
for positive drain voltages..
Then the charge per unit area in the channel at the some point x is given by:
( )
th GS C c
V x V V C x Q − − − = ) ( ) (
for V
DS
> 0 (3)
Once the region underneath the gate oxide is inverted (strong inversion), the pn diodes that existed between the channel
and the ohmic contact regions will have disappeared. Looking from the source towards the drain through the channel we
see a ntype region contacted by two ideal contacts. When applying a voltage across this structure from source to drain
we expect only current of electrons (now the majority carriers in each region). Since in strong inversion the minority
carriers are unimportant, the current through the inverted channel will be via drift only. Therefore the MOSFET is often
called a majority carrier device. It is unipolar as only the majority carriers are of influence on the current. If the width of
the channel is W (in the ydirection), the amount of charge passing the point x per second is Q
C
Wv
e
(see p.13) and the
current flowing from drain to source is:
e C DS
Wv Q I − = (4)
With v
e
, the velocity of the electrons in the inverted channel region.
The horizontal electric field strength at the point x, is dV(x)/dx and the electron drift velocity v
e
from source to drain
varies with x:
v
e
= µ
e
dV(x)
dx
(5)
Introducing (3) and (5) in (4) gives:
( )
dx
dV
V x V V W C I
th GS e ox DS
− − = ) ( µ
At every point in the channel the drain current is the same, i.e. I
DS
= constant and solving the above differential
equation is straightforward:
( )dV V x V V W C dx I
DS
V
th GS e ox
L
DS
∫ ∫
− − =
0 0
) ( µ
With L the gate length and VDS the voltage applied on the drain with respect to the source a distance L removed from
the high doping implanted ohmic contact region.
44
Hence:
( )
(
¸
(
¸
− − =
2
2
DS
DS th GS
e ox
DS
V
V V V
L
W C
I
µ
(6)
Note: i) This result is only valid for
th GS DS th GS
V V V V V − ≤ > &
ii) The value of the quantity K
L
W C
e ox
2 =
µ
is used by circuit designers. For example in the Analogue
electronics courses.
iii) For the same biasing arrangements, devices with different length to width ratios will carry different
currents.
iv) p and nchannel devices with exactly the same geometry and biasing will carry different currents because
of the different value of the mobility µ of holes and electrons.
The value of the current needs to be determined for
th GS DS
V V V − > . This condition is called the onset of saturation in
MOSFETs. For an ideal MOSFET the current in the saturation region – saturation current – is constant as a function of
applied voltage on the drain.
Figure 6: The influence of the gate voltage (2 values of V
GS
) and drain voltage (1 value of V
DS
) on the energy band
diagram of an nMOS drawn from the source to the drain through the channel region under the gate oxide. Applying a
drain voltage will create an electric field across the channel region → energy bands tilt and e

“roll down the hill”. In
the case V
GS
is well below V
th
(top curve) the potential barrier between source and channel blocks the injection of
electrons into the channel region (where hardly any are available) and thus no current flows. In the case V
GS
is above
V
th
(2
nd
curve down) the potential barrier between source and channel is lowered and injection of electrons into the
channel region occurs. These electrons are then transported through the channel via drift thus a current occurs.
Increasing the drain voltage will increase the slope ot the curve. At saturation the supply of electrons is limited by the
sourcechannel barrier independent on the electric field across the channel and then the current remains constant.
(a) Ideal MOSFET
When V
DS
= V
GS
 V
th
, the potential difference between the gate and the drain end of the channel is now just V
th
and
thus theoretically, no inversion layer exists at the drain end of the channel. In contrast the drain end of the channel is
depleted and thus there are no free electrons near the drain. The channel is said to be pinched off at the drain. This
marks the onset of drain current saturation. To obtain an expression for the drain current in saturation, we use equation
6 to calculate the current with: V
DS
=V
DS
sat
= V
DS
 V
th
ie
( )
2
2
th GS
e ox sat
DS
V V
L
W C
I − =
µ
(7)
The pinched off region of the channel is very resistive, so the additional drain voltage (V
DS
 V
DS
sat
) appears across
it. In an ideal MOSFET the current remains constant as V
DS
is increased further.
Distance from source to drain
Energy
E
FD
source channel drain
E
E
c
E
v
E
FS
45
Figure 7: The family of currentvoltage characteristics for an
enhancement mode nMOS. Each currentvoltage curve
corresponds to one gate voltage value. The higher the gate
voltage the higher the current. The MOSFET reached pinchoff
at different drain voltages dependent on the gate voltage. The
locus of the pinchoff voltage position is given by the grey line.
From the family curves given in fig.5 we see two major operation regimes in the MOSFET. The one at low V
DS
voltages, well below the saturation point (left of the saturation locus) is called the triode region. In this region the
MOSFET behaves as a voltage controlled resistor – control voltage is the gate voltage. The less inversion the higher
the resistance of the channel and thus the shallower the slope of the IV curve. The other region is above the point of
saturation where the MOSFET behaves as a voltage controlled current source.
(b) Real device
As V
DS
is increased above V
DS
sat
= (V
DS
 V
th
) the point along the channel at which the channel pinch off condition
is reached is moving towards the source. Thus the pinchedoff (depleted) region of the channel lengthens towards the
source and the effective gate length (inversion layer length) reduces. The drain current now rises slightly above the
value
sat
DS
I , because when the effective length L of the channel reduces in eq(7), the current increases. The small
increase in current in the saturation region is modelled in two ways. (i) by an output resistance r
0
in the equivalent
circuit, and (ii) mathematically by the introduction into the equation for
sat
DS
I of an Early voltage V
A
,
analogous to that
used for the BJT:
( )


¹

\

+ − =
A
DS
th GS
e ox sat
DS
V
V
V V
L
W C
I 1
2
2
µ
(8)
Figure 8: The family of currentvoltage characteristics for an enhancement
mode nMOS. Each currentvoltage curve corresponds to one gate voltage
value. The saturation current increases due to gate length modulation.
Different types of MOSFETs exist are shown below.
a) Enhancement mode  depletion mode
 structure
gate drain
n
+
ptype Si body
n
+
source gate drain
n
+
ptype Si body
n
+
source
n
Enhancement Depletion
Figure 9: nMOS. Left: enhancement mode. No channel when no gate voltage is applied. Right: depletion mode a
channel exists without application of a gate voltage as a result of a metalsemiconductor work functioning difference
or as a result of implantation of the bulk in the channel region with donor atoms
IDS
VDS
I
D
V
DS
locus of points
at which
V
DS
=V
GS
 V
th
V
GS2
V
GS3
V
GS1
V
GS3
> V
GS2
> V
GS1
0
46
 characteristics
I
D
V
DS
V
GS
6
5
4
3
I
D
V
GS
V
th
I
D
V
DS
V
GS
+1
0
1
2
I
D
V
GS
V
th
Figure 10: The family of currentvoltage characteristics for an enhancement mode nMOS (left) and a depletion mode
nMOS (right).The transfer characteristic I
DS
versus V
GS
for 1 V
DS
is also shown for V
DS
in the saturation region. The
threshold voltage is indicated in both cases.
c) nchannel  pchannel enhancement mode
I
D
V
DS
V
GS
6
5
4
3
n
+
p
n
+
S
G
D
+
+

p
+
n
p
+
S
G
D

I
D
V
DS
V
GS
3
4
5
6
Figure 11: Left: Enhancement mode nMOS. Right: enhancement mode pMOS. Top: structure and bottom: family of IV
curves. Note the biasing condition on the pMOS.
Draw the transfer characteristics for an enhancement and depletion mode pMOS.
One of the strengths of MOSFETs is that it is easy to fabricate the combination of an nMOS and a pMOS in one structure.
This combined structure is called a complementary MOS or CMOS and immediately behaves as an inverter! This makes the
CMOS the device par excellent for digital applications.
Figure 12: left: a schematic cross section of a CMOS. The left part of the structure is the pMOS and the right part (in the p
well) is the nMOS). Right: the CMOS connection for making an inverter. When the input is high the nMOS is on and pMOS is
off and grounds the output, when the input is low the nMOS is off and pMOS is on and connects the signal to VDD. Pictures
taken from http://www.tf.unikiel.de/matwis/amat/elmat_en/kap_5/backbone/r5_1_5.html.
47
3. Small signal equivalent circuit of a MOSFET
Source
C
gs
Gate
r
ds
g v
m gs
Drain
i
d
v
gs
Figure 12: Simple small signal equivalent circuit for a MOSFET that is valid in saturation.
Some important parameters that determine the operation of the MOSFET can be determined via experimental
characterisation and are used to linearise the MOSFET characteristics for use in circuit analysis in case small ac voltages
are applied on the gate.
One of the most important parameters is the transconductance g
m
.
Transconductance, g
m
g
m
= dI
D
/ dV
GS
at constant V
DS
g
m
gives an indication of how well the gate controls the carriers in the channel. The higher g
m
the better the control and
the better the cutoff frequency f
T
. (this is the frequency at which point the current gain disappears).
The output resistance gives an indication of channel length modulation effects and other effects which influence the
character of the saturation current.
r
ds
= 1 / g
ds
= (dI
D
/ dV
DS
)
1
at constant V
GS
The gate capacitance will be an important parameter for digital applications as it determines the gate delay of a digital
circuit. The input (Gate ) Capacitance, C
gs
is given by:
C
gs
≈
W L ε
SiO2
ε
0
t
ox
where W = gate width and L = gate length as before
This expression is actually only valid when no drain voltage is applied. Inn reality C
gs
varies with V
DS
in quite a
complicated fashion, due to changes in the distribution of charge in the channel. At very low drain voltages a good
approximation is to take
2
WL C
C
ox triode
gs
=
In saturation, the input capacitance becomes more:
3
2 WL C
C
ox sat
gs
=
* Amplification in MOSFETs
The channel resistance of a MOSFET in its onstate is very low, such that a small change in V
GS
results in a large
current change.
* Switching in MOSFETs
For digital applications a low channel resistance means that the voltage drop across the MOSFET when operating as a
switch is very small in ON state.
The offcurrents in a MOSFET are also very small and thus in the OFF state the MOSFET will draw only a small
amount of power.
For a CMOS switch, 1 MOSFET is always OFF when the other is ON, so the current is small. The power consumption
in a CMOS switch happens only when switching due to the charging effects of the gate capacitance.
48
Chapter 4: The Bipolar Transistor – BJT
In contrast to the MOSFET that is a majority carrier device where the strong inversion characteristics are determined by
drift, the bipolar junction transistor is a minority carrier device meaning that the minority carriers in the different regions
of the device will determine the current governed by diffusion
24
. The bipolar transistor is a relatively complicated device
when compared to the MOSFET. However under the right assumptions, the calculation of currents simplifies to
calculations of currents in short pn diodes as we have seen in chapter 2. Therefore in the EE1 course we will study BJT
which consist of short diodes only
25
.
1 Principles behind the operation of a BJT
A bipolar transistor consists of a connection of three materials in the form of an npn or a pnp junction. Thus there are
two pn junctions in this device. When looking back at the MOSFET we see that actually the sourcechanneldrain also
forms an npn or pnp junction. The question is therefore, why is the BJT different from the MOSFET. The first
important difference is that the BJT does not have a control contact that is insulated from the middle layer of the device
as in a MOSFET. In contrast the control contact in BJT will be an ohmic contact to the middle layer of the device that is
able to inject current. It is the magnitude of this current that will influence the magnitude of the current between the two
ohmic contacts on the other layer of the BJT. In figure 1 a schematic cross section of a planar BJT is given.
Figure 1: Schematic cross section of a planar npn bipolar transistor on a ptype Si substrate. The control contact is B
(base). The current in the base will control the current between E and C (emitter and collector).
In order to understand why the connection of two pn junctions can give transistor family currentvoltage curves that is
controlled via a current, we will take a closer look at the pn diodes involved.
1. Reverse biased pn junction, I=I
sat
independent of voltage V
The reverse bias current in a pn diode is due to injection of minority carriers across the junction. As the supply of
minority carriers is limited (small amount of minority carriers available) the current is small and constant as a function
of electric field. The current Isat is given by (see eq.(11) Chapter 2.):


¹

\

+ =


¹

\

+ =
n A
n
p D
p
i
n
p n
p
n p
sat
L N
D
L N
D
eAn
L
n D
L
p D
eA I
2
(1)
p n
V
I
V
I
I
sat
Figure 2: pn diode under reverse bias (left) and the offleakage current (right)
24
Note that drift of minority carriers results in very small currents only for any acceptable magnitude of applied
voltage. Thus when minority carriers are important, current will be due to diffusion as in diffusion gradients rather than
absolute values of the carrier density are important.
25
This will be extended in the EE2 course.
p
+
Si
p
+
Si
p Si
n Si
n
+
Si
E
B
C
p Si
49
2. Minority carrier injection by a hypothetical device (hole injector)
If we want to increase the off leakage current in a pn diode, we have to find a method to generate more minority carriers
than already available under bulk conditions. This can for instance be done by shining light with an energy (and thus
associated wavelength – “colour”) larger than the bandgap of the semiconductor (
λ
υ
h
h E = = ). This will create
electron hole pairs and thus increase the minority carrier substantially compared to what was originally available
26
.
Thus increasing minority carrier concentrations n
p
and p
n
in equation (1) through this process, will increase the off
current as illustrated in figure 3.
p n
V
I
V
I
I
sat
hole injector
Figure 3: Reverse biased pn junction with light shining of the device. When the intensity of the light increases, more
minority carriers are generated and the off current I
sat
 increases.
3. Minority carrier injection by a semiconductor device (hole injector)
Remember the pn diode under forward bias. Then majority carriers are injected across the junction: hole from the p
region into the nregion and electrons from the nregion into the pregion. In case we make an asymmetric pn diode
with a heavily doped pregion and a lowly doped nregion. Then the amount of holes injected from p to n is a lot larger
than the amount of electrons injected from n to p.
p tot n p
p n n p
n p
D
i
A
i
D A
A
i
p p
D
i
n n
I I I I
n I p I
p n
N
n
N
n
N N
kT
eV
N
n
kT
eV
n n
kT
eV
N
n
kT
eV
p p
≈ ⇒ >>>
∝ ∝
<<< ⇒ <<< ⇒ >>>

¹

\

= 
¹

\

=

¹

\

= 
¹

\

=
' & '
' '
exp exp '
exp exp '
2 2
2
2
0
0
(2)
Thus a forward biased p
+
n junction is a hole injector. This forward biased p
+
n junction can replace the light used in the
previous section in order to inject holes into the n region of a reverse biased np junction. In that case the holes injected
by the first junction increases the minority carriers in the second layer which will be collected by the reverse biased
junction. The result is given in figure 4.
p
+
n
V
EB
V
BC
I
C
I
E
I
B
I
C
V
BC
p
Emitter
Collector
holes injected holes collected
Base
W
b
I
E
Figure 4: Left a connection of two pn junctions, one p
+
n is forward biased and the second one np is reverse biased. The
output current at C will then be the offcurrent of the second junction as shown right. This is a common base
configuration.
26
It will also increase the majority carriers but since there are already a large amount available to start with (10
17
cm
3
) a
bit more (e.g. 10
3
cm
3
) will not make a big difference. The picture is completely different for minority carriers as
originally there were only about 10
3
cm
3
available.
50
The heavily doped p layer on the forward biased junction is called the emitter. The middle layer is called the base and
the other outer layer, of the reverse biased junction, is called the collector. This structure is a pnp BJT. When the emitter
is heavily doped ntype, the base lowly doped p and the collector lowly doped n then we have an npn transistor. The
main current component in a pnp transistor are holes, in an npn transistor are electrons, but the control current through
the base is respectively electrons and holes (thus opposite to the carriers forming the main output current). In what
follows, we study the pnp rather than the npn BJT, this is solely due to the fact that hole flux and hole current point in
the same direction, and thus simplifying the graphical picture.
An extremely important remark in BJTs is that in order to function properly, the middle region – the base – should be
sufficiently short. If the base is short the minority carriers injected into it from the emitter will all be collected by the
reverse biased collector junction
27
. In what follows we will assume that the base region is thinner than the diffusion
length L of the minority carriers.
Find the two main differences between the layer structure from source to drain through channel of an nMOS (no bias
applied) and an npn BJT.
2 Currents in a short BJT
The currents in a bipolar transistor are determined by diffusion of carries in the different regions similar to the pn diode. We
will investigate each current component I
E
(emitter current), I
C
(collector current) and I
B
(base current) separately (see fig.4
for the definition of the different currents in a BJT) for the transistor is active mode (EB junction forward biased and BC
junction reverse biased)
1. The emitter current I
E
The emitter current is defined as the total current across the emitterbase junction. In forward bias across a pn junction, holes
are injected from the p region to the n region – thus from emitter to base and electrons are injected from the n region to the p
region – thus from base to emitter. The total current across the EB junction is the sum of these two current components:
Thus
EB EB
p n E
I I I + = . If we assume the emitter base is a short diode, then the emitter current can be easily calculated.
Figure 5: Minority carrier concentration in a forward biased emitter base p
+
n junction. The width of the emitter is x
e
and of the base is W
b
. The total emitter current is I
n
+I
p
.
Due to the knowledge on the variation of the minority carrier concentration we can calculate the diffusion currents across
the EB junction:
( )
( )

¹

\

≈
−
=

¹

\

≈
−
=
kT
eV
x
n eAD
x
n n
eAD I
kT
eV
W
p eAD
W
p p
eAD I
EB
e
p n
e
p p
n n
EB
b
n p
b
n n
p p
exp
exp
"
0 0
0
'
'
(3)
Note that the minority carrier concentration in the base at the collector side is determined by the basecollector voltage,
which in active mode is reverse biased (V
BC
<0). For sufficiently large forward bias conditions, the minority carrier
27
A proof will be given in the 2
nd
year course
Minority carrier concentration
Distance in the
direction of current
flow
p
+
n
E B
I
d
e
a
l
o
h
m
i
c
c
o
n
t
a
c
t
B
a
s
e

C
o
l
l
e
c
t
o
r
j
u
n
c
t
i
o
n
p’
n
p”
n
n’
p
n
p0
h+
e
I
p
I
n
V
EB
Determined by
V
BC
x
e
W
b
51
concentration at the EB junction is a lot larger than the minority carrier concentration at the contact and at the BC
junction.
2. The collector current I
C
The reverse biased collector will collect all the minority carriers made available by the base at the BC junction. Since all
the holes injected into the base by the emitter are diffusing from the base to the collector, all these holes will be
collected. The current associated to this hole flow is the hole current that is flowing in the base and is given by the
previously calculated I
p
in eq. (3). On the other hand, the collector junction is reverse biased and there will be a reverse
biased current component that is only due to the BC junction (thus as if not connected to the emitter). This current is the
offleakage current of the reverse biased pn junction given by eq. (1) with minority carrier values as given in the bulk
material (before junction were made). However the pure offleakage current in a pn junction is very small and is
negligible compared to the injected hole current that is flowing in the base.
Therefore the total collector current is:

¹

\

= ≈
kT
eV
W
p eAD
I I
EB
b
n p
p C
exp
0
(4)
3. The base current I
B
In principle is it now very easy to derive the base current from the knowledge of the collector and emitter current. Since
no current can be lost in the device we have to find that the base current has to make up for the difference between the
emitter and collector current following:
I
E
=I
B
+I
C
Figure 6: The currents in a pnp BJT in active mode.
Thus from eq. (3) and (4) we find that

¹

\

= =
kT
eV
x
n eAD
I I
EB
e
p n
n B
exp
0 (5)
Although this approach is completely acceptable, we have lost the physical reason behind the fact the the base current is the
electron current that is escaping from the base. In what follows we will reestablish this physical interpretation.
Holes are injected into the thin base from the forward biased emitter. They diffuse towards the collector where they are
accelerated by the large electric field across the reverse biased base/collector junction and contribute to the collector current.
Figure 7: Different current components that are flowing in the base under the condition of a short base (W
b
shorter than the
diffusion length of the minority carriers that are flowing through the base) in a pnp BJT in active mode.
1) holes reaching the reversebiased collector junction; 2) electrons injected across the forwardbiased emitter junction 3)
thermally generated electrons and holes making up the reverse saturation current of the collector junction.
I
B
= I
B
’
+  I
CBO
where I
B
’
= base current injected into the emitter
I
CBO
= reverse bias leakage current into collector (very small indeed)
IE
IB
IC
p
+
n
p
V
EB
V
BC
I
E
I
C
I
B
h
+
e

1)
2)
3)
52
The base current comes from the fact that the electrons that are disappearing out of the base via the forward bias junction
need to be resupplied in order to avoid losing equilibrium charge conditions. If the carriers would not be resupplied then
equilibrium charge condition can only be obtained by a changing voltage drop across the junctions.
Current gain in the short BJT
The current gain is the ratio of the collector current to the base current and this is given by (see eq. (4) & (5)):
b D n
e A p
EB
b p n
EB
e n p
n
p
B
C
W N D
x N D
kT
eV
W n eAD
kT
eV
x p eAD
I
I
I
I
B
E
=

¹

\


¹

\

≈ = =
exp
exp
0
0
β
(6)
In order to increase the current gain one can: a) increase the doping density of the emitter or decrease the width of the base.
Changes in the other parameters lead to other detrimental effects (e.g. high base resistance when lowering the base doping).
Emitter efficiency in a short BJT
β
γ
1
1
1
1
1
+
=
+
=
+
= =
p
n
p n
p
E
p
I
I
I I
I
I
I
The emitter efficiency describes which part of the total emitter current is used to generate the collector current. Thus for a
good BJT we want β to be large and γ to be equal to 1.
3 Other BJT connections
In the previous we used the common base connection in order to explain the currents in the BJT. This is because in
common base a direct control of the junction biases is available that allows a straightforward connection of the BJT to
the pn junction diodes operations. In most circuits however the common emitter configuration is more popular. In the
common emitter configuration the two bias voltages used in BJT biasing are: one between the emitter and base
(control of I
B
) and one between the emitter and collector. Thus the bias across the basecollector junction can change
with both V
BE
and V
EC
.
active active
I
C
I
C
I
E
I
B
cutoff cutoff
V
CB
V
CE
saturation saturation
Common base connection Common emitter connection
Figure 8: Family curves of the BJT. Note that definition of saturation in the BJT is different from in the MOSFET. The
regions with constant current are the active regions and outside the active region is the saturation region. Left: in
common base connection the control current is the emitter current and no real gain can be found between emitter and
collector current. Right in commonemitter configuration, the base current is the control current and there exist a gain
between the base current and the output current.
Note: in the saturation region the basecollector junction is forward biased.
4 Physics behind the BJT small signal equivalent circuit
Figure 8: Simplified small signal equivalent circuit of
a BJT
B
C
E
r
ce v
be
r
be
g
m
v
be
βi
b
or
i
b i
c
53
Smallsignal current generator β (alternative symbol h
fe
)
β =
dI
C
dI
B
=
i
c
i
b
for high gain we require
(i) small base width W
(ii) large emitter doping, compared to base doping.
Transconductance
g
m
=
i
c
v
be
=
dI
C
dV
BE
Input resistance, r
be
r
be
=
dV
BE
dI
B
=
dV
BE
dI
C
dI
C
dI
B
Note: in a MOSFET the input resistance is infinite (in case of an ideal gate oxide) because no gate current flows for
DC bias conditions. In the BJT the input resistance is determined by the pn diode differential resistance as given on
p39 (chapter 2).
Output resistance, r
ce
r
ce
=
dV
CE
dI
C
In real BJTs the current in active mode is not completely constant but increases slightly with increasing bias voltage.
This feature is due to base width modulation, similar to gate length modulation in MOSFETs. For increasing bias in
the active region, the basecollector junction is increasingly reverse biased. This has the consequence that the depletion
region of the BC junction widens. Therefore the resulting active base width (undepleted base width) is decreasing as
the reverse bias voltage goes up. Since the collector current is indirectly proportional to the active base width, the
current increases with increasing reverse bias across the BC junction.
* Amplification with a BJT
In bipolar transistors the input impedance is low, such that a small input voltage change can result in a high current
change.
first solid state amplifier was invented! That this didn’t happen overnight can be read in e.g. Miracle Month on web page: [http://www.pbs.org/transistor/background1/events/miraclemo.html]. Although a lot smaller than a vacuum tube and operating at lower voltage and current levels, the picture of the first semiconductor transistor in figure 2 (left) directly illuminates why this didn’t lead immediately to a microprocessor (Fig.2 right). A large amount of research on the physics behind the operation of semiconductor devices and into fabrication techniques and tools had to be done before the era of integrated circuits started in 1971. Figure 3 gives an idea of the time it has taken research and industry to get to were we are today in the world of semiconductor technology. Timeline 1930 1940 1950 1960 1970 2000
1928: Lilienfield – FET patent
2000: Nobel Prize for Physics Jack S. Kilby – integrated circuit Z. I. Alferov, H. Kroemer – 1948: Shockley, Bardeen, Brattain – semiconductor heterostructures BJT 1960: Kahng, Atalla – Si MOSFET 1962: Wanlass, Sah, Moore – CMOS 1964: Fairchild / RCA – 1 commercial MOSFETs 1968: Noyce & Moore found Intel 1971: 1 microprocessor, intel4004
st st
Figure 3: A timeline on semiconductor research showing that it took more than 20 years of research to get from a device concept to an integrated circuit. The invention of the transistor was a major event that changed the course of history for electronics, where now technology is pushed forward based on the requirements of computers (and computer games!). The first generation of computers used vacuum tubes; the second generation of computers used a connection between discrete transistors and passive components1 (similar to the circuit you will built for the EE1 radio project at the end of the academic year); the third generation of computers used integrated circuits; and the fourth generation of computers uses microprocessors. The aim of this course is not to find out how to build the circuits (that is taught in the Analysis of Circuits and the Analogue Electronics course), but it is to find out how the basic components of the circuits – the semiconductor devices – work and what can be done to make them better (faster, smaller and operating at reduced power levels).
2. Why study semiconductor devices?
Present day devices are no longer just diodes or transistors, but are either large scale integrated circuits or special purpose components whose design and performance are intimately connected with their physics and processing. For the future engineer it is no longer enough to study the terminal electrical characteristics of the semiconductor device while treating the device itself as a “black box”. Most of the sophistication of modern electronics is hidden in that box, and more and more engineering and scientific effort will be required in device development, design, simulation, production and testing in the future. The devices in fact become subsystems, ready for use for the system engineer. Even he, the user of the devices, will not be able to get the most out of them or contribute towards design of more advanced devices and systems without a good knowledge of the principles underlying their operation and the technology used in manufacturing them. This course therefore aims to give you the basic knowledge to understand simple semiconductor devices and to give you a background that will enable you to understand more complicated structures.
1
Such as resistors, capacitor and inductors 2
3. The course aims
(1) To give insight into the structure of semiconductors (2) To give insight into the physics of semiconductor diodes and transistors. (3) To give models of device behaviour that can be used as a basis for understanding the functioning of other/new semiconductor devices. (4) To give insight into the fabrication methods of diodes and transistors.
4. Objectives
At the end of the course students should be able to: (1) Discuss the characteristics of semiconductors, in particular Si, that make the material suitable for electronic devices (2) Explain qualitatively the mechanisms of electronic conduction in semiconductors, and calculate relevant quantities from given data. (3) Calculate and explain the DC currentvoltage behaviour of diodes and transistors, given their geometry and material properties. (4) Explain the fabrication of simple diodes and transistors.
5. Recommended textbooks
As these course notes are summary notes, summarising the most important issues, the students are strongly recommended to consult/buy one of the following books: "Microelectronic Devices", K.D. Leaver, IC Press, 2nd ed. (This book is written by the former lecturer of this course. The advantage of this book is that it focuses only on those topics discussed in the first and second year devices course in the Electrical and Electronic Engineering Department and that it is affordable. It is well worth buying as there is, in general, a rush on these books in the library near the end of the year.) "Solid State Electronic Devices", B.G. Streetman, Prentice Hall International Editions, 4th ed. (Much of what will be discussed in the course is based on this book. It gives both mathematical as well as more intuitive interpretations of the functioning of the devices discussed in the course. The advantage of this book is that it is closely linked to the course contents but it contains much more info that is taught in the course. There should be an ample supply of this book in the central library, but it is well worth buying if you have genuine interest in the topic. The first chapters might also be helpful for a part of the Engineering materials course.)
6. Course synopsis
Introduction into semiconductor materials A semiconductor is a material with a conductivity level between metals and insulators. Unlike metals, the charges in the semiconductor are more tightly bound to the atoms and although some of these charges travel around in the semiconductor, they are only quasifree as they feel the continuous influence of the surrounding lattice (atoms). Semiconductors’ strength is based on the existence of 2 types of moving charges: negatively charged electrons and positively charged holes. The energetic state of the charges is described using an “energy band model” which is based on sound quantummechanical calculations but which will be introduced in a more informal way in this course. The energy band diagram with its associated bandgap and position of the Fermi level will form the basis of understanding the operation of semiconductor devices. Two different types of currents, drift and diffusion, can occur in a semiconductor. Although these currents normally occur at the same time in “real” devices, in this course we take the liberty to make approximations such that only one of them will occur at any one time. The reasoning behind the approximations is based on the concept of majority and minority carriers. The MOS capacitor and MOSFET Semiconductors become devices the moment they are combined with other types of semiconductors or metals. A semiconductor with two metal contacts becomes a resistor or a Schottky diode depending on the material characteristics of both the semiconductor and the metal. We will look into this kind of metalsemiconductor junctions. Although in traditional textbooks it is common to start with discussing the functioning of a pndiode, in this course we will first focus on what is called majority carrier devices – devices where only one type of carriers play an important role in its operation. A metaloxidesemiconductor (MOS) contact can be used as a capacitor in integrated circuits but is also used in MOS Field Effect Transistors (MOSFETs) to control the conduction in the channel without injecting carriers. We will study the functioning of this device using energy band diagrams and investigate the parameters that influence the operation of this device. 3
The pn junction and BJT Diodes can be made from pn junctions – thus the same material but different doping types at each side. This is a device where both majority and minority carriers play an important role. The current is governed by diffusion of minority carriers rather than by drift of majority carriers as was the case in the MOSFET. We will explore the reason for the rectifying behaviour of these pndiodes. A more complicated npn or pnp junction is the basis for the bipolar junction transistor (BJT). Based on our knowledge of pn junctions, the functioning of a BJT will be described. We will find out how current gain exist in this device and we will find out why BJTs are used in highspeed analogue applications whilst MOSFETs govern the digital world.
7. Contents of the lecture notes
Chapter 1: Semiconductors and their characteristics Chapter 2: Semiconductor junctions Chapter 3: The MetalOxideSemiconductor Field Effect Transistor – MOSFET Chapter 4: The Bipolar Junction Transistor – BJT
4
Chapter 1: Semiconductors and their characteristics
In this chapter we will explain what a semiconductor is and why these materials are interesting for the electronics industry. The reader should be aware that the comprehensive explanation of the physics behind transport in semiconductor devices is based on quantum mechanical calculations and statistics. In this lecture we will introduce some quantum mechanical concepts using intuitive explanations rather than employing the full mathematical approach in order to simplify the physics whilst still delivering the background to understand semiconductor devices. A slightly deeper insight into the quantum mechanical background will be given in the course: EE1.5 Engineering Materials by Dr. W.T. Pike2 in the spring term.
1. Introduction
A semiconductor belongs to the group of materials called solids. A solid consist of atoms bonded together by coulomb attraction. Each atom consist of a nucleus built from neutrons (no charge) and protons (positively charged), surrounded by negatively charged electrons of which the amount is equal to the amount of protons in the nucleus. Thus the bonding of two atoms is caused by the electrostatic force between the nucleus of one atom and the surrounding electrons of the other atoms and vice verse. The Coulomb force, F between the charges is given by:
F=
q1 q 2 4πε 0 r 2
1
With qi (i=1,2) the 2 charges involved in the attraction or repulsion, r the distance between the charges and ε0 the permittivity of free space: ε0.= 8.854 1012 F/m. Bonding begins at a certain distance between the two atoms – the bond length (lattice constant) – where the energy of the solid becomes minimised. Bringing the atoms closer together will dramatically increase the repulsive force between the nuclei and between the surrounding electrons of each atom and is thus unfavourable. Two extreme types of bonding exist: the ionic and the covalent bond. In the ionic bond one atom transfers one or more of its electrons to the other atom. In a covalent bond the electrons are mutually shared. This is illustrated in figure 1.
+ e +
+ +
e
Ionic bond e+ + + e +

Covalent bond
+ +
e
+ +
e
Figure 1: A simplified cartoon of ionic and covalent bonding Now take a look at the periodic table in figure 2. The elements in the periodic table are organised according to their atomic number which is equal to their number of protons and thus electrons. This number increases by one with each element listed, thus different elements have a different number of electrons. Quantum mechanics has shown that these electrons cannot all have the same energy contents (see 2). A more simplified view of an atom (element) was introduced by Niels Bohr in 1913. This model shows the electrons in orbit around the nucleus on different “distances from the nucleus” – shells. Each shell can only contain a certain maximum amount of electrons and the closer the shell to the nucleus the stronger the bond between the nucleus and the electron. On the first shell (“closest to the nucleus”) only 2 electrons are allowed, on the 2nd 8, on the 3rd 18, etc. Although the Borh model with “distances from the nucleus” is not completely correct, it is a useful tool to explain why certain bonds are made. Take the last column of the periodic table (fig.2) with elements such as He2, Ne2,8, Ar2,8,8, Kr2,8,18,8, Xe2,8,18,18,8,…(noble gases)3 We know from chemistry that these elements are chemical inert (do not react, are very stable). On the other hand we notice that the outer shell in these stable atoms (apart from He) has 8 electrons. As a rule of thumb, individual atoms will react in such a way as to fill or empty the outer shell such that it obtains 8 electrons and thus takes the electron configuration of a noble gas. These outer shell electrons are also called valence electrons.
2 3
See teaching on http://www.ee.ic.ac.uk/wtp/ The superscript on the elements give the number of electrons in each shell. 5
the Si lattice needs to be crystalline. As. allows each Si atom in the lattice the noble gas configuration within the solid.1. Si. Therefore the elements in the middle of the periodic table such as C. Cl2. These values are tabulated in textbooks and are the energy required respectively released by losing resp. Thus Na and Cl made an ionic bond. In a bonding process it will be happy to lose one electron to obtain the Ne configuration. Once more electrons have to be transferred.Figure 2: Periodic table To illustrate its influence on bonding. By sharing. large amounts of energy are needed that are not normally available at room temperature. These solids are formed by covalent bonds. Ga. nor perfectly pure (lacking of any “foreign” atom). A more quantitative measure of the ability to donate electrons is called ionisation potential. see figure 3.8. This means that the position of the atoms must be periodic in the whole volume of the material. or otherwise the electron affinity which gives the ability of an element to accept electrons. It is impossible to fabricate semiconductor materials that are perfectly crystalline. Ge.8. Middle: covalent bonding with its neighbours. This type of bond works well with elements that do not have to lose or gain more than 2 max 3 electrons. 6 . The same happens with Ge. Ge. Right: an alternative representation of the covalent bonds in solids. gaining an electron. But material fabricants are making Si very close to perfect and this then allows processors to become faster and cheaper. Si has 4 valence atoms and forms covalent bonds with the neighbouring Si to obtain the noble gas electron configuration. Historically we know that C. Si. In this lecture course we will focus on devices made in Si only.7 on the other hand is happy to receive one electron.… prefer a covalent bond where electrons are shared rather than transferred. In order for the semiconductor to be of interest for mainstream Si technology (as required in the processors of your PC). This concept of electron affinity will be useful later in the course. GaAs are semiconductors. take Na (Sodium): Na2. Ga has 5 valence electrons whilst Al has 3. atoms feel surrounded by 8 valence electrons Figure 3: Left: a Si (silicon) atom with its 4 valence electrons. the covalent bond of these elements also leads to a shared 8electron configuration in the outer shell.
Figure 4 gives a schematic picture of freed electrons in the lattice. At the same time a certain amount of holes (empty spaces) will be filled with electrons. can release some electrons from the covalent bond. 2. 7 . Energy supplied to the semiconductor. At absolute zero temperature: T=0K and without any other excitation none of the electrons will be released from the covalent bonds of the semiconductor lattice. Based on this knowledge an alternative definition of a semiconductor can be given: a semiconductor is a solid material with an electrical conductivity5 between that of a metal and an insulator. A consequence of the freed electrons is that some atoms do not have the noble gas electron configuration any more. Sufficient energy needs to be applied to the lattice in order to break some of the bonds and thus release electrons from the nuclei.g.1975) Conductivity is a parameter that indicates how much current will flow through the solid when a voltage is applied. it looks as if the empty space is travelling through the structure (since the hole is not bound to the atom – it can travel – and is thus free). These released charges are going to roam around the semiconductor in all directions (random motion) due to the thermal energy available. electrons4. A metal can be regarded as made up of lattice ions surrounded by highly mobile negative carriers. Given that the “empty space” is a lack of an electron it behaves as a positively charged carrier. Thus. Walsh (Oxford University press . the thermal energy is sufficient to release some electrons. Electrons released from the covalent bond. The concerned atoms will strive to fill these “empty spaces” with another electron in order to rebuild the 8valence electron configuration. a process called recombination of electrons and holes. Conductivity in semiconductors In metals the highly mobile electrons roam freely within the structure. “Lecture on electrical properties of materials” by L. such as in the form of temperature. Solymar and D. These atoms now miss an electron for a noble gas configuration. At T=0K do you expect the semiconductor to behave as a metal or as an insulator? The conductivity of a semiconductor is dependent on the amount of charged carriers that can participate in conduction. Remember an electron is a negatively charged carrier. The charged carriers that can conduct are only those that are released from the covalent bonds in the lattice. a process that is called generation of electronhole pairs. As illustrated in Figure 4. the freed electrons leave behind “empty spaces”. The “empty spaces” are called holes and since they will be filled by creating an empty space at another atom position. in a semiconductor the electrons are “trapped” by the covalent bonding process – the electrostatic forces between the atoms that form the lattice. At room temperature there will be a sufficient amount of electrons freed from the bonds to enable electrical conduction in the semiconductor. Thus in a metal the electrons roam freely within the confines of the metal boundary.Whilst semiconductors are built of atoms with strong covalent bonding of the valence electrons. However when we increase the temperature. but still a lot less than in metals where the number of electrons involved in the conduction is a lot higher and are more mobile than in semiconductors. thermal energy will generate free electrons and holes (empty spaces). Figure 4: Thermal energy has broken 2 covalent bonds and two electrons are released to roam within the lattice. The amount of free electrons per volume (density of 4 5 See e. metal have a different bonding structure which is more ionic in character.
Again quantum mechanics is needed to. show that free positively charged carriers – holes – exist in semiconductors but is also needed to explain the specific character of these charges. electrons compared to the amount of the other carrier type. Figure 5: Left ntype doping by replacing an amount of Si atoms by atoms with 5 valence electrons.g.carriers) generated via thermal energy is ni= 1. electrons or holes. the foreign element has 5 valence electron. Sb. A foreign element is introduced. that can prove that positive charge exists in semiconductors? Hint: remember the expression for a force. Can you suggest an experiment. when chosen well. Figure 6 gives the variation of the carrier concentration (electrons) in donor doped Si to a level of ND=1015 cm3 as a function of temperature. it has generated a hole. will increase the conductivity of the material. The picture we have sketched here to explain the existence of holes is indeed rather intuitive. Right: ptype doping by replacing an amount of Si atoms by atoms with only 3 valence electrons. Fig. The foreign elements.>) This is a very interesting result as it concludes that in a semiconductor we have not one but two types of charged carriers: the electron with its negative charge and the hole with a positive charge. in order to be useful for devices another method needs to be suggested. B P has 1 more valence electron than Si. Doping is a selective process. using electric and magnetic fields. Only 4 of the 5 valence electrons of the foreign element will bond. foreign elements can be introduced that replace some of the Si atoms in the lattice. B and As doping in Si we can assume. e. with negligible error. Ntype doping levels of up to 1019 cm3 and ptype of up to 1020 cm3 can be introduced without destroying the crystallinity of the Si lattice or the Si electrooptical character of the lattice. Since the foreign element lacks 1 electron in the bond. 8 . Thus the temperature of the materials has to be well above absolute zero for doping to be effective. What is the relationship between the amount of free electrons and free holes created by thermal energy only? (<.g. P e. Figure 5 left demonstrates a doping process in which a surplus amount of electrons is introduced: ntype doping. q in a static electromagnetic field: F = qE + q (v × B ) with E: electric field. For ptype doping the foreign element should only have 3 valence electrons. There exist another way to increase the amount of charges – called doping. For ntype doping.4 1013 cm3 at room temperature.45 1010 cm3 for Si at room temperature. F on a charge. will go into covalent bonding with the surrounding Si lattice. The electron charge is q=e and the hole charge is q=+e with e=1. Or take a look at your Engineering Materials course. that all doping atoms (foreign elements) are ionised and thus all extra introduced carriers free. The number of foreign elements we can introduce in this way can be a lot higher than the amount of intrinsic carriers. B has 1 valence electron less than Si. holes. It remains to be noted that for the doping induced carriers to be free. B: magnetic field and v velocity of the moving charge. typically B is used in Si. We know already that an increase in free charges.g. Temperature is not a sufficient parameter in order to change the conduction of the semiconductor when one wants to use it in microprocessors.5 right shows the situation of ptype doping – a surplus of holes. typically P or Sb is used in Si.6 1019 C. At room temperature for P. for Ge it is: ni= 2.g. A foreign element is introduced. These foreign elements have to sit on the exact lattice positions of the removed Si atoms. ionisation of the foreign element needs to occur. in one semiconductor.=. For another semiconductor it will be a different value e. This means that by using doping we can increase the amount of one type of carriers e. not only. Using a process called ion implantation. leaving one free electron.
pure.e. In this case. The semiconductor is then called an ntype semiconductor. additional nomenclature for the different types of carriers within this semiconductor has been introduced. undoped) semiconductors have a small amount of free carriers at room temperature and therefore have a very low conductivity (e. the conductivity σ of the semiconductor can be changed. The acceptor density notation is NA The density of dopants is normally higher than the intrinsic density of free carriers in the semiconductor.g. The conductivity is directly related to the amount of free carriers in a semiconductor. are introduced in the pure intrinsic semiconductor.e. Within a doped semiconductor we call the 9 . At very high T. all donor atoms ionised ni<ND & n=ND At very low T. Donor doping (donors donate an extra electron) creates an ntype material.g. for Si ni=1.45 1010cm3 whilst doping density introduced in the lattice is >1015cm3) As a consequence of doping. few electronhole pairs generated and donor electrons stay bound to donor atoms 12 0 2 4 6 8 10 1000/T (K1) Figure 6: Free carrier concentration as a function of temperature for ntype Si. In an ntype semiconductor at room temperature the density of electrons will be equal to the doping density n=ND because ND>>ni. increases the conductivity. and holes from acceptor atoms. The donor density notation is ND Acceptor doping creates a ptype material. the doping atoms are called acceptors. The doping atoms (foreign elements) are called donors in this case. doped) semiconductors have better conductivity. diamond). huge electronhole pair generation: ni>ND Free electron density (cm3) 10 17 1015 1013 1011 At moderate T. The semiconductor is then called a ptype semiconductor. Summary: * Intrinsic (i. ptype doping changes the semiconductor into a material with a surplus of holes compared to the amount of electrons. In a ptype semiconductor we find that p>n. donors or acceptors. ni = p i ni is the intrinsic number of electrons pi is the intrinsic number of holes (1) * Extrinsic (i. The number of holes and electrons are equal in an intrinsic semiconductor as the free carriers are generated by thermal energy and thus whilst and electron is created a holes occurs simultaneously (electronhole pairs). (e. If we call the density of electrons n and the density of holes p then in an ntype semiconductor we find that n>p. dopants + intrinsic = extrinsic semiconductor semiconductor Impurities. Thermal energy frees electrons from donor atoms.ntype doping changes the semiconductor into a material with a surplus of electrons compared to the amount of holes. increasing the amount of free carriers. Note that the reciprocal of conductivity is resistivity ρ=1/σ. Therefore the conductivity of an ntype material is directly proportional to the donor doping density: n = ND σ ∝ ND Similar in ptype material p=NA because NA>>pi and thus: (2) p = NA σ ∝ NA (3) Since a surplus of one type of carriers can be established via doping in one semiconductor.
D. Thought experiment Assume we fabricate two resistors in Si using doping implantation. 10 . Resistor R2 is implanted in the same volumes with a density of doping atoms ND2.g. For resistor R1 we implant the Si surface A with P to a depth d with a density of doping atoms ND1. Charge neutrality should of course still be maintained. applying a voltage and measuring the current through the structure. by Dr. The result of the measurements is given in figure 7 below I I − + V R1 R2 V Figure 7: Measured currentvoltage (IV) characteristics of the two resistors. They do not contribute towards current. We note that the current through R1 is smaller than through R2 for the same voltage.carrier type with the larger density the majority carrier. N A ionised acceptor atoms (are negatively charged) and N D ionised donor atoms (are positively charged). (7) *The majority and minority carrier concentrations within one semiconductor are related by: n n p n = ni2 n p p p = ni2 (8) Although these names. (5) Note the subscript n to indicate that we are looking at the carrier densities in an ntype material. Note that the ionised doping atoms are fixed within the lattice and cannot roam around the lattice. After defining two contacts to the implanted Si volumes. * ptype semiconductors Majority carrier concentration. they will be useful in the discussion of devices where both electrons and holes play a role – the socalled bipolar devices. nn = N D ni2 pn = ND pp = N A np = ni2 NA (4) Minority carrier concentration. What is the name of the majority carrier in an ntype semiconductor? There exist relationships between the majority and minority carrier concentration (density) in one semiconductor: * ntype semiconductors Majority carrier concentration. therefore the total number of negative charge = total number of positive charges: − + n + NA = p + ND With n: density of free electrons. p density of free holes. (6) Minority carrier concentration. seem pointless at the moment. the resistance of R1 and R2 can be determined by e. Haigh) then we can determine which of the two Si resistors has the highest doping density. If we take into account Ohms’ law V=R I (see Course Analysis of circuits. whilst the carrier with the lower density is called the minority carrier. majority and minority carrier.
MOSFETs are small and the resistance offered by a MOSFET can be varied electrostatically. Determine the charge of the carrier (. followed by interactions of the carriers with the lattice which makes them lose energy and/or change direction. This motion of carriers under an applied electric field is called drift. Figure 8 illustrates what is happening with 1 carrier. In semiconductors two types of current can exist: drift and diffusion currents. 3.=. and each individual carrier might not take necessarily the same path. but the average direction of movement (velocity) of all the carriers is determined by the applied electric field. as presented in the example above. Currents in semiconductors The interest in semiconductors is based on their ability to generate currents in response to an applied voltage and that somehow we can control these current by changing the material properties itself (e. It needs to be pointed out that Si doped resistors.or +) discussed in figure 8 based on its movement relative to the electric field. Path followed when no electric field is applied Path followed when an electric field is applied E Scattering events Scattering events still occur but the electric field pulls the carrier to the “left”. The random motion can be seen as a process of acceleration of the carriers due to the thermal energy input. because of the large area necessary to make such a resistor and because of its constant value (if one gets it wrong. The drift current caused by charged carriers under an electric field must be proportional to the amount of carriers available and the speed with which these carriers move.g. These free carriers – the ones that are not stuck in the covalent bonds – are always whizzing around in the semiconductor in no particular direction due to the existence of thermal energy ~ with kB = 1. 3. 2 If an electric (or magnetic) field is applied then the motion of the carriers is still under the influence of scattering processes. When an electric field is applied the scattering processes still occur but the average direction the charges go is determined by the direction of the electric field. or there exist a surplus of one type of carriers – the majority carriers – in an extrinsic semiconductor due to doping of the material. It is the aim of this section to generate an understanding into the physical principles behind the existence of the currents.1 Drift currents 3 k BT . Integrated circuit design relies on active devices – the MOSFET to function as a resistor. Newton 2nd law gives the relationship between acceleration dv and electric field E: dt 11 .38 1023 J/K the Boltzman constant and T the temperature in K (equivalent to molecules in a gas). The relationship between the current through and the voltage applied across the semiconductor (device) is not necessarily linear and creates a lot more circuit potential when it is nonlinear. there is no easy solution).Determine the relationship between the doping density of the two resistors of the experiment ND1 <. So although the carriers are moving continuously. doping) or indirectly by external currents or voltages on a device made from a combination of materials with different properties. In previous section we have seen that at room temperature there exist an equal amount of free holes and electrons in an intrinsic semiconductor. Figure 8: Schematic illustration of the random motion of a carrier. In the following we will derive the velocity of the carriers in a semiconductor under an electric field – drift velocity – based on classical formulae and quantum mechanical arguments. This is called elastic (only energy contents is changed) or inelastic scattering (both energy and direction are changed). The amount of carriers available is determined by their doping density.> ND2. is avoided in integrated circuits notwithstanding their simplicity. they move randomly and therefore do not generate a current.
In the quantum mechanical approach electrons and holes are regarded as having both a particle and a wave character (cfr light). Since introducing doping atoms is actually disrupting the periodicity of the lattice. There is of course a difference between an electron in vacuum and an electron in a semiconductor. Ge and GaAs Effective mass7 Si Ge electrons 0.16 Do electrons and holes in one semiconductor have the same mass? If the carriers obey (9) then they would undergo a continuous acceleration in the direction of the electric field. imperfections increase the number of scattering events. However if we want to avoid having to go through rigorous quantum mechanical calculations it would be preferable to stick to this wellknown law. and * * m = m0 mn . Table 1: The average effective mass of electrons and holes in Si. p with m0 the free electron mass.33 0. Moreover no lattice is perfectly pure and thus not perfectly periodic. Thus the speed with which the electron in a semiconductor is travelling will be influenced by the electrostatic forces that act upon them. The deceleration of the carriers due to scattering processes can be mathematically expressed as: dv − v = dt τ GaAs 0. therefore from (9) and (10)8 we find the average net velocity of the carriers in a semiconductor under and electric field: v= qEτ m (11) The material constant: 6 7 See the Engineering Materials course Average effective mass over the degenerate bands 8 gain+loss=0 12 . but that is not the case because the net acceleration of (9) is just balanced by deceleration due to scattering processes to create a steady state condition. this gives temporal changes in the periodic potential of the lattice through which the carriers are travelling. the atoms vibrate around a fixed position due to the thermal energy. b. mn m * the effective mass of the hole.26 (10) The average time between the scattering events is given by τ – the mean free time. electrons with a charge q=e and a mass holes with a charge q=+e and a mass * m n = m0 m n m p = m0 m * p The value of the effective mass for different semiconductors are different and can be found in tables in textbooks for most of the available semiconductors. This model leads to two important conclusions: 1) the electrons cannot have all possible energy values. Remember that the carriers are still under the influence of the thermal energy and are still being scattered. As a m result (9) is still valid when the value for the mass m is replaced by the effective mass of the electron.dv (9) = qE dt This is a well known classical relationship but what is the mass m of a carrier? We know that the mass of a free electron in vacuum is m0=0. These interactions are taken into account through a change in the carrier mass for both electrons and holes. This intuitive approach of introducing a p different mass for the carriers in a semiconductor can also be derived from quantum mechanics6.067 0. because there exist a region of forbidden energies.12 holes 0. 2) there exist two types of carriers: a. Table 1 give a short list of effective masses for different popular semiconductor. Thus in steady state the average gain in velocity (acceleration) is equal to the average loss in velocity (deceleration). Of course in (9) this is not taken into account and in principle makes it inappropriate for use in a situation of a semiconductor.91 1030 kg. This is due to fact that the position of the atoms in the lattice is not constant. The electron in a semiconductor is moving in the neighbourhood of other electrons and more importantly in the neighbourhood of positively charged nuclei.26 0. The carrier within a semiconductor is regarded as only quasi free as it still feels the interactions with the lattice. doping atoms also increase the number of scattering events. One can calculate the propagation of the electron wave through a semiconductor taking into account the periodic electrostatic potential changes of the lattice that will be felt by the carrier wave (the KrönigPenney model).
ρ: ρ = 1 . 13 . thickness (perpendicular to the direction of current flow) 50µm x 10nm. How can you derive the mobility from the vE graph given in Figure 9? Does GaAs have a higher mobility than Si? Why? How do you expect the relationship between the hole mobility of Si and Ge to be (<. we can derive the expression of drift current in semiconductors. The reciprocal of the conductivity σ is the resistivity. σ We are now able to calculate the resistance of a volume of a certain semiconductor doped to a known level. at higher electric fields the characteristics of the scattering processes change and become field dependent such that the linear relationship between drift velocity and electric field no longer exists. Therefore the average net velocity of the carriers in a semiconductor under and electric field – also called the drift velocity – is: v n . Which of the two carrier types in silicon will have the highest velocity? The expression of the drift velocity given in (13) is only valid for low electric fields. width resp. The donor doping density in the Si is 2 1017 cm3 . The values of the doping dependent mobilities can be found in textbooks for different semiconductors.for electrons. Emax is the maximum electric field for which the linear relationship between drift velocity and electric field as given by (13) is valid.>)? As we now know the velocity and the number of carriers. The current density J due to the net drift of carriers is the number of carriers crossing a unit area per unit time multiplied by the charge: J n = qnv n = −env n = enµ n E is the current density (A/cm2) for electrons J p = qpv p = epv p = epµ p E is the current density (A/cm2) for holes The total current is then: J tot = J n + J p = e(nµ n + pµ p )E From Ohm’s law we know J=σ E. v GaAs Si E Emax Figure 9: Drift velocityelectric field curves. Calculate the resistance of a Si volume with the geometry: length in the direction of the current flow 100µm. (13) Sketch the direction of the electron velocity relative to the electric field for both electrons and holes. thus we find the expression for the total conductivity: (14) σ tot = σ n + σ p = e(nµ n + pµ p ) (15) The units for conductivity are (Ω cm)1. How would this resistance compare to that of the same volume of GaAs with the same doping density? Remember that the resistance R is given by: R = ρl with l the length of the resistor (in the direction of current flow) and A the cross A sectional area. p E with + for holes and .µ= eτ m (12) Is called the mobility (in cm2/Vs)and is a material and doping dependent positive value. p = ± µ n .=.
The carriers are going to react as what you would expect from gas molecules.11. when only diffusion is taking place.g.M. than the number of electrons will remain constant (thus the area under each graph in fig. This would generate a local gradient of carriers. Figure 11 gives the variation of the density of electrons as a function of space and time (in 1 dimension only). The charges still whiz around the lattice but the average velocity of the total amount of charges is determined by the electric field and thus a current is generated – drift current. If at a corner of the room a chemical (e.11 remains constant). one that is due to excess carriers. n(x) t1 t3>t2>t1 t2 t3 x t3 n n+∆n x x+∆x linear e. Sze “Physics of Semiconductor Devices. 3. 14 . When taking an infinitesimal small region. With reference to fig. Right: Flux of electrons draw only in the +x direction. As seen before generation of carriers via temperature is always in pairs of electrons and holes and thus the number of electrons and holes caused by generation is equal (the intrinsic carrier concentration at a certain temperature). When we wait long enough the variation of the electrons as a function of space will be zero (no excess and thus also no gradient any more) but its value nonzero. they will diffuse in order to eliminate the excess.Figure 10: The low field mobility as a function of doping concentration for different semiconductors. The same happens with excess carriers in a semiconductor. Assume that a process exists that can create locally an excess of one type of carriers compared to the other.2 Diffusion currents In the above section we have seen that the random motion of the charges can be changed by applying an electric field. This process will cause diffusion currents. In semiconductors another type of current can occur. gas molecules different than nitrogen and oxygen that normally occur in air) the after a while the observer can smell the gas at the other side of the room because the molecules have diffuse throughout the room to cancel the gradient in its density. Taken from S. This diffusion is indeed not completely random any more as it moves the carriers on average in the direction determined by the gradient.flux n(x) x Figure 11: Left: diffusion of an excess of electrons as a function of time and space. the graph is linear.
This extremely small region is as good as linear and therefore we can easily calculate the gradient of this region. we have seen that covalent bonding will occur. If we look at an infinitesimal region (∆x) of space in fig. then in principle. (14). 15 . formulised by Feynman. Recombination is the opposite of generation: during generation an electronhole pair is made. This allows us to calculate the drift currents given by eq. All these electrons have certain energies in relation to their “position”9 from the nucleus (see Fig. see eq. the density of mobile charges at room temperature is equal to the density of the doping atoms (at room temperature). This means that from time to time. However we will use the characteristic lifetime of the carriers to make approximations when discussing devices and treat them as the cutoff value. (4) & (6). The distance the carrier has travelled is then Lp or Ln – the diffusion length of the carrier. during recombination an electronhole pair disappears. When a carrier is travelling in a time span smaller than its life time. Thus the 4 outer shell electrons of each neighbouring Si atom will be shared. This means that the energy of the single Si atoms will be different from the energy of the Si atoms within a lattice. Mathematical description of the energy of electrons and holes The optical and electrical properties of semiconductors are determined by the energy of the free carriers. calculates that the original energy level E0 splits in two different levels E1 and E2. If recombination occurs during the diffusion process then the number of excess carriers lowers and the area under the graphs in fig. This means that in reality some carriers will recombine sooner and some later than these given characteristic times.12a). with a characteristic time τp or τn – the characteristic life time – the excess carriers are going to recombine with the other type of carriers available. they do not recombine. The diffusion current will be proportional to the charge and the number of carriers that flow across a certain position x as a function of time. At x we find a carrier concentration n and at x+∆x we find a carrier concentration n+∆n: thus the carrier gradient is n( x) − n( x + ∆x) ∆n dn =− =− (for ∆x→0) x − ( x + ∆x ) ∆x dx Thus the gradient of the curve of the excess carrier concentration in each point x is its first derivative. the energy of the electrons has changed. This will not be done in this course but you will get a glimpse of quantum mechanics in the spring term course: Engineering Materials. The diffusion constant stands in relation with the mobility following the Einstein equation: Dn. The coupled mode theory.026V @ T = 300 K ) e (18) In order to be able to use equations (16) & (17) we need to know the variation of the excess carrier concentration as a function of distance. If we take 2 Si atoms.11 (right). each one individually surrounded by vacuum will have an energy value E0. But in a Si crystal we have 1023 cm3 atoms which will all interact 9 Bohr model. 4. one higher and one lower than the original single atom energy (see Fig.In real semiconductors however there are two kinds of carriers. This number will be directly proportional to the gradient of the excess carrier concentration. We have already seen that a Si atom has 14 electrons. Again these times τp or τn are average times (average over the huge amount of carriers available in a semiconductor). both electrons and holes.12 b). In the case an excess charge is introduced the number of charges are defined by the introduction process. When we bring the Si atoms together into a Si lattice. We can accept that under these interactions. interactions cause covalent bonding and each atom cannot have the same energy value E0 any more. which will strengthen the more intuitive approach we give here.11 will decrease as a function of increasing diffusion time. What remains to be determined is how recombination will change this number.p is the proportionality constant and is called the diffusion constant. one has to look into the subject of quantum mechanics. Homogeneous doping does not create gradients and thus also no diffusion currents. When we bring the two close together. Remember that when a semiconductor is uniformly doped. p = kT (= 0. The diffusion current due to excess carriers is then − dn( x) − dn( x) dn( x) = −eDn for electrons = eDn dx dx dx − dp ( x) − dp ( x) dp ( x) J p = qD p = + eD p = −eD p for holes dx dx dx J n = qDn (16) (17) Dn. p µ n. then we find an infinitesimal variation of the carrier concentration (∆n). In order to build a robust mathematical picture of the energy relationships of the free carriers.
as there are a lot of free energy levels available. Thus filled energy levels in the conduction band (electrons) can travel and thus carry current. The conduction band is the higher lying energy band with closely spaced energy levels. If we apply a voltage across the semiconductor and thus increase the energy of the electrons than these would have energies within the bandgap. called sp*3 is completely empty (total number of levels are maintained but electrons are redistributed over levels). In between these two regions that are filled with energy levels that can each carry 2 electrons. c) (right) N Si atoms brought together increases the number of energy levels in sp3 to 2N and in sp*3 too. on the semiconductor.energy 3 Completely empty 3s sp3 outer shell electrons 3s 3 3s Valence band 2p 2s 1s ∆E≈1eV energy with their neighbours. this space can be occupied by other electrons gaining energy in the valence band or can be refilled with electrons falling back from the conduction band. In the given situation with complete covalent bonds. This band is completely empty of electrons when the covalent bonding is complete. the valence band energy levels are all completely filled up. In the first case we see an “empty” space travelling. These electrons gain enough energy to occur in the conduction band. 12c. thus the energy levels will split again into 2N filled energy levels and 2N empty energy levels as shown in Fig. 16 . One sp3 energy configuration is completely filled the other one. b) (middle) Energy of the valence electrons when 2 Si atoms are covalently bonded. lies a region where no states (energy levels) occur. Photons (light particles) with an energy transfer their energy to the valence electrons and create electronhole pairs. no current can flow in this system. This is consistent with what we have seen before because current can only be carried by free electrons (not bonded to the atom) which only occur when the covalent bonding is not complete. On each level 2 electrons occur (Pauli’s exclusion principle). Another method to create free electrons (in conduction band) and free holes (in valence band) is by shining light with the correct wavelength. How do electrons gain sufficient energy to cross the bandgap? We have seen that at room temperature there will be a certain amount of electrons that break away from the covalent bond. In energy bands below the valence band are the other electrons that do not take part in the covalent bonding. The difference between the bottom of the conduction band and the top of the valence band is Eg. Of course when an electron jumps to the conduction band it leaves and empty space on an energy level in the valence band. This means that there cannot exist an electron with an energy within this region10. 10 E= h λ = hf > E g will For pure material and ignoring possible quantum mechanical tunnelling processes. λ. in order to generate a current some of the electrons in the valence band should “jump” to the conduction band. Thus the covalent bonding of the valence electrons within the semiconductor lattice has created bands of allowed energies. Conduction band sp*3 energy 3p No energy levels Completely filled 2p 2s 1s do not take part in bonding Figure 12: a) (left) Energy of the 14 electrons in an isolated Si atom. which is an energy region with extremely closely spaced energy levels (states) is completely filled with the valence electrons of all the atoms. then there are 4N valence electrons. When N atoms are brought close together. The valence band. Each energy level (also called a state) can only take two electrons). The same is valid for the empty spaces in the valence band (holes) which can travel and carry current. Since this is forbidden. This will be the hole we have talked about before. Thus. a constant (at constant T) for each semiconductor. The region without energy levels is the forbidden band or bandgap.
At room temperature there are of course a large amount of free electrons and holes and we require knowledge on whether a state at a certain energy is filled or not by an electron or hole. Since there are a large number of carriers and they are continuously moving. At the Fermi level the probability to find an electron is ½. that they behave as waves in a crystal and that they obey the Pauli exclusion principle. Figure 13 gives the FermiDirac distribution function for different temperatures. This has led to the FermiDirac statistics that expresses the probability of finding an electron at an available state at a certain energy E and temperature T: f (E ) = 1 ( ) 1 + exp E − E F kT (19) Where k is the Boltzmann constant: k=1.Both methods given above create the same amount of free electrons as free holes via direct energy transfer to the valence electrons. What is the amount of electrons in the conduction band of Si at absolute zero temperature T=0K? Given the energy band diagram. The quantity EF is the Fermi level.38 1023 J/K and T is the absolute temperature in K. f(E) 1 1/2 T2>T1 T=0K T1 EF E Figure 13: The FermiDirac distribution function as a function of temperature. This means that generation (creation of electron hole pairs) and recombination (annihilation of electron hole pairs = excited electrons fall back to the valence band) is a continuously ongoing process. donor doping). If f(E) gives the probability to find an electron then 1f(E) must give the probability to find a hole. In the above we have seen that electrons and holes occupy certain energy levels or states that are discrete but closely spaced in energy (therefore we talk of an energy band). Note that these electrons are in a higher (excited) state and will try to return to their lowest possible energy value. What is the probability to find an electron at energies larger than EF at absolute zero temperature? What is the probability of finding a hole at energies lower than EF at T=0K? The FermiDirac distribution function can be used to calculate the number of free electrons and holes via: +∞ n= p= ∫ f ( E ) g ( E )dE (20) Ev Ec ∫ (1 − f ( E ))g ( E )dE −∞ 11 Spring term course 17 . We also know that free electrons and holes can only have an energy value at which point there is an available energy level (state) and only 2 electrons or holes per level. f(E) is called the FermiDirac distribution function. statistical methods need to be applied. The statistics is based on the knowledge that electrons are indistinguishable. we still need to find expressions that relate the density of free electrons (n) and free holes (p) to certain energy levels. The number of available states for free electrons increases with increasing energy above the bottom of the conduction band and the number of states for free holes increases with decreasing energy below the top of the valence band. How these free electrons or holes into the energy band formalism will be discussed later. In the course Engineering Materials11 you will see that the number of states as a function of energy g(E) is proportional to g ( E ) ∝ E . We have seen a 3rd method to increase the number of free carriers and that is implantation where a certain density of Si atoms is replaced by group III or group V atoms (acceptor resp.
The Fermi level will then lie at some intrinsic level Ei near the middle of the band and the electron and hole concentrations are then given by: − (E c − E i ) n i = N C exp kT − (E i − E v ) p i = N V exp kT Eg ⇒ n i p i = n i2 = N C N V exp − 2kT Eg ⇒ n i = N C N V exp − kT (24) You can now derive that the intrinsic level Ei is lying midgap. Thus in an electric field this electron in vacuum will undergo a force given by the classical formula F=qE and since F=ma (a is acceleration) thus the speed of the electron will be determined by its mass and the applied electric field. Thus we can apply the classical formulae when we use the quantum mechanical values of the mass for electrons and holes: * m n = m0 m n m * = m0 m p p (23) With mn and mp the quantum corrections on the mass. the free carriers can be expressed as a function of the distance between the intrinsic level and the Fermi level. p Before we go further with the discussion on the density of free carriers in a semiconductor. let’s interpret the concepts of effective masses. This is of course a tremendous setback when we want to study transport of charged carriers in a semiconductor and in semiconductor devices. 12 13 In units of cm3 See Engineering Materials 18 .With Ec the bottom of the conduction band and Ev the top of the valence band. Explain why the mobility of holes in Si is lower than the mobility of the electrons. n is the density12 of free electrons and p is the density of free holes. What is happening is that all the additional forces that are imposed by the lattice on the free carriers in the semiconductor are taken up in the value of the effective mass of the electrons and holes.26 mp=0. the hole. the valence band. Can we apply the same classical formulae to the electrons and holes that are whizzing around within the periodic lattice of the semiconductor? The answer is in principle “no” since the electrons and holes moving inside a crystal will undergo additional forces from the surrounding atoms in the lattice which will be superimposed onto the applied electric field. * 2πm n kT N C = 2 h2 3 2 (22) 3 2 2πm kT N V = 2 h2 * p With * mn & m * the effective mass of the electron. When the semiconductor is doped. that these describe the transport of free carriers in the semiconductor perfectly well. For Si for carriers not too far away from Ev and Ec the values are: mn=0. It was found however that if one introduces the quantum mechanically derived masses of the free electrons and holes into the classical formulae. The result of the integration is13: − (E c − E F ) n = N C exp kT (21) − (E F − E v ) p = N V exp kT With NC and NV the effective density of states in the conduction resp.54 Thus in Si the holes are heavier than electrons. resp.11 1031 kg. Back to the density of free carriers as a function of energy at room temperature. The mass of an electron in vacuum is given by m0=9. When we have an intrinsic material (no doping) we have seen that the density of free electrons is equal to the density of free holes.
E E E electrons T>0K Intrinsic semiconductor Ec EF Ev a) intrinsic g(E) E Ec EF E 1/2 1 F(E) E holes carrier concentration electrons Ev b) ntype g(E) E Ec E 1/2 1 F(E) E holes carrier concentration electrons Extrinsic semiconductor EF Ev c) ptype g(E) 1/2 1 F(E) holes carrier concentration g(E) Density of states F(E) FermiDirac distribution function Figure 14: a) intrinsic semiconductor. The Fermi level lies closer to the conduction band than the valence band and as a consequence the integration of the product of the density of states and the FermiDirac function gives an increased density of electrons and a decreased density of holes. Thus a large amount of electrons can be found at energies close to the conduction band edge (Ec). Similarly for holes. c) ptype semiconductor. Draw the carrier concentration of two ptype semiconductors. a large amount of holes is available near the valence band edge (Ev) and decreases rapidly for decreasing energies. but further away the number decreases rapidly. Make sure that you understand the graph. are of ultimate importance to understand the physics behind the currentvoltage characteristics of semiconductor devices. b) ntype semiconductor. and extrinsic (ndoping resp. The comprehension of these graphs. pdoping). 14) that shows the band diagram. In the extrinsic semiconductor we see that the density of free electrons first increases as a function of energy and then decreases exponentially as a function of energy. (E − E i ) n = n i exp F kT (E − E F ) p = n i exp i kT (25) From the above equations we see that the distance between the Fermi level and the conduction band decreases when the number of free carriers due to doping is increasing. Which case has the largest density of free holes deeper in the valence band? 19 . Based upon this we can plot the following graph (fig. One has a doping density NA1 and the other NA2 with NA2>NA1. especially the left hand side and right hand side graphs. Plot both on adjacent graphs and ensure that the qualitative difference between the two graphs is clear. The Fermi level lies closer to the valence band than the conduction band and as a consequence the integration of the product of the density of states and the FermiDirac function gives an increased density of holes and a decreased density of electrons. the density of states the FermiDirac distribution function and the density of free carriers in three cases: intrinsic (no doping). Similarly the Fermi level comes closer to the valence band when the number of free holes is increasing as a result of doping. Fermi level lies ±midgap and the density of holes and electrons is equal (shaded regions).
free holes will move from left to right (up the hill).g.→ v+ (electrostatic attraction). We aim to find the variation of the potential energy Ec as a function of an electric field E and an electrostatic potential V. An electric field applied in the x direction E(x). Most semiconductor devices are constructed from a connection of different materials.to v+. partially filled Ec Ev filled or overlap a) empty Ec Eg Ev filled Ec empty Eg Ev Ev Ec b) filled c) 5. the lowest potential energy a free electron can have.15) E(x)=dV(x)/dx=1/e dEi/dx (27) The direction of the slope of the bands is easy to remember: electrons drift “downhill”. Note that the bandgap is unchanged under the influence of an electric field and that the intrinsic level follows the gradient of the band edges. A travelling electron is converting its potential energy in kinetic energy and thus its potential energy should lower from v. The question is 14 15 See Fields course and Analysis of Circuits Also metallurgic junction 20 . The electrostatic potential difference V (x) varies in the opposite direction following14: E(x)=dV(x)/dx (26) We know that the electrons will travel from v. Energy E(x) Ec Ei Eg Eg Ev x Figure 15: The tilt of the energy bands under influence of an electric field.Based on what we have learned. Different materials have different characteristics because the energy of their free carriers might be different. holes drift “uphill” like bubbles of air in water. based on the energy band diagrams given below. due to different doping densities (or because they have a different band gap). Some important relationships concerning energy bands The energy bands give in indication of the potential energy of the free electrons. decide. thus Ec is. This means that applying an electric field will cause a gradient in the energy bands such that the electric field points in the direction of increasing potential energy (see Fig. Free electron will move from right to left (down the hill).to low electrostatic potential. which one is a metal. e. points from high electrostatic potential v+ → v. The position where the materials touch is called the junction15. thus in the opposite direction of the electric field. a semiconductor and an insulator.
The minimum energy at which this happens is called the workfunction φ of the material. we need to “calibrate” the energy of the electrons in the different materials to an universal energy level. The material placed in vacuum is irradiated with photons and for a certain energy of the irradiation electrons will be freed into vacuum from the material. In order to do that. To do this the photoelectric effect is used. then the total current should be zero. for a gradient in hole density) gives the Einstein equation: D kT = µ e This equation relates mobility to diffusion constant. Thus we can draw the energy band diagrams of each material next to each other to form the junctions with respect to the vacuum level (see fig. During this process the Fermi levels align.16). The workfunction is the energy difference between the Fermi level and the vacuum level and is a constant for each material dependent on doping density. The existence of this potential difference results in an internal electric field and thus we should find that the band across the junction show a gradient. Thus each carrier current component should be zero. This will be discussed in detail in the pndiode section. (30) 21 . This level will be the vacuum level. far from the junction will not change with applied bias. When the Fermi levels are aligned.g. The Fermi levels align and thus a potential difference will occur across the junction.how to draw the energy band diagram of a combination of materials. no more diffusion will occur. When the two are brought into contact electrons will diffuse to the available states at lower energies if possible. Due to the difference in workfunction one material will have electrons at higher energy levels compared to the other material. 14. 16. J ntot = en( x) µ n E + eDn J ptot dn( x) dx dp ( x) = ep ( x) µ p E − eD p dx (28) The total electron and total hole current are caused by drift and diffusion. When no external bias is applied. Right: After forming the junction electron diffuse from higher energy levels to lower energy levels (occupying lowest available states within the system). Introducing this into (28) gives an expression for an electric field E that is caused by a carrier gradient d[carrier]/dx: E=− Dn dn( x) n( x) µ n dx Dp (29) dp( x) E= p( x) µ p dx Using equation (25) and (27) in (29) (e. Note that the value of the workfunction in each material. Potential difference across the junction Evac Evac eφ1 Energ eφ2 eφ1 e(φ2φ1) Evac eφ2 Ec EF Ec EF Ev EF Ev Figure 16: left: The energy band diagram of two semiconductors before forming a junction relative to the vacuum level. 17). Thus in a junction without external bias the Fermi level is constant throughout the structure otherwise there would be further diffusion of carriers until the Fermi level is aligned. That diffusion causes internal electric fields and thus gradients in the energy band diagrams can be demonstrated based on the expressions for the current in semiconductors (see eq. This process of diffusion has created a potential difference across the junction that is directly proportional to the workfunction difference.
Clearly. initially uncharged. metal and semiconductor) it is useful to know that the Fermi level in different materials can be defined with respect to a reference level – the vacuum level. the electrons close to the junction redistribute themselves via diffusion17 so that the Fermi energy is constant across the junction (in the absence of an applied voltage). In order to simplify the description of the device physics and the derivation of the currentvoltage characteristics we will ignore recombination in what follows. In the case drawn in Fig. another useful quantity is the electron affinity. Once the physics is understood the equations for current as a function of applied voltage can be derived. This constant is the work function φ. for a metal (which has no energy gap) the electron affinity and work function are the same! We have seen that when two different conducting materials. an internal electric field is introduced and thus the bands bend in the region where the field exist. are brought into contact.Chapter 2: Semiconductor junctions In this chapter we will explain what is happening to the carrier concentrations when two different materials are connected together. In order to draw an energy band diagram we find the value of the workfunctions and then draw the different material in the junction with respect to the vacuum level as given in Fig. We have also seen that when diffusion happens. In the next step we will apply voltages across the junction and based on energy band diagrams the physics behind carrier transport will be discussed.1 the internal electric field caused by diffusion is pointing from the semiconductor to the metal. electrons will diffuse from the material with the higher lying Fermi level to the material with the lower lying Fermi level in order to align the Fermi levels for material in contact without applied external bias. As a consequence Ec. This will be a connection between a metal and semiconductor or between two semiconductors made from the same material (Si in this case) but doped differently.1. 22 . This energy can be supplied by placing the metal or semiconductor in a large electric field (field emission) or by raising its temperature (thermionic emission) of by shining light onto the solid (photoelectric effect). The latter is a pn junction that is the basis for a diode. Metalsemiconductor junctions In order to allow us to study junctions of dissimilar materials (e. χ. were recombination will be taken into account. This approximation is also called the SHORT diode approximation. The workfunction is derived from the fact that it takes a certain amount of energy to drag an electron out of a metal or semiconductor into a vacuum. Note that no contact between the different materials has been made. The extra energy required to remove an electron at the Fermi energy to a point some distance (in energy) away from the metal (known as the vacuum level) is called the work function φ. For a semiconductor. 1. which is the energy required to remove an electron from the bottom of the conduction band and place it at the vacuum level. The more general case.1 this means that electrons will diffuse from the semiconductor to the metal. When we bring these materials into contact.g. Vacuum Level Øs Øm χ s Ec s EF Ev m EF Metal n type semiconductor Figure 1: Definition of the energy bands of a metal and a semiconductor with respect to the vacuum level via the use of the workfunction of each material. Thus in fig. will be discussed in year 216. Ei and Ev will 16 17 See EE2 Devices and Fields Note that diffusion can happen because of concentration gradients but also because of gradients in energy in which the electrons/holes are found. The diffusion of electrons from semiconductor to metal will create an internal electric field across the junction that aims to induce a flow of electrons in the opposite direction to the diffusion electrons (in order to make the net current zero as required in an unbiased junction).
This causes an accumulation of majority carriers – electrons – near the junction and the bands bend down towards the junction. When applying an external bias. Due the initial diffusion. the band bending will decrease and with sufficiently large external electric fields. an internal electric field exists across the junction that is pointing from the metal to the semiconductor. Thus the net electric field across the junction is the vector sum of the internal and external electric field.2) – called depletion – and one that causes an increase in majority carrier at the junction – called accumulation. In fact two categories of junctions exist: one that causes a decrease of the majority carriers at the junction (as in fig. When a positive voltage is applied on the metal. the band bending at the junction will be different and as a consequence we can expect the different metalsemiconductor junctions to react differently in response to an applied voltage. Ohmic contact In figure 3 we combine a metal with a workfunction φm with a ntype semiconductor with a function φs. turn around. with φm < φs. These two cases are referred respectively as a Schottky contact and an Ohmic contact. When the external electric field is opposing the internal electric field. In good ohmic contacts the work function different generates only a small amount of band bending (metal is well chosen with a workfunction close to that of the semiconductor). the above metalsemiconductor junction is drawn under a positive and negative voltage on the metal.2. Thus electrons will diffuse from the metal to the semiconductor. Then a small voltage will be sufficient for the higher lying electrons in the metal to cross the junction and generate current. When doping the semiconductor more heavily ntype. In order to find the characteristic of an ohmic contact an external voltage needs to be applied. We take a closer look into these junctions in the figure below. the Fermi level of the metal is decreasing with respect to the Fermi level in the semiconductor. metalsemiconductor junction metal EFm ntype metal Ec EFs Ev +p +Ec EF Ev ohmic contact Figure 3: left: metal and semiconductor before contact draw with respect to the vacuum level (not drawn). the electric field due to this bias will be superimposed on the internal electric field. the Fermi level of the metal comes lower in energy than the Fermi level of the semiconductor. 23 . the metal Fermi level is increasing compared to the semiconductor Fermi level. This means that the higher lying electrons (in energy) in the semiconductor “see” empty states at the other side of the junction and thus a current can flow. This makes this junction an ohmic contact where no severe inhibition of carrier flow occurs. As a voltage is applied externally and thus a net current can be flowing. the Fermi level will not be constant across the junction. Right: metalsemiconductor junction in contact. In the case of a positive voltage.1 in contact.all have a gradient such that potential energy is higher at the junction and decreases towards the semiconductor. Depending on the relationship between the workfunctions of the material that make the junction. In Figure 4. metal semiconductor E Ec EF Ev Figure 2: The metalsemiconductor junction of Fig. bottom: gives the energy band diagram. Diffusion of electrons from the semiconductor to the metal has left the semiconductor near the junction with less electrons than in the bulk far from the junction. The distance between the two Fermi levels is proportional to the applied voltage. If the external electric field is in the same direction as the internal electric field. Top: gives the charge accumulation near the junction. This gives an ohmic contact on an ntype semiconductor. When a negative voltage is applied on the metal. This results in an energy band diagram given in fig. the bands will bend further down in energy near the junction. the ohmic contact will improve. The magnitude of the internal electric field is defined by the workfunction difference between the metal and the semiconductor.
Top: gives the charge accumulation near the junction. bottom: gives the energy band diagram.diffusion from m → s Ec EF Ev Vext Vext>0 + Eext e. As a result of the uninhibited flow of carriers.Vext=0 Eint barrier cancels e. Schottky contact In figure 6 we combine a metal and an ntype semiconductor with φm > φs Thus electrons will diffuse from the semiconductor to the metal and holes will diffuse from the metal to the semiconductor. For good ohmic contact the band bending should be small. metalsemiconductor junction metal ntype Ec EF s Ev metal +n + Ec EF Ev Schottky contact EF m Figure 6: left: metal and semiconductor before contact draw with respect to the vacuum level (not drawn). Right: a positive potential on the metal decreases the band bending such that electrons can easily cross the junction to the side to which they are attracted based on electrostatics.roll down the hill Etot eVext Ec EFs Ev Figure 4: Top: the metalsemiconductor junctions under zero bias. This causes a depletion of majority carriers – electrons – near the junction and the bands bend up towards the junction. 18 A positive potential attracts electrons and a negative potential attracts holes. within the region where an electric field exist (band bending) the Fermi levels become quasi Fermi levels and do not retain the same meaning as EF before contact. Far away from the junction these Fermi levels become the same as before the voltage was applied (EF lies at a distance from the band determined by the doping density). Left: a positive potential on the metal makes it easy for the electrons in the semiconductor to cross the junction to the side to which they are attracted based on electrostatics18.4 that the Fermi levels are no longer aligned and are now notated with m and s at opposite sides of the junction. 24 . I V Figure 5: the currentvoltage characteristic of an ohmic contact.roll down the hill Etot Ec EFs EFm eVext Ev EFm  Vext Eext Vext<0 + e.5). the currentvoltage characteristic is linear and the relation between the current and the voltage is given by Ohm’s law: V=RI with R the resistance of the contact. The slope gives the ohmic contact reistance. This gives a Schottky contact on an ntype semiconductor. Right: metalsemiconductor junction in contact. Note in fig. (see fig.
We see that now a certain amount large amount of carriers has a sufficiently high energy to cross the potential barrier. the barrier decreases and the drift does not compensate the diffusion any more. when the width of this forbidden region is small. Electron diffusion is cancelled and no current can flow. The influence of the voltage on the metal is to increase or decrease the potential barrier against carrier flow. quantum mechanical tunnelling can occur19). the potential barrier increases and stop carrier diffusion. As a consequence the Schottky contact is a rectifier. One feature is that near the junction the semiconductor is depleted of mobile carriers since all the electrons are repelled. When a positive voltage is applied to the metal. the potential barrier at the junction is lowered and more electrons can diffuse across the junction. A better insight into the interpretation of potential barriers acting against current flow that would be expected based on electrostatic principles only can be found using figure 9.Vext=0 Eint e(φmφs) E E E Vext Etot e(φmφs)eVext Ec EF Vext + Etot e(φmφs)+eVext Ec EF + Eext Eext Vext>0 eVext Vext<0 eVext Ev Ev Figure 7: The Schottky contact under biasing conditions. Note that underneath the Ec line near the junction. thus a net current can flow. Currentvoltage characteristics: I V Figure 8: The current voltage characteristic of a Schottky contact on an ntype semiconductor.9 right). there are no states (forbidden gap) thus in a pure semiconductor no carriers can cross this region (in quantum mechanics. Under “forward” bias the potential barrier is decreased and carrier can diffuse across the junction whilst under “reverse” bias. the potential barrier at the junction is increasing and the electrons in the metal do not have enough energy to cross this barrier. In the bulk of the semiconductor the carrier concentration as a function of energy is plotted together with a decrease of the band bending at the junction due to the applied external electric field (fig. When a negative potential is applied on the metal. 25 .8. This means that current is flowing in one bias direction. but is blocked in the other bias direction. The currentvoltage characteristics of the Schottky contact is given in fig. When no external bias is applied then the amount of carriers that can diffuse across the barrier is equal to the amount of carriers that is drifting back as a consequence of the internal electric field. In fig. Figure 7 shows the energy band diagram of the Schottky contact under different biasing conditions. When this field across the junction is decreased. 19 See Advanced electronic devices in the third year. Thus only the carriers with an energy higher than the maximum of Ec can diffuse across the junction and deliver current (see n3).9 ntype Schottky contact is drawn.
To determine the depletion width. Potential barrier to electrons intending to traverse to the metal distance Forbidden band.Energy metal semiconductor V+ Ec Ec EF EFm EFs n3 Density of electrons at each energy value. we take a look at the energy band diagram of the semiconductor only. that makes the foundation of the MOSFET. metaloxidesemiconductor metal Evac qφ m qφ s Ec Es F Es vs qφ m oxide ptype Evac qφ s Eco Ec o EF m Ecs EF Evs Evo Evo d Figure 10: The energy band diagram of an MOS on a ptype semiconductor with dissimilar workfunctions.11. right after contact. d is the depletion width caused by the work function difference between the metal and the semiconductor. The approach for drawing the energy band diagrams is the same as for the previous junctions. Again there will be a potential drop across the oxide and semiconductor that is caused by the depletion or accumulation of the carriers near the oxidesemiconductor junction. Note: the work functions of the materials do not change upon contact. This potential drop will be equal to the difference between the semiconductor and metal workfunction. In this junction an insulator. n2 n1 Only these electrons have sufficient energy not to have to go through the forbidden band. This happens via a redistribution of the carriers but without any effective transport of carriers possible through the junction. Left before contact. is the metaloxidesemiconductor junction or MOS. Right energy band diagram under bias. When the different materials are brought into contact the Fermi levels must align. SiO2 is sandwiched between the metal and the semiconductor. Metaloxidesemiconductor junctions An important junction. The oxide will be treated as a perfect insulator and will thus stop any currents flowing through. given in fig. First draw the energy band of each component separately with the Fermi level referred to the vacuum level. Few electrons>small current. An example of a MOS with φs>φm and a ptype semiconductor is given in figure 10. Lots of electrons close to Ec but the number is exponentially decreasing with increasing energy. no electrons can travel through the wide forbidden band Ev Figure 9: Left energy band diagram under zero bias. The density of electrons as a function of energy is also given 2. 26 .
Ecs EF + + Evs Figure 12: The MOS on a ptype semiconductor under different biasing conditions and the definition of the result of the biasing condition. The surface potential is dependent on both the work function difference and the applied voltage on the metal. see pneN A junctions for a more detailed derivation of depletion widths).Oxidesemiconductor interface Ec Ei qφs qφF EF Ev Figure 11: Energy band diagram of the semiconductor only. 27 . Note that the structure metalinsulatordoped semiconductor (which can be regarded as a conducting material) is similar to a parallel plate capacitor (see Fields course). Voltage applied on MOS V<0 E Eco EFm qV Ecs EF + + + Evs m o Evo V>0 E Eco qV EFm m o Evo s hole depletion Ecs EF + + Evs qV EFm m o Evo s strong inversion s hole accumulation V>>0 V>Vth E Eco . q=e. Definition of parameters. φF is the Fermi potential ( = (Ei − EF ) e in bulk) and φs the surface potential ( = (E i bulk − Ei surface ) e ). The metal on the MOS is regularly called the gate because of its close relation with the MOSFET. Ei is the intrinsic level and is defined via: n = ni e ( E F − Ei )/ kT p = ni e ( Ei − EF )/ kT The intrinsic level will bend as a function of applied voltage. The depletion width d will be a function of φs ( d = 2ε 0ε Siφs .
Oxidesemiconductor interface at threshold Ec Ei eφF eφs=2φF EF Ev Figure 14: The energy band diagram of the semiconductor from oxide into bulk at the point of threshold. the region under the oxide is depleted of mobile carriers. Since the total insulator thickness increases the MOS capacitance decreases. The few holes that are in this region are recombining with the few electrons – minority carriers. 13. This is called inversion. Measuring this capacitor would give the characteristic drawn in fig. At a certain moment we reach a condition where the distance between the Fermi level and the conduction band at the oxide/semiconductor interface is equal to the distance of the Fermi level to the valence band far away from that interface (that is thus where the bulk conditions – the original material conditions – can be found). When we apply a positive voltage. This means that a region is generated that is deplete of mobile holes. For convenience one can ground the semiconductor contact. This situation is plotted for the ptype MOS in Figure 14 (only semiconductor band bending shown). When a positive voltage is applied to the metal. The residual electric field is dropped across the inversion region and attracts minority carriers across the depletion width in to the inversion region.12: When a negative voltage is applied to the gate with respect to the semiconductor then the Fermi level of the metal will shift up with respect to the Fermi level of the semiconductor. thus becomes an insulator. The electrostatic forces will attract the positively charged holes (of which there are plenty – majority carriers) to the semiconductor/oxide interface. What remains is to define the threshold voltage. We will assume that this region is therefore completely free of mobile charges. The bends are bending down as a consequence of the applied external electric field. the depletion width “d” has reached a maximum value. the electrostatic forces aim to repel the holes – majority carriers – from the oxide/semiconductor interface. the density of previously called the minority carriers at the interface is equal to the density of the majority carriers in the bulk of the material. How does this influence the capacitance of the MOS? We saw that under negative bias. the depletion width is maximum and an highly conductive inversion layer is created between the oxide insulator and the maximum depletion width insulator and thus we find a series connection of two capacitors. At the point of inversion. The voltage applied to the gate that causes this feature to appear is called the threshold voltage. The capacitance of this MOS capacitor is then determined by the oxide thickness. We find the condition of accumulation of majority carriers. Surely we cannot call the surface ptype any more. At that moment. These holes are accumulating at the interface as they cannot pass through the oxide. Vth as the voltage at which point the electron (hole) concentration at the silicon surface is equal to the hole (electron) concentration in the bulk. At the threshold voltage. In a MOS capacitor these minority carriers are those that are generated via electronhole pair generation close to the depletion region edge and can be captured by the field and dragged across to the inversion layer.With reference to fig. 28 . C accumulation de depletion pl eti on maximum depletion width reached inversion Vth V Figure 13: The capacitancevoltage characteristic of a MOS on ptype semiconductor. it has been converted into an ntype material near the oxide/semiconductor interface. This region increases in with for more negative voltages. holes are accumulated and the capacitance is determined by the oxide thickness.
MOS capacitance Assuming that there are no mobile carriers in the depletion width. For more info on heterojunctions. in this course we will only study homojunctions. in words. the pn junction.0. 29 . also called the pn diode is the most popular. Of the homojunctions. we can see that the MOS acts as a parallel plate capacitor with a capacitance value dependent width of the depletion region and thus on the gate voltage. This is then a heterojunction.0 W width. The pn diode pn diodes are fabricated via the implantation of a ptype or an ntype substrate (in VLSI ptype Si substrates are preferred due to the fact that an nMOSFET is defined on a ptype substrate (see later)) with the opposite carrier type. They can also be composed from a combination of different materials with the same or different doping type. Vth = (φ m − φ s ) + − QB + 2φ F C ox (2) The first term at the rhs takes into account the work function different between metal and semiconductor. Thus threshold is reached when φs=2φF. this is called a homojunction. 3. The pn diode is the connection of two solids of the same kind but with opposite doping type. Note also that we assume that the oxide is completely free of imbedded charges. The MOScaps have the same area. the same oxide thickness. The implantation dose is sufficiently higher than the original carrier concentration available. the definition of threshold voltage.Then Ei lies as far below EF at the surface as it lies above EF in the bulk this is expressed by: φsinv = 2φF = 2 kT N A . Note that in current VLSI all contacts will be made on the top separate by SiO2. both on a ptype substrate but with different doping densities in the substrate. Semiconductorsemiconductor junctions Semiconductorsemiconductor junctions can be composed from 1 type of material with different doping type or density. thus: d max = 2ε 0ε Si 2φ F =2 eN A ε 0ε Si kT ln N A n e2 N A i (4) and the minimum capacitance will be a series connection of the oxide and depletion capacitance: C min With 1 1 = WL + C ox C max depl WL t ox + d max ε 0 ε SiO ε 0ε Si 2 −1 −1 (5) εSi = 4. Give. we make the assumption that “real” inversion only happens when the condition φs=2φF is fulfilled (called strong inversion). From this knowledge one can derive the expression of the threshold voltage as a function of material parameters (see 2nd year Devices). Maximum depletion occurs when inversion starts. Point out what is different and explain why. Although heterojunctions have become increasingly important in semiconductor technology. L length of gate tox oxide thickness When the MOS cap. The maximum capacitance is for accumulation: C max = With ε 0 ε oxWL t ox = C oxWL (3) εox = 4. ln e ni (1) Note that whilst the surface is inverted whenever φs>φF. is in depletion the capacitance will decrease due to the increase of the depletion width (see Fields course). ε0=8. the second term takes into account the voltage drop across the depletion region and the last term is due to the inversion condition. the interface between oxide and semiconductor is perfect and that no current can flow through the oxide. Then ohmic contact are defined on each side. see 3rd year course Advanced Electronic Devices.85 1012 F/m Draw the capacitancevoltage characteristics of two MOS capacitors on the same graph.
The larger the internal field the larger the regions with fixed ionised charges. These are negatively charged since they lost a hole. V0 is the contact electrostatic potential or builtin voltage. The electric field will send electrons back to the nregion and holes back to the pregion. Note on the distance between the Fermi level and the band edges. This region with fixed ionised charges from which the free charges are removed is called the depletion region or space charge region. we find that the currentvoltage characteristic is exponential (very similar to the Schottky contact). The diffusion of holes from the ptype region leaves the ionised acceptor doping atoms behind. W0 is the depletion region. In general: ( Ev − E F ) (Ei − E F ) p = N ve kT and pi = N ve kT n = N ce ( E F − Ec ) kT and ni = N c e ( E F − Ei ) kT In ntype semiconductors n » p and since NC ≈ NV this can only be the case if (ECEF) < (EFEV) ie EF is closer to the conduction band. Since an internal electric field occurs across the junction.implantation p n n n metal p p n n metal p n Figure 15: Left: Schematic of the fabrication process of a pn diode. Right: the circuit symbol for a pn diode. Additionally. Since there is no bias applied. Thus at zero bias there is a steady flow of carriers due to diffusion and an opposite and equal amount of carriers flow due to the internal electric field. Energy band diagrams are a good tool to explain this rectifying behaviour. internal electric fields and band bending – the latter results in a creation of potential barriers against diffusion of carriers. The energy band diagram that results is given in fig. the net current needs to be zero. diffusion of electrons from the ntype region across the junction leaves behind positively charged donor atoms which are fixed in the lattice. When measuring a pn diode. whilst a decrease will allow more diffusion. Thus we have fixed charges at opposite sides of the junctions of opposite character. We have seen that this causes an internal electric field to be build up across the junction. These charges are the result of the disappearance of mobile carriers from the junction region due to the steady state diffusion that is occurring. Band diagrams are based on some simple rules that give the relation between diffusion. Evn 30 . charges must be associated to this field. but also they are fixed in the Si lattice and cannot move. Due this massive concentration gradient a diffusion of electrons from n to p and of holes from p to n will occur. Sketches of energy bands under an external potential are easy to derive from the previous when knowing that external electric fields are superimposed on the internal field and thus change the band bending. And similar for the holes in p and n region.16. Band diagram of unbiased junction When bringing an n and a p type material together there is of course a large concentration gradient across the junction: in the n material there are many more electrons – majority carriers – than in the pmaterial where there are just a few – minority carriers. This means that these fixed ionised charges cannot carry current! Similarly. we can always rely on electrostatics to find out where the carriers want to go to and the band bending will then indicate if this will be possible or not. For ptype n « p and a similar argument shows that EF is closer to the valence band. The magnitude of the internal electric field will be such that it cancels the diffusion. The internal electric field causes a potential barrier with a potential difference between n and p side equal to V0. W0 Ecp Eg EF Evp Ecn EF Ecp EF Evp Eg eV 0 Ecn EF Evn ptype ntype ptype ntype Figure 16: The energy band diagram of a p and ntype semiconductor before contact (left) and after contact (right). An increase in resultant field will lead to a reduction of diffusion. The internal electric field will point from the positively charged region to the negatively charge region (and thus uphill in the energy band diagram). Note: EF constant across unbiased junction.
This region is empty of mobile carriers but consists of fixed ionised doping atoms20. hole diffusion hole drift electron diffusion Current electron drift Drift current flows under the influence of an electric field (this field can also be internal). V0 From the right diagram in figure 16 we can find an expression for the builtin voltage that is associated to the builtin electric field: eV0 = Ecp – Ecn. Diffusion current flow under influence of a concentration gradient. take eq.7 10 10 10 15 N AND ni2 Figure 18: The variation of the builtin voltage V0 as a function of doping density. W0 is the depletion width when no external bias is applied. To prove the “drift cancels diffusion” reasoning above.+ . Thus E(x) has its extreme at the junction itself. Derivation of the builtin voltage across a junction.+ .Particle flow The current due to drift of carriers under Efield exactly cancels diffusion current under zero bias. (chapter 1. Note that the electron currents are opposite the carrier flux as a consequence of the negative charge of the electrons that is taken into account in the current versus field expression. These fixed ionised atoms generate an internal electric field.+ depletion region n ve acceptor builtin +ve donor ions Efield ions Figure 17: Depletion region with a width W0 build up around the junction and depletes a part of the ntype and ptype material of moving carriers. The builtin voltage is the difference between the position of the conduction band in the ptype region and the conduction band in the ntype region. Because the charge density is uniform within each depletion region. Thus carrier gradient causes diffusion of mobile carriers which leaves behind fixed ions that induce an electric field that causes drift. The position of the bands can be derived from the doping concentration and the position of the Fermi level: In ntype nn ≅ Nc exp (EcnEF)/kT but also nn = ND ni2 In ptype np ≅ Nc exp (EcpEF)/kT and np = NA Combining these gives the builtin voltage: V0 = kT n n kT N A N D ln = ln e n p e ni2 (6) V0 (V) 0. we can expect that the electric field strength changes linearly with distance from the depletion layer edge.e Dh dp/dx = 0 under zero bias Jn = n e µ e E + e De dn/dx = 0 under zero bias drift diffusion Space charge at junction W0 p n p . 28) and find that drift is equal and opposite to diffusion current: Jh = p e µ h E . 20 The consequence of this approximation will be discussed in the 2nd year 31 .9 0.
How does this solution compare to the bandgap of Si? ni=1.45 1010 cm3. W. reverse bias V<0. the Poisson equation21 needs to be solved in each region of the device. In what follows we will assume that the ohmic contacts are ideal and that the externally applied voltage will drop solely across the depletion region – the resistance of the depletion region is many time higher (no free carriers) than the resistance of the neutral regions (plenty of free carriers). wp is the depletion width into the pdope region. kT/e=0. the total electric field across the junction will increase and thus the depletion width that supports this electric field will increase. one should keep in mind that putting the voltage drop across the neutral regions to zero might have consequences on the interpretation of the total picture behind the operation of semiconductor devices.026V at room temperature and Eg(Si)=1. electric fields and currents.the electrostatic potential should be continuous . Forward bias: V>0. and (c) reverse bias Depletion layer width is calculated using electrostatic theory. This is schematically given in fig.charge neutrality should be maintained Thus we start with the general expression of the Poisson equation which relates the gradient of the electric field to the local space charge density at any point x : 21 See Fields course (Gauss law in 1D) 32 .Note: Holes are majority carriers in ptype material : pp Electrons are minority carriers in ptype material : np The subscript indicates the material type. so they are still the same as bulk). Wo a) ptype ntype b) ptype W<Wo ntype c) ptype W>Wo ntype Figure 19: The depletion layer width. When a voltage is applied externally. This is the same as assuming that the workfunction of the chosen metal is exactly the same as the workfunction of the semiconductor and that no interfacial layer such as an oxide exists between metal and semiconductor. at (a) zero bias (b) forward bias. value 11. Although these assumptions will lead to valuable methods to extract useful expressions for depletion regions. Sketch the energy band diagram of this pn junction to help to explain your answer. 19. In contrast when the external electric field adds to the internal electric field. V is the externally applied voltage. We have also neglected that any voltage is dropped across the ohmic contacts that must exist at the edges of the neutral regions.7εo In order to calculate the depletion width. The solution in each region will depend on integration constants that have to be determined via the boundary conditions: . We have seen that at zero bias a depletion layer width consistent with the magnitude of the internal electric field is builtup. Calculate the builtin potential of a pn diode with ND=1020 cm3 and NA=1020 cm3. the external field will be superimposed on the internal field. ε is the permittivity of silicon. The assumption we make here is that we neglect that any of the externally applied voltage will drop across the neutral regions (this are the n and pregion where no depletion occurred. wn is the depletion width extending in the ndoped region. The total depletion width is the sum of the two.the electric field should be continuous across the junctions . In many cases it is acceptable to just add series resistances to the ideal ohmic contact to give a more realistic picture.11eV. We can expect that when the externally applied electric field is opposite to the internal electric field then the depletion width will decrease as the total field across the junction will have reduced – this is the case in forward bias.
20. then we have two regions with constant space charge for which we can write (abrupt junction) : dE e + = N D when 0 < x < wn dx ε dE e − = − N A when .. These are different at the pside and the nside. Note that each region will have homogeneous doping. The maximum potential at zero bias is the builtin voltage V0. In the depletion region we have assumed no free carriers. The total under of charges in the neutral regions is zero as holes.m1 ie the fields within a pn junction are very large... W0 p W p .dE e + − = p − n + ND − N A dx ε ( ) (7) This equation has to be written in each part of the semiconductor junction (each part will have a different charge density)... Second down: the total number of charges in each region of the diode.++ 0 eN d + Wn Q(x) Q+ QQ: charge density Q=Q+ fixed ionised charge in depletion layer n x density of mobile charge in depletion layer negligible x eNaE(x) x Emax V(x) x Figure 20: Top: the pn junction with depletion region and neutral regions defined.. We have assumed that the electric field is zero in the neutral regions. so only the doping atoms are left.++ . The 33 e e . This can be done by using information in fig.w p < x < 0 dx ε dE = 0 elsewhere dx ( ) ( ) (8) Integrating the left and right hand sides of the equations and assuming that the complete electric field is dropped across the depletion region (no potential drop across the neutral regions) gives: 0 ∫ dE ( x) = ∫ dE ( x) = Emax Emax 0 (N ) ∫ dx when 0 < x < w ε e + D 0 wn n −e ε (N ) ∫ dx when .++ . Bottom: the variation of the electrostatic potential. Third down: the variation of the electric field. In the depletion region we neglect n and p (no mobile carriers).w − A w p 0 p <x<0 (9) Thus Emax = − N D wn = − N Aw p ε ε For typical doping concentrations we find Emax > 106 V. electrons and ionised doping atoms cancel each other out.
To find wn and wp in terms of the applied bias we need to integrate again after introducing the relationship of electric field and electrostatic potential: E ( x) = − dV dx − V0 = ∫ E ( x) dx −wp wn Thus the negative builtin voltage is simply the area underneath the E(x) triangle (see graphs previous page): 1e 1 V0 = − Emax wdepl = N D wn wdepl 2 2ε since wn N D = w p N A and wdepl = wn + w p then wn = thus V0 = wdepl N A N A + ND 1 e ND ND 2 wdepl 2 ε N A + ND When a voltage is applied across the pn diode we assume that all the applied voltage is dropped across the high resistance depletion layer.above equation also shows us that: N D wn = N Aw p . it shows that the depletion region extends in the lowest doped region of the pn diode. Thus if we have a heavily doped n+ surface in 2ε r ε 0 (V0 − V ) (eN D ) and in this case wdep ~ wp ≅ 34 . This is also a consequence of charge neutrality across the depletion region.w < x < 0 E ( x) = ε e ε + D n n − A p p For the case of an abrupt junction the electric field E(x) decreases and increases linearly across the junction. The boundary conditions are: E ( x → − 0) = E ( x → + 0) E ( x = wn ) = E ( x = w p ) = 0 The solution is then: E ( x) = (N )(x . V0. The potential barrier ∆V then becomes: ie ∆V = V0 .V where V = applied bias > 0 in forward bias < 0 in reverse bias Using this result with ionised charge equality across the junction. V. If we consider the two limiting cases when NA is much bigger or much smaller than ND (this is called a onesided pnjunction) we find that : If NA » ND then wp « wn in this limit wdep ~ wn ≅ If NA « ND then wn « wp 2ε r ε 0 (V0 − V ) (eN A ) Thus we conclude that the depletion extends in the lowest doped region. The variation of the electric field as a function of x is found by integrating the equations with undefined boundaries and then determining the integration constant via the electric field value at the edges of the depletion region. This is an important equation.w ) when 0 < x < w −e (N )(x + w ) when . It turns out that many real junctions have very asymmetric doping levels. plus any applied bias. and the total voltage across the junction consists of the builtin voltage. gives: wn = wp = 2ε 0 ε r NA (V0 − V ) 2 q NAND + ND 2ε 0 ε r ND (V0 − V ) 2 q NAND + NA As expected wn and wp are voltage dependent and become smaller under forward bias (V>0) and larger under reverse bias (V<0).
Now an external bias has been applied that lowers the total field across the junction. nor generation of carries in the depletion region The ohmic contacts are ideal The density of injected minority carriers is far below the density of majority carriers The externally applied voltage drops completely across the depletion region * The pn junction under forward bias V depletion regions Wp ++ ++ ++ ++ ++ Wn free electrons e (V0 . This injection of carriers creates an increased minority carrier concentration at the depletion region edge in each region compared to the bulk value initially available. Now what about the majority carriers? Charge neutrality claims that if the minority carrier concentration increases at the depletion region edge. Also note that the depletion width is dependent on the builtin voltage (associated to the band bending across the junction). 9 in Chapter 1: the carriers that first participate in the current flow are those in the top of the Fermitail. But while the increase of minority carrier concentration is important in comparison with the concentration initially available. The ideal metal contacts at the other hand keep the number of majority carriers and minority carriers exactly the same at what is found for the bulk condition (thus completely determined by the doping density and the material). Now go back to the depletion width in a MOS capacitor and see that the equation given is consistent with what we have derived for the onesided pnjunction above. Similarly: a high density of holes at the depletion region edge in the ntype region and a lower bulk value minority carrier concentration at the metal contact.contact with a lowly doped p layer.V) eV + + + ptype neutral region ntype neutral region fixed acceptor ions fixed donor ions Ec EF Ev free holes Figure 21: pn junction under forward bias and the change in the energy band diagram Forward bias lowers the potential barrier across the junction. Remember that the internal electric field was built up under zero bias in order to compensate for the diffusion of carriers from high to low concentration (so electrons from n to p and holes from p to n). this means that the resulting electric field is not sufficiently large any more to compensate the diffusion of electrons and holes. This gradient of minority carriers is very large and will define the currents that are flowing through the diode (this is because there were only a few minority carriers available thus any added will make a difference). We can expect an exponential increase of the current due to the exponential increase in density of carriers with sufficient energy to cross the potential barrier. A small field will be able to carry a sufficiently large majority carrier current to the depletion region edge due to the fact that there are many majority carriers available and 35 . This means that minority carrier gradients have been formed: a high density of electrons at the depletion region edge in the ptype material and a lower bulk value of minority carriers at the metal contact. Another way to see is to refer back to fig. Note that there are a large amount of these carriers available to carry the current. therefore more electrons will have an energy higher than the barrier and cross from n to p and more holes will be able to overcome the barrier and flow from p to n. Derivation of currents in pn diodes In order to derive the expression for the current in pn junctions we will make some assumptions: There is no recombination of carriers in the neutral region There is no recombination. the same increase in majority carrier concentration (for the low injection approximation) is negligible compared to the huge amount of majority carriers that are already available. then we can expect the depletion width to extend in the lowest doped region and the width to be inversely proportional to the doping in this lowest doped region. then so must the majority carrier concentration. In forward bias majority carriers in each region are thus injected across the junction (and across the depletion region) and end up as minority carriers at the other side of the junction. Thus the gradient caused is negligible and this implies that the majority carrier current can only be due the existence of a small electric field in the neutral region.
I ∝ density of carriers × electric field . This minority carrier current – due to diffusion – is the only way to derive the current for the pn diode based on the knowledge of the material parameters (it is very difficult if not impossible to derive the small electric field that determines the majority carrier current from the known parameters). * The pn junction under reverse bias V ptype neutral region Wp +++ +++ +++ +++ +++ Wn ntype neutral region Ec free electrons e (V0 + V) EF Ev eV + + + free holes Figure 22: pn junction under reverse bias and the change in the energy band diagram The reverse bias adds to the builtin voltage increasing the potential barriers. Now the barrier has become VV0 thus the associated injected minority carrier concentration is: e(V − V ) (7) n' p = n n exp 0 kT under the assumption that the majority carrier concentration didn’t change22. 36 . When looking at the energy band diagram given in fig. Thus the reverse bias current will be determined by the amount of minority carriers available close to the depletion region edge. This concentration is determined by generation in the neutral regions. 21 we can derive that the minority carrier concentration that is due to charge injection across the junction. Combining equation (6) and (7) gives (and similar for the injected holes): eV n' p = n p0 exp kT (8) eV p 'n = pn0 exp kT Or the injected minority carrier concentration at the depletion region edge of a short pn junction diode under bias voltage V obeys the relation: 22 Good approximation for low levels of injection. To derive the expression for the current we start with drawing the minority carrier concentration in the p and n region under forward bias (the reverse bias current will result directly from this approach). the minority carrier gradient that is created by the injection of carriers across the reduced potential barrier at the junction is large enough to determine the currents flowing. Notwithstanding this. therefore there at no carriers with sufficient energy to travel across the barrier. Breaks down for high levels of injection as those occurring in power devices. However there will be a leakage current due to the very small amount of minority carriers available in the ptype region that can travel to the ntype region and vice verse. neglecting the electric field in the neutral region for the calculation of the depletion region width was useful but breaks down in the physical interpretation of where the majority carrier supply is coming from. Remember equation (6) for zero bias: kT nn eV V0 = ln → n p = nn exp 0 = n p0 n e p kT with np0 the minority carrier concentration in bulk. So whilst the very very small electric field cannot generate a sufficiently large magnitude of minority carrier current to explain the experimental characteristics. the approximation leads to very reliable equations. As indicated before.
the continuity equation becomes: ∂p ∂ 2 p ( x. This proves the linear variation of the minority carrier concentration when recombination is not taken into account. t ) = Dp ∂t ∂x 2 2 ∂n ∂ n ( x. the time derivative is zero and thus the solution to the second order differential equation for the minority carrier concentration must be linear. L Lnp np ptype n' p p' n Ln Lp p n n p = minority electron concentration in ptype contact at zero bias p n = minority hole concentration in ntype contact at zero bias depletion layer ntype Figure 23: Linear variation of the minority carrier concentration as a function of distance of a short pn diode under forward bias. The hole diffusion current is by definition given by the gradient of the holes in the ntype region: I p = −eADh I p = eADh (p dp dp note < 0 but holes diffuse in + x direction dx dx ' n − pn Lp ) The electron diffusion current is given by the gradient of the electrons in the ptype region: I n = eADn I n = eADn (n dn dn > 0 but electrons diffuse in . Any length larger than this diffusion length makes the short diode approximation invalid. The total current through the diode is the sum of the hole and the electron current. Due to current continuity throughout the whole structure we can say that the total electron current is due to the diffusion of electrons in the pdoped region and the total hole current is due to the diffusion of the holes in the ntype region.x direction note dx dx ' p − np Ln ) 37 . The linear variation of the minority carrier concentration is only valid when no recombination of minority carriers occurs whilst they diffuse through the neutral regions. Under steady state injection (DC voltage applied). t ) = Dn ∂t ∂x 2 (10) and similarly for electrons. In order to check the validity of the linear variation of the minority carriers we start from the time dependent variation of the carriers in a semiconductor under influence of a current on (recombination ignored): For holes this is: ∂p 1 J p ( x) − J p ( x + ∆x) = ∂t x→ x + ∆x e ∆x Or in words: the rate of hole buildup is equal to the increase of holes concentration in ∆x × A per unit time for current flowing in the x direction through a cross sectional area A. When ∆x becomes infinitesimal small and stating that the current is solely due to diffusion current. Note that the lengths of the neutral regions are chosen to be the diffusion length of the minority carriers. The physical interpretation of these lengths are that they give the average distance an electron can travel in the ptype region without recombining (Ln) and a hole can travel in the ntype region without recombining (Lp). The maximum lengths of the neutral regions for which this approximation is valid are the minority carrier diffusion lengths Ln and Lp. The general expression for the diffusion length is given by: L = Dτ with D the diffusion constant and τ the average lifetime (is the average time before recombination occurs).n' p n p0 = p' n eV = exp p n0 kT (9) In figure 23 the variation of the minority carrier concentration as a function of distance in both regions of the short pn junction under forward bias is given.
(8): I tot = I p + I n eV I tot = I 0 e kT − 1 D p pn Dn n p I 0 = eA + Lp Ln (11) reverse saturation (leakage) current The forward bias current is exponentially dependent on the applied voltage and the reverse leakage current is indeed defined by the available minority carriers in the bulk. current Depletion region p+region Itot nregion Ip In contact Minority carrier diffusion currents junction contact Remain constant in space charge region. pn diodes are devices with a nonlinear currentvoltage characteristic. The value of the series resistance can be determined via measurements. In fig. 25 a cross sectional view of a diode is given: depletion region contact contact nSi pSi Figure 25: a cross sectional view of the pn diode consisting of two ohmic contacts. In order to estimate their influence in circuits and systems where DC or small AC signal are applied. In this course we will derive the equivalent circuit of the pn diode based on the physical principles behind the flow of carriers. The slope of the exponential currentvoltage characteristic is dependent on the chosen biasing condition. Small signal equivalent circuit of a pn diode. two doped semiconductor regions with opposite doping and a depletion region with a voltage dependent width. This can be done by proposing an equivalent circuit for the diode (each little segment of the nonlinear curve for very small voltage variations looks linear).Thus the total currentvoltage equation is found using eq. the diode response needs to be linearised23. Majority carriers injected across the junction are resupplied via drift through the contact and diffuse to the other contact through the minority carrier gradient region. The influence of the contacts and the doped semiconductor regions can be represented via a series resistance across which a certain amount of the applied voltage will be dropped. This slope can 23 via the traditional techniques that are taught in the Analysis of Circuit course 38 . Derive the approximate expression of the current in a pn junction with a heavily doped pregion (the doping density in the pregion is 103 times larger than in the nregion. The minority carrier gradients determine the total current completely. Figure 24 gives an insight in the minority and majority carrier currents flowing in the diode. The current remains constant in the space charge region because there is no recombination no generation of carriers (assumption). Majority carrier drift currents Figure 24: The contribution of the minority and majority carrier current to the total current through the pn junction.
c. voltage regulators – see radio design in lab. The capacitance C is the parallel connection of the diffusion and depletion capacitance.see Power Supply Experiment (ii) Zener diodes for e. the depletion width sandwiched between two doped semiconductor regions behave as a parallel plate capacitance. signals . This variation of the charge as a function of voltage is of course also a capacitance. Moreover the depletion width will change quite dramatically in reverse bias as a function of applied voltage. whilst the diffusion capacitance is important in forward bias.g. (iii) optoelectronic devices: photodetectors solar cells LEDs Lasers 39 . the injected minority carrier concentration at the depletion region edge increases and thus the total excess of minority carriers increases. Some applications of p .n junction diodes (i) rectification of a. gives: eV dI 0 exp − 1 kT eI for sufficient forward bias gd = ≈ dV kT As with the MOS capacitor. Not immediately obvious is the existence of another capacitance that is due to the minority carriers that are present in the neutral region in forward bias and the fact the this concentration of charges is changing as a function of forward bias voltage.be represented via a differential conductance that is determined by: gd = dI dV Introducing the diode current expression. As the forward bias voltage increases. 2 dQ e d p' n − p n0 L p d n' p − n p0 Ln 1 L p dI p L2 dI n e (τ p + τ n )I = + = + n = dV 2 dV dV 2 D p dV Dn dV 2kT Cd = ( ) ( ) The depletion capacitance will be important in reverse bias. The small signal equivalent circuit: Rs r d = 1/gd C Figure 26: small signal equivalent circuit of the pndiode. As a consequence this will be represented in the equivalent circuit via a capacitor given by: Cj = ε 0ε Si W (V ) A With W the depletion width as a function of applied voltage and A the cross sectional area of the diode.
insulators. The third contact can control the current in the two other contacts or via an electrostatic field (attraction and repulsion of free charged carriers without current flowing) or via the injection of a small amount of current. section 2 p. Fabrication Fabrication of Si MOSFETs is a massive industry with big companies such as Intel. each separated by insulators. There is only 1 characteristic (1 IV and 1 CV) associated to these devices.oxidation at high temperatures (~1000°C) in pure O2 . The MOS cap makes the control contact on a MOSFET. Ge. AMD and Toshiba the main drivers behind the technological field.26).jpg) this IC consists of areas with memories. 40 .deposition of metals. the processor in your computers) is at the moment as high as 10. 1. W.…).net/images/articles/ppc970. GaAs. Au…) and insulators (SiO2.Chapter 3: The MetalOxideSemiconductor Field Effect Transistor – MOSFET In the previous chapter. This third contact will allow onoff switching of electrical signals – an electronic switch rather than a mechanical switch. it is essential to understand the workings of a MOS capacitor (see notes chapter 2. one IV graph per control signal value.etching (chemical and chemical/mechanical removal of material) .theinquirer. Transistors are characterised by a set of currentvoltage graphs. etc. This increased functionality of 3terminal devices has made them most popular in integrated circuits (ICs). These IC’s. In these devices the currentvoltage and capacitancevoltage characteristics are fixed by the processing and material parameters. which consists of a billion transistors. Right: What one buys/sees after packaging – a “black” box. Figure 1: Left a microscope picture of IBM's PPC 970 die (from http://www. and due to metal pads. are then packaged intro a chip carrier for protection and easy connection to the external world. And will allow amplification – a small signal on the third (control) contact will result in a larger signal at the other contact. This contact will control the current that is flowing between the two other contacts. …. The different colours are due to the different thicknesses and types of insulators.lithography (determination of protected and unprotected areas) .) All semiconductor devices consist of 3 types of materials: semiconductors (Si. The number of metal layers in an IC (e. The first gives a MOSFET and the second a BJT (bipolar transistor (see later). Si3N4.g. The 4 steps are: . IBM.…). we presented devices consisting of 2 contacts. In this course we’ll take a look at one MOSFET only and we will aim to understand the essential material needed and the physical processes behind conduction. In order to understand the operation of the MOSFET. busses. Ti. metals (Al. In transistors a third contact is introduced. Fabrication of MOSFETs (and other semiconductor devices) is based on the repetition of 4 important fabrication steps within an ultra clean environment – clean room.
2.2 and based on the knowledge of the MOS capacitor the operation of the MOSFET can be explained as follows: as the gate voltage increases from zero. The gate voltage is also applied between gate and source: VGS is the Gate voltage relative to Source. is normally connected to the source. Seen from source to drain. Draw the energy band diagram of an n+ – p – n+ junction in Si and compare this to the energy band diagram of an n+ – n – n+ junction in Si. each type can be either 41 . for short gate length (90 nm. In this course we will assume that the oxide is a perfect insulator. followed by a depletion region without mobile carriers.g. In this particular example the doping in the contacts is ntype and is opposite to the doping in the substrate (body. The source is normally grounded. These are Ohmic contacts made on heavily doped (indicated via the superscript + next to the doping type) semiconductor to make an as ideal contact as possible. The gate consists of a MOS capacitor thus a thin high quality SiO2 insulator on Si and a metal or heavily doped polySi on top of the oxide. (inversion). VDS is conventionally POSITIVE in an nchannel transistor. Functioning of MOSFETs In a MOSFET the conduction between DRAIN and SOURCE is controlled by the voltage applied to the GATE. Further increase beyond the threshold voltage causes accumulation of electrons to the surface. thus isolating the drain from the source in the absence of a positive gate voltage.channel SiO2 ~ 50 nm thick Gate Contact Drain Contact n+ Drain L = 0. at inversion. at zero gate voltage an n+ region is followed by a p region followed by an n+ region. What happened to the potential barriers? To which gate bias condition refers each of the band diagrams? * Voltage conventions Terminal voltages are usually by convention quoted relative to the source. Any influence of the contact will be taken into account via a resistance.1 . enhancement mode MOSFET. through the channel. There exist different types of MOSFETs depending on the type of carriers available in the channel and dependent on the existence or not of a channel for zero gate voltage. The depth to which the substrate is changed depends on the technology. The substrate is a ~500 µm thick Si wafer (polished disks of Si) on which the surface is modified via the fabrication steps (processing steps) to make devices. Thus seen from gate into bulk. There clearly exist pn junctions between the source and drain that disappear when the gate voltage becomes larger than the threshold voltage. e. In between the Ohmic contacts is the control contact – called the gate. at voltages larger than the threshold voltage first a region with free electrons is found. Thus the influence of the gate voltage on the sourcechannel and drainchannel pn junctions is to lower the potential barriers between contact and channel. The body. if necessary. This ensures that the drainbody pn junction is always reversebiased. The length of this gate is the distance between the source and drain contact in fig. With reference to fig. (i) p – channel – pMOS: inversion layer consists of holes and consequently current is carried by holes in the channel (ii) n – channel – nMOS: inversion layer consists of electrons and thus current carried by electrons in the channel of which. forming the conducting channel between source and drain. This length is parameter that has an important influence on the speed of the MOSFETs. followed by the ptype region of the substrate. The success of the MOSFET is completely due to the success in fabricating extremely high quality gate oxides. 2.10µm ptype Si body Source Contact n+ Source Figure 2: A schematic crosssection of a MOSFET The two contacts between which the currents are flowing are called the source (sourcing of carriers) and the drain (draining of carriers) contact. bulk). an n+ region is followed by an n region and then by an n+ region. or substrate. holes (majority carriers in the bulk) are first repelled from the channel region under the gate (depletion of majority carriers) thus a depletion region is built underneath the gate oxide between the source and the drain. 45 nm technology is the near future/current process) this depth reduces to 2050 nm.2 will results in an nchannel. In contrast. VDS is the Drain voltage relative to Source. The structure given in fig. For large gate lengths this depth will be down to 500nm.
Energy source channel VGS Ec EF drain Ev Distance from source to drain Figure 4: The influence of the gate voltage on the energy band diagram of an nMOS drawn from the source to the drain through the channel region under the gate oxide. The charge of carriers in channel and substrate after inversion is opposite. The device behaves like a capacitor when the voltage VGS is varied. VDS = 0 VGS + Gate SiO Source 2 Drain t ox  Figure 3: Enhancement mode nMOS with gate biasing but without drain biasing With VDS = 0V no current flows in the structure when the gate oxide is ideal (no current through the gate contact). the channel region turns ntype and the potential barrier at the contactchannel interfaces lowers. This is the condition for strong inversion. This is when the MOS capacitor is in depletion or accumulation. increases the amount of opposite charges at the opposite side of the insulator with the same amount. Thus increasing VGS beyond Vth must with Q the number of charges and V the applied voltage gives the results in an extra charge. Then the MOS capacitance is at its minimum. There are three different cases to consider: i) When VGS < Vth no conducting channel exists. This charge is carried by the electrons in the channel. 42 . Discussion of an nchannel enhancement mode MOSFET with no source drain bias applied. The smallsignal capacitance of the gate contact depends on voltage VGS. will not conduct at VGS = 0) b) depletion mode (normallyon. conducts at VGS = 0) Draw a schematic cross section of a depletion mode pMOS and determine the sign of the threshold voltage. Remembering C = dQ dV number of charges on the gate electrode as: Q = C (VGS − Vth ) (1) Assuming that the charge in the channel is zero when VGS =Vth. ii) When VGS = Vth. an inversion layer is being formed.a) enhancement mode (normallyoff. Note that at VGS=Vth the density of inversion charge in the channel is equal to the density of doping in the substrate. With increasing gate voltage. increasing the amount of charges on the metal of the capacitor. iii) When VGS > Vth the gate attracts more electrons to form a conducting channel (density of inversion charge is now larger than the density of doping atoms in the substrate). a charge equal to Q must then be present in the channel. As in a parallel plate capacitor. which forms the lower "plate" of the capacitor.
43 ..13) and the current flowing from drain to source is: I DS = −QC Wv e (4) With ve. Thus the voltage across the gate oxide at the source side is VGS and the voltage across the gate oxide at the drain side is VGSVDS=VGD which smaller than VGS for positive drain voltages. Cox is the capacitance per unit area and is called the oxide capacitance. It is unipolar as only the majority carriers are of influence on the current. the pn diodes that existed between the channel and the ohmic contact regions will have disappeared. i. the velocity of the electrons in the inverted channel region. IDS = constant and solving the above differential equation is straightforward: ∫I 0 L VDS DS dx = ∫C 0 ox Wµ e (VGS − V ( x) − Vth )dV With L the gate length and VDS the voltage applied on the drain with respect to the source a distance L removed from the high doping implanted ohmic contact region. is dV(x)/dx and the electron drift velocity ve from source to drain varies with x: dV(x) ve = µ e (5) dx Introducing (3) and (5) in (4) gives: I DS = C oxWµ e (VGS − V ( x) − Vth ) dV dx At every point in the channel the drain current is the same. the current through the inverted channel will be via drift only. the inversion charge at the Si/SiO2 interface is given by: when VDS = 0 (2) QC = −Cox (VGS − Vth ) QC is the charge per unit area carried by electrons in the channel (therefore the negative sign). If the potential at a point x along the channel relative to the source is V(x) then the voltage there across the oxide capacitance is VGS .V(x). The horizontal electric field strength at the point x.Derivation of the Drain Current Equation for nchannel MOSFET VDS VGS Gate SiO 2 Source x=0 y into paper x x=L Drain t ox z Figure 5: Enhancement mode nMOS with gate biasing and drain biasing As shown previously. the voltage across the gate/oxide/channel sandwich varies at different points in the channel between the source and drain. The area is the area of the gate (gate length x gate width). If the width of the channel is W (in the ydirection).e. When applying a voltage across this structure from source to drain we expect only current of electrons (now the majority carriers in each region). C = ε 0ε ox with t the oxide thickness ox ox t ox But when VDS >0. Looking from the source towards the drain through the channel we see a ntype region contacted by two ideal contacts. Therefore the MOSFET is often called a majority carrier device. Since in strong inversion the minority carriers are unimportant. the amount of charge passing the point x per second is QCWve (see p. Then the charge per unit area in the channel at the some point x is given by: for VDS > 0 Qc ( x) = −CC (VGS − V ( x) − Vth ) (3) Once the region underneath the gate oxide is inverted (strong inversion).
we use equation 6 to calculate the current with: VDS=VDSsat = VDS . In contrast the drain end of the channel is depleted and thus there are no free electrons near the drain. iv) p. This condition is called the onset of saturation in MOSFETs. In an ideal MOSFET the current remains constant as VDS is increased further.and nchannel devices with exactly the same geometry and biasing will carry different currents because of the different value of the mobility µ of holes and electrons. iii) For the same biasing arrangements. so the additional drain voltage (VDS . This marks the onset of drain current saturation. Increasing the drain voltage will increase the slope ot the curve. the potential difference between the gate and the drain end of the channel is now just Vth and thus theoretically. Energy source channel drain E Ec EFS EFD Ev Distance from source to drain Figure 6: The influence of the gate voltage (2 values of VGS) and drain voltage (1 value of VDS) on the energy band diagram of an nMOS drawn from the source to the drain through the channel region under the gate oxide.Vth. Applying a drain voltage will create an electric field across the channel region → energy bands tilt and e. These electrons are then transported through the channel via drift thus a current occurs. At saturation the supply of electrons is limited by the sourcechannel barrier independent on the electric field across the channel and then the current remains constant. To obtain an expression for the drain current in saturation. The value of the current needs to be determined for V DS > VGS − Vth .“roll down the hill”. The channel is said to be pinched off at the drain.Hence: I DS = Note: C oxWµ e L ii) The value of the quantity 2 (VGS − Vth )VDS − VDS 2 i) This result is only valid for VGS > Vth & V DS ≤ VGS − Vth C oxWµ e (6) L = 2 K is used by circuit designers. In the case VGS is above Vth (2nd curve down) the potential barrier between source and channel is lowered and injection of electrons into the channel region occurs.VDSsat) appears across it. In the case VGS is well below Vth (top curve) the potential barrier between source and channel blocks the injection of electrons into the channel region (where hardly any are available) and thus no current flows. For an ideal MOSFET the current in the saturation region – saturation current – is constant as a function of applied voltage on the drain. devices with different length to width ratios will carry different currents. (a) Ideal MOSFET When VDS = VGS . For example in the Analogue electronics courses.Vth ie sat I DS = C oxWµ e (VGS − Vth )2 2L (7) The pinched off region of the channel is very resistive. 44 . no inversion layer exists at the drain end of the channel.
analogous to that C oxWµ e (VGS − Vth )2 1 + VDS 2L VA (8) IDS VDS Figure 8: The family of currentvoltage characteristics for an enhancement mode nMOS.ID V GS3 locus of points at which V DS =V GS . well below the saturation point (left of the saturation locus) is called the triode region. a) Enhancement mode . The higher the gate voltage the higher the current. Right: depletion mode a channel exists without application of a gate voltage as a result of a metalsemiconductor work functioning difference or as a result of implantation of the bulk in the channel region with donor atoms 45 . The less inversion the higher the resistance of the channel and thus the shallower the slope of the IV curve.structure source n+ ptype Si body Enhancement gate n+ drain source n+ gate n+ drain n ptype Si body Depletion Figure 9: nMOS. (i) by an output resistance r0 in the equivalent circuit. and (ii) mathematically by the introduction into the equation for used for the BJT: sat I DS = sat sat I DS of an Early voltage VA. because when the effective length L of the channel reduces in eq(7).5 we see two major operation regimes in the MOSFET. The drain current now rises slightly above the value I DS . the current increases. Left: enhancement mode.depletion mode . Each currentvoltage curve corresponds to one gate voltage value. The locus of the pinchoff voltage position is given by the grey line. The one at low VDS voltages. From the family curves given in fig. Different types of MOSFETs exist are shown below. Thus the pinchedoff (depleted) region of the channel lengthens towards the source and the effective gate length (inversion layer length) reduces. Each currentvoltage curve corresponds to one gate voltage value. The MOSFET reached pinchoff at different drain voltages dependent on the gate voltage.Vth) the point along the channel at which the channel pinch off condition is reached is moving towards the source. In this region the MOSFET behaves as a voltage controlled resistor – control voltage is the gate voltage. The other region is above the point of saturation where the MOSFET behaves as a voltage controlled current source.V th V GS2 V GS1 0 V GS3 > V GS2 > V GS1 V DS Figure 7: The family of currentvoltage characteristics for an enhancement mode nMOS. The saturation current increases due to gate length modulation. No channel when no gate voltage is applied. The small increase in current in the saturation region is modelled in two ways. (b) Real device As VDS is increased above VDSsat = (VDS .
Top: structure and bottom: family of IV curves. Right: enhancement mode pMOS.tf. When the input is high the nMOS is on and pMOS is off and grounds the output. Figure 12: left: a schematic cross section of a CMOS. This combined structure is called a complementary MOS or CMOS and immediately behaves as an inverter! This makes the CMOS the device par excellent for digital applications.characteristics ID VGS 6 5 4 3 VDS Vth VGS VDS ID ID VGS +1 0 1 2 Vth VGS ID Figure 10: The family of currentvoltage characteristics for an enhancement mode nMOS (left) and a depletion mode nMOS (right). Draw the transfer characteristics for an enhancement and depletion mode pMOS. The left part of the structure is the pMOS and the right part (in the pwell) is the nMOS). when the input is low the nMOS is off and pMOS is on and connects the signal to VDD.de/matwis/amat/elmat_en/kap_5/backbone/r5_1_5. The threshold voltage is indicated in both cases. One of the strengths of MOSFETs is that it is easy to fabricate the combination of an nMOS and a pMOS in one structure. 46 . Right: the CMOS connection for making an inverter. c) nchannel .pchannel enhancement mode + S n+ p G + n+ D S p+ n G p+ D ID VGS 6 5 4 3 VDS ID 3 4 5 6 VGS VDS Figure 11: Left: Enhancement mode nMOS.html. Note the biasing condition on the pMOS..The transfer characteristic IDS versus VGS for 1 VDS is also shown for VDS in the saturation region.unikiel. Pictures taken from http://www.
One of the most important parameters is the transconductance gm. Cgs is given by: Cgs ≈ W L εSiO2 ε0 t ox where W = gate width and L = gate length as before This expression is actually only valid when no drain voltage is applied. The input (Gate ) Capacitance. 47 . so the current is small. rds = 1 / gds = (dID / dVDS ) 1 at constant VGS The gate capacitance will be an important parameter for digital applications as it determines the gate delay of a digital circuit. * Switching in MOSFETs For digital applications a low channel resistance means that the voltage drop across the MOSFET when operating as a switch is very small in ON state. The offcurrents in a MOSFET are also very small and thus in the OFF state the MOSFET will draw only a small amount of power. Transconductance.3. (this is the frequency at which point the current gain disappears). The output resistance gives an indication of channel length modulation effects and other effects which influence the character of the saturation current. At very low drain voltages a good approximation is to take triode C gs = C oxWL 2 In saturation. Some important parameters that determine the operation of the MOSFET can be determined via experimental characterisation and are used to linearise the MOSFET characteristics for use in circuit analysis in case small ac voltages are applied on the gate. due to changes in the distribution of charge in the channel. such that a small change in VGS results in a large current change. The higher gm the better the control and the better the cutoff frequency fT. The power consumption in a CMOS switch happens only when switching due to the charging effects of the gate capacitance. 1 MOSFET is always OFF when the other is ON. gm gm = dID / dVGS at constant VDS gm gives an indication of how well the gate controls the carriers in the channel. Small signal equivalent circuit of a MOSFET Gate id Drain v gs C gs g mv gs r ds Source Figure 12: Simple small signal equivalent circuit for a MOSFET that is valid in saturation. For a CMOS switch. the input capacitance becomes more: sat C gs = 2C oxWL 3 * Amplification in MOSFETs The channel resistance of a MOSFET in its onstate is very low. Inn reality Cgs varies with VDS in quite a complicated fashion.
Therefore in the EE1 course we will study BJT which consist of short diodes only25. As the supply of minority carriers is limited (small amount of minority carriers available) the current is small and constant as a function of electric field. Thus there are two pn junctions in this device. The current Isat is given by (see eq. Reverse biased pn junction. I=Isat independent of voltage V The reverse bias current in a pn diode is due to injection of minority carriers across the junction. 25 This will be extended in the EE2 course. 1. In order to understand why the connection of two pn junctions can give transistor family currentvoltage curves that is controlled via a current. In contrast the control contact in BJT will be an ohmic contact to the middle layer of the device that is able to inject current. the calculation of currents simplifies to calculations of currents in short pn diodes as we have seen in chapter 2. current will be due to diffusion as in diffusion gradients rather than absolute values of the carrier density are important.(11) Chapter 2. 1 Principles behind the operation of a BJT A bipolar transistor consists of a connection of three materials in the form of an npn or a pnp junction. When looking back at the MOSFET we see that actually the sourcechanneldrain also forms an npn or pnp junction.Chapter 4: The Bipolar Transistor – BJT In contrast to the MOSFET that is a majority carrier device where the strong inversion characteristics are determined by drift. It is the magnitude of this current that will influence the magnitude of the current between the two ohmic contacts on the other layer of the BJT. Thus when minority carriers are important. 48 24 . The question is therefore. The control contact is B (base). The current in the base will control the current between E and C (emitter and collector). In figure 1 a schematic cross section of a planar BJT is given.): D p p n Dn n p I sat = eA + L Ln p V Dp Dn = eAni2 + N L D p N A Ln I (1) I p n Isat V Figure 2: pn diode under reverse bias (left) and the offleakage current (right) Note that drift of minority carriers results in very small currents only for any acceptable magnitude of applied voltage. we will take a closer look at the pn diodes involved. The first important difference is that the BJT does not have a control contact that is insulated from the middle layer of the device as in a MOSFET. The bipolar transistor is a relatively complicated device when compared to the MOSFET. the bipolar junction transistor is a minority carrier device meaning that the minority carriers in the different regions of the device will determine the current governed by diffusion24. However under the right assumptions. why is the BJT different from the MOSFET. B E C p+ Si n+ Si p Si n Si p+ Si p Si Figure 1: Schematic cross section of a planar npn bipolar transistor on a ptype Si substrate.
49 26 . Then majority carriers are injected across the junction: hole from the pregion into the nregion and electrons from the nregion into the pregion. more minority carriers are generated and the off current Isat increases. The picture is completely different for minority carriers as originally there were only about 103 cm3 available. The result is given in figure 4. IE VEB IC VBC IB p+ Emitter n Base Wb p Collector IC IE VBC holes injected holes collected Figure 4: Left a connection of two pn junctions. one p+n is forward biased and the second one np is reverse biased. In case we make an asymmetric pn diode with a heavily doped pregion and a lowly doped nregion. The output current at C will then be the offcurrent of the second junction as shown right. Then the amount of holes injected from p to n is a lot larger than the amount of electrons injected from n to p. Minority carrier injection by a hypothetical device (hole injector) If we want to increase the off leakage current in a pn diode.2. In that case the holes injected by the first junction increases the minority carriers in the second layer which will be collected by the reverse biased junction. This can for instance be done by shining light with an energy (and thus associated wavelength – “colour”) larger than the bandgap of the semiconductor ( E = hυ = h electron hole pairs and thus increase the minority carrier substantially compared to what was originally available26. 2 eV ni eV p ' n = p n0 exp exp = kT N D kT 2 eV ni eV n' p = n p0 exp exp = kT kT N A N A >>> N D ⇒ ni2 n2 <<< i ⇒ n' p <<< p' n NA ND (2) I p ∝ p ' n & I n ∝ n' p I p >>> I n ⇒ I tot ≈ I p Thus a forward biased p+n junction is a hole injector. will increase the offcurrent as illustrated in figure 3. λ ). Thus increasing minority carrier concentrations np and pn in equation (1) through this process.g. This will create V I I p n V Isat hole injector Figure 3: Reverse biased pn junction with light shining of the device. This is a common base configuration. we have to find a method to generate more minority carriers than already available under bulk conditions. When the intensity of the light increases. It will also increase the majority carriers but since there are already a large amount available to start with (1017 cm3) a bit more (e. This forward biased p+n junction can replace the light used in the previous section in order to inject holes into the n region of a reverse biased np junction. 103 cm3) will not make a big difference. Minority carrier injection by a semiconductor device (hole injector) Remember the pn diode under forward bias. 3.
the middle region – the base – should be sufficiently short. We will investigate each current component IE (emitter current). The main current component in a pnp transistor are holes. and thus simplifying the graphical picture. 2 Currents in a short BJT The currents in a bipolar transistor are determined by diffusion of carries in the different regions similar to the pn diode. If we assume the emitter base is a short diode. The emitter current IE The emitter current is defined as the total current across the emitterbase junction. The total current across the EB junction is the sum of these two current components: Thus I E = I nEB + I pEB . we study the pnp rather than the npn BJT. An extremely important remark in BJTs is that in order to function properly. in an npn transistor are electrons. this is solely due to the fact that hole flux and hole current point in the same direction. Find the two main differences between the layer structure from source to drain through channel of an nMOS (no bias applied) and an npn BJT. In forward bias across a pn junction. holes are injected from the p region to the n region – thus from emitter to base and electrons are injected from the n region to the p region – thus from base to emitter. The total emitter current is In+Ip. Due to the knowledge on the variation of the minority carrier concentration we can calculate the diffusion currents across the EB junction: ( p ' − p"n ) ≈ eADp pn0 exp eVEB I p = eADp n Wb Wb (3) kT (n'p − n p0 ) ≈ eADnn p0 exp eVEB I n = eADn xe xe kT Note that the minority carrier concentration in the base at the collector side is determined by the basecollector voltage. which in active mode is reverse biased (VBC<0). then the emitter current can be easily calculated. IC (collector current) and IB (base current) separately (see fig.The heavily doped p layer on the forward biased junction is called the emitter. When the emitter is heavily doped ntype. In what follows we will assume that the base region is thinner than the diffusion length L of the minority carriers. the minority carrier 27 A proof will be given in the 2nd year course 50 . The width of the emitter is xe and of the base is Wb. is called the collector.4 for the definition of the different currents in a BJT) for the transistor is active mode (EB junction forward biased and BC junction reverse biased) 1. the base lowly doped p and the collector lowly doped n then we have an npn transistor. of the reverse biased junction. If the base is short the minority carriers injected into it from the emitter will all be collected by the reverse biased collector junction27. The middle layer is called the base and the other outer layer. In what follows. This structure is a pnp BJT. Minority carrier concentration E B p’n n Ip h+ In en’p BaseCollector junction Ideal ohmic contact p+ np0 Determined by VBC p”n xe VEB Wb Distance in the direction of current flow Figure 5: Minority carrier concentration in a forward biased emitter base p+n junction. For sufficiently large forward bias conditions. but the control current through the base is respectively electrons and holes (thus opposite to the carriers forming the main output current).
This current is the offleakage current of the reverse biased pn junction given by eq. the collector junction is reverse biased and there will be a reverse biased current component that is only due to the BC junction (thus as if not connected to the emitter). IB = IB’ + . Holes are injected into the thin base from the forward biased emitter. The current associated to this hole flow is the hole current that is flowing in the base and is given by the previously calculated Ip in eq. Thus from eq.concentration at the EB junction is a lot larger than the minority carrier concentration at the contact and at the BC junction. (3). On the other hand. (1) with minority carrier values as given in the bulk material (before junction were made). However the pure offleakage current in a pn junction is very small and is negligible compared to the injected hole current that is flowing in the base. The collector current IC The reverse biased collector will collect all the minority carriers made available by the base at the BC junction. Since all the holes injected into the base by the emitter are diffusing from the base to the collector. all these holes will be collected.ICBO where IB’ = base current injected into the emitter ICBO = reverse bias leakage current into collector (very small indeed) 51 . we have lost the physical reason behind the fact the the base current is the electron current that is escaping from the base. They diffuse towards the collector where they are accelerated by the large electric field across the reverse biased base/collector junction and contribute to the collector current. Therefore the total collector current is: eAD p pn0 eV (4) IC ≈ I p = exp EB Wb kT 3. 2) electrons injected across the forwardbiased emitter junction 3) thermally generated electrons and holes making up the reverse saturation current of the collector junction. The base current IB In principle is it now very easy to derive the base current from the knowledge of the collector and emitter current. 2. VEB IB p+ IE e  VBC p 3) h+ IC 2) n 1) Figure 7: Different current components that are flowing in the base under the condition of a short base (Wb shorter than the diffusion length of the minority carriers that are flowing through the base) in a pnp BJT in active mode. Since no current can be lost in the device we have to find that the base current has to make up for the difference between the emitter and collector current following: IC IB IE IE=IB+IC Figure 6: The currents in a pnp BJT in active mode. In what follows we will reestablish this physical interpretation. 1) holes reaching the reversebiased collector junction. (3) and (4) we find that eADn n p 0 eV IB = In = exp EB xe kT (5) Although this approach is completely acceptable.
This is because in common base a direct control of the junction biases is available that allows a straightforward connection of the BJT to the pn junction diodes operations. the base current is the control current and there exist a gain between the base current and the output current. 4 Physics behind the BJT small signal equivalent circuit ib B ic C βib vbe rbe or rce Figure 8: Simplified small signal equivalent circuit of a BJT E gmvbe 52 . In most circuits however the common emitter configuration is more popular. high base resistance when lowering the base doping). Left: in common base connection the control current is the emitter current and no real gain can be found between emitter and collector current. Emitter efficiency in a short BJT I Ip 1 1 γ = p = = = IE In + I p 1 + In 1 + 1 Ip β The emitter efficiency describes which part of the total emitter current is used to generate the collector current.The base current comes from the fact that the electrons that are disappearing out of the base via the forward bias junction need to be resupplied in order to avoid losing equilibrium charge conditions. active IC IE cutoff IC IB cutoff active VCB VCE saturation saturation Common base connection Common emitter connection Figure 8: Family curves of the BJT. Note that definition of saturation in the BJT is different from in the MOSFET. Thus the bias across the basecollector junction can change with both VBE and VEC. Thus for a good BJT we want β to be large and γ to be equal to 1. Right in commonemitter configuration. (4) & (5)): eV eAD p pn0 xe exp EB (6) IC I p kT = D p N AE xe β= = ≈ I B In eVEB Dn N DB Wb eADn n p0Wb exp kT In order to increase the current gain one can: a) increase the doping density of the emitter or decrease the width of the base. If the carriers would not be resupplied then equilibrium charge condition can only be obtained by a changing voltage drop across the junctions. Changes in the other parameters lead to other detrimental effects (e. Note: in the saturation region the basecollector junction is forward biased. The regions with constant current are the active regions and outside the active region is the saturation region. Current gain in the short BJT The current gain is the ratio of the collector current to the base current and this is given by (see eq. 3 Other BJT connections In the previous we used the common base connection in order to explain the currents in the BJT. In the common emitter configuration the two bias voltages used in BJT biasing are: one between the emitter and base (control of IB) and one between the emitter and collector.g.
the current increases with increasing reverse bias across the BC junction. rbe ic = vbe dIC dVBE dVBE dVBE dIC = dI B dIC dI B Note: in a MOSFET the input resistance is infinite (in case of an ideal gate oxide) because no gate current flows for DC bias conditions. 53 . Since the collector current is indirectly proportional to the active base width. similar to gate length modulation in MOSFETs. the basecollector junction is increasingly reverse biased. Therefore the resulting active base width (undepleted base width) is decreasing as the reverse bias voltage goes up. rce rce = dVCE dIC In real BJTs the current in active mode is not completely constant but increases slightly with increasing bias voltage. This feature is due to base width modulation. rbe = Output resistance. In the BJT the input resistance is determined by the pn diode differential resistance as given on p39 (chapter 2). such that a small input voltage change can result in a high current change.Smallsignal current generator β dI C ic β= = dIB ib (alternative symbol hfe) for high gain we require (i) small base width W (ii) large emitter doping. compared to base doping. * Amplification with a BJT In bipolar transistors the input impedance is low. For increasing bias in the active region. This has the consequence that the depletion region of the BC junction widens. Transconductance gm = Input resistance.