Digital Timing Analysis Digital Timing Analysis

, Ruey-Beei Wu
Rm. 340, Department of Electrical Engineering E-mail: rbwu@ew.ee.ntu.edu.tw url: 140.112.19.180

Contents
Common-clock Bus Design Source Synchronous Design

R. B. Wu

Block Diagram of Common-Clock Bus

Sequence of a data transfer
Processor core provides data at input Dp System clock edge 1 (clk in) propagates down Tx-line and latches data from Dp to output Qp. Signal on Qp propagates down a line to Dc and is latched in by clock edge 2. Max. clock rate is decided such that the delay of circuitry and tx-line must be smaller than the cycle time. R. B. Wu

Timing Diagram common-clock bus

Nomenclature
Tco: time from clock to output Tflt: flight times of tx line delay Tjitter: clock jitter, cycle-to-cycle variations R. B. Wu

Timing Equation Setup/Hold Timing

Setup timing loop
T data tot = Tco clkB + Tflt clkB + Tco data + Tflt data T clock tot = T cycle + Tco clkA + Tflt clkA Tjitter T setup margin= (T clock tot Tdata tot) Tsetup = Tcycle TPCB skew Tclock skew Tjitter Tco data Tflt data Tsetup
Tclock skew = Tco clkB + Tco clkA TPCB skew= Tflt clkB Tflt clkA

Hold timing loop

T hold margin= (T data tot Tclock tot) Thold = Tco data + Tflt data + Tclock skew + TPCB skew Thold

R. B. Wu

Rules of Thumb common-clock bus design

Common-clock techniques are adequate for medium-speed buses with frequencies below 200 to 300 MHz. The component delays and PCB trace delays place a hard theoretical limit on the max. speed. Subsequently, a max. limit is placed on the lengths of the PCB traces. Trace propagation delays are governed by trace length. Trace length are often governed by the thermal solution. As speeds increase, hear sinks get larger and force components farther away from each other, which limit the speed

R. B. Wu

Source Synchronous Clock Bus

Advantages: significant increase in max. bus speed.

Limitations on freq.
Delay difference between data and strobe The difference depends on SSN, trace lengths, Zo, SI, & buffer characteristics

R. B. Wu

Block Diagram of Source Synchronous Bus

Transmission of strobe must be timed so that both setup and hold requirements of the receiver latch are satisfied.

R. B. Wu

Setup Timing Source Synchronous bus

T data = Tco data + Tflt data T strobe = T co strobe + Tflt strobe + Tdelay T setup margin= (Tstrobe Tdata) Tsetup = Tvb Tsetup TPCB skew where Tvb = Tco data (Tco strobe + Tdelay) < 0 TPCB skew = Tflt data Tflt strobe R. B. Wu

Hold Timing Source Synchronous bus

T data = Tco data + Tflt data + Tdelay T strobe = T co strobe + Tflt strobe T hold margin= (Tdata Tstrobe) Thold = Tva Thold TPCB skew where Tva = Tco data Tco strobe + Tdelay > 0 TPCB skew = Tflt data Tflt strobe R. B. Wu

Alternative Source Synchronous Scheme

Tva = Thold margin + Thold + TPCB skew T hold margin= Tva Thold TPCB skew Tvb = Tsetup margin + Tsetup + TPCB skew T setup margin= Tvb Tsetup TPCB skew

R. B. Wu

Rules of Thumb Source Synchronous

No theoretical limit on max. bus speed Bus speed depends on difference in delay (skew) between data and strobe. SI cause unwanted skew and thus limits on max. speed. Flight time is not a factor. It is beneficial to make strobe signal identical to data signal (so as to minimize skew)

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Alternative Source Synchronous Scheme

Dual-strobe technology

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Alternative Bus Signaling Techniques

Source synchronous timing sends strobe later than data and suffers from SI at different time, causing skew. Indident clocking
Data & strobe are sent out simultaneously. Delay the strobe on the silicon at receiver. Coupled noise should be much smaller.

Embedded clocking
Embed the clock into the data signal. PLL constructs a clock from data patterns Some overhead in data signals, say 20%.
R. B. Wu