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Solid-State Electronics 43 (1999) 791799

A high speed and low power SOI inverter using active body-bias
Joonho Gil a, Minkyu Je a, Jongho Lee b, Hyungcheol Shin a,*
a

Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1 Kusong-dong, Yusonggu, Taejon 305-701, South Korea b School of Electrical Engineering, Wonkwang University, 344-2 Shinyong-dong, Iksan, Chonpuk 570-749, South Korea Received 17 September 1998; received in revised form 10 November 1998

Abstract We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with ecient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5 V, the proposed circuit operates 27% faster than the conventional SOI circuit with almost the same power dissipation. # 1999 Elsevier Science Ltd. All rights reserved.

1. Introduction One of the main approaches to low power consumption is to reduce the supply voltage. However, reducing the supply voltage should be accompanied by a threshold voltage reduction and the reduction of the threshold voltage is limited by the amount of the ostate leakage current. One solution to this problem is a dynamic threshold operation by applying an active body-bias to MOSFETs [1]. Because of low threshold voltage during the logic transition and high threshold voltage during the o-state, the dynamic threshold circuit operates at high speed with low power. The body of an SOI MOSFET can be easily isolated from other electrical nodes, which makes the dynamic threshold scheme possible by applying an independent body-bias. Several SOI dynamic threshold circuits have been proposed recently (Fig. 1) [14].

In this paper, we propose a new scheme of a high speed, low power SOI inverter using active body-bias [5]. The proposed circuit is evaluated and compared with other schemes by both circuit simulation and device simulation. Also, the dependence of the circuit performance on the body resistance of the MOSFETs is evaluated.

2. Circuit description The proposed inverter circuit is shown in Fig. 2. The bodies of the main MOSFETs, Mn and Mp, are connected to the sources of the subsidiary MOSFETs, Mn and Mp, respectively. The subsidiary MOSFETs are designed to be small. The additional input capacitance increase is only the junction capacitance of the subsidiary MOSFETs. Fig. 3 compares the layouts of the proposed inverter and the conventional SOI inverters with source-body tie structure and T-gate structure body contact. For compact layout of the proposed inverter, T-gate

* Corresponding author. Tel.: +82-42-869-3459; fax: +8242-869-8590. E-mail address: hcslab@eekaist.kaist.ac.kr (H. Shin)

0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 9 8 ) 0 0 3 3 7 - 2

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electrons of Mn are injected into the body of Mn and recombined with the holes and also because of the drain-to-body capacitive coupling of Mn (region B). When IN changes from `H' to `L' during pull-up, initially the body potential of Mn decreases abruptly due to the oating body eect because Mn is o at this time and therefore the body of Mn is oating (region C) [6]. As OUT increases, the body potential increases due to the drain-to-body capacitive coupling (region D). When OUT goes up above the VT of Mn, Mn turns on and the body potential of Mn returns to `L' (region E). The operation of the PMOSFETs can be explained symmetrically. 3. Simulation results We used the BSIM3SOI circuit simulator [7] and ATLAS two dimensional device simulator [8] to simulate the proposed circuit, and compared the performance with the other circuits. The transient waveforms of the output and the body potential of the main MOSFETs were compared with those of the conventional SOI inverter in Fig. 4. The initial body potential increase in the main MOSFETs is close to 0.7 V. Fig. 5 shows the IDVGS characteristics of the pulldown stage. The results were obtained by mixed-mode simulation. The insert is the simulation domain of the pull-down stage. From this, we were able to observe the superior IV characteristics of the proposed

Fig. 1. Reported SOI inverter circuits. (a) circuit in Ref. [1]. (b) Circuit in Ref. [2].

devices are used and the body of the main MOSFET and the source of the subsidiary MOSFET are connected with the contact-silicide. In the conventional SOI inverter, Fig. 3(b) is more compact than Fig. 3(c). In the simulation, the width of all subsidiary MOSFETs (Mn and Mp) are 1 mm and that of the main MOSFETs (Mn and Mp) are 12 and 24 mm, respectively. In comparison, 14 mm (N) and 28 mm (P) devices in the conventional SOI were used in the simulation for the same total area. The pull-down operation of the proposed inverter is as follows (Fig. 4). When IN is `L' and OUT is `H', Mn is o and Mn is on. At this time, the body potential of Mn is `L'. When IN changes from `L' to `H', both Mn and Mn are on simultaneously. The body potential of Mn becomes charged up to the diode turn-on voltage of about 0.7 V soon after the pull-down begins (region A in Fig. 4). The lowered threshold voltage of Mn enhanced the drain current and the pull-down transition time is reduced. Also, the higher channel mobility [1] and parasitic bipolar action [2] contribute to the enhanced performance. As OUT goes down, the body potential of Mn decreases because some channel

Fig. 2. The proposed circuit scheme. Mn and Mp are the main MOSFETs. Mn and Mp are the subsidiary MOSFETs.

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Fig. 3. Comparison of the layouts. (a) The proposed inverter. (b) The conventional SOI inverter with source-body tie structure body contact. (c) The conventional SOI inverter with T-gate structure body contact.

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Fig. 4. OUT and body nodes transient waveforms of the proposed circuit. The eective gate length of all MOSFETs is 0.25 mm. The width of all subsidiary MOSFETs are 1 mm and that of the main MOSFETs are 12 mm (N) and 24 mm (P). In comparison, 14 mm (N) and 28 mm (P) devices in the conventional SOI were used. The solid line and the dashed line are the results from circuit simulation and device simulation, respectively.

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Fig. 5. The IDVGS characteristics of the pull-down stage with the xed drain voltage of 1.5 V obtained by device simulation. The silicon lm thickness in the simulation domain is 200 nm. Also, the device sizes are as follows: W/L = 12/0.25 mm (main), 1/0.25 mm (subsidiary) for the proposed and Ref. [2] schemes, W/L = 11.5/0.25 mm (main), 1/0.25 mm (subsidiary 1), 0.5/0.25 mm (subsidiary 2) for the Ref. [3] scheme, W/L = 14/0.25 mm for the conventional SOI scheme. (a) Drain current. (b) Body potential.

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Fig. 6. Delay time and power dissipation of 7-stage inverter chains at 100 MHz. The device sizes are as follows: W/L = 12/0.25 mm (N-main), 24/0.25 mm (P-main), 1/0.25 mm (subsidiary) for the proposed and Ref. [2] schemes, W/L = 14/0.25 mm (N), 28/0.25 mm (P) for the conventional SOI circuit. The total layout area of the proposed circuit is the same as the conventional one.

scheme. The proposed circuit had the lowest input threshold voltage and the highest body potential compared with the other schemes, which led to the highest speed. To check the ac performance and how the supply voltage aects the delay time and power dissipation, 7stage inverter chains were simulated at Cint = 70 fF and CL = 200 fF (Fig. 6). At the supply voltage of 1.5 V, the proposed circuit operates 27% faster than the

conventional circuit with almost the same power dissipation. The proposed circuit also runs 16% faster than the circuit reported in Ref. [2] because our circuit has a smaller input threshold of the Mn and higher body potential. Also, the circuit in Ref. [3] requires two more MOSFETs than the proposed circuit. As the supply voltage decreases, the speed advantage of the proposed circuit increases. At the supply voltage of 1.2 V, the proposed circuit has the speed merit of 35 and

Fig. 7. Load capacitance dependence of delay time and power dissipation at Vdd of 1.5 V.

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Fig. 8. The body series resistance dependence of the delay time.

22% over the conventional SOI circuit and the circuit in Ref. [2], respectively. Fig. 7 shows how the load capacitance aected the delay time and power dissipation at Vdd of 1.5 V. As the load capacitance increases, the advantages of the proposed circuit over the conventional SOI also increases. The proposed circuit operates 20% faster at 100 fF and 23% faster at 700 fF than the conventional SOI.

4. Design insight Fig. 8 shows how the body resistance on the main MOSFETs aected the delay time. As the body resistance increases, the speed performance degrades. To limit the delay time increase due to the body resistance to less than 5%, the body resistance should be kept below 3 kO/q.

Fig. 9. The current drivability of the various channel doping engineering obtained by device simulation. Device parameters are (a) NA = 2.5 1017 cm3; (b) NA = 2 1017 cm3, N+ = 1 1018 cm3, d = 55 nm and (c) NA = 2 1017 cm3, N+ = 1 1019 cm3, A A d = 60 nm.

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In the previous study, very large DVt can be obtained by using the retrograde doping [9]. How the doping engineering aected the circuit performance is shown in Fig. 9. The current drivability of the retrograde doped inverter is dramatically enhanced compared with that of the uniformly doped inverter due to the higher body eect factor. Also, note that the retrograde-doping results in reducing the body resistance. Consequently, to reduce the body resistance and

maximize DVt, retrograde doping engineering is recommended. Fig. 10(a) shows the proposed circuit diagram of the NAND gate as one of the applications of the proposed scheme. The gates of all subsidiary MOSFETs in series network should be connected to the output node for both the subsidiary MOSFETs to operate eectively. When VB changes of the xed VA of 1.5 V, resultant output waveforms for both the

Fig. 10. (a) The proposed circuit diagram of NAND gate. (b) Transient waveforms. Device sizes are as follows: (W/L )main = 7/0.25 mm and (W/L )subsidiary = 1/0.25 mm for the proposed NAND circuit, (W/L )N,P = 9/0.25 mm for the conventional SOI NAND circuit.

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proposed and the conventional circuits are shown in Fig. 10(b). It can be seen that the speed of the proposed NAND circuit is superior to that of the conventional SOI circuit. 5. Conclusion We have proposed a new scheme of high speed and low power SOI inverter using an active body-bias. The operation and performance of the circuit was evaluated by BSIM3SOI and ATLAS simulation. The proposed circuit shows excellent characteristics for high speed and low power applications. The proposed circuit also can be applied to the general CMOS logic circuits for low power applications. Acknowledgements The authors wish to acknowledge Stephen H. Tang in UC Berkeley for much technical support.

References
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