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**Chris Haji-Michael
**

www.sunshadow.co.uk/chris.htm

This sheet is used to design a low speed Miller Operational Amplifier, using the technique explained by Willy

Sansen in his book "Analog Design Essentials" chapters 1 and 6, main slide 0629.

PMOS input devices are chosen as these normally have better matching and lower noise. There is a good

explanation of why this is generally better in Analog integrated Circuit Design, Johns, Martin, page 232

Cc in the following schematic is replaced with Cc and Rc in series.

Design Inputs yellow; BSIM inputs blue; outputs green

µm

m

10

6

:·

kohm 1000 ohm ⋅ :·

q 1.60217733 10

19 −

⋅ coul ⋅ :·

k

b

1.380658 10

23 −

⋅

joule

K

⋅ :·

T 270K :·

e

ox

8.8542 10

12 −

⋅ 3.9 ⋅

F

m

⋅ :·

The starting point of the analysis

focuses on this graph, which shows the

EKV model and gives i the inversion

coefficient for Vgs-Vt.

The EKV model allows a single equation

to be used for both the striong inversion

and weak inversion operating zones on

the FET.

This model allows Vgs-Vt (Vgt) to be

negative and typically vary from -0.2 to

0.5V. It is unusualy positive, otherwise

the ROUT is too low and we get no gain.

STEP 1. Design requirements in yellow. Blue are the BSIM3 MOS parameters.

CL = a Cc, Cc = ß Cgs6, F6 = ? GBW

Normally these are 2 3 2

TOX 510

9 −

m :· U0

n

388

cm

2

V s ⋅

:· UA

n

6.5 10

9 −

×

m

V

:· UB

n

4.2 10

18 −

×

m

2

V

2

⋅ :·

NFACTOR

n

1.14 :· VTH0

n

0.633V :· VSAT

n

86301

m

s

:·

U0

p

139

cm

2

V s ⋅

:· UA

p

1.399 10

9 −

×

m

V

:· UB

p

1.0 10

19 −

×

m

2

V

2

⋅ :·

NFACTOR

p

1.54 :·

VTH0

p

0.673V :· VSAT

p

103503

m

s

:·

STEP 2. From U0 and the other BSIM mobility parameters, calculate the mobility for the NMOS and the PMOS

devices as this changes with Vgt. The equations for this are from W Liu "Mosfet Models for Spice Simulation",

page 249. Assume MOBMOD=1 which is the default.

µ

n

Vgt ( )

U0

n

1 UA

n

Vgt 2 VTH0

n

⋅ +

TOX

⋅ + UB

n

Vgt 2 VTH0

n

⋅ +

TOX

¸

¸

_

,

2

⋅ +

:·

µ

p

Vgt ( )

U0

p

1 UA

p

Vgt 2 VTH0

p

⋅ +

TOX

⋅ + UB

p

Vgt 2 VTH0

p

⋅ +

TOX

¸

¸

_

,

2

⋅ +

:·

0.2 − 0.1 − 0 0.1 0.2

80

100

120

140

160

µ

n

Vgt ( )

cm

2

Vs ⋅

µ

p

Vgt ( )

cm

2

Vs ⋅

Vgt

µ

n

Vgt6 ( ) 118.769

cm

2

V s ⋅

⋅ ·

This shows how the mobility

changes with Vgt for both the

NMOS and PMOS

It is 50% higher for the NMOS

STEP 3. Calculate FT (frequency at which gain equals 1) for transistor M6 to get the gain-bandwidth. From this

we can calculate L (Gate Length) and we use this same L for most of the transistors. The EKV model is used

here, as this is what Samson uses, refer slides: 0138, 0140, 0165, 0627. The gate length needs to be at least

twice the minimum.

V

GSTtn

2 NFACTOR

n

⋅

k

b

T ⋅

q

⋅ :· 0138 0138

i Vgt ( ) ln e

Vgt

V

GSTtn

¸

¸

_

,

1 +

¸

1

1

]

¸

1

1

]

2

:·

GM Vgt ( )

1 e

i Vgt ( ) −

−

i Vgt ( )

:· 0140 F

T

a ß ⋅ ? ⋅ 1

1

ß

+

¸

¸

_

,

⋅ GBW ⋅ :· 0627

0165

L

n

Vgt F

T

, ( )

µ

n

Vgt ( )

k

b

T ⋅

q

⋅

p F

T

⋅

i Vgt ( ) 1 e

i Vgt ( ) −

−

¸

¸

_

,

⋅

¸

1

]

⋅ :·

V

GSTtn

0.053 V ⋅ · i Vgt6 ( ) 14.386 ·

L

n

Vgt6 F

T

, ( ) 0.824 µm ⋅ · F

T

480 MHz ⋅ ·

2 10

8

× 3 10

8

× 4 10

8

× 5 10

8

× 6 10

8

× 7 10

8

× 8 10

8

×

6 10

7 −

×

7.333 10

7 −

×

8.667 10

7 −

×

1 10

6 −

×

1.133 10

6 −

×

1.267 10

6 −

×

1.4 10

6 −

×

L

n

0.2V FT , ( )

FT

This graph shows how the length of

the gate influences the FT (the

frequency at which the gain is 1)

0.2 − 0.1 − 0 0.1 0.2

0

0.2

0.4

0.6

0.8

1

L

n

Vgt F

T

, ( )

µm

Vgt

We also get this strange graph that

shows how the required gate length

changes with Vgt.

STEP 4. Use the following equations to calculate the widths and currents of M6 and M5, which are dependent

on CL.

C

c

C

L

a

:· C

gs6

C

L

a ß ⋅

:· 0621 C

ox

e

ox

TOX

:· W

6

C

gs6

3

2

⋅

1

L

n

Vgt6 F

T

, ( ) C

ox

⋅

⋅ :· 0161

I

DSt6

µ

n

Vgt6 ( ) C

ox

⋅

W

6

L

n

Vgt6 F

T

, ( )

⋅ V

GSTtn

( )

2

⋅ :· 0138

I

DS6

I

DSt6

ln 1 e

ln e

i Vgt6 ( )

1 −

( )

+

¸

¸

_

,

¸

¸

_

,

⋅ :·

I

DSt6

8.199 µA ⋅ · C

c

0.333 pF ⋅ ·

g

m6

GM Vgt6 ( ) I

DS6

⋅ 2 ⋅

V

GSTtn

:· 0141

g

m6

0.302

mA

V

⋅ ·

I

DS6

31.099 µA ⋅ · W

6

29.278 µm ⋅ ·

STEP 5. We need the Early voltage for M6 so that we can calculate the output resistance to get the voltage

gain. From this we can convert Cc to the equivalent input capacitance from the Miller equation. W Liu "Mosfet

Models for Spice Simulation", equations A-62, A-78. The equivalent Early voltage is VA and this converts to

the ro6 by the slope at the point of operation. The output impedance is halved as M5 needs to be considered and is

assumed to be equal to rout of M6. Also a 1/2 adjustment is made for ro, as we are working near VTH0 and ro is

reduced.

e

sat6

2 VSAT

n

⋅

µ

n

Vgt6 ( )

:· VA6 e

sat6

L

n

Vgt6 F

T

, ( ) ⋅ :· ro6

1

2

VA6 VTH0

n

+ Vgt6 +

I

DS6

¸

¸

_

,

:· ro5 ro6 :·

Vgain6 g

m6

ro6

2

⋅ :· C

n1

C

gs6

1 Vgain6 + ( ) C

c

⋅ + :· ro6 2.06 10

5

× ohm ⋅ · VA6 11.979 V ⋅ ·

C

n1

10.818 pF ⋅ · Vgain6 31.119 ·

Vgain6_dB 10 log Vgain6 ( ) ⋅ :·

Vgain6_dB 14.93 ·

STEP 6. Now scale M1 and M2. Keep Vgt1 low to minimise noise. B needs to be high to save current, but

recommend this is kept at 1. L needs to be greater than twice the process minimum.

g

m1

2 p ⋅ C

n1

⋅ GBW ⋅ :· 063 I

DS1

I

DS6

2 B ⋅

:· GM1

g

m1

I

DS1

NFACTOR

p

⋅

k

b

T ⋅

q

⋅ :· 0141

i 1 :· Given GM1

1 e

i −

−

i

= i Find GM1 ( ) :·

0165

and 065 for FT V

GSTtp

2 NFACTOR

p

⋅

k

b

T ⋅

q

⋅ :· L

p

µ

p

Vgt1 ( )

k

b

T ⋅

q

⋅

p

F

T

4

⋅

i 1 e

i −

−

¸

¸

_

,

⋅

¸

1

]

⋅ :·

L

p

0.515 µm ⋅ ·

W

1

I

DS1

i

L

p

⋅

µ

p

Vgt1 ( ) C

ox

⋅ V

GSTtp

( )

2

¸

1

]

⋅

:· 0138

W

4

W

6

2

1

B

⋅ :·

g

m1

1.359

mA

V

⋅ ·

W

1

36.276 µm ⋅ ·

STEP 7. Calculate the voltage gain for stage 1 and then calculate the overall voltage gain. The output

resistance is the Early voltage divided by the current. This is halved because both there are two FETS and the

gain is halved again as we are working near VTH0 and the output resistance is slightly lower at this point.

e

sat1

2 VSAT

p

⋅

µ

p

Vgt1 ( )

:· VA1 e

sat1

L

p

⋅ :· ro1

1

2

VA1 VTH0

p

+ Vgt1 +

I

DS1

2

¸

¸

_

,

:·

Vgain1 g

m1

ro1

2

⋅ :· Gain_dB 20log Vgain1 Vgain6 ⋅ ( ) :· VA1 10.827 V ⋅ ·

Vgain1 507.055 ·

Vgain1_dB 10 log Vgain1 ( ) ⋅ :·

ro1 7.46 10

5

× ohm ⋅ · Vgain1_dB 27.051 ·

STEP 8. Calculate the compensation components Rc and Cc. This is calculated to 5.74, 5.75, 5.76 according

to Analog integrated Circuit Design, Johns, Martin, page 243. The classic method is Rc1, but because we

know the outpu capacitance the Rc3 is a good choice. I chose just to average these.

Rc1

1

g

m6

:· Rc2

1

g

m6

1

C

gs6

C

L

+

C

c

+

¸

¸

_

,

:· Rc3

1

1.2 g

m1

⋅

:· Rc

Rc1 Rc2 +

2

:·

Rc3 0.613kohm ·

Rc1 3.31kohm ·

Rc2 14.341kohm ·

Rc 8.825 kohm ⋅ ·

Design Requirements

C

L

1pF ≡ GBW 20MHz ≡ Vgt6 0.2V ≡ a 3 ≡ ß 3 ≡ ? 2 ≡ B 1 ≡ Vgt1 0.1V ≡

Summary of circuit values

L

n

Vgt6 F

T

, ( ) 0.824 µm ⋅ · L

p

0.515 µm ⋅ · C

c

0.333 pF ⋅ · I

DS6

31.099 µA ⋅ ·

W

6

29.278 µm ⋅ · W

1

36.276 µm ⋅ · Rc 8.825 kohm ⋅ · Gain_dB 83.962 ·

W

4

14.639 µm ⋅ ·

Ln is the length of

all devices except

M1 and M2

Lp is the length of

M1 and M2

W1 is the width

of M1 and M2 W6 is the width of

M6, M5 and M7.

W4 is the width

of M3 and M4

Simulation

The amplifier is simulated using ADS with BSIM3 parameters available from the BSIM3 website at Berkeley (and

used in the calculations). The current reference is set to 31uA. The output range goes to within 300mV of the

rails.

This is a very good amplifier for this current and such a large output capacitance

The gain from the first stage is simulated 27.6dB, calculated 27.051dB

The gain from the second stage is simulated 36dB, calculated 14.93dB

The gm6 is simulated 0.254mA/V, calculated 0.302mA/V.

I think there is something wrong with the sims!!! Vgain1_dB 27.051 ·

Vgain6_dB 14.93 ·

g

m6

0.302

mA

V

⋅ ·

The unity gain frequency is simulated 100MHz, calculated 20MHz. The top sims are with open loop gain

The plot at the bottom is in unity gain config showing that there is some peaking.

053 ⋅ V Ln( Vgt6. FT ) := µn( Vgt) ⋅ − i( Vgt ) p ⋅ FT 0165 VGSTtn = 0. The EKV model is used here. kb⋅ T q VGSTtn := 2⋅ NFACTORn ⋅ 0138 Vgt VGSTtn +1 i( Vgt) := ln e FT := a ⋅ ß ⋅ ? ⋅ 1 + 1 ß 2 0138 GM ( Vgt) := 1−e − i( Vgt ) 0140 i( Vgt) kb⋅ T q ⋅ i( Vgt) ⋅ 1 − e ⋅ GBW 0627 Ln( Vgt .0 × 10 − 19 ⋅ m V 2 2 VTH0p := 0. µn( Vgt) := 1 + UA n⋅ TOX U0n Vgt + 2⋅ VTH0n Vgt + 2⋅ VTH0n + UBn⋅ TOX 2 µp( Vgt) := 1 + UA p⋅ TOX U0p Vgt + 2⋅ VTH0p + UBp⋅ Vgt + 2⋅ VTH0p TOX 2 µn( Vgt6) = 118.54 cm 2 V⋅ s UA p := 1.2 − 0. The equations for this are from W Liu "Mosfet Models for Spice Simulation". From this we can calculate L (Gate Length) and we use this same L for most of the transistors.U0p := 139 NFACTORp := 1. refer slides: 0138.824 ⋅ µm i( Vgt6) = 14. 0165.2 STEP 3. The gate length needs to be at least twice the minimum.1 0. From U0 and the other BSIM mobility parameters. Assume MOBMOD=1 which is the default. Calculate FT (frequency at which gain equals 1) for transistor M6 to get the gain-bandwidth. as this is what Samson uses. 0140.1 0 Vgt 0.769 ⋅ cm 2 160 V⋅ s µn( Vgt ) 140 2 cm V⋅s This shows how the mobility changes with Vgt for both the NMOS and PMOS It is 50% higher for the NMOS µp( Vgt ) 2 cm V⋅s 120 100 80 − 0.386 FT = 480 ⋅ MHz . page 249.673V VSATp := 103503 m s STEP 2. 0627.399 × 10 −9m V UBp := 1. calculate the mobility for the NMOS and the PMOS devices as this changes with Vgt. FT ) = 0.

Cgs6 := CL a⋅ß Cox := e ox TOX 3 1 W 6 := Cgs6⋅ ⋅ 2 Ln( Vgt6. FT ) ro6 := 1 VA6 + VTH0n + Vgt6 2 STEP 5.133×10 Ln( 0.302 ⋅ mA V IDSt6 = 8. W Liu "Mosfet Models for Spice Simulation". e sat6 := 2⋅ VSATn µn( Vgt6) VA6 := e sat6⋅ Ln( Vgt6. From this we can convert Cc to the equivalent input capacitance from the Miller equation.333×10 6×10 −6 −6 −6 −6 −7 −7 −7 This graph shows how the length of the gate influences the FT (the frequency at which the gain is 1) 2×10 8 3×10 8 4×10 8 5×10 FT 8 6×10 8 7×10 8 8×10 8 1 0. The equivalent Early voltage is VA and this converts to the ro6 by the slope at the point of operation.8 We also get this strange graph that shows how the required gate length changes with Vgt. IDS6 ro5 := ro6 . FT µm ( ) 0. as we are working near VTH0 and ro is reduced. FT ) ⋅ Cox Cc := 0621 0161 IDSt6 := µn( Vgt6) ⋅ Cox⋅ Ln( Vgt6. which are dependent on CL.6 0. FT ) 1×10 8.2V. equations A-62. CL a Use the following equations to calculate the widths and currents of M6 and M5.267×10 1.1 0. FT ) W6 ⋅ ( VGSTtn) 2 IDS6 := IDSt6 ⋅ ln 1 + e ln e ( i( Vgt6) −1 ) 0138 g m6 := GM ( Vgt6) ⋅ IDS6⋅ 2 VGSTtn 0141 g m6 = 0.099 ⋅ µA Cc = 0.667×10 7.199 ⋅ µA IDS6 = 31. A-78. Also a 1/2 adjustment is made for ro. The output impedance is halved as M5 needs to be considered and is assumed to be equal to rout of M6. Ln Vgt .4×10 1.1 0 Vgt 0.2 0 − 0.278 ⋅ µm We need the Early voltage for M6 so that we can calculate the output resistance to get the voltage gain.2 − 0.2 STEP 4.333 ⋅ pF W 6 = 29.4 0.1.

825 ⋅ kohm Design Requirements CL ≡ 1pF GBW ≡ 20MHz Vgt6 ≡ 0.051 STEP 8. Calculate the voltage gain for stage 1 and then calculate the overall voltage gain.93 Vgain6_dB := 10 ⋅ log( Vgain6) STEP 6. Rc1 := 1 g m6 Rc2 := Cgs6 + CL 1 + g m6 Cc 1 Rc3 := 1 1.31 kohm Rc2 = 14.76 according to Analog integrated Circuit Design.359 ⋅ Lp = 0.74.1V .119 Vgain6_dB = 14. Martin. B needs to be high to save current. Now scale M1 and M2. page 243. e sat1 := 2⋅ VSATp µp( Vgt1) ro1 2 VA1 := e sat1⋅ Lp ro1 := 1 VA1 + VTH0p + Vgt1 2 IDS1 2 VA1 = 10. Keep Vgt1 low to minimise noise. but recommend this is kept at 1.2 ⋅ g m1 Rc := Rc1 + Rc2 2 Rc3 = 0.979 ⋅ V Vgain6 = 31.276 ⋅ µm STEP 7.46 × 10 ⋅ ohm 5 Vgain1_dB := 10 ⋅ log( Vgain1) Vgain1_dB = 27. The classic method is Rc1. Calculate the compensation components Rc and Cc. This is calculated to 5. but because we know the outpu capacitance the Rc3 is a good choice. L needs to be greater than twice the process minimum.06 × 10 ⋅ ohm Cn1 = 10.75. 5.Vgain6 := g m6⋅ ro6 2 Cn1 := Cgs6 + ( 1 + Vgain6) ⋅ Cc ro6 = 2. 5.515 ⋅ µm mA V W 1 = 36.055 Vgain1 := g m1⋅ Gain_dB := 20 log( Vgain1⋅ Vgain6) ro1 = 7.341 kohm Rc = 8. Johns.2V a≡3 ß≡3 ? ≡2 B≡1 Vgt1 ≡ 0.818 ⋅ pF 5 VA6 = 11. I chose just to average these. This is halved because both there are two FETS and the gain is halved again as we are working near VTH0 and the output resistance is slightly lower at this point. 063 IDS1 := − g m1 := 2⋅ p ⋅ Cn1⋅ GBW IDS6 2⋅ B GM1 := g m1 IDS1 ⋅ NFACTORp ⋅ kb⋅ T q 0141 i := 1 Given GM1 = 1−e i i := Find( GM1) i kb⋅ T q ⋅ i⋅ 1 − e VGSTtp := 2⋅ NFACTORp ⋅ kb⋅ T q µp( Vgt1) ⋅ Lp := p⋅ FT 4 − i 0165 and 065 for FT IDS1 W 1 := i ⋅ Lp 2 µp( Vgt1) ⋅ Cox⋅ ( VGSTtp) 0138 W 4 := W6 2 ⋅ 1 B g m1 = 1.613 kohm Rc1 = 3.827 ⋅ V Vgain1 = 507. The output resistance is the Early voltage divided by the current.

Summary of circuit values Ln( Vgt6. The output range goes to within 300mV of the rails.825 ⋅ kohm IDS6 = 31. M5 and M7.962 Simulation The amplifier is simulated using ADS with BSIM3 parameters available from the BSIM3 website at Berkeley (and used in the calculations).639 ⋅ µm Ln is the length of all devices except M1 and M2 W6 is the width of M6.515 ⋅ µm W 1 = 36.278 ⋅ µm W 4 = 14. W4 is the width of M3 and M4 Lp is the length of M1 and M2 W1 is the width of M1 and M2 Lp = 0.824 ⋅ µm W 6 = 29.276 ⋅ µm Cc = 0.099 ⋅ µA Gain_dB = 83.333 ⋅ pF Rc = 8. The current reference is set to 31uA. FT ) = 0. This is a very good amplifier for this current and such a large output capacitance .

calculated 27.302 ⋅ mA V . calculated 0.051dB The gain from the second stage is simulated 36dB.The gain from the first stage is simulated 27.254mA/V.6dB.302mA/V.93 g m6 = 0. calculated 14.93dB The gm6 is simulated 0.051 Vgain6_dB = 14. I think there is something wrong with the sims!!! Vgain1_dB = 27.

The top sims are with open loop gain The plot at the bottom is in unity gain config showing that there is some peaking.The unity gain frequency is simulated 100MHz. . calculated 20MHz.

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