Advanced Microprocessors − November 2004

Time : 3 Hrs.] N.B.: (1) Question No.1 is compulsory. (2) Attempt any four questions out of the remaining six questions. (3) Assumptions made should be clearly stated. (4) Assume suitable data wherever required but justify the same. (5) Figures to the right indicate full marks. [Marks : 100

1.

Discuss in detail, the evolution of Pentium processors with regard to the new features added in every model i.e. Pentium – I to Pentium – IV. [20] Explain how virtual memory concept is implemented in P– IV ? (a) Explain the state transition diagram for Pentium processor bus cycle. (b) List the bus cycles run by Pentium processor and explain the burst cycle in detail. [10] [10]

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Explain the concept of pipelining and branch prediction with respect to the latest model of Alpha AXP RISC Microprocessor. [20] Explain the architecture of Super SPARC microprocessor with the help of a neat block diagram. (a) Explain the following instructions with respect to the Alpha AXP Microprocessor : (i) LDWU (iv) CMPULE (ii) S4ADDL (v) UMULH (iii) BEQ (b) Compare the following : (i) PCI and ISA Bus. (ii) USB and Serial Ports. [20] [10]

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(a) A microprocessor has 32 address pins and 64– bit wide data bus. It is to be interfaced with 128 MB ROM and 3 GB RAM. ROM chips are available in size of 16M × 8 and RAM chips are available in size of 128M × 8. Draw the interface diagram and explain the design. [10] (b) Explain the following instructions with respect to Pentium processor : [10] (i) SMI (ii) RDTSC (iii) INIT (iv) WRMSR (v) IRETD. Write short notes on following : (a) Branch Prediction Logic. (b) Line storage algorithm for code cache. (c) VM86 extension for Pentium processor. (d) Model specific register instruction. [5×4]

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Advanced Microprocessors − May 2005
Time : 3 Hrs.] N.B.: (1) Question No.1 is compulsory. (2) Attempt any four out of the remaining six questions. (3) Assumptions made should be clearly stated. (4) Assume suitable data wherever required but justify the same. (5) Figures to the right indicate full marks. [15] [5] [15] [5] [Marks : 100

1. 2. 3.

(a) Explain different stages of integer pipeline and floating point pipeline of pentium processor. (b) Write short note on branch prediction logic. (a) Explain protection mechanism of X86 intel family microprocessor. (b) Write short note on VM86 extension for Pentium Processor.

(a) Draw block diagram of 21064 microprocessor chip (Alpha AXP implementation). Explain the function of each block. [15] (b) Which are the different addressing modes supported by Alpha architecture. [5] Explain the architecture of super SPARC microprocessor with the help of neat block diagram. Explain the following : (a) Virtual Memory Concept. (b) Cache Organization of Pentium (c) Data types supported by SPARC architecture (d) Register file of SPARC architecture. (a) Write features of Pentium IV. (b) Explain the concept of physical memory interface with Pentium processor. Write short note on any four : (a) USB (b) AGP (c) SCSI interface (d) PCMCIA Cards and Slots (e) EISA [20] [20]

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[10] [10] [20]

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University Question Papers

Advanced Microprocessors − December 2005
Time : 3 Hrs.] N.B.: (1) Q. Nos. 1 is compulsory. (2) Attempt any four questions from remaining. [10] [10] [10] [10] [12] [8] [10] [10] [10] [10] [20] [Marks : 100

1. 2. 3. 4. 5. 6.

(a) Explain how the flushing of pipeline problem is minimized in Pentium Arch. (b) Differentiated between real mode and protected mode of X86 family. (a) Explain Architecture of Alpha AXP machine. (b) Explain the architecture of super SPARC. (a) Explain architecture of Pentium. (b) Explain control registers of X86 family. (a) Discuss phases of SCSI. (b) Explain PCI bus. (a) Explain cache organization of Pentium. (b) Explain ISA Timers types. Write short note on any four: (a) IDE (d) EISA (b) VESA (e) USB. (c) AGP

Advanced Microprocessors − May 2006
Time : 3 Hrs.] N.B.: (1) Q. Nos. 1 is compulsory. (2) Attempt any four questions from remaining six. (3) Assume suitable data wherever required, but justify the same. [Marks : 100

1.

(a) Draw block schematic of Pentium processor and explain its operation in brief. [10] (b) State integer pipeline stages of pentium processor and explain functionality of each stage in brief. List steps followed by pentium in "Instruction Issue Algorithm" for superscalar execution. [10] (a) Draw protected mode address translation mechanism in X86 processor with neat flow diagram. Explain segment translation in detail. List and explain fields of Non−system segment descriptor. [12] (b) Explain the concept of "Dynamic Branch Prediction Logic" in Pentium. [8] (a) List the features of Pentium−4 processor. Explain Intel's Net Burst Micro architecture with neat schematic. Also highlight on hyper−pipeline concept and rapid execution engine. [12] (b) State the features of PCI bus. Draw a typical PCI bus workstation and explain it in brief. [8] (a) Explain control registers with functionality of each bit in pentium processor register model. [10] (b) State features of SCSI bus and discuss layered architecture of SCSI protocol. Differentiate between single ended and differential ended SCSI. [10] (a) State the versions of 80386 processor. Draw block diagram of 80386DX processor and explain each block. [10] (b) Draw and explain Super−SPARC processor architecture. [10] (a) Draw block diagram of DEC Alpha AXP processor 21064 and explain function of each block. [10] (b) List the features of each ISA bus version namely 8 bit, 16 bit and 32 bit EISA. Compare bus bandwidth of EISA to that of MCA bus. [10] Write short notes on the following : (a) Basic SPARC architecture register model (b) V−86 mode of operation (c) Addressing modes of DEC Alpha processors [7] [7] [6]

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Advanced Microprocessors − November 2006
Time : 3 Hrs.] N.B.: 1. (a) (b) (c) (d) (1) Question No.1 is compulsory. (2) Attempt any four questions out of the remaining six questions. Enlist the ‘instruction pairing’ rules for U and V pipeline in Pentium. Explain how the flushing of pipeline problem is minimized in Pentium Architecture. With a neat diagram, explain different stages of Floating point pipeline of Pentium? List the steps of “Instruction Issue Algorithm” in Pentium.
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[Marks : 100

[5] [5] [5] [5]

Vidyalankar : BE − MP

2.

(a) Draw and explain super−SPARC architecture. (b) Explain with a neat block diagram, the architecture of a typical Alpha AXP Processor. (a) (b) (c) (d) What are the different addressing modes supported by ALPH architecture. Data types supported by SPARC architecture. Register file of SPARC architecture. Split−Line access with respect to Code Cache of Pentium.

[10] [10] [5] [5] [5] [5] [20] [10] [10]

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4. 5.

Explain with a neat diagram the internal Cache organization of Data Cache and Code Cache Of Pentium. (a) State the features of PCI Bus. Draw a typical PCI Bus work station and explain it in brief. (b) List the features of each ISA bus version namely 8 bit, 16 bit and 32 bit EISA.

6.

State features of SCSI bus and discuss layered architecture of SCSI protocol. Differentiate between single ended and differential ended SCSI. Discuss the different phases of SCSI. [20]

Advanced Microprocessors − May 2007
Time : 3 Hrs.] N.B.: (1) Question Nos. 1 is compulsory. (2) Attempt any four questions out of remaining six questions. [Marks : 100

1.

(a) Show the register model of X86 processor and explain all control registers and memory management registers in detail. [12] (b) State and explain operating modes of X86 family of processors. Show mode transition diagram highlighting important features. [8] List important features of Pentium−2 processor. Differentiate between Pentium−2 xeon and Celeron versions. Draw a typical Pentium−2 xeon system and explain. Show memory map of Pentium−2 system and discuss the same. [20] (a) Explain in brief integer instruction pipeline stages of Pentium processor. List the steps in instruction issue algorithm. [10] (b) List SCSI bus features. Explain SCSI bus phases with diagram. [10] (a) State the features of PCI bus. Draw a typical PCI workstation and explain in brief. (b) Draw and explain Super−SPARC processor architecture. [10] [10]

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(a) Explain the state transition diagram for Pentium processor bus cycles. [10] (b) Explain segment translation mechanism in detail for X86 processors. List and explain various fields of non−system segment descriptor. [10] (a) Draw block diagram of DEC Alpha AXP processor 21064 and explain function of each block. (b) Draw block diagram of 80186 processor and explain. Write short notes on delete : (a) ISA bus versions and bandwidth (b) PCMCIA cards and slots (c) Intel’s Net burst microarchitecture (d) Branch prediction logic [10] [10] [20]

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Advanced Microprocessors − November 2007
Time : 3 Hrs.] N.B.: (1) Question No.1 is compulsory. (2) Attempt any four questions out of remaining six questions. [Marks : 100

1.

(a) Differentiate segmentation in real mode and in protected mode. [5] (b) State the role of I/O permission bitmap in protection of X86 processor. Also explain the function of IOPL bits. [5] (c) In sun SPARC processor, explain the function of the registers : processor state register, window Invalid Mask register, PC and nPC, Ancillary state register. [5] (d) Explain Debug registers of X86 processor. [5]

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University Question Papers

2.

(a) State the features of Intel Itanium processor. Draw the block diagram of Itanium processor and explain in brief. [10] (b) State the features of PCI bus. Draw a work station based on PCI bus and explain. [10] (a) Draw and explain Pentium Processor architecture. Highlight architectural features. (b) Explain the following Pentium−II instructions : CPUID, SYSENTER, SYSEXIT, FXSAVE, FXRSTOR. [10] [10]

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(a) Show steps in segment translation of X86 processor. Explain various segment descriptor bits/fields in detail. [10] (b) Compare X86 processors (8086 to Pentium) with respect to the points : [10] size of processor, CK frequency of operation, No. of transistors on semi-conductor die, size of physical memory, size of prefetch queue, performance in MIPS, size of L1 cache. (a) State the features of SCSI interface. Compare single ended and differential SCSI. Explain in brief SCSI bus phases. [12] (b) Explain EFLAG bits of pentium. [8] (a) Explain with block diagram, architecture of 80286 microprocessor. (b) Draw and explain DEC Alpha AXP processor architecture − 21064. Write short notes : (a) Type and limit checking aspects of segment level protection (b) Instruction formats of sun SPARC (c) CALL gate mechanism (d) V − 86 mode of X86 processor. [10] [10] [20]

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Advanced Microprocessors − May 2008
Time : 3 Hrs.] N.B.: (1) (2) (3) (4) Question No. 1 is compulsory. Attempt any four questions out of remaining six questions. Draw neat sketches wherever required. All questions carry equal marks. [Marks : 100

1.

(a) Compare 386 SX and 386 DX processors. Draw block diagram of 386 DX processor. [5] (b) Compare single ended and differential ended SCSI. [5] (c) State the use of following X86 flags : [5] RF, VM, ID, NT, IOPL. (d) Compare 8-bit ISA with 16-bit ISA with respect to the base processor used, address bus, data bus length, transfer rate and on board peripherals. [5] (a) Explain segment translation mechanism of X86 processor with flowchart. Also explain segment descriptor fields. [10] (b) State PCI bus features. Draw a typical PCI bus workstation and explain. [10] (a) Explain layered architecture and bus phases of SCSI bus. [10] (b) State features of super SPARC. Draw block diagram of super SPARC and explain it with respect to Cache, ALU's, FPU and external interface. [10] (a) State and explain the functionality of X86 system address registers. [10] (b) Explain Itanium processor with respect to instruction format, core pipeline stages and the functionality.[10] (a) Draw block diagram of Pentium processor and explain its superscalar operation. [10] (b) Draw the Willamette pipeline of pentium-4 processor. Compare Pentium-3 and Pentium-4 w.r.t. CK frequency, processor technology, no. of transistors, MIPS and multiprocessor support. [10] (a) Explain Alpha AXP instruction formats. (b) Explain in details Pentium processor instruction issue algorithm. Write short notes on : (a) FP pipe line stages of Pentium. (b) CALL gate mechanism. (c) Ultra SPARC processor. (d) COM port Vs. USB port. [10] [10] [20]

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