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The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON) Nov.

5-8, 2007, Taipei, Taiwan

A Fast PLL Method for Power Electronic Systems Connected to Distorted Grids
Mu WEI1,2

Zhe CHEN'

IInstitute of Energy Technology, Aalborg University, Aalborg, Denmark 2Faculty of Electronics and Information Engineering, Southwest University, Chongqing, P.R. China
mwegiet.aau.dk, zchgiet.aau.dk
Abstract- A phase-locked loop (PLL) for power electronic systems is presented in this paper. The PLL system can fast detect the voltage magnitudes, phase angles and frequency under distorted power system conditions. A series of simulation studies have been conducted. The results are presented and compared with some other PLL systems.

have been conducted. The performances of the proposed PLL have been investigated and compared with the SRF-PLL and the software based PLL systems. II. SYNCHRONOUS REFERENCE FRAME (SRF)-PLL The synchronous d-q reference frame PLL is a simple and stable three-phase PLL system which detects the phase angle in the synchronous d-q reference frame, the reference frame is synchronized to the input voltage frequency [1]. A block diagram of SRF-PLL is shown in Fig. 1.

I. INTRODUCTION

In ac power systems, the phase, amplitude and frequency of the grid voltage are very important information for gridconnected operation. Especially for power electronic converters which are more and more used as the interface for distributed generation (DG) units, the information of grid voltage is essential for operation and control of the power electronic converters and the interfaced DG units. With the increase of the DG units and the renewable energy generation units, such as wind and solar energy conversion system, the accurate grid voltage information becomes crucial for system security and quality power supply. Therefore the phase-locked loop (PLL) can be considered to be an important part of grid-connected power generation systems. The PLL technique has been used as a common way of obtaining the phase and frequency information in electrical systems. For power electronic applications, the PLL technique has been adopted for the speed control of electric motors. It has also been used for generating the reference signals synchronized with the utility voltages in power conversion systems. A simple method of obtaining the phase information is the zero-crossing method, which detects the zero crossing points of the utility ac voltages. However, the zero crossing points can only be detected at every half-cycle of the ac frequency, the phase tracking becomes impossible between the detecting points, consequently, the fast tracking performance cannot be achieved. In three-phase systems, the dq transform of the three-phase variables has the quadrature feature, as the "synchronous d-q frame reference" SRF PLL [1], which can be used in various applications for the detection of the phase or angular position. But the waveforms of the grid voltage may be the distorted with harmonics and unbalanced voltages, which could seriously affect the accuracy of the obtained grid voltage information. This paper firstly briefs the principle of the SRF-PLL, discusses the concept used for extracting fundamental positive sequence component [2] and the Software based PLL [3]. Then the proposed PLL is introduced. The simulation studies

V~

Vb~

Fig. 1 Basic structure of SRF-PLL

|M|

s
S

*0

iff

-f

The closed loop transfer function of this system can be represented as a generalized second order system in (1):
Hclose(S) =

s2 + 2 s+w 2

2Gw(n s + tq9n

(1)

the PI controller, and Em is the magnitude of the input signal. Depending on the pre-conditioning applied on the signals, the signal entering the system may be normalised or nonnormalised. If the normalised PLL system is adopted by using the output of M , then the Em for the parameters of PI controller may be taken as unity. Consequently, the PI controller parameters may not be affected by the variations of input utility voltage value. However, the measured waveform may be unbalanced with negative and zero sequence components, the harmonics and distortions could deteriorate the performance of the simple SRF PLL system. Thus the conventional methods are not sufficient to cope with various distortions of the measured

E =l/K Where, K = 2 /o) ,K=o2 Em, Ti= and Kp is the proportional gain and Ki is the integral gain of

voltage signals.

1-4244-0783-4/07/$20.00 C 2007 IEEE

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III. FUNDAMENTAL POSITIVE SEQUENCE COMPONENT EXTRACTION FOR PLL SYSTEMS Due to the poor performance of SRF-PLL under unbalanced or distorted conditions, various PLL systems have been proposed to overcome the problem [2-5]. A basic concept is to extract the fundamental positive sequence component by processing the signal, and then to obtain the angle and frequency of the fundamental positive sequence component for the operation and control of power conversion systems. The unbalanced three phase voltage may be expressed as (2) cos(cd+- +)
cos( T +

basic structure of the software based PLL is shown in Fig. 2. In this PLL system, the three phase input voltage signals are converted to o-P system. The o-P components can also be expressed as their positive and negative components as
Va
=
=

Vpa
Vpm

Vna cos(O + Op )

+ Vnm

cos(O + On)

(4)

V8= V pP/i Vn6 p8+ ni = pm sin(O +OSP)

Vnm *sin(O +OSn)

cos()

Differentiating Eqn. (4) with respect to 0, to obtain


d

Va
v

Vpi + Vn/

(5)

2~~~~~~~~~~2

Vpa

V,a

and v0 r denote the magnitudes of the positive, negative and zero sequence terms respectively. The positive sequence component is extracted as an input of the PLL system to eliminate the effects of unbalanced and harmonics. Reference [2] presented a d-q synchronous PLL system which produces phase angle and frequency locked to positive sequence components. The three positive sequence components ( ve, ,avn, are related to three phase voltages z) Where vprn
V ) va (vbby
a a

~vnrn

By using (5) the positive sequence components in o-P frame can be calculated as shown in (6), where the derivative terms are calculated with numerical methods which is the main task of the first stage in the reported software based PLL [2].
vp
v Pf
=

0.5 (va

dS
d

v,

(6)

O.5 (v,

d0

V~a)

V
-

avp

2
a
a
2

2J

Lv
)

- v - a _

2
1

a21i31
A/

(Vb-C vc (b

(3)

The second stage transforms the o-P components of the positive sequence to the rotating synchronous frame. The quadrature axis component is then regulated by a PI controller. The second stage tracks the phase angles and angular velocities ofthe positive and negative sequence components. The third stage is essentially a lead-lag compensator with good filtering properties. In this stage, the parameter o- At is calculated, filtered and fed back to the first stage.

(Vap +vcp )
-

2 C

2V

.r (j(VaVb)
a

aq_a

oc-+vcdv- ,O

..
Vpg

Ic-

v13-_dv1

2fT

Where,a=

It can be seen that a phase shift of 90 degree is required for all three phase components to extract the positive phase sequence components. In reference [2], three all-pass filters are respectively applied on three phase voltage signals to perform 90 degree phase shift. Then a second-order low-pass filter is added to reduce the effects of high-order harmonics. The extracted positive sequence components are then fed into a SRF PLL which produces the phase angle locked to the positive sequence component. IV. SOFTWARE BASED PLL
In reference [3], a software based PLL is proposed. The

or a

e 3

AU~~

~~~~~1 AO

,
P

UA

Lead-Lag
Compnao

=k-_
S A9

Th71e thEk tagge


Fig.2 Basic structure of Software based PLL

Such a system can provide fast response to follow the system frequency variations and voltage magnitude variations. However, the derivative calculation could be sensitive to certain types of waveform distortions, such as harmonics. In the following section, a PLL with the improving ability of working under distortion condition is proposed.

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Bode Diagram

V.

TUE PROPOSED FAST PHASE DETECTING METHOD

Basic structure of the proposed fast phase detecting method The basic structure of the proposed fast phase detecting method is shown in Fig. 3, where two band pass filters are used as the conditioning part for the input signal in o-P frame. Also a phase locked loop for negative sequence component is established in the voltage detection system.
AS
V

Fa

Vb

b-D _ .

aL( Badps te. 7Fl r ps Filte

pa

sv1 -_dv13

.B o

.1P# VIa
nV
Frequency (rad/sec)

Fig.4 Band pass filter characteristics

Negative phase angle calculation The information about the negative phase component may be used for control or power quality identification. Based on equations (5) and (6), the negative phase component can be calculated as C
d

Vn

.5(v,,

v,

(8)

Vn#

- 0.5

(V0

Va )

AI
Fig. 3 Structure ofthe proposed PLL

o-P frame can be found, then they can be converted into the d-q frame in a similar way to the positive sequence component. The negative phase sequence angle and magnitude can be obtained with the PLL as shown in Fig. 3.
components in

Therefore, with the phase shifted components, the negative

Band pass filter


The

transfer
PLL

function of

the

band-pass
as

filters used in the

VI.

SIMULATION STUDY

proposed

system may be expressed

G (-)
Y(s)
=

I + 2

co ( s + ()
)c

(7)
)c

)2

Where ; is the damping ratio, 0) is the characteristic frequency and G is the gain. In this study, the band pass filter is such designed,; is 0.5, ()O is 314.159 radians /s (50 Hz) and G is 1.0. The frequency characteristics of the filter are plotted in Fig. 4. It can be seen that the filter can effectively attenuate signals at frequencies other than the characteristic frequency where the signal has no phase shift.

Simulation studies have been performed to investigate the performance of the proposed PLL system. In this section, the simulation conditions and results are presented. A Description of the test conditions Two tests are reported in this paper. Assuming the normal positive sequence component voltage has a phase peak value of 1000 V, and the utility voltage has balanced harmonics which can be formulated as follows:
Va

=vl cos0+v5 cos50+v7 cos70+ *+v25 cos250


2

Vb =V COS(- fZ)+V5 COo5(0


3
2

-z)+v7 cos7O+.. +v25cos25(0--Z)


3 3 2 2 2

V, =VI COS(O+- z)+V5 cos5(0+-zr)+v7 cos7(0+-zr)+. +v25 cos25(0+-z) 3 3 3 3


(9)

The used harmonics components are as specified in EN50160 and scaled down to 8% THD. The harmonics last for the whole simulation period and their magnitudes have the same dip in the percentage of the positive sequence

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components in Test 1. The other used test conditions are given in Table 1. The test waveforms are illustrated in Fig. 5(a)-(d). Fig. 5 (a) shows a part of the three phase test voltage signals in Test 1, Fig.5 (b)-(d) show three parts of the test signals in Test 2 respectively, i.e. the first frequency rampingdown part, the frequency ramping-up part, and the second frequency ramping-down part. The output frequency is observed after a 2nd order low pass filter with damping ratio of 0.707and characteristic frequency of 10lHz. B SRF-PLL performance Fig. 6 shows the tracked angle and the angle error of the SRF-PLL under Test 1. It can be seen that the angle error increases dramatically to approximate 50 degrees during the period when the negative sequence components emerge.
Table 1 Some test conditions Conditions The positive sequence component voltage dip from 100% to Test 1 15% for 0.3s, during the same period, 15%, negative __________ |sequence component present with a 30 degrees phase shift The frequency ramps down from 50.0Hz to 47.5Hz within 0.25s, maintains at 47.5Hz for 0.3s, then it ramps up from Test 2 47.5Hz to 51.5Hz within 0.4s, maintains at 51.5Hz for 0.2s, |________ |and then ramps down from 51.5Hz to 50.0Hz within 0.15s
Test

frequency ramps well. Particularly the steady state frequency error can be kept within 0.01o%.
1500

The First Test Condition

100 0

..

..

-100 0

.............m

-1500.

Fig.5(a) A part of the three phase test voltage signals in Test 1.

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

O.Y -. .7

150 i
-1000 {iIlill

The Second Test Condition

Fig.7 shows the voltage magnitude output of the SRF-PLL. The envelope of the magnitude curve reflects the signal magnitude; however it is combined with harmonics. Fig.8 shows the SRF-PLL test results under the second test condition. The frequency output follows the reference frequency ramps very well; the frequency error is in a range of about 0.0050. The negative sequence component can not be detected with SRF-PLL. C Software based PLL performance The results from the Software based PLL are presented in Figs.9-12. Fig.9 shows the tracked positive sequence angle and angle error under Test 1. In the steady state the angle error is in the range of-0.5 to 2 degrees in steady state. Fig. 10 shows the tracked negative sequence angle and angle error under Test 1. It can be seen that the angle error is no more than 2 degrees. Fig. 11 shows the positive and negative sequence components magnitudes respectively. Compared with the reference magnitudes (in green), the voltage magnitude outputs of the software based PLL are always affected by harmonics. In particular the negative magnitude is influenced seriously by the harmonics. Fig. 12 shows that the frequency output can follow the reference frequency ramps in Test 2 and the frequency error is in a range of about 0.015o%. D The performance of the proposed PLL Figs. 13-17 show the results of the proposed PLL. Under the Test 1 condition, the tracked positive sequence angle and the angle error are shown in Fig. 13. In steady state the angle error is in a range of -0.1 to 0.2 degrees. Fig. 14 presents the negative sequence angle which have been tracked very well, and the steady state angle error is no more than 0.5 degrees. In Test 2, the frequency output can follow the reference

,5

Fig.5(b) The first frequency ramping-down part in Test 2


The Second Test Condition
15001

0. 25

0.3

0-35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.775

1000|

Soo

-1000

-15001

Fig.5(c) The frequency ramping-up part in Test 2


15001

0.8

0.9

1.1

1.2

1.3

1.4

The Second Test Condition

0.

.1

-1500

----

Fig.5(d) The second frequency ramping-down part in Test 2

1.4

1.45

1.5

1.55

1.6

1.65

1 .7

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Locked Angle, SRF and Ref(rad.)

Negative Angle,

SoftwareBased and

Ref(rad.)

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

-5 0.2

0.3

0.4

0.5

0.6

0.7

0.8

Angle error, Ref-SRF(deg.)


40 20
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65

< -20

Fig. 10 Negative angle and angle error ofSoftware based PLL under Test 1
I_1 nn z 1500

-40 -60 0.2

Positive Magnitude, Software based and Ref

Fig.6 Angle and angle error of SRF-PLL under Test


-Vagstue SF adFe

0.3

0.4

0.5

0.6

0.7
1

0.8
1000

.M

u0

0.3

0.4

0.5

0.6

0.7

o. .8

Negative Magnitude, Software based and Ref

Fig.7 Magnitude of SRF-PLL unde~rTest 1


55

400
200 U
0

Frequency, SRF and Ref

02...

Fig. 11 Positive and Negative magnitude of software based PLL in Test 1


SS .,

0.2

0.3

04 03II
0.4

07 05 08

0.5

0.6

0.7

0.8

Frequency, SoftwareBased and Ref

v 50

45

I550 v0.4 0.6 0.8 1.2 1.4 1.6 1.8


4D5
._

0.01 0.005 _

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-0.005 -0.01

Fig.8 Frequency and frequency

0.4

0.6

0.8

error

of SRF-PLL under test 2


Ref(rad.)

1.2

1.4

1.6

1.8

Locked Angle, SoftwareBased and

Fig. 12 Frequency and frequency error ofSoftware based PLL under Test 2
5

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Locked Angle, Improved and Ref(rad.)

-50.2 0
21.

0.3

0.4

0.5

0.6

0.7

0.8
-5
0.2 0.3 0.4 0.5 0.6 0.7

0 .8

Angle error, Ref-SoftwareBased(deg.) Angle error, Ref-Improved(deg.)


023

01~~~~~~~~~~~~~~~~~11

Fig.9 Positive angle and angle error of Software based PLL under Test 1

-1.50 0.2

0.3

0.4

0.5

0.6

0.7

0.8

Fig. 13 Positive angle and angle error ofthe proposed PLL under Test

0.2

0.3

0.4

0.5

0.6

0.7

0.).8

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Negative Angle, Improved

and

Ref(rad.)

0.3

0.35

0.4

0.45

0.5

0.55

0.6

L 0.65

0.7

Fig. 14 Negative angle and angle error ofthe proposed PLL under Test 1
Positive Magnitude, Improved and Ref
1000

77-

VII. CONCLUSION A fast PLL has been proposed, where a band-pass filter is designed to make the system immune to distorted waveforms, such as harmonic distortions. Therefore the system performance can be significantly improved without sacrificing the responding speed. Simulations under various conditions have been conducted, including system voltage dips and frequency variations under distorted conditions. The comparisons with the synchronous reference frame (SRF)-PLL and the software based PLL has been made. The proposed PLL has demonstrated significant improvements. The proposed PLL system can be used for the power electronic interfaces of renewable energy and energy storage technologies, including wind energy conversion systems and solar PV systems, etc.
REFERENCES

>

600
400
200

O_
0.2

0.3

0.4

0.5

0.6

0.7

0.8

250 200
150

Negative Magnitude, Improved and Ref

[1]. S.-K. Chung "Phase-locked loop for grid-connected three-phase power conversion systems", IEE Proceedings-Electric Power Applications, Volume 147, Issue 3, May 2000 Page(s):213-219. [2]. Sang-Joon Lee; Jun-Koo Kang; Seung-Ki Sul; A new phase detecting method for power conversion systems considering Conference, 1999. Thirty-Fourth IAS Annual Meeting. Conference Record of the 1999 IEEE, Volume 4, 3-7 Oct. 1999 Page(s):2167 2172 vol.4. [3]. S.R. Naidu, A.W Mascarenhas,.; D. A. Fernandes, "A software phase locked loop for unbalanced and distorted utility conditions"; International Conference on Power System Technology, PowerCon 2004. Vol. 2, pp 999 -1004. [4]. M. Karimi-Ghartemani, M.R. Iravani, "A method for synchronization of power electronic converters in polluted and variable-frequency environments", IEEE Transactions on Power Systems, Volume 19, Issue 3, Aug. 2004 Page(s): 1263 - 1270. [5]. P. Rodriguez, R. Teodorescu, I. Candela, A. Timbus, M. Liserre, F. Blaabjerg, "New Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under Faulty Grid Conditions", in Proc. IEEE Power Electronics Specialists 37th Conference on, pp. 1942-1948, June 18-22, 2006.
distorted conditions in power system, Industry Applications

100 _
50 1,.

Fig. 15 Positivle and Negative magnitude of proposed PLL under T est I


55-

0.2

03

0*4

0*5

0*6

0.7

0'8

Frequency, Improved and Ref

50-

45

0.4

0.6

0.8

1.2

1.4

1.6

1.8

0.01 r

0.005
0

00

-0.005

.01

Fig. 16 Frequency and frequency error ofthe proposed PLL under Test 2

04

0.6

0.8

1.2

1.4

1.6

1.8

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