DFT Embedded Memory



Sangmin, Sangmin Bae DFX Group IDC, System LSI, Samsung Electronics Co, Ltd Co Samsung Property

Contents » Introduction • Environments and Scopes » Technical Items • Integration complexity • MBIST design consideration • Design flow consideration • Repair and ECC » More Technical Items » Summary Samsung Property 2 .

• • • Design capacity : Mega SOC. analysis » Well tuned DFx technique • Typically. near NoC product » Hierarchical. Debug.Introduction » Status on eMemory Testing • Driver » Complex advanced design flow with limited TAT Complex. test escape reduction Bit-cell engineering requires efficient channel for si. etc. modular design flow Advanced lo po e Ad anced low-power design techniq e technique Design reuse : Heterogeneous IP integration » R id process migration i Rapid i i into nano-technology h l • • • Performance gain and yield goal is more challenging than before Reliability. Reliability. DFT resources are re-purposed for DFx » Productivity. Samsung Property 3 .

g » Not easy to maintain current through-put within the previous DFT resource (test cost. but most of eMemory design and test issues are tightly coupled with DFT logic ( g (MBIST). re-visiting of MBIST is still occurred ) . So. memory is not fully controllable and we have fewer knobs than logic dft (scan) technique technique. H/W area) cost • Providing flexible MBIST automation tool is not sufficient • SiP.Introduction » Scope and limitation on eMemory Testing • Typically. TSV testing is still challenging area in the real action » Evolution of existing technique is not sufficient Samsung Property 4 . • Memory BIST y » MBIST is classical and well-defined technique.

Integration Complexity » Difficulty on SRAM Tests • • • • • • Layout is more crucial compare with logic std. has very strong relationship : y g p » Trade-off exists between area. yield Bit-cell array and peri. circuit is controlled by self-timed logic SRAM configuration widely varies on their usages Most SRAM are deeply embedded in a chip MBIST just do functional test on SRAMs Samsung Property Row-Decoder o Column mux + Sense Amp 5 . cell Each 6 tr. performance.

SNM DNM + peri.Integration Complexity » Who is DFT player? • Example : test lvcc problem Vector and screening condition Test eng’r IP or package eng’r SoC DFT design’r FE/BE eng r eng’r IO + package spec. full-chip full chip level DFT planning power-clock network Design methodology + Sign-off rules MBIST eng’r SRAM core 6T bit-cell w/ SNM. design w/ self-timing margin Process eng r eng’r SRAM designer Samsung Property 6 .

1 0 A Type B Type C Type Samsung Property 7 . MBIST is implemented on ASIC flow » Test is based on functional test » Without memory changes.Integration Complexity » Memory BIST Limitation • • Typically. mem. Port A Port B 0 1 1 0 0 1 mem. very difficult to obtain useful knobs on test Example : Controlling clock skew between multi-port memories » Each type could requires extra implementation overhead • Sacrifice parallelism for area reduction • Poor resolution • Pattern development difficulties p p / p » ROI perspective : Trade-off b/w implementation efforts and TAT BIST A BIST B BIST BIST direct control clock mem.

RTL insertion • Hierarchical test-bus • mbist Block A IP i/f mbist mbist mbist Block C mbist IP i/f Block B Big hard-macro IP inc. » Programmability control » Redundancy information handling SoC JTAG IP i/f mbist Top controller w/ repair function block IP i/f mbist mbist mbist » Solution approaches JTAG + IEEE1500 interface with tricky interface blocks • MBIST insertion variation » GL vs. memories Typical SoC MBIST Architecture Samsung Property 8 .Integration Complexity » MBIST complexity • Increased memory counts » Hierarchical/multi-step generation and insertion capacity » Redundancy strategy • Multiple power-domain and various power-gating scheme » Repair-information distribution » T Test condition control i multiple voltage l di i l in li l l level l • Light-weight clock-domain crossing control is required » JTAG is just simple std.

Memory BIST Design » Memory BIST Design • MBIST using HDL based ASIC flow » Common features : • Programmable. at-speed fail-bit map • High-speed option : PLL. and scan mode isolation scheme » Seamless automation flow requires continuous efforts • Hard to be properly hidden during implementation flow » Timing closure. FSM design • MBIST generator : easily adapted and deployed in industry » Script or GUI based input form : memory and MBIST lib. Verification closure STA Samsung Property • 9 . format » Based on configurable and parameterized template ased o co gu ab e a d pa a e e ed e p a e » IDE fasten DK iteration : planning. STA. data-path pipelining. verification Several consideration : mainly automation and flow issues » Customization can not be avoidable • Different DFT budgets and targets by different customer • Clock scheme. insertion.

Design Flow Consideration » RTL vs. loose standards RTL Logic. GL MBIST Flow • TAT is a main driving factor : IP and tools status • Selection could different depends on design-flow and tool-chain • It mainly depends on other constraints.synthesis Scan Synthesis Boundary Scan Simple Concept design planning Top-level integration l l IP integration ECO & verification Timing closure flow automation EDA tool integration Complex Execution Samsung Property 10 . not by MBIST » HDL interface capability is mandatory » No leading/full standards exists g/ • JTAG + IEEE1500 style is very popular but.

detected by design verification review and work around work-around can be exists » Test escape • • • Re producing Re-producing fail on DFT@ATE test is technical goal Main barrier : lacks of fail modeling and MBIST flexibilities Diagnosis time is most important Samsung Property 11 . diagnosis motivation » Low yield. Diagnosis • eMemory Si. • Several approaches pp » » » » Initial statistical analysis Extract exact fail bit-map Parametric analysis using memory operation mode MBIST logic fails • Typically. etc.Si. poor device characteristics. Diagnosis of SRAM » eMemory Si. test escape.

repair analysis Si. pattern • Pattern level programmability seems to be not sufficient » ALPG ( i i memory ATE) approaches i popular (mini. KGD(SiP. diagnosis.Programmable MBIST » Programmable MBIST • Flexibility depends on structures » FSM-based FSM based » ALPG like (micro-code based) » Extension of general micro-controller ISA w/ custom module • Needs of programmable MBIST » Control of complex memory IP : eDRAM. h is l » Pattern development costs » Well defined flexible ISA • ATE or on-chip control interface is one of issues » JTAG or AMBA-bus based » Vector and simulation flow is required Samsung Property 12 . TSV) » Si diagnosis repair analysis : diagnostic pattern.

5D Redundancy (Row + Column) * M 2N * M Complex Samsung Property 13 . BIRA Single (Row / Column / IO) N Simple 2D Redundancy Row + Column 2N Medium 2. Type # of Red. Redundancy Redundancy 1D Redundancy Red.Repair and ECC » General Memory Redundancy Scheme 1D Redundancy 2D (Row/Column) Redundancy Hier.

.Repair and ECC » Typical MBIST structure on SOC • Top DFT controller inc. SRAM SRAM Serial or Parallel Bus Repair Address Repair Address General MBIST Structure Samsung Property 14 .. JTAG interface • Local Memory BISTs • Fuse related logic for repair » Features on MBIST design • Memory isolation and clocking scheme • Interface between Top DFT controller and Local BIST logics • Repair policy and repair-bus structure repair bus JTAG IEEE 1500 or custom control Wrapper Wrapper Wrapper JTAG Top DFT Controller Repair Analysis BIST Fuse Related Controller SRAM .

SRAM ECC regarded as having big-overhead technique » Area. SEC-SED • Architectural approaches are trends for eMemory ECC » Combined with redundancy and other design constraints/techniques Samsung Property 15 .Repair and ECC » ECC • Typically. timing overhead » Increase complexities of test condition and repair flow • Popular ECC code : SEC-DED.

Memory Interconnection Samsung Property 16 . implementation TAT intrusive • W ll d fi d and fi d Well-defined d find-grain t t b i test-bus protocol will catch both performance t l ill t h b th f and DFT productivity goals • Current MBIST solution is not suitable for this kind of approaches • Early stage of its adaption on several IPs Pre-designed Re-configurable IP Re epairBu us repair interconnection Serial F/F Memory Instance Me emory Ins stance Me emory Ins stance Configurable BIST or BIRA w/o Memory Memory Te est-Bus Memory Instance Memory Instance F/F normal memory bus Memory Instance e Memory Instance normal memory bus normal memory bus F/F F/F BIST vs.Memory Test Bus » Memory Test Bus Motivation i i • Traditional memory isolation and MBIST insertion are can be performance.

pattern. spec. how to merge/split MBIST(s)? • Trades-off is exists (accuracy or q&d solution) ( y q ) » Approaches Candidates • Memory BIST grouping/scheduling automation • » Both.MBIST Planning and Test Scheduling » Backgrounds For multiple MBISTs in a chip. and run-time level required . peak power based Clock skew and timing dependency P&R floor-planning back-annotation Memory operations Peak Power Run #1 Run #2 Run u #3 Run #4 Capacities » MILP or graph-based solver » Graph-based : bin-packing problem Graph based bin packing Test Time Samsung Property 17 . p q » Should consider BIST generation. repair • Run-time scheduling flow should reflect other constraints » ATE interface overhead » Diagnosis » Flow Considerations • Accuracies » » » » • Average vs.

Hot-carrier.More Technical Items » Several topics on eMemory DFT • Bit-cell related » Reliability and manufacturability issues • NBTI. SiP memory test support • • Samsung Property 18 . TDDB Memory related » Multi port memory related Multi-port » Parametric diagnosis structure » Memory test-assist function support g g / » Design-assist function using BIST/BIRA resource BIST-BIRA related » BISR(self-repair) • Repair analysis algorithm • fuse-compress and repair-bus structure » BIST/BIRA planning and scheduling • Shared BIST or hierarchical BIST architecture • BIST/BIRA planning w/ design constraints » TSV.

TSV • Latest full-chip DFT architecture compliance Samsung Property 19 .Summary » DFT for Memories • Memory BIST for eSRAM » On-product diagnostic features in mass volume On product » Fluent and flexible design flow • Memory BIST for SiP. TSV » KGD test is still challenging on real execution • Memory BIST for DFx » Basic infra structure for eSRAM DFT » Technical requirements on current MBIST • Well-designed memory test-bus g y • Matured programmable MBIST for SiP.

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