Carpinelli Solutions | Instruction Set | All Rights Reserved

SOLUTIONS MANUAL

Computer Systems Organization
and Architecture
John D. Carpinelli
Copyright © 2001, Addison Wesley Longman - All Rights Reserved
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page ii
Table of Contents
Chapter 1....................................................................................................................................1
Chapter 2....................................................................................................................................8
Chapter 3.................................................................................................................................. 18
Chapter 4.................................................................................................................................. 21
Chapter 5.................................................................................................................................. 33
Chapter 6.................................................................................................................................. 45
Chapter 7.................................................................................................................................. 59
Chapter 8.................................................................................................................................. 80
Chapter 9.................................................................................................................................. 92
Chapter 10 .............................................................................................................................. 100
Chapter 11 .............................................................................................................................. 106
Chapter 12 .............................................................................................................................. 116
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Chapter 1
1.
x y z x + y´ y + z (x + y´)(y + z) xy xz y´z xy + xz + y´z
0 0 0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 0 1 1
0 1 0 0 1 0 0 0 0 0
0 1 1 0 1 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 0 1
1 1 1 1 1 1 1 1 0 1
2. a)
w x y z wx xz y´ wx + xz + y´
b)
w x y z w + x + y + z
0 0 0 0 0 0 1 1 0 0 0 0 0
0 0 0 1 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 0 0 0 1 0 1
0 0 1 1 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 1 1 0 1 0 0 1
0 1 0 1 0 1 1 1 0 1 0 1 1
0 1 1 0 0 0 0 0 0 1 1 0 1
0 1 1 1 0 1 0 1 0 1 1 1 1
1 0 0 0 0 0 1 1 1 0 0 0 1
1 0 0 1 0 0 1 1 1 0 0 1 1
1 0 1 0 0 0 0 0 1 0 1 0 1
1 0 1 1 0 0 0 0 1 0 1 1 1
1 1 0 0 1 0 1 1 1 1 0 0 1
1 1 0 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 0 0 1 1 1 1 0 1
1 1 1 1 1 1 0 1 1 1 1 1 1
c)
w x y z w´x´yz w´xyz w´x´yz´ w´xyz´ w´x´yz + w´xyz + w´x´yz´ + w´xyz´
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 1 0 1
0 0 1 1 1 0 0 0 1
0 1 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0
0 1 1 0 0 0 0 1 1
0 1 1 1 0 1 0 0 1
1 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0
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3.
a b ab (ab)´ a´ b´ a´ + b´ a b a + b (a + b)´ a´ b´ a´b´
0 0 0 1 1 1 1 0 0 0 1 1 1 1
0 1 0 1 1 0 1 0 1 1 0 1 0 0
1 0 0 1 0 1 1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 1 1 1 0 0 0 0
4. a) w' + x' + y' + z'
b) w' + x' + y'z
c) (w' + x') + (w' + y') + (w' + z') + (x' + y') + (x' + z') + (y' + z') = w' + x' + y' + z'
5. a)
wx\yz 00 01 11 10
b)
wx\yz 00 01 11 10
00 1 1 0 0 00 1 1 0 1
01 0 1 1 0 01 1 1 1 0
11 0 0 1 1 11 1 1 1 0
10 1 0 0 1 10 1 0 0 1
w´x´y´ + w´xz + wxy + wx´z´ x´z´ + w´y´ + xz + xy´
or or
x´y´z´ + w´y´z + xyz + wyz´ x´z´ + w´y´ + xz + y´z´
6. a)
wx\yz 00 01 11 10
b)
wx\yz 00 01 11 10
00 1 0 0 1 00 X 1 1 X
01 1 X 1 1 01 0 X X 0
11 0 1 X 0 11 0 0 X 0
10 0 X X 0 10 X X X X
w´z´ + xy x´
7. a)
wx\yz 00 01 11 10
b)
wx\yz 00 01 11 10
c)
wx\yz 00 01 11 10
00 0 1 0 0 00 1 0 0 0 00 0 1 0 1
01 0 1 1 0 01 1 1 0 0 01 1 0 1 0
11 1 1 1 1 11 1 1 0 1 11 0 1 0 1
10 0 0 0 0 10 1 0 0 1 10 1 0 1 0
wx + xz + w´y´z y´z´ + xy´ + wz´ Already minimal
8. a) b) c)
9. wxy´ + wxz + w´xy + xyz´:
wx\yz 00 01 11 10
00 0 0 0 0
01 0 0 1 1
11 1 1 1 1
10 0 0 0 0
wx + xy
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10. a) b)
11. Change the AND gates to NAND gates. The rest of the circuit is unchanged.
12. Remove the tri-state buffers and do one of the following:
a) Change each 2-input AND gate to a 3-input AND gate. Each gates' inputs should be its two original
inputs and E, or
b) Have each AND gate's output serve as an input to another 2-input AND gate, one gate for each original
AND gate. The second input to the new 2-input AND gates is E.
13.
14.
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15. Set up Karnaugh maps for each output, then develop minimal logic expressions and design the appropriate
logic circuits.
X > Y:
X
1
X
0
\Y
1
Y
0
00 01 11 10
X = Y:
X
1
X
0
\Y
1
Y
0
00 01 11 10
X < Y:
X
1
X
0
\Y
1
Y
0
00 01 11 10
00 0 0 0 0 00 1 0 0 0 00 0 1 1 1
01 1 0 0 0 01 0 1 0 0 01 0 0 1 1
11 1 1 0 1 11 0 0 1 0 11 0 0 0 0
10 1 1 0 0 10 0 0 0 1 10 0 0 1 0
(X > Y) = X
1
Y
1
' + X
0
Y
1
'Y
0
' + X
1
X
0
Y
0
'
(X = Y) = X
1
'X
0
'Y
1
'Y
0
' + X
1
'X
0
Y
1
'Y
0
+ X
1
X
0
'Y
1
Y
0
' + X
1
X
0
Y
1
Y
0
= (X
1
⊕ Y
1
)'(X
0
⊕ Y
0
)'
(X < Y) = X
1
'Y
1
+ X
1
'X
0
'Y
0
+ X
0
'Y
1
Y
0
16. C
3
= X
2
Y
2
+ (X
2
⊕ Y
2
)(X
1
Y
1
+ (X
1
⊕ Y
1
)(X
0
Y
0
+ (X
0
⊕ Y
0
)C
0
))
C
4
= X
3
Y
3
+ (X
3
⊕ Y
3
)(X
2
Y
2
+ (X
2
⊕ Y
2
)(X
1
Y
1
+ (X
1
⊕ Y
1
)(X
0
Y
0
+ (X
0
⊕ Y
0
)C
0
)))
17.
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18
X
3
X
2
\X
1
X
0
00 01 11 10 X
3
X
2
\X
1
X
0
00 01 11 10
00 1 0 1 1 00 1 0 0 1
01 0 1 0 1 01 0 0 0 1
11 X X X X 11 X X X X
10 1 0 X X 10 1 0 X X
d = X
2
'X
0
' + X
2
'X
1
+ X
1
X
0
' + X
2
X
1
'X
0
e = X
2
'X
0
' + X
1
X
0
'
X
3
X
2
\X
1
X
0
00 01 11 10 X
3
X
2
\X
1
X
0
00 01 11 10
00 1 0 0 0 00 0 0 1 1
01 1 1 0 1 01 1 1 0 1
11 X X X X 11 X X X X
10 1 1 X X 10 1 1 X X
f = X
3
+ X
2
X
0
' + X
2
X
1
' + X
1
'X
0
' g = X
3
+ X
2
X
0
' + X
1
X
0
' + X
2
'X
1
19.
X
3
X
2
X
1
X
0
a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 0 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
a:
X
3
X
2
\X
1
X
0
00 01 11 10
b:
X
3
X
2
\X
1
X
0
00 01 11 10
c:
X
3
X
2
\X
1
X
0
00 01 11 10
00 0 1 0 0 00 0 0 0 0 00 0 0 0 1
01 1 0 0 0 01 0 1 0 1 01 0 0 0 0
11 X X X X 11 X X X X 11 X X X X
10 0 0 X X 10 0 0 X X 10 0 0 X X
a = X
3
'X
2
'X
1
'X
0
+ X
2
X
1
'X
0
' b = X
2
X
1
'X
0
+ X
2
X
1
X
0
' c = X
2
'X
1
X
0
'
d:
X
3
X
2
\X
1
X
0
00 01 11 10
e:
X
3
X
2
\X
1
X
0
00 01 11 10
f:
X
3
X
2
\X
1
X
0
00 01 11 10
00 0 1 0 0 00 0 1 1 0 00 0 1 1 1
01 1 0 1 0 01 1 1 1 0 01 0 0 1 0
11 X X X X 11 X X X X 11 X X X X
10 0 1 X X 10 0 1 X X 10 0 0 X X
d = X
2
X
1
'X
0
' + X
2
'X
1
'X
0
+ X
2
X
1
X
0
e = X
2
X
1
' + X
0
f = X
1
X
0
+ X
3
'X
2
'X
0
+ X
2
'X
1
g:
X
3
X
2
\X
1
X
0
00 01 11 10
00 1 1 0 0
01 0 0 1 0
11 X X X X
10 0 0 X X
g = X
3
'X
2
'X
1
' + X
2
X
1
X
0
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20. The four inputs can be in one of 24 (= 4!) possible orders. Since each sorter has two possible states (MAX
= X MIN = Y, or MAX = Y MIN = X), n sorters can have up to 2
n
states. Four sorters can have only 2
4
= 16
states, not enough to sort all 24 possible input orders. Five sorters have 2
5
= 32 states, which could be
sufficient. (This argument establishes a lower bound; it does not guarantee the existence of a 5-sorter
network that can sort four inputs. Since the sorting network of Figure 1.24(b) matches this bound, it is a
minimal network.)
21. a) b)
22. A flip-flop is clocked if the increment signal and clock are asserted, and all flip-flops to its right are 1.
23. Each clock is driven by Q of the flip-flop to its right instead of Q'. The clock of the rightmost flip-flop is
unchanged. All other signals are unchanged.
24.
X
2
X
1
X
0
Q
2
Q
1
Q
0
J
2
K
2
J
1
K
1
J
0
K
0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
J
2
:
X
2
\X
1
X
0
00 01 11 10
J
1
:
X
2
\X
1
X
0
00 01 11 10
J
0
:
X
2
\X
1
X
0
00 01 11 10
0 0 0 0 1 0 0 1 X X 0 1 X X 0
1 X X X X 1 0 0 X X 1 0 X X 1
J
2
= X
1
X
0
' J
1
= X
2
'X
0
J
0
= X
2
'X
1
' + X
2
X
1
K
2
:
X
2
\X
1
X
0
00 01 11 10
K
1
:
X
2
\X
1
X
0
00 01 11 10
K
0
:
X
2
\X
1
X
0
00 01 11 10
0 X X X X 0 X X 0 0 0 X 0 1 X
1 1 0 0 0 1 X X 1 0 1 X 1 0 X
K
2
= X
1
'X
0
' K
1
= X
2
X
0
K
0
= X
2
'X
1
+ X
2
X
1
'
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25. a) b)
26. a) b)
27.
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Chapter 2
1. a)
Present State D Next State
0 0 0
0 1 1
1 0 0
1 1 1
b)
Present State T Next State
0 0 0
0 1 1
1 0 1
1 1 0
2.
Present State S R Next State
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 U
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 U
U 0 0 U
U 0 1 0
U 1 0 1
U 1 1 U
3. Add the following states to the state table. Since all additions are self-loops, it is not necessary to change
the state diagram.
Present State C I
1
I
0
Next State R G A
S
NOCAR
0 0 1 S
NOCAR
1 0 0
S
NOCAR
0 1 0 S
NOCAR
1 0 0
S
NOCAR
0 1 1 S
NOCAR
1 0 0
SP
AID
1 0 1 SP
AID
0 1 0
SP
AID
1 1 0 SP
AID
0 1 0
SP
AID
1 1 1 SP
AID
0 1 0
S
CHEAT
0 0 1 S
CHEAT
1 0 1
S
CHEAT
0 1 0 S
CHEAT
1 0 1
S
CHEAT
0 1 1 S
CHEAT
1 0 1
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4.
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5.
6.
Address Data (Mealy) Data (Moore)
0000 0000 0000
0001 0010 0010
0010 0100 0100
0011 0110 0110
0100 1000 1000
0101 1010 1010
0110 1101 1100
0111 1110 1110
1000 0000 0000
1001 0010 0010
1010 0100 0100
1011 0110 0110
1100 1000 1001
1101 1010 1011
1110 1101 1100
1111 1110 1110
7.
Present State I Next State M
00 0 00 0
00 1 01 0
01 0 00 0
01 1 10 0
10 0 11 0
10 1 10 0
11 0 00 1
11 1 01 1
N
1
= P
1
'P
0
I + P
1
P
0
'
N
0
= P
1
'P
0
'I + P
1
P
0
'I' + P
1
P
0
I
M = P
1
P
0
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8.
9.
Address Data (Mealy) Data (Moore)
000 000 000
001 010 010
010 000 000
011 100 100
100 111 110
101 100 100
110 000 001
111 010 011
10. State value assignments (P
3
- P
0
): S
0
= 0000 S
5
= 0001 S
10
= 0010 S
15
= 0011 S
20
= 0100
S
25
= 0101 S
30
= 0110 S
PAID
= 0111 S
NOCAR
= 1000 S
CHEAT
= 1001
N
3
= C'
N
2
= P
3
'CI
1
I
0
+ P
3
'(P
2
+ P
1
)CI
1
I
0
' + P
3
'(P
2
+ P
1
P
0
)CI
1
'I
0
+ P
2
CI
1
'I
0
'
N
1
= P
3
'(P
2
+ P
1
+ P
0
)CI
1
I
0
+ P
3
'(P
2
+ P
1
')CI
1
I
0
' + P
3
'(P
1
'P
0
+ P
1
P
0
' + P
2
P
1
P
0
)CI
1
'I
0
+ P
1
P
0
CI
1
'I
0
'
N
0
= P
3
'(P
2
+ P
1
+ P
0
')CI
1
I
0
+ P
3
'(P
0
+ P
2
P
1
)CI
1
I
0
' + P
3
'(P
0
' + P
2
P
1
)CI
1
'I
0
+ P
3
'P
0
CI
1
'I
0
' + P
3
P
0
C
+ P
3
'(P
2
' + P
1
' + P
0
')C'
R = S
PAID
'
G = S
PAID
A = S
CHEAT
11. State value assignments (P
3
- P
0
): S
0
= 0000 S
5
= 0001 S
10
= 0010 S
15
= 0011 S
20
= 0100
S
25
= 0101 S
30
= 0110 S
PAID
= 0111 S
NOCAR
= 1000 S
CHEAT
= 1001
N
3
= C'
N
2
= P
3
'CI
1
I
0
+ P
3
'(P
2
+ P
1
)CI
1
I
0
' + P
3
'(P
2
+ P
1
P
0
)CI
1
'I
0
+ P
2
CI
1
'I
0
'
N
1
= P
3
'(P
2
+ P
1
+ P
0
)CI
1
I
0
+ P
3
'(P
2
+ P
1
')CI
1
I
0
' + P
3
'(P
1
'P
0
+ P
1
P
0
' + P
2
P
1
P
0
)CI
1
'I
0
+ P
1
P
0
CI
1
'I
0
'
N
0
= P
3
'(P
2
+ P
1
+ P
0
')CI
1
I
0
+ P
3
'(P
0
+ P
2
P
1
)CI
1
I
0
' + P
3
'(P
0
' + P
2
P
1
)CI
1
'I
0
+ P
3
'P
0
CI
1
'I
0
' + P
3
P
0
C
+ P
3
'(P
2
' + P
1
' + P
0
')C'
R = G'
G = P
3
'(P
2
+ P
1
)CI
1
I
0
+ P
3
'P
2
P
0
CI
1
+ P
3
'P
2
P
1
C(I
1
+ I
0
) + P
3
'P
2
P
1
P
0
C
A = P
3
'(P
2
+ P
1
+ P
0
)C'
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12.
Address Data
0000XXX 1001101 1001101 1001101 1001101 0000100 0001100 0010100 0101100
0001XXX 1001101 1001101 1001101 1001101 0001100 0010100 0011100 0110100
0010XXX 1001101 1001101 1001101 1001101 0010100 0011100 0100100 0111010
0011XXX 1001101 1001101 1001101 1001101 0011100 0100100 0101100 0111010
0100XXX 1001101 1001101 1001101 1001101 0100100 0101100 0110100 0111010
0101XXX 1001101 1001101 1001101 1001101 0101100 0110100 0111010 0111010
0110XXX 1001101 1001101 1001101 1001101 0110100 0111010 0111010 0111010
0111XXX 1000100 1000100 1000100 1000100 0111010 0111010 0111010 0111010
1000XXX 1000100 1000100 1000100 1000100 0000100 0000100 0000100 0000100
1001XXX 1001101 1001101 1001101 1001101 0000100 0000100 0000100 0000100
1010XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
1011XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
1100XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
1101XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
1110XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
1111XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100
13. N
2
:
P
2
P
1
\P
0
U 00 01 11 10
N
1
:
P
2
P
1
\P
0
U 00 01 11 10
N
2
:
P
2
P
1
\P
0
U 00 01 11 10
00 0 0 0 0 00 0 0 1 0 00 0 1 0 1
01 0 0 1 0 01 1 1 0 1 01 0 1 0 1
11 0 0 0 0 11 0 0 0 0 11 0 0 0 0
10 1 1 0 1 10 0 0 0 0 10 0 1 0 1
14. The next state logic is the same as for the Moore machine.
N
2
= P
2
P
0
' + P
2
U' + P
1
P
0
U
N
1
= P
1
P
0
' + P
1
U' + P
2
'P
1
'P
0
U
N
0
= P
0
'U + P
0
U'
C = P
2
'P
1
'P
0
'U' + P
2
P
1
'P
0
U
V
2
= P
2
'P
1
P
0
U + P
2
P
1
'P
0
' + P
2
P
1
'P
0
U'
V
1
= P
2
'P
1
'P
0
U + P
2
'P
1
P
0
' + P
2
'P
1
P
0
U'
V
0
= (P
2
' + P
1
')P
0
'U + (P
2
' + P
1
)P
0
U'
15. All possible next state values are already used.
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16. State value assignments (P
3
- P
0
): S
0
= 0000 S
5
= 0001 S
10
= 0010 S
15
= 0011 S
20
= 0100
S
25
= 0101 S
30
= 0110 S
PAID
= 0111 S
NOCAR
= 1000 S
CHEAT
= 1001 S
A
= 1010
S
B
= 1011 S
C
= 1100 S
D
= 1101 S
E
= 1110 S
F
= 1111
Add to state table: Present State C I
1
I
0
Next State R G A
1010 X X X 1000 0 0 0
1011 X X X 1000 0 0 0
1100 X X X 1000 0 0 0
1101 X X X 1000 0 0 0
1110 X X X 1000 0 0 0
1111 X X X 1000 0 0 0
Add to state diagram:
N
3
= C' + P
3
(P
2
+ P
1
)
N
2
= P
3
'CI
1
I
0
+ P
3
'(P
2
+ P
1
)CI
1
I
0
' + P
3
'(P
2
+ P
1
P
0
)CI
1
'I
0
+ P
2
CI
1
'I
0
'
N
1
= P
3
'(P
2
+ P
1
+ P
0
)CI
1
I
0
+ P
3
'(P
2
+ P
1
')CI
1
I
0
' + P
3
'(P
1
'P
0
+ P
1
P
0
' + P
2
P
1
P
0
)CI
1
'I
0
+ P
1
P
0
CI
1
'I
0
'
N
0
= P
3
'(P
2
+ P
1
+ P
0
')CI
1
I
0
+ P
3
'(P
0
+ P
2
P
1
)CI
1
I
0
' + P
3
'(P
0
' + P
2
P
1
)CI
1
'I
0
+ P
3
'P
0
CI
1
'I
0
' + P
3
P
0
C
+ P
3
'(P
2
' + P
1
' + P
0
')C'
R = S
PAID
'
G = S
PAID
A = S
CHEAT
17. N
3
= P
2
P
1
P
0
U' + P
3
(P
2
' + P
1
' + P
0
' + U)
N
2
= P
3
P
2
(P
0
+ U) + P
2
P
1
+ P
3
'P
1
P
0
'U'
N
1
= P
3
' (P
2
+ P
1
)U' + P
2
P
1
P
0
U' + P
1
U
N
0
= (P
3
' + P
2
)P
1
'U + P
3
'P
2
U + P
0
U'
C = P
2
'P
1
'P
0
'
V
2
= P
3
P
1
'P
0
+ P
3
P
2
P
0
'
V
1
= P
3
'P
1
P
0
' + P
2
P
1
P
0
V
0
= P
3
'P
2
'P
0
+ P
2
P
1
P
0
+ P
3
P
1
'P
0
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 14
18.
19.
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20. States are of the form ABCYZ, where A|B|C = 0 if a player may signal, or 1 if the player may not signal. YZ
represents the player answering the question (01 = player 1, 10 = player 2, 11 = player 3, 00 = no player).
Although not shown in the diagram, there is an arc from every state back to state 00000 with condition R.
Address Data Address Data Address Data
XXXXX XX1X 00000 000 00110 XX00 00110 010 10010 XX00 10010 010
00000 000X 00000 000 00110 XX01 01100 010 10010 XX01 11000 010
00000 010X 00001 000 01000 X00X 01000 000 10011 XX00 10011 001
00000 100X 00010 000 01000 010X 01001 000 10011 XX01 10100 001
00000 110X 00011 000 01000 110X 01011 000 10100 0X0X 10100 000
00001 XX00 00001 100 01001 XX00 01001 100 10100 100X 10110 000
00001 XX01 10000 100 01001 XX01 11000 100 10100 110X 10100 000
00010 XX00 00010 010 01011 XX00 01011 001 10110 XX00 10110 010
00010 XX01 01000 010 01011 XX01 01100 001 10110 XX01 11100 010
00011 XX00 00011 001 01100 000X 01100 000 11000 0X0X 11000 000
00011 XX01 00100 001 01100 010X 01101 000 11000 100X 11000 000
00100 000X 00100 000 01100 1X0X 01100 000 11000 110X 11011 000
00100 010X 00101 000 01101 XX00 01101 100 11011 XX00 11011 001
00100 100X 00110 000 01101 XX01 11100 100 11011 XX01 11100 001
00100 110X 00100 000 10000 0X0X 10000 000 11100 XX0X 11100 000
00101 XX00 00101 100 10000 100X 10010 000 All others 00000 000
00101 XX01 10100 100 10000 110X 10011 000
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21. States are of the form ABCYZ, where A|B|C = 0 if a player may signal, or 1 if the player may not signal. YZ
represents the player answering the question (01 = player 1, 10 = player 2, 11 = player 3, 00 = no player).
Although not shown in the diagram, there is an arc from every state back to state 00000 with condition R.
Address Data Address Data Address Data
XXXXX XX1X 00000 000 00110 XX00 00110 010 10010 XX00 10010 010
00000 000X 00000 000 00110 XX01 01100 000 10010 XX01 11000 000
00000 010X 00001 100 01000 X00X 01000 000 10011 XX00 10011 001
00000 100X 00010 010 01000 010X 01001 100 10011 XX01 10100 000
00000 110X 00011 001 01000 110X 01011 001 10100 0X0X 10100 000
00001 XX00 00001 100 01001 XX00 01001 100 10100 100X 10110 010
00001 XX01 10000 000 01001 XX01 11000 000 10100 110X 10100 000
00010 XX00 00010 010 01011 XX00 01011 001 10110 XX00 10110 010
00010 XX01 01000 000 01011 XX01 01100 000 10110 XX01 11100 000
00011 XX00 00011 001 01100 000X 01100 000 11000 0X0X 11000 000
00011 XX01 00100 000 01100 010X 01101 100 11000 100X 11000 000
00100 000X 00100 000 01100 1X0X 01100 000 11000 110X 11011 001
00100 010X 00101 100 01101 XX00 01101 100 11011 XX00 11011 001
00100 100X 00110 010 01101 XX01 11100 000 11011 XX01 11100 000
00100 110X 00100 000 10000 0X0X 10000 000 11100 XX0X 11100 000
00101 XX00 00101 100 10000 100X 10010 010 All others 00000 000
00101 XX01 10100 000 10000 110X 10011 001
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 17
22.
23.
24.
25. P
1
: P
0
X'Y should be P
0
XY
P
0
: P
0
XY' should be P
0
X'Y'
B: P
0
should be P
0
'
26. CLR: 0XY' should be 1XY'
Counter input D
0
: 0X'Y should be 0XY
A: 1 should be 0
27.
Address Correct Data
0011 01110
0100 01011
1011 00111
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Chapter 3
1. a) Data movement b) Data operation c) Program control d) Data operation e) Data operation
2. a) Data operation b) Program control c) Data movement d) Data movement e) Data operation
3. a) Direct b) Implied c) Implicit
4. a) Implicit b) Direct c) Implicit
5. a) Implicit b) Direct c) Implicit
6. a) Register Direct b) Immediate c) Implicit d) Immediate e) Direct
7. a) Implicit b) Direct c) Indirect d) Register Indirect e) Register Direct
8. a) Register Direct b) Register Indirect c) Implicit d) Implicit e) Immediate
9. a) AC = 11 b) AC = 12 c) AC = 10 d) AC = 11 e) AC = 10 f) AC = 33 g) AC = 41
10. a) AC = 11 b) AC = 12 c) AC = 30 d) AC = 31 e) AC = 10 f) AC = 23 g) AC = 31
11. a) AC = 11 b) AC = 12 c) AC = 20 d) AC = 21 e) AC = 10 f) AC = 43 g) AC = 21
12. a)
MUL X,B,C
b)
MOV X,B
c)
LOAD B
d)
PUSH A
ADD X,X,A MUL X,C MUL C PUSH B
ADD X,X,D ADD X,A ADD A PUSH C
ADD X,D ADD D MUL
STORE X PUSH D
ADD
ADD
POP X
13. a)
MUL T,A,B
b)
MOV T,A
c)
LOAD A
d)
PUSH A
MUL T,T,C MUL T,B MUL B PUSH B
ADD X,E,F MUL T,C MUL C MUL
MUL X,X,D MOV X,E STORE T PUSH C
ADD X,X,T ADD X,F LOAD E MUL
MUL X,D ADD F PUSH D
ADD X,T MULT D PUSH E
ADD T PUSH F
STORE X ADD
MUL
ADD
POP X
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14. a)
MUL X,B,C
b)
MOV T,B
c)
LOAD B
d)
PUSH A
SUB X,A,X MUL T,C MUL C PUSH B
MUL T,E,F MOV X,A STORE T PUSH C
ADD T,T,D SUB X,T LOAD A MUL
MUL X,X,T MOV T,E SUB T SUB
MUL T,F STORE X PUSH D
ADD T,D LOAD E PUSH E
MUL X,T MUL F PUSH F
ADD D MUL
MUL X ADD
STORE X MUL
POP X
15.
Processor Time per instruction # Instructions Total time
0 35 ns 4 140 ns
1 50 ns 3 150 ns
2 70 ns 2 140 ns
3 100 ns 1 100 ns fastest
16.
Processor Time per instruction # Instructions Total time
0 35 ns 8 280 ns
1 50 ns 5 250 ns fastest
2 70 ns 4 280 ns
3 100 ns 3 300 ns
17.
Processor Time per instruction # Instructions Total time
0 35 ns 12 420 ns fastest
1 50 ns 9 450 ns
2 70 ns 7 490 ns
3 100 ns 5 500 ns
18.
Processor Time per instruction # Instructions Total time
0 35 ns 12 420 ns fastest
1 50 ns 11 550 ns
2 70 ns 8 560 ns
3 100 ns 5 500 ns
19.
LDAC 1001H
MVAC
LDAC 1002H
ADD
MVAC
LDAC 1003H
ADD
MVAC
LDAC 1004H
ADD
MVAC
LDAC 1005H
ADD
MVAC
LDAC 1006H
ADD
MVAC
LDAC 1007H
ADD
MVAC
LDAC 1008H
ADD
MVAC
LDAC 1009H
ADD
MVAC
LDAC 100AH
ADD
STAC 1000H
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20.
Loop:
LXI H, 1001H
MVI B,0AH
XRA A
ADD M
INX H
DCR B
JNZ Loop
STA 1000H
21.
Loop:
CLAC
INAC
STAC FA
INAC
STAC FB
STAC Count
STAC FN
MVAC
LDAC
SUB
JMPZ Done
LDAC FA
MVAC
LDAC FB
ADD
STAC FA
LDAC Count
INAC
STAC Count
MVAC
LDAC n
SUB
JMPZ DoneA
FA = 1
FB = 2
Count = 2
FN = 2
If n = 2 then done
FA = FA + FB
Count = Count + 1
If Count = n then
done, result in FA
DoneA:
DoneB:
Done:
LDAC FB
MVAC
LDAC FA
ADD
STAC FB
LDAC Count
INAC
STAC Count
MVAC
LDAC n
SUB
JMPZ DoneB
JUMP Loop
LDAC FA
STAC FN
JUMP Done
LDAC FB
STAC FN

FB = FB + FA
Count = Count + 1
If Count = n then
done, result in FB
Not done, loop back
FN = FA
FN = FB
22.
Loop:
Done:
LDA n
MOV D,A
MVI B,1
MVI A,2
MOV C,A
DCR D
DCR D
JZ Done
ADD B
MOV B,A
DCR D
JZ Done
ADD C
MOV C,A
DCR D
JNZ Loop
STA FN
D = n
B = FA
C = FB
Initially A = FA
FA = FA + FB
If D = 0 then done
FB = FB + FA
If D = 0 then done
Not done, loop back
Store FN
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 21
Chapter 4
1.
2.
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3.
4.
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5.
6.
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7.
8.
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9.
10. a.) CE = A
7
'A
6
'A
5
'A
4
' ( M IO/ )' OE = RD
b.) CE = A
7
'A
6
'A
5
'A
4
( M IO/ )' OE = RD
c.) CE = A
7
A
6
A
5
A
4
( M IO/ )' OE = RD
11.
Big Endian Little Endian
a)
22 12H
23 34H
24 56H
25 78H
22 78H
23 56H
24 34H
25 12H
b)
22 09H
23 27H
22 27H
23 09H
c)
22 05H
23 55H
24 12H
25 12H
22 12H
23 12H
24 55H
25 05H
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 26
12. Start each value at location 4X, where X ∈ I ≥ 0, 20 for example.
13.
14. This is the same as the previous problem, except M IO/ is not included.
15.
16. This is the same as the previous problem, except M IO/ is not included.
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 27
17.
18. This is the same as the previous problem, except M IO/ is not included.
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19.
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 29
20.
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21.
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22. Memory subsystem:
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22 (continued). I/O subsystem:
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Chapter 5
1. a) α: W ← X, Y ← Z
b) α: W ← X
α': Y ← Z
c) α': W ← X
2. a) b) c)
3. a) α: X ← Y
β: X ← Y'
b) α: X ← 0
β: X ← X'
4. a) b)
5.
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 34
6. a) b)
c)
7.
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 35
8. a) 0011 0010 0000 0100
b) 0100 1100 1000 0001
c) 0011 0010 0000 0101
d) 0100 1100 1000 0001
e) 1011 0010 0000 0100
f) 1100 1100 1000 0001
g) 1001 0000 0010 0000
h) 0000 1001 1001 0000
9. a) 0000 0111 0010 1010
b) 0100 0001 1100 1010
c) 0000 0111 0010 1011
d) 1100 0001 1100 1010
e) 1000 0111 0010 1010
f) 1100 0001 1100 1010
g) 0011 1001 0101 0000
h) 0000 1000 0011 1001
10. a) 1011 0010 1111 0000
b) 0010 1100 1011 1100
c) 1011 0010 1111 0000
d) 0010 1100 1011 1100
e) 0011 0010 1111 0000
f) 0010 1100 1011 1100
g) 1001 0111 1000 0000
h) 0000 0101 1001 0111
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 36
11. a)
b)
c)
d)
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 37
12. a)
b)
c) d)
13. a) X ← 0,X[(n-2)-1]
b) X ← X[(n -2)-0,( n -1)]
c) X ← X[0,( n -1)-1]
d) X[(n -2)-0] ← X[(n -3)-0],0
e) X[(n -2)-0] ← X[(n -1)-1]
f) X ← X[(n -5)-0],0000
g) X ← 0000,X[(n -1)-4]
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 38
14. Define X
1
X
0
= 00 (S
0
), 01 (S
1
), 10 (S
2
), 11 (S
3
). I is the input bit.
X
1
'X
0
'I': M ← 0
X
1
'X
0
'I: X
0
← 1, M ← 0
X
1
'X
0
I': X
0
← 0
X
1
'X
0
I: X
1
← 1, X
0
← 0
X
1
X
0
'I': X
0
← 1, M ← 1
X
1
X
0
I': X
1
← 0, X
0
← 0, M ← 0
X
1
X
0
I: X
1
← 0, M ← 0
15.
16. Define X
1
X
0
= 00 (S
0
), 01 (S
1
), 10 (S
2
), 11 (S
3
). I is the input bit.
Brute force solution (one RTL
statement per input value per state)
X
2
'X
1
'X
0
'I': M ← 0
X
2
'X
1
'X
0
'I: X
0
← 1, M ← 0
X
2
'X
1
'X
0
I': X
1
← 1, X
0
← 0
X
2
'X
1
'X
0
I: X
1
← 1, X
0
← 1
X
2
'X
1
X
0
'I': X
2
← 1, X
1
← 0
X
2
'X
1
X
0
'I: X
2
← 1, X
1
← 0, X
0
← 1
X
2
'X
1
X
0
I': X
2
← 1, X
0
← 0, M ← 1
X
2
'X
1
X
0
I: X
2
← 1
X
2
X
1
'X
0
'I': X
2
← 0
X
2
X
1
'X
0
'I: X
2
← 0, X
0
← 1
X
2
X
1
'X
0
I': X
2
← 0, X
1
← 1, X
0
← 0
X
2
X
1
'X
0
I: X
2
← 0, X
1
← 1
X
2
X
1
X
0
'I': X
1
← 0, M ← 0
X
2
X
1
X
0
'I: X
1
← 0, X
0
← 1, M ← 0
X
2
X
1
X
0
I': X
0
← 0
Simpler solution (one RTL statement per state)
X
2
'X
1
'X
0
': X
0
← I, M ← 0
X
2
'X
1
'X
0
: X
1
← 1, X
0
← I
X
2
'X
1
X
0
': X
2
← 1, X
1
← 0, X
0
← I
X
2
'X
1
X
0
: X
2
← 1, X
0
← I, M ← I'
X
2
X
1
'X
0
': X
2
← 0, X
0
← I
X
2
X
1
'X
0
: X
2
← 0, X
1
← 1, X
0
← I
X
2
X
1
X
0
': X
1
← 0, X
0
← I, M ← 0
X
2
X
1
X
0
: X
0
← I, M ← I'
Simplest solution (combining states)
1: X
2
← X
1
, X
1
← X
0
, X
0
← I
X
2
'X
1
'X
0
' + X
2
'X
1
X
0
I' + X
2
X
1
X
0
': M ← X
2
'X
1
X
0
I'
17.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 39
18. library IEEE;
use IEEE.std_logic_1164.all;
entity string_checker is
port(
I,clk: in std_logic;
M: out std_logic
);
end string_checker;
architecture a_string_checker of string_checker is
type states is (S0, S1, S2, S3);
signal present_state, next_state: states;
begin
state_check_string: process(present_state,I)
begin
case present_state is
when S0 => M<='0';
if (I='0') then next_state <= S0;
else next_state <= S1;
end if;
when S1 => M<='0';
if (I='0') then next_state <= S0;
else next_state <= S2;
end if;
when S2 => M<='0';
if (I='0') then next_state <= S3;
else next_state <= S2;
end if;
when S3 => M<='1';
if (I='0') then next_state <= S0;
else next_state <= S1;
end if;
end case;
end process state_check_string;
state_transition: process(clk)
begin
if rising_edge(clk) then present_state <= next_state;
end if;
end process state_transition;
end a_string_checker;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 40
19. library IEEE;
use IEEE.std_logic_1164.all;
entity string_checker is
port(
I,clk: in std_logic;
X1,X0: buffer std_logic;
M: out std_logic
);
end string_checker;
architecture a_string_checker of string_checker is
begin
cct_string_checker: process(X1,X0,I,clk)
begin
if rising_edge(clk) then
X1 <= (X1 and (not X0)) or
((not X1) and X0 and I);
X0 <= ((not X1) and (not X0) and I) or
(X1 and (not X0) and (not I)) or
(X1 and X0 and I);
end if;
M <= X1 AND X0;
end process cct_string_checker;
end a_string_checker;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 41
20. library IEEE;
use IEEE.std_logic_1164.all;
entity string_checker is
port(
I,clk: in std_logic;
M: out std_logic
);
end string_checker;
architecture a_string_checker of string_checker is
type states is (S0, S1, S2, S3, S4, S5, S6, S7);
signal present_state, next_state: states;
begin
state_check_string: process(present_state,I)
begin
case present_state is
when S0 => M<='0';
if (I='0') then next_state <= S0;
else next_state <= S1;
end if;
when S1 => M<='0';
if (I='0') then next_state <= S2;
else next_state <= S3;
end if;
when S2 => M<='0';
if (I='0') then next_state <= S4;
else next_state <= S5;
end if;
when S3 => M<='0';
if (I='0') then next_state <= S6;
else next_state <= S7;
end if;
when S4 => M<='0';
if (I='0') then next_state <= S0;
else next_state <= S1;
end if;
when S5 => M<='0';
if (I='0') then next_state <= S2;
else next_state <= S3;
end if;
when S6 => M<='1';
if (I='0') then next_state <= S4;
else next_state <= S5;
end if;
when S7 => M<='0';
if (I='0') then next_state <= S6;
else next_state <= S7;
end if;
end case;
end process state_check_string;
state_transition: process(clk)
begin
if rising_edge(clk) then present_state <= next_state;
end if;
end process state_transition;
end a_string_checker;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 42
21. library IEEE;
use IEEE.std_logic_1164.all;
entity string_checker is
port(
I,clk: in std_logic;
X2,X1,X0: buffer std_logic;
M: out std_logic
);
end string_checker;
architecture a_string_checker of string_checker is
begin
cct_string_checker: process(X1,X0,I,clk)
begin
if rising_edge(clk) then
X2 <= X1;
X1 <= X0;
X0 <= I;
end if;
M <= X2 and X1 and (not X0);
end process cct_string_checker;
end a_string_checker;
22. library IEEE;
use IEEE.std_logic_1164.all;
entity toll_booth_controller is
port(
I1,I0,C,clk: in std_logic;
R,G,A: out std_logic
);
end toll_booth_controller;
architecture a_toll_booth_controller of toll_booth_controller is
type states is (SN, S0, S5, S10, S15, S20, S25, S30, SP, SC);
signal present_state, next_state: states;
begin
state_toll_booth_controller: process(present_state,I1,I0)
begin
case present_state is
when SN => R<='1'; G<='0'; A<='0';
if (C='1') then next_state <= S0;
else next_state <= SN;
end if;
when S0 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S5;
elsif (I1 = '1' AND I0 = '0') then next_state <= S10;
elsif (I1 = '1' AND I0 = '1') then next_state <= S25;
else next_state <= S0;
end if;
when S5 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S10;
elsif (I1 = '1' AND I0 = '0') then next_state <= S15;
elsif (I1 = '1' AND I0 = '1') then next_state <= S30;
else next_state <= S5;
end if;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 43
when S10 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S15;
elsif (I1 = '1' AND I0 = '0') then next_state <= S20;
elsif (I1 = '1' AND I0 = '1') then next_state <= SP;
else next_state <= S10;
end if;
when S15 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S20;
elsif (I1 = '1' AND I0 = '0') then next_state <= S25;
elsif (I1 = '1' AND I0 = '1') then next_state <= SP;
else next_state <= S15;
end if;
when S20 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S25;
elsif (I1 = '1' AND I0 = '0') then next_state <= S30;
elsif (I1 = '1' AND I0 = '1') then next_state <= SP;
else next_state <= S20;
end if;
when S25 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '0' AND I0 = '1') then next_state <= S30;
elsif (I1 = '1') then next_state <= SP;
else next_state <= S25;
end if;
when S30 => R<='1'; G<='0'; A<='0';
if (C='0') then next_state <= SC;
elsif (I1 = '1' OR I0 = '1') then next_state <= SP;
else next_state <= S30;
end if;
when SP => R<='0'; G<='1'; A<='0';
if (C='0') then next_state <= SN;
else next_state <= SP;
end if;
when SC => R<='1'; G<='0'; A<='1';
if (C='1') then next_state <= S0;
else next_state <= SC;
end if;
end case;
end process state_toll_booth_controller;
state_transition: process(clk)
begin
if rising_edge(clk) then present_state <= next_state;
end if;
end process state_transition;
end a_toll_booth_controller;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 44
23. library IEEE;
use IEEE.std_logic_1164.all;
entity toll_booth_controller is
port(
I1,I0,C,clk: in std_logic;
X3,X2,X1,X0: buffer std_logic;
R,G,A: out std_logic
);
end toll_booth_controller;
architecture a_toll_booth_controller of toll_booth_controller is
begin
cct_toll_booth_controller: process(X3,X2,X1,X0,I1,I0,C,clk)
begin
if rising_edge(clk) then
X3 <= not C;
X2 <= ((not X3) and C and I1 and I0) or
((not X3) and (X2 or X1) and C and I1 and (not I0)) or
((not X3) and (X2 or (X1 and X0)) and C and (not I1) and I0)
or (X2 and C and (not I1) and (not I0));
X1 <= ((not X3) and (X2 or X1 or X0) and C and I1 and I0)or
((not X3) and (X2 or (not X1)) and C and I1 and (not I0)) or
((not X3) and (((not X1) and X0) or (X1 and (not X0)) or
(X2 and X1 and X0)) and C and (not I1) and I0) or
(X1 and X0 and C and (not I1) and (not I0));
X0 <= ((not X3) and (X2 or X1 or (not X0)) and C and I1 and I0) or
((not X3) and (X0 or (X2 and X1)) and C and I1 and (not I0))
or ((not X3) and ((not X0) or (X2 and X1)) and C and
(not I1) and I0) or ((not X3) and X0 and C and (not I1) and
(not I0)) or (X3 and X0 and (not C)) or ((not X3) and
((not X2) or (not X1) or (not X0)) and (not C));
end if;
R <= X3 or (not X2) or (not X1) or (not X0);
G <= (not X3) and X2 and X1 and X0;
A <= X3 and (not X2) and (not X1) and X0;
end process cct_toll_booth_controller;
end a_toll_booth_controller;
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 45
Chapter 6
1. JMP11: PC ← AR
JMP12: PC ← PC + 1
INC21: AC ← AC + 1
INC22: AC ← AC + 1
ADD11: DR ← M, AC ← AC + 1
ADD12: AC ← AC + DR
SKIP1: PC ← PC + 1
2.
Instruction Instruction Code Operation
ADDADD 00AAAAAA AC ← AC + M[AAAAAA] + M[AAAAAA + 1]
ANDSKIP 01AAAAAA AC ← AC ^ M[AAAAAA], PC ← PC + 1
INCAND 1XAAAAAA AC ← (AC + 1) ^ M[AAAAAA]
3. This is one of many possible solutions.
4.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 46
5. Change the input to the counter to X, X', Y, X ∨ Y.
Change INC input IA3 to IA2.
Change CLR input IA2 to IA3.
6. (IR must have 3 bits instead of 2.)
FETCH3: IR ← DR[7..5], AR ← DR[5..0]
CLEAR1: AC ← 0
7. i) IR must have 3 bits instead of 2. It receives bus bits 7..5 as its inputs. During FETCH3, bit 5 of DR is
sent to both IR and AR.
ii) AC needs a CLR input (ACCLR is a new control signal which connects to the new CLR input.)
8. Arbitrarily assign CLEAR1 to decoder output 15.
i) New input to counter: 1,IR[2..1],(IR
2
^ IR
1
^ IR
0
).
ii) Add CLEAR1 to the inputs of the OR gate driving counter CLR.
iii) New control signal ACCLR = CLEAR1.
9. Test program: 0: CLEAR
Instruction State Operations performed Next state
CLEAR FETCH1 AR ← 0 FETCH2
FETCH2 DR ← E0H, PC ← 1 FETCH3
FETCH3 IR ← 111, AR ← 20H CLEAR1
CLEAR1 AC ← 0 FETCH1
10. (IR must have 4 bits instead of 2.)
FETCH3: IR ← DR[7..4], AR ← DR[5..0]
MVAC1: R ← AC
MOVR1: AC ← R
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 47
11. i.) IR must have 4 bits instead of 2. It receives bus bits 7..4 as its inputs. During FETCH3, bit DR[5..4] is
sent to both IR and AR. This is shown below.
ii) Register R is added to the CPU. It receives data from the bus and sends data to the bus through tri-state
buffers. It requires only a LD signal. This is shown below.
iii) The ALU is modified as shown below.
12. Arbitrarily assign MVAC1 and MOVR1 to decoder outputs 6 and 7, respectively.
i) New input to counter: (IR
3
^ IR
2
^ IR
1
)', IR[3..2],(IR
3
^ IR
2
^ IR
1
^ IR
0
.).
ii) Add MVAC1 and MOVR1 to the inputs of the OR gate driving counter CLR.
iii) New control signals RLOAD = MVAC1 and RBUS = MOVR1.
iv) Add MOVR1 to the inputs of the OR gate generating ACLOAD.
13. Test program: 0: MVAC
1: MOVR
Instruction State Operations performed Next state
MVAC FETCH1 AR ← 0 FETCH2
FETCH2 DR ← E0H, PC ← 1 FETCH3
FETCH3 IR ← 1110, AR ← 20H MVAC1
MVAC1 R ← 1 FETCH1
MOVR FETCH1 AR ← 1 FETCH2
FETCH2 DR ← F0H, PC ← 2 FETCH3
FETCH3 IR ← 1111, AR ← 30H MOVR1
MOVR1 AC← 1 FETCH1
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 48
14. All operations except AND are performed by the parallel adder.
Micro-operation Adder inputs
ADD1 AC + BUS + 0
shl AC + AC + 0
neg 0 + BUS' + 0
ad1 AC + BUS + 1
15.
PCLOAD =JUMP3 ∨ JMPZY3 ∨ JPNZY3
PCINC =FETCH2 ∨ LDAC1 ∨ LDAC2 ∨ STAC1 ∨ STAC2 ∨ JMPZN1 ∨ JMPZN2 ∨ JPNZN1 ∨
JPNZN2
DRLOAD =FETCH2 ∨ LDAC1 ∨ LDAC2 ∨ LDAC4 ∨ STAC1 ∨ STAC2 ∨ STAC4 ∨ JUMP1 ∨ JUMP2
∨ JMPZY1 ∨ JMPZY2 ∨ JPNZY1 ∨ JPNZY2
TRLOAD =LDAC2 ∨ STAC2 ∨ JUMP2 ∨ JMPZY2 ∨ JPNZY2
IRLOAD =FETCH3
16.
RLOAD =MVAC1
ACLOAD =LDAC5 ∨ MOVR1 ∨ ADD1 ∨ SUB1 ∨ INAC1 ∨ CLAC1 ∨ AND1 ∨ OR1 ∨ XOR1 ∨ NOT1
ZLOAD =ADD1 ∨ SUB1 ∨ INAC1 ∨ CLAC1 ∨ AND1 ∨ OR1 ∨ XOR1 ∨ NOT1
17.
State ALUS[1..7]
LDAC5 0 0 1 0 X X 0
MOVR1 0 0 1 0 X X 0 ALUS1 = ADD1 ∨ SUB1 ∨ INAC1
ADD1 1 0 1 0 X X 0 ALUS2 = SUB1
SUB1 1 1 0 0 X X 0 ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1
INAC1 1 0 0 1 X X 0 ALUS4 = SUB1 ∨ INAC1
CLAC1 0 0 0 0 X X 0 ALUS5 = XOR1 ∨ NOT1
AND1 X X X X 0 0 1 ALUS6 = OR1 ∨ NOT1
OR1 X X X X 0 1 1 ALUS7 = AND1 ∨ OR1 ∨ XOR1 ∨ NOT1
XOR1 X X X X 1 0 1
NOT1 X X X X 1 1 1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 49
18. The student can execute the following program using the Relatively Simple CPU simulator to verify that
each instruction performs properly.
0: LDAC 0000 (AC ← 1)
NOP
MVAC (R ← 1)
ADD (AC ← 2, Z ← 0)
INAC (AC ← 3, Z ← 0)
XOR (AC ← 2, Z ← 0)
AND (AC ← 0, Z ← 1)
9: JMPZ 000D (jump is taken)
NOP (skipped by JMPZ 000D)
D: JPNZ 0009 (jump is not taken)
NOT (AC ← FF, Z ← 0)
JMPZ 0009 (jump is not taken)
JPNZ 0018 (jump is taken)
NOP (skipped by JMPZ 0018)
18: CLAC (AC ← 0, Z ← 1)
OR (AC ← 1, Z ← 0)
SUB (AC ← 0, Z ← 1)
MOVR (AC ← 1)
STAC 0030 (M[30] ← 1)
AND (AC ← 1, Z ← 0)
JUMP 0000 (start again)
19. SETR1: R ← 0
SETR2: R ← R - 1
20. R needs two additional inputs: CLR, driven by new control signal RCLR, and DCR, driven by new control
signal RDCR.
21. i.) Add hardware to generate ISETR = I
7
' ^ I
6
' ^ I
5
' ^ I
4
^ I
3
' ^ I
2
' ^ I
1
' ^ I
0
', SETR1 = ISETR ^ T3, and
SETR2 = ISETR ^ T4.
ii) Add SETR1 to the OR gate driving INC of the time counter and SETR2 to the OR gate driving CLR of
the time counter.
iii) New control signals RCLR = SETR1 and RDCR = SETR2.
22. Test program: 0: SETR
Instruction State Operations performed Next state
SETR FETCH1 AR ← 0 FETCH2
FETCH2 DR ← 11H, PC ← 1 FETCH3
FETCH3 IR ← 11, AR ← 1 SETR1
SETR1 R ← 0 SETR2
SETR2 R ←FF FETCH1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 50
23.
ADDB1: AC ← AC + B
SUBB1: AC ← AC - B
ANDB1: AC ← AC ^ B
ORB1: AC ← AC ∨ B
XORB1: AC ← AC ⊕ B
24. i.) No ALU changes are needed!
ii) Register B is added to the CPU. It sends data to the bus through tri-state buffers but does not receive
data from the bus (since it is never loaded). This is shown below.
25. i.) Add the hardware shown below to generate IADDB, ISUBB, IANDB, IORB, and IXORB, and add
hardware to generate ADDB1 = IADDB ^ T3, SUBB1 = ISUBB ^ T3, ANDB1 = IANDB ^ T3,
ORB1 = IORB ^ T3, and XORB1 = IXORB ^ T3.
ii) OR together ADDB1, SUBB1, ANDB1, ORB1, and XORB1 to generate BBUS.
iii) Add the same five signals to the OR gate driving CLR of the counter.
iv) Change ALUS[1..7] such that ADD1 is replaced by ADD1 ∨ ADDB1, and so on for SUB1, AND1,
OR1, and XOR1, yielding:
ALUS1 = ADD1 ∨ ADDB1 ∨ SUB1 ∨ SUBB1 ∨ INAC1
ALUS2 = SUB1 ∨ SUBB1
ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1∨ ADDB1
ALUS4 = SUB1 ∨ SUBB1∨ INAC1
ALUS5 = XOR1 ∨ XORB1 ∨ NOT1
ALUS6 = OR1 ∨ ORB1 ∨ NOT1
ALUS7 = AND1 ∨ ANDB1 ∨ OR1 ∨ ORB1 ∨ XOR1 ∨ XORB1 ∨ NOT1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 51
26. Initially AC = 1 and B = 2. Fetch cycles not shown.
Instruction State Operations performed
ORB ORB1 AC ← 1 ∨ 2 = 3
ADDB ADDB1 AC ← 3 + 2 = 5
ANDB ANDB1 AC ← 5 ^ 2 = 0
XORB XORB1 AC ← 0 ⊕ 2 = 2
SUBB SUBB1 AC ← 2 - 2 = 0
27. i.) Remove CLAC1 and INAC1 as inputs to the OR gate which generates ACLOAD.
ii) Add control inputs to AC: CLR = CLAC1, and INC = INAC1.
iii) Change the input to Z as shown below. ZLOAD is unchanged.
28. State diagram and RTL code:
FETCH1: AR ← PC
FETCH2: DR ← M, PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
COM1: AC ← AC'
JREL1: DR ← M
JREL2: PC ← PC + DR[5..0]
OR1: DR ← M
OR2: AC ← AC ∨ DR
SUB11: DR ← M
SUB12: AC ← AC + DR'
The register section is the same as Figure 6.6, except for the data input to PC, shown below.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 52
Control signals: ARLOAD =FETCH1 ∨ FETCH3
PCLOAD =JREL2
PCINC =FETCH2
PCBUS =FETCH1
DRLOAD = MEMBUS = READ =FETCH2 ∨ JREL1∨ OR1∨ SUB11
DRBUS =FETCH3 ∨ JREL2 ∨ OR2 ∨ SUB12
ACLOAD =COM1 ∨ OR2 ∨ SUB12
IRLOAD =FETCH3
ALU:
Control unit:
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 53
29. State diagram and RTL code:
FETCH1: AR ← PC ADD1: DR ← M, PC ← PC + 1
FETCH2: DR ← M, PC ← PC + 1 ADD2: AC ← AC + DR
FETCH3: IR ← DR[7..5], AR ← PC OR1: DR ← M, PC ← PC + 1
LDI1: DR ← M, PC ← PC + 1 OR2: AC ← AC ∨ DR
LDI2: AC ← DR JUMP1: DR ← M
STO1: DR ← M, PC ← PC + 1 JUMP2: PC ← DR
STO2: AR ← DR JREL1: PC ← PC + 000DR[4..0]
STO3: DR ← AC SKIP1: PC ← PC + 1
STO4: M ← DR RST1: PC ← 0, AC ← 0
Control signals: ARLOAD =FETCH1 ∨ FETCH3 ∨ STO2
PCLOAD =JUMP2 ∨ JREL2
PCINC =FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ SKIP1
PCCLR =RST1
PCBUS =FETCH1 ∨ FETCH3
PCMUX =JUMP2
DRLOAD =FETCH2 ∨ LDI1 ∨ STO1 ∨ STO3 ∨ ADD1 ∨ OR1 ∨ JUMP1
DRBUS =FETCH3 ∨ LDI2 ∨ STO2 ∨ STO4 ∨ ADD2 ∨ OR2 ∨ JUMP2 ∨ JREL1
ACLOAD =LDI2 ∨ ADD2 ∨ OR2
ACCLR =RST1
ACBUS =STO3
IRLOAD =FETCH3
MEMBUS = READ =FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ JUMP1
BUSMEM = WRITE =STO4
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 54
Register section:
ALU:
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 55
Control unit:
FETCH1 = T0 ADD1 = IADD ^ T3
FETCH2 = T1 ADD2 = IADD ^ T4
FETCH3 = T2 OR1 = IOR ^ T3
LDI1 = ILDI ^ T3 OR2 = IOR ^ T4
LDI2 = ILDI ^ T4 JUMP1 = IJUMP ^ T3
STO1 = ISTO ^ T3 JUMP2 = IJUMP ^ T4
STO2 = ISTO ^ T4 JREL1 = IJREL ^ T3
STO3 = ISTO ^ T5 JREL2 = IJREL ^ T4
STO4 = ISTO ^ T6 SKIP1 = ISKIP ^ T3
RST1 = IRST ^ T3
30. Modified state diagram:
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 56
Modified RTL code:
LDSP1: DR ← M, AR ← AR + 1, PC ← PC + 1 PUSHAC1: SP ← SP - 1, DR ← AC
LDSP2: TR ← DR, DR ← M, PC ← PC + 1 PUSHAC2: AR ← SP
LDSP3: SP ← DR,TR PUSHAC3: M ← DR
CALL1: DR ← M, AR ← AR + 1, PC ← PC + 1 POPAC1: AR ← SP
CALL2: TR ← DR, DR ← M, PC ← PC + 1 POPAC2: DR ← M, SP ← SP + 1
CALL3: TR2 ← DR, DR ← PC[15..8], SP ← SP - 1 POPAC3: AC ← DR
CALL4: AR ← SP PUSHR1: SP ← SP - 1, DR ← R
CALL5: M ← DR, AR ← AR - 1, SP ← SP - 1 PUSHR2: AR ← SP
CALL6: DR ← PC[7..0] PUSHR3: M ← DR
CALL7: M ← DR POPR1: AR ← SP
CALL8: PC ← TR2,DR POPR2: DR ← M, SP ← SP + 1
RET1: AR ← SP POPR3: R ← DR
RET2: DR ← M, SP ← SP + 1, AR ← AR + 1
RET3: TR ← DR, DR ← M, SP ← SP + 1
RET4: PC ← DR,TR
Modified register section: (shown below)
• New registers: SP (with LD, DEC, INC), TR2 (with LD, receives data directly from DR)
• New control signal: AR adds a DEC signal
• New data path: DR can receive data from BUS[15..8] or BUS[7..0]
• All other connections remain the same as shown in Figure 6.15.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 57
New control signals:
ARDEC = CALL5
SPLOAD = LDSP3
SPINC = RET2 ∨ RET3 ∨ POPAC2 ∨ POPR2
SPDEC = CALL3 ∨ CALL5 ∨ PUSHAC1 ∨ PUSHR1
SPBUS = CALL4 ∨ RET1 ∨ PUSHAC2 ∨ POPAC1 ∨ PUSHR2 ∨ POPR1
DRSEL = CALL3
TR2LOAD = CALL3
TR2BUS = CALL8
Modified control signals:
ARLOAD = (original value) ∨ CALL4 ∨ RET1 ∨ PUSHAC2 ∨ POPAC1 ∨
PUSHR2 ∨ POPR1
ARINC = (original value) ∨ LDSP1 ∨ CALL1 ∨ RET2
PCLOAD = (original value) ∨ CALL8 ∨ RET4
PCINC = (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2
PCBUS = (original value) ∨ CALL3 ∨ CALL6
DRLOAD = (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨
CALL3 ∨ CALL6 ∨ RET2 ∨ RET3 ∨ PUSHAC1 ∨ POPAC2 ∨
PUSHR1 ∨ POPR2
DRHBUS = (original value) ∨ LDSP3 ∨ RET4
DRLBUS = (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ POPAC3 ∨
PUSHR3 ∨ POPR3
TRLOAD = (original value) ∨ LDSP2 ∨ CALL2 ∨ RET3
TRBUS = (original value) ∨ LDSP3 ∨ CALL8 ∨ RET4
RLOAD = (original value) ∨ POPR3
RBUS = (original value) ∨ PUSHR1
ACLOAD = (original value) ∨ POPAC3
ACBUS = (original value) ∨ PUSHAC1
ALUS1 = (original value) ∨ POPAC3
MEMBUS = (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨ RET2
∨ RET3 ∨ POPAC2 ∨ POPR2
BUSMEM = (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ PUSHR3
WRITE = (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ PUSHR3
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 58
Control unit modifications:
• Increase the counter size to 4 bits. The decoder now outputs T
0
- T
10
.
• Add a second instruction decoder as shown below.
• Modify the INC and CLR inputs to the counter as follows:
INC = (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨ CALL3 ∨ CALL4 ∨ CALL5 ∨ CALL6
∨ CALL7 ∨ RET1 ∨ RET2 ∨ RET3 ∨ PUSHAC1 ∨ PUSHAC2 ∨ POPAC1 ∨ POPAC2
∨ PUSHR1 ∨ PUSHR2 ∨ POPR1 ∨ POPR2
CLR = (original value) ∨ LDSP3 ∨ CALL8 ∨ RET4 ∨ PUSHAC3 ∨ POPAC3 ∨ PUSHR3 ∨ POPR3
LDSP1 = ILDSP ^ T3 PUSHAC1 = IPUSHAC ^ T3
LDSP2 = ILDSP ^ T4 PUSHAC2 = IPUSHAC ^ T4
LDSP3 = ILDSP ^ T5 PUSHAC3 = IPUSHAC ^ T5
CALL1 = ICALL ^ T3 POPAC1 = IPOPAC ^ T3
CALL2 = ICALL ^ T4 POPAC2 = IPOPAC ^ T4
CALL3 = ICALL ^ T5 POPAC3 = IPOPAC ^ T5
CALL4 = ICALL ^ T6 PUSHR1 = IPUSHR ^ T3
CALL5 = ICALL ^ T7 PUSHR2 = IPUSHR ^ T4
CALL6 = ICALL ^ T8 PUSHR3 = IPUSHR ^ T5
CALL7 = ICALL ^ T9 POPR1 = IPOPR ^ T3
CALL8 = ICALL ^ T10 POPR2 = IPOPR ^ T4
RET1 = IRET ^ T3 POPR3 = IPOPR ^ T5
RET2 = IRET ^ T4
RET3 = IRET ^ T5
RET4 = IRET ^ T6
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 59
Chapter 7
1.
IR MAP
00 0011
01 0101 MAP = IR
1
^ IR
0
, IR
1
⊕ IR
0
,

IR
0
',(IR
1
^ IR
0
)'
10 0111
11 1000
2.
State Address S
E
L
A
R
P
C
A
I
D
R
P
C
I
N
P
C
D
R
D
R
M
P
L
U
S
A
N
D
A
C
I
N
ADDR
FETCH1 0000 (0) 0 1 0 0 0 0 0 0 0 0001
FETCH2 0001 (1) 0 0 0 1 0 1 0 0 0 0010
FETCH3 0010 (2) 1 0 1 0 0 0 0 0 0 XXXX
ADD1 0011 (3) 0 0 0 0 0 1 0 0 0 0100
ADD2 0100 (4) 0 0 0 0 0 0 1 0 0 0000
AND1 0101 (5) 0 0 0 0 0 1 0 0 0 0110
AND2 0110 (6) 0 0 0 0 0 0 0 1 0 0000
JMP1 0111 (7) 0 0 0 0 1 0 0 0 0 0000
INC1 1000 (8) 0 0 0 0 0 0 0 0 1 0000
3.
M1 M2
NOP NOP Required
DR ← M PC ← PC + 1 Micro-operations in these two rows must be
AC ← AC' AC ← AC + 1 allocated the same relative to each other
DR ← DR + 1 PC ← PC + DR[5..0] The remaining operations are assigned
AR ← PC arbitrarily
IR,AR ← DR
AC ← AC ⊕ DR
M ← DR
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 60
4. Test program: 0: ADD 4
1: AND 5
2: INC
3: JMP 0
4: 27H
5: 39H
Instruction State Address Micro-operations Operations performed Next Address
ADD 4 FETCH1 0000 ARPC AR ← 0 0001
FETCH2 0001 DRM, PCIN DR ← 04H, PC ← 1 0010
FETCH3 0010 AIDR IR ← 00, AR ← 04H 1000
ADD1 1000 DRM DR ← 27H 1001
ADD2 1001 PLUS AC ← 0 + 27H = 27H 0000
AND 5 FETCH1 0000 ARPC AR ← 1 0001
FETCH2 0001 DRM, PCIN DR ← 45H, PC ← 2 0010
FETCH3 0010 AIDR IR ← 01, AR ← 05H 1010
AND1 1010 DRM DR ← 39H 1011
AND2 1011 AND AC ← 27H ^ 39H = 31H 0000
INC FETCH1 0000 ARPC AR ← 2 0001
FETCH2 0001 DRM, PCIN DR ← C0H, PC ← 3 0010
FETCH3 0010 AIDR IR ← 11, AR ← 00H 1110
INC1 1110 ACIN AC ← 21H + 1 = 22H 0000
JMP 0 FETCH1 0000 ARPC AR ← 3 0001
FETCH2 0001 DRM, PCIN DR ← 80H, PC ← 4 0010
FETCH3 0010 AIDR IR ← 10, AR ← 00H 1100
JMP1 1100 PCDR PC ← 0 0000
5. Use the same test program as in problem 4.
Instruction State Address M1 M2 Operations performed Next Address
ADD 4 FETCH1 0000 ARPC NOP AR ← 0 0001
FETCH2 0001 DRM PCIN DR ← 04H, PC ← 1 0010
FETCH3 0010 AIDR NOP IR ← 00, AR ← 04H 1000
ADD1 1000 DRM NOP DR ← 27H 1001
ADD2 1001 PLUS NOP AC ← 0 + 27H = 27H 0000
AND 5 FETCH1 0000 ARPC NOP AR ← 1 0001
FETCH2 0001 DRM PCIN DR ← 45H, PC ← 2 0010
FETCH3 0010 AIDR NOP IR ← 01, AR ← 05H 1010
AND1 1010 DRM NOP DR ← 39H 1011
AND2 1011 AND NOP AC ← 27H ^ 39H = 31H 0000
INC FETCH1 0000 ARPC NOP AR ← 2 0001
FETCH2 0001 DRM PCIN DR ← C0H, PC ← 3 0010
FETCH3 0010 AIDR NOP IR ← 11, AR ← 00H 1110
INC1 1110 ACIN NOP AC ← 21H + 1 = 22H 0000
JMP 0 FETCH1 0000 ARPC NOP AR ← 3 0001
FETCH2 0001 DRM PCIN DR ← 80H, PC ← 4 0010
FETCH3 0010 AIDR NOP IR ← 10, AR ← 00H 1100
JMP1 1100 PCDR NOP PC ← 0 0000
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 61
6. Use the same test program as in problem 4.
Instruction State Address Control Signals Operations performed Next Address
ADD 4 FETCH1 0000 PCBUS, ARLOAD AR ← 0 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← 04H, PC ← 1 0010
FETCH3 0010 DRBUS, ARLOAD,
IRLOAD
IR ← 00, AR ← 04H 1000
ADD1 1000 READ, MEMBUS,
DRLOAD
DR ← 27H 1001
ADD2 1001 DRBUS, ACLOAD AC ← 0 + 27H = 27H 0000
AND 5 FETCH1 0000 PCBUS, ARLOAD AR ← 1 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← 45H, PC ← 2 0010
FETCH3 0010 DRBUS, ARLOAD,
IRLOAD
IR ← 01, AR ← 05H 1010
AND1 1010 READ, MEMBUS,
DRLOAD
DR ← 39H 1011
AND2 1011 DRBUS, ALUSEL,
ACLOAD
AC ← 27H ^ 39H = 31H 0000
INC FETCH1 0000 PCBUS, ARLOAD AR ← 2 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← C0H, PC ← 3 0010
FETCH3 0010 DRBUS, ARLOAD,
IRLOAD
IR ← 11, AR ← 00H 1110
INC1 1110 ACINC AC ← 21H + 1 = 22H 0000
JMP 0 FETCH1 0000 PCBUS, ARLOAD AR ← 3 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← 80H, PC ← 4 0010
FETCH3 0010 DRBUS, ARLOAD,
IRLOAD
IR ← 10, AR ← 00H 1100
JMP1 1100 DRBUS, PCLOAD PC ← 0 0000
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 62
7. Modified state diagram: (same as for problem 6.6)
Modified RTL code: (same as for problem 6.6)
FETCH3: IR ← DR[7..5], AR ← DR[5..0]
CLEAR1: AC ← 0
Microsequencer modifications:
Change the mapping hardware so that its inputs are IR[2..0] and its outputs are 1,IR[2..1],(IR
2
^ IR
1
^ IR
0
).
Register modifications: (same as for problem 6.7)
i) IR must have 3 bits instead of 2. It receives bus bits 7..5 as its inputs. During FETCH3, bit 5 of DR is
sent to both IR and AR.
ii) AC needs a CLR input (ACCLR is a new control signal which connects to the new CLR input.)
Microcode modifications:
i) Add mico-operation ACCL, which sets AC ← 0. Connect this bit of the microsequencer to the CLR
input of AC.
ii) Add the following to microcode memory. Set the ACCL field to 0 for all other microinstructions.
State Address S
E
L
A
R
P
C
A
I
D
R
P
C
I
N
P
C
D
R
D
R
M
P
L
U
S
A
N
D
A
C
I
N
A
C
C
L
ADDR
CLEAR1 1111 (15) 0 0 0 0 0 0 0 0 0 1 0000
Verification: Test program: 0: CLEAR
Instruction State Address Micro-operations Operations performed Next Address
CLEAR FETCH1 0000 ARPC AR ← 0 0001
FETCH2 0001 DRM, PCIN DR ← 04H, PC ← 1 0010
FETCH3 0010 AIDR IR ← 111, AR ← 04H 1111
CLEAR1 1111 ACCL AC ← 00 0000
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 63
8. The modifications are the same as in problem 7 with the following exceptions.
i) Label output 0 of the M1 decoder ACCL. (This can be done because the NOP of M1 is never used.
If it was used, a new micro-operation code would have to be created.) The code for ACCL is M1 = 000.
ii) Connect ACCL to ACCLR.
iii) Add the following to microcode memory.
State Address SEL M1 M2 ADDR
CLEAR1 1111 0 000 0 0000
Verification: Test program: 0: CLEAR
Instruction State Address M1 M2 Operations performed Next Address
CLEAR FETCH1 0000 ARPC NOP AR ← 0 0001
FETCH2 0001 DRM PCIN DR ← 04H, PC ← 1 0010
FETCH3 0010 AIDR NOP IR ← 111, AR ← 04H 1111
CLEAR1 1111 ACCL NOP AC ← 00 0000
9. The modifications are the same as in problem 7 with the following exceptions.
i) Add control signal output ACCLR to the control signals in microcode memory. Set it to 0 for all
microinstructions except the microinstruction at address 1111.
ii) Add the following to microcode memory.
State Address S
E
L
A
R
L
O
A
D
P
C
L
O
A
D
P
C
I
N
C
D
M
R
A
C
L
O
A
D
A
C
I
N
C
I
R
L
O
A
D
A
L
U
S
E
L
P
C
B
U
S
D
R
B
U
S
A
C
C
L
R
ADDR
CLEAR1 1111 (15) 0 0 0 0 0 0 0 0 0 0 0 1 0000
Verification: Test program: 0: CLEAR
Instruction State Address Control Signals Operations performed Next Address
CLEAR FETCH1 0000 PCBUS, ARLOAD AR ← 0 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← 04H, PC ← 1 0010
FETCH3 0010 DRBUS,
ARLOAD,
IRLOAD
IR ← 111, AR ← 04H 1111
CLEAR1 1111 ACCLR AC ← 00 0000
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 64
10. Modified state diagram: (same as for problem 6.10)
(IR must have 4 bits instead of 2.)
Modified RTL code: (same as for problem 6.10)
FETCH3: IR ← DR[7..4], AR ← DR[5..0]
MVAC1: R ← AC
MOVR1: AC ← R
Microsequencer modifications:
i) Change the mapping hardware so that its inputs are IR[3..0] and its outputs are
(IR
3
^ IR
2
^ IR
1
),IR[3..2],(IR
3
^ IR
2
^ IR
1
^ IR
0
).
ii) Add micro-operation RAC (R ← AC); connect it to an OR gate that generates ACBUS and have it
directly drive RLOAD.
iii) Add micro-operation ACR (AC ← R); connect it to directly to RBUS and connect it to an OR gate
that generates ACLOAD.
Register and ALU modifications: (same as for problem 6.11)
i.) IR must have 4 bits instead of 2. It receives bus bits 7..4 as its inputs. During FETCH3, bit DR[5..4] is
sent to both IR and AR. This is shown below.
ii) Register R is added to the CPU. It receives data from the bus and sends data to the bus through tri-state
buffers. It requires only a LD signal. This is shown below.
iii) The ALU is modified as shown below.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 65
Microcode modifications:
Add the following to microcode memory. Set the RAC and ACR fields to 0 for all other microinstructions.
State Address S
E
L
A
R
P
C
A
I
D
R
P
C
I
N
P
C
D
R
D
R
M
P
L
U
S
A
N
D
A
C
I
N
R
A
C
A
C
R
ADDR
MVAC1 0110 (6) 0 0 0 0 0 0 0 0 0 1 0 0000
MOVR1 0111 (7) 0 0 0 0 0 0 0 0 0 0 1 0000
Verification: Test program: 0: MVAC (Initially AC = 1)
1: MOVR
Instruction State Address Micro-operations Operations performed Next Address
MVAC FETCH1 0000 ARPC AR ← 0 0001
FETCH2 0001 DRM, PCIN DR ← E0H, PC ← 1 0010
FETCH3 0010 AIDR IR ← 1110, AR ← 20H 0110
MVAC1 0110 RAC R ← 01H 0000
MOVR FETCH1 0000 ARPC AR ← 1 0001
FETCH2 0001 DRM, PCIN DR ← F0H, PC ← 2 0010
FETCH3 0010 AIDR IR ← 1111, AR ← 30H 0111
MOVR1 0111 ACR AC ← 01H 0000
11. The modifications are the same as in problem 10 with the following exceptions.
i) Add micro-operations RAC (R ← AC) and ACR (AC ← R) to M2 with the following assignments.
M2 Micro-operation
00 NOP
01 PCIN
10 RAC
11 ACR
ii) Use a 2-to-4 decoder to generate the control signals for M2.
iii) Modify the existing microinstructions to accommodate the new values for M2 (0 → 00, 1 → 01).
iv) Add the following to microcode memory.
State Address SEL M1 M2 ADDR
MVAC1 0110 0 000 10 0000
MOVR1 0111 0 000 11 0000
Verification: Test program: 0: MVAC (Initially AC = 1)
1: MOVR
Instruction State Address M1 M2 Operations performed Next Address
MVAC FETCH1 0000 ARPC NOP AR ← 0 0001
FETCH2 0001 DRM PCIN DR ← E0H, PC ← 1 0010
FETCH3 0010 AIDR NOP IR ← 1110, AR ← 20H 0110
MVAC1 0110 NOP RAC R ← 01H 0000
MOVR FETCH1 0000 ARPC NOP AR ← 1 0001
FETCH2 0001 DRM PCIN DR ← F0H, PC ← 2 0010
FETCH3 0010 AIDR NOP IR ← 1111, AR ← 30H 0111
MOVR1 0111 NOP ACR AC ← 01H 0000
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 66
12. The modifications are the same as in problem 10 with the following exceptions.
i) Add control signals RLOAD, RBUS, ACBUS, and ALUS2 to the control signals in microcode memory.
Set them to 0 for all microinstructions except those at addresses 0110 and 0111.
ii) Add the following to microcode memory.
State Address S
E
L
A
R
L
O
A
D
P
C
L
O
A
D
P
C
I
N
C
D
M
R
A
C
L
O
A
D
A
C
I
N
C
I
R
L
O
A
D
A
L
U
S
E
L
P
C
B
U
S
D
R
B
U
S
R
L
O
A
D
R
B
U
S
P
C
B
U
S
A
L
U
S
2
ADDR
MVAC1 0110 (6) 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0000
MOVR1 0111 (7) 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0000
Verification: Test program: 0: MVAC (Initially AC = 1)
1: MOVR
Instruction State Address Control Signals Operations performed Next Address
MVAC FETCH1 0000 PCBUS, ARLOAD AR ← 0 0001
FETCH2 0001 READ, MEMBUS,
DRLOAD, PCINC
DR ← E0H, PC ← 1 0010
FETCH3 0010 DRBUS, ARLOAD,
IRLOAD
IR ← 1110, AR ← 20H 0110
MVAC1 0110 ACBUS, RLOAD R ← 01H 0000
MOVR FETCH1 0000 ARPC AR ← 1 0001
FETCH2 0001 DRM, PCIN DR ← F0H, PC ← 2 0010
FETCH3 0010 AIDR IR ← 1111, AR ← 30H 0111
MOVR1 0111 RBUS, ACLOAD,
ALUS2
AC ← 01H 0000
13. Some points that might be included:
• The mapping hardware change is equivalent to changing the inputs to the counter in the hardwired
controller.
• The changes in the state diagram and register hardware are the same for either control unit.
• The microcode may require less hardware changes in the control unit than the hardwired control unit,
especially if no new micro-operations are needed.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 67
14. Modified state diagram and RTL code: (same as for problem 6.19)
SETR1: R ← 0
SETR2: R ← R - 1
Register and ALU modifications: (same as for problem 6.20)
R needs two additional inputs: CLR, driven by new control signal RCLR, and DCR, driven by new control
signal RDCR. There are no ALU modifications.
Microcode and microsequencer modifications:
i) Add micro-operations CLRR (R ← 0) and DECR (R ← R - 1) to the microcode. These fields are set to
zero for all existing microinstructions.
ii) Change the mapping function to (IR
4
∨ IR
3
),(IR
4
∨ IR
2
),(IR
4
∨ IR
1
), (IR
4
∨ IR
0
),IR
4
,0.
iii) Add the following microinstructions to the microprogram.
State Address Condition BT All other micro-operations CLRR DECR ADDR
SETR1 62 1 J 0 1 0 63
SETR2 63 1 J 0 0 1 1
Verification: Test program: 0: SETR
Instruction State Active signals Operations performed Next state
SETR FETCH1 PCBUS, ARLOAD AR ← 0 FETCH2
FETCH2 READ, MEMBUS,
DRLOAD, PCINC
DR ← 10H, PC ← 1 FETCH3
FETCH3 DRBUS, ARLOAD,
IRLOAD
IR ← 10H, AR ← 01H SETR1
SETR1 CLRR R ← 00H SETR2
SETR2 DECR R ← FFH FETCH1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 68
15. Modified state diagram and RTL code: (same as for problem 6.23)
ADDB1: AC ← AC + B
SUBB1: AC ← AC - B
ANDB1: AC ← AC ^ B
ORB1: AC ← AC ∨ B
XORB1: AC ← AC ⊕ B
Register and ALU modifications: (same as for problem 6.24)
i.) No ALU changes are needed!
ii) Register B is added to the CPU. It sends data to the bus through tri-state buffers but does not receive
data from the bus (since it is never loaded). This is shown below.
Microcode and microsequencer modifications:
i) Add micro-operations BPLU (AC ← AC + B), BMIN (AC ← AC - B), BAND (AC ← AC ^ B),
BOR (AC ← AC ∨ B), and BXOR (AC ← AC ⊕ B) to the microcode. These fields are set to
zero for all existing microinstructions.
ii) Change the mapping function to IR
3
,IR
2
,IR
1
,IR
0
,0,IR
4
.
iii) Change ALUS[1..7] such that ADD1 is replaced by ADD1 ∨ ADDB1, and so on for SUB1, AND1,
OR1, and XOR1, yielding:
ALUS1 = ADD1 ∨ ADDB1 ∨ SUB1 ∨ SUBB1 ∨ INAC1
ALUS2 = SUB1 ∨ SUBB1
ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1∨ ADDB1
ALUS4 = SUB1 ∨ SUBB1∨ INAC1
ALUS5 = XOR1 ∨ XORB1 ∨ NOT1
ALUS6 = OR1 ∨ ORB1 ∨ NOT1
ALUS7 = AND1 ∨ ANDB1 ∨ OR1 ∨ ORB1 ∨ XOR1 ∨ XORB1 ∨ NOT1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 69
iv) Add the following microinstructions to the microprogram.
State Address Cond. BT All other
µ µ-ops
BPLU BMIN BAND BOR BXOR ADDR
ADDB1 33 1 J 0 1 0 0 0 0 1
SUBB1 37 1 J 0 0 1 0 0 0 1
ANDB1 49 1 J 0 0 0 1 0 0 1
ORB1 53 1 J 0 0 0 0 1 0 1
XORB1 57 1 J 0 0 0 0 0 1 1
Verification: Test program shown below. Fetch cycles not shown
Instruction State Micro-operations Operations performed
ORB ORB1 BOR AC ← 1 ∨ 2 = 3
ADDB ADDB1 BPLU AC ← 3 + 2 = 5
ANDB ANDB1 BAND AC ← 5 ^ 2 = 0
XORB XORB1 BXOR AC ← 0 ⊕ 2 = 2
SUBB SUBB1 BMIN AC ← 2 - 2 = 0
16.
PCLOAD = PCDT RBUS = ACR ∨ PLUS ∨ MINU ∨ AND ∨ OR ∨ XOR
TRLOAD = TRDR ALUS1 = PLUS ∨ MINU ∨ ACIN
PCBUS = ARPC ALUS2 = MINU
DRHBUS = ARDT ∨ PCDT ALUS3 = ACDR ∨ ACR ∨ PLUS
DRLBUS = ACDR ∨ MDR ALUS4 = MINU ∨ ACIN
ACBUS = DRAC ∨ RAC ALUS5 = XOR ∨ NOT
READ = DRM ALUS6 = OR ∨ NOT
WRITE = MDR ALUS7 = AND ∨ OR ∨ XOR ∨ NOT
MEMBUS
BUSMEM
= DRM
= MDR
ACLOAD = ACDR ∨ ACR ∨ PLUS ∨ MINU ∨ ACIN ∨ ACZO ∨
AND ∨ OR ∨ XOR ∨ NOT
17. The subroutine now consists only of its last two instructions:
State A
d
d
r
e
s
s
C
o
n
d
i
t
i
o
n
B
T
A
R
P
C
A
R
I
N
A
R
D
T
P
C
I
N
P
C
D
T
D
R
M
D
R
A
C
I
R
D
R
R
A
C
Z
A
L
U
T
R
D
R
A
C
D
R
A
C
R
P
L
U
S
M
I
N
U
A
C
I
N
A
C
Z
O
A
N
D
O
R
X
O
R
N
O
T
M
D
R
A
D
D
R
SUB1 61 1 J 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 62
SUB2 62 1 R 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 70
18. i) The microsequencer is the same as shown in Figure 7.8, except the micro-operations fields are input to
decoders which generate the micro-operations.
ii) From the microcode of Table 7.17, the following groups of micro-operations must occur
simultaneously at least once, and therefore must be located in different fields:
• PCIN, DRM, and ARIN
• ARPC, and IRDR
• PCIN, DRM, and TRDR
• ZALU, and each of the arithmetic and logic micro-operations (PLUS, MINU, ACIN, ACZO,
AND, OR, XOR, and NOT)
iii) Since some microinstructions (such as NOP1) perform no micro-operations, each field requires a NOP.
One possible partitioning of the micro-operations, and its resultant microcode, are shown below.
M1 M2 M3
NOP PLUS NOP NOP
TRDR MINU PCIN DRM
ARIN ACIN IRDR
ARPC ACZO ZALU
ARDT AND ACDR
PCDT OR ACR
DRAC XOR MDR
RAC NOT
State A
d
d
r
e
s
s
C
o
n
d
i
t
i
o
n
B
T
M1 M2 M3 A
D
D
R
State A
d
d
r
e
s
s
C
o
n
d
i
t
i
o
n
B
T
M1 M2 M3 A
D
D
R
FETCH1 1 1 J ARPC NOP NOP 2 JMPZ1 24 Z′ J NOP NOP NOP 41
FETCH2 2 1 J NOP PCIN DRM 3 JMPZY1 25 1 J ARIN NOP DRM 26
FETCH3 3 X M ARPC IRDR NOP X JMPZY2 26 1 J TRDR NOP DRM 27
NOP1 0 1 J NOP NOP NOP 1 JMPZY3 27 1 J PCDT NOP NOP 1
LDAC1 4 1 J ARIN PCIN DRM 5 JMPZN1 41 1 J NOP PCIN NOP 42
LDAC2 5 1 J TRDR PCIN DRM 6 JMPZN2 42 1 J NOP PCIN NOP 1
LDAC3 6 1 J ARDT NOP NOP 7 JPNZ1 28 Z J NOP NOP NOP 45
LDAC4 7 1 J NOP NOP DRM 33 JPNZY1 29 1 J ARIN NOP DRM 30
LDAC5 33 1 J NOP ACRD NOP 1 JPNZY2 30 1 J TRDR NOP DRM 31
STAC1 8 1 J ARIN PCIN DRM 9 JPNZY3 31 1 J PCDT NOP NOP 1
STAC2 9 1 J TRDR PCIN DRM 10 JPNZN1 45 1 J NOP PCIN NOP 46
STAC3 10 1 J ARDT NOP NOP 11 JPNZN2 46 1 J NOP PCIN NOP 1
STAC4 11 1 J DRAC NOP NOP 34 ADD1 32 1 J PLUS ZALU NOP 1
STAC5 34 1 J NOP MDR NOP 1 SUB1 36 1 J MINU ZALU NOP 1
MVAC1 12 1 J NOP NOP NOP 1 INAC1 40 1 J ACIN ZALU NOP 1
MOVR1 16 1 J NOP NOP NOP 1 CLAC1 44 1 J ACCL ZALU NOP 1
JUMP1 20 1 J ARIN NOP DRM 21 AND1 48 1 J AND ZALU NOP 1
JUMP2 21 1 J TRDR NOP DRM 22 OR1 52 1 J OR ZALU NOP 1
JUMP3 22 1 J PCDT NOP NOP 1 XOR1 56 1 J XOR ZALU NOP 1
NOT1 60 1 J NOT ZALU NOP 1
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 71
19. The microsequencer is the same as shown in Figure 7.8, except the micro-operations fields outputs the
control signals directly, as shown in the following table.
State Address Condition BT Active control signals ADDR
FETCH1 1 1 J ARLOAD, PCBUS 2
FETCH2 2 1 J PCINC, DRLOAD, MEMBUS, READ 3
FETCH3 3 X M ARLOAD, IRLOAD, PCBUS X
NOP1 0 1 J None 1
LDAC1 4 1 J ARINC, PCINC, DRLOAD, MEMBUS, READ 5
LDAC2 5 1 J PCINC, DRLOAD, TRLOAD, MEMBUS, READ 6
LDAC3 6 1 J ARLOAD, DRHBUS, TRBUS 7
LDAC4 7 1 J DRLOAD, MEMBUS, READ 33
LDAC5 33 1 J ACLOAD, ALUS3, DRLBUS 1
STAC1 8 1 J ARINC, PCINC, DRLOAD, MEMBUS, READ 9
STAC2 9 1 J PCINC, DRLOAD, TRLOAD, MEMBUS, READ 10
STAC3 10 1 J ARLOAD, DRHBUS, TRBUS 11
STAC4 11 1 J DRLOAD, ACBUS 34
STAC5 34 1 J DRLBUS, BUSMEM, WRITE 1
MVAC1 12 1 J RLOAD, ACBUS 1
MOVR1 16 1 J ACLOAD, ALUS3, RBUS 1
JUMP1 20 1 J ARINC, DRLOAD, MEMBUS, READ 21
JUMP2 21 1 J DRLOAD, TRLOAD, MEMBUS, READ 22
JUMP3 22 1 J PCLOAD, DRHBUS, TRBUS 1
JMPZ1 24 Z′ J None 41
JMPZY1 25 1 J ARINC, DRLOAD, MEMBUS, READ 26
JMPZY2 26 1 J DRLOAD, TRLOAD, MEMBUS, READ 27
JMPZY3 27 1 J PCLOAD, DRHBUS, TRBUS 1
JMPZN1 41 1 J PCINC 42
JMPZN2 42 1 J PCINC 1
JPNZ1 28 Z J None 45
JPNZY1 29 1 J ARINC, DRLOAD, MEMBUS, READ 30
JPNZY2 30 1 J DRLOAD, TRLOAD, MEMBUS, READ 31
JPNZY3 31 1 J PCLOAD, DRHBUS, TRBUS 1
JPNZN1 45 1 J PCINC 46
JPNZN2 46 1 J PCINC 1
ADD1 32 1 J ACLOAD, ZALU, ALUS1, ALUS3, RBUS 1
SUB1 36 1 J ACLOAD, ZALU, ALUS1, ALUS2, ALUS4, RBUS 1
INAC1 40 1 J ACLOAD, ZALU, ALUS1, ALUS4 1
CLAC1 44 1 J ACLOAD, ZALU 1
AND1 48 1 J ACLOAD, ZALU, ALUS7, RBUS 1
OR1 52 1 J ACLOAD, ZALU, ALUS6, ALUS7, RBUS 1
XOR1 56 1 J ACLOAD, ZALU, ALUS5, ALUS7, RBUS 1
NOT1 60 1 J ACLOAD, ZALU, ALUS5, ALUS6, ALUS7 1
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 72
20. This solution is the same as for Problem 6.18. The student can execute the following program using the
Relatively Simple CPU simulator to verify that each instruction performs properly.
0: LDAC 0000 (AC ← 1)
NOP
MVAC (R ← 1)
ADD (AC ← 2, Z ← 0)
INAC (AC ← 3, Z ← 0)
XOR (AC ← 2, Z ← 0)
AND (AC ← 0, Z ← 1)
9: JMPZ 000D (jump is taken)
NOP (skipped by JMPZ 000D)
D: JPNZ 0009 (jump is not taken)
NOT (AC ← FF, Z ← 0)
JMPZ 0009 (jump is not taken)
JPNZ 0018 (jump is taken)
NOP (skipped by JMPZ 0018)
18: CLAC (AC ← 0, Z ← 1)
OR (AC ← 1, Z ← 0)
SUB (AC ← 0, Z ← 1)
MOVR (AC ← 1)
STAC 0030 (M[30] ← 1)
AND (AC ← 1, Z ← 0)
JUMP 0000 (start again)
21. The state diagram, RTL code, register section, and ALU are the same as for Problem 6.28.
State diagram and RTL code:
FETCH1: AR ← PC
FETCH2: DR ← M, PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
COM1: AC ← AC'
JREL1: DR ← M
JREL2: PC ← PC + DR[5..0]
OR1: DR ← M
OR2: AC ← AC ∨ DR
SUB11: DR ← M
SUB12: AC ← AC + DR'
The register section is the same as Figure 6.6, except for the data input to PC, shown below.
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Control signals: ARLOAD =FETCH1 ∨ FETCH3
PCLOAD =JREL2
PCINC =FETCH2
PCBUS =FETCH1
DRLOAD = MEMBUS = READ =FETCH2 ∨ JREL1∨ OR1∨ SUB11
DRBUS =FETCH3 ∨ JREL2 ∨ OR2 ∨ SUB12
ACLOAD =COM1 ∨ OR2 ∨ SUB12
IRLOAD =FETCH3
ALU:
The microsequencer hardware is the same as shown in Figures 7.3 and 7.4, except the micro-operations are
replaced by control signals.
Microcode:
State Address S
E
L
A
R
L
O
A
D
P
C
L
O
A
D
P
C
I
N
C
P
C
B
U
S
D
M
R
D
R
B
U
S
A
C
L
O
A
D
I
R
L
O
A
D
A
L
U
S
1
A
L
U
S
2
ADDR
FETCH1 0000 (0) 0 1 0 0 1 0 0 0 0 0 0 0001
FETCH2 0001 (1) 0 0 0 1 0 1 0 0 0 0 0 0010
FETCH3 0010 (2) 1 1 0 0 0 0 1 0 1 0 0 XXXX
COM1 1000 (8) 0 0 0 0 0 0 0 1 0 0 0 0000
JREL1 1010 (10) 0 0 0 0 0 1 0 0 0 0 0 1011
JREL2 1011 (11) 0 0 1 0 0 0 1 0 0 0 0 0000
OR1 1100 (12) 0 0 0 0 0 1 0 0 0 0 0 1101
OR2 1101 (13) 0 0 0 0 0 0 1 1 0 1 0 0000
SUB11 1110 (14) 0 0 0 0 0 1 0 0 0 0 0 1111
SUB12 1111 (15) 0 0 0 0 0 0 1 1 0 0 1 0000
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22. The state diagram, RTL code, register section, and ALU are the same as for Problem 6.29.
State diagram and RTL code:
FETCH1: AR ← PC ADD1: DR ← M, PC ← PC + 1
FETCH2: DR ← M, PC ← PC + 1 ADD2: AC ← AC + DR
FETCH3: IR ← DR[7..5], AR ← PC OR1: DR ← M, PC ← PC + 1
LDI1: DR ← M, PC ← PC + 1 OR2: AC ← AC ∨ DR
LDI2: AC ← DR JUMP1: DR ← M
STO1: DR ← M, PC ← PC + 1 JUMP2: PC ← DR
STO2: AR ← DR JREL1: PC ← PC + 000DR[4..0]
STO3: DR ← AC SKIP1: PC ← PC + 1
STO4: M ← DR RST1: PC ← 0, AC ← 0
Control signals: ARLOAD =FETCH1 ∨ FETCH3 ∨ STO2
PCLOAD =JUMP2 ∨ JREL2
PCINC =FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ SKIP1
PCCLR =RST1
PCBUS =FETCH1 ∨ FETCH3
PCMUX =JUMP2
DRLOAD =FETCH2 ∨ LDI1 ∨ STO1 ∨ STO3 ∨ ADD1 ∨ OR1 ∨ JUMP1
DRBUS =FETCH3 ∨ LDI2 ∨ STO2 ∨ STO4 ∨ ADD2 ∨ OR2 ∨ JUMP2 ∨ JREL1
ACLOAD =LDI2 ∨ ADD2 ∨ OR2
ACCLR =RST1
ACBUS =STO3
IRLOAD =FETCH3
MEMBUS = READ =FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ JUMP1
BUSMEM = WRITE =STO4
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Register section:
ALU:
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The microsequencer hardware is the same as shown in Figures 7.3 and 7.4, except the micro-operations are
output to decoders to generate the actual micro-operation signals, and the mapping function is 1,IR[2..0],0.
Micro-operation field assignments:
M1 M2
0 NOP 0 NOP
1 AR ← PC 1 IR ← DR[7..5]
2 DR ← M 2 PC ← PC + 1
3 AC ← DR 3 PC ← 0
4 AR ← DR 4 PC ← DR
5 DR ← AC 5 PC ← PC + 000DR[4..0]
6 M ← DR 6 AC ← AC + DR
7 AC ← 0 7 AC ← AC ∨ DR
Microcode:
State Address SEL M1 M2 ADDR
FETCH1 00000 0 001 000 00001
FETCH2 00001 0 101 010 00010
FETCH3 00010 1 001 001 XXXX
STO3 00100 0 101 000 00101
STO4 00101 0 110 000 00000
LDI1 10000 0 010 010 10001
LDI2 10001 0 011 000 00000
STO1 10010 0 010 010 10011
STO2 10011 0 100 000 00100
ADD1 10100 0 010 010 10101
ADD2 10101 0 000 110 00000
OR1 10110 0 010 010 10111
OR2 10111 0 000 111 00000
JUMP1 11000 0 010 000 11001
JUMP2 11001 0 000 100 00000
JREL1 11010 0 000 101 00000
SKIP1 11100 0 000 010 00000
RST1 11110 0 111 011 00000
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23. The state diagram, RTL code, and register section are the same as in Problem 6.30.
Modified state diagram:
Modified RTL code:
LDSP1: DR ← M, AR ← AR + 1, PC ← PC + 1 PUSHAC1: SP ← SP - 1, DR ← AC
LDSP2: TR ← DR, DR ← M, PC ← PC + 1 PUSHAC2: AR ← SP
LDSP3: SP ← DR,TR PUSHAC3: M ← DR
CALL1: DR ← M, AR ← AR + 1, PC ← PC + 1 POPAC1: AR ← SP
CALL2: TR ← DR, DR ← M, PC ← PC + 1 POPAC2: DR ← M, SP ← SP + 1
CALL3: TR2 ← DR, DR ← PC[15..8], SP ← SP - 1 POPAC3: AC ← DR
CALL4: AR ← SP PUSHR1: SP ← SP - 1, DR ← R
CALL5: M ← DR, AR ← AR - 1, SP ← SP - 1 PUSHR2: AR ← SP
CALL6: DR ← PC[7..0] PUSHR3: M ← DR
CALL7: M ← DR POPR1: AR ← SP
CALL8: PC ← TR2,DR POPR2: DR ← M, SP ← SP + 1
RET1: AR ← SP POPR3: R ← DR
RET2: DR ← M, SP ← SP + 1, AR ← AR + 1
RET3: TR ← DR, DR ← M, SP ← SP + 1
RET4: PC ← DR,TR
Modified register section: (shown below)
• New registers: SP (with LD, DEC, INC), TR2 (with LD, receives data directly from DR)
• New control signal: AR adds a DEC signal
• New data path: DR can receive data from BUS[15..8] or BUS[7..0]
• All other connections remain the same as shown in Figure 6.15.
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New micro-operations:
SPDT: SP ← DR,TR DRPL: DR ← PC[7..0]
T2DR: TR2 ← DR PCTR: PC ← TR2,TR
DRPH: DR ← PC[15..8] SPIN: SP ← SP + 1
SPDC: SP ← SP - 1 DRR: DR ← R
ARSP: AR ← SP RDR: R ← DR
ARDC: AR ← AR - 1
New mapping function: IR[7,3..0]00 (The extra MSB in ADDR is 0 for all current instructions.)
ARDEC = ARDC
SPLOAD = SPDT
SPINC = SPIN
SPDEC = SPDC
SPBUS = ARSP
DRSEL = DRPH
TR2LOAD = T2DR
TR2BUS = PCTR
Modified control signals:
ARLOAD = (original value) ∨ ARSP
ARINC = (original value) ∨ PCTR
PCLOAD = (original value) ∨ DRPH ∨ DRPL ∨ DRR
DRLOAD = (original value) ∨ DRPH ∨ DRPL ∨ DRR
DRHBUS = (original value) ∨ SPDT
DRLBUS = (original value) ∨ T2DR ∨ RDR
TRLOAD = (original value) ∨ LDSP2 ∨ CALL2 ∨ RET3
TRBUS = (original value) ∨ PCTR
RLOAD = (original value) ∨ RDR
RBUS = (original value) ∨ DRR
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New microinstructions:
State Address SEL Micro-operations ADDR
LDSP1 100 0000 0 DRM, ARIN, PCIN 100 0001
LDSP2 100 0001 0 TRDR, DRM, PCIN 100 0010
LDSP3 100 0010 0 SPDT 000 0001
CALL1 100 1000 0 DRM, ARIN, PCIN 100 1001
CALL2 100 1001 0 TRDR, DRM, PCIN 100 1010
CALL3 100 1010 0 T2DR, DRPH, SPDC 100 1011
CALL4 100 1011 0 ARSP 100 0100
CALL5 100 0100 0 MDR, ARDC, SPDC 100 0101
CALL6 100 0101 0 DRPL 100 0110
CALL7 100 0110 0 MDR 100 0111
CALL8 100 0111 0 PCTR 000 0001
RET1 100 1100 0 ARSP 100 1101
RET2 100 1101 0 DRM, SPIN, ARIN 100 1110
RET3 100 1110 0 TRDR, DRM, SPIN 100 1111
RET4 100 1111 0 PCDT 000 0001
PUSHAC1 101 0000 0 SPDC, DRAC 101 0001
PUSHAC2 101 0001 0 ARSP 101 0010
PUSHAC3 101 0010 0 MDR 000 0001
POPAC1 101 0100 0 ARSP 101 0101
POPAC2 101 0101 0 DRM, SPIN 101 0110
POPAC3 101 0110 0 ACDR 000 0001
PUSHR1 101 1000 0 SPDC, DRR 101 1001
PUSHR2 101 1001 0 ARSP 101 1010
PUSHR3 101 1010 0 MDR 000 0001
POPR1 101 1100 0 ARSP 101 1101
POPR2 101 1101 0 DRM, SPIN 101 1110
POPR3 101 1110 0 RDR 000 0001
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Chapter 8
1. a)
64 = 01000000 64' = 1100 0000
b)
33 = 0010 0001 33' = 1101 1111
c)
-1 = 1111 1111 -1' = 0000 0001
2.
Non-negative Unsigned two's-complement
a)
29 = 0001 1101 0001 1101
b)
-128 = N/A 1000 0000
c)
199 = 1100 0111 N/A
3.
Signed-Magnitude Signed-Two's Complement
a)
-63 = 1011 1111 1100 0001
b)
147 = N/A N/A
c)
85 = 0101 0101 0101 0101
4. a)
0011 1101 (180 - 119 = 61)
b)
N/A (56 + 205 = 261, overflow)
c)
1111 1111 (139 + 116 = 255)
d)
N/A (116 - 139 = -23, negative number)
5. a)
N/A (-76 - 119 = -193, overflow)
b)
0000 0101 (56 + -51 = 5)
c)
1111 1111 (-117 + 116 = -1)
d)
N/A (116 - -117 = 233, overflow)
6. The worst cases are +127 + (-1) = +126 and +0 + (-128) = -128, both of which produce valid results.
7.
Conditions Micro-operations i C U V Y Z FINISH
START x x xxxx xxxx 1110 0
1 U ← 0, i ← 4 4 0000 0
2 i ← i - 1 3 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0000 0xxx 0111
Y
0
2,2 CU ← U + X, i ← i - 1 2 0 1001 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0100 10xx 1011
Y
0
2,2 CU ← U + X, i ← i - 1 1 0 1101 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0110 110x 1101
Y
0
2,2 CU ← U + X, i ← i - 1 0 0 1111 1
3,Z3 shr(CUV), cir(Y), FINISH ← 1 0 0111 1110 1110 1
Result: 9 * 14 = 126, or 1001 * 1110 = 0111 1110
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8.
Conditions Micro-operations i C U V Z FINISH
START x x xxxx 1110 0
1 U ← 0, i ← 4 4 0000 0
2 i ← i - 1 3 0
3,Z´3 shr(CUV), goto 2 0 0000 0111
V
0
2,2 CU ← U + X, i ← i - 1 2 0 1001 0
3,Z´3 shr(CUV), goto 2 0 0100 1011
V
0
2,2 CU ← U + X, i ← i - 1 1 0 1101 0
3,Z´3 shr(CUV), goto 2 0 0110 1101
V
0
2,2 CU ← U + X, i ← i - 1 0 0 1111 1
3,Z3 shr(CUV), FINISH ← 1 0 0111 1110 1
Result: 9 * 14 = 126, or 1001 * 1110 = 0111 1110
9.
Conditions Micro-operations i U V Y Y
-1
Z FINISH
START x xxxx xxxx 1011 x 0
1 U ← 0, Y
-1
← 0, i ← 4 4 0000 0 0
Y
0
Y
-1
´2,2 U ← U + X′ + 1, i ← i – 1 3 1010 0
3,Z´3 ashr(UV), cir(Y), Y
-1
← Y
0
, goto 2 1101 0xxx 1101 1
2 i ← i – 1 2 0
3,Z´3 ashr(UV), cir(Y), Y
-1
← Y
0
, goto 2 1110 10xx 1110 1
Y
0
´Y
-1
2,2 U ← U + X, i ← i – 1 1 0100 0
3,Z´3 ashr(UV), cir(Y), Y
-1
← Y
0
, goto 2 0010 010x 0111 0
Y
0
Y
-1
´2,2 U ← U + X′ + 1, i ← i – 1 0 1100 1
3,Z3 ashr(UV), cir(Y), Y
-1
← Y
0
, FINISH ← 1 1110 0010 1011 1
Result: 6 * -5 = -30, or 0110 * 1011 = 1110 0010
10.
1:U ← 0, V
-1
← 0, i ← n
V
0

-1
2:U ← U + X′ + 1

0
V
-1
2:U ← U + X
2:i ← i – 1
3:ashr(UVV
-1
)
Z´3:goto 2
Z3:FINISH ← 1
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11.
Conditions Micro-operations i C U V Y Z OVERFLOW FINISH
START x x 0110 1011 xxxx 0
1
1 CU ← U + X′ + 1 0 1100
1
2 U ← U + X 0110
2 Y ← 0, OVERFLOW ← 0, i ← 4 4 0000 0 0
3 shl CUV, shl Y, i ← i – 1 3 0 1101 0110 0000 0
C´4
1 CU ← U + X′ + 1 1 0011
C4
2
,Z´4
2 Y
0
← 1, goto 3 0001
3 shl CUV, shl Y, i ← i – 1 2 0 0110 1100 0010 0
C´4
1 CU ← U + X′ + 1 0 1100
C´4
2
,Z´4
2 U ← U + X, goto 3 0 0110
3 shl CUV, shl Y, i ← i – 1 1 0 1101 1000 0100 0
C´4
1 CU ← U + X′ + 1 1 0011
C4
2
,Z´4
2 Y
0
← 1, goto 3 0101
3 shl CUV, shl Y, i ← i – 1 0 0 0111 0000 1010 1
C´4
1 CU ← U + X′ + 1 0 1101
C´4
2
,Z4
2 U ← U + X, FINISH ← 1 0111 1
Result: 107 ÷ 10 = 10 R 7, or 0110 1011 ÷ 1010 = 1010 R 0111
12.
Conditions Micro-operations i C U V Y Z FINISH
START x x 0110 1011 xxxx 0
1 NONE
2 Y ← 0, C ← 0,
OVERFLOW ← 0, i ← 4
4 0 0000 0
3 shl CUV, shl Y, i ← i – 1 3 0 1101 0110 0000 0
(C + G)4,Z´4 Y
0
← 1, U ← U + X′ + 1,
goto 3
0011 0001
3 shl CUV, shl Y, i ← i – 1 2 0 0110 1100 0010 0
Z´4 goto 3
3 shl CUV, shl Y, i ← i – 1 1 0 1101 1000 0100 0
(C + G)4,Z´4 Y
0
← 1, U ← U + X′ + 1,
goto 3
0011 0101
3 shl CUV, shl Y, i ← i – 1 0 0 0111 0000 1010 1
Z4 FINISH ← 1 1
Result: 107 ÷ 10 = 10 R 7, or 0110 1011 ÷ 1010 = 1010 R 0111
13.
1:OVERFLOW ← G
G1:FINISH ← 1
2:Y ← 0, C ← 0, i ← n
3:shl CUV, shl Y, i ← i – 1
(C + G)4:Y
0
← 1, U ← U + X′ + 1
Z´4:goto 3
Z 4:FINISH ← 1
(Only 1, G1, and 2, and the OVERFLOW hardware are changed; the rest is the same as in the chapter.)
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14.
1
1
: CU ← U + X′ + 1
1
2
: U ← U + X, OVERFLOW ← C
C1
2
: FINISH ← 1
2: Y ← 0, i ← n
3: shl CUV, shl Y, i ← i – 1
C4
1
: U ← U + X′ + 1
C´4
1
: CU ← U + X′ + 1
C4
2
: Y
0
← 1
C´4
2
: U ← U + X
Z 4
2
: FINISH ← 1
Z´4
2
: goto 3
(Only 1
2
, and 2, and the OVERFLOW hardware are changed; the rest is the same as in the chapter.)
15.
1
0
:NU ← U
n-1
, NX ← X
n-1
U
n-1
1
0
:UV ← (UV)' + 1
X
n-1
1
0
:X ← X' + 1
G1:FINISH ← 1, OVERFLOW ← 1
NUG1:UV ← (UV)' + 1
NXG1:X ← X' + 1
2:Y ← 0, C ← 0, OVERFLOW ← 0, i ← n
3:shl CUV, shl Y, i ← i – 1
(C + G)4:Y
0
← 1, U ← CU + X′ + 1
Z´4:goto 3
(NU⊕NX)5:Y ← Y' + 1, U ← U' + 1
NX5:X ← X' + 1
5:FINISH ← 1
16.
1
0
:NU ← U
n-1
, NX ← X
n-1
U
n-1
1
0
:UV ← (UV)' + 1
X
n-1
1
0
:X ← X' + 1
1
1
:CU ← U + X′ + 1
1
2
:U ← U + X
C1
2
:FINISH ← 1, OVERFLOW ← 1
NUC1
2
:UV ← (UV)' + 1
NXC1
2
:X ← X' + 1
2:Y ← 0, C ← 0, OVERFLOW ← 0, i ← n
3:shl CUV, shl Y, i ← i – 1
C4
1
:U ← U + X′ + 1
C´4
1
:CU ← U + X′ + 1
C4
2
:Y
0
← 1
C´4
2
:U ← U + X
Z´4
2
:goto 3
(NU⊕NX)5:Y ← Y' + 1, U ← U' + 1
NX5:X ← X' + 1
5:FINISH ← 1
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17. a) PM1: CU ← 0 1110, OVERFLOW ← 0 b) PM´1: U
s
← 0, CU ← 1 0000
C´PM2,2: U
s
← 1, U ← 0010, FINISH ← 1 PM´2,2: OVERFLOW ← 1, FINISH ← 1
Result: U
s
U = 1 0010 = -2 Result: Overflow
c)
PM1: CU ← 0 1110, OVERFLOW ← 0
d)
PM´1: U
s
← 0, CU ← 1 0000
C´PM2,2: U
s
← 0, U ← 0010, FINISH ← 1 PM´2,2: OVERFLOW ← 1, FINISH ← 1
Result: U
s
U = 0 0010 = +2 Result: Overflow
18.
PM´1:U
s
← X
s
, CU ← X + Y
PM1:CU ← X + Y′ + 1, OVERFLOW ← 0
CZ´PM2:U
s
← X
s
CZPM2:U
s
← 0
C´PM2:U
s
← X
s
′, U ← U′ + 1
2:OVERFLOW ← PM' ^ C, FINISH ← 1
(Only PM1, PM'2 (deleted), and 2, and the OVERFLOW hardware are changed; the rest is the same as in the
chapter.)
19. a)
Conditions Micro-operations i C U V Y Z FINISH
START x x xxxx xxxx 1001 0
1 U
s
← 1, V
s
← 1, U ← 0, i ← 4 4 0000 0
Y
0
2,2 CU ← U + X, i ← i - 1 3 0 0111 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0011 1xxx 1100
2 i ← i - 1 2 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0001 11xx 0110
2 i ← i - 1 1 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0000 111x 0011
Y
0
2,2 CU ← U + X, i ← i - 1 0 0 0111 1
3,Z3 shr(CUV), cir(Y), FINISH ← 1 0 0011 1111 1001 1
Result: +7 × -9 = -63, or 0 0111 × 1 1001 = 1 0011 1111
b)
Conditions Micro-operations i C U V Y Z FINISH
START x x xxxx xxxx 0000 0
1 U
s
← 1, V
s
← 1, U ← 0, i ← 4 4 0000 0
2 i ← i - 1 3 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0000 0xxx 0000
2 i ← i - 1 2 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0000 00xx 0000
2 i ← i - 1 1 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0000 000x 0000
2 i ← i - 1 0 0 0000 1
ZT3,3,Z3 U
s
← 0, V
s
← 0,
shr(CUV), cir(Y), FINISH ← 1
0 0000 0000 0000 1
Result: -13 × +0 = +0, or 1 1101 × 0 0000 = 0 0000 0000
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c)
Conditions Micro-operations i C U V Y Z FINISH
START x x xxxx xxxx 1111 0
1 U
s
← 0, V
s
← 0, U ← 0, i ← 4 4 0000 0
Y
0
2,2 CU ← U + X, i ← i - 1 3 0 1111 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 0111 1xxx 1111
Y
0
2,2 CU ← U + X, i ← i - 1 2 1 0110 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 1011 01xx 1111
Y
0
2,2 CU ← U + X, i ← i - 1 1 1 1010 0
3,Z´3 shr(CUV), cir(Y), goto 2 0 1101 001x 1111
Y
0
2,2 CU ← U + X, i ← i - 1 0 1 1100 1
3,Z3 shr(CUV), cir(Y), FINISH ← 1 0 1110 0001 1111 1
Result: +15 × +15 = +225, or 0 1111 × 0 1111 = 0 1110 0001
20.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 86
21. Add the following RTL statement. The rest of the algorithm is unchanged.
G'1: U
s
← U
s
⊕ X
s
, Y
s
← U
s
⊕ X
s
22. Add the following RTL statement. The rest of the algorithm is unchanged.
C'1
2
: U
s
← U
s
⊕ X
s
, Y
s
← U
s
⊕ X
s
23. a) PM1: CU ← 0 98, OVERFLOW ← 0 b) PM1: CU ← 0 64, OVERFLOW ← 0
C´PM2,2: U
s
← 1, U ← 02, FINISH ← 1 C´PM2,2: U
s
← 1, U ← 36, FINISH ← 1
Result: U
s
U = 1 02 = -2 Result: U
s
U = 1 36 = -36
c)
PM´1: CU ← 0 30
PM´2,2: U
s
← 0, OVERFLOW ← 0, FINISH ← 1
Result: U
s
U = 0 30 = +30
24. a)
Conditions Micro-operations i C
d
U V Y Z
Y0
Z FINISH
START x x xx xx 23 0 0
1 U
s
← 0, V
s
← 0,
U ← 00, i ← 2, C
d
← 0
2 0 00 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 17 22 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 34 21 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 51 20 1
Z
Y0
2 i ← i – 1 1 0
3,Z´3 dshr(C
d
UV), dshr(Y), goto 2 0 05 1x 02 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 22 01 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 39 00 1
Z
Y0
2 i ← i – 1 0 1
3,Z3 dshr(C
d
UV), dshr(Y),
FINISH ← 1
03 91 1
Result: +17 × +23 = +391
b)
Conditions Micro-operations i C
d
U V Y Z
Y0
Z FINISH
START x x xx xx 32 0 0
1 U
s
← 1, V
s
← 1,
U ← 00, i ← 2, C
d
← 0
2 0 00 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 71 31 0

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
1 42 30 1
Z
Y0
2 i ← i – 1 1 0
3,Z´3 dshr(C
d
UV), dshr(Y), goto 2 0 14 2x 03

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 85 02 0

Y0
2 C
d
U ← C
d
U + X, 1 56 01 0
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 87
Y
d0
← Y
d0
– 1, goto 2

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
2 27 00 1
Z
Y0
2 i ← i – 1 0 1
3,Z3 dshr(C
d
UV), dshr(Y),
FINISH ← 1
22 72 1
Result: +71× -32 = -2272
c)
Conditions Micro-operations i C
d
U V Y Z
Y0
Z FINISH
START x x xx xx 10 0 0
1 U
s
← 0, V
s
← 0,
U ← 00, i ← 2, C
d
← 0
2 0 00 0
Z
Y0
2 i ← i – 1 1 0
3,Z´3 dshr(C
d
UV), dshr(Y), goto 2 0 00 0x 01

Y0
2 C
d
U ← C
d
U + X,
Y
d0
← Y
d0
– 1, goto 2
0 39 00 1
Z
Y0
2 i ← i – 1 0 1
3,Z3 dshr(C
d
UV), dshr(Y),
FINISH ← 1
0 03 90 1
Result: -39× -10 = +390
25.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 88
26.
G'1:U
s
← U
s
⊕ X
s
, Y
s
← U
s
⊕ X
s
G1:FINISH ← 1, OVERFLOW ← 1
2:Y ← 0, C
d
← 0, OVERFLOW ← 0, i ← n
3:dshl C
d
UV, dshl Y, i ← i – 1
(Z'
cd
+ G)4:Y
0
← Y
0
+ 1, C
d
U ← C
d
U + X′ + 1, goto 4
Z
cd
G'Z'4:goto 3
Z
cd
G'Z4:FINISH ← 1
27.
1
1
:C
d
U ← C
d
U + X′ + 1 (Note: X′ + 1 = 967, not 67)
1
2
:U ← U + X
Z'
cd
1
2
:FINISH ← 1, OVERFLOW ← 1
Z
cd
1
2
:U
s
← U
s
⊕ X
s
, Y
s
← U
s
⊕ X
s
2:Y ← 0, OVERFLOW ← 0, i ← n
3:dshl C
d
UV, dshl Y, i ← i – 1
4
1
:CC
d
U ← C
d
U + X′ + 1
C4
2
:Y
0
← Y
0
+ 1, C
d
U ← C
d
U + X′ + 1, goto 4
2
C'4
2
:C
d
U ← C
d
U + X
Z'C'4
2
:goto 3
ZC'4
2
:FINISH ← 1
28. a) 20 ns
b) 2
20
15 10 15
1
·
+ +
· ·

k
T
T
S
c) n * 40 > 20 * (n + 2), which yields n > 2
d) 5 . 1
) 2 ( 2
40 *
·
+ n
n
, which yields n = 6
29.
Addresses xxx000 xxx001 xxx010 xxx011 xxx100 xxx101 xxx110 xxx111
0-7 0 0 0 0 0 0 0 0
8-15 0 1 2 3 4 5 6 7
16-23 0 2 4 6 8 10 12 14
24-31 0 3 6 9 12 15 18 21
32-39 0 4 8 12 16 20 24 28
40-47 0 5 10 15 20 25 30 35
48-55 0 6 12 18 24 30 36 42
56-63 0 7 14 21 28 35 42 49
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 89
30.
31.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 90
32.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 91
33. The following symbols are used in this design.
Condition Symbol Condition Symbol
(I
X
N'
Y
+ N
X
+ Z
Y
)1: 1 CPM´4: 9
(N'
Y
Z
X
Z'
Y
+ I'
X
I
Y
N'
X
)1: 2 C
E
PM´5: 10
(I
Y
N
X
+ N'
X
N
Y
)1: 3 PM´5: 11
E
XY
2: 4 C´PM4: 12
E
YX
2: 5 Z'
U
C'
E
U'
F(n-1)
PM5: 13
PM´3: 6 (Z
U
+ C
E
)PM 5: 14
PM3: 7 C'
E
U
F(n-1)
PM 5: 15
3: 8
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 92
Chapter 9
1. Mask: 1111 1111 0000 0000
Data: 1111 0000 xxxx xxxx
2. a) The fifth location from the top
b) The third, seventh, and eighth locations from the top
c) No locations match this criteria
3. a)
20 bit tag 16 bit data Valid bit 37 bits
b)
7 bit tag 16 bit data Valid bit 24 bits
c)
8 bit tag 16 bit data Valid bit 8 bit tag 16 bit data Valid bit 50 bits
Way 1 Way 2
d)
9 bit tag 16 bit data Valid
bit
9 bit tag 16 bit
data
Valid
bit
9 bit tag 16 bit
data
Valid
bit
9 bit tag 16 bit
data
Valid
bit
Way 1 Way 2 Way 3 Way 4
104 bits
4. a)
18 bit tag 8 bit data Valid bit 27 bits
b)
4 bit tag 8 bit data Valid bit 13 bits
c)
5 bit tag 8 bit data Valid bit 5 bit tag 8 bit data Valid bit 28 bits
Way 1 Way 2
d)
6 bit tag 8 bit data Valid
bit
6 bit tag 8 bit
data
Valid
bit
6 bit tag 8 bit
data
Valid
bit
6 bit tag 8 bit
data
Valid
bit
Way 1 Way 2 Way 3 Way 4
60 bits
5. a) 32 or 33 bits: 15 for the address tag
8 for the first data value
8 for the second data value
1 for the valid bit
1 for the dirty bit (only if the cache uses write-back)
b) Assuming the bits are ordered as listed in part a: 111 1111 1111 1111 0000 0000 0000 0000
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 93
6.
Only changes shown
Instruction Address bits Data 1 Data 2 Valid Comments
LDAC 4234 000 0000 0000 0000
000 0000 0000 0001
010 0001 0001 1010
01
42
55
34
0B
29
1
1
1
CLAC No changes Cache hit
JMPZ 000A 000 0000 0000 0010
000 0000 0000 0011
06
00
0A
05
1
1
INAC 000 0000 0000 0101 0A 03 1
MVAC No changes Cache hit
ADD 000 0000 0000 0110 08 02 1
STAC 0927
000 0000 0000 0111
000 0100 1001 0011
29
--
09
02
1
1
Cache hit
(opcode)
JUMP 0000 000 0000 0000 1000
000 0000 0000 1001
05
00
00
--
1
1
7.
Only changes shown
Instruction Address bits Tag Data Valid Dirty Comments
LDAC 4234 0
1
2
4
000
000
000
423
01
34
42
55
1
1
1
1
0
0
0
0
CLAC 3 000 0B 1 0
JMPZ 000A 4
5
6
000
000
000
06
0A
00
1
1
1
0
0
0
Replace data
INAC A 000 0A 1 0
MVAC B 000 03 1 0
ADD C 000 08 1 0
STAC 0927 D
E
F
7
000
000
000
092
02
27
09
02
1
1
1
1
0
0
0
1
JUMP 0000 0
1
2
001
001
001
05
00
00
1
1
1
1
1
1
Replace data
Replace data
Replace data
8.
Only changes shown
Instruction Address bits Tag Data 0 Data 1 Data 2 Data 3 Valid Dirty Comments
LDAC 4234 0
1
000
423
01
55
34
29
42
--
0B
--
1
1
0
0
CLAC No changes Cache hit
JMPZ 000A 1 000 06 0A 00 05 1 0 Replace data
INAC 2 000 00 00 0A 03 1 0
MVAC No changes Cache hit
ADD 3 000 08 02 27 09 1 0
STAC 0927
1 092 -- -- -- 02 1 1
Cache hit (instr)
Replace data
JUMP 0000 0 001 05 00 00 -- 1 0 Replace data
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 94
9.
Only changes shown
Instruction Address bits Tag 1 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments
LDAC 4234 0
1
2
4
000
000
000
423
01
34
42
55
1
1
1
1
0
0
0
0
CLAC 3 000 0B 1 0
JMPZ 000A 4
5
6
423
000
000
55
0A
00
1
1
1
0
0
0
000 06 1 0
INAC A 000 0A 1 0
MVAC B 000 03 1 0
ADD C 000 08 1 0
STAC 0927 D
E
F
7
000
000
000
092
02
27
09
02
1
1
1
1
0
0
0
1
JUMP 0000 0
1
2
000
000
000
01
34
42
1
1
1
0
0
0
001
001
001
05
00
00
1
1
1
0
0
0
10.
Only changes shown
Instruction Address bits Tag 1 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments
LDAC 4234 0
1
2
000
000
423
01/34
42/0B
55/29
1
1
1
0
0
0
CLAC No change Cache hit
JMPZ 000A 2
3
423
000
55/29
00/05
1
1
0
0
000 06/0A 1 0
INAC 5 000 0A/03 1 0
MVAC No change Cache hit
ADD 6 000 08/02 1 0
STAC 0927
7
3
000
000
27/09
00/05
1
1
0
0 092 --/02 1 1
Hit (instr)
JUMP 0000 0
1
000
000
01/34
42/0B
1
1
0
0
001
001
05/00
00/--
1
1
0
0
11.
Only changes shown Note: Both LRU and FIFO replacement policies replace the
same values for this program.
Instruction Address Tag1 Data1 Valid1 Dirty1 Tag2 Data2 Valid2 Dirty2 Comments
LDAC 4234 0
1
000
423
01/34/42/0B
55/29/--/--
1
1
0
0
CLAC No change Cache hit
JMPZ 000A 1 423 55/29/--/-- 1 0 000 06/0A/00/05 1 0
INAC 2 000 00/00/0A/03 1 0
MVAC No change Cache hit
ADD 3 000 08/02/27/09 1 0
STAC 0927
1
423 55/29/--/-- 1 0
092
--/--/--/02
1 1
Hit (instr)
Replace
JUMP 0000 0 000 01/34/42/0B 1 0 001 05/00/00/-- 1 0
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 95
12.
Hit ratio = 4.5%
Instruction Tag Data Valid Dirty Comments
LDAC 4234 0000
0001
0002
4234
01
34
42
55
1
1
1
1
0
0
0
0
STAC 4235 0003
0004
0005
4235
0B
35
42
55
1
1
1
1
0
0
0
1
MVAC 0006 03 1 0
INAC 0007 0A 1 0
ADD 0008 08 1 0
JPNZ 0020 0009
000A
000B
07
20
00
1
1
1
0
0
0
LDAC 4235 0020
0021
0022
4235
01
35
42
55
1
1
1
1
0
0
0
1 Cache hit
JUMP 0029 0023
0024
0025
05
29
00
1
1
1
0
0
0
AND 0029 0C 1 0
13.
Hits in italics Hit ratio = 40.9%
Instruction Tag Data Valid Dirty Comments
LDAC 4234 0000
0001
211A
01/34
42/0B
55/55
1
1
1
0
0
0
STAC 4235
0002
211A
35/42
55/55
1
1
0
1
Hit (instr)
Hit (4235)
MVAC 0003 03/0A 1 0
INAC Cache hit
ADD 0004 08/07 1 0
JPNZ 0020
0005 20/00 1
1
0
0
Hit (instr)
Hit (00)
LDAC 4235 0010
0011
211A
01/35
42/05
1
1
0
0
Hit (instr)
Hit (05) - replaces data
Hit (55) - replaces data
JUMP 0029
0012 29/00 1 0
Hit (instr)
Replaces data
AND 0014 00/0C 1 0 Replaces data
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 96
14.
Hit ratio = 4.5%
Instruction Address Tag Data Valid Dirty Comments
LDAC 4234 0
1
2
4
000
000
000
423
01
34
42
55
1
1
1
1
0
0
0
0
STAC 4235 3
4
5
5
000
000
000
423
0B
35
42
55
1
1
1
1
0
0
0
1
Replaces data
Replaces data
MVAC 6 000 03 1 0
INAC 7 000 0A 1 0
ADD 8 000 08 1 0
JPNZ 0020 9
A
B
000
000
000
07
20
00
1
1
1
0
0
0
LDAC 4235 0
1
2
002
002
002
01
35
42
1
1
1
0
0
0
Replaces data
Replaces data
Replaces data
Hit (read from 4235)
JUMP 0029 3
4
5
002
002
002
05
29
00
1
1
1
0
0
0
Replaces data
Replaces data
Replaces data
AND 9 002 0C 1 0 Replaces data
15.
Hits in italics Hit ratio = 50.0%
Instruction Address Tag Data Valid Dirty Comments
LDAC 4234 0
1
2
000
000
423
01/34
42/0B
55/--
1
1
1
0
0
0
Hit (34)
STAC 4235
2
2
000
423
35/42
55/55
1
1
0
1
Hit (STAC)
Hit (42) - Replaces data
Hit (4235) Replaces data
MVAC 3 000 03/0A 1 0
INAC Hit (INAC)
ADD 4 000 08/07 1 0
JPNZ 0020
5 000 20/00 1 0
Hit (STAC)
Hit (00)
LDAC 4235 0
1
002
002
01/35
42/05
1
1
0
0
Hit (35) - Replaces data
Replaces data
Hit (4235)
JUMP 0029
2 002 29/00 1 0
Hit (JUMP)
Hit (00) - Replaces data
AND 4 002 00/0C 1 0 Replaces data
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 97
16.
Hits in italics LRU value underlined Hit ratio = 4.5%
Instruction Address Tag1 Data1 V1 D1 Tag2 Data2 V2 D2 Tag3 Data3 V3 D3 Tag4 Data4 V4 D4
LDAC 4234 0
1
2
0000
0000
0000
01
34
42
1
1
1
0
0
0
108D 55 1 0
STAC 4235 3
0
1
0000
0000
0000
0B
01
34
1
1
1
0
0
0
108D
0001
55
42
1
1
0
0
0001
108D
35
55
1
1
0
1
MVAC 2 0000 42 1 0 0001 03 1 0
INAC 3 0000 0B 1 0 0001 0A 1 0
ADD 0 0000 01 1 0 108D 55 1 0 0001 35 1 0 0002 08 1 0
JPNZ 0020 1
2
3
0000
0000
0000
34
42
0B
1
1
1
0
0
0
0001
0001
0001
42
03
0A
1
1
1
0
0
0
108D
0002
0002
55
20
00
1
1
1
1
0
0
0002 07 1 0
LDAC 4235 0
1
2
0008
0008
0000
01
35
42
1
1
1
0
0
0
108D
0001
0001
55
42
03
1
1
1
0
0
0
0001
108D
0002
35
55
20
1
1
1
0
1
0
0002
0002
0008
08
07
42
1
1
1
0
0
0
JUMP 0029 3
0
1
0000
0008
0008
0B
01
01
1
1
1
0
0
0
0001
0009
0009
0A
29
00
1
1
1
0
0
0
0002
0001
108D
00
35
55
1
1
1
0
0
0
0008
0002
0002
05
08
07
1
1
1
0
0
0
AND 1 0008 01 1 0 0009 00 1 0 000A 0C 1 0 0002 07 1 0
17.
Hits in italics LRU value underlined Hit ratio = 40.9%
Instruction Address Tag1 Data1 V1 D1 Tag2 Data2 V2 D2
LDAC 4234 0
1
2
0000
0000
211A
01/34
42/02
55/--
1
1
1
0
0
0
STAC 4235
2 211A 55/55 1 0 0000 35/42 1 1
MVAC 3 0000 03/0A 1 0
INAC
ADD 0 0000 01/34 1 0 0001 08/07 1 0
JPNZ 0020
1 0000 42/02 1 0 0002 20/00 1 0
LDAC 4235 0
1
1
0008
0008
0008
01/35
42/05
42/05
1
1
1
0
0
0
0001
0002
211A
08/07
20/00
29/00
1
1
1
0
0
0
JUMP 0029
2 0009 29/00 1 0 0000 35/42 1 1
AND 0 0008 01/35 1 0 0009 0C/-- 1 0
18. T
M
= hT
C
+ (1 - h)T
P
= (.75 * 8 ns) + (.25 * 65 ns) = 22.25 ns
19. T
C
= (T
M
- (1 - h)T
P
)/h = (39.9 ns - .35 * 75 ns) / .65 = 21 ns
20. T
P
= (T
M
- hT
C
)/(1 - h) = (24 ns - .8 * 10 ns) / .2 = 80 ns
21. h = (T
M
- T
P
)/(T
C
- T
P
) = (40 ns - 55 ns) / (10 ns - 55 ns) = 0.333 ns
22. The next jump instruction is always overwritten by its predecessor; h = 0.
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 98
23.
(Only changes shown)
Address Frame Valid Comments
LDAC 4234 0 0 1
4 1 1
JUMP 1000 No changes
STAC 4235 1 2 1 4235 already in memory
JUMP 2000 No changes
JUMP 0010 2 3 1
JUMP 3000 No changes
JUMP 0100 3 0 1
0 0 0
JUMP 1100 0 1 0
24.
LDAC 4234
JUMP 1000
STAC 4235
JUMP 2000
JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100
P F V P F V P F V P F V P F V P F V
0 0 1 1 2 1 1 2 1 0 0 1 3 0 1 3 0 1
4 1 1 4 1 1 2 3 1 2 3 1 2 3 1 0 1 1
25.
LDAC 4234
JUMP 1000
STAC 4235
JUMP 2000
JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100
P F V P F V P F V P F V P F V P F V
0 0 1 1 2 1 1 2 1 0 0 1 3 0 1 3 0 1
4 1 1 4 1 1 2 3 1 2 3 1 2 3 1 0 1 1
26. a) 1554H
b) 2000H
c) Fault
27. a) F231H
b) Fault
c) 4401H
28. a) 1C35H
b) 0A38H
c) Fault
29. a) C543H
b) 4077H
c) 8401H
30. a) 2000H
b) 0D61H
c) 3FFFH
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31. a) 9512H
b) 3456H
c) 63EDH
32. a)
2 C 1
b)
9 6 1
c)
E A 1
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Chapter 10
1.
2.
3.
OTPT1: DR ← M, PC ← PC + 1, AR ← AR + 1
OTPT2: TR ← DR, DR ← M, PC ← PC + 1
OTPT3: AR ← DR,TR
OTPT4: DR ← AC
OTPT5: Output port ← DR
3. Add the following connections using the same decoder used to generate the states of the INPT execute
routine. The rest of the circuit is unchanged.
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5. MEMBUS = (old value of MEMBUS) ∨ INPT1 ∨ INPT2 ∨ INPT4
PCINC = (old value of PCINC) ∨ INPT1 ∨ INPT2
TRLOAD = (old value of TRLOAD) ∨ INPT2
ARLOAD = (old value of ARLOAD) ∨ INPT3
DRHBUS = (old value of DRHBUS) ∨ INPT3
TRBUS = (old value of TRBUS) ∨ INPT3
DRLBUS = (old value of DRLBUS) ∨ INPT5
6. The control unit changes are the same as for Problem 10.4. The control signal changes are as follows.
ARINC = (old value of ARINC) ∨ OTPT1
MEMBUS = (old value of MEMBUS) ∨ OTPT1 ∨ OTPT2
BUSMEM = (old value of BUSMEM) ∨ OTPT5
PCINC = (old value of PCINC) ∨ OTPT1 ∨ OTPT2
TRLOAD = (old value of TRLOAD) ∨ OTPT2
ARLOAD = (old value of ARLOAD) ∨ OTPT3
DRHBUS = (old value of DRHBUS) ∨ OTPT3
TRBUS = (old value of TRBUS) ∨ OTPT3
DRLBUS = (old value of DRLBUS) ∨ OTPT5
7. i) Modify the mapping function to map instruction code 0010 0000 to microcode address 100 0000.
ii) Add microcode signal IO, which is 1 only for the microinstruction at address 67.
iii) Add the following microinstructions to memory. (Only active control signals are shown.)
64: DRLOAD, MEMBUS, PCINC, ARINC U J 65
65: TRLOAD, DRLOAD, MEMBUS, PCINC U J 66
66: ARLOAD, DRHBUS, TRBUS U J 67
67: DRLOAD, MEMBUS U J 68
68: ACLOAD, DRLBUS U J 01
8. i) Modify the mapping function to map instruction code 0010 0001 to microcode address 100 1000.
ii) Add microcode signal IO, which is 1 for the microinstruction at address 76.
iii) Add the following microinstructions to memory. (Only active control signals are shown.)
72: DRLOAD, MEMBUS, PCINC, ARINC U J 73
73: TRLOAD, DRLOAD, MEMBUS, PCINC U J 74
74: ARLOAD, DRHBUS, TRBUS U J 75
75: DRLOAD, ACBUS U J 76
76: BUSMEM, DRLBUS U J 01
9.
Time (ns) 0 10 20 40 45 60 80 85 90 100
Routine MAIN IRQ1 IRQ2 IRQ1 IRQ3 IRQ4 IRQ3 IRQ1 MAIN
10.
Time (ns) 0 10 30 50 70 90 100
Routine MAIN IRQ6 IRQ5 IRQ4 IRQ3 MAIN
11.
Time (ns) 0 10 20 40 50 60 80 90 100
Routine MAIN IRQ4 IRQ6 IRQ4 IRQ1 IRQ3 IRQ1 MAIN
12. Daisy chaining is easier to modify when it is necessary to add peripherals to a computer system. It also
requires fewer pins on the CPU. Other points may also be considered for this question.
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13. IACK
out
= IACK
in
^ IRQ'
14.
Time (ns) 0 10 20 40 50 60 80 90 100
Routine MAIN IRQ4 IRQ6 IRQ4 IRQ1 IRQ3 IRQ1 MAIN
IACK6
in
IACK6
out
IACK4
in
IACK4
out
IACK3
in
IACK3
out
IACK1
in
IACK1
out
15.
Time (ns) 0 10 20 45 60
Int. Req.
Int. Ack.
Vector 4 6 1 3
16.
17.
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18. i) Add the following hardware to implement INT.
ii) Change the following state signals:
FETCH1 = T0 ^ (IP' ∨ IE')
FETCH2 = T1 ^ INT'
FETCH3 = T2 ^ INT'
iii) Add hardware to generate the following new state signals:
INT1 = T0 ^ (IP ^ IE)
INT2 = T1 ^ INT
INT3 = T2 ^ INT
INT4 = T3 ^ INT
INT5 = T4 ^ INT
INT6 = T5 ^ INT
INT7 = T6 ^ INT
iv) Modify the following internal control unit signals:
Decoder enable = (Old value of Decoder Enable) ^ INT'
Time counter CLR = (Old value of Time counter CLR) ^ INT7
19. Replace state FETCH1 and its input and output arcs with the following.
20. IE ^ IP ^ FETCH1: AR ← SP
(IE' ∨ IP') ^ FETCH1: AR ← PC
INT2 - INT7 are the same as in the chapter text.
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21.
ARLOAD =(Original value of ARLOAD) ∨ INT1
ARDEC =(Original value of ARDEC) ∨ INT3
SPBUF =(Original value of SPBUF) ∨ INT1
SPDEC =(Original value of SPDEC) ∨ INT2 ∨ INT3
DRLOAD =(Original value of DRLOAD) ∨ INT2 ∨ INT4 ∨ INT6
DRLBUS =(Original value of DRLBUS) ∨ INT3 ∨ INT5 ∨ INT7
PCHBUS =(Original value of PCHBUS) ∨ INT2
PCLBUS =(Original value of PCLBUS) ∨ INT4
PCLOAD =(Original value of PCLOAD) ∨ INT7
BUSMEM =(Original value of BUSMEM) ∨ INT3 ∨ INT5
WRITE =(Original value of WRITE) ∨ INT3 ∨ INT5
MEMBUS =(Original value of MEMBUS) ∨ INT6
IACK =INT5 ∨ INT6
22.
23. LDAC 2000
OTPT 8000
LDAC 2001
OTPT 8001
LDAC 2002
OTPT 8002
24. Replace the FETCH1 input to the OR gate which drives the INC signal of the Time Counter with
FETCH1 ^ BR'.
25. No changes are required, since the CPU does not interact with the data bus while a DMA transfer is active.
26. i) COH 10H 00H 00H 20H 99H 00H
ii) C1H 11H 00H 08H 28H 99H 01H
iii) C0H 10H 80H 00H 01H 99H 02H
27. a) 1 start + 0 parity + 1½ stop bits = 2½ bits overhead; 2½ ÷ (2½ + 8) = 23.8%.
b) 1 start + 1 parity + 2 stop bits = 4 bits overhead; 4 ÷ (4 + 7) = 36.4%.
c) 1 start + 1 parity + 1 stop bits = 3 bits overhead; 3 ÷ (3 + 5) = 37.5%.
28. a) Asynchronous: 2 ÷ (2 + 8) = 20.0%; HDLC: 48 ÷ (48 + 96) = 33.3%; Asynchronous has less overhead
b) Asynchronous: 2½ ÷ (2½ + 7) = 26.3%; HDLC: 48 ÷ (48 + 168) = 22.2%; HDLC has less overhead
c) Asynchronous: 2 ÷ (2 + 8) = 20.0%; HDLC: 48 ÷ (48 + 192) = 20.0%; Both have the same overhead.
29. LDAC 1111
OTPT 9800H
LDAC 1112H
OTPT 9801H
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30. a) Token packet: 24 bits
Data packet: 6168 bits
Handshaking packet: 8 bits
TOTAL: 6200 bits
b) 56 ÷ 6200 = 0.90%
c) 1536 × (1 start bit + 8 data bits + 1 stop bit) = 15,360 bits
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Chapter 11
1. a) 25 ns × 100% vs. (24 ns × 99%) + (24 ns × 4 instructions × 1%) average time
25 ns vs. 23.76 ns + 0.96 ns
25 ns > 24.72 ns, therefore the second CPU has better performance
b) 25 ns × 100% = (24 ns × (100 - x)%) + (96 ns × x%); x = 1.389%
c) 25 ns × 100% = (24 ns × 99%) + (24 ns × x instructions × 1%); x = 5.167 instructions
d) x ns × 100% = (24 ns × 99%) + (96 ns × 1%); x = 24.72 ns
e) 25 ns × 100% = (x ns × 99%) + (4x ns × 1%); x = 24.272 ns
2. a) 15 ns × 100% vs. (12 ns × 98%) + (12 ns × 6 instructions × 2%) average time
15 ns > 13.2 ns, therefore the second CPU has better performance
b) 15 ns × 100% = (12 ns × (100 - x)%) + (72 ns × x%); x = 5%
c) 15 ns × 100% = (12 ns × 98%) + (12 ns × x instructions × 2%); x = 13.5 instructions
d) x ns × 100% = (12 ns × 98%) + (72 ns × 2%); x = 13.2 ns
e) 15 ns × 100% = (x ns × 98%) + (6x ns × 2%); x = 13.636 ns
3. a) 18 ns × 100% vs. (16 ns × 96%) + (16 ns × 5 instructions × 4%) average time
18 ns > 18.56 ns, therefore the first CPU has better performance
b) 18 ns × 100% = (16 ns × (100 - x)%) + (80 ns × x%); x = 3.125%
c) 18 ns × 100% = (16 ns × 96%) + (16 ns × x instructions × 4%); x = 4.125 instructions
d) x ns × 100% = (16 ns × 96%) + (80 ns × 4%); x = 18.56 ns
e) 18 ns × 100% = (x ns × 96%) + (5x ns × 4%); x = 15.517 ns
4. a) Clock period = 80 ns
Steady state speedup = (40 + 80 + 50)/80 = 2.125
b) 160/80 = 2
5. a) Clock period = 60 ns
Steady state speedup = (30 + 25 + 60 + 40)/60 = 2.583
b) 150/60 = 2.5
6. a) Clock period = 70 ns
Steady state speedup = (20 + 25 + 20 + 70 + 40)/70 = 2.5
b) 160/70 = 2.286
7. a) Clock period = 50 ns
Steady state speedup = (40 + 45 + 35 + 50)/50 = 3.4
b) 160/50 = 3.2
8. a) Clock period = 40 ns
Steady state speedup = (30 + 25 + 20 + 40 + 40)/40 = 3.875
b) 150/40 = 3.75
9. a) Clock period = 45 ns
Steady state speedup = (20 + 25 + 20 + 25 + 45 + 40)/45 = 3.889
b) 160/45 = 3.556
c) Combine stages 1 and 2, and combine stages 3 and 4
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10. 10 global registers + 8 windows × (4 input registers + 10 local registers) = 122 registers
Note: Common output registers are not counted since they are already counted as common input
registers of the next window.
11. 160 registers = 16 global registers + W windows × (8 input registers + 16 local registers); W = 6 windows
12. 192 registers = 12 global registers + 10 windows × (6 input registers + L local registers);
L = 12 local registers
13. 188 registers = 20 global registers + 12 windows × (C input registers + 10 local registers);
C = 4 common input (and common output) registers
14. a) 2 no-ops
b) 2 no-ops
15. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
N1:No-op 1 1 N1 2 N2 3 4 5 N3 6
2:R4 ← R1 + R2 2 - 1 N1 2 N2 3 4 5 N3 6
N2:No-op 3 - - 1 N1 2 N2 3 4 5 N3 6
3:R3 ← R1 + R4
4:R5 ← R2 + R6
5:R6 ← R1 + R2
N3:No-op
6:R7 ← R5 + R6
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8
4:R5 ← R2 + R6 1 1 4 2 5 3 6
2:R4 ← R1 + R2 2 - 1 4 2 5 3 6
5:R6 ← R1 + R2 3 - - 1 4 2 5 3 6
3:R3 ← R1 + R4
6:R7 ← R5 + R6
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
2:R4 ← R1 + R2 1 1 2 S 3 S 4 5 S 6
3:R3 ← R1 + R4 2 - 1 2 S 3 S 4 5 S 6
4:R5 ← R2 + R6 3 - - 1 2 S 3 S 4 5 S 6
5:R6 ← R1 + R2
6:R7 ← R5 + R6
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8
2:R4 ← R1 + R2 1 1 2 3 4 5 6
3:R3 ← R1 + R4 2 - 1 2 3 4 5 6
4:R5 ← R2 + R6 3 - - 1 2 3 4 5 6
5:R6 ← R1 + R2
6:R7 ← R5 + R6
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16. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N1:No-op 1 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N2:No-op 2 - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
2:R4 ← R1 + R2 3 - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N3:No-op 4 - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N4:No-op
3:R3 ← R1 + R4
4:R5 ← R2 + R6
5:R6 ← R1 + R2
N5:No-op
N6:No-op
6:R7 ← R5 + R6
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
4:R5 ← R2 + R6 1 1 4 N1 2 5 N2 3 6
N1:No-op 2 - 1 4 N1 2 5 N2 3 6
2:R4 ← R1 + R2 3 - - 1 4 N1 2 5 N2 3 6
5:R6 ← R1 + R2 4 - - - 1 4 N1 2 5 N2 3 6
N2:No-op
3:R3 ← R1 + R4
6:R7 ← R5 + R6
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2:R4 ← R1 + R2 1 1 S S 2 S S 3 4 5 S S 6
3:R3 ← R1 + R4 2 - 1 S S 2 S S 3 4 5 S S 6
4:R5 ← R2 + R6 3 - - 1 S S 2 S S 3 4 5 S S 6
5:R6 ← R1 + R2 4 - - - 1 S S 2 S S 3 4 5 S S 6
6:R7 ← R5 + R6
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9
2:R4 ← R1 + R2 1 1 2 3 4 5 6
3:R3 ← R1 + R4 2 - 1 2 3 4 5 6
4:R5 ← R2 + R6 3 - - 1 2 3 4 5 6
5:R6 ← R1 + R2 4 - - - 1 2 3 4 5 6
6:R7 ← R5 + R6
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17. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N1:No-op 1 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N2:No-op 2 - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
2:R4 ← R1 + R2 3 - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N3:No-op 4 - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
N4:No-op 5 - - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6
3:R3 ← R1 + R4
4:R5 ← R2 + R6
5:R6 ← R1 + R2
N5:No-op
N6:No-op
6:R7 ← R5 + R6
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12
4:R5 ← R2 + R6 1 1 4 N1 2 5 N2 3 6
N1:No-op 2 - 1 4 N1 2 5 N2 3 6
2:R4 ← R1 + R2 3 - - 1 4 N1 2 5 N2 3 6
5:R6 ← R1 + R2 4 - - - 1 4 N1 2 5 N2 3 6
N2:No-op 5 - - - - 1 4 N1 2 5 N2 3 6
3:R3 ← R1 + R4
6:R7 ← R5 + R6
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2:R4 ← R1 + R2 1 1 S S 2 S S 3 4 5 S S 6
3:R3 ← R1 + R4 2 - 1 S S 2 S S 3 4 5 S S 6
4:R5 ← R2 + R6 3 - - 1 S S 2 S S 3 4 5 S S 6
5:R6 ← R1 + R2 4 - - - 1 S S 2 S S 3 4 5 S S 6
6:R7 ← R5 + R6 5 - - - - 1 S S 2 S S 3 4 5 S S 6
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10
2:R4 ← R1 + R2 1 1 2 3 4 5 6
3:R3 ← R1 + R4 2 - 1 2 3 4 5 6
4:R5 ← R2 + R6 3 - - 1 2 3 4 5 6
5:R6 ← R1 + R2 4 - - - 1 2 3 4 5 6
6:R7 ← R5 + R6 5 - - - - 1 2 3 4 5 6
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18. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10
N1:No-op 1 1 N1 2 3 4 N2 5 6
2:R1 ← R1 + R2 2 - 1 N1 2 3 4 N2 5 6
3:R2 ← R3 + R4 3 - - 1 N1 2 3 4 N2 5 6
4:R5 ← R6 + R7
N2:No-op
5:R5 ← R5 + R7
6:R6 ← R1 + R2
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8
3:R2 ← R3 + R4 1 1 3 4 2 5 6
4:R5 ← R6 + R7 2 - 1 3 4 2 5 6
2:R1 ← R1 + R2 3 - - 1 3 4 2 5 6
5:R5 ← R5 + R7
6:R6 ← R1 + R2
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10
2:R1 ← R1 + R2 1 1 2 3 S 4 5 S 6
3:R2 ← R3 + R4 2 - 1 2 3 S 4 5 S 6
4:R5 ← R6 + R7 3 - - 1 2 3 S 4 5 S 6
5:R5 ← R5 + R7
6:R6 ← R1 + R2
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8
2:R1 ← R1 + R2 1 1 2 3 4 5 6
3:R2 ← R3 + R4 2 - 1 2 3 4 5 6
4:R5 ← R6 + R7 3 - - 1 2 3 4 5 6
5:R5 ← R5 + R7
6:R6 ← R1 + R2
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19. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13
N1:No-op 1 1 N1 N2 2 3 4 N3 N4 5 6
N2:No-op 2 - 1 N1 N2 2 3 4 N3 N4 5 6
2:R1 ← R1 + R2 3 - - 1 N1 N2 2 3 4 N3 N4 5 6
3:R2 ← R3 + R4 4 - - - 1 N1 N2 2 3 4 N3 N4 5 6
4:R5 ← R6 + R7
N3:No-op
N4:No-op
5:R5 ← R5 + R7
6:R6 ← R1 + R2
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
3:R2 ← R3 + R4 1 1 3 4 N1 2 5 N2 6
4:R5 ← R6 + R7 2 - 1 3 4 N1 2 5 N2 6
N1:No-op 3 - - 1 3 4 N1 2 5 N2 6
2:R1 ← R1 + R2 4 - - - 1 3 4 N1 2 5 N2 6
5:R5 ← R5 + R7
N2:No-op
6:R6 ← R1 + R2
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13
2:R1 ← R1 + R2 1 1 2 S S 3 4 S S 5 6
3:R2 ← R3 + R4 2 - 1 2 S S 3 4 S S 5 6
4:R5 ← R6 + R7 3 - - 1 2 S S 3 4 S S 5 6
5:R5 ← R5 + R7 4 - - - 1 2 S S 3 4 S S 5 6
6:R6 ← R1 + R2
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9
2:R1 ← R1 + R2 1 1 2 3 4 5 6
3:R2 ← R3 + R4 2 - 1 2 3 4 5 6
4:R5 ← R6 + R7 3 - - 1 2 3 4 5 6
5:R5 ← R5 + R7 4 - - - 1 2 3 4 5 6
6:R6 ← R1 + R2
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20. a)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
N1:No-op 1 1 N1 N2 2 3 4 N3 N4 5 6
N2:No-op 2 - 1 N1 N2 2 3 4 N3 N4 5 6
2:R1 ← R1 + R2 3 - - 1 N1 N2 2 3 4 N3 N4 5 6
3:R2 ← R3 + R4 4 - - - 1 N1 N2 2 3 4 N3 N4 5 6
4:R5 ← R6 + R7 5 - - - - 1 N1 N2 2 3 4 N3 N4 5 6
N3:No-op
N4:No-op
5:R5 ← R5 + R7
6:R6 ← R1 + R2
b)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12
3:R2 ← R3 + R4 1 1 3 4 N1 2 5 N2 6
4:R5 ← R6 + R7 2 - 1 3 4 N1 2 5 N2 6
N1:No-op 3 - - 1 3 4 N1 2 5 N2 6
2:R1 ← R1 + R2 4 - - - 1 3 4 N1 2 5 N2 6
5:R5 ← R5 + R7 5 - - - - 1 3 4 N1 2 5 N2 6
N2:No-op
6:R6 ← R1 + R2
c)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
2:R1 ← R1 + R2 1 1 2 S S 3 4 S S 5 6
3:R2 ← R3 + R4 2 - 1 2 S S 3 4 S S 5 6
4:R5 ← R6 + R7 3 - - 1 2 S S 3 4 S S 5 6
5:R5 ← R5 + R7 4 - - - 1 2 S S 3 4 S S 5 6
6:R6 ← R1 + R2 5 - - - - 1 2 S S 3 4 S S 5 6
d)
1:R1 ← R2 + R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10
2:R1 ← R1 + R2 1 1 2 3 4 5 6
3:R2 ← R3 + R4 2 - 1 2 3 4 5 6
4:R5 ← R6 + R7 3 - - 1 2 3 4 5 6
5:R5 ← R5 + R7 4 - - - 1 2 3 4 5 6
6:R6 ← R1 + R2 5 - - - - 1 2 3 4 5 6
21.
Stage\Cycle 1 2 3 4 5 6 7 8
1 1 2 3 S S 10
2 - 1 2 3 S S 10
3 - - 1 2 3 S S 10
22.
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 2 3 4 5 N N 2 3 4 5 N N
2 - 1 2 3 4 5 N N 2 3 4 5 N N
3 - - 1 2 3 4 5 N N 2 3 4 5 N N
23.
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
1 1 4 5 2 3 4 5 2 3
2 - 1 4 5 2 3 4 5 2 3
3 - - 1 4 5 2 3 4 5 2 3
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24. a)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7 8 9
2:R3 ← R3 + R4 1 1 2 3 4 N1 N2 9
3:R5 ← R1 + R5 2 - 1 2 3 4 N1 N2 9
4:JUMP 9 3 - - 1 2 3 4 N1 N2 9
N1:No-op
N2:No-op
9:R2 ← R1 + R3
b)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7
4:JUMP 9 1 1 4 2 3 9
2:R3 ← R3 + R4 2 - 1 4 2 3 9
3:R5 ← R1 + R5 3 - - 1 4 2 3 9
9:R2 ← R1 + R3
c)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7 8 9
2:R3 ← R3 + R4 1 1 2 3 4 S S 9
3:R5 ← R1 + R5 2 - 1 2 3 4 S S 9
4:JUMP 9 3 - - 1 2 3 4 S S 9
9:R2 ← R1 + R3
25. a)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
2:R3 ← R3 + R4 1 1 2 N1 3 4 N2 N3 9
N1:No-op 2 - 1 2 N1 3 4 N2 N3 9
3:R5 ← R1 + R5 3 - - 1 2 N1 3 4 N2 N3 9
4:JUMP 9 4 - - - 1 2 N1 3 4 N2 N3 9
N2:No-op
N3:No-op
9:R2 ← R1 + R3
b)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7 8 9
4:JUMP 9 1 1 4 2 3 N 9
2:R3 ← R3 + R4 2 - 1 4 2 3 N 9
3:R5 ← R1 + R5 3 - - 1 4 2 3 N 9
N:No-op 4 - - - 1 4 2 3 N 9
9:R2 ← R1 + R3
c)
1:R1 ← R1 + R2 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11
2:R3 ← R3 + R4 1 1 2 3 S 4 S S 9
3:R5 ← R1 + R5 2 - 1 2 3 S 4 S S 9
4:JUMP 9 3 - - 1 2 3 S 4 S S 9
9:R2 ← R1 + R3 4 - - - 1 2 3 S 4 S S 9
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 114
26. a)
1:R1 ← 3
2:R2 ← R2 + R3
3:R3 ← R3 + R4
4:R4 ← R1 + R2
5:R1 ← R1 − 1
N1:No-op
6:IF (R1 ≠ 0) THEN GOTO 2
N2:No-op
N3:No-op
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1 1 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 7 8
2 - 1 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 7 8
3 - - 1 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 2 3 4 5 N1 6 N2 N3 7 8
b)
1:R1 ← 3
N:No-op
5:R1 ← R1 − 1
2:R2 ← R2 + R3
6:IF (R1 ≠ 0) THEN GOTO 2
3:R3 ← R3 + R4
4:R4 ← R1 + R2
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
1 1 N 5 2 6 3 4 5 2 6 3 4 5 2 6 3 4 7 8
2 - 1 N 5 2 6 3 4 5 2 6 3 4 5 2 6 3 4 7 8
3 - - 1 N 5 2 6 3 4 5 2 6 3 4 5 2 6 3 4 7 8
c)
1:R1 ← 3
2:R2 ← R2 + R3
3:R3 ← R3 + R4
4:R4 ← R1 + R2
5:R1 ← R1 − 1
6:IF (R1 ≠ 0) THEN GOTO 2
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1 1 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 7 8
2 - 1 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 7 8
3 - - 1 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 2 3 4 5 S 6 S S 7 8
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 115
27.
1:R1 ← 3
2:R2 ← R2 + R3
3:R3 ← R3 + R4
4:R4 ← R1 + R2
5:R1 ← R1 − 1
N:No-op
6:IF (R1 ≠ 0) THEN GOTO 2
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Underlined instructions are annulled
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
2 - 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
3 - - 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
28. a)
1:R1 ← 3
2:R2 ← R2 + R3
3:R3 ← R3 + R4
4:R4 ← R1 + R2
5:R1 ← R1 − 1
N:No-op
6:IF (R1 ≠ 0) THEN GOTO 2
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Underlined instructions are annulled
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 1 2 3 4 5 N 6 2 3 4 5 N 6 2 3 4 5 N 6 2 3 7 8
2 - 1 2 3 4 5 N 6 2 3 4 5 N 6 2 3 4 5 N 6 2 3 7 8
3 - - 1 2 3 4 5 N 6 2 3 4 5 N 6 2 3 4 5 N 6 2 3 7 8
b)
1:R1 ← 3
2:R2 ← R2 + R3
3:R3 ← R3 + R4
4:R4 ← R1 + R2
5:R1 ← R1 − 1
N:No-op
6:IF (R1 ≠ 0) THEN GOTO 2
7:R5 ← R6 + R7
8:R6 ← R7 + R8
Underlined instructions are annulled
Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
2 - 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
3 - - 1 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8 2 3 4 5 N 6 7 8
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 116
Chapter 12
1. a) diameter = 1; bandwidth = 500 Mb/s; bisection bandwidth = 500 Mb/s
b) diameter = 32; bandwidth = 32000 Mb/s; bisection bandwidth = 1000 Mb/s
c) diameter = 10; bandwidth = 31000 Mb/s; bisection bandwidth = 500 Mb/s
d) diameter = 16; bandwidth = 56000 Mb/s; bisection bandwidth = 4000 Mb/s
e) diameter = 8; bandwidth = 64000 Mb/s; bisection bandwidth = 8000 Mb/s
f) diameter = 6; bandwidth = 96000 Mb/s; bisection bandwidth = 16000 Mb/s
g) diameter = 1; bandwidth = 1008000 Mb/s; bisection bandwidth = 512000 Mb/s
2. a) diameter = 1; bandwidth = 10 Mb/s; bisection bandwidth = 10 Mb/s
b) diameter = 8; bandwidth = 160 Mb/s; bisection bandwidth = 20 Mb/s
c) diameter = 6; bandwidth = 150 Mb/s; bisection bandwidth = 10 Mb/s
d) diameter = 8; bandwidth = 240 Mb/s; bisection bandwidth = 40 Mb/s
e) diameter = 4; bandwidth = 320 Mb/s; bisection bandwidth = 80 Mb/s
f) diameter = 4; bandwidth = 320 Mb/s; bisection bandwidth = 80 Mb/s
g) diameter = 1; bandwidth = 1200 Mb/s; bisection bandwidth = 640 Mb/s
3. d(tree) = 2*¸lg n], d(ring) = n/2; 2*¸lg n] < n/2 for 13 ≤ n ≤ 15 and n ≥ 17
4. d(mesh) = n , d(tree) = 2*¸lg n]; n < 2*¸lg n] for 2 ≤ n ≤ 196
5. b(hc) = (n/2) * lg n * l, b(cc) = (¸n/2] * n/21) * l; (n/2) * lg n * l < (¸n/2] * n/21) * l for n ≥ 5
6. a) bb(mesh) = 2 16 * 100 Mb/s = 800 Mb/s = (¸16/2] * 16/21) * l
cc
; l
cc
= 12.5 Mb/s
b) 800 Mb/s = 16/2 * l
hc
; l
hc
= 100 Mb/s
c) 800 Mb/s = 2 2 / 16 1*l
mesh
; l
mesh
= 200 Mb/s
7. The hardware complexity is O(n
2
).
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Copyright © 2001 Addison Wesley - All Rights Reserved Page 117
8.

,
_

¸
¸
3 5 7 4 2 6 0 1
7 6 5 4 3 2 1 0
9.

,
_

¸
¸
3 0 1 2 5 7 6 4
7 6 5 4 3 2 1 0
10.

,
_

¸
¸
5 1 0 6 2 7 3 4
7 6 5 4 3 2 1 0
11. Circled switches were set randomly.
a)
b)
c)
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 118
12. a) b)
c)
13. a)
Module Address Range Addresses
M
0 0 to 8M − 1 00 0XXX XXXX XXXX XXXX XXXX XXXX
M
1 8M to 16M − 1 00 1XXX XXXX XXXX XXXX XXXX XXXX
M
2 16M to 24M − 1 01 0XXX XXXX XXXX XXXX XXXX XXXX
M
3 24M to 32M − 1 01 1XXX XXXX XXXX XXXX XXXX XXXX
M
4 32M to 40M − 1 10 0XXX XXXX XXXX XXXX XXXX XXXX
M
5 40M to 48M − 1 10 1XXX XXXX XXXX XXXX XXXX XXXX
M
6 48M to 56M − 1 11 0XXX XXXX XXXX XXXX XXXX XXXX
M
7 56M to 64M − 1 11 1XXX XXXX XXXX XXXX XXXX XXXX
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 119
b)
Module Address Range Addresses
M
0 0 to 32M − 1 00X XXXX XXXX XXXX XXXX XXXX XXXX
M
1 32M to 64M − 1 01X XXXX XXXX XXXX XXXX XXXX XXXX
M
2 64M to 96M − 1 10X XXXX XXXX XXXX XXXX XXXX XXXX
M
3 96M to 128M − 1 11X XXXX XXXX XXXX XXXX XXXX XXXX
c)
Module Address Range Addresses
M
0 0 to 4M − 1 0 00XX XXXX XXXX XXXX XXXX XXXX
M
1 4M to 8M − 1 0 01XX XXXX XXXX XXXX XXXX XXXX
M
2 8M to 12M − 1 0 10XX XXXX XXXX XXXX XXXX XXXX
M
3 12M to 16M − 1 0 11XX XXXX XXXX XXXX XXXX XXXX
M
4 16M to 20M − 1 1 00XX XXXX XXXX XXXX XXXX XXXX
M
5 20M to 24M − 1 1 01XX XXXX XXXX XXXX XXXX XXXX
M
6 24M to 28M − 1 1 10XX XXXX XXXX XXXX XXXX XXXX
M
7 28M to 32M − 1 1 11XX XXXX XXXX XXXX XXXX XXXX
14. a)
Module Address Range Addresses
M
0 i mod 8 = 0 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X000
M
1 i mod 8 = 1 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X001
M
2 i mod 8 = 2 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X010
M
3 i mod 8 = 3 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X011
M
4 i mod 8 = 4 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X100
M
5 i mod 8 = 5 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X101
M
6 i mod 8 = 6 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X110
M
7 i mod 8 = 7 (0 ≤ i ≤ 64M − 1) XX XXXX XXXX XXXX XXXX XXXX X111
b)
Module Address Range Addresses
M
0 i mod 4 = 0 (0 ≤ i ≤ 128M − 1) XXX XXXX XXXX XXXX XXXX XXXX XX00
M
1 i mod 4 = 1 (0 ≤ i ≤ 128M − 1) XXX XXXX XXXX XXXX XXXX XXXX XX01
M
2 i mod 4 = 2 (0 ≤ i ≤ 128M − 1) XXX XXXX XXXX XXXX XXXX XXXX XX10
M
3 i mod 4 = 3 (0 ≤ i ≤ 128M − 1) XXX XXXX XXXX XXXX XXXX XXXX XX11
c)
Module Address Range Addresses
M
0 i mod 8 = 0 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X000
M
1 i mod 8 = 1 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X001
M
2 i mod 8 = 2 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X010
M
3 i mod 8 = 3 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X011
M
4 i mod 8 = 4 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X100
M
5 i mod 8 = 5 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X101
M
6 i mod 8 = 6 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X110
M
7 i mod 8 = 7 (0 ≤ i ≤ 32M − 1) X XXXX XXXX XXXX XXXX XXXX X111
15.
Action Result Cache 0 Cache 1 Cache 2 Cache 3 Shared
P0 read Read miss 1000:K
1
E 1000:K
1
P2 write Write miss 1000:XX I 1000:K
2
M 1000:K
1
P1 read Read miss 1000:K
2
S 1000:K
2
S 1000:K
2
P0 write Write miss 1000:K
3
M 1000:XX I 1000:XX I 1000:K
2
P3 read Read miss 1000:K
3
S 1000:K
3
S 1000:K
3
P1 write Write miss 1000:XX I 1000:K
4
M 1000:XX I 1000:K
3
P1 read Read hit 1000:K
4
M 1000:K
4
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 120
16.
Action Result Cache 0 Cache 1 Cache 2 Cache 3 Shared
P2 write Write miss 1100:K
1
M 1100:K
0
P1 read Read miss 1100:K
1
S 1100:K
1
S 1100:K
1
P3 write Write miss 1100:XX I 1100:XX I 1100:K
2
M 1100:K
1
P2 read Read miss 1100:K
2
S 1100:K
2
S 1100:K
2
P0 read Read miss 1100:K
2
S 1100:K
2
S 1100:K
2
S 1100:K
2
P1 write Write miss 1100:XX I 1100:K
3
M 1100:XX I 1100:XX I 1100:K
2
P2 write Write miss 1100:XX I 1100:K
2
M 1100:K
3
17.
Data dependencies: 1 → 3 (A); 2 → 3 (D); 2 → 4 (D)
Data anti-dependencies 3 → 4 (A)
Data output dependencies: 1 → 4 (A)
18.
Data dependencies: 1 → 2 (A); 2 → 5 (A); 3 → 4 (D)
Data anti-dependencies 2 → 4 (B); 1 → 6 (C); 2 → 3 (D) ; 3 → 6 (F)
Data output dependencies: 1 → 2 (A)
19.
Data dependencies: 1 → 2 (A); 1 → 3 (A); 2 → 3 (B); 2 → 4 (B); 2 → 7 (B); 3 → 5 (C);
3 → 7 (C); 4 → 6 (A); 6 → 8 (A); 7 → 8 (E)
Data anti-dependencies 1 → 2 (B); 1 → 3 (C); 2 → 3 (C); 2 → 4 (A); 2 → 6 (A); 3 → 4 (A);
3 → 6 (A); 4 → 5 (D); 5 → 7 (E); 6 → 8 (F)
Data output dependencies: 1 → 4 (A); 1 → 6 (A); 4 → 6 (A);
20.
i j k C
1..3 1..3 1
1
1
]
1

¸

0 2 0
2 0 2
1 0 2
1..3 1..3 2
1
1
]
1

¸

+ + +
+ + +
+ + +
0 0 4 2 4 0
0 2 1 0 2 2
2 1 0 0 0 2
1..3 1..3 3
1
1
]
1

¸

+ + +
+ + +
+ + +
4 0 0 6 2 4
1 2 4 1 2 4
0 3 1 0 2 2
- - -
1
1
]
1

¸

4 6 6
3 5 6
3 1 4
Computer Systems Organization and Architecture - Solutions Manual
Copyright © 2001 Addison Wesley - All Rights Reserved Page 121
21. 1. A ← B + C
2. A1 ← A + D
3. D1 ← C + E
4. B1 ← D1 + F
5. G ← A1 + H
22. 1. A ← B + C
2. B1 ← A + A
3. C1 ← B1 + A
4. B2 ← C1 + D
5. B3 ← B2 + A

Computer Systems Organization and Architecture - Solutions Manual

Table of Contents
Chapter 1 ....................................................................................................................................1 Chapter 2 ....................................................................................................................................8 Chapter 3 ..................................................................................................................................18 Chapter 4 ..................................................................................................................................21 Chapter 5 ..................................................................................................................................33 Chapter 6 ..................................................................................................................................45 Chapter 7 ..................................................................................................................................59 Chapter 8 ..................................................................................................................................80 Chapter 9 ..................................................................................................................................92 Chapter 10 .............................................................................................................................. 100 Chapter 11 .............................................................................................................................. 106 Chapter 12 .............................................................................................................................. 116

Copyright © 2001 Addison Wesley - All Rights Reserved

Page ii

Computer Systems Organization and Architecture - Solutions Manual

Chapter 1
1.
x 0 0 0 0 1 1 1 1 w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z x + y´ y + z (x + y´)(y + z) 0 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 wx 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 xy xz y´z xy + xz + y´z 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1

2. a)

xz y´ wx + xz + y´ 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1

b)

w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

z w+x+y+z 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

c) w
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

z w´x´yz w´xyz w´x´yz´ w´xyz´ w´x´yz + w´xyz + w´x´yz´ + w´xyz´ 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Copyright © 2001 Addison Wesley - All Rights Reserved

Page 1

Computer Systems Organization and Architecture .Solutions Manual 3.All Rights Reserved Page 2 . a 0 0 1 1 b 0 1 0 1 ab (ab)´ a´ b´ a´ + b´ 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 a 0 0 1 1 b a + b (a + b)´ a´ b´ a´b´ 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0 0 4. a) wx\yz 00 01 11 10 00 01 11 10 0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 wx + xz + w´y´z b) wx\yz 00 01 11 10 00 01 11 10 1 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 y´z´ + xy´ + wz´ c) wx\yz 00 01 11 10 00 01 11 10 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 Already minimal 8. a) b) c) 9. a) wx\yz 00 01 11 10 00 01 11 10 1 0 0 1 1 X 1 1 0 1 X 0 0 X X 0 w´z´ + xy b) wx\yz 00 01 11 10 00 01 11 10 X 1 1 X 0 X X 0 0 0 X 0 X X X X x´ 7. a) b) wx\yz 00 01 11 10 00 01 11 10 1 1 0 1 1 1 1 0 1 1 1 0 1 0 0 1 w´x´y´ + w´xz + wxy + wx´z´ or x´y´z´ + w´y´z + xyz + wyz´ x´z´ + w´y´ + xz + xy´ or x´z´ + w´y´ + xz + y´z´ 6. wxy´ + wxz + w´xy + xyz´: wx\yz 00 01 11 10 00 01 11 10 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 wx + xy Copyright © 2001 Addison Wesley . a) w' + x' + y' + z' b) w' + x' + y'z c) (w' + x') + (w' + y') + (w' + z') + (x' + y') + (x' + z') + (y' + z') = w' + x' + y' + z' wx\yz 00 01 11 10 00 01 11 10 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 5.

Remove the tri-state buffers and do one of the following: a) Change each 2-input AND gate to a 3-input AND gate. The rest of the circuit is unchanged. 14. Each gates' inputs should be its two original inputs and E. Change the AND gates to NAND gates. Copyright © 2001 Addison Wesley . 13. The second input to the new 2-input AND gates is E. a) b) 11.Computer Systems Organization and Architecture . or b) Have each AND gate's output serve as an input to another 2-input AND gate. 12.Solutions Manual 10.All Rights Reserved Page 3 . one gate for each original AND gate.

Set up Karnaugh maps for each output. 17. then develop minimal logic expressions and design the appropriate logic circuits. C3 = X2Y2 + (X2 ⊕ Y2)(X1Y1 + (X1 ⊕ Y1)(X0Y0 + (X0 ⊕ Y0)C0)) C4 = X3Y3 + (X3 ⊕ Y3)(X2Y2 + (X2 ⊕ Y2)(X1Y1 + (X1 ⊕ Y1)(X0Y0 + (X0 ⊕ Y0)C0))) Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture . X > Y: X1X0\Y1Y0 00 01 11 10 X = Y: X1X0\Y1Y0 00 01 11 10 X < Y: X1X0\Y1Y0 00 01 11 10 00 01 11 10 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 00 01 11 10 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 00 01 11 10 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 (X > Y) = X1Y1' + X0Y1'Y0' + X1X0Y0' (X = Y) = X1'X0'Y1'Y0' + X1'X0Y1'Y0 + X1X0'Y1Y0' + X1X0Y1Y0 = (X1 ⊕ Y1)'(X0 ⊕ Y0)' (X < Y) = X1'Y1 + X1'X0'Y0 + X0'Y1Y0 16.Solutions Manual 15.All Rights Reserved Page 4 .

X3 X2 X1 X0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 a 0 1 0 0 1 0 0 0 0 0 b 0 0 0 0 0 1 1 0 0 0 c 0 0 1 0 0 0 0 0 0 0 a: X3X2\X1X0 00 01 11 10 00 01 11 10 0 1 0 0 1 0 0 0 X X X X 0 0 X X b: X3X2\X1X0 00 01 11 10 c: X3X2\X1X0 00 01 11 10 00 01 11 10 0 0 0 1 0 0 0 0 X X X X 0 0 X X a = X3'X2'X1'X0 + X2X1'X0' b = X2X1'X0 + X2X1X0' c = X2'X1X0' d: X3X2\X1X0 00 01 11 10 00 01 11 10 0 1 0 0 1 0 1 0 X X X X 0 1 X X e: X3X2\X1X0 00 01 11 10 00 01 11 10 0 1 1 0 1 1 1 0 X X X X 0 1 X X f: X3X2\X1X0 00 01 11 10 00 01 11 10 0 1 1 1 0 0 1 0 X X X X 0 0 X X d = X2X1'X0' + X2'X1'X0 + X2X1X0 e = X2X1' + X0 f = X1X0 + X3'X2'X0 + X2'X1 g: X3X2\X1X0 00 01 11 10 00 01 11 10 1 1 0 0 0 0 1 0 X X X X 0 0 X X g = X3'X2'X1' + X2X1X0 Copyright © 2001 Addison Wesley .All Rights Reserved Page 5 .Computer Systems Organization and Architecture .Solutions Manual 18 X3X2\X1X0 00 01 11 10 00 01 11 10 1 0 1 1 0 1 0 1 X X X X 1 0 X X X3X2\X1X0 00 01 11 10 00 01 11 10 1 0 0 1 0 0 0 1 X X X X 1 0 X X e = X2'X0' + X1X0' d = X2'X0' + X2'X1 + X1X0' + X2X1'X0 X3X2\X1X0 00 01 11 10 00 01 11 10 1 0 0 0 1 1 0 1 X X X X 1 1 X X X3X2\X1X0 00 01 11 10 00 01 11 10 0 0 1 1 1 1 0 1 X X X X 1 1 X X f = X3 + X2X0' + X2X1' + X1'X0' g = X3 + X2X0' + X1X0' + X2'X1 d 0 1 0 0 1 0 0 1 0 1 e 0 1 0 1 1 1 0 1 0 1 f 0 1 1 1 0 0 0 1 0 0 g 1 1 0 0 0 0 0 1 0 0 00 01 11 10 0 0 0 0 0 1 0 1 X X X X 0 0 X X 19.

Since each sorter has two possible states (MAX = X MIN = Y.Solutions Manual 20.24(b) matches this bound. Since the sorting network of Figure 1. The four inputs can be in one of 24 (= 4!) possible orders. it does not guarantee the existence of a 5-sorter network that can sort four inputs. (This argument establishes a lower bound. Each clock is driven by Q of the flip-flop to its right instead of Q'. it is a minimal network.Computer Systems Organization and Architecture . The clock of the rightmost flip-flop is unchanged. Five sorters have 25 = 32 states. and all flip-flops to its right are 1. All other signals are unchanged. n sorters can have up to 2n states. A flip-flop is clocked if the increment signal and clock are asserted. 23. which could be sufficient. or MAX = Y MIN = X).All Rights Reserved Page 6 . not enough to sort all 24 possible input orders. a) b) 22. X2 X1 X0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 1 J2 : J2 K2 0 X 0 X 1 X 0 X X 1 X 0 X 0 X 0 J1 : J1 K1 0 X 1 X X 0 X 0 0 X 0 X X 0 X 1 J0 K0 1 X X 0 0 X X 1 0 X X 1 1 X X 0 J0 : X2\X1X0 00 01 11 10 0 1 X X 0 1 0 X X 1 J0 = X2'X1' + X2X1 K0: X2\X1X0 00 01 11 10 0 X 0 1 X 1 X 1 0 X K0 = X2'X1 + X2X1' X2\X1X0 00 01 11 10 0 0 0 0 1 1 X X X X J2 = X1X0' X2\X1X0 00 01 11 10 0 0 1 X X 1 0 0 X X J1 = X2'X0 K2: X2\X1X0 00 01 11 10 0 X X X X 1 1 0 0 0 K2 = X1'X0' K1: X2\X1X0 00 01 11 10 0 X X 0 0 1 X X 1 0 K1 = X2X0 Copyright © 2001 Addison Wesley . Four sorters can have only 24 = 16 states. 24.) 21.

All Rights Reserved Page 7 . a) b) 27.Computer Systems Organization and Architecture . a) b) 26.Solutions Manual 25. Copyright © 2001 Addison Wesley .

Add the following states to the state table. it is not necessary to change the state diagram.All Rights Reserved Page 8 .Solutions Manual Chapter 2 1. Present State SNOCAR SNOCAR SNOCAR SPAID SPAID SPAID SCHEAT SCHEAT SCHEAT C 0 0 0 1 1 1 0 0 0 I1 0 1 1 0 1 1 0 1 1 I0 1 0 1 1 0 1 1 0 1 Next State SNOCAR SNOCAR SNOCAR SPAID SPAID SPAID SCHEAT SCHEAT SCHEAT R 1 1 1 0 0 0 1 1 1 G 0 0 0 1 1 1 0 0 0 A 0 0 0 0 0 0 1 1 1 Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture . a) Present State 0 0 1 1 Present State 0 0 1 1 D Next State 0 0 1 1 0 0 1 1 T Next State 0 0 1 1 0 1 1 0 b) 2. Present State 0 0 0 0 1 1 1 1 U U U U S 0 0 1 1 0 0 1 1 0 0 1 1 R Next State 0 0 1 0 0 1 1 U 0 1 1 0 0 1 1 U 0 U 1 0 0 1 1 U 3. Since all additions are self-loops.

Computer Systems Organization and Architecture .Solutions Manual 4.All Rights Reserved Page 9 . Copyright © 2001 Addison Wesley .

Address Data (Mealy) Data (Moore) 0000 0000 0000 0001 0010 0010 0010 0100 0100 0011 0110 0110 0100 1000 1000 0101 1010 1010 0110 1101 1100 0111 1110 1110 1000 0000 0000 1001 0010 0010 1010 0100 0100 1011 0110 0110 1100 1000 1001 1101 1010 1011 1110 1101 1100 1111 1110 1110 Present State 00 00 01 01 10 10 11 11 I Next State 0 00 1 01 0 00 1 10 0 11 1 10 0 00 1 01 M 0 0 0 0 0 0 1 1 7. N1 = P1'P0I + P1P0' N0 = P1'P0'I + P1P0'I' + P1P0I M = P1P0 Copyright © 2001 Addison Wesley . 6.Solutions Manual 5.Computer Systems Organization and Architecture .All Rights Reserved Page 10 .

All Rights Reserved Page 11 .Solutions Manual 8. State value assignments (P3 .P0): S0 = 0000 S5 = 0001 S10 = 0010 S15 = 0011 S25 = 0101 S30 = 0110 SPAID = 0111 SNOCAR = 1000 SCHEAT = 1001 S20 = 0100 N3 = C' N2 = P3'CI1I0 + P3'(P2 + P1)CI1I0' + P3'(P2 + P1P0)CI1'I0 + P2CI1'I0' N1 = P3'(P2 + P1 + P0)CI1I0 + P3'(P2 + P1')CI1I0' + P3'(P1'P0 + P1P0' + P2P1P0)CI1'I0 + P1P0CI1'I0' N0 = P3'(P2 + P1 + P0')CI1I0 + P3'(P0 + P2P1)CI1I0' + P3'(P0' + P2P1)CI1'I0 + P3'P0CI1'I0' + P3P0C + P3'(P2' + P1' + P0')C' R = G' G = P3'(P2 + P1)CI1I0 + P3'P2P0CI1 + P3'P2P1C(I1 + I0) + P3'P2P1P0C A = P3'(P2 + P1 + P0)C' Copyright © 2001 Addison Wesley .P0): S0 = 0000 S5 = 0001 S10 = 0010 S15 = 0011 S25 = 0101 S30 = 0110 SPAID = 0111 SNOCAR = 1000 SCHEAT = 1001 S20 = 0100 10.Computer Systems Organization and Architecture . Address Data (Mealy) Data (Moore) 000 000 000 001 010 010 010 000 000 011 100 100 100 111 110 101 100 100 110 000 001 111 010 011 State value assignments (P3 . N3 = C' N2 = P3'CI1I0 + P3'(P2 + P1)CI1I0' + P3'(P2 + P1P0)CI1'I0 + P2CI1'I0' N1 = P3'(P2 + P1 + P0)CI1I0 + P3'(P2 + P1')CI1I0' + P3'(P1'P0 + P1P0' + P2P1P0)CI1'I0 + P1P0CI1'I0' N0 = P3'(P2 + P1 + P0')CI1I0 + P3'(P0 + P2P1)CI1I0' + P3'(P0' + P2P1)CI1'I0 + P3'P0CI1'I0' + P3P0C + P3'(P2' + P1' + P0')C' R = SPAID' G = SPAID A = SCHEAT 11. 9.

N2 = P2P0' + P2U' + P1P0U N1 = P1P0' + P1U' + P2'P1'P0U N0 = P0'U + P0U' C = P2'P1'P0'U' + P2P1'P0U V2 = P2'P1P0U + P2P1'P0' + P2P1'P0U' V1 = P2'P1'P0U + P2'P1P0' + P2'P1P0U' V0 = (P2' + P1')P0'U + (P2' + P1)P0U' 15.All Rights Reserved Page 12 . The next state logic is the same as for the Moore machine.Solutions Manual 12. Address 0000XXX 0001XXX 0010XXX 0011XXX 0100XXX 0101XXX 0110XXX 0111XXX 1000XXX 1001XXX 1010XXX 1011XXX 1100XXX 1101XXX 1110XXX 1111XXX Data 1001101 1001101 1001101 1001101 0000100 0001100 0010100 0101100 1001101 1001101 1001101 1001101 0001100 0010100 0011100 0110100 1001101 1001101 1001101 1001101 0010100 0011100 0100100 0111010 1001101 1001101 1001101 1001101 0011100 0100100 0101100 0111010 1001101 1001101 1001101 1001101 0100100 0101100 0110100 0111010 1001101 1001101 1001101 1001101 0101100 0110100 0111010 0111010 1001101 1001101 1001101 1001101 0110100 0111010 0111010 0111010 1000100 1000100 1000100 1000100 0111010 0111010 0111010 0111010 1000100 1000100 1000100 1000100 0000100 0000100 0000100 0000100 1001101 1001101 1001101 1001101 0000100 0000100 0000100 0000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100 13. Copyright © 2001 Addison Wesley . N2: P2P1\P0U 00 01 11 10 00 01 11 10 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 N1: P2P1\P0U 00 01 11 10 00 01 11 10 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 N2: P2P1\P0U 00 01 11 10 00 01 11 10 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 14.Computer Systems Organization and Architecture . All possible next state values are already used.

P0): S0 = 0000 S5 = 0001 S10 = 0010 S15 = 0011 S20 = 0100 S25 = 0101 S30 = 0110 SPAID = 0111 SNOCAR = 1000 SCHEAT = 1001 SA = 1010 SB = 1011 SC = 1100 SD = 1101 SE = 1110 SF = 1111 Add to state table: Present State 1010 1011 1100 1101 1110 1111 C X X X X X X I1 X X X X X X I0 X X X X X X Next State 1000 1000 1000 1000 1000 1000 R 0 0 0 0 0 0 G 0 0 0 0 0 0 A 0 0 0 0 0 0 Add to state diagram: N3 = C' + P3(P2 + P1) N2 = P3'CI1I0 + P3'(P2 + P1)CI1I0' + P3'(P2 + P1P0)CI1'I0 + P2CI1'I0' N1 = P3'(P2 + P1 + P0)CI1I0 + P3'(P2 + P1')CI1I0' + P3'(P1'P0 + P1P0' + P2P1P0)CI1'I0 + P1P0CI1'I0' N0 = P3'(P2 + P1 + P0')CI1I0 + P3'(P0 + P2P1)CI1I0' + P3'(P0' + P2P1)CI1'I0 + P3'P0CI1'I0' + P3P0C + P3'(P2' + P1' + P0')C' R = SPAID' G = SPAID A = SCHEAT 17.Solutions Manual 16. State value assignments (P3 .All Rights Reserved Page 13 .Computer Systems Organization and Architecture . N3 = P2P1P0U' + P3(P2' + P1' + P0' + U) N2 = P3P2(P0 + U) + P2P1 + P3'P1P0'U' N1 = P3' (P2 + P1)U' + P2P1P0U' + P1U N0 = (P3' + P2)P1'U + P3'P2U + P0U' C = P2'P1'P0' V2 = P3P1'P0 + P3P2P0' V1 = P3'P1P0' + P2P1P0 V0 = P3'P2'P0 + P2P1P0 + P3P1'P0 Copyright © 2001 Addison Wesley .

19.Computer Systems Organization and Architecture .All Rights Reserved Page 14 . Copyright © 2001 Addison Wesley .Solutions Manual 18.

10 = player 2. States are of the form ABCYZ.Computer Systems Organization and Architecture . Although not shown in the diagram. 11 = player 3. 00 = no player). Address XXXXX XX1X 00000 000X 00000 010X 00000 100X 00000 110X 00001 XX00 00001 XX01 00010 XX00 00010 XX01 00011 XX00 00011 XX01 00100 000X 00100 010X 00100 100X 00100 110X 00101 XX00 00101 XX01 Data 00000 000 00000 000 00001 000 00010 000 00011 000 00001 100 10000 100 00010 010 01000 010 00011 001 00100 001 00100 000 00101 000 00110 000 00100 000 00101 100 10100 100 Address 00110 XX00 00110 XX01 01000 X00X 01000 010X 01000 110X 01001 XX00 01001 XX01 01011 XX00 01011 XX01 01100 000X 01100 010X 01100 1X0X 01101 XX00 01101 XX01 10000 0X0X 10000 100X 10000 110X Data 00110 010 01100 010 01000 000 01001 000 01011 000 01001 100 11000 100 01011 001 01100 001 01100 000 01101 000 01100 000 01101 100 11100 100 10000 000 10010 000 10011 000 Address 10010 XX00 10010 XX01 10011 XX00 10011 XX01 10100 0X0X 10100 100X 10100 110X 10110 XX00 10110 XX01 11000 0X0X 11000 100X 11000 110X 11011 XX00 11011 XX01 11100 XX0X All others Data 10010 010 11000 010 10011 001 10100 001 10100 000 10110 000 10100 000 10110 010 11100 010 11000 000 11000 000 11011 000 11011 001 11100 001 11100 000 00000 000 Copyright © 2001 Addison Wesley . or 1 if the player may not signal. YZ represents the player answering the question (01 = player 1. there is an arc from every state back to state 00000 with condition R.All Rights Reserved Page 15 . where A|B|C = 0 if a player may signal.Solutions Manual 20.

States are of the form ABCYZ. where A|B|C = 0 if a player may signal.Computer Systems Organization and Architecture .All Rights Reserved Page 16 . Address XXXXX XX1X 00000 000X 00000 010X 00000 100X 00000 110X 00001 XX00 00001 XX01 00010 XX00 00010 XX01 00011 XX00 00011 XX01 00100 000X 00100 010X 00100 100X 00100 110X 00101 XX00 00101 XX01 Data 00000 000 00000 000 00001 100 00010 010 00011 001 00001 100 10000 000 00010 010 01000 000 00011 001 00100 000 00100 000 00101 100 00110 010 00100 000 00101 100 10100 000 Address 00110 XX00 00110 XX01 01000 X00X 01000 010X 01000 110X 01001 XX00 01001 XX01 01011 XX00 01011 XX01 01100 000X 01100 010X 01100 1X0X 01101 XX00 01101 XX01 10000 0X0X 10000 100X 10000 110X Data 00110 010 01100 000 01000 000 01001 100 01011 001 01001 100 11000 000 01011 001 01100 000 01100 000 01101 100 01100 000 01101 100 11100 000 10000 000 10010 010 10011 001 Address 10010 XX00 10010 XX01 10011 XX00 10011 XX01 10100 0X0X 10100 100X 10100 110X 10110 XX00 10110 XX01 11000 0X0X 11000 100X 11000 110X 11011 XX00 11011 XX01 11100 XX0X All others Data 10010 010 11000 000 10011 001 10100 000 10100 000 10110 010 10100 000 10110 010 11100 000 11000 000 11000 000 11011 001 11011 001 11100 000 11100 000 00000 000 Copyright © 2001 Addison Wesley . 11 = player 3. there is an arc from every state back to state 00000 with condition R. 00 = no player). or 1 if the player may not signal. 10 = player 2. Although not shown in the diagram.Solutions Manual 21. YZ represents the player answering the question (01 = player 1.

P1: P0X'Y P0: P0XY' should be P0X'Y' B: P0 should be P0' CLR: Counter input D0: A: 0XY' should be 1XY' 0X'Y should be 0XY 1 should be 0 should be P0XY 26. Address Correct Data 0011 01110 0100 01011 1011 00111 Copyright © 2001 Addison Wesley .Solutions Manual 22. 23. 24. 25.All Rights Reserved Page 17 . 27.Computer Systems Organization and Architecture .

a) MUL X. a) Data movement 2.B MUL T.A ADD X.D c) LOAD B MUL C ADD A ADD D STORE X d) PUSH A PUSH B PUSH C MUL PUSH D ADD ADD POP X 13.Computer Systems Organization and Architecture .D ADD X. a) Implicit 8.D b) MOV X.A. a) Implicit 5.D ADD X.X.B.X.F MUL X.C ADD X.B MUL X.A MUL T. a) Register Direct 7.T.E ADD X.E.A ADD X. a) Direct 4. a) AC = 11 b) AC = 12 c) AC = 30 d) AC = 31 e) AC = 10 f) AC = 23 g) AC = 31 11.All Rights Reserved Page 18 .C ADD X. a) Data operation 3.B MUL T.X.C MOV X. a) Implicit 6.C ADD X.F MUL X.T b) MOV T.Solutions Manual Chapter 3 1.T c) LOAD A MUL B MUL C STORE T LOAD E ADD F MULT D ADD T STORE X d) PUSH A PUSH B MUL PUSH C MUL PUSH D PUSH E PUSH F ADD MUL ADD POP X Copyright © 2001 Addison Wesley .X. a) Register Direct b) Data operation c) Program control d) Data operation d) Data movement e) Data operation e) Data operation b) Program control c) Data movement b) Implied b) Direct b) Direct b) Immediate b) Direct c) Implicit c) Implicit c) Implicit c) Implicit c) Indirect d) Immediate e) Direct d) Register Indirect e) Register Direct d) Implicit e) Immediate b) Register Indirect c) Implicit 9. a) AC = 11 b) AC = 12 c) AC = 10 d) AC = 11 e) AC = 10 f) AC = 33 g) AC = 41 10. a) MUL T. a) AC = 11 b) AC = 12 c) AC = 20 d) AC = 21 e) AC = 10 f) AC = 43 g) AC = 21 12.

T. Processor Time per instruction # Instructions Total time 0 35 ns 4 140 ns 1 50 ns 3 150 ns 2 70 ns 2 140 ns 3 100 ns 1 100 ns Processor Time per instruction # Instructions Total time 0 35 ns 8 280 ns 1 50 ns 5 250 ns 2 70 ns 4 280 ns 3 100 ns 3 300 ns Processor Time per instruction # Instructions Total time 0 35 ns 12 420 ns 1 50 ns 9 450 ns 2 70 ns 7 490 ns 3 100 ns 5 500 ns Processor Time per instruction # Instructions Total time 0 35 ns 12 420 ns 1 50 ns 11 550 ns 2 70 ns 8 560 ns 3 100 ns 5 500 ns LDAC 1001H MVAC LDAC 1002H ADD MVAC LDAC 1003H ADD MVAC LDAC 1004H ADD MVAC LDAC 1005H ADD MVAC fastest 16.Solutions Manual 14.Computer Systems Organization and Architecture .E.F ADD T.C MOV X.F ADD T. LDAC 1006H ADD MVAC LDAC 1007H ADD MVAC LDAC 1008H ADD MVAC LDAC 1009H ADD MVAC LDAC 100AH ADD STAC 1000H Copyright © 2001 Addison Wesley . fastest 17.T b) MOV T.T MOV T. fastest 18.All Rights Reserved Page 19 . fastest 19.C SUB X.X.A SUB X.T c) LOAD B MUL C STORE T LOAD A SUB T STORE X LOAD E MUL F ADD D MUL X STORE X d) PUSH A PUSH B PUSH C MUL SUB PUSH D PUSH E PUSH F MUL ADD MUL POP X 15.E MUL T.D MUL X.X MUL T.A. a) MUL X.B.B MUL T.D MUL X.

result in FB Not done. FA = 1 FB = 2 Count = 2 FN = 2 FB = FB + FA Count = Count + 1 If n = 2 then done Loop: If Count = n then done.Computer Systems Organization and Architecture .1 MVI A.A MVI B.A DCR D JNZ Loop STA FN D=n B = FA C = FB Initially A = FA FA = FA + FB If D = 0 then done FB = FB + FA If D = 0 then done Not done.0AH XRA A ADD M INX H DCR B JNZ Loop STA 1000H CLAC INAC STAC FA INAC STAC FB STAC Count STAC FN MVAC LDAC SUB JMPZ Done LDAC FA MVAC LDAC FB ADD STAC FA LDAC Count INAC STAC Count MVAC LDAC n SUB JMPZ DoneA LDAC FB MVAC LDAC FA ADD STAC FB LDAC Count INAC STAC Count MVAC LDAC n SUB JMPZ DoneB JUMP Loop DoneA: LDAC FA STAC FN JUMP Done DoneB: LDAC FB STAC FN Done: … 21.Solutions Manual 20. loop back Store FN Copyright © 2001 Addison Wesley . Loop: Done: LDA n MOV D.All Rights Reserved Page 20 . 1001H MVI B. result in FA 22.2 MOV C. loop back FN = FA FA = FA + FB FN = FB Count = Count + 1 If Count = n then done.A DCR D JZ Done ADD C MOV C.A DCR D DCR D JZ Done ADD B MOV B. Loop: LXI H.

All Rights Reserved Page 21 . 2.Solutions Manual Chapter 4 1.Computer Systems Organization and Architecture . Copyright © 2001 Addison Wesley .

Computer Systems Organization and Architecture . 4.Solutions Manual 3.All Rights Reserved Page 22 . Copyright © 2001 Addison Wesley .

6. Copyright © 2001 Addison Wesley .Solutions Manual 5.All Rights Reserved Page 23 .Computer Systems Organization and Architecture .

Solutions Manual 7. Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture . 8.All Rights Reserved Page 24 .

10.Computer Systems Organization and Architecture . a. Little Endian 22 78H 23 56H 24 34H 25 12H 22 27H 23 09H 22 12H 23 12H 24 55H 25 05H Copyright © 2001 Addison Wesley .) CE = A7'A6'A5'A4' ( IO / M )' b.All Rights Reserved Page 25 .) CE = A7A6A5A4 ( IO / M )' Big Endian a) 22 12H 23 34H 24 56H 25 78H b) 22 09H 23 27H c) 22 05H 23 55H 24 12H 25 12H OE = RD OE = RD OE = RD 11.Solutions Manual 9.) CE = A7'A6'A5'A4 ( IO / M )' c.

All Rights Reserved Page 26 . 13. where X ∈ I ≥ 0. except IO / M is not included. 20 for example.Solutions Manual 12.Computer Systems Organization and Architecture . Start each value at location 4X. This is the same as the previous problem. This is the same as the previous problem. 16. except IO / M is not included. 15. Copyright © 2001 Addison Wesley . 14.

Computer Systems Organization and Architecture . This is the same as the previous problem. 18.Solutions Manual 17. except IO / M is not included.All Rights Reserved Page 27 . Copyright © 2001 Addison Wesley .

Computer Systems Organization and Architecture . Copyright © 2001 Addison Wesley .All Rights Reserved Page 28 .Solutions Manual 19.

Solutions Manual 20. Copyright © 2001 Addison Wesley .All Rights Reserved Page 29 .Computer Systems Organization and Architecture .

Copyright © 2001 Addison Wesley .All Rights Reserved Page 30 .Solutions Manual 21.Computer Systems Organization and Architecture .

Memory subsystem: Copyright © 2001 Addison Wesley .Solutions Manual 22.All Rights Reserved Page 31 .Computer Systems Organization and Architecture .

All Rights Reserved Page 32 . I/O subsystem: Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .Solutions Manual 22 (continued).

Solutions Manual Chapter 5 1. a) b) c) 3.All Rights Reserved Page 33 . Y ← Z b) α: W ← X α': Y ← Z c) α': W ← X 2.Computer Systems Organization and Architecture . a) α: W ← X. a) α: X ← Y β: X ← Y' b) α: X ← 0 β: X ← X' 4. a) b) 5. Copyright © 2001 Addison Wesley .

Computer Systems Organization and Architecture .All Rights Reserved Page 34 . a) b) c) 7. Copyright © 2001 Addison Wesley .Solutions Manual 6.

a) b) c) d) e) f) g) h) 9.All Rights Reserved Page 35 . a) b) c) d) e) f) g) h) 0011 0010 0000 0100 0100 1100 1000 0001 0011 0010 0000 0101 0100 1100 1000 0001 1011 0010 0000 0100 1100 1100 1000 0001 1001 0000 0010 0000 0000 1001 1001 0000 0000 0111 0010 1010 0100 0001 1100 1010 0000 0111 0010 1011 1100 0001 1100 1010 1000 0111 0010 1010 1100 0001 1100 1010 0011 1001 0101 0000 0000 1000 0011 1001 1011 0010 1111 0000 0010 1100 1011 1100 1011 0010 1111 0000 0010 1100 1011 1100 0011 0010 1111 0000 0010 1100 1011 1100 1001 0111 1000 0000 0000 0101 1001 0111 Copyright © 2001 Addison Wesley . a) b) c) d) e) f) g) h) 10.Solutions Manual 8.Computer Systems Organization and Architecture .

a) b) c) d) Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .All Rights Reserved Page 36 .Solutions Manual 11.

a) b) c) d) 13.Computer Systems Organization and Architecture .Solutions Manual 12.0 X[(n -2)-0] ← X[(n -1)-1] X ← X[(n -5)-0].X[(n -1)-4] Copyright © 2001 Addison Wesley .( n -1)] X ← X[0. a) b) c) d) e) f) g) X ← 0.0000 X ← 0000.X[(n-2)-1] X ← X[(n -2)-0.All Rights Reserved Page 37 .( n -1)-1] X[(n -2)-0] ← X[(n -3)-0].

Define X1X0 = 00 (S0). I is the input bit. M ← I' X2 ← 0. X0 ← 0 X0 ← 1. M ← 1 X2 ← 1 X2 ← 0 X2 ← 0. X0 ← I. X0 ← I X2 ← 0. 01 (S1). 01 (S1). X1 ← 1. X0 ← 1. X0 ← I X1 ← 0. I is the input bit. 11 (S3). X1 ← 0. M ← 0 X0 ← I. X0 ← I. M ← 1 X1 ← 0. X1 ← 0 X2 ← 1. Copyright © 2001 Addison Wesley . X1'X0'I': X1'X0'I: X1'X0I': X1'X0I: X1X0'I': X1X0I': X1X0I: M←0 X0 ← 1. X0 ← 1 X2 ← 1. M ← 0 X1 ← 0. M ← I' Simplest solution (combining states) 1: X2'X1'X0' + X2'X1X0 I' + X2X1X0': X2 ← X1. M ← 0 X0 ← 0 X1 ← 1. X1 ← 1.Computer Systems Organization and Architecture . X0 ← 0. Define X1X0 = 00 (S0).All Rights Reserved Page 38 . X0 ← I M ← X2'X1X0 I' 17. M ← 0 X1 ← 0. X0 ← 0 X1 ← 1. X0 ← I X2 ← 1. 10 (S2). X0 ← 1 X2 ← 0. M ← 0 X1 ← 1. M ← 0 X0 ← 0 Simpler solution (one RTL statement per state) X2'X1'X0': X2'X1'X0: X2'X1X0': X2'X1X0: X2X1'X0': X2X1'X0: X2X1X0': X2X1X0: X0 ← I. X0 ← I X2 ← 1. X0 ← 1 X2 ← 1. Brute force solution (one RTL statement per input value per state) X2'X1'X0'I': X2'X1'X0'I: X2'X1'X0I': X2'X1'X0I: X2'X1X0'I': X2'X1X0'I: X2'X1X0I': X2'X1X0I: X2X1'X0'I': X2X1'X0'I: X2X1'X0I': X2X1'X0I: X2X1X0'I': X2X1X0'I: X2X1X0I': M←0 X0 ← 1. 11 (S3). X1 ← 1 X1 ← 0. X0 ← 0. 16. X1 ← 0. M ← 0 X1 ← 1. X0 ← 0 X2 ← 0. M ← 0 15. 10 (S2).Solutions Manual 14. X1 ← X0.

else next_state <= S2. if (I='0') then next_state <= S0. end case. entity string_checker is port( I. state_transition: process(clk) begin if rising_edge(clk) then present_state <= next_state. end a_string_checker. begin state_check_string: process(present_state. when S1 => M<='0'. end if. end if. if (I='0') then next_state <= S0. Copyright © 2001 Addison Wesley . end if. end if. S1. S2.All Rights Reserved Page 39 . end if.I) begin case present_state is when S0 => M<='0'. end string_checker. when S2 => M<='0'. when S3 => M<='1'.std_logic_1164. M: out std_logic ). end process state_check_string.Computer Systems Organization and Architecture .clk: in std_logic. library IEEE. else next_state <= S1. if (I='0') then next_state <= S3. use IEEE. architecture a_string_checker of string_checker is type states is (S0. else next_state <= S1. if (I='0') then next_state <= S0. signal present_state. end process state_transition. else next_state <= S2.Solutions Manual 18.all. S3). next_state: states.

clk) begin if rising_edge(clk) then X1 <= (X1 and (not X0)) or ((not X1) and X0 and I).std_logic_1164. library IEEE.Computer Systems Organization and Architecture . end a_string_checker. entity string_checker is port( I.all. architecture a_string_checker of string_checker is begin cct_string_checker: process(X1. M: out std_logic ). X0 <= ((not X1) and (not X0) and I) or (X1 and (not X0) and (not I)) or (X1 and X0 and I).X0: buffer std_logic. end if.I. Copyright © 2001 Addison Wesley . use IEEE. end string_checker.X0. M <= X1 AND X0. X1.Solutions Manual 19.clk: in std_logic.All Rights Reserved Page 40 . end process cct_string_checker.

std_logic_1164. S4. else next_state <= S7. Copyright © 2001 Addison Wesley . S3. if (I='0') then next_state <= S2. end if. if (I='0') then next_state <= S0. next_state: states. when S3 => M<='0'. M: out std_logic ). end case. else next_state <= S5. else next_state <= S7. end string_checker. if (I='0') then next_state <= S6.clk: in std_logic. if (I='0') then next_state <= S6.Solutions Manual 20. S5. S6. S2. end process state_transition.All Rights Reserved Page 41 . else next_state <= S5. when S5 => M<='0'. use IEEE. if (I='0') then next_state <= S0. when S1 => M<='0'. begin state_check_string: process(present_state. architecture a_string_checker of string_checker is type states is (S0. entity string_checker is port( I. if (I='0') then next_state <= S4. else next_state <= S1.all. end if. end if. end if. when S2 => M<='0'. if (I='0') then next_state <= S4. else next_state <= S3. when S6 => M<='1'. when S4 => M<='0'. end if. end if. state_transition: process(clk) begin if rising_edge(clk) then present_state <= next_state. else next_state <= S1. end a_string_checker. else next_state <= S3. end process state_check_string. end if.I) begin case present_state is when S0 => M<='0'. S7).Computer Systems Organization and Architecture . if (I='0') then next_state <= S2. library IEEE. when S7 => M<='0'. S1. end if. end if. signal present_state.

G<='0'. <= S25. when S5 => R<='1'. M <= X2 and X1 and (not X0).clk: in std_logic. else next_state <= SN. <= S5. S25. S0.std_logic_1164. <= S15. architecture a_toll_booth_controller of toll_booth_controller is type states is (SN.Solutions Manual 21. end if.G. R. <= S30. end process cct_string_checker.All Rights Reserved Page 42 . library IEEE. use IEEE. S30.X0. SP.X1. next_state: states. when S0 => R<='1'. SC). <= S10. end string_checker. elsif (I1 = '0' AND I0 = '1') then next_state elsif (I1 = '1' AND I0 = '0') then next_state elsif (I1 = '1' AND I0 = '1') then next_state else next_state <= S0. Copyright © 2001 Addison Wesley . S15. end if.Computer Systems Organization and Architecture .I0. end a_string_checker. end if.A: out std_logic ).X0: buffer std_logic. X2. X0 <= I.all. 22. if (C='1') then next_state <= S0.clk: in std_logic. if (C='0') then next_state <= SC. A<='0'.clk) begin if rising_edge(clk) then X2 <= X1. use IEEE. if (C='0') then next_state <= SC. G<='0'. begin state_toll_booth_controller: process(present_state. M: out std_logic ). library IEEE. end if. S5.I. X1 <= X0.I0) begin case present_state is when SN => R<='1'.C. <= S10. end toll_booth_controller. entity toll_booth_controller is port( I1. A<='0'. S10. signal present_state.I1. S20.all.std_logic_1164. G<='0'. architecture a_string_checker of string_checker is begin cct_string_checker: process(X1. elsif (I1 = '0' AND I0 = '1') then next_state elsif (I1 = '1' AND I0 = '0') then next_state elsif (I1 = '1' AND I0 = '1') then next_state else next_state <= S5. A<='0'. entity string_checker is port( I.

A<='1'. elsif (I1 = '0' AND I0 = '1') then next_state <= S15. end if. else next_state <= S25. end case. A<='0'. state_transition: process(clk) begin if rising_edge(clk) then present_state <= next_state. G<='0'. G<='0'. A<='0'. when SC => R<='1'. else next_state <= S15. elsif (I1 = '1') then next_state <= SP. A<='0'. if (C='0') then next_state <= SC. elsif (I1 = '0' AND I0 = '1') then next_state <= S25. elsif (I1 = '1' AND I0 = '0') then next_state <= S30. elsif (I1 = '0' AND I0 = '1') then next_state <= S30. end process state_transition. else next_state <= S20. end if. A<='0'. elsif (I1 = '0' AND I0 = '1') then next_state <= S20. when SP => R<='0'. end a_toll_booth_controller. else next_state <= S30. if (C='0') then next_state <= SN. end if. else next_state <= SP. Copyright © 2001 Addison Wesley . if (C='0') then next_state <= SC. elsif (I1 = '1' AND I0 = '0') then next_state <= S25. G<='0'. elsif (I1 = '1' AND I0 = '1') then next_state <= SP. end if. end if. G<='0'.Solutions Manual when S10 => R<='1'. elsif (I1 = '1' AND I0 = '1') then next_state <= SP. G<='0'. elsif (I1 = '1' OR I0 = '1') then next_state <= SP. when S25 => R<='1'. if (C='0') then next_state <= SC. else next_state <= SC. end process state_toll_booth_controller. if (C='0') then next_state <= SC. A<='0'. end if.Computer Systems Organization and Architecture .All Rights Reserved Page 43 . end if. end if. elsif (I1 = '1' AND I0 = '1') then next_state <= SP. if (C='1') then next_state <= S0. A<='0'. when S15 => R<='1'. when S30 => R<='1'. elsif (I1 = '1' AND I0 = '0') then next_state <= S20. when S20 => R<='1'. G<='1'. G<='0'. else next_state <= S10. if (C='0') then next_state <= SC.

all. R. end toll_booth_controller.clk) begin if rising_edge(clk) then X3 <= not C. Copyright © 2001 Addison Wesley .A: out std_logic ).G.Solutions Manual 23. use IEEE.C. end if. end a_toll_booth_controller. R <= X3 or (not X2) or (not X1) or (not X0). entity toll_booth_controller is port( I1.std_logic_1164.X1. X3.X0: buffer std_logic. G <= (not X3) and X2 and X1 and X0.All Rights Reserved Page 44 .I1. X2 <= ((not X3) and C and I1 and I0) or ((not X3) and (X2 or X1) and C and I1 and (not I0)) or ((not X3) and (X2 or (X1 and X0)) and C and (not I1) and I0) or (X2 and C and (not I1) and (not I0)).clk: in std_logic.X2. architecture a_toll_booth_controller of toll_booth_controller is begin cct_toll_booth_controller: process(X3.I0. X0 <= ((not X3) and (X2 or X1 or (not X0)) and C and I1 and I0) or ((not X3) and (X0 or (X2 and X1)) and C and I1 and (not I0)) or ((not X3) and ((not X0) or (X2 and X1)) and C and (not I1) and I0) or ((not X3) and X0 and C and (not I1) and (not I0)) or (X3 and X0 and (not C)) or ((not X3) and ((not X2) or (not X1) or (not X0)) and (not C)).X2. library IEEE. X1 <= ((not X3) and (X2 or X1 or X0) and C and I1 and I0)or ((not X3) and (X2 or (not X1)) and C and I1 and (not I0)) or ((not X3) and (((not X1) and X0) or (X1 and (not X0)) or (X2 and X1 and X0)) and C and (not I1) and I0) or (X1 and X0 and C and (not I1) and (not I0)). A <= X3 and (not X2) and (not X1) and X0.C.I0.X0.X1.Computer Systems Organization and Architecture . end process cct_toll_booth_controller.

All Rights Reserved Page 45 . PC ← PC + 1 INCAND 1XAAAAAA AC ← (AC + 1) ^ M[AAAAAA] This is one of many possible solutions. 4. 3. AC ← AC + 1 ADD12: AC ← AC + DR SKIP1: PC ← PC + 1 Instruction Instruction Code Operation ADDADD 00AAAAAA AC ← AC + M[AAAAAA] + M[AAAAAA + 1] ANDSKIP 01AAAAAA AC ← AC ^ M[AAAAAA]. 2.Computer Systems Organization and Architecture . JMP11: PC ← AR JMP12: PC ← PC + 1 INC21: AC ← AC + 1 INC22: AC ← AC + 1 ADD11: DR ← M.Solutions Manual Chapter 6 1. Copyright © 2001 Addison Wesley .

9. Change INC input IA3 to IA2. Y. AR ← DR[5. bit 5 of DR is sent to both IR and AR. Instruction CLEAR 10. Change the input to the counter to X.5]. Change CLR input IA2 to IA3. ii) Add CLEAR1 to the inputs of the OR gate driving counter CLR..) Arbitrarily assign CLEAR1 to decoder output 15. X'. i) IR must have 3 bits instead of 2.. It receives bus bits 7. AR ← 20H AC ← 0 Next state FETCH2 FETCH3 CLEAR1 FETCH1 8.) 6.1]. X ∨ Y.All Rights Reserved Page 46 . PC ← 1 IR ← 111.. (IR must have 3 bits instead of 2. Test program: 0: CLEAR State FETCH1 FETCH2 FETCH3 CLEAR1 Operations performed AR ← 0 DR ← E0H. During FETCH3.. AR ← DR[5.4]. (IR must have 4 bits instead of 2.Computer Systems Organization and Architecture .0] AC ← 0 7.0] R ← AC AC ← R Copyright © 2001 Addison Wesley .) FETCH3: MVAC1: MOVR1: IR ← DR[7. FETCH3: CLEAR1: IR ← DR[7.5 as its inputs.(IR2 ^ IR1 ^ IR0).. iii) New control signal ACCLR = CLEAR1. ii) AC needs a CLR input (ACCLR is a new control signal which connects to the new CLR input. i) New input to counter: 1..Solutions Manual 5.IR[2.

Arbitrarily assign MVAC1 and MOVR1 to decoder outputs 6 and 7. It receives data from the bus and sends data to the bus through tri-state buffers. Test program: Instruction MVAC MOVR Copyright © 2001 Addison Wesley . It requires only a LD signal. 0: 1: MVAC MOVR State FETCH1 FETCH2 FETCH3 MVAC1 FETCH1 FETCH2 FETCH3 MOVR1 Operations performed AR ← 0 DR ← E0H. New control signals RLOAD = MVAC1 and RBUS = MOVR1.) IR must have 4 bits instead of 2. IR[3. iii) The ALU is modified as shown below. This is shown below. bit DR[5. AR ← 30H AC← 1 Next state FETCH2 FETCH3 MVAC1 FETCH1 FETCH2 FETCH3 MOVR1 FETCH1 13.4] is sent to both IR and AR. AR ← 20H R←1 AR ← 1 DR ← F0H.All Rights Reserved Page 47 .2]. This is shown below.Computer Systems Organization and Architecture . i.. PC ← 1 IR ← 1110. ii) Register R is added to the CPU.. PC ← 2 IR ← 1111. i) ii) iii) iv) New input to counter: (IR3 ^ IR2 ^ IR1)'.. Add MOVR1 to the inputs of the OR gate generating ACLOAD. During FETCH3.4 as its inputs. respectively. 12.).(IR3 ^ IR2 ^ IR1 ^ IR0.Solutions Manual 11. It receives bus bits 7. Add MVAC1 and MOVR1 to the inputs of the OR gate driving counter CLR.

ALUS1 = ADD1 ∨ SUB1 ∨ INAC1 ALUS2 = SUB1 ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1 ALUS4 = SUB1 ∨ INAC1 ALUS5 = XOR1 ∨ NOT1 ALUS6 = OR1 ∨ NOT1 ALUS7 = AND1 ∨ OR1 ∨ XOR1 ∨ NOT1 Copyright © 2001 Addison Wesley .7] 0010XX0 0010XX0 1010XX0 1100XX0 1001XX0 0000XX0 XXXX001 XXXX011 XXXX101 XXXX111 16. 17. PCLOAD = JUMP3 ∨ JMPZY3 ∨ JPNZY3 PCINC = FETCH2 ∨ LDAC1 ∨ LDAC2 ∨ STAC1 ∨ STAC2 ∨ JMPZN1 ∨ JMPZN2 ∨ JPNZN1 ∨ JPNZN2 DRLOAD = FETCH2 ∨ LDAC1 ∨ LDAC2 ∨ LDAC4 ∨ STAC1 ∨ STAC2 ∨ STAC4 ∨ JUMP1 ∨ JUMP2 ∨ JMPZY1 ∨ JMPZY2 ∨ JPNZY1 ∨ JPNZY2 TRLOAD = LDAC2 ∨ STAC2 ∨ JUMP2 ∨ JMPZY2 ∨ JPNZY2 IRLOAD =FETCH3 RLOAD = MVAC1 ACLOAD = LDAC5 ∨ MOVR1 ∨ ADD1 ∨ SUB1 ∨ INAC1 ∨ CLAC1 ∨ AND1 ∨ OR1 ∨ XOR1 ∨ NOT1 ZLOAD = ADD1 ∨ SUB1 ∨ INAC1 ∨ CLAC1 ∨ AND1 ∨ OR1 ∨ XOR1 ∨ NOT1 State LDAC5 MOVR1 ADD1 SUB1 INAC1 CLAC1 AND1 OR1 XOR1 NOT1 ALUS[1..Computer Systems Organization and Architecture .Solutions Manual 14. Micro-operation ADD1 shl neg ad1 Adder inputs AC + BUS + 0 AC + AC + 0 0 + BUS' + 0 AC + BUS + 1 15. All operations except AND are performed by the parallel adder.All Rights Reserved Page 48 .

Z ← 0) (jump is not taken) (jump is taken) (skipped by JMPZ 0018) (AC ← 0. driven by new control signal RDCR. Instruction SETR Copyright © 2001 Addison Wesley . 0: LDAC 0000 NOP MVAC ADD INAC XOR AND 9: JMPZ 000D NOP D: JPNZ 0009 NOT JMPZ 0009 JPNZ 0018 NOP 18: CLAC OR SUB MOVR STAC 0030 AND JUMP 0000 SETR1: R ← 0 SETR2: R ← R . Z ← 0) (AC ← 3. 20. R needs two additional inputs: CLR. Z ← 0) (start again) 19. SETR1 = ISETR ^ T3. ii) Add SETR1 to the OR gate driving INC of the time counter and SETR2 to the OR gate driving CLR of the time counter. PC ← 1 IR ← 11. and SETR2 = ISETR ^ T4. Test program: 0: SETR State FETCH1 FETCH2 FETCH3 SETR1 SETR2 Operations performed AR ← 0 DR ← 11H.) Add hardware to generate ISETR = I7' ^ I6' ^ I5' ^ I4 ^ I3' ^ I2' ^ I1' ^ I0'.Computer Systems Organization and Architecture . Z ← 1) (jump is taken) (skipped by JMPZ 000D) (jump is not taken) (AC ← FF. The student can execute the following program using the Relatively Simple CPU simulator to verify that each instruction performs properly. iii) New control signals RCLR = SETR1 and RDCR = SETR2.Solutions Manual 18. Z ← 0) (AC ← 0. i. 21. Z ← 1) (AC ← 1) (M[30] ← 1) (AC ← 1. AR ← 1 R←0 R ←FF Next state FETCH2 FETCH3 SETR1 SETR2 FETCH1 22. driven by new control signal RCLR. Z ← 0) (AC ← 0.1 (AC ← 1) (R ← 1) (AC ← 2. Z ← 0) (AC ← 2. Z ← 1) (AC ← 1. and DCR.All Rights Reserved Page 49 .

i.. and IXORB. and XORB1 to generate BBUS. i. and add hardware to generate ADDB1 = IADDB ^ T3.All Rights Reserved Page 50 .B AC ← AC ^ B AC ← AC ∨ B AC ← AC ⊕ B 24.) No ALU changes are needed! ii) Register B is added to the CPU. and XOR1.7] such that ADD1 is replaced by ADD1 ∨ ADDB1. ORB1. iv) Change ALUS[1. ISUBB. ORB1 = IORB ^ T3. IANDB. and so on for SUB1. ANDB1. OR1. ANDB1 = IANDB ^ T3. and XORB1 = IXORB ^ T3. 25. yielding: ALUS1 = ADD1 ∨ ADDB1 ∨ SUB1 ∨ SUBB1 ∨ INAC1 ALUS2 = SUB1 ∨ SUBB1 ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1∨ ADDB1 ALUS4 = SUB1 ∨ SUBB1∨ INAC1 ALUS5 = XOR1 ∨ XORB1 ∨ NOT1 ALUS6 = OR1 ∨ ORB1 ∨ NOT1 ALUS7 = AND1 ∨ ANDB1 ∨ OR1 ∨ ORB1 ∨ XOR1 ∨ XORB1 ∨ NOT1 Copyright © 2001 Addison Wesley .) Add the hardware shown below to generate IADDB. This is shown below.Solutions Manual 23. IORB. iii) Add the same five signals to the OR gate driving CLR of the counter.Computer Systems Organization and Architecture . SUBB1 = ISUBB ^ T3. It sends data to the bus through tri-state buffers but does not receive data from the bus (since it is never loaded). ii) OR together ADDB1. ADDB1: SUBB1: ANDB1: ORB1: XORB1: AC ← AC + B AC ← AC . SUBB1. AND1.

Solutions Manual 26.2 = 0 27.. iii) Change the input to Z as shown below.6]. State diagram and RTL code: FETCH1: FETCH2: FETCH3: COM1: JREL1: JREL2: OR1: OR2: SUB11: SUB12: AR ← PC DR ← M.. Fetch cycles not shown. Copyright © 2001 Addison Wesley . and INC = INAC1.Computer Systems Organization and Architecture . except for the data input to PC. AR ← DR[5. ZLOAD is unchanged. shown below.) Remove CLAC1 and INAC1 as inputs to the OR gate which generates ACLOAD.6. ii) Add control inputs to AC: CLR = CLAC1.0] DR ← M AC ← AC ∨ DR DR ← M AC ← AC + DR' The register section is the same as Figure 6.. i.0] AC ← AC' DR ← M PC ← PC + DR[5. PC ← PC + 1 IR ← DR[7. Initially AC = 1 and B = 2. Instruction ORB ADDB ANDB XORB SUBB State ORB1 ADDB1 ANDB1 XORB1 SUBB1 Operations performed AC ← 1 ∨ 2 = 3 AC ← 3 + 2 = 5 AC ← 5 ^ 2 = 0 AC ← 0 ⊕ 2 = 2 AC ← 2 .All Rights Reserved Page 51 . 28.

Solutions Manual ARLOAD = FETCH1 ∨ FETCH3 PCLOAD = JREL2 PCINC =FETCH2 PCBUS = FETCH1 DRLOAD = MEMBUS = READ = FETCH2 ∨ JREL1∨ OR1∨ SUB11 DRBUS = FETCH3 ∨ JREL2 ∨ OR2 ∨ SUB12 ACLOAD = COM1 ∨ OR2 ∨ SUB12 IRLOAD = FETCH3 Control signals: ALU: Control unit: Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .All Rights Reserved Page 52 .

Computer Systems Organization and Architecture . AR ← PC DR ← M. AC ← 0 Control signals: ARLOAD = FETCH1 ∨ FETCH3 ∨ STO2 PCLOAD = JUMP2 ∨ JREL2 PCINC = FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ SKIP1 PCCLR =RST1 PCBUS = FETCH1 ∨ FETCH3 PCMUX = JUMP2 DRLOAD = FETCH2 ∨ LDI1 ∨ STO1 ∨ STO3 ∨ ADD1 ∨ OR1 ∨ JUMP1 DRBUS = FETCH3 ∨ LDI2 ∨ STO2 ∨ STO4 ∨ ADD2 ∨ OR2 ∨ JUMP2 ∨ JREL1 ACLOAD = LDI2 ∨ ADD2 ∨ OR2 ACCLR =RST1 ACBUS =STO3 IRLOAD =FETCH3 MEMBUS = READ = FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ JUMP1 BUSMEM = WRITE = STO4 Copyright © 2001 Addison Wesley .All Rights Reserved Page 53 . PC ← PC + 1 ADD2: AC ← AC + DR OR1: DR ← M.. PC ← PC + 1 IR ← DR[7..0] SKIP1: PC ← PC + 1 RST1: PC ← 0. PC ← PC + 1 AC ← DR DR ← M. PC ← PC + 1 OR2: AC ← AC ∨ DR JUMP1: DR ← M JUMP2: PC ← DR JREL1: PC ← PC + 000DR[4.Solutions Manual 29. PC ← PC + 1 AR ← DR DR ← AC M ← DR ADD1: DR ← M.5]. State diagram and RTL code: FETCH1: FETCH2: FETCH3: LDI1: LDI2: STO1: STO2: STO3: STO4: AR ← PC DR ← M.

All Rights Reserved Page 54 .Computer Systems Organization and Architecture .Solutions Manual Register section: ALU: Copyright © 2001 Addison Wesley .

Solutions Manual Control unit: FETCH1 = FETCH2 = FETCH3 = LDI1 = LDI2 = STO1 = STO2 = STO3 = STO4 = T0 T1 T2 ILDI ^ T3 ILDI ^ T4 ISTO ^ T3 ISTO ^ T4 ISTO ^ T5 ISTO ^ T6 ADD1 = ADD2 = OR1 = OR2 = JUMP1 = JUMP2 = JREL1 = JREL2 = SKIP1 = RST1 = IADD ^ T3 IADD ^ T4 IOR ^ T3 IOR ^ T4 IJUMP ^ T3 IJUMP ^ T4 IJREL ^ T3 IJREL ^ T4 ISKIP ^ T3 IRST ^ T3 30. Modified state diagram: Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .All Rights Reserved Page 55 .

DR ← M.. PC ← PC + 1 CALL2: TR ← DR. INC). DR ← PC[15. PUSHAC1: PUSHAC2: PUSHAC3: POPAC1: POPAC2: POPAC3: PUSHR1: PUSHR2: PUSHR3: POPR1: POPR2: POPR3: SP ← SP .. DR ← AC AR ← SP M ← DR AR ← SP DR ← M. SP ← SP + 1.Computer Systems Organization and Architecture ..8]..DR RET1: AR ← SP RET2: DR ← M.15.Solutions Manual Modified RTL code: LDSP1: DR ← M. DEC.1 CALL4: AR ← SP CALL5: M ← DR. TR2 (with LD.TR Modified register section: (shown below) • • • • New registers: SP (with LD. PC ← PC + 1 LDSP3: SP ← DR.1.0] All other connections remain the same as shown in Figure 6.8] or BUS[7. PC ← PC + 1 LDSP2: TR ← DR. receives data directly from DR) New control signal: AR adds a DEC signal New data path: DR can receive data from BUS[15. AR ← AR .TR CALL1: DR ← M.All Rights Reserved Page 56 . SP ← SP + 1 AC ← DR SP ← SP . SP ← SP + 1 R ← DR Copyright © 2001 Addison Wesley . DR ← R AR ← SP M ← DR AR ← SP DR ← M. SP ← SP + 1 RET4: PC ← DR.1.1.1 CALL6: DR ← PC[7. DR ← M. PC ← PC + 1 CALL3: TR2 ← DR. AR ← AR + 1 RET3: TR ← DR. SP ← SP .0] CALL7: M ← DR CALL8: PC ← TR2. SP ← SP . AR ← AR + 1. DR ← M. AR ← AR + 1.

Solutions Manual New control signals: ARDEC = SPLOAD = SPINC = SPDEC = SPBUS = DRSEL = TR2LOAD = TR2BUS = Modified control signals: ARLOAD = ARINC = PCLOAD = PCINC = PCBUS = DRLOAD = (original value) ∨ CALL4 ∨ RET1 ∨ PUSHAC2 ∨ POPAC1 ∨ PUSHR2 ∨ POPR1 (original value) ∨ LDSP1 ∨ CALL1 ∨ RET2 (original value) ∨ CALL8 ∨ RET4 (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 (original value) ∨ CALL3 ∨ CALL6 (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨ CALL3 ∨ CALL6 ∨ RET2 ∨ RET3 ∨ PUSHAC1 ∨ POPAC2 ∨ PUSHR1 ∨ POPR2 (original value) ∨ LDSP3 ∨ RET4 (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ POPAC3 ∨ PUSHR3 ∨ POPR3 (original value) ∨ LDSP2 ∨ CALL2 ∨ RET3 (original value) ∨ LDSP3 ∨ CALL8 ∨ RET4 (original value) ∨ POPR3 (original value) ∨ PUSHR1 (original value) ∨ POPAC3 (original value) ∨ PUSHAC1 (original value) ∨ POPAC3 (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨ RET2 ∨ RET3 ∨ POPAC2 ∨ POPR2 (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ PUSHR3 (original value) ∨ CALL5 ∨ CALL7 ∨ PUSHAC3 ∨ PUSHR3 CALL5 LDSP3 RET2 ∨ RET3 ∨ POPAC2 ∨ POPR2 CALL3 ∨ CALL5 ∨ PUSHAC1 ∨ PUSHR1 CALL4 ∨ RET1 ∨ PUSHAC2 ∨ POPAC1 ∨ PUSHR2 ∨ POPR1 CALL3 CALL3 CALL8 DRHBUS = DRLBUS = TRLOAD = TRBUS = RLOAD = RBUS = ACLOAD = ACBUS = ALUS1 = MEMBUS = BUSMEM = WRITE = Copyright © 2001 Addison Wesley .All Rights Reserved Page 57 .Computer Systems Organization and Architecture .

The decoder now outputs T0 . Modify the INC and CLR inputs to the counter as follows: INC = (original value) ∨ LDSP1 ∨ LDSP2 ∨ CALL1 ∨ CALL2 ∨ CALL3 ∨ CALL4 ∨ CALL5 ∨ CALL6 ∨ CALL7 ∨ RET1 ∨ RET2 ∨ RET3 ∨ PUSHAC1 ∨ PUSHAC2 ∨ POPAC1 ∨ POPAC2 ∨ PUSHR1 ∨ PUSHR2 ∨ POPR1 ∨ POPR2 CLR = (original value) ∨ LDSP3 ∨ CALL8 ∨ RET4 ∨ PUSHAC3 ∨ POPAC3 ∨ PUSHR3 ∨ POPR3 LDSP1 = LDSP2 = LDSP3 = CALL1 = CALL2 = CALL3 = CALL4 = CALL5 = CALL6 = CALL7 = CALL8 = RET1 = RET2 = RET3 = RET4 = ILDSP ^ T3 ILDSP ^ T4 ILDSP ^ T5 ICALL ^ T3 ICALL ^ T4 ICALL ^ T5 ICALL ^ T6 ICALL ^ T7 ICALL ^ T8 ICALL ^ T9 ICALL ^ T10 IRET ^ T3 IRET ^ T4 IRET ^ T5 IRET ^ T6 PUSHAC1 = PUSHAC2 = PUSHAC3 = POPAC1 = POPAC2 = POPAC3 = PUSHR1 = PUSHR2 = PUSHR3 = POPR1 = POPR2 = POPR3 = IPUSHAC ^ T3 IPUSHAC ^ T4 IPUSHAC ^ T5 IPOPAC ^ T3 IPOPAC ^ T4 IPOPAC ^ T5 IPUSHR ^ T3 IPUSHR ^ T4 IPUSHR ^ T5 IPOPR ^ T3 IPOPR ^ T4 IPOPR ^ T5 Copyright © 2001 Addison Wesley .All Rights Reserved Page 58 .Computer Systems Organization and Architecture .T10. Add a second instruction decoder as shown below.Solutions Manual Control unit modifications: • • • Increase the counter size to 4 bits.

IR MAP 00 0011 01 0101 10 0111 11 1000 State MAP = IR1 ^ IR0.. Address S E L 0 0 1 0 0 0 0 0 0 FETCH1 FETCH2 FETCH3 ADD1 ADD2 AND1 AND2 JMP1 INC1 0000 (0) 0001 (1) 0010 (2) 0011 (3) 0100 (4) 0101 (5) 0110 (6) 0111 (7) 1000 (8) A R P C 1 0 0 0 0 0 0 0 0 A I D R 0 0 1 0 0 0 0 0 0 P C I N 0 1 0 0 0 0 0 0 0 P C D R 0 0 0 0 0 0 0 1 0 D R M 0 1 0 1 0 1 0 0 0 P L U S 0 0 0 0 1 0 0 0 0 A N D 0 0 0 0 0 0 1 0 0 A C I N 0 0 0 0 0 0 0 0 1 ADDR 0001 0010 XXXX 0100 0000 0110 0000 0000 0000 3. M1 M2 NOP NOP DR ← M PC ← PC + 1 AC ← AC' AC ← AC + 1 DR ← DR + 1 PC ← PC + DR[5.(IR1 ^ IR0)' 2.Computer Systems Organization and Architecture .0] AR ← PC IR.Solutions Manual Chapter 7 1. IR0'.AR ← DR AC ← AC ⊕ DR M ← DR Required Micro-operations in these two rows must be allocated the same relative to each other The remaining operations are assigned arbitrarily Copyright © 2001 Addison Wesley . IR1 ⊕ IR0.All Rights Reserved Page 59 .

Test program: 0: 1: 2: 3: 4: 5: ADD 4 AND 5 INC JMP 0 27H 39H Address 0000 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 Micro-operations ARPC DRM. AR ← 00H AC ← 21H + 1 = 22H AR ← 3 DR ← 80H. AR ← 04H DR ← 27H AC ← 0 + 27H = 27H AR ← 1 DR ← 45H. AR ← 00H PC ← 0 Next Address 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 0000 AND 5 INC JMP 0 Copyright © 2001 Addison Wesley . PC ← 4 IR ← 10. PC ← 1 IR ← 00. AR ← 04H DR ← 27H AC ← 0 + 27H = 27H AR ← 1 DR ← 45H.Computer Systems Organization and Architecture . PC ← 4 IR ← 10. PCIN AIDR PCDR Operations performed AR ← 0 DR ← 04H. PCIN AIDR ACIN ARPC DRM. AR ← 05H DR ← 39H AC ← 27H ^ 39H = 31H AR ← 2 DR ← C0H. PCIN AIDR DRM AND ARPC DRM.Solutions Manual 4. PC ← 2 IR ← 01.All Rights Reserved Page 60 . AR ← 00H PC ← 0 Next Address 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 0000 Instruction ADD 4 AND 5 INC JMP 0 State FETCH1 FETCH2 FETCH3 ADD1 ADD2 FETCH1 FETCH2 FETCH3 AND1 AND2 FETCH1 FETCH2 FETCH3 INC1 FETCH1 FETCH2 FETCH3 JMP1 5. AR ← 05H DR ← 39H AC ← 27H ^ 39H = 31H AR ← 2 DR ← C0H. PC ← 1 IR ← 00. Instruction ADD 4 State FETCH1 FETCH2 FETCH3 ADD1 ADD2 FETCH1 FETCH2 FETCH3 AND1 AND2 FETCH1 FETCH2 FETCH3 INC1 FETCH1 FETCH2 FETCH3 JMP1 Address 0000 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 M1 ARPC DRM AIDR DRM PLUS ARPC DRM AIDR DRM AND ARPC DRM AIDR ACIN ARPC DRM AIDR PCDR M2 NOP PCIN NOP NOP NOP NOP PCIN NOP NOP NOP NOP PCIN NOP NOP NOP PCIN NOP NOP Operations performed AR ← 0 DR ← 04H. PC ← 2 IR ← 01. AR ← 00H AC ← 21H + 1 = 22H AR ← 3 DR ← 80H. PC ← 3 IR ← 11. Use the same test program as in problem 4. PCIN AIDR DRM PLUS ARPC DRM. PC ← 3 IR ← 11.

ACLOAD PCBUS. ALUSEL. IRLOAD READ. MEMBUS.Solutions Manual 6. ARLOAD. ARLOAD READ. AR ← 05H DR ← 39H AC ← 27H ^ 39H = 31H AR ← 2 DR ← C0H. MEMBUS. PC ← 2 IR ← 01. ARLOAD. IRLOAD DRBUS. PC ← 3 IR ← 11. PCINC DRBUS. ARLOAD READ. IRLOAD READ. PC ← 4 IR ← 10. PCLOAD Operations performed AR ← 0 DR ← 04H. PCINC DRBUS. DRLOAD. DRLOAD. PCINC DRBUS. MEMBUS. DRLOAD DRBUS. PC ← 1 IR ← 00. DRLOAD DRBUS. IRLOAD ACINC PCBUS. ACLOAD PCBUS. MEMBUS. AR ← 00H PC ← 0 Next Address 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 0000 AND 5 JMP 0 Copyright © 2001 Addison Wesley . ARLOAD READ. DRLOAD. ARLOAD. AR ← 00H AC ← 21H + 1 = 22H AR ← 3 DR ← 80H. MEMBUS.Computer Systems Organization and Architecture . PCINC DRBUS. AR ← 04H DR ← 27H AC ← 0 + 27H = 27H AR ← 1 DR ← 45H. ARLOAD READ.All Rights Reserved Page 61 . DRLOAD. MEMBUS. Use the same test program as in problem 4. Instruction ADD 4 State FETCH1 FETCH2 FETCH3 ADD1 ADD2 FETCH1 FETCH2 FETCH3 AND1 AND2 INC FETCH1 FETCH2 FETCH3 INC1 FETCH1 FETCH2 FETCH3 JMP1 Address 0000 0001 0010 1000 1001 0000 0001 0010 1010 1011 0000 0001 0010 1110 0000 0001 0010 1100 Control Signals PCBUS. ARLOAD.

5].0] and its outputs are 1. During FETCH3. Modified state diagram: (same as for problem 6. ii) AC needs a CLR input (ACCLR is a new control signal which connects to the new CLR input..) Microcode modifications: i) Add mico-operation ACCL.6) FETCH3: CLEAR1: IR ← DR[7.. Register modifications: i) (same as for problem 6.5 as its inputs.0] AC ← 0 Microsequencer modifications: Change the mapping hardware so that its inputs are IR[2..(IR2 ^ IR1 ^ IR0). PCIN AIDR ACCL Copyright © 2001 Addison Wesley .7) IR must have 3 bits instead of 2. bit 5 of DR is sent to both IR and AR.Computer Systems Organization and Architecture . It receives bus bits 7.Solutions Manual 7.IR[2. Set the ACCL field to 0 for all other microinstructions. ii) Add the following to microcode memory. which sets AC ← 0..All Rights Reserved Page 62 . PC ← 1 IR ← 111.1]. State Address S E L 0 0: A R P C 0 A I D R 0 P C I N 0 P C D R 0 D R M 0 P L U S 0 A N D 0 A C I N 0 A C C L 1 ADDR CLEAR1 Verification: Instruction CLEAR 1111 (15) Test program: Address 0000 0001 0010 1111 0000 CLEAR Operations performed AR ← 0 DR ← 04H.. AR ← 04H AC ← 00 Next Address 0001 0010 1111 0000 State FETCH1 FETCH2 FETCH3 CLEAR1 Micro-operations ARPC DRM. AR ← DR[5. Connect this bit of the microsequencer to the CLR input of AC.6) Modified RTL code: (same as for problem 6.

State Address S E L A R L O A D 0 0: P C L O A D 0 P C I N C 0 D M R A C L O A D 0 A C I N C 0 I R L O A D 0 A L U S E L 0 P C B U S 0 D R B U S 0 A C C L R 1 ADDR i) CLEAR1 Verification: Instruction CLEAR 1111 (15) 0 0 0000 Test program: Address 0000 0001 0010 CLEAR Operations performed AR ← 0 DR ← 04H. ii) Add the following to microcode memory. PCINC DRBUS. iii) Add the following to microcode memory. PC ← 1 IR ← 111. PC ← 1 IR ← 111. Set it to 0 for all microinstructions except the microinstruction at address 1111. AR ← 04H AC ← 00 Next Address 0001 0010 1111 0000 State FETCH1 FETCH2 FETCH3 CLEAR1 M1 ARPC DRM AIDR ACCL 9. If it was used.Computer Systems Organization and Architecture . Add control signal output ACCLR to the control signals in microcode memory. IRLOAD ACCLR 0000 Copyright © 2001 Addison Wesley .Solutions Manual 8. ARLOAD READ.) The code for ACCL is M1 = 000. The modifications are the same as in problem 7 with the following exceptions. ii) Connect ACCL to ACCLR. DRLOAD. ARLOAD. a new micro-operation code would have to be created. AR ← 04H AC ← 00 Next Address 0001 0010 1111 State FETCH1 FETCH2 FETCH3 CLEAR1 1111 Control Signals PCBUS. MEMBUS. Label output 0 of the M1 decoder ACCL. (This can be done because the NOP of M1 is never used.All Rights Reserved Page 63 . The modifications are the same as in problem 7 with the following exceptions. State CLEAR1 Verification: Instruction CLEAR Address 1111 SEL 0 0: M1 000 M2 0 ADDR 0000 i) Test program: Address 0000 0001 0010 1111 CLEAR M2 NOP PCIN NOP NOP Operations performed AR ← 0 DR ← 04H.

iii) Add micro-operation ACR (AC ← R)... (same as for problem 6. Copyright © 2001 Addison Wesley . iii) The ALU is modified as shown below. connect it to an OR gate that generates ACBUS and have it directly drive RLOAD. This is shown below.IR[3.4].Solutions Manual 10.Computer Systems Organization and Architecture .) IR must have 4 bits instead of 2.. ii) Register R is added to the CPU.. This is shown below.) Modified RTL code: (same as for problem 6.4] is sent to both IR and AR. bit DR[5.4 as its inputs. ii) Add micro-operation RAC (R ← AC).0] and its outputs are (IR3 ^ IR2 ^ IR1)...All Rights Reserved Page 64 . During FETCH3. It receives bus bits 7.10) (IR must have 4 bits instead of 2.2]. connect it to directly to RBUS and connect it to an OR gate that generates ACLOAD.10) FETCH3: MVAC1: MOVR1: IR ← DR[7. AR ← DR[5.0] R ← AC AC ← R Microsequencer modifications: i) Change the mapping hardware so that its inputs are IR[3.(IR3 ^ IR2 ^ IR1 ^ IR0).11) Register and ALU modifications: i. It requires only a LD signal. It receives data from the bus and sends data to the bus through tri-state buffers. Modified state diagram: (same as for problem 6.

AR ← 30H AC ← 01H Next Address 0001 0010 0110 0000 0001 0010 0111 0000 MOVR State FETCH1 FETCH2 FETCH3 MVAC1 FETCH1 FETCH2 FETCH3 MOVR1 M1 ARPC DRM AIDR NOP ARPC DRM AIDR NOP Copyright © 2001 Addison Wesley . PC ← 2 IR ← 1111. AR ← 30H AC ← 01H Next Address 0001 0010 0110 0000 0001 0010 0111 0000 11. i) Add micro-operations RAC (R ← AC) and ACR (AC ← R) to M2 with the following assignments. State Address S E L 0 0 0: 1: A R P C 0 0 A I D R 0 0 P C I N 0 0 P C D R 0 0 D R M 0 0 P L U S 0 0 A N D 0 0 A C I N 0 0 R A C 1 0 A C R 0 1 ADDR MVAC1 MOVR1 Verification: 0110 (6) 0111 (7) Test program: 0000 0000 MVAC MOVR (Initially AC = 1) Instruction MVAC MOVR State FETCH1 FETCH2 FETCH3 MVAC1 FETCH1 FETCH2 FETCH3 MOVR1 Address 0000 0001 0010 0110 0000 0001 0010 0111 Micro-operations ARPC DRM. The modifications are the same as in problem 10 with the following exceptions. AR ← 20H R ← 01H AR ← 1 DR ← F0H. AR ← 20H R ← 01H AR ← 1 DR ← F0H.All Rights Reserved Page 65 . State MVAC1 MOVR1 Verification: Instruction MVAC Address 0110 0111 SEL 0 0 0: 1: M1 000 000 M2 10 11 ADDR 0000 0000 Test program: Address 0000 0001 0010 0110 0000 0001 0010 0111 MVAC MOVR M2 NOP PCIN NOP RAC NOP PCIN NOP ACR (Initially AC = 1) Operations performed AR ← 0 DR ← E0H. PCIN AIDR ACR Operations performed AR ← 0 DR ← E0H. iii) Modify the existing microinstructions to accommodate the new values for M2 (0 → 00. PCIN AIDR RAC ARPC DRM. PC ← 1 IR ← 1110. iv) Add the following to microcode memory.Solutions Manual Microcode modifications: Add the following to microcode memory.Computer Systems Organization and Architecture . Set the RAC and ACR fields to 0 for all other microinstructions. PC ← 2 IR ← 1111. M2 00 01 10 11 Micro-operation NOP PCIN RAC ACR ii) Use a 2-to-4 decoder to generate the control signals for M2. PC ← 1 IR ← 1110. 1 → 01).

ACLOAD. The modifications are the same as in problem 10 with the following exceptions. The changes in the state diagram and register hardware are the same for either control unit. especially if no new micro-operations are needed. PC ← 1 IR ← 1110. i) Add control signals RLOAD. ACBUS. ii) Add the following to microcode memory. DRLOAD. ALUS2 Operations performed AR ← 0 DR ← E0H. AR ← 20H R ← 01H AR ← 1 DR ← F0H. and ALUS2 to the control signals in microcode memory.Solutions Manual 12.Computer Systems Organization and Architecture . Copyright © 2001 Addison Wesley . AR ← 30H AC ← 01H Next Address 0001 0010 0110 0000 0001 0010 0111 0000 13. MEMBUS. IRLOAD ACBUS. Set them to 0 for all microinstructions except those at addresses 0110 and 0111. State Address S E L A R L O A D 0 0 P C L O A D 0 0 0: 1: P C I N C 0 0 D M R A C L O A D 0 1 A C I N C 0 0 I R L O A D 0 0 A L U S E L 0 0 P C B U S 0 0 D R B U S 0 0 R L O A D 1 0 R B U S P C B U S 1 0 A L U S 2 0 1 ADDR MVAC1 MOVR1 0110 (6) 0111 (7) 0 0 0 0 MVAC MOVR 0 1 0000 0000 Verification: Test program: (Initially AC = 1) Instruction MVAC State FETCH1 FETCH2 FETCH3 MVAC1 FETCH1 FETCH2 FETCH3 MOVR1 Address 0000 0001 0010 0110 0000 0001 0010 0111 MOVR Control Signals PCBUS. RLOAD ARPC DRM. The microcode may require less hardware changes in the control unit than the hardwired control unit. Some points that might be included: • • • The mapping hardware change is equivalent to changing the inputs to the counter in the hardwired controller.All Rights Reserved Page 66 . PCIN AIDR RBUS. RBUS. ARLOAD. PC ← 2 IR ← 1111. PCINC DRBUS. ARLOAD READ.

driven by new control signal RCLR. (IR4 ∨ IR0).Solutions Manual 14.(IR4 ∨ IR1). MEMBUS. AR ← 01H R ← 00H R ← FFH Next state FETCH2 FETCH3 SETR1 SETR2 FETCH1 All other micro-operations 0 0 CLRR 1 0 DECR 0 1 ADDR 63 1 Test program: State FETCH1 FETCH2 FETCH3 SETR1 SETR2 Active signals PCBUS.Computer Systems Organization and Architecture . Microcode and microsequencer modifications: Add micro-operations CLRR (R ← 0) and DECR (R ← R .All Rights Reserved Page 67 .IR4.(IR4 ∨ IR2). Modified state diagram and RTL code: (same as for problem 6. PC ← 1 IR ← 10H.1) to the microcode. ARLOAD READ. PCINC DRBUS.1 Register and ALU modifications: (same as for problem 6. These fields are set to zero for all existing microinstructions.19) SETR1: R ← 0 SETR2: R ← R . IRLOAD CLRR DECR Copyright © 2001 Addison Wesley . and DCR. There are no ALU modifications. i) State SETR1 SETR2 Verification: Instruction SETR Address 62 63 Condition 1 1 0: BT J J SETR Operations performed AR ← 0 DR ← 10H. ii) Change the mapping function to (IR4 ∨ IR3).0. iii) Add the following microinstructions to the microprogram.20) R needs two additional inputs: CLR. ARLOAD. driven by new control signal RDCR. DRLOAD.

Computer Systems Organization and Architecture - Solutions Manual

15.

Modified state diagram and RTL code: (same as for problem 6.23)

ADDB1: SUBB1: ANDB1: ORB1: XORB1:

AC ← AC + B AC ← AC - B AC ← AC ^ B AC ← AC ∨ B AC ← AC ⊕ B (same as for problem 6.24)

Register and ALU modifications:

i.) No ALU changes are needed! ii) Register B is added to the CPU. It sends data to the bus through tri-state buffers but does not receive data from the bus (since it is never loaded). This is shown below.

Microcode and microsequencer modifications: Add micro-operations BPLU (AC ← AC + B), BMIN (AC ← AC - B), BAND (AC ← AC ^ B), BOR (AC ← AC ∨ B), and BXOR (AC ← AC ⊕ B) to the microcode. These fields are set to zero for all existing microinstructions. ii) Change the mapping function to IR3,IR2,IR1,IR0,0,IR4. iii) Change ALUS[1..7] such that ADD1 is replaced by ADD1 ∨ ADDB1, and so on for SUB1, AND1, OR1, and XOR1, yielding: i) ALUS1 = ADD1 ∨ ADDB1 ∨ SUB1 ∨ SUBB1 ∨ INAC1 ALUS2 = SUB1 ∨ SUBB1 ALUS3 = LDAC5 ∨ MOVR1 ∨ ADD1∨ ADDB1 ALUS4 = SUB1 ∨ SUBB1∨ INAC1 ALUS5 = XOR1 ∨ XORB1 ∨ NOT1 ALUS6 = OR1 ∨ ORB1 ∨ NOT1 ALUS7 = AND1 ∨ ANDB1 ∨ OR1 ∨ ORB1 ∨ XOR1 ∨ XORB1 ∨ NOT1

Copyright © 2001 Addison Wesley - All Rights Reserved

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Computer Systems Organization and Architecture - Solutions Manual

iv) Add the following microinstructions to the microprogram. State ADDB1 SUBB1 ANDB1 ORB1 XORB1 Address 33 37 49 53 57 Cond. 1 1 1 1 1 BT J J J J J All other µ-ops 0 0 0 0 0 BPLU 1 0 0 0 0 BMIN 0 1 0 0 0 BAND 0 0 1 0 0 BOR 0 0 0 1 0 BXOR 0 0 0 0 1 ADDR 1 1 1 1 1

Verification:

Test program shown below. Fetch cycles not shown Instruction ORB ADDB ANDB XORB SUBB State ORB1 ADDB1 ANDB1 XORB1 SUBB1 Micro-operations BOR BPLU BAND BXOR BMIN Operations performed AC ← 1 ∨ 2 = 3 AC ← 3 + 2 = 5 AC ← 5 ^ 2 = 0 AC ← 0 ⊕ 2 = 2 AC ← 2 - 2 = 0

16.

PCLOAD TRLOAD PCBUS DRHBUS DRLBUS ACBUS READ WRITE MEMBUS BUSMEM

= PCDT = TRDR = ARPC = ARDT ∨ PCDT = ACDR ∨ MDR = DRAC ∨ RAC = DRM = MDR = DRM = MDR

RBUS ALUS1 ALUS2 ALUS3 ALUS4 ALUS5 ALUS6 ALUS7 ACLOAD

= ACR ∨ PLUS ∨ MINU ∨ AND ∨ OR ∨ XOR = PLUS ∨ MINU ∨ ACIN = MINU = ACDR ∨ ACR ∨ PLUS = MINU ∨ ACIN = XOR ∨ NOT = OR ∨ NOT = AND ∨ OR ∨ XOR ∨ NOT = ACDR ∨ ACR ∨ PLUS ∨ MINU ∨ ACIN ∨ ACZO ∨ AND ∨ OR ∨ XOR ∨ NOT

17.
State

The subroutine now consists only of its last two instructions: A d d r e s s C o n d i t i o n 1 1 B A A T R R P I C N A R D T P C I N P D D I R Z T A A P M A C R R R A A R C C L I C D M A D C L D D R U N I S U N T U R R C R A A O X N M C N R O O D R T R Z D O A D D R

SUB1 SUB2

61 62

J 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 R 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

62 X

Copyright © 2001 Addison Wesley - All Rights Reserved

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Computer Systems Organization and Architecture - Solutions Manual

18.

i)

The microsequencer is the same as shown in Figure 7.8, except the micro-operations fields are input to decoders which generate the micro-operations. ii) From the microcode of Table 7.17, the following groups of micro-operations must occur simultaneously at least once, and therefore must be located in different fields: • • • • PCIN, DRM, and ARIN ARPC, and IRDR PCIN, DRM, and TRDR ZALU, and each of the arithmetic and logic micro-operations (PLUS, MINU, ACIN, ACZO, AND, OR, XOR, and NOT)

iii) Since some microinstructions (such as NOP1) perform no micro-operations, each field requires a NOP. One possible partitioning of the micro-operations, and its resultant microcode, are shown below. M1 NOP TRDR ARIN ARPC ARDT PCDT DRAC RAC
State A d d r e s s C o n d i t i o n 1 1 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B T M1

PLUS MINU ACIN ACZO AND OR XOR NOT
M2 M3

M2 NOP PCIN IRDR ZALU ACDR ACR MDR

M3 NOP DRM

A D D R

State

A d d r e s s

FETCH1 FETCH2 FETCH3 NOP1 LDAC1 LDAC2 LDAC3 LDAC4 LDAC5 STAC1 STAC2 STAC3 STAC4 STAC5 MVAC1 MOVR1 JUMP1 JUMP2 JUMP3

1 2 3 0 4 5 6 7 33 8 9 10 11 34 12 16 20 21 22

J J M J J J J J J J J J J J J J J J J

ARPC NOP ARPC NOP ARIN TRDR ARDT NOP NOP ARIN TRDR ARDT DRAC NOP NOP NOP ARIN TRDR PCDT

NOP PCIN IRDR NOP PCIN PCIN NOP NOP ACRD PCIN PCIN NOP NOP MDR NOP NOP NOP NOP NOP

NOP DRM NOP NOP DRM DRM NOP DRM NOP DRM DRM NOP NOP NOP NOP NOP DRM DRM NOP

2 3 X 1 5 6 7 33 1 9 10 11 34 1 1 1 21 22 1

JMPZ1 JMPZY1 JMPZY2 JMPZY3 JMPZN1 JMPZN2 JPNZ1 JPNZY1 JPNZY2 JPNZY3 JPNZN1 JPNZN2 ADD1 SUB1 INAC1 CLAC1 AND1 OR1 XOR1 NOT1

24 25 26 27 41 42 28 29 30 31 45 46 32 36 40 44 48 52 56 60

C o n d i t i o n Z′ 1 1 1 1 1 Z 1 1 1 1 1 1 1 1 1 1 1 1 1

B T

M1

M2

M3

A D D R

J J J J J J J J J J J J J J J J J J J J

NOP ARIN TRDR PCDT NOP NOP NOP ARIN TRDR PCDT NOP NOP PLUS MINU ACIN ACCL AND OR XOR NOT

NOP NOP NOP NOP PCIN PCIN NOP NOP NOP NOP PCIN PCIN ZALU ZALU ZALU ZALU ZALU ZALU ZALU ZALU

NOP DRM DRM NOP NOP NOP NOP DRM DRM NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP

41 26 27 1 42 1 45 30 31 1 46 1 1 1 1 1 1 1 1 1

Copyright © 2001 Addison Wesley - All Rights Reserved

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READ ACLOAD. ALUS3. READ PCLOAD.All Rights Reserved Page 71 . READ PCLOAD. DRLOAD. ZALU. Address 1 2 3 0 4 5 6 7 33 8 9 10 11 34 12 16 20 21 22 24 25 26 27 41 42 28 29 30 31 45 46 32 36 40 44 48 52 56 60 Condition 1 1 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z′ 1 1 1 1 1 Z 1 1 1 1 1 1 1 1 1 1 1 1 1 BT J J M J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J Active control signals ARLOAD. RBUS ACLOAD. TRBUS PCINC PCINC None ARINC.Solutions Manual 19. DRLOAD. PCINC. ALUS7. READ ARLOAD. PCBUS PCINC. ALUS4 ACLOAD. READ PCLOAD. DRHBUS. MEMBUS. ACBUS ACLOAD. DRHBUS. ALUS7. DRLOAD. WRITE RLOAD. DRLBUS ARINC. READ PCINC. MEMBUS. DRHBUS. ALUS1. ALUS3. READ DRLOAD. TRBUS DRLOAD. RBUS ACLOAD. ALUS7 ADDR 2 3 X 1 5 6 7 33 1 9 10 11 34 1 1 1 21 22 1 41 26 27 1 42 1 45 30 31 1 46 1 1 1 1 1 1 1 1 1 State FETCH1 FETCH2 FETCH3 NOP1 LDAC1 LDAC2 LDAC3 LDAC4 LDAC5 STAC1 STAC2 STAC3 STAC4 STAC5 MVAC1 MOVR1 JUMP1 JUMP2 JUMP3 JMPZ1 JMPZY1 JMPZY2 JMPZY3 JMPZN1 JMPZN2 JPNZ1 JPNZY1 JPNZY2 JPNZY3 JPNZN1 JPNZN2 ADD1 SUB1 INAC1 CLAC1 AND1 OR1 XOR1 NOT1 Copyright © 2001 Addison Wesley . DRHBUS. ZALU. IRLOAD. ZALU. DRLOAD. ZALU. TRBUS PCINC PCINC ACLOAD. ZALU. The microsequencer is the same as shown in Figure 7. TRLOAD. RBUS ACLOAD. READ DRLOAD. ACBUS DRLBUS. RBUS ARINC. TRLOAD. MEMBUS.8. ALUS7. ZALU ACLOAD. TRBUS DRLOAD. TRBUS None ARINC. ALUS6. PCINC. READ PCINC. ALUS1. as shown in the following table. ALUS1. READ ARLOAD. ALUS4. BUSMEM.Computer Systems Organization and Architecture . MEMBUS. ALUS5. DRLOAD. MEMBUS. MEMBUS. ZALU. TRLOAD. ZALU. MEMBUS. DRLOAD. DRHBUS. TRLOAD. MEMBUS. DRLOAD. RBUS ACLOAD. READ ARLOAD. ALUS2. MEMBUS. PCBUS None ARINC. ALUS3. RBUS ACLOAD. ALUS5. MEMBUS. except the micro-operations fields outputs the control signals directly. ALUS6. DRLOAD. READ DRLOAD. MEMBUS. TRLOAD. MEMBUS.

.0] AC ← AC' DR ← M PC ← PC + DR[5.6. and ALU are the same as for Problem 6. Z ← 0) (AC ← 3.28.Computer Systems Organization and Architecture . Z ← 1) (jump is taken) (skipped by JMPZ 000D) (jump is not taken) (AC ← FF.6]. Z ← 0) (AC ← 2. The student can execute the following program using the Relatively Simple CPU simulator to verify that each instruction performs properly. Z ← 1) (AC ← 1. Z ← 0) (AC ← 0. Copyright © 2001 Addison Wesley . PC ← PC + 1 IR ← DR[7. The state diagram. except for the data input to PC. register section.Solutions Manual 20. AR ← DR[5. Z ← 1) (AC ← 1) (M[30] ← 1) (AC ← 1. Z ← 0) (start again) 21. RTL code.0] DR ← M AC ← AC ∨ DR DR ← M AC ← AC + DR' The register section is the same as Figure 6..All Rights Reserved Page 72 . Z ← 0) (jump is not taken) (jump is taken) (skipped by JMPZ 0018) (AC ← 0. This solution is the same as for Problem 6. State diagram and RTL code: FETCH1: FETCH2: FETCH3: COM1: JREL1: JREL2: OR1: OR2: SUB11: SUB12: AR ← PC DR ← M. shown below.. 0: LDAC 0000 NOP MVAC ADD INAC XOR AND 9: JMPZ 000D NOP D: JPNZ 0009 NOT JMPZ 0009 JPNZ 0018 NOP 18: CLAC OR SUB MOVR STAC 0030 AND JUMP 0000 (AC ← 1) (R ← 1) (AC ← 2.18. Z ← 0) (AC ← 0.

3 and 7.Solutions Manual ARLOAD = FETCH1 ∨ FETCH3 PCLOAD = JREL2 PCINC =FETCH2 PCBUS = FETCH1 DRLOAD = MEMBUS = READ = FETCH2 ∨ JREL1∨ OR1∨ SUB11 DRBUS = FETCH3 ∨ JREL2 ∨ OR2 ∨ SUB12 ACLOAD = COM1 ∨ OR2 ∨ SUB12 IRLOAD = FETCH3 Control signals: ALU: The microsequencer hardware is the same as shown in Figures 7.Computer Systems Organization and Architecture . Microcode: State Address S E L A R L O A D 1 0 1 0 0 0 0 0 0 0 P C L O A D 0 0 0 0 0 1 0 0 0 0 P C I N C 0 1 0 0 0 0 0 0 0 0 P C B U S 1 0 0 0 0 0 0 0 0 0 D M R D R B U S 0 0 1 0 0 1 0 1 0 1 A C L O A D 0 0 0 1 0 0 0 1 0 1 I R L O A D 0 0 1 0 0 0 0 0 0 0 A L U S 1 0 0 0 0 0 0 0 1 0 0 A L U S 2 0 0 0 0 0 0 0 0 0 1 ADDR FETCH1 FETCH2 FETCH3 COM1 JREL1 JREL2 OR1 OR2 SUB11 SUB12 0000 (0) 0001 (1) 0010 (2) 1000 (8) 1010 (10) 1011 (11) 1100 (12) 1101 (13) 1110 (14) 1111 (15) 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0001 0010 XXXX 0000 1011 0000 1101 0000 1111 0000 Copyright © 2001 Addison Wesley .4. except the micro-operations are replaced by control signals.All Rights Reserved Page 73 .

. PC ← PC + 1 AR ← DR DR ← AC M ← DR ADD1: DR ← M. and ALU are the same as for Problem 6.0] SKIP1: PC ← PC + 1 RST1: PC ← 0.Computer Systems Organization and Architecture . AR ← PC DR ← M. PC ← PC + 1 AC ← DR DR ← M. The state diagram.29.Solutions Manual 22.. PC ← PC + 1 OR2: AC ← AC ∨ DR JUMP1: DR ← M JUMP2: PC ← DR JREL1: PC ← PC + 000DR[4. AC ← 0 Control signals: ARLOAD = FETCH1 ∨ FETCH3 ∨ STO2 PCLOAD = JUMP2 ∨ JREL2 PCINC = FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ SKIP1 PCCLR =RST1 PCBUS = FETCH1 ∨ FETCH3 PCMUX = JUMP2 DRLOAD = FETCH2 ∨ LDI1 ∨ STO1 ∨ STO3 ∨ ADD1 ∨ OR1 ∨ JUMP1 DRBUS = FETCH3 ∨ LDI2 ∨ STO2 ∨ STO4 ∨ ADD2 ∨ OR2 ∨ JUMP2 ∨ JREL1 ACLOAD = LDI2 ∨ ADD2 ∨ OR2 ACCLR =RST1 ACBUS =STO3 IRLOAD =FETCH3 MEMBUS = READ = FETCH2 ∨ LDI1 ∨ STO1 ∨ ADD1 ∨ OR1 ∨ JUMP1 BUSMEM = WRITE = STO4 Copyright © 2001 Addison Wesley .All Rights Reserved Page 74 . RTL code. State diagram and RTL code: FETCH1: FETCH2: FETCH3: LDI1: LDI2: STO1: STO2: STO3: STO4: AR ← PC DR ← M. PC ← PC + 1 IR ← DR[7.5]. PC ← PC + 1 ADD2: AC ← AC + DR OR1: DR ← M. register section.

Solutions Manual Register section: ALU: Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .All Rights Reserved Page 75 .

0] AC ← AC + DR AC ← AC ∨ DR 0 1 2 3 4 5 6 7 Microcode: State FETCH1 FETCH2 FETCH3 STO3 STO4 LDI1 LDI2 STO1 STO2 ADD1 ADD2 OR1 OR2 JUMP1 JUMP2 JREL1 SKIP1 RST1 Address 00000 00001 00010 00100 00101 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11100 11110 0 1 2 3 4 5 6 7 SEL 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1 001 101 001 101 110 010 011 010 100 010 000 010 000 010 000 000 000 111 M2 000 010 001 000 000 010 000 010 000 010 110 010 111 000 100 101 010 011 ADDR 00001 00010 XXXX 00101 00000 10001 00000 10011 00100 10101 00000 10111 00000 11001 00000 00000 00000 00000 Copyright © 2001 Addison Wesley .5] PC ← PC + 1 PC ← 0 PC ← DR PC ← PC + 000DR[4.4.0]. Micro-operation field assignments: M1 NOP AR ← PC DR ← M AC ← DR AR ← DR DR ← AC M ← DR AC ← 0 M2 NOP IR ← DR[7. except the micro-operations are output to decoders to generate the actual micro-operation signals. and the mapping function is 1..Computer Systems Organization and Architecture .All Rights Reserved Page 76 .IR[2...Solutions Manual The microsequencer hardware is the same as shown in Figures 7.0.3 and 7.

SP ← SP + 1. DR ← AC AR ← SP M ← DR AR ← SP DR ← M.1 CALL4: AR ← SP CALL5: M ← DR.1 CALL6: DR ← PC[7.0] All other connections remain the same as shown in Figure 6. DR ← M.. SP ← SP + 1 R ← DR Copyright © 2001 Addison Wesley .8] or BUS[7. AR ← AR + 1..TR CALL1: DR ← M.. PUSHAC1: PUSHAC2: PUSHAC3: POPAC1: POPAC2: POPAC3: PUSHR1: PUSHR2: PUSHR3: POPR1: POPR2: POPR3: SP ← SP .Computer Systems Organization and Architecture . SP ← SP .8]. PC ← PC + 1 LDSP2: TR ← DR. SP ← SP . RTL code.1. TR2 (with LD. DR ← PC[15. DEC. PC ← PC + 1 LDSP3: SP ← DR.0] CALL7: M ← DR CALL8: PC ← TR2. INC). Modified state diagram: Modified RTL code: LDSP1: DR ← M.1. receives data directly from DR) New control signal: AR adds a DEC signal New data path: DR can receive data from BUS[15.. SP ← SP + 1 RET4: PC ← DR.1. AR ← AR . DR ← M.All Rights Reserved Page 77 . The state diagram. DR ← M. PC ← PC + 1 CALL3: TR2 ← DR. AR ← AR + 1. PC ← PC + 1 CALL2: TR ← DR. and register section are the same as in Problem 6.DR RET1: AR ← SP RET2: DR ← M.Solutions Manual 23.15.30.TR Modified register section: (shown below) • • • • New registers: SP (with LD. AR ← AR + 1 RET3: TR ← DR. SP ← SP + 1 AC ← DR SP ← SP . DR ← R AR ← SP M ← DR AR ← SP DR ← M.

8] SP ← SP .All Rights Reserved Page 78 ..1 DRPL: PCTR: SPIN: DRR: RDR: DR ← PC[7.Solutions Manual New micro-operations: SPDT: T2DR: DRPH: SPDC: ARSP: ARDC: SP ← DR.0] PC ← TR2...3.TR SP ← SP + 1 DR ← R R ← DR New mapping function: ARDEC = SPLOAD = SPINC = SPDEC = SPBUS = DRSEL = TR2LOAD = TR2BUS = Modified control signals: ARLOAD = ARINC = PCLOAD = DRLOAD = DRHBUS = DRLBUS = TRLOAD = TRBUS = RLOAD = RBUS = IR[7.) ARDC SPDT SPIN SPDC ARSP DRPH T2DR PCTR (original value) ∨ ARSP (original value) ∨ PCTR (original value) ∨ DRPH ∨ DRPL ∨ DRR (original value) ∨ DRPH ∨ DRPL ∨ DRR (original value) ∨ SPDT (original value) ∨ T2DR ∨ RDR (original value) ∨ LDSP2 ∨ CALL2 ∨ RET3 (original value) ∨ PCTR (original value) ∨ RDR (original value) ∨ DRR Copyright © 2001 Addison Wesley .TR TR2 ← DR DR ← PC[15.1 AR ← SP AR ← AR .Computer Systems Organization and Architecture .0]00 (The extra MSB in ADDR is 0 for all current instructions.

SPIN.All Rights Reserved Page 79 . DRM. ARIN. DRR ARSP MDR ARSP DRM. DRM. SPIN PCDT SPDC. PCIN T2DR. ARDC. DRM. SPDC ARSP MDR. DRPH. PCIN SPDT DRM. ARIN TRDR. ARIN.Computer Systems Organization and Architecture . DRAC ARSP MDR ARSP DRM. SPIN RDR ADDR 100 0001 100 0010 000 0001 100 1001 100 1010 100 1011 100 0100 100 0101 100 0110 100 0111 000 0001 100 1101 100 1110 100 1111 000 0001 101 0001 101 0010 000 0001 101 0101 101 0110 000 0001 101 1001 101 1010 000 0001 101 1101 101 1110 000 0001 Copyright © 2001 Addison Wesley .Solutions Manual New microinstructions: State LDSP1 LDSP2 LDSP3 CALL1 CALL2 CALL3 CALL4 CALL5 CALL6 CALL7 CALL8 RET1 RET2 RET3 RET4 PUSHAC1 PUSHAC2 PUSHAC3 POPAC1 POPAC2 POPAC3 PUSHR1 PUSHR2 PUSHR3 POPR1 POPR2 POPR3 Address 100 0000 100 0001 100 0010 100 1000 100 1001 100 1010 100 1011 100 0100 100 0101 100 0110 100 0111 100 1100 100 1101 100 1110 100 1111 101 0000 101 0001 101 0010 101 0100 101 0101 101 0110 101 1000 101 1001 101 1010 101 1100 101 1101 101 1110 SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Micro-operations DRM. PCIN TRDR. SPDC DRPL MDR PCTR ARSP DRM. SPIN ACDR SPDC. PCIN TRDR.

2 CU ← U + X. Non-negative 29 = 0001 1101 -128 = N/A 199 = 1100 0111 Unsigned two's-complement 0001 1101 1000 0000 N/A Signed-Two's Complement 1100 0001 N/A 0101 0101 Signed-Magnitude -63 = 1011 1111 147 = N/A 85 = 0101 0101 0011 1101 N/A 1111 1111 N/A N/A 0000 0101 1111 1111 N/A (180 . i ← 4 2 i←i-1 3.Computer Systems Organization and Architecture .2 CU ← U + X. goto 2 Y02. a) b) c) 3. or 1001 * 1110 = 0111 1110 Copyright © 2001 Addison Wesley . both of which produce valid results.Solutions Manual Chapter 8 1. goto 2 Y02. cir(Y).119 = -193. overflow) (139 + 116 = 255) (116 . i ← i . overflow) (56 + -51 = 5) (-117 + 116 = -1) (116 .-117 = 233. cir(Y). overflow) The worst cases are +127 + (-1) = +126 and +0 + (-128) = -128.2 CU ← U + X. Conditions Micro-operations START 1 U ← 0. negative number) (-76 . a) 64 = 01000000 64' = 1100 0000 b) 33 = 0010 0001 33' = 1101 1111 c) -1 = 1111 1111 -1' = 0000 0001 2. a) b) c) d) 5.119 = 61) (56 + 205 = 261. i ← i .1 3.139 = -23. FINISH ← 1 i x 4 3 2 1 0 C U V Y Z FINISH x xxxx xxxx 1110 0 0000 0 0 0 0000 0xxx 0111 0 1001 0 0 0100 10xx 1011 0 1101 0 0 0110 110x 1101 0 1111 1 0 0111 1110 1110 1 Result: 9 * 14 = 126.Z3 shr(CUV).Z´3 shr(CUV).1 3. cir(Y). a) b) c) d) 6.Z´3 shr(CUV). goto 2 Y02. cir(Y). 7. i ← i . a) b) c) 4.All Rights Reserved Page 80 .Z´3 shr(CUV).1 3.

Z3 ashr(UV).Z3 Micro-operations U ← 0. cir(Y). goto 2 2 i←i–1 3.Z´3 ashr(UV).1 shr(CUV). goto 2 CU ← U + X. Y-1 ← 0.Computer Systems Organization and Architecture . i ← i – 1 3.1 shr(CUV). or 1001 * 1110 = 0111 1110 9.Z´3 ashr(UV).2 U ← U + X′ + 1. Y-1 ← Y0. FINISH ← 1 i x 4 3 2 1 0 C U V Z FINISH x xxxx 1110 0 0000 0 0 0 0000 0111 0 1001 0 0 0100 1011 0 1101 0 0 0110 1101 0 1111 1 0 0111 1110 1 Result: 9 * 14 = 126.2 3.All Rights Reserved Page 81 . goto 2 CU ← U + X. Conditions Micro-operations START 1 U ← 0.2 3. 1: U ← 0. i ← i . FINISH ← 1 Result: 6 * -5 = -30. Y-1 ← Y0. Conditions START 1 2 3.Solutions Manual 8. cir(Y).Z´3 V02. i ← i . i ← 4 i←i-1 shr(CUV). or 0110 * 1011 = 1110 0010 i U x xxxx 4 0000 3 1010 1101 2 1110 1 0100 0010 0 1100 1110 V Y Y-1 Z FINISH xxxx 1011 x 0 0 0 0 0xxx 1101 1 0 10xx 1110 1 0 010x 0111 0 1 0010 1011 1 10. i ← 4 Y0Y-1´2. i ← i – 1 3. i ← i .2 3.2 U ← U + X′ + 1. Y-1 ← Y0.Z´3 V02.2 U ← U + X. Y-1 ← Y0. goto 2 CU ← U + X.1 shr(CUV).Z´3 ashr(UV). goto 2 Y0´Y-12. cir(Y). V-1 ← 0. goto 2 Y0Y-1´2.Z´3 V02. i ← n V0V´-12: U ← U + X′ + 1 V´0V-12: U ← U + X 2: i ← i – 1 3:ashr(UVV-1) Z´3:goto 2 Z3: FINISH ← 1 Copyright © 2001 Addison Wesley . i ← i – 1 3. cir(Y).

Z´42 Y0 ← 1.Solutions Manual 11. i ← n 3: shl CUV. FINISH ← 1 i x 4 3 2 1 0 C U V Y x 0110 1011 xxxx 0 1100 0110 0000 0 1101 0110 0000 1 0011 0001 0 0110 1100 0010 0 1100 0 0110 0 1101 1000 0100 1 0011 0101 0 0111 0000 1010 0 1101 0111 Z OVERFLOW FINISH 0 0 0 0 0 0 1 1 Result: 107 ÷ 10 = 10 R 7. shl Y. i ← i – 1 C´41 CU ← U + X′ + 1 C´42. goto 3 3 shl CUV. shl Y.Z´4 3 Z´4 3 (C + G)4. the rest is the same as in the chapter. i ← i – 1 goto 3 shl CUV. U ← U + X′ + 1. shl Y. i ← 4 shl CUV. C ← 0. shl Y. i ← i – 1 C´41 CU ← U + X′ + 1 C42. C ← 0. or 0110 1011 ÷ 1010 = 1010 R 0111 13. goto 3 shl CUV. i ← i – 1 C´41 CU ← U + X′ + 1 C42. 1: OVERFLOW ← G G1: FINISH ← 1 2: Y ← 0. i ← i – 1 C´41 CU ← U + X′ + 1 C´42. i ← i – 1 (C + G)4: Y0 ← 1. i ← i – 1 FINISH ← 1 i x 4 3 C x 0 0 U 0110 V 1011 Y xxxx 0000 Z FINISH 0 0 0 1101 0011 0110 1101 0011 0111 0110 0000 0001 0010 0100 0101 1010 2 1 0 0 1100 1000 0 0 0 0 0000 1 1 Result: 107 ÷ 10 = 10 R 7. Conditions Micro-operations START 11 CU ← U + X′ + 1 12 U←U+X 2 Y ← 0.Z´4 3 Z4 Micro-operations NONE Y ← 0. and the OVERFLOW hardware are changed. goto 3 3 shl CUV. G1. shl Y. goto 3 shl CUV. shl Y. shl Y. goto 3 3 shl CUV.Z´42 U ← U + X.Z´42 Y0 ← 1. and 2. shl Y. OVERFLOW ← 0.) Copyright © 2001 Addison Wesley . i ← i – 1 Y0 ← 1. i ← 4 3 shl CUV.Computer Systems Organization and Architecture . shl Y. OVERFLOW ← 0. i ← i – 1 Y0 ← 1.Z42 U ← U + X.All Rights Reserved Page 82 . U ← U + X′ + 1. Conditions START 1 2 3 (C + G)4. or 0110 1011 ÷ 1010 = 1010 R 0111 12. U ← U + X′ + 1 Z´4:goto 3 Z 4: FINISH ← 1 (Only 1.

U ← U' + 1 NX5: X ← X' + 1 5: FINISH ← 1 16. i ← n 3: shl CUV. 10: NU ← Un-1. U ← CU + X′ + 1 Z´4:goto 3 (NU⊕NX)5:Y ← Y' + 1. NX ← Xn-1 Un-110: UV ← (UV)' + 1 Xn-110: X ← X' + 1 G1: FINISH ← 1.All Rights Reserved Page 83 . the rest is the same as in the chapter.) 14. OVERFLOW ← 0. OVERFLOW ← 1 NUG1: UV ← (UV)' + 1 NXG1: X ← X' + 1 2: Y ← 0. OVERFLOW ← 1 NUC12: UV ← (UV)' + 1 NXC12: X ← X' + 1 2: Y ← 0. i ← n 3: shl CUV. i ← i – 1 (C + G)4: Y0 ← 1. shl Y. OVERFLOW ← 0. Copyright © 2001 Addison Wesley . i ← n 3: shl CUV. and the OVERFLOW hardware are changed. and 2. i ← i – 1 C41: U ← U + X′ + 1 C´41: CU ← U + X′ + 1 C42: Y0 ← 1 C´42: U ← U + X Z´42:goto 3 (NU⊕NX)5:Y ← Y' + 1. shl Y. C ← 0. i ← i – 1 C41: U ← U + X′ + 1 C´41: CU ← U + X′ + 1 C42: Y0 ← 1 C´42: U ← U + X Z 42: FINISH ← 1 Z´42: goto 3 (Only 12. 15. shl Y.Computer Systems Organization and Architecture . OVERFLOW ← C C12: FINISH ← 1 2: Y ← 0. NX ← Xn-1 Un-110: UV ← (UV)' + 1 Xn-110: X ← X' + 1 11: CU ← U + X′ + 1 12 : U ← U + X C12: FINISH ← 1. C ← 0.Solutions Manual 11: CU ← U + X′ + 1 12: U ← U + X. U ← U' + 1 NX5: X ← X' + 1 5: FINISH ← 1 10: NU ← Un-1.

Z´3 2 3. FINISH ← 1 Result: UsU = 1 0010 = -2 PM1: CU ← 0 1110. U ← U′ + 1 2: OVERFLOW ← PM' ^ C.Z3 i x Us ← 1.2 3. i ← i . CU ← 1 0000 PM´2.) 19.Z´3 shr(CUV).2: OVERFLOW ← 1.1 shr(CUV). cir(Y). a) Conditions START 1 Y02. FINISH ← 1 i x 4 3 2 1 0 C U V Y Z FINISH x xxxx xxxx 0000 0 0000 0 0 0 0000 0xxx 0000 0 0 0000 00xx 0000 0 0 0000 000x 0000 0 0000 1 0 0000 0000 0000 1 Result: -13 × +0 = +0. U ← 0. the rest is the same as in the chapter. or 1 1101 × 0 0000 = 0 0000 0000 Copyright © 2001 Addison Wesley . and 2. cir(Y). PM´1: Us ← Xs. i ← 4 4 3 CU ← U + X. goto 2 0 CU ← U + X. cir(Y). CU ← X + Y PM1: CU ← X + Y′ + 1.1 shr(CUV). FINISH ← 1 Result: UsU = 0 0010 = +2 PM´1: Us ← 0.2: Us ← 1. goto 2 1 i←i-1 shr(CUV).3. U ← 0010. OVERFLOW ← 0 CZ´PM2: Us ← Xs CZPM2: Us ← 0 C´PM2: Us ← Xs′.All Rights Reserved Page 84 . CU ← 1 0000 PM´2. i ← 4 2 i←i-1 3. goto 2 2 i←i-1 ZT3. goto 2 2 i←i-1 3. U ← 0010. FINISH ← 1 Result: Overflow 17. Vs ← 1. cir(Y).Solutions Manual PM1: CU ← 0 1110. PM'2 (deleted).Z´3 shr(CUV). OVERFLOW ← 0 C´PM2. cir(Y).2: Us ← 0. OVERFLOW ← 0 C´PM2. or 0 0111 × 1 1001 = 1 0011 1111 b) Conditions Micro-operations START 1 Us ← 1. a) b) c) d) 18. and the OVERFLOW hardware are changed. FINISH ← 1 Micro-operations C U V Y Z FINISH x xxxx xxxx 1001 0 0000 0 0 0111 0 0 0011 1xxx 1100 0 0 0001 11xx 0110 0 0 0000 111x 0011 0 0111 1 0 0011 1111 1001 1 Result: +7 × -9 = -63. shr(CUV).Z3 Us ← 0.2: OVERFLOW ← 1.Z´3 shr(CUV).Computer Systems Organization and Architecture .2 3. goto 2 2 i←i-1 3. i ← i . U ← 0. cir(Y). goto 2 2 i←i-1 shr(CUV). cir(Y). cir(Y). Vs ← 1.Z´3 Y02. FINISH ← 1 (Only PM1. FINISH ← 1 Result: Overflow PM´1: Us ← 0. Vs ← 0.Z´3 2 3.

i ← i . Vs ← 0.1 shr(CUV). U ← 0. cir(Y). cir(Y). i ← 4 4 3 CU ← U + X. i ← i . goto 2 2 CU ← U + X. or 0 1111 × 0 1111 = 0 1110 0001 20.2 3.2 3.1 shr(CUV). goto 2 0 CU ← U + X.1 shr(CUV). FINISH ← 1 Micro-operations C U x xxxx 0000 0 1111 0 0111 1 0110 0 1011 1 1010 0 1101 1 1100 0 1110 V Y Z FINISH xxxx 1111 0 0 0 1xxx 1111 0 01xx 1111 0 001x 1111 1 0001 1111 1 Result: +15 × +15 = +225.Z´3 Y02.1 shr(CUV).2 3.All Rights Reserved Page 85 .Z3 i x Us ← 0. cir(Y). Copyright © 2001 Addison Wesley . i ← i . cir(Y). i ← i .Solutions Manual c) Conditions START 1 Y02.Z´3 Y02.Computer Systems Organization and Architecture .Z´3 Y02.2 3. goto 2 1 CU ← U + X.

U ← 00. The rest of the algorithm is unchanged. goto 2 CdU ← CdU + X. OVERFLOW ← 0 C´PM2. FINISH ← 1 Cd U V Y ZY0 Z FINISH x xx xx 23 0 0 0 00 0 0 0 0 17 34 51 22 21 20 0 0 1 0 0 0 0 05 1x 02 22 01 39 00 0 0 1 1 03 91 1 Result: +17 × +23 = +391 b) Conditions START 1 Z´Y0 2 Z´Y0 2 ZY02 3.Solutions Manual 21.2: Us ← 1. goto 2 CdU ← CdU + X.2: Us ← 0. G'1: Us ← Us ⊕ Xs. goto 2 CdU ← CdU + X.Z´3 Z´Y0 2 Z´Y0 2 ZY02 3. FINISH ← 1 Result: UsU = 1 02 = -2 PM´1: CU ← 0 30 PM´2. The rest of the algorithm is unchanged. goto 2 CdU ← CdU + X. i x 2 Cd U V Y ZY0 Z FINISH x xx xx 32 0 0 0 00 0 0 1 71 42 31 30 0 1 0 0 0 1 14 2x 03 85 02 56 01 0 0 Copyright © 2001 Addison Wesley . goto 2 CdU ← CdU + X. Vs ← 1. i ← 2. Yd0 ← Yd0 – 1. goto 2 CdU ← CdU + X. a) PM1: CU ← 0 98. goto 2 0 i←i–1 dshr(CdUV). U ← 02. goto 2 1 i←i–1 dshr(CdUV). FINISH ← 1 Result: UsU = 1 36 = -36 c) 24. Ys ← Us ⊕ Xs 23. goto 2 1 i←i–1 dshr(CdUV).Z3 Us ← 0. Vs ← 0. Yd0 ← Yd0 – 1. U ← 00.Z´3 Z´Y0 2 Z´Y0 2 Micro-operations Us ← 1. dshr(Y). Yd0 ← Yd0 – 1. FINISH ← 1 Result: UsU = 0 30 = +30 Micro-operations i x 2 b) PM1: CU ← 0 64. Cd ← 0 CdU ← CdU + X. OVERFLOW ← 0 C´PM2. a) Conditions START 1 Z´Y0 2 Z´Y0 2 Z´Y0 2 ZY02 3. dshr(Y).2: Us ← 1. OVERFLOW ← 0. Yd0 ← Yd0 – 1.Computer Systems Organization and Architecture . Yd0 ← Yd0 – 1. Cd ← 0 CdU ← CdU + X. Yd0 ← Yd0 – 1. Add the following RTL statement. U ← 36. Add the following RTL statement. goto 2 CdU ← CdU + X. dshr(Y). Ys ← Us ⊕ Xs 22. i ← 2. C'12: Us ← Us ⊕ Xs. Yd0 ← Yd0 – 1. Yd0 ← Yd0 – 1.All Rights Reserved Page 86 .

FINISH ← 1 Z´Y0 2 ZY02 3.Z´3 Z´Y0 2 ZY02 3. FINISH ← 1 i x 2 Cd U V Y ZY0 Z FINISH x xx xx 10 0 0 0 00 0 0 0 0 00 0x 01 39 00 1 1 0 03 90 1 Result: -39× -10 = +390 25. goto 2 0 i←i–1 dshr(CdUV).Computer Systems Organization and Architecture . goto 2 CdU ← CdU + X. Copyright © 2001 Addison Wesley . Cd ← 0 1 i←i–1 dshr(CdUV). goto 2 CdU ← CdU + X. goto 2 i←i–1 dshr(CdUV). Yd0 ← Yd0 – 1. i ← 2. U ← 00. dshr(Y).Solutions Manual Yd0 ← Yd0 – 1. Yd0 ← Yd0 – 1.Z3 Micro-operations Us ← 0. Vs ← 0.All Rights Reserved Page 87 . dshr(Y). dshr(Y).Z3 2 0 27 00 1 1 22 72 1 Result: +71× -32 = -2272 c) Conditions START 1 ZY02 3.

Computer Systems Organization and Architecture .All Rights Reserved Page 88 . i ← i – 1 41: CCdU ← CdU + X′ + 1 C42: Y0 ← Y0 + 1. OVERFLOW ← 1 Zcd12: Us ← Us ⊕ Xs. i ← n 3: dshl CdUV. OVERFLOW ← 1 2: Y ← 0. Ys ← Us ⊕ Xs 2: Y ← 0. CdU ← CdU + X′ + 1. dshl Y. OVERFLOW ← 0. i ← n 3: dshl CdUV. 28.Solutions Manual G'1: Us ← Us ⊕ Xs. Ys ← Us ⊕ Xs G1: FINISH ← 1. Addresses xxx000 xxx001 xxx010 xxx011 xxx100 xxx101 xxx110 xxx111 0-7 0 0 0 0 0 0 0 0 8-15 0 1 2 3 4 5 6 7 16-23 0 2 4 6 8 10 12 14 24-31 0 3 6 9 12 15 18 21 32-39 0 4 8 12 16 20 24 28 40-47 0 5 10 15 20 25 30 35 48-55 0 6 12 18 24 30 36 42 56-63 0 7 14 21 28 35 42 49 Copyright © 2001 Addison Wesley . not 67) 12 : U ← U + X Z'cd12: FINISH ← 1. dshl Y. CdU ← CdU + X′ + 1. a) 20 ns T 15 + 10 + 15 b) S ∞ = 1 = =2 Tk 20 c) n * 40 > 20 * (n + 2). 27. Cd ← 0. goto 42 C'42: CdU ← CdU + X Z'C'42:goto 3 ZC'42: FINISH ← 1 26. which yields n = 6 d) 2( n + 2) 29. which yields n > 2 n * 40 = 1. i ← i – 1 (Z'cd + G)4: Y0 ← Y0 + 1. OVERFLOW ← 0. goto 4 ZcdG'Z'4:goto 3 ZcdG'Z4: FINISH ← 1 11: CdU ← CdU + X′ + 1 (Note: X′ + 1 = 967.5 .

Solutions Manual 30. Copyright © 2001 Addison Wesley .All Rights Reserved Page 89 .Computer Systems Organization and Architecture . 31.

Copyright © 2001 Addison Wesley .Solutions Manual 32.Computer Systems Organization and Architecture .All Rights Reserved Page 90 .

All Rights Reserved Page 91 .Computer Systems Organization and Architecture . Condition Symbol (IXN'Y + NX + ZY)1: 1 (N'YZXZ'Y + I'XIYN'X)1: 2 (IYNX + N'XNY)1: 3 EXY2: 4 EYX2: 5 PM´3: 6 PM3: 7 3: 8 Condition Symbol CPM´4: 9 CEPM´5: 10 PM´5: 11 C´PM4: 12 Z'UC'EU'F(n-1)PM5: 13 (ZU + CE)PM 5: 14 C'EUF(n-1)PM 5: 15 Copyright © 2001 Addison Wesley .Solutions Manual 33. The following symbols are used in this design.

Computer Systems Organization and Architecture .Solutions Manual Chapter 9 1.All Rights Reserved Page 92 . Mask: Data: 1111 1111 0000 0000 1111 0000 xxxx xxxx 2. seventh. a) 18 bit tag 8 bit data Valid bit b) c) 4 bit tag 8 bit data Valid bit 27 bits 13 bits 28 bits 5 bit tag 8 bit data Valid bit 5 bit tag 8 bit data Valid bit Way 1 Way 2 Valid 6 bit tag 8 bit bit data Way 3 60 bits d) 6 bit tag 8 bit data Valid 6 bit tag 8 bit bit Way 1 data Way 2 Valid 6 bit tag 8 bit bit data Way 4 Valid bit 5. a) 20 bit tag 16 bit data Valid bit b) c) 7 bit tag 16 bit data Valid bit 37 bits 24 bits 50 bits 8 bit tag 16 bit data Valid bit 8 bit tag 16 bit data Valid bit Way 1 Way 2 d) 9 bit tag 16 bit data Valid 9 bit tag 16 bit Valid 9 bit tag 16 bit Valid 9 bit tag 16 bit bit Way 1 data Way 2 bit 104 bits data Way 3 bit data Way 4 Valid bit 4. a) The fifth location from the top b) The third. and eighth locations from the top c) No locations match this criteria 3. a) 32 or 33 bits: 15 for the address tag 8 for the first data value 8 for the second data value 1 for the valid bit 1 for the dirty bit (only if the cache uses write-back) b) Assuming the bits are ordered as listed in part a: 111 1111 1111 1111 0000 0000 0000 0000 Copyright © 2001 Addison Wesley .

Computer Systems Organization and Architecture . Only changes shown Instruction Address bits Data 1 Data 2 Valid Comments LDAC 4234 000 0000 0000 0000 01 34 1 000 0000 0000 0001 42 0B 1 010 0001 0001 1010 55 29 1 CLAC No changes Cache hit JMPZ 000A 000 0000 0000 0010 06 0A 1 000 0000 0000 0011 00 05 1 INAC 000 0000 0000 0101 0A 03 1 MVAC No changes Cache hit ADD 000 0000 0000 0110 08 02 1 STAC 0927 Cache hit 000 0000 0000 0111 29 09 1 (opcode) 000 0100 1001 0011 -02 1 JUMP 0000 000 0000 0000 1000 05 00 1 000 0000 0000 1001 00 -1 7.All Rights Reserved Page 93 . Only changes shown Instruction Address bits Tag LDAC 4234 0 000 1 423 CLAC No changes JMPZ 000A 1 000 INAC 2 000 MVAC No changes ADD 3 000 STAC 0927 1 092 JUMP 0000 0 001 Data 0 Data 1 Data 2 Data 3 Valid Dirty 01 34 42 0B 1 0 55 29 --1 0 06 00 08 -05 0A 00 02 -00 00 0A 27 -00 05 03 09 02 -1 1 1 1 1 0 0 0 1 0 Cache hit (instr) Replace data Replace data Comments Cache hit Replace data Cache hit Copyright © 2001 Addison Wesley . Only changes shown Instruction Address bits Tag 000 LDAC 4234 0 000 1 000 2 423 4 CLAC 3 000 000 JMPZ 000A 4 000 5 000 6 INAC A 000 MVAC B 000 ADD C 000 000 STAC 0927 D 000 E 000 F 092 7 001 JUMP 0000 0 001 1 001 2 Data Valid Dirty Comments 0 1 01 0 1 34 0 1 42 0 1 55 0B 1 0 0 Replace data 1 06 0 1 0A 0 1 00 0A 1 0 03 1 0 08 1 0 0 1 02 0 1 27 0 1 09 1 1 02 1 Replace data 1 05 00 1 1 Replace data 00 1 1 Replace data 8.Solutions Manual 6.

Computer Systems Organization and Architecture - Solutions Manual

9.

Only changes shown Instruction Address bits Tag 1 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments LDAC 4234 0 000 01 1 0 1 000 34 1 0 2 000 42 1 0 4 423 55 1 0 CLAC 3 000 0B 1 0 JMPZ 000A 4 423 55 1 0 000 06 1 0 5 000 0A 1 0 6 000 00 1 0 INAC A 000 0A 1 0 MVAC B 000 03 1 0 ADD C 000 08 1 0 000 02 1 0 STAC 0927 D 000 27 1 0 E 000 09 1 0 F 092 02 1 1 7 0 1 05 001 0 1 01 000 JUMP 0000 0 0 1 00 001 0 1 34 000 1 0 1 00 001 0 1 42 000 2

10.

Only changes shown Instruction Address bits Tag 1 000 LDAC 4234 0 000 1 423 2 CLAC No change JMPZ 000A 2 423 3 000 INAC 5 000 MVAC No change ADD 6 000 STAC 0927 7 000 3 000 JUMP 0000 0 000 1 000 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments 0 1 01/34 0 1 42/0B 0 1 55/29 Cache hit 55/29 1 0 000 06/0A 1 0 00/05 1 0 0A/03 1 0 Cache hit 08/02 1 0 Hit (instr) 27/09 1 0 00/05 1 0 092 --/02 1 1 01/34 1 0 001 05/00 1 0 42/0B 1 0 001 00/-1 0 Note: Both LRU and FIFO replacement policies replace the same values for this program. Data2 Valid2 Dirty2 Comments

11.
Instruction LDAC 4234

Only changes shown

Address 0 1 CLAC No change JMPZ 000A 1 INAC 2 MVAC No change ADD 3 STAC 0927 1 JUMP 0000 0

Tag1 Data1 Valid1 Dirty1 Tag2 000 01/34/42/0B 1 0 423 55/29/--/-1 0 423 55/29/--/-000 00/00/0A/03 000 08/02/27/09 423 55/29/--/-000 01/34/42/0B 1 1 1 1 1 0 0 0 0 0

Cache hit 000 06/0A/00/05 1 0 Cache hit --/--/--/02 092 001 05/00/00/-Hit (instr) Replace

1 1

1 0

Copyright © 2001 Addison Wesley - All Rights Reserved

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Computer Systems Organization and Architecture - Solutions Manual

12.
Instruction LDAC 4234 Tag 0000 0001 0002 4234 0003 0004 0005 4235 0006 0007 0008 0009 000A 000B 0020 0021 0022 4235 0023 0024 0025 0029 Hits in italics Instruction Tag LDAC 4234 0000 0001 211A STAC 4235 0002 211A MVAC 0003 INAC ADD 0004 JPNZ 0020 0005 LDAC 4235 0010 0011 211A JUMP 0029 0012 AND 0014 Data Valid 1 01/34 42/0B 1 1 55/55 35/42 55/55 03/0A 08/07 20/00 01/35 42/05 1 1 1 1 1 1 1 1 Dirty 0 0 0

Hit ratio = 4.5% Data Valid 01 1 34 1 42 1 55 1 0B 1 35 1 42 1 55 1 03 1 0A 1 08 1 07 1 20 1 00 1 1 01 1 35 1 42 1 55 1 05 1 29 1 00 0C 1 Dirty 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Comments

STAC 4235

MVAC INAC ADD JPNZ 0020

LDAC 4235

Cache hit

JUMP 0029

AND

13.

Hit ratio = 40.9% Comments

Hit (instr) 0 1 0 0 Hit (instr) 0 0 0 0 Hit (00) Hit (instr) Hit (05) - replaces data Hit (55) - replaces data Hit (instr) Replaces data Replaces data Hit (4235) Cache hit

29/00 00/0C

1 1

0 0

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Instruction Address Tag LDAC 4234 0 000 1 000 2 000 4 423 000 STAC 4235 3 000 4 000 5 423 5 MVAC 6 000 INAC 7 000 ADD 8 000 JPNZ 0020 9 000 A 000 B 000 002 LDAC 4235 0 002 1 002 2 JUMP 0029 3 4 5 9 002 002 002 002 Data Valid 01 1 34 1 42 1 55 1 0B 1 35 1 42 1 55 1 03 1 0A 1 08 1 07 1 20 1 00 1 1 01 1 35 1 42 05 29 00 0C 1 1 1 1

Hit ratio = 4.5% Dirty 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Comments

Replaces data Replaces data

AND

Replaces data Replaces data Replaces data Hit (read from 4235) Replaces data Replaces data Replaces data Replaces data

15.

Hits in italics Instruction Address Tag 000 LDAC 4234 0 000 1 423 2 STAC 4235 2 000 2 423 MVAC 3 000 INAC ADD 4 000 JPNZ 0020 5 000 LDAC 4235 0 002 1 002 JUMP 0029 AND 2 4 002 29/00 002 00/0C 1 1 Data Valid 1 01/34 42/0B 1 1 55/-35/42 55/55 03/0A 08/07 20/00 01/35 42/05 1 1 1 1 1 1 1

Hit ratio = 50.0% Dirty 0 0 0 0 1 0 0 0 0 0 Hit (STAC) Hit (00) Hit (35) - Replaces data Replaces data Hit (4235) Hit (JUMP) Hit (00) - Replaces data Replaces data Comments Hit (34)

Hit (STAC) Hit (42) - Replaces data Hit (4235) Replaces data Hit (INAC)

0 0

Copyright © 2001 Addison Wesley - All Rights Reserved

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1 18.55 ns) / (10 ns . 22.Solutions Manual 16. TM = hTC + (1 .1 211A 55/55 1 0000 03/0A 1 0000 01/34 1 0000 0008 0008 0008 42/02 01/35 42/05 42/05 1 1 1 1 0 0 0 0 0 0 0000 35/42 1 1 STAC 4235 MVAC INAC ADD JPNZ 0020 LDAC 4235 0001 08/07 1 20/00 08/07 20/00 29/00 1 1 1 1 0 0 0 0 0 1 0 0 0002 0 0001 0 0002 0 211A 0 0 JUMP 0029 AND 0009 29/00 1 0008 01/35 1 0000 35/42 1 0009 0C/-.h)TP = (.65 = 21 ns TP = (TM .5% Instruction Address Tag1 Data1 V1 D1 Tag2 Data2 V2 D2 Tag3 Data3 V3 D3 Tag4 Data4 V4 D4 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0008 0008 0000 0000 0008 0008 0008 01 34 42 0B 01 34 42 0B 01 34 42 0B 01 35 42 0B 01 01 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108D 55 1 0 STAC 4235 MVAC INAC ADD JPNZ 0020 LDAC 4235 JUMP 0029 AND 108D 55 0001 42 0001 03 0001 0A 108D 55 0001 42 0001 03 0001 0A 108D 55 0001 42 0001 03 0001 0A 0009 29 0009 00 0009 00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001 108D 35 55 1 1 0 1 0001 35 108D 55 0002 20 0002 00 0001 35 108D 55 0002 20 0002 00 0001 35 108D 55 000A 0C 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0002 0002 08 07 1 1 0 0 0002 0002 0008 0008 0002 0002 0002 08 07 42 05 08 07 07 1 1 1 1 1 1 1 0 0 0 0 0 0 0 17..55 ns) = 0.333 ns The next jump instruction is always overwritten by its predecessor. h = 0. LDAC 4234 Hits in italics LRU value underlined Hit ratio = 4.h) = (24 ns . 19.25 ns TC = (TM . Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture .TP) = (40 ns .8 * 10 ns) / .h)TP)/h = (39.2 = 80 ns h = (TM . LDAC 4234 Hits in italics LRU value underlined Hit ratio = 40.hTC)/(1 .(1 . 20. 21..25 * 65 ns) = 22.TP)/(TC .9 ns .All Rights Reserved Page 97 .75 * 8 ns) + (.35 * 75 ns) / .9% Instruction Address Tag1 Data1 V1 D1 Tag2 Data2 V2 D2 0 1 2 2 3 0 1 0 1 1 2 0 0000 01/34 1 0000 42/02 1 211A 55/-.

Computer Systems Organization and Architecture . a) 1554H b) 2000H c) Fault 27.All Rights Reserved Page 98 . (Only changes shown) Address Frame Valid Comments LDAC 4234 0 0 1 4 1 1 JUMP 1000 STAC 4235 JUMP 2000 JUMP 0010 JUMP 3000 JUMP 0100 3 0 0 0 0 1 1 0 0 2 3 1 No changes 1 2 1 No changes 4235 already in memory No changes JUMP 1100 24. a) C543H b) 4077H c) 8401H 30. 26. a) 1C35H b) 0A38H c) Fault 29. a) 2000H b) 0D61H c) 3FFFH Copyright © 2001 Addison Wesley . a) F231H b) Fault c) 4401H 28.Solutions Manual 23. LDAC 4234 STAC 4235 JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100 JUMP 1000 JUMP 2000 PFV PFV PFV PFV PFV PFV 001 121 121 001 301 301 411 411 231 231 231 011 LDAC 4234 STAC 4235 JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100 JUMP 1000 JUMP 2000 PFV PFV PFV PFV PFV PFV 001 121 121 001 301 301 411 411 231 231 231 011 25.

Solutions Manual 31.All Rights Reserved Page 99 . a) b) c) 2 9 E C 6 A 1 1 1 Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture . a) 9512H b) 3456H c) 63EDH 32.

Computer Systems Organization and Architecture . DR ← M. 3.All Rights Reserved Page 100 . Add the following connections using the same decoder used to generate the states of the INPT execute routine. OTPT1: DR ← M.TR OTPT4: DR ← AC OTPT5: Output port ← DR 3.Solutions Manual Chapter 10 1. PC ← PC + 1. The rest of the circuit is unchanged. PC ← PC + 1 OTPT3: AR ← DR. Copyright © 2001 Addison Wesley . 2. AR ← AR + 1 OTPT2: TR ← DR.

DRLOAD. MEMBUS ACLOAD.Computer Systems Organization and Architecture . DRLOAD. which is 1 only for the microinstruction at address 67. Other points may also be considered for this question. ACBUS BUSMEM. TRBUS DRLOAD. MEMBUS. i) Modify the mapping function to map instruction code 0010 0000 to microcode address 100 0000. DRLBUS U J 73 U J 74 U J 75 U J 76 U J 01 9. DRLBUS U J 65 U J 66 U J 67 U J 68 U J 01 8. PCINC.Solutions Manual 5. TRBUS DRLOAD. PCINC. 11. MEMBUS. MEMBUS PCINC TRLOAD ARLOAD DRHBUS TRBUS DRLBUS = = = = = = = (old value of MEMBUS) ∨ INPT1 ∨ INPT2 ∨ INPT4 (old value of PCINC) ∨ INPT1 ∨ INPT2 (old value of TRLOAD) ∨ INPT2 (old value of ARLOAD) ∨ INPT3 (old value of DRHBUS) ∨ INPT3 (old value of TRBUS) ∨ INPT3 (old value of DRLBUS) ∨ INPT5 6. which is 1 for the microinstruction at address 76. iii) Add the following microinstructions to memory. DRHBUS. ARINC TRLOAD. ii) Add microcode signal IO. (Only active control signals are shown. DRHBUS.) 72: 73: 74: 75: 76: DRLOAD. The control signal changes are as follows. Time (ns) Routine Time (ns) Routine Time (ns) Routine 0 10 20 40 45 60 80 85 90 100 MAIN IRQ1 IRQ2 IRQ1 IRQ3 IRQ4 IRQ3 IRQ1 MAIN 0 10 30 50 70 90 100 MAIN IRQ6 IRQ5 IRQ4 IRQ3 MAIN 0 10 20 40 50 60 80 90 100 MAIN IRQ4 IRQ6 IRQ4 IRQ1 IRQ3 IRQ1 MAIN Daisy chaining is easier to modify when it is necessary to add peripherals to a computer system. MEMBUS.) 64: 65: 66: 67: 68: DRLOAD. ii) Add microcode signal IO. 10. PCINC ARLOAD. PCINC ARLOAD.4. ARINC TRLOAD. ARINC MEMBUS BUSMEM PCINC TRLOAD ARLOAD DRHBUS TRBUS DRLBUS = = = = = = = = = (old value of ARINC) ∨ OTPT1 (old value of MEMBUS) ∨ OTPT1 ∨ OTPT2 (old value of BUSMEM) ∨ OTPT5 (old value of PCINC) ∨ OTPT1 ∨ OTPT2 (old value of TRLOAD) ∨ OTPT2 (old value of ARLOAD) ∨ OTPT3 (old value of DRHBUS) ∨ OTPT3 (old value of TRBUS) ∨ OTPT3 (old value of DRLBUS) ∨ OTPT5 7. It also requires fewer pins on the CPU. Copyright © 2001 Addison Wesley . 12. The control unit changes are the same as for Problem 10. MEMBUS. iii) Add the following microinstructions to memory. (Only active control signals are shown. i) Modify the mapping function to map instruction code 0010 0001 to microcode address 100 1000.All Rights Reserved Page 101 .

0 10 20 45 60 4 6 1 3 16. Int.Computer Systems Organization and Architecture . Copyright © 2001 Addison Wesley . Req. 17. IACKout = IACKin ^ IRQ' 14.All Rights Reserved Page 102 . Time (ns) Routine IACK6in IACK6out IACK4in IACK4out IACK3in IACK3out IACK1in IACK1out Time (ns) Int. Vector 0 10 20 40 50 60 80 90 100 MAIN IRQ4 IRQ6 IRQ4 IRQ1 IRQ3 IRQ1 MAIN 15. Ack.Solutions Manual 13.

ii) Change the following state signals: FETCH1 = T0 ^ (IP' ∨ IE') FETCH2 = T1 ^ INT' FETCH3 = T2 ^ INT' iii) Add hardware to generate the following new state signals: INT1 = T0 ^ (IP ^ IE) INT2 = T1 ^ INT INT3 = T2 ^ INT INT4 = T3 ^ INT INT5 = T4 ^ INT INT6 = T5 ^ INT INT7 = T6 ^ INT iv) Modify the following internal control unit signals: Decoder enable = (Old value of Decoder Enable) ^ INT' Time counter CLR = (Old value of Time counter CLR) ^ INT7 19.All Rights Reserved Page 103 . Copyright © 2001 Addison Wesley . i) Add the following hardware to implement INT.Computer Systems Organization and Architecture .Solutions Manual 18. 20. IE ^ IP ^ FETCH1: AR ← SP (IE' ∨ IP') ^ FETCH1: AR ← PC INT2 .INT7 are the same as in the chapter text. Replace state FETCH1 and its input and output arcs with the following.

HDLC: 48 ÷ (48 + 96) = 33. HDLC has less overhead c) Asynchronous: 2 ÷ (2 + 8) = 20. 27. 26. a) 1 start + 0 parity + 1½ stop bits = 2½ bits overhead. LDAC 2000 OTPT 8000 LDAC 2001 OTPT 8001 LDAC 2002 OTPT 8002 Replace the FETCH1 input to the OR gate which drives the INC signal of the Time Counter with FETCH1 ^ BR'.All Rights Reserved Page 104 .0%. a) Asynchronous: 2 ÷ (2 + 8) = 20. Asynchronous has less overhead b) Asynchronous: 2½ ÷ (2½ + 7) = 26.0%. i) COH 10H 00H 00H 20H 99H 00H ii) C1H 11H 00H 08H 28H 99H 01H iii) C0H 10H 80H 00H 01H 99H 02H 24. 4 ÷ (4 + 7) = 36. Both have the same overhead.2%. 22.3%. HDLC: 48 ÷ (48 + 168) = 22. b) 1 start + 1 parity + 2 stop bits = 4 bits overhead. 3 ÷ (3 + 5) = 37. since the CPU does not interact with the data bus while a DMA transfer is active.3%. 29. c) 1 start + 1 parity + 1 stop bits = 3 bits overhead.4%. 2½ ÷ (2½ + 8) = 23.Computer Systems Organization and Architecture . 25.8%. 28. 23. LDAC 1111 OTPT 9800H LDAC 1112H OTPT 9801H Copyright © 2001 Addison Wesley .Solutions Manual ARLOAD = (Original value of ARLOAD) ∨ INT1 ARDEC = (Original value of ARDEC) ∨ INT3 SPBUF = (Original value of SPBUF) ∨ INT1 SPDEC = (Original value of SPDEC) ∨ INT2 ∨ INT3 DRLOAD = (Original value of DRLOAD) ∨ INT2 ∨ INT4 ∨ INT6 DRLBUS = (Original value of DRLBUS) ∨ INT3 ∨ INT5 ∨ INT7 PCHBUS = (Original value of PCHBUS) ∨ INT2 PCLBUS = (Original value of PCLBUS) ∨ INT4 PCLOAD = (Original value of PCLOAD) ∨ INT7 BUSMEM = (Original value of BUSMEM) ∨ INT3 ∨ INT5 WRITE = (Original value of WRITE) ∨ INT3 ∨ INT5 MEMBUS = (Original value of MEMBUS) ∨ INT6 IACK = INT5 ∨ INT6 21. HDLC: 48 ÷ (48 + 192) = 20.5%.0%. No changes are required.

90% c) 1536 × (1 start bit + 8 data bits + 1 stop bit) = 15.Solutions Manual 30.360 bits Copyright © 2001 Addison Wesley .Computer Systems Organization and Architecture . a) Token packet: 24 bits Data packet: 6168 bits Handshaking packet: 8 bits TOTAL: 6200 bits b) 56 ÷ 6200 = 0.All Rights Reserved Page 105 .

96 ns 25 ns > 24. (24 ns × 99%) + (24 ns × 4 instructions × 1%) average time b) c) d) e) 25 ns vs. 23.556 c) Combine stages 1 and 2.167 instructions x ns × 100% = (24 ns × 99%) + (96 ns × 1%). a) 25 ns × 100% vs. x = 1.56 ns 18 ns × 100% = (x ns × 96%) + (5x ns × 4%). x = 13. a) 15 ns × 100% vs. x = 15.286 7. therefore the second CPU has better performance 15 ns × 100% = (12 ns × (100 .Computer Systems Organization and Architecture . a) Clock period = 50 ns Steady state speedup = (40 + 45 + 35 + 50)/50 = 3.75 9.583 b) 150/60 = 2.875 b) 150/40 = 3.125 b) 160/80 = 2 5. a) 18 ns × 100% vs. (12 ns × 98%) + (12 ns × 6 instructions × 2%) average time b) c) d) e) 15 ns > 13. a) Clock period = 70 ns Steady state speedup = (20 + 25 + 20 + 70 + 40)/70 = 2.76 ns + 0. and combine stages 3 and 4 Copyright © 2001 Addison Wesley .56 ns.5 b) 160/70 = 2.72 ns.517 ns 4. x = 5.All Rights Reserved Page 106 .Solutions Manual Chapter 11 1.2 ns.x)%) + (72 ns × x%).x)%) + (96 ns × x%). a) Clock period = 45 ns Steady state speedup = (20 + 25 + 20 + 25 + 45 + 40)/45 = 3.5 instructions x ns × 100% = (12 ns × 98%) + (72 ns × 2%).4 b) 160/50 = 3. x = 18. x = 24.125 instructions x ns × 100% = (16 ns × 96%) + (80 ns × 4%). a) Clock period = 80 ns Steady state speedup = (40 + 80 + 50)/80 = 2. therefore the first CPU has better performance 18 ns × 100% = (16 ns × (100 . x = 13. x = 13.2 ns 15 ns × 100% = (x ns × 98%) + (6x ns × 2%). x = 3. therefore the second CPU has better performance 25 ns × 100% = (24 ns × (100 . (16 ns × 96%) + (16 ns × 5 instructions × 4%) average time b) c) d) e) 18 ns > 18.5 6.72 ns 25 ns × 100% = (x ns × 99%) + (4x ns × 1%).2 8. x = 24.889 b) 160/45 = 3. x = 5% 15 ns × 100% = (12 ns × 98%) + (12 ns × x instructions × 2%). x = 4.272 ns 2.125% 18 ns × 100% = (16 ns × 96%) + (16 ns × x instructions × 4%).636 ns 3.x)%) + (80 ns × x%).389% 25 ns × 100% = (24 ns × 99%) + (24 ns × x instructions × 1%). a) Clock period = 40 ns Steady state speedup = (30 + 25 + 20 + 40 + 40)/40 = 3. a) Clock period = 60 ns Steady state speedup = (30 + 25 + 60 + 40)/60 = 2.

a) 2 no-ops b) 2 no-ops 15.1 N1 5 3 N2 2 6 4 3 N2 7 8 9 10 11 5 N3 6 4 5 N3 6 3 4 5 N3 6 b) Stage\Cycle 1 2 3 1 1 - 2 4 1 - 3 2 4 1 4 5 2 4 5 3 5 2 6 6 3 5 7 6 3 8 6 c) Stage\Cycle 1 2 3 1 1 - 2 2 1 - 3 S 2 1 4 3 S 2 5 S 3 S 6 4 S 3 7 5 4 S 8 S 5 4 9 6 S 5 10 11 6 S 6 d) Stage\Cycle 1 2 3 1 1 - 2 2 1 - 3 3 2 1 4 4 3 2 5 5 4 3 6 6 5 4 7 6 5 8 6 Copyright © 2001 Addison Wesley .. L = 12 local registers 188 registers = 20 global registers + 12 windows × (C input registers + 10 local registers). 10 global registers + 8 windows × (4 input registers + 10 local registers) = 122 registers Note: Common output registers are not counted since they are already counted as common input registers of the next window. W = 6 windows 192 registers = 12 global registers + 10 windows × (6 input registers + L local registers).Solutions Manual 10. 160 registers = 16 global registers + W windows × (8 input registers + 16 local registers).All Rights Reserved Page 107 .1 N1 2 . a) 1: R1 ← R2 + R3 N1:No-op 2: R4 ← R1 + R2 N2:No-op 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 N3:No-op 6: R7 ← R5 + R6 1: R1 ← R2 + R3 4: R5 ← R2 + R6 2: R4 ← R1 + R2 5: R6 ← R1 + R2 3: R3 ← R1 + R4 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 Stage\Cycle 1 2 3 1 2 3 4 1 N1 2 N2 . 13. C = 4 common input (and common output) registers 11. 14. 12.Computer Systems Organization and Architecture .

Solutions Manual 1: R1 ← R2 + R3 N1:No-op N2:No-op 2: R4 ← R1 + R2 N3:No-op N4:No-op 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 N5:No-op N6:No-op 6: R7 ← R5 + R6 1: R1 ← R2 + R3 4: R5 ← R2 + R6 N1:No-op 2: R4 ← R1 + R2 5: R6 ← R1 + R2 N2:No-op 3: R3 ← R1 + R4 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 16.1 N1 N2 2 ..1 N1 6 N4 N3 2 N2 7 3 N4 N3 2 8 4 3 N4 N3 9 5 4 3 N4 10 N5 5 4 3 11 N6 N5 5 4 12 6 N6 N5 5 13 14 15 6 N6 6 N5 N6 6 b) Stage\Cycle 1 2 3 4 1 1 - 2 3 4 5 6 4 N1 2 5 N2 1 4 N1 2 5 .All Rights Reserved Page 108 .1 4 N1 2 .1 N1 N2 ...1 4 N1 7 3 N2 5 2 8 6 3 N2 5 9 10 11 6 3 6 N2 3 6 c) Stage\Cycle 1 2 3 4 1 1 - 2 S 1 - 3 S S 1 - 4 2 S S 1 5 S 2 S S 6 S S 2 S 7 3 S S 2 8 4 3 S S 9 10 11 5 S S 4 5 S 3 4 5 S 3 4 12 6 S S 5 13 14 15 6 S S 6 S 6 d) Stage\Cycle 1 2 3 4 1 1 - 2 2 1 - 3 3 2 1 - 4 4 3 2 1 5 5 4 3 2 6 6 5 4 3 7 6 5 4 8 9 6 5 6 Copyright © 2001 Addison Wesley .. a) Stage\Cycle 1 2 3 4 1 2 3 4 5 1 N1 N2 2 N3 .Computer Systems Organization and Architecture .

a) Stage\Cycle 1 2 3 4 5 1 2 3 4 5 6 1 N1 N2 2 N3 N4 ....All Rights Reserved Page 109 .1 4 N1 2 5 .1 4 N1 2 .1 N1 N2 2 ..1 N1 N2 2 N3 .....Computer Systems Organization and Architecture .1 N1 7 3 N4 N3 2 N2 8 4 3 N4 N3 2 9 5 4 3 N4 N3 10 N5 5 4 3 N4 11 N6 N5 5 4 3 12 6 N6 N5 5 4 13 14 15 16 6 N6 6 N5 N6 6 5 N5 N6 6 b) Stage\Cycle 1 2 3 4 5 1 1 - 2 3 4 5 6 7 4 N1 2 5 N2 3 1 4 N1 2 5 N2 .Solutions Manual 1: R1 ← R2 + R3 N1:No-op N2:No-op 2: R4 ← R1 + R2 N3:No-op N4:No-op 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 N5:No-op N6:No-op 6: R7 ← R5 + R6 1: R1 ← R2 + R3 4: R5 ← R2 + R6 N1:No-op 2: R4 ← R1 + R2 5: R6 ← R1 + R2 N2:No-op 3: R3 ← R1 + R4 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 1: R1 ← R2 + R3 2: R4 ← R1 + R2 3: R3 ← R1 + R4 4: R5 ← R2 + R6 5: R6 ← R1 + R2 6: R7 ← R5 + R6 17..1 N1 N2 .1 4 N1 8 6 3 N2 5 2 9 10 11 12 6 3 6 N2 3 6 5 N2 3 6 c) Stage\Cycle 1 2 3 4 5 Stage\Cycle 1 2 3 4 5 1 1 1 1 - 2 S 1 2 2 1 - 3 S S 1 3 3 2 1 - 4 2 S S 1 4 4 3 2 1 - 5 S 2 S S 1 5 5 4 3 2 1 6 S S 2 S S 6 6 5 4 3 2 7 3 S S 2 S 7 6 5 4 3 8 4 3 S S 2 8 9 10 11 5 S S 4 5 S 3 4 5 S 3 4 S S 3 9 10 12 6 S S 5 4 13 14 15 16 6 S S 5 6 S S 6 S 6 d) 6 5 4 6 5 6 Copyright © 2001 Addison Wesley .

.All Rights Reserved Page 110 . a) Stage\Cycle 1 2 3 1 2 3 4 1 N1 2 3 .Solutions Manual 1: R1 ← R2 + R3 N1:No-op 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 N2:No-op 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 3: R2 ← R3 + R4 4: R5 ← R6 + R7 2: R1 ← R1 + R2 5: R5 ← R5 + R7 6: R6 ← R1 + R2 18.1 N1 2 .Computer Systems Organization and Architecture .1 N1 5 6 7 8 9 10 4 N2 5 6 3 4 N2 5 6 2 3 4 N2 5 6 b) Stage\Cycle 1 2 3 1 1 - 2 3 1 - 3 4 3 1 4 2 4 3 5 5 2 4 6 6 5 2 7 6 5 8 6 c) 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2 Stage\Cycle 1 2 3 1 1 - 2 2 1 - 3 3 2 1 4 S 3 2 5 4 S 3 6 5 4 S 7 S 5 4 8 6 S 5 9 10 6 S 6 d) Stage\Cycle 1 2 3 1 1 - 2 2 1 - 3 3 2 1 4 4 3 2 5 5 4 3 6 6 5 4 7 6 5 8 6 Copyright © 2001 Addison Wesley .

Computer Systems Organization and Architecture - Solutions Manual 1: R1 ← R2 + R3 N1:No-op N2:No-op 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 N3:No-op N4:No-op 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 3: R2 ← R3 + R4 4: R5 ← R6 + R7 N1:No-op 2: R1 ← R1 + R2 5: R5 ← R5 + R7 N2:No-op 6: R6 ← R1 + R2 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2

19. a)

Stage\Cycle 1 2 3 4

1 2 3 4 5 1 N1 N2 2 3 - 1 N1 N2 2 - - 1 N1 N2 - - - 1 N1

6 4 3 2 N2

7 N3 4 3 2

8 N4 N3 4 3

9 5 N4 N3 4

10 6 5 N4 N3

11 12 13 6 5 6 N4 5

6

b)

Stage\Cycle 1 2 3 4

1 1 -

2 3 1 -

3 4 5 6 7 4 N1 2 5 N2 3 4 N1 2 5 1 3 4 N1 2 - 1 3 4 N1

8 6 N2 5 2

9 10 11 6 N2 6 5 N2 6

c)

Stage\Cycle 1 2 3 4

1 1 -

2 2 1 -

3 S 2 1 -

4 S S 2 1

5 3 S S 2

6 4 3 S S

7 S 4 3 S

8 S S 4 3

9 10 11 12 13 5 6 S 5 6 S S 5 6 4 S S 5 6

d)

Stage\Cycle 1 2 3 4

1 1 -

2 2 1 -

3 3 2 1 -

4 4 3 2 1

5 5 4 3 2

6 6 5 4 3

7 6 5 4

8

9

6 5

6

Copyright © 2001 Addison Wesley - All Rights Reserved

Page 111

Computer Systems Organization and Architecture - Solutions Manual 1: R1 ← R2 + R3 N1:No-op N2:No-op 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 N3:No-op N4:No-op 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 3: R2 ← R3 + R4 4: R5 ← R6 + R7 N1:No-op 2: R1 ← R1 + R2 5: R5 ← R5 + R7 N2:No-op 6: R6 ← R1 + R2 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2 1: R1 ← R2 + R3 2: R1 ← R1 + R2 3: R2 ← R3 + R4 4: R5 ← R6 + R7 5: R5 ← R5 + R7 6: R6 ← R1 + R2 Stage\Cycle 1 2 3 Stage\Cycle 1 2 3 Stage\Cycle 1 2 3 1 1 1 1 1 1 2 2 1 2 2 1 2 4 1 3 3 2 1 3 3 2 1 3 5 4 1 4 S 3 2 4 4 3 2 4 2 5 4

20. a)

Stage\Cycle 1 2 3 4 5

1 2 3 4 5 6 1 N1 N2 2 3 4 - 1 N1 N2 2 3 - - 1 N1 N2 2 - - - 1 N1 N2 - - - - 1 N1

7 N3 4 3 2 N2

8 N4 N3 4 3 2

9 5 N4 N3 4 3

10 6 5 N4 N3 4

11 12 13 14 6 5 6 N4 5 6 N3 N4 5

6

b)

Stage\Cycle 1 2 3 4 5

1 1 -

2 3 1 -

3 4 5 6 7 8 4 N1 2 5 N2 6 3 4 N1 2 5 N2 1 3 4 N1 2 5 - 1 3 4 N1 2 - - 1 3 4 N1

9 10 11 12 6 N2 6 5 N2 6 2 5 N2 6

c)

Stage\Cycle 1 2 3 4 5 Stage\Cycle 1 2 3 4 5 5 6 7 8 S 10 S S 10 3 S S 10 5 6 7 8 5 N N 2 4 5 N N 3 4 5 N 5 3 2 5 6 4 3 2 7 5 4 3 8 2 5 4

1 1 1 1 -

2 2 1 2 2 1 -

3 S 2 1 3 3 2 1 -

4 S S 2 1 4 4 3 2 1 -

5 3 S S 2 1 5 5 4 3 2 1

6 4 3 S S 2 6 6 5 4 3 2

7 S 4 3 S S 7 6 5 4 3

8 S S 4 3 S 8

9 10 11 5 6 S 5 6 S S 5 4 S S 3 4 S 9 10

12 13 14

6 5 S

6 5

6

d)

6 5 4

6 5

6

21.

22.

9 3 2 N

10 4 3 2

11 5 4 3

12 N 5 4

13 14 15 N N N 5 N N

23.

9 10 11 3 2 3 5 2 3

Copyright © 2001 Addison Wesley - All Rights Reserved

Page 112

Computer Systems Organization and Architecture - Solutions Manual 1: R1 ← R1 + R2 2: R3 ← R3 + R4 3: R5 ← R1 + R5 4:JUMP 9 N1:No-op N2:No-op 9: R2 ← R1 + R3 1: R1 ← R1 + R2 4:JUMP 9 2: R3 ← R3 + R4 3: R5 ← R1 + R5 9: R2 ← R1 + R3

24. a)

Stage\Cycle 1 2 3

1 1 -

2 2 1 -

3 3 2 1

4 5 6 7 8 9 4 N1 N2 9 3 4 N1 N2 9 2 3 4 N1 N2 9

b)

Stage\Cycle 1 2 3

1 1 -

2 4 1 -

3 2 4 1

4 3 2 4

5 9 3 2

6 9 3

7

9

c)

1: R1 ← R1 + R2 2: R3 ← R3 + R4 3: R5 ← R1 + R5 4:JUMP 9 9: R2 ← R1 + R3 1: R1 ← R1 + R2 2: R3 ← R3 + R4 N1:No-op 3: R5 ← R1 + R5 4:JUMP 9 N2:No-op N3:No-op 9: R2 ← R1 + R3 1: R1 ← R1 + R2 4:JUMP 9 2: R3 ← R3 + R4 3: R5 ← R1 + R5 N:No-op 9: R2 ← R1 + R3

Stage\Cycle 1 2 3

1 1 -

2 2 1 -

3 3 2 1

4 4 3 2

5 S 4 3

6 S S 4

7 9 S S

8 9 S

9

9

25. a)

Stage\Cycle 1 2 3 4

1 1 -

2 3 4 5 6 2 N1 3 4 N2 1 2 N1 3 4 - 1 2 N1 3 - - 1 2 N1

7 N3 N2 4 3

8 9 N3 N2 4

9 10 11 9 N3 9 N2 N3 9

b)

Stage\Cycle 1 2 3 4

1 1 -

2 4 1 -

3 2 4 1 -

4 5 6 7 8 9 3 N 9 2 3 N 9 4 2 3 N 9 1 4 2 3 N 9

c)

1: R1 ← R1 + R2 2: R3 ← R3 + R4 3: R5 ← R1 + R5 4:JUMP 9 9: R2 ← R1 + R3

Stage\Cycle 1 2 3 4

1 1 -

2 2 1 -

3 3 2 1 -

4 S 3 2 1

5 4 S 3 2

6 S 4 S 3

7 S S 4 S

8 9 S S 4

9 10 11 9 S S

9 S

9

Copyright © 2001 Addison Wesley - All Rights Reserved

Page 113

.1 2 3 4 .Solutions Manual 1: R1 ← 3 2: R2 ← R2 + R3 3: R3 ← R3 + R4 4: R4 ← R1 + R2 5: R1 ← R1 − 1 N1:No-op 6: IF (R1 ≠ 0) THEN GOTO 2 N2:No-op N3:No-op 7: R5 ← R6 + R7 8: R6 ← R7 + R8 1 2 3 4 5 1 2 3 4 5 .1 2 3 6 7 8 9 10 11 N1 6 N2 N3 2 3 5 N1 6 N2 N3 2 4 5 N1 6 N2 N3 12 4 3 2 13 5 4 3 14 15 16 17 18 19 N1 6 N2 N3 2 3 5 N1 6 N2 N3 2 4 5 N1 6 N2 N3 20 4 3 2 21 5 4 3 22 23 24 25 26 27 28 29 N1 6 N2 N3 7 8 5 N1 6 N2 N3 7 8 4 5 N1 6 N2 N3 7 8 26..1 2 3 6 S 5 4 7 6 S 5 8 S 6 S 9 S S 6 10 2 S S 11 3 2 S 12 4 3 2 13 5 4 3 14 S 5 4 15 6 S 5 16 S 6 S 17 S S 6 18 2 S S 19 3 2 S 20 4 3 2 21 5 4 3 22 S 5 4 23 6 S 5 24 S 6 S 25 S S 6 26 7 S S 27 28 29 8 7 8 S 7 8 Stage\Cycle 1 2 3 Copyright © 2001 Addison Wesley .All Rights Reserved Page 114 . a) Stage\Cycle 1 2 3 b) 1: R1 ← 3 N:No-op 5: R1 ← R1 − 1 2: R2 ← R2 + R3 6: IF (R1 ≠ 0) THEN GOTO 2 3: R3 ← R3 + R4 4: R4 ← R1 + R2 7: R5 ← R6 + R7 8: R6 ← R7 + R8 1 2 3 4 5 1 N 5 2 6 .1 2 3 4 .1 N 5 2 .1 N 5 6 3 6 2 7 4 3 6 8 5 4 3 9 2 5 4 10 6 2 5 11 3 6 2 12 4 3 6 13 5 4 3 14 2 5 4 15 6 2 5 16 3 6 2 17 4 3 6 18 7 4 3 19 20 21 8 7 8 4 7 8 Stage\Cycle 1 2 3 c) 1: R1 ← 3 2: R2 ← R2 + R3 3: R3 ← R3 + R4 4: R4 ← R1 + R2 5: R1 ← R1 − 1 6: IF (R1 ≠ 0) THEN GOTO 2 7: R5 ← R6 + R7 8: R6 ← R7 + R8 1 2 3 4 5 1 2 3 4 5 ..Computer Systems Organization and Architecture .

..1 2 3 6 N 5 4 7 6 N 5 8 2 6 N 9 3 2 6 10 4 3 2 11 5 4 3 12 N 5 4 13 6 N 5 14 2 6 N 15 3 2 6 16 4 3 2 17 5 4 3 18 N 5 4 19 6 N 5 20 2 6 N 21 3 2 6 22 7 3 2 23 24 25 8 7 8 3 7 8 b) 1: R1 ← 3 2: R2 ← R2 + R3 3: R3 ← R3 + R4 4: R4 ← R1 + R2 5: R1 ← R1 − 1 N:No-op 6: IF (R1 ≠ 0) THEN GOTO 2 7: R5 ← R6 + R7 8: R6 ← R7 + R8 Underlined instructions are annulled Stage\Cycle 1 2 3 1 2 3 4 5 1 2 3 4 5 .Computer Systems Organization and Architecture .1 2 3 4 .1 2 3 6 N 5 4 7 6 N 5 8 7 6 N 9 8 7 6 10 2 8 7 11 3 2 8 12 4 3 2 13 5 4 3 14 N 5 4 15 6 N 5 16 7 6 N 17 8 7 6 18 2 8 7 19 3 2 8 20 4 3 2 21 5 4 3 22 N 5 4 23 6 N 5 24 7 6 N 25 26 27 8 7 8 6 7 8 27.1 2 3 4 . a) 1: R1 ← 3 2: R2 ← R2 + R3 3: R3 ← R3 + R4 4: R4 ← R1 + R2 5: R1 ← R1 − 1 N:No-op 6: IF (R1 ≠ 0) THEN GOTO 2 7: R5 ← R6 + R7 8: R6 ← R7 + R8 Underlined instructions are annulled Stage\Cycle 1 2 3 1 2 3 4 5 1 2 3 4 5 .All Rights Reserved Page 115 . 28.1 2 3 4 .Solutions Manual 1: R1 ← 3 2: R2 ← R2 + R3 3: R3 ← R3 + R4 4: R4 ← R1 + R2 5: R1 ← R1 − 1 N:No-op 6: IF (R1 ≠ 0) THEN GOTO 2 7: R5 ← R6 + R7 8: R6 ← R7 + R8 Underlined instructions are annulled Stage\Cycle 1 2 3 1 2 3 4 5 1 2 3 4 5 ..1 2 3 6 N 5 4 7 6 N 5 8 7 6 N 9 8 7 6 10 2 8 7 11 3 2 8 12 4 3 2 13 5 4 3 14 N 5 4 15 6 N 5 16 7 6 N 17 8 7 6 18 2 8 7 19 3 2 8 20 4 3 2 21 5 4 3 22 N 5 4 23 6 N 5 24 7 6 N 25 26 27 8 7 8 6 7 8 Copyright © 2001 Addison Wesley .

diameter = 4. diameter = 8.Computer Systems Organization and Architecture . bandwidth = 1008000 Mb/s. a) b) c) d) e) f) g) 2. d(ring) = n/2. The hardware complexity is O(n2). bandwidth = 10 Mb/s. diameter = 6. diameter = 1. lcc = 12.Solutions Manual Chapter 12 1. diameter = 1. bandwidth = 64000 Mb/s. 5. diameter = 4. bandwidth = 240 Mb/s. bisection bandwidth = 500 Mb/s bisection bandwidth = 1000 Mb/s bisection bandwidth = 500 Mb/s bisection bandwidth = 4000 Mb/s bisection bandwidth = 8000 Mb/s bisection bandwidth = 16000 Mb/s bisection bandwidth = 512000 Mb/s bisection bandwidth = 10 Mb/s bisection bandwidth = 20 Mb/s bisection bandwidth = 10 Mb/s bisection bandwidth = 40 Mb/s bisection bandwidth = 80 Mb/s bisection bandwidth = 80 Mb/s bisection bandwidth = 640 Mb/s d(tree) = 2*lg n. 2*lg n < n/2 for 13 ≤ n ≤ 15 and n ≥ 17 d(mesh) = n . 4. bandwidth = 320 Mb/s. a) bb(mesh) = 2 16 * 100 Mb/s = 800 Mb/s = (16/2 * 16/2) * lcc.5 Mb/s b) 800 Mb/s = 16/2 * lhc. bandwidth = 96000 Mb/s. bandwidth = 320 Mb/s. diameter = 8. b(cc) = (n/2 * n/2) * l. bandwidth = 160 Mb/s. diameter = 1. bandwidth = 500 Mb/s. bandwidth = 1200 Mb/s. (n/2) * lg n * l < (n/2 * n/2) * l for n ≥ 5 6. bandwidth = 31000 Mb/s. n < 2*lg n for 2 ≤ n ≤ 196 b(hc) = (n/2) * lg n * l. diameter = 1. diameter = 6. Copyright © 2001 Addison Wesley . diameter = 32. lhc = 100 Mb/s c) 800 Mb/s = 2 16 / 2 *lmesh. diameter = 16. a) b) c) d) e) f) g) 3. bandwidth = 32000 Mb/s. bandwidth = 150 Mb/s. diameter = 10.All Rights Reserved Page 116 . d(tree) = 2*lg n. diameter = 8. lmesh = 200 Mb/s 7. bandwidth = 56000 Mb/s.

11. 10.Computer Systems Organization and Architecture .Solutions Manual 8. 9.  0 1 2 3 4 5 6 7   1 0 6 2 4 7 5 3  0 1 2 3 4 5 6 7    4 6 7 5 2 1 0 3  0 1 2 3 4 5 6 7    4 3 7 2 6 0 1 5 Circled switches were set randomly. a) b) c) Copyright © 2001 Addison Wesley .All Rights Reserved Page 117 .

Computer Systems Organization and Architecture .All Rights Reserved Page 118 .Solutions Manual 12. a) Module M0 M1 M2 M3 M4 M5 M6 M7 Address Range 0 to 8M − 1 8M to 16M − 1 16M to 24M − 1 24M to 32M − 1 32M to 40M − 1 40M to 48M − 1 48M to 56M − 1 56M to 64M − 1 Addresses 00 0XXX XXXX XXXX XXXX XXXX XXXX 00 1XXX XXXX XXXX XXXX XXXX XXXX 01 0XXX XXXX XXXX XXXX XXXX XXXX 01 1XXX XXXX XXXX XXXX XXXX XXXX 10 0XXX XXXX XXXX XXXX XXXX XXXX 10 1XXX XXXX XXXX XXXX XXXX XXXX 11 0XXX XXXX XXXX XXXX XXXX XXXX 11 1XXX XXXX XXXX XXXX XXXX XXXX Copyright © 2001 Addison Wesley . a) b) c) 13.

Result Read miss Write miss Read miss Write miss Read miss Write miss Read hit Cache 0 Cache 1 1000:K1 E 1000:XX I 1000:K2 S 1000:K3 M 1000:XX I 1000:K3 S 1000:XX I 1000:K4 M 1000:K4 M Copyright © 2001 Addison Wesley . a) Address Range i mod 8 = 0 (0 ≤ i ≤ 64M − 1) i mod 8 = 1 (0 ≤ i ≤ 64M − 1) i mod 8 = 2 (0 ≤ i ≤ 64M − 1) i mod 8 = 3 (0 ≤ i ≤ 64M − 1) i mod 8 = 4 (0 ≤ i ≤ 64M − 1) i mod 8 = 5 (0 ≤ i ≤ 64M − 1) i mod 8 = 6 (0 ≤ i ≤ 64M − 1) i mod 8 = 7 (0 ≤ i ≤ 64M − 1) Address Range i mod 4 = 0 (0 ≤ i ≤ 128M − 1) i mod 4 = 1 (0 ≤ i ≤ 128M − 1) i mod 4 = 2 (0 ≤ i ≤ 128M − 1) i mod 4 = 3 (0 ≤ i ≤ 128M − 1) Address Range i mod 8 = 0 (0 ≤ i ≤ 32M − 1) i mod 8 = 1 (0 ≤ i ≤ 32M − 1) i mod 8 = 2 (0 ≤ i ≤ 32M − 1) i mod 8 = 3 (0 ≤ i ≤ 32M − 1) i mod 8 = 4 (0 ≤ i ≤ 32M − 1) i mod 8 = 5 (0 ≤ i ≤ 32M − 1) i mod 8 = 6 (0 ≤ i ≤ 32M − 1) i mod 8 = 7 (0 ≤ i ≤ 32M − 1) b) c) 15.Computer Systems Organization and Architecture .All Rights Reserved Page 119 .Solutions Manual b) Module M0 M1 M2 M3 Module M0 M1 M2 M3 M4 M5 M6 M7 Module M0 M1 M2 M3 M4 M5 M6 M7 Module M0 M1 M2 M3 Module M0 M1 M2 M3 M4 M5 M6 M7 Action P0 read P2 write P1 read P0 write P3 read P1 write P1 read Address Range 0 to 32M − 1 32M to 64M − 1 64M to 96M − 1 96M to 128M − 1 Address Range 0 to 4M − 1 4M to 8M − 1 8M to 12M − 1 12M to 16M − 1 16M to 20M − 1 20M to 24M − 1 24M to 28M − 1 28M to 32M − 1 Addresses 00X XXXX XXXX XXXX XXXX XXXX XXXX 01X XXXX XXXX XXXX XXXX XXXX XXXX 10X XXXX XXXX XXXX XXXX XXXX XXXX 11X XXXX XXXX XXXX XXXX XXXX XXXX Addresses 0 00XX XXXX XXXX XXXX XXXX XXXX 0 01XX XXXX XXXX XXXX XXXX XXXX 0 10XX XXXX XXXX XXXX XXXX XXXX 0 11XX XXXX XXXX XXXX XXXX XXXX 1 00XX XXXX XXXX XXXX XXXX XXXX 1 01XX XXXX XXXX XXXX XXXX XXXX 1 10XX XXXX XXXX XXXX XXXX XXXX 1 11XX XXXX XXXX XXXX XXXX XXXX Addresses XX XXXX XXXX XXXX XXXX XXXX X000 XX XXXX XXXX XXXX XXXX XXXX X001 XX XXXX XXXX XXXX XXXX XXXX X010 XX XXXX XXXX XXXX XXXX XXXX X011 XX XXXX XXXX XXXX XXXX XXXX X100 XX XXXX XXXX XXXX XXXX XXXX X101 XX XXXX XXXX XXXX XXXX XXXX X110 XX XXXX XXXX XXXX XXXX XXXX X111 Addresses XXX XXXX XXXX XXXX XXXX XXXX XX00 XXX XXXX XXXX XXXX XXXX XXXX XX01 XXX XXXX XXXX XXXX XXXX XXXX XX10 XXX XXXX XXXX XXXX XXXX XXXX XX11 Addresses X XXXX XXXX XXXX XXXX XXXX X000 X XXXX XXXX XXXX XXXX XXXX X001 X XXXX XXXX XXXX XXXX XXXX X010 X XXXX XXXX XXXX XXXX XXXX X011 X XXXX XXXX XXXX XXXX XXXX X100 X XXXX XXXX XXXX XXXX XXXX X101 X XXXX XXXX XXXX XXXX XXXX X110 X XXXX XXXX XXXX XXXX XXXX X111 Cache 2 Shared 1000:K1 1000:K2 M 1000:K1 1000:K2 S 1000:K2 1000:XX I 1000:K2 1000:K3 S 1000:K3 1000:XX I 1000:K3 1000:K4 Cache 3 c) 14.

3 1. 2 → 4 (A).. 2 0 1  2 0 2 0 2 0   2 + 0 0 + 0 1 + 2   2 + 2 0 + 1 2 + 0 0 + 4 2 + 4 0 + 0   2 + 2 0 + 1 3 + 0  4 + 2 1 + 4 2 + 1  4 + 2 6 + 0 0 + 4    4 1 3  6 5 3    6 6 4 1. 6 → 8 (A). 6 → 8 (F) Data output dependencies: 1 → 4 (A).Computer Systems Organization and Architecture .. 3 → 6 (A). 2 → 4 (B). 3 → 4 (D) Data anti-dependencies 2 → 4 (B).3 1. 1 → 6 (A).. 1 → 6 (C). 2 → 7 (B). 3 → 7 (C). 7 → 8 (E) Data anti-dependencies 1 → 2 (B).3 3 - - - Copyright © 2001 Addison Wesley . 2 → 3 (C). 2 → 6 (A). 3 → 5 (C). 19. 3 → 4 (A).Solutions Manual 16.. Data dependencies: 1 → 3 (A).3 k 1 C 18.. 4 → 6 (A). 2 → 4 (D) Data anti-dependencies 3 → 4 (A) Data output dependencies: 1 → 4 (A) Data dependencies: 1 → 2 (A).3 2 1. 2 → 3 (D) . 4 → 5 (D). Data dependencies: i j 1. 20. 2 → 3 (B). Action P2 write P1 read P3 write P2 read P0 read P1 write P2 write Result Cache 0 Cache 1 Write miss Read miss 1100:K1 S Write miss 1100:XX I Read miss Read miss 1100:K2 S Write miss 1100:XX I 1100:K3 M Write miss 1100:XX I Cache 2 1100:K1 M 1100:K1 S 1100:XX I 1100:K2 S 1100:K2 S 1100:XX I 1100:K2 M Cache 3 1100:K2 M 1100:K2 S 1100:K2 S 1100:XX I Shared 1100:K0 1100:K1 1100:K1 1100:K2 1100:K2 1100:K2 1100:K3 17. 2 → 5 (A). 2 → 3 (D).3 1.All Rights Reserved Page 120 . 5 → 7 (E). 4 → 6 (A).. 1 → 3 (C). 3 → 6 (F) Data output dependencies: 1 → 2 (A) 1 → 2 (A). 1 → 3 (A).

G ← A1 + H 22. A ← B + C 2.All Rights Reserved Page 121 . D1 ← C + E 4. B1 ← D1 + F 5. 1. B2 ← C1 + D 5.Computer Systems Organization and Architecture .Solutions Manual 21. 1. B1 ← A + A 3. B3 ← B2 + A Copyright © 2001 Addison Wesley . A ← B + C 2. C1 ← B1 + A 4. A1 ← A + D 3.

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