ECE 124A

VLSI Principles
Lecture 4
Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: @

Lecture 4, ECE 124A, VLSI Principles

Kaustav Banerjee

in scaled CMOS technology in (solution: use STI-shallow trench isolation) Lecture 4. VLSI Principles Kaustav Banerjee ...CMOS Process A single-well CMOS…..which can eliminate the active areas areas…...Bird’s Beak!.. ECE 124A. Note the LOCOS (Local Oxidation of Si) process used for isolation of different transistors A problem with LOCOS is….

wafer has a typical resistivity of 25-50 Ohm-cm. VLSI Principles Kaustav Banerjee .gives significantly better Si/SiO2 interface) Lecture 4. lightly-doped wafer ( g y .Basic Steps-I Steps Si Wafer:         Single-crystalline. ECE 124A. which corresponds to a doing level of the order of 1015 cm-3 Defect density must be very low Well dopings are of the order of 1016 to 1017 cm-3 (this explains the lower doping of the p substrate Crystal orientation: all ICs are manufactured using (100) surface orientation. Why? (f f i t ti Wh ? (fewer i imperfections on a (100) f ti surface…. g y p (6-12 inch diameter) ) Thickness of at most 1mm Obtained by cutting a single crystal ingot into thin slices An epitaxial layer is grown over the surface of the wafers before device processing b f d i i A starting p.

ECE 124A.A Modern CMOS Process gate-oxide id TiSi2 AlCu SiO2 Tungsten poly p-well n-well SiO2 p+ n+ p-epi p p+ DualDual-Well Trench-Isolated CMOS Process Trench----allows ----allows more precise control of substrate doping Lecture 4. VLSI Principles Kaustav Banerjee .

g. ion implantation  Diff Different operations involved i a t i l photolithographic t ti i l d in typical h t lith hi process – Oxidation layering. but has the property that the polymers cross-link when exposed to light. photoresist (PR) coating. acid etching. a certain area of the chip needs to be masked out---using an appropriate optical mask  Desired processing step can be selectively applied to the remaining regions  Needed for a number of processing steps: – oxidation. VLSI Principles Kaustav Banerjee . etching. metal and polysilicon deposition. making the affected areas insoluble.Basic Steps-II Steps Photolithography:  Applied throughout the manufacturing process  In each processing step. ECE 124A. spin-rinse-dry p . p y Negative PR: a light sensitive polymer that is originally soluble in an organic solvent. Positive PR: originally insoluble but soluble after exposure Lecture 4. PR development and bake. stepper exposure.

VLSI Principles .Photolithography: Photomasking with negative photoresist Kaustav Banerjee Lecture 4. ECE 124A.

dry p y 4 In acid or base solutions to remove the non-exposed areas of PR Wafer is “softsoftbaked” to harden the remaining PR 8 Exposed area ready for any process steps such as implantation.PhotoPhoto-Lithographic Process Clean room is needed: density of dust particles around 1-10 per cubic foot of air! 1 10 cubic-foot automated handling of wafers…. p process step 6 7 Clean wafer with deionized water 5 Material is selectively removed from areas of wafer that are not covered by PR Lecture 4. ECE 124A. optical mask Start…. photoresist development acid etch spin. VLSI Principles Kaustav Banerjee . metal deposition etc. 1 oxidation 3b 2 A glass mask or reticle containing g the patterns that we want to transfer to the Si Selectively S l ti l remove remaining PR using high-temperature plasma without damaging device layers 3a photoresist removal (ashing) photoresist coating stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). rinse.

VLSI Principles Kaustav Banerjee . chemical or plasma etch of SiO h i l l h f 2 Hardened resist SiO 2 SiO 2 Lecture 4.Patterning of SiO2 g Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO 2 Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate Si b t t UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure ( ) St Si-substrate () (f) Final result after removal of resist (e) After etching Hardened resist SiO 2 Si-substrate (d) After development and etching of resist. ECE 124A.

Shallow Trench isolation (STI): better suited for small device geometries. VLSI Principles Kaustav Banerjee . Plasma etch trench + grow thi “li thin “liner” oxide (10 20 ” id (10-20 nm) layer + deposit oxide in trench Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows p p y Deposit and pattern metal layers Lecture 4.CMOS Process at a Glance Define active areas Etch and fill trenches Device isolation: Local Oxidation of Si (LOCOS)—Bird’s Beak problem…. ECE 124A.

ECE 124A.Recurring Process Steps-I Steps Diffusion  Wafers placed in quartz tube embedded in a heated furnace (900-1100 C) g gas  Dopants introduced through a g  Dopants diffuse into the exposed surface  Final dopant concentration greatest at the surface and decreases in a gaussian profile deeper into the material  Ion I l t ti I Implantation:  Dopants are introduced as ions in the material  Implantation system directs and sweeps a beam of purified ions over the Si surface  Wafer needs annealing (wafer is heated to 1000 C for 15-30 minutes) to repair lattice damage and to activate the dopants Lecture 4. VLSI Principles Kaustav Banerjee .

ECE 124A. silicon nitride. VLSI Principles Kaustav Banerjee . poly etc) are directly deposited  Using a chemical deposition process (CVD etc)  Etching:  Wet etching: uses acid or basic solutions  Dry etching: uses plasma (like sandblasting…)  Planarization  Surfaces must be flat  Chemical Mechanical Polishing (CMP) before deposition Lecture 4.Recurring Process Steps-II Steps Deposition  Many of the materials (gate oxide.

CMOS Process Walk-Through Walkp-epi p epi + p SiN 34 p-epi + p SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) (a) Base material: p+ substrate ( )B t i l b t t with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask Lecture 4. ECE 124A. VLSI Principles Kaustav Banerjee .

VLSI Principles Kaustav Banerjee . ECE 124A.CMOS Process Walk-Through WalkSiO 2 ( ) (d) After trench filling. CMP g. planarization. and removal of sacrificial nitride n (e) After n-well and V adjust implants Tp p (f) After p-well and V adjust implants Tn Lecture 4.

CMOS Process Walk-Through Walkpoly(silicon) (g) After polysilicon deposition and etch n + + p (h) After n+ source/drain and p+source/drain i l t Th + /d i implants. ECE 124A. Lecture 4. VLSI Principles Kaustav Banerjee . SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. These steps also dope the polysilicon.

Lecture 4. etching of via’s. VLSI Principles Kaustav Banerjee . ECE 124A. 2 deposition and patterning of second layer of Al.CMOS Process Walk-Through WalkAl (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO insulator.

ECE 124A. Lecture 4.Advanced Metallization Older (prior to 1997) VLSI interconnect technology: used AlCu for lines and W for i f vias…. VLSI Principles Kaustav Banerjee .

Advanced Metallization: Cu based Lecture 4. ECE 124A. VLSI Principles Kaustav Banerjee .

com Lecture 4.amd. VLSI Principles Kaustav Banerjee .Fully Processed Wafer u y ocessed a e Single die Wafer Going up to 12” (30cm) From http://www. ECE 124A.

Tri-Gate---Intel) Tri-Gate---Intel) Tri-gate Gate 3 Drain Multi-Fin Structure Lg Gate 1 WSi TSi Gate 2 Gate Drain Source Source: Intel Source Improved short-channel effects short channel Higher ON current for lower SD Leakage Even better FETs: i) Gate All Around FETs--.New Transistors: Double Gate FETs (FinFETs— (FinFETs—Berkeley. VLSI Principles Kaustav Banerjee .ultimate case is GAA Si Nanowire FET or Gate-All-Around FETs ii) Carbon Nanotube FETs (back-gated or top-gated structures) Lecture 4. ECE 124A.