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Creating Sine-Wave Modulated PWM Signal

V1.2 - May 29, 2006 English Version

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Creating Sine-Wave Modulated PWM Signal

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Creating Sine-Wave Modulated PWM Signal

Revision History
Page Number(s)

Revision V1.3 V1.2

Date 2006/12/22 2006/05/29

By Li Jing Li Jing Proofreading

Remark

Translate Creating Sine-Wave Modulated PWM Signal V1.2, Chinese version

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Table of Content
PAGE

1 System Design Summary .................................................................................................................. 1 1.1 System Design .............................................................................................................................. 1 1.2 Sine-Wave Generating Principle ................................................................................................... 1 2 Design Tips ......................................................................................................................................... 4 2.1 Demo ............................................................................................................................................. 4 3 Flow Charts ......................................................................................................................................... 7 3.1 Main Process Description.............................................................................................................. 7 3.2 ISR Description.............................................................................................................................. 7 4 MCU Resource .................................................................................................................................... 9 5 Test..................................................................................................................................................... 10 5.1 Test Circuit ................................................................................................................................... 10 5.2 Test Waveform............................................................................................................................. 10

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1 System Design Summary


1.1 System Design
MCP timer on the SPMC75F2413A chip is dedicated to driving a motor which can generate

various PWM signals according to user settings. This application selects TMR3 to generate six programmable center-aligned SPWM waveform output signals with 120 degrees out of phase. The hardware structure is shown in Figure 1-1.

Figure 1-1 Hardware Structure

Where, PWMUN = ! PWMU, PWMVN = ! PWMV, PWMWN = ! PWMW. Affected by dead-time timer, these relations are not absolutely true.

1.2 Sine-Wave Generating Principle


Figure 1-2 uses sawtooth wave to generate the three-phase SPWM waveform. When the input voltage is higher than sawtooth voltage, PWM outputs high; otherwise, PWM outputs low. If the frequency of sawtooth wave is higher than that of input voltage, PWM duty will vary linearly with the input voltage and the period of PWM wave is the same as that of sawtooth wave.

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Creating Sine-Wave Modulated PWM Signal

Figure 1-2 Three-Phase SPWM Generating Principle

The PWM wave can be described by a Fourier decomposition as a Fourier series, thus the amplitude of the lowest frequency can be obtained as:

U 1m = U m [1

1 N

cos(2i 1) N ]
i =1

(1-1)

Where, N is the number of pulses within half waveform and voltage.

U m is the amplitude of input

m , thus the fundamental wave of output voltage is just the sine wave When N>1, 1m needed. In this way we can inhibit the low order harmonic wave effectively.

=U

Practically, PWM waveform is not generated by comparing the values between sine-wave and sawtooth wave. To reduce the CPU burden, the values of PWM duty register are fetched from lookup table stored inside the program memory of CPU according to sinusoidal wave. The main controller generates SPWM by DDS algorithm. As shown in Figure 1-3, it is a typical DDS system except for substituting PWM (with a carrier frequency of 10KHz) for DAC. The phase data is obtained by getting the high 10 bits in the 16-bit accumulator. So we define a 2n (1024) size of data table to speed up this procedure and save the processing cycle in CPU. Accordingly, the error can be calculated as below: The most error of phase is = 360/ 1024 = 0.3516 in theory. Even if we count the software bouncing on, the phase error will not exceed 0.5 at most. Since 1024 is not an integral multiple of 3, the phase-different constants of 120 and 240 have to be presented approximately with an error of 0.5. within 180/2n.
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So the

phase-different constant is not the exact 120 or 240, but the error for Ti must be

Creating Sine-Wave Modulated PWM Signal

Additionally, the more depiction points are selected, the more precise the generated waveform is, especially under the low frequency mode.

Figure 1-3 Three-Phase SPWM Generating Diagram

Note: The formulas listed above are only suitable for the case that phase error is lower than that of amplitude. In fact, when amplitude error increases, the phase error will increase accordingly. You can define all kinds of waveform in the 1024-point data table, such as a third harmonic enhanced waveform.

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2 Design Tips
2.1 Demo
#include "Spmc75_regs.h" #include "unspmacro.h" void SPMC75_SPWM_Init(void); void SPMC75_SPWM_ISR(void); void SPMC75_SPWM(unsigned int F,unsigned int AM); main() { Disable_FIQ_IRQ(); SPMC75_SPWM_Init(); INT_IRQ(); SPMC75_SPWM(0x3200,0); // Set output frequency as 50Hz while(1); } //===================================================================== // Description: IRQ3 interrupt source is XXX,used to XXX // Notes: //===================================================================== void IRQ3(void) __attribute__ ((ISR)); void IRQ3(void) { if(P_TMR3_Status->B.TPRIF) { P_TMR3_Status->B.TPRIF = 1; // Clear TPRIF flag SPMC75_SPWM_ISR(); } } #include "Spmc75_regs.h" const unsigned int Sin_TAB_dot = 1024;// Size of sine-wave lookup table const unsigned int Phases_120 = 341; // Offset at 120 degrees in sine-wave table const unsigned int Phases_240 = 682; // Offset at 240 degrees in sine-wave table extern int iSin_TAB[]; // Using DDFS algorithm to generate SPWM waveform static unsigned int g_uiAM_Data; // SPWM amplitude

modulation coefficient
static unsigned int g_uiSPWM_phases_Add; static unsigned int g_uiPhases_Add_Data; static unsigned int PWM_shift; // SPWM phase accumulation // SPWM phase increment

void SPWM_AM_MUL(int *p_Data,unsigned int uiK); unsigned int ASM_MUL(unsigned int a,unsigned int b); //===================================================================== // ----Function: void SPWM_TMR3_Init(void); // -Description: TMR3_module initialize function // --Parameters: None

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Creating Sine-Wave Modulated PWM Signal // -----Returns: None // -------Notes: //===================================================================== void SPMC75_SPWM_Init(void) { P_IOB_Dir->W |= 0x00bf; // IO setting 0x00ff P_IOB_Attrib->W |= 0x00bf; P_IOB_Buffer->W &= 0xff00; P_IOB_Buffer->W |= 0x0047; P_IOB_SPE->W |= 0x003f; // MCP write enable P_TPWM_Write->W |= CW_TWCR_TMR3WE; /* Configure MCP control registers, make MCP operate on PWM mode, count on FCK/1, at rising edge, clear on TPR match, interrupt every period. */ P_TMR3_Ctrl->B.PRDINT = CB_TMR3_PRDINT_Period; P_TMR3_Ctrl->B.MODE = CB_TMR3_MODE_PWM_Center; P_TMR3_Ctrl->B.CCLS = CB_TMR3_CCLS_TPR; P_TMR3_Ctrl->B.CKEGS = CB_TMR3_CKEGS_Rising; P_TMR3_Ctrl->B.TMRPS = CB_TMR3_TMRPS_FCKdiv1; // Set dead time P_TMR3_DeadTime->B.DTWE = 1; P_TMR3_DeadTime->B.DTVE = 1; P_TMR3_DeadTime->B.DTUE = 1; P_TMR3_DeadTime->B.DTP = 4; // Set timer period and initial duty P_TMR3_TPR->W = 2048; P_TMR3_TGRA->W = (unsigned int)iSin_TAB[0]; P_TMR3_TGRB->W = (unsigned int)iSin_TAB[Phases_120]; P_TMR3_TGRC->W = (unsigned int)iSin_TAB[Phases_240]; // Set PWM output mode, output polarity, and IO P_TMR3_OutputCtrl->B.DUTYMODE = CB_TMR3_DUTYMODE_Independent; P_TMR3_OutputCtrl->B.POLP = CB_TMR3_POLP_Active_High; P_TMR3_OutputCtrl->W |= CW_TMR3_UOC_Mode0 + CW_TMR3_VOC_Mode0; P_TMR3_OutputCtrl->W |= CW_TMR3_WOC_Mode0 + CW_TMR3_WPWM_Out_PWM; P_TMR3_OutputCtrl->W |= CW_TMR3_VPWM_Out_PWM + CW_TMR3_UPWM_Out_PWM; P_TMR3_OutputCtrl->B.SYNC = CB_TMR3_SYNC_NoSync; P_TMR3_IOCtrl->W = CW_TMR3_IOCMOD_Output_01+CW_TMR3_IOBMOD_Output_01; P_TMR3_IOCtrl->W |= CW_TMR3_IOAMOD_Output_01; P_TMR_Output->W |= 0x003f; P_TMR3_INT->B.TPRIE = CB_TMR3_TPRIE_Enable; } //===================================================================== // ----Function: void SPWM_ISR(void); // -Description: SPWM generating ISR // --Parameters: // -----Returns: // -------Notes: //===================================================================== void SPMC75_SPWM_ISR(void) { unsigned int uiPhases_Temp;

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Creating Sine-Wave Modulated PWM Signal int iNEW_Data[3]; g_uiSPWM_phases_Add += g_uiPhases_Add_Data; // Phase accumulation uiPhases_Temp = g_uiSPWM_phases_Add >> 6; // Obtain phase value iNEW_Data[0] = iSin_TAB[uiPhases_Temp]; // Look up next data iNEW_Data[1] = iSin_TAB[(uiPhases_Temp + Phases_120)&(Sin_TAB_dot - 1)]; iNEW_Data[2] = iSin_TAB[(uiPhases_Temp + Phases_240)&(Sin_TAB_dot - 1)]; SPWM_AM_MUL(iNEW_Data,g_uiAM_Data); // Modulate amplitude P_TMR3_TGRA->W = (unsigned int)iNEW_Data[0]; // Update data P_TMR3_TGRB->W = (unsigned int)iNEW_Data[1]; P_TMR3_TGRC->W = (unsigned int)iNEW_Data[2]; P_TMR_LDOK->W |= CW_TMR_LDOK0; // Enable data update synchronously } //===================================================================== // ----Function: void SPMC75_SPWM(unsigned int F,unsigned int AM); // -Description: // --Parameters: // -----Returns: // -------Notes: //===================================================================== void SPMC75_SPWM(unsigned int F,unsigned int AM) { if(F > 0) { g_uiPhases_Add_Data = ASM_MUL(F,5726); P_TMR_Start->B.TMR3ST = 1; } else { g_uiPhases_Add_Data = 0; P_TMR_Start->B.TMR3ST = 0; } g_uiAM_Data = AM; }

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3 Flow Charts
3.1 Main Process Description
The main program mainly performs the system initialization, then calls SPMC75_SPWM (unsigned int F, unsigned int AM) function to update the waveform parameters. Changing the value of F (Q8 format) means to change the base frequency of SPWM and changing the value of AM (Q16 format) means to change the amplitude of SPWM base frequency. Figure 3-1 flow charts the main process.

Figure 3-1 Main Process

3.2 ISR Description


Once entering PWM period interrupt, system will perform DDS operation. By adding the phase increment N (proportional to PWM frequency) to the initial phase, the new waveform phase will be acquired, then look up the corresponding amplitude, 120-degree and 240-degree phase interval amplitudes. At last, multiply these three amplitude values by AM (amplitude modulation coefficient), and then input them to PWM generating module to generate corresponding PWM signals. Figure 3-2 flow charts the ISR process.

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Figure 3-2 ISR Process

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4 MCU Resource

CPU Type

SPMC75F2413A crystal

Package Frequency Input frequency 6MHz

QFP80-0.8

Oscillator external WATCHDOG Enable Disable IOA[11]: TCLKA IO port Use IOA[12]: TCLKB IOB[02]: PWM output Timer Interrupt ROM MCP3 SPWM generator

MCP3 (IRQ3): encoder interface 1.48K Words

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5 Test
5.1 Test Circuit
The test circuit, as shown in Figure 5-1, uses 2nd-order low-pass filter to filter the high

R1C1 = R2 C 2 = RC and R1 << R2 , the cut-off frequency of filter will 1 Fc = 2RC =795Hz. be
when
32 31 30 29 28 27 26 25 24 23 22 21 20 U1 SPMC75F2413A - QFP64 VSS VDD IOA15/ADCTRG IOA14/TCLKD IOA13/TCLKC IOA12/TCLKB IOA11/TCLKA IOA10/TIO2B IOA9/TIO2A IOA8 IOB15 IOB14 IOB13/SDO/TXD1

frequency component of SPWM signal thus to obtain the base frequency. In the circuit,

IOC3/EXINT1 IOC4/BZO IOC5/TIO1A IOC6/TIO1B IOC7/TIO1C IOC8/OL2 IOC9/FTIN2 IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12/TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

IOA0/AN0 IOA1/AN1 IOA2/AN2 IOA3/AN3 IOA4/AN4 IOA5/AN5 IOA6/AN6 IOA7/AN7 VEXTREF AVSS AVDD VDDL XTAL1 XTAL2 VSSL IOD4 IOC0/RXD2 IOC1/TXD2 IOC2/EXINT0

IOB12/SDI/RXD1 IOB11/SCK IOB10/TIO0A IOB9/TIO0B IOB8/TIO0C IOB7/OL1 IOB6/FTIN1 IOB5/TIO3A/U1 IOB4/TIO3B/V1 IOB3/TIO3C/W1 IOB2/TIO3D/U1N IOB1/TIO3E/V1N IOB0/TIO3F/W1N IOD3 RESET IOD2 IOD1/ICESDA IOD0/ICECLK TEST/ICEN

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

R1 2K

R2

1M

A_Out C2 201

C1 104

R1 2K

R2

1M

A_Out C2 201

C1 104

R1 2K

R2

1M

A_Out C2 201

C1 104

5.2 Test Waveform


The test waveforms are listed in the following. Here the output frequency of signal

waveform is 10Hz, 25Hz, 50Hz, 100Hz or 200Hz respectively. Since adopting passive filter, the actual waveform amplitude may have some difference from the ideal waveform amplitude.

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52 53 54 55 56 57 58 59 60 61 62 63 64

Figure 5-1 Test Circuit

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Type Time Source Delta

Coursor1 Coursor2

Type Time Source Delta

Coursor1

Coursor2

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