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147352

ELECTRONIC CIRCUITS I LAB

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Expt No.1 Fixed Bias amplifier circuit using BJT 1.Waveforms at input and output without bias. 2.Determination of bias resistance to locate Q-point at center of load line. 3.Measurement of gain. 4.Plot the frequency response & Determination of Gain Bandwidth Product Expt No.2 Design and construct BJT Common Emitter Amplifier using voltage divider bias (self-bias) with and without bypassed emitter resistor. 1.Measurement of gain. 2.Plot the frequency response & Determination of Gain Bandwidth Product Expt No.3 Design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias). 1.Measurement of gain. 2.Plot the frequency response & Determination of Gain Bandwidth Product Expt No.4 Darlington Amplifier using BJT. 1.Measurement of gain and input resistance. 2.Comparison with calculated values. 3.Plot the frequency response & Determination of Gain Bandwidth Product Expt No.5 Source follower with Bootstrapped gate resistance 1.Measurement of gain, input resistance and output resistance with and without Bootstrapping. 2.Comparison with calculated values. Expt No.6 Differential amplifier using BJT Measurement of CMRR. Expt No.7 Class A Power Amplifier 1.Observation of output waveform. 2.Measurement of maximum power output. 3.Determination of efficiency. 4.Comparison with calculated values. Expt No.8 Class B Complementary symmetry power amplifier 1.Observation of the output waveform with crossover Distortion. 2.Modification of the circuit to avoid crossover distortion. 3.Measurement of maximum power output. 4.Determination of efficiency. 5.Comparison with calculated values. Expt No.9 Power Supply circuit - Half wave rectifier with simple capacitor filter. 1.Measurement of DC voltage under load and ripple factor, Comparison with calculated values. 2.Plot the Load regulation characteristics using Zener diode. Expt No.10 Power Supply circuit - Full wave rectifier with simple capacitor filter 1.Measurement of DC voltage under load and ripple factor, Comparison with calculated values. 2.Measurement of load regulation characteristics. Comparison with calculated values.

Circuit diagram of Fixed Bias amplifier:

Model Graph:

f1 Tabular Column:

f2

f (Hz)

Keep the input voltage constant (Vin) = Frequency (Hz) Output voltage (volts) Gain=20log(V0/Vin) db

Ex. no: Date: COMMON EMITTER AMPLIFIER WITH FIXED BIAS Aim: To design and construct BJT Common Emitter Amplifier using fixed bias . To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW) and bias resistance to locate Q-point at center of load line. Apparatus Required: S.No. 1. 2. 3. 4. 5. 6. 7. Theory: In order to operate the transistor in the desired region, we have to apply an external dc voltage of correct polarity and magnitude to the two junctions of the transistor. This is called biasing of the transistor. When we bias a transistor, we establish certain current and voltage conditions for the transistor. These conditions are called operating conditions or dc operating point or quiescent point. This point must be stable for proper operation of transistor. An important and common type of biasing is called Fixed Biasing. The circuit is very simple and uses only few components. But the circuit does not check the collector current which increases with the rise in temperature. Design : Choose = 250, VCC = 12V, IC = 1 mA By applying KVL to output side, V CC I CR C V CE = 0 V CC = I C R C V CE Assume equal drops across RC and VCE VRC = VCE = 6V, ICRC = 6V RC = 6V/10-3 = 6K Choosing a standard value for RC as 5.1 K By applying KVL to the input side, V CC I BR B V BE = 0 IB = IC/ = 1mA/250 = 4A RB = (VCC VBE) / IB = (12 0.7)/4x10-6 = 2.825M 3M Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Bread Board and Connecting wires Range BC 107 5.1k, 3M 0.01F (0-3)MHz 30MHz (0-30)V Quantity 1 1,1 2 1 1 1 1

Design of input capacitor: F = 1/2hieC Take F = 1000Hz and hie = 1.6 K C1 = 1/ (2 X 1.6 K X 100) = 0.09F 0.01 F

Procedure: 1) Connect the circuit as per the circuit diagram 2) Set Vin = 0.2V in the signal generator. Keeping input voltage constant, vary the frequency from 100Hz to 1MHz in regular steps. 3) Note down the corresponding output voltage. 4) Plot the graph: Gain in dB Vs Frequency in Hz. 5) Calculate the Bandwidth from the Frequency response graph

Result : Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and the frequency response curve is plotted. The bandwidth is found to be ------The bias resistance ------Gain Bandwidth product -----

Circuit diagram of Common Emitter Amplifier:

Model graph:

f1 Tabular column: Keep the input voltage constant (Vin) = Frequency (Hz) Output voltage (volts)

f2

f (Hz)

Gain=20log(V0/Vin) db

Ex. no: Date: COMMON EMITTER AMPLIFIER USING VOLTAGE BIAS Aim: To design and construct BJT Common Emitter Amplifier using voltage bias (self bias) with and without bypassed emitter resistor. To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). Apparatus Required: S.No. 1. 2. 3. 4. 5. 6. 7. Theory: Combination of fixed and self-bias can be used to improve stability and at the same time overcome some of the disadvantages of the other two biasing methods. One of the most widely used combination-bias systems is the voltagedivider type. The voltage divider is formed using external resistors R1 and R2. The voltage across R2 forward biases the emitter junction. By proper selection of resistors R1 and R2, the operating point of the transistor can be made independent of. In this circuit, the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. However, even with a fixed base voltage, collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point. However, to provide long-term or dc thermal stability, and at the same time, allow minimal ac signal degeneration, the bypass capacitor (Cbp) is placed across R3. If Cbp is large enough, rapid signal variations will not change its charge materially and no degeneration of the signal will occur. Merits: Unlike above circuits, only one dc supply is necessary. Operating point is almost independent of variation. Operating point stabilized against shift in temperature. Design: Drop across RE (VRE) is assumed to be 1V. Drop across VCE with the supply of 12V is given by 12V 1V = 11V Assume equal drops across ICRC and VCE So ICRC = VRC = 11/2 = 5.5V Assume IC = 1 mA, Then RC = VRC / IC = 5.5V / 1mA = 5.5 K Instead of using 5.5 K, we can use a standard value of 4.7 K VRE = 1V, IE IC = 1mA RE = VRE/IE = 1V/1mA = 1K Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Bread Board and Connecting wires Range BC 107 61K,10 K,1 K,4.7 K 0.01F, 47F (0-3)MHz 30MHz (0-30)V Quantity 1 1,1 2,1 1 1 1 1

Design of R1 and R2 : Drop across VBE = 0.7V Drop across R2 (VR2) = VBE + VRE = 1.7V Assume R2 = 10 K VR2 = VCC.R2/ (R1+R2) R1 = (12 X 10) / (1.7 10) = 60.5 K R1 is assumed to be 61 K Design of input capacitor : F = 1/2hieC Take F = 1000Hz and hie = 1.6 K C1 = 1/ (2 X 1.6 K X 1000) = 0.09F 0.01 F Procedure: 1) Connect the circuit as per the circuit diagram 2) Set Vin = 0.2V in the signal generator. Keeping input voltage constant, vary the frequency from 100Hz to 1MHz in regular steps. 3) Note down the corresponding output voltage. 4) Plot the graph: Gain in dB Vs Frequency in Hz. 5) Calculate the Bandwidth from the Frequency response graph

Result : Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency response curve is plotted. Bandwidth =

Circuit Diagram Common Collector Transistor Amplifier:

Model graph:

f1 TABULAR COLUMN: Keep the input voltage constant (Vin) = Frequency (Hz) Output voltage (volts)

f2

f (Hz)

Gain=20log(V0/Vin) db

Ex. no: Date: COMMON COLLECTOR TRANSISTOR AMPLIFIER Aim: To design and construct BJT Common Collector Amplifier using voltage divider bias(self-bias). To measure the gain and to plot the frequency response & to determination of Gain Bandwidth Product Apparatus Required: S.No. 1. 2. 3. 4. 5. 6. 7. Design: Since voltage amplification is done in the transistor amplifier circuit, we assume equal drops across VCE and Emitter Resistance RE. VRE = 6V. The quiescent current of 1mA is assumed. We assume a standard supply of Vcc = 12V Drop across RE is assumed to be VRE =6V Drop across VCE is VCC VRE =6V We know that ICQ =IE=IC Now RE = VRE = 6 = 6K IE 1X 10-3 Design of R1 & R2: Drop across RE is 6V Drop across VBE is 0.6V Drop across the resistance R2 is VR2 = VBE + VRE =6.6V Assume R2 =10K VR2= VCC*R2 R1 + R2 6.6 V= 12 X 10 X 103 R1 + 10 X 103 R1 = 8 K (3.3 K + 4.7 K) Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Bread Board and Connecting wires Range BC 107 6K, 8K, 10K 0.01F, 47F (0-3)MHz 30MHz (0-30)V Quantity 1 1 1,1 1 1 1 1

Procedure: 1. Connect the circuit as per the circuit diagram. 2. Set Vin = 1mV using AFO. 3. Keeping the input voltage constant, vary the frequency from 100 Hz to 1 MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph gain Vs frequency. 5. Calculate bandwidth from the graph.

Result : Thus a BJT Common Collector Amplifier is designed and implemented and the frequency response curve is plotted. Bandwidth =

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Circuit diagram of Darlington amplifier:

Model graph:

f1 Tabular column: Frequency (Hz)

f2

f (Hz)

Output voltage (volts)

Gain=20log(V0/Vin) db

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Ex. no: Date: DARLINGTON COMMON EMITTER AMPLIFIER Aim: To design a Darlington amplifier using BJT and to measure the gain and input resistance. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW). Apparatus required: S.No. 1. 2. 3. 4. 5. 6. 7. Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Connecting wires & Breadboard Range BC 107 1K, 4.7K, 47K, 10K 47F, 100F (0-3)MHz 30MHz (0-30)V Quantity 1 1,1,1,1 2, 1 1 1 1 1

Theory: The Darlington amplifier is a useful circuit and has the advantage of providing a very high current gain, high input impedance and higher output power and smaller signal transistor driving a larger power transistor.When using an emitter follower in a circuit, the level of current gain, and the input impedance of the circuit is limited by the current gain that can be achieved using a single transistor. The gain of the Darlington transistor pair is that gain of the two individual transistors multiplied together. The basic Darlington transistor circuit is formed by taking the emitter of the input transistor and connecting it such that its emitter drives the base of the second and then connecting both collectors together. The Darlington pair has more phase shift at high frequencies than a single transistor and hence can more easily become unstable with negative feedback drawback of the Darlington pair is its increased "saturation" voltage. The output transistor is not allowed to saturate (i.e. its base-collector junction must remain reverse-biased) because the first transistor, when saturated, establishes full (100%) parallel negative feedback between the collector and the base of the second transistor. Since collector-emitter voltage is equal to the sum of its own base-emitter voltage and the collector-emitter voltage of the first transistor, both positive quantities in normal operation, it always exceeds the base-emitter voltage. Thus the "saturation" voltage of a Darlington transistor is one VBE (about 0.65 V in silicon) higher than a single transistor saturation voltage, which is typically 0.1 - 0.2 V in silicon.

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Design: Assume R2 = 10K and Ic = 1mA. Since voltage amplification is done in the Darlington transistor amplifier circuit, we assume equal drops across VCE and load resistance RC. The ICQ = 1mA is assumed. We assume standard supply of 12V. Drop across Re is assumed to be 1V. The drop across VCE with a supply of 1.2 V is given by 12 1 = 11V. It is equal to VRC & VCE = 5.5V RC = VRC = 5.5 K (4.7 K) IC Design of R1 & R2: Drop across RE is 1V. Drop across VBE1 & VBE2 is 0.6V. Drop across the resistance R2 is VRE + VBE1 + VBE2 = 1 + 0.6 + 0.6 VR2 = 2.2V R2 is assumed to be 10 K VR2 = VCC R2 R1 + R2 2.2= 12X10 X 103 R1 + 10 X 103 R1 = 44.5 X 103 R1 is rounded to be 47 K Procedure: 1. Connect the circuit as per the circuit diagram. 2. Set Vin = 1 mV using AFO. 3. Keeping the input voltage constant, vary the frequency from 100 Hz to 1 MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph gain Vs frequency. 5. Calculate bandwidth from the graph.

Result: The frequency response curve is plotted on a log scale. From the graph the bandwidth is obtained Bandwidth =

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Circuit diagram of with bootstrapping:

Without bootstrapping:

1.8

Vcc

T B2 4 1 F4 B 1 0
1 0

1.8

T B 24 1 F 4B

10

10

1 0 + F G 470 -

1 0

10

10 + F G 470

CO R -

+ C O R 3

Model graph:

f1 TABULAR COLUMN: Frequency (Hz) Output voltage (volts)

f2

f (Hz)

Gain=20log(V0/Vin) db

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Ex. no: Date: COMMON DRAIN AMPLIFIER Aim: To design a common drain amplifier and to measure the gain, input resistance and output resistance with and without Bootstrapping. Apparatus required: S.No. 1. 2. 3. 4. 5. 6. 7. Name FET Resistor Capacitor Function Generator CRO Regulated power supply Connecting wires & Breadboard Range BFW10 4.7K, 2.7K, 1M 10 F (0-3)MHz 30MHz (0-30)V Quantity 1 1,1,1 1 1 1 1 1

Theory: Source follower is similar to the emitter follower (the output source voltage follow the gate input voltage), the circuit has a voltage gain of less than unity, no phase reversal, high input impedance, low output impedance. Here the Bootstrapping is used to increase the input resistance by connecting a resistance in between gate and source terminals. The gate resister is required to develop the necessary bias for the gate. Here input is applied between gate and source & output between source and Drain. Here Vs = VG + VGS. When a signal is applied to JFET gate via Cin,VG varies with the signal. As VGS is fairly constant and Vs varies with Vi. Here output voltage follows the change in the signal voltage applied to the gate, the circuit is also called as Source follower. The biasing network consists of R1 and R2 lower the input resistor of the gate in source followers. The technique of Boot Strapping of this is used to resolve the high input resistance. Assuming the resistance of external capacitance between the gate and source too negligible at the lowest operating frequency and the gain to the near unit the potential and its upper end, thus the circuit resists its words, practically zero voltage exists across R3 and so it takes an current. Hence R3 is isolated from the input and R1, R2 input to amplifier passes through the gate only. Bias design: VDD = 12 V, IDSS = 9.5mA, ID = 1mA, VP = -4V, Ci = 1F VGS = ID RS , ID = IDSS{1-(VGS/VP)}2 RS = 2.7K , Voltage drop across RS = 2.7V VRD + VDS = VDD-VRS = 12-2.7=9.3V. Assume equal drops across VRD & VDS VRD = VDS = 4.65V RD = VRD/ID = 4.65K Instead of 4.65K, we can select standard value = 4.7K FET input is always reverse bias. So choose the value of resistance RG very large with in the range of 1M to 10M 15

Procedure: 1. Connect the circuit as shown in the circuit diagram 2. Set Vs= 1mv in AFO 3. Keeping the input voltage constant, vary the frequency from 100 Hz to1MHz in regular steps and note down the corresponding output voltage. 4. Plot the graph: gain Vs Frequency 5. Calculate the bandwidth from the Graph

Result: Thus a common drain amplifier is designed and the gain, input resistance and output Resistance is calculated using the measured parameters.

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Circuit Diagram Differential Amplifier

TABULAR COLUMN: Common mode V1 (VOLTS) V2 (VOLTS) Vout (VOLTS)

V1 (VOLTS)

Difference mode V2 (VOLTS) Vout (VOLTS)

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Ex. no: Date: DIFFERENTIAL AMPLIFIER Aim : To construct the Differential Amplifier in Common mode and Differential mode, and to find the common mode rejection ratio (CMRR). Apparatus required : S.No. 1. 2. 3. 4. 5. 6. Name Transistor Resistor Function Generator CRO Regulated power supply Connecting wires & Breadboard Range BC 107 1K, 470 (0-3)MHz 30MHz (0-30)V Quantity 1 2,1 1 1 1 1

Formula: C.M.R.R = Ad/Ac C.M.R.R in dB = 20 log Ad/Ac Ad = Differential mode gain , Ad=Vo/Vd, Where Vd=Vin =V1-V2 Ac = Common mode gain , Ac=Vo/Vc, Where Vc=Vin =V1+V2 2 Theory: The Differential amplifier amplifies the difference between two input voltage signals. Hence it is called differential amplifier.V1 and V2 are input voltages, Vo is proportional to difference between two input signals. If we apply two input voltages equal in all respects then in ideal case output should be zero. But output voltage depends on the average common level of the inputs. Such an average level of two input signals is called common mode signal.Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve C.M.R.R we have to increase differential mode gain and decrease common mode gain. Procedure : 1. Connections are given as per the circuit diagram 2. Set Vi=5mV and note down Vo in both differential mode & common mode 3. Calculate the gain for both the modes 4. Calculate C.M.R.R Result : Thus a differential amplifier is constructed in both common mode and differential mode and the corresponding gains are obtained and the CMRR is calculated. 1. Common mode gain = 2. Differential mode gain = 3. CMRR =

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Circuit Diagram:

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Ex. no: Date: CLASS - A AMPLIFIER Aim: To design and construct a Class A power amplifier. To observe the output waveform and to measure the maximum power output and to determine the efficiency Apparatus required: S.No. Name Range Quantity 1. Transistor BC 107 1 2. Resistor 1K,4.7K,61K,10K 1,1,1,1 3. Capacitors 1f,100f 1,1 4. Function Generator (0-3)MHz 1 5. CRO 30MHz 1 6. Regulated power supply (0-30)V 1 7. Connecting wires & 1 Breadboard Formula: Maximum power output =Po=Vo2/RL Efficiency, = Pac/Pdc Pac=Vm2/2RL Vm=Vpp/2 Pdc=VccxIcQ IcQ= x IBQ IBQ = Vcc-VBE RB

Theory: The Class A amplifier is the most common and simplest form of power amplifier that uses the switching transistor in the standard common emitter circuit configuration. The transistor is always biased "ON" so that it conducts during one complete cycle of the input signal wave form producing minimum distortion and maximum amplitude to the output. This means that the Class A Amplifier configuration is the ideal operating mode, because there can be no crossover or switch-off distortion to the output waveform even during the negative half of the cycle. Class A power amplifier output stages may use a single power transistor or pairs of transistors connected together to share the high load current. Then the transistor switches "ON" it sinks the output current through the Collector resulting in an inevitable voltage drop across the Emitter resistance thereby limiting the negative output capability. The efficiency of this type of circuit is very low (less than 30%) and delivers small power outputs for a large drain on the DC power supply. A Class A amplifier stage passes the same load current even when no input signal is applied so large heat sinks are needed for the output transistors.

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Bias design: Since voltage amplification is done in the transistor amplifier circuit, We as equal drops across VCE & load resistance RE. The quiescent current of 1mA is assumed, we assume a standard supply of 12V. Drop across RE is assumed to be 1V,the drop across VCE with a supply of 12V is given by 12-1V=11V It is equal to 11/2=5.5V Now the voltage across the resistance RE is 5.5V VCE = 5.5V VC = 5.5V IC = 1mA RC = 5.5V/1mA = 5.5K Instead of using 5.5K , We can use a standard value of 4.7K. It is assumed that RBB / (dc+1) = RE / 10 Hence RBB / (dc+1) is neglected when compared RE. Hence VBB = IERE+VBE Hence VBE is neglected when compared to IERE Hence IE = VBB / RE. DESIGN OF R1 & R2: Voltage drop across RE = VRE = 1V Drop across VBE = 0.7V Drop across the resistance R2 = VBE +VRE = VR2 VR2=1.7V ; R2 is assumed to be 10K VCCR2 / (R1 + R2 ) = VR2 10*12K/(R1+10K)=1.7V R1=61K Procedure: 1. Connect the circuit as per the circuit diagram. 2. Set VS=10mV using AFO. 3. Keeping the input voltage constant, vary the frequency from few 100Hz to 1MHz in regular steps & note down the correspondingly output voltage. 4. Plot the graph: gain Vs frequency. 5. Calculate bandwidth from the graph. Result: The class-A amplifier is designed, constructed and the output waveform is observed. The Maximum power output and the efficiency are determined.

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MODEL GRAPH:

TABULAR COLUMN: Amplitude INPUT OUTPUT Time period Distortion

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Ex. no: Date: CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER Aim: To construct a Class B complementary symmetry power amplifier and observe the waveforms with and without cross-over distortion and to compute maximum output power and efficiency. Apparatus required: S.No. 1. 2. 3. 4. 5. 6. 7. 8. Formula: Maximum power output = (Pac)max=Vcc2/2RL Efficiency, = Pac/Pdc Pac=Vm2/2RL Pdc=2Vcc x Im Im = Vm/RL = Vcc/RL THEORY: A power amplifier is said to be Class B amplifier if the Q-point and the input signal are selected such that the output signal is obtained only for one half cycle for a full input cycle. The Q-point is selected on the X-axis. Hence, the transistor remains in the active region only for the positive half of the input signal. There are two types of Class B power amplifiers: Push Pull amplifier and complementary symmetry amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p transistor is used. The matched pair of transistor are used in the common collector configuration. In the positive half cycle of the input signal, the n-p-n transistor is driven into active region and starts conducting and in negative half cycle, the p-n-p transistor is driven into conduction. However there is a period between the crossing of the half cycles of the input signals, for which none of the transistor is active and output, is zero It is a type of push-pull CLASS-B amplifier, which employs one PNP, and one NPN transistor and requires no transformers. This type of amplifier use complementary symmetry. When the signal voltage is positive NPN transistor will conduct, while PNP transistor is cut off.' When the signal voltage is negative T2 conducts and T1 is cut off. Load Current IL= Ic1 - Ic2 Advantage of this amplifier is transformer less operation, saves on weight and cost and balanced Push- pull input signals are not required. Disadvantages are the needs of both positive and negative of supply voltages. Name Transistor Resistor Capacitor Diode Signal Generator CRO Regulated power supply Bread Board Range CL100, BC558 4.7k,15k 47K,1K 100F IN4007 (0-3)MHz 30MHz (0-30)V Quantity 1,1 2,1 2 2 1 1 1 1

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PROCEDURE: 1. Connections are given as per the circuit diagram without diodes. 2. Observe the waveforms and note the amplitude and time period of the input signal and distorted waveforms. 3. Connections are made with diodes. 4. Observe the waveforms and note the amplitude and time period of the input signal and output signal. 5. Draw the waveforms and calculate the maximum output power and efficiency. RESULT: Thus the Class B complementary symmetry power amplifier was constructed to observe cross-over distortion and the circuit was modified to avoid the distortion. The following parameters were calculated: a)Maximum output power= b)Efficiency=

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Circuit diagram of half wave rectifier with capacitor filter:

Model graph: Load Regulation: Vout RL ()

C1 100u

R2 230

T1 BC107

D 1 1N4007

R3 1k

R1 1k

N2 N1 N3

D 2 1N4007

Z1 1N2804

TR 1

VM 1

Without filter Input signal Amplitude(V)

Time period

With filter Output signal Amplitude(V)

Tabular column: Time period

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Load Regulation: S .no Load resistance () Output voltage (V)

Ex. no: Date: POWER SUPPLY CIRCUIT - HALF WAVE RECTIFIER WITH SIMPLE CAPACITOR FILTER Aim: To measure the DC voltage under load and ripple factor and Compare with calculated values. 27

Plot the Load regulation characteristics using Zener diode. Apparatus required: SI NO 1 2 3 4 5 6 7 Formula Used: Dc voltage under load = Vm/ IRMS = Im/2 , IDC= Im/ , Im=Vm/RL Ripple Factor = [IRMS / IDC ] 2-1 Where Im is the peak current APPARATUS Transformer p-n diode Resistors Capacitor zener diode Transistor DRB RANGE (220/12V) 1N4001 (1K ,220 ) 100F FZ5.1 SL 100 QUANDITY 1 2 1 1 1 1 1

Theory: Power supply consists of the transformer to obtain required voltage load. Rectifier to convert a.c signal to d.c signal. Filter to remove ripples and voltage regulator to regulate load voltage. The transformer step-down the 230v a.c to required load. The simple clipping property of p-n junction is used for this purpose. The output is in pulsating d.c. From filter it removes the ripples and give constant d.c voltage. Half wave rectifier: A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C voltage. In this rectifier during the positive half cycle of the A.C input voltage, the diode is forward biased and conducts for all voltages greater than the offset voltage of the semiconductor material used. The voltage produced across the load resistor has same shape as that of the positive input half cycle of A.C input voltage. During the negative half cycle, the diode is reverse biased and it does not conduct. So there is no current flow or voltage drop across load resistor. The net result is that only the positive half cycle of the input voltage appears at the output.

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Apply A.C input using transformer. 3. Measure the amplitude and time period for the input and output waveforms. 4. Calculate ripple factor. 5. Decade resistance box is connected as load.

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6. The load is varied from minimum value to maximum value. 7. The output voltage is noted at the each variation and draw load regulation.

Result: Thus the half wave rectifier was constructed and its input and output waveforms are drawn. The ripple factor of capacitive filter is calculated as Ripple factor= and load regulation characteristics were obtained.

Circuit diagram of Full wave rectifier with filter:

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C1 100u

R2 230

T1 BC107

D 1 1N4007

R3 1k

R1 1k

N2 N1 N3

D 2 1N4007

Model graph: Load Regulation: Vout RL ()

Tabular column: Without filter Input signal Amplitude(V) With filter Output signal Amplitude(V)

Time period

Z1 1N2804

TR1

VM1

Time period

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Load regulation: S.no Load resistance Out put voltage (V)

Ex. no: Date: POWER SUPPLY CIRCUIT - FULL WAVE RECTIFIER WITH SIMPLE CAPACITOR FILTER Aim: To measure the DC voltage under load and ripple factor and Compare with calculated values. Plot the Load regulation characteristics using Zener diode. Apparatus required: SI NO 1 2 3 4 5 6 7 APPARATUS Transformer p-n diode Resistors Capacitor zener diode Transistor DRB RANGE (220/12V) 1N4001 (1K ,220 ) 100F FZ5.1 SL 100 QUANDITY 1 2 1 1 1 1 1

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Formula Used: Dc voltage under load = 2Vm/ IRMS = Im/2 , IDC=2 Im/ , Im=Vm/RL Ripple Factor = [IRMS / IDC ] 2-1 Where Im is the peak current Ripple Factor = [(Im/2) / (2*Im /)] 2-1 Where Im is the peak current Theory: The full wave rectifier conducts for both the positive and negative half cycles of the input ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in this circuit. The diodes feed a common load RL with the help of a centre tapped transformer. The ac voltage is applied through a suitable power transformer with proper turns ratio. The rectifiers dc output is obtained across the load. The dc load current for the full wave rectifier is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less compared to the half wave rectifier. Procedure: Connections are given as per the circuit diagram wiyhout filter. Note the amplitude and time period of the input signal at the secondary winding of the transformer and rectified output. Repeat the same steps with the filter and measure Vdc. Calculate the ripple factor. Decade resistance box is connected as load. The load is varied from minimum value to maximum value. The output voltage is noted at the each variation and draw load regulation.

Result: Thus the full wave rectifier was constructed and its input and output waveforms are drawn. The ripple factor of capacitive filter is calculated as Ripple factor= and load regulation characteristics were obtained.

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