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J K FLIP FLOP
entity jkff is port ( j,k,cp,reset: in bit; q: out bit); end entity; architecture jkff_arch of jkff is signal fout:bit; begin q <= fout; process(cp) begin if(reset ='1') then fout <= '0'; elsif(cp='1') then if(j='1' and k='1') then fout <= not fout; elsif(j='1' and k='0') then fout <= '1'; elsif(j='0' and k='1') then fout <= '0'; else fout <=fout; end if; end if; end process; end jkff_arch; JK FLIP FLOP TEST BENCH entity jkff_test is end jkff_test; architecture jkff_test_arch of jkff_test is component jkff is port ( j,k,cp: in bit; q: out bit); end component; signal j,k,clk,sig: bit; begin inst: jkff port map(j,k,clk,sig); process

744/IT/07 begin j <= '1'; wait for 80 ns; k <= '0'; wait for 20 ns; end process; process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; end jkff_test_arch;

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OUTPUT

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entity dff is port(d,clk,reset: in bit; q: out bit); end entity;

D FLIP FLOP

architecture dff_arch of dff is begin process(clk,reset) begin if(reset='1') then q <='0'; elsif (clk='1') then q <= d; end if; end process; end dff_arch; D FLIP FLOP TEST BENCH entity dff_test is end entity; architecture dff_test_arch of dff_test is component dff is port ( d,clk,reset: in bit; q: out bit); end component; signal d,res,clk,sig: bit; begin inst: dff port map(d,clk,res,sig); process begin d <= '1'; wait for 50 ns; d <= '0'; wait for 50 ns; end process; process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; end dff_test_arch;

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OUTPUT

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entity halfadd is port (a,b : in bit; c,s :out bit); end halfadd; architecture half_add of halfadd is begin c<= a and b; s<= (a and (not b)) or (b and (not a)); end half_add; Half Adder Test Bench entity testbench3 is end testbench3; architecture testhalf of testbench3 is component halfadd port(a,b:in bit;c,s:out bit); end component; signal p,q,r,s:bit; begin inst2 :halfadd port map(p,q,r,s); process begin p<= '0'; q<= '0'; wait for 20 ns; p<= '1'; q<= '0'; wait for 20 ns; p<= '0'; q<= '1'; wait for 20 ns; p<= '1'; q<= '1'; wait for 20 ns; end process; end testhalf

HALF ADDER

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OUTPUT

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entity fulladd is port (a,b,c : in bit; c1,s :out bit); end fulladd; architecture full_add of fulladd is begin c1<= (a and b) or (b and c) or (a and c); s<= (a and (not b) and (not c)) or (b and (not a) and (not c)) or (c and (not a) and (not b)) or (a and b and c); end full_add; Full Adder Test Bench entity testbench4 is end testbench4; architecture testfull of testbench4 is component fulladd port(a,b,c:in bit;c1,s:out bit); end component; signal p,q,r,c,s:bit; begin inst2 :fulladd port map(p,q,r,c,s); process begin p<= '0'; q<= '0'; r<= '0'; wait for 10 ns; p<= '1'; q<= '0'; r<= '0'; wait for 10 ns; p<= '0'; q<= '1'; r<= '0'; wait for 10 ns; p<= '1'; q<= '1'; r<= '0'; wait for 10 ns; p<= '0'; q<= '0'; r<= '1'; wait for 10 ns;

FULL ADDER

744/IT/07 p<= '1'; q<= '0'; r<= '1'; wait for 10 ns; p<= '0'; q<= '1'; r<= '1'; wait for 10 ns; p<= '1'; q<= '1'; r<= '1'; wait for 10 ns; end process; end testfull;

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OUTPUT

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entity decoder3x8 is port (x,y,z: in bit; fout: out bit_vector(7 downto 0)); end entity;

3X8 DECODER

architecture decoder3x8_arch of decoder3x8 is begin fout(0) <= (not x)and(not y)and(not z); fout(1) <= (not x)and(not y)and z; fout(2) <= (not x)and y and(not z); fout(3) <= (not x)and y and z; fout(4) <= x and(not y)and(not z); fout(5) <= (not y)and x and z; fout(6) <= x and y and(not z); fout(7) <= x and y and z; end architecture; TEST BENCH entity decoder_test is end entity; architecture decoder_test_arch of decoder_test is component decoder3x8 is port (x,y,z: in bit; fout: out bit_vector(7 downto 0)); end component; signal input: bit_vector(2 downto 0); signal output: bit_vector(7 downto 0); begin inst1: decoder3x8 port map(input(2),input(1),input(0),output); process begin input <= "001"; wait for 20 ns; input <= "011" ; wait for 20 ns; input <= "110"; wait for 20 ns; end process; end decoder_test_arch;

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4x1 MUX
entity mux4x1 is port (ip: in bit_vector(3 downto 0); s1,s2: in bit; e: out bit); end entity; architecture mux4x1_arch of mux4x1 is begin e <= ip(0) when s1='0' and s2='0' else ip(1) when s1='0' and s2='1' else ip(2) when s1='1' and s2='0' else ip(3) ; end mux4x1_arch; Test Bench entity test_mux4 is end entity; architecture test_mux4_arch of test_mux4 is component mux4x1 port (ip: in bit_vector(3 downto 0); s1,s2: in bit; e: out bit); end component; signal s1,s2,e: bit; signal ip:bit_vector(3 downto 0); begin inst: mux4x1 port map(ip,s1,s2,e); process begin ip <= "1010"; s1 <= '0'; s2 <= '0'; wait for 10 ns; s1 <= '0'; s2 <= '1'; wait for 10 ns; s1 <= '1'; s2 <= '0';

744/IT/07 wait for 10 ns; s1 <= '1'; s2 <= '1'; wait for 10 ns; end process; end test_mux4_arch;

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OUTPUT