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Subject Code : 06EC71 IA Marks Exam Hours Exam Marks : 25 : 03 : 100
No. of Lecture Hrs/Week : 04 Total no. of Lecture Hrs. : 52
PART - A UNIT - 1 Layered tasks, OSI Model, Layers in OSI model, TCP?IP Suite, Addressing, Telephone and cable networks for data transmission, Telephone networks, Dial up modem, DSL, Cable TV for data transmission. 6 Hours UNIT - 2 DATA LINK CONTROL: Framing, Flow and error control, Protocols, Noiseless channels and noisy channels, HDLC. 7 Hours UNIT - 3 MULTIPLE ACCESSES: Random access, Controlled access, Channelisation. UNIT - 4 Wired LAN, Ethernet, IEEE standards, Standard Ethernet. Changes in the standards, Fast Ethernet, Gigabit Ethernet, Wireless LAN IEEE 802.11 7 Hours 6 Hours
PART - B UNIT - 5 Connecting LANs, Backbone and Virtual LANs, Connecting devices, Back bone Networks, Virtual LANs 6 Hours UNIT - 6 Network Layer, Logical addressing, Ipv4 addresses, Ipv6 addresses, Ipv4 and Ipv6 Transition from Ipv4 to Ipv6. 7 Hours UNIT - 7 Delivery, Forwarding, Unicast Routing Protocols, Multicast Routing protocols 6 Hours
Introduction to Data communication and Networking. advantages. photonic crystal. mode filed diameter. cylindrical fiber (no derivations in article 2. UDP. 2 Edition. Computer nd Networks.4. Domain name system. Ray theory. Optical Fibers: fiber materials.A UNIT . Kurose. Historical development.1 OVERVIEW OF OPTICAL FIBER COMMUNICATION: Introduction.2 . 8 Hours UNIT . Optical Fiber Communication Subject Code : 06EC72 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 No. optical fiber waveguides. 2003 2. of Lecture Hrs. and applications of optical fiber communication. Keith W. James F. single mode fiber. of Lecture Hrs/Week : 04 Total no. B Forouzan. Data Communication and Networking. TMH 2006 REFERENCE BOOKS: 1. disadvantages. Wayne Tomasi: Pearson education 2007 3. Resolution 6 Hours TEXT BOOK: 1.8 Transport layer Process to process Delivery. : 52 PART . fiber optic cables specialty fibers. general system. Ross: Pearson education. TCP. 4th Ed. cutoff wave length.UNIT .4).
Radio over fiber links. Power penalties. link power budget. RF over fiber. LASER diodes. fiber splices. comparison of photo detectors. 8 Hours UNIT . Inter model dispersion. point–to–point links.6 ANALOG AND DIGITAL LINKS: Analog links – Introduction. multichannel transmission techniques. scattering losses. operation.B UNIT . LED’s. resistive budget. dispersion. short wave length band. key link parameters.3 OPTICAL SOURCES AND DETECTORS: Introduction. fiber alignment and joint loss. fiber connectors and fiber couplers. Analog receivers 6 Hours UNIT . Digital links – Introduction. microwave photonics. single mode fiber joints. absorption. Optical Receiver Operation. quantum limit.7 . coherent detection.4 FIBER COUPLERS AND CONNECTORS: Introduction. nodal noise and chirping. eye diagrams. burst mode receiver.5 OPTICAL RECEIVER: Introduction. CNR. transmission distance for single mode fibers. Intra model dispersion. 6 Hours PART .TRANSMISSION CHARACTERISTICS OF OPTICAL FIBERS: Introduction. bending loss. System considerations. Attenuation. receiver sensitivity. Photo diodes. Photo detector noise. Response time. Photo detectors. double hetero junction structure. overview of analog links. 7 Hours UNIT . 5 Hours UNIT .
of Lecture Hrs/Week : 04 Total no. MEMS technology. Mach-Zehender interferometer. High – speed light – waveguides. Types of power electronics circuits. Fiber Optic Communication . "Optical Fiber Communications". tunable optical fibers.8 Optical Amplifiers and Networks – optical amplifiers. SONET / SDH.Joseph C Palais: 4th Edition. SONET/SDH rings.WDM CONCEPTS AND COMPONENTS: WDM concepts. 5 Hours . Senior. "Optical Fiber Communication”. WDM standards.. Pearson Education. REFERENCE BOOK: 1. Pearson Education. Power semiconductor devices. of Lecture Hrs. EDFA. 4th Ed. basic applications and types. semiconductor optical amplifiers. Control characteristics. John M. 6 Hours TEXT BOOKS: 1. Optical Interfaces. OPTICAL NETWORKS: Introduction. dynamic gain equalizers. 6 Hours UNIT . optical drop multiplexers. tunable light sources. Isolators and circulators. Power Electronics Subject Code : 06EC73 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 No. polarization controllers. 3rd Impression. 2007. MGH. 2. Peripheral effects. 2008. : 52 PART . variable optical attenuators. direct thin film filters. Applications of power electronics. active optical components.1 Introduction. Gerd Keiser. chromatic dispersion compensators. multiplexer.A UNIT . overview of WDM operation principles.
self commutation. Single phase controllers with restive loads and Inductive loads. Thyristor firing circuits. numerical problems. Gate drive. 6 Hours UNIT . Switching limits.6 AC VOLTAGE CONTROLLERS: Introduction. 5 Hours PART . auxiliary commutation.2 POWER TRANSISTOR: Power BJT’s.4 CONTROLLED RECTIFIERS: Introduction. 1 φ semi converters (all converters with R & RL load). Dynamic Turn-on and turn-off characteristics.B UNIT . Switching characteristics. Duel converters. IGBT’s. numerical problems. Gate trigger circuits.5 Thyristor turn off methods. Principles of on and off control. Power MOSFET’s. Two transistor model. natural and forced commutation. Isolation of gate and base drives. Principles of phase control. 1φ fully controlled converters. class A and class B types. di / dt and dv / dt protection. Base derive control. Principles of phase controlled converter operation. Complementary commutation. Turn-on Methods. 7 Hours UNIT . 7 Hours UNIT . Switching characteristics.UNIT . 6 Hours UNIT . AC line commutation.3 INTRODUCTION TO THYRISTORS: Principle of operation states anode-cathode characteristics. external pulse commutation.7 . Gate characteristics.
Step down chopper with RL loads.DC CHOPPERS: Introduction. of Lecture Hrs/Week : 04 Total no. Analysis of impulse commutated Thyristor chopper (only qualitative analysis). “Power Electronics” . : 52 PART . “Power Electronics” . 2007. DSP Algorithms and Architecture Subject Code : 06EC74 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 No. Digital Filters. Chopper classification.2 . H. Discrete Time Sequences. REFERENCE BOOKS: 1. TMH publisher.8 INVERTORS: Introduction. PHI / Pearson publisher 2004. A Digital SignalProcessing System. R.A UNIT . “Thyristorized Power Controllers” . Decimation and Interpolation. 5 Hours UNIT . Joshi and Rmk Sinha New age international (P) ltd reprint 1999.B. The Sampling Process. 7 Hours TEXT BOOKS: 1. Linear Time-Invariant Systems. 2. D.M. 2.G.1 INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). Dubey S.Cynil W. “Power Electronics” . Doradla. 8 Hours UNIT . Principles of operation. A. Variable DC link inverter. Performance parameters.M. Singh and Kanchandani K. MGH 2003. 1φ bridge inverter. nd 2 Ed. Lander 3rd edition. Rashid 3rd edition. Principles of step down and step up choppers. voltage control of 1φ invertors. K. of Lecture Hrs. current source invertors.
6 Hours PART . Address Generation Unit. Data Addressing Capabilities. Bus Architecture and Memory. Bit-Reversed Index Generation & Implementation on the TMS32OC54xx.ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNALPROCESSORS: Introduction. Program Control. IIR Filters. Interpolation and Decimation Filters (one example in each case). Pipeline Operation of TMS32OC54xx Processor.B UNIT . 8 Hours UNIT . FIR Filters. The Q-notation.5 IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction. An FFT Algorithm for DFT Computation. DSP Computational Building Blocks. Parallel I/O Interface. On-Chip peripherals.4 Detail Study of TMS320C54X & 54xx Instructions and Programming.7 INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES: Introduction. Memory Interface. Data Addressing Modes of TMS32OC54xx. Programmed I/O. Overflow and Scaling. 6 Hours UNIT . 6 Hours UNIT . External Bus Interfacing Signals.3 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction. Basic Architectural Features.8 . Interrupts and I / O Direct Memory Access (DMA). Interrupts of TMS32OC54XX Processors. Commercial Digital Signal-processing Devices. Memory Space of TMS32OC54xx Processors. Memory Space Organization. Programmability and Program Execution.6 IMPLEMENTATION OF FFT ALGORITHMS: Introduction.. 6 Hours UNIT . Features for External Interfacing. 8 Hours UNIT .
Relationships between Pixels. of Lecture Hrs. fundamental Steps in Digital Image Processing. Ifeachor E. Thomson Learning. 6 Hours UNIT . “Digital Signal Processing”. DSP Based Bio-telemetry Receiver. W Pearson-Education.2 Image Sensing and Acquisition.1 DIGITAL IMAGE FUNDAMENTALS: What is Digital Image Processing. 2004. A Speech Processing System. Avatar Singh and S. of Lecture Hrs/Week : 04 Total no. Image Sampling and Quantization. Jervis B. : 52 PART . elements of Visual Perception.. C. Components of an Image processing system. Digital Signal Processing: A practical approach. An Image Processing System.A UNIT . REFERENCE BOOKS: 1. Some Basic . A CODEC Interface Circuit. Peter Pirsch John Weily. Srinivasan. PHI/ 2002 2. “Digital Signal Processors”. 2007 IMAGE PROCESSING Subject Code : 06EC756 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 No. Linear and Nonlinear Operations. B Venkataramani and M Bhaskar TMH.INTERFACING AND APPLICATIONS OF DSP PROCESSOR: Introduction. “Architectures for Digital Signal Processing”. Synchronous Serial Interface. 2002 3. 6 Hours TEXT BOOK: 1.
Enhancement Using Arithmetic/Logic Operations. Linear Position-Invariant Degradations. Sharpening Frequency Domain filters. Histogram Processing. Smoothing Frequency Domain filters.6 Basics of Spatial Filtering Image enhancement in the Frequency Domain filters.3 IMAGE TRANSFORMS: Two-dimensional orthogonal & unitary transforms. 6 Hours UNIT . KL transform. Restoration in the Presence of Noise.5 IMAGE ENHANCEMENT: Image Enhancement in Spatial domain. Hadamard transform. minimum mean square error (Weiner) Filtering 10 Hours . sine transform. homomorphic filtering. Some Basic Gray Level Trans -formations. inverse filtering. 6 Hours UNIT . 6 Hours PART . Only-Spatial Filtering Periodic Noise Reduction by Frequency Domain Filtering.4 Discrete cosine transform. Slant transform. properties of unitary transforms. noise models.7 Model of image degradation/restoration process.B UNIT . 6 Hours UNIT . two dimensional discrete Fourier transform. Haar transform.6 Hours UNIT .
Pearson Education. 2003. 2nd edition. Chanda and D. of Lecture Hrs/Week : 04 Total no. 2001. Color Models. Rafael C. Time constraints.A UNIT .UNIT . Woods. Jain. RTS Definition.1 INTRODUCTION TO REAL-TIME SYSTEMS: Historical background. processing basics of full color image processing 6 Hours TEXT BOOK: 1. “Digital Image Processing Majumdar. Pearson Edun. and Analysis”.8 Color Fundamentals.Gonzalez and Richard E. 2. “Digital Image Processing”. : 52 PART . “Fundamentals of Digital Image Processing”.2 . 2001. of Lecture Hrs.. Classification of Programs. Pseudo color Image Processing. Anil K. 6 Hours UNIT . Classification of Real-time Systems. PHI. REFERENCE BOOKS: 1. B. Dutta REAL-TIME SYSTEMS Subject Code : 06EC762 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 No.
Mutual exclusion.B UNIT . Communications. Loop control. Priority Structures. Concurrency. Real-time multi-tasking OS. Exception Handling. Syntax layout and readability. 6 Hours UNIT . Humancomputer interface. Minimum OS kernel. Overview of real-time languages. Data transfer techniques. Scheduler and real-time clock interrupt handles.3 COMPUTER HARDWARE REQUIREMENTS FOR RTS: Introduction.7 .5 & 6 OPERATING SYSTEMS: Introduction. Co routines. Data transfer. Code sharing. 8 Hours PART . Declaration and Initialization of Variables and Constants. Compilation. Specialized processors. Task cooperation and communication. Modularity and Variables.4 LANGUAGES FOR REAL-TIME APPLICATIONS: Introduction. Scheduling strategies. General purpose computer. Interrupts and Device handling. Task management. 12 Hours UNIT . Single chip microcontroller. Distributed system. Standard Interface. Memory Management. Centralised computer control. Benefits of computer control systems. Liveness.CONCEPTS OF COMPUTER CONTROL: Introduction. Sequence Control. Data types. Examples. 6 Hours UNIT . Real-time support. Control Structure. Process-related Interfaces. Low-level facilities. Resource control. Supervisory control.
8 RTS DEVELOPMENT METHODOLOGIES: Introduction. Laplante. second edition. Pearson Education. Ward and Mellor Method. Single-program approach. Stuart Bennet. Raj Kamal.DESIGN OF RTSS – GENERAL INTRODUCTION: Introduction. Requirement definition for Drying Oven. Specification documentation. Rob Williams. Monitors. Preliminary design. Phillip. 2005. REFERENCE BOOKS: 1. Elsevier. Yourdon Methodology. 6 Hours TEXT BOOKS: 1. 2006. 8 Hours UNIT . Multi-tasking approach. Real . India. Hately and Pirbhai Method. A. 2nd Edn. 2005.Time Computer Control. Embedded Systems. of Practical Hrs/Week : 03 . VLSI Lab Subject Code : 06ECL77 IA Marks Exam Hours : 25 : 03 No. 2005. 3. Mutual exclusion. PHI. Real-Time Systems Development. Tata Mc Graw Hill. Foreground/background. 2. Real-Time Systems Design and Analysis.An Introduction.
Design an Inverter with given specifications*. iii. vii. Do the initial timing verification w simulation. D. viii. completing the design flow mentioned below: a. i.Total no. vi. Draw the Layout and verify the DRC. ERC c. ii. v. Check for LVS d. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Write Verilog Code for the following circuits and their Test Bench for verification.B ANALOG DESIGN Analog Design Flow 1. observe th and synthesisethe code with technological library with given Constraints*. iv. Draw the schematic and verify the following . Design the following circuits with given specifications*. Power and Area to the given constraint*** 2. MS.A : 50 DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW 1. Verify & Optimize for Time. completing the design flow mentioned below: a. Extract RC and back annotate the same and verify the Design e. An inverter A Buffer Transmission Gate Basic/universal gates Flip flop -RS. JK. of Practical Hrs. T Serial & Parallel adder 4-bit counter [Synchronous and Asynchronous counter] Successive approximation register [SAR] * An appropriate constraint should be given PART . : 42 Exam Marks PART .
a. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned usi amp in the library**. AC Analysis iii) Transient Analysis b. 5. Check for LVS d. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Check for LVS d. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier 3. ERC c.i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Extract RC and back annotate the same and verify the Design. ERC c. Draw the schematic and verify the following i) DC Analysis ii). Extract RC and back annotate the same and verify the Design. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the fun . Draw the Layout and verify the DRC. Extract RC and back annotate the same and verify the Design. 4. Draw the Layout and verify the DRC. Draw the Layout and verify the DRC. Design an op-amp with given specification* using given differential amplifier Common source and Co amplifier in library** and completing the design flow mentioned below: a. ERC c. Check for LVS d.
UJT firing circuit for HWR and FWR circuits. ** Applicable Library should be added & information should be given to the Designer. AC voltage controller using triac – diac combination. SCR turn off using i) LC circuit ii) Auxiliary Commutation 5. 3. 7. of Practical Hrs. : 42 1. [Specifications to GDS-II] * Appropriate specification should be given. Single phase Fully Controlled Bridge Converter with R and R-L loads. 8.completing ASIC Design FLOW. 2. Static characteristics of SCR and DIAC. . Controlled HWR and FWR using RC triggering circuit 4. Generation of firing signals for thyristors/ trials using digital circuits / microprocessor. of Practical Hrs/Week: 03 Total no. *** An appropriate constraint should be given Power Electronics Lab Subject Code : 06ECL78 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 No. Static characteristics of MOSFET and IGBT. 6.
11. 10. 13. Speed control of stepper motor. Speed control of universal motor.9. Note: Experiments to be conducted with isolation transformer and low voltage . 12. Speed control of a separately exited DC motor. Voltage (Impulse) commutated chopper both constant frequency and variable frequency operations. Parallel / series inverter.
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