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A Sub 1 V Bandgap Reference Circuit

by
Ashish A Digvadekar
A Thesis submitted in Partial Fulfillment of the
Requirements for the Degree of
MASTERS OF SCIENCE
In
Electrical Engineering

Approved by: Professor _____________________________
(Dr. James E. Moon – Advisor)

Professor _____________________________
(Dr. P R Mukund – Committee Member)

Professor _____________________________
(Dr. Syed S. Islam – Committee Member)

Professor _____________________________
(Dr. Robert J. Bowman – Department Head)


DEPARTMENT OF ELECTRICAL ENGINEERING
COLLEGE OF ENGINEERING
ROCHSTER INSTITUTE OF TECHNOLOGY
ROCHESTER, NEW YORK
MAY 2005
THESIS RELEASE PERMISSION
DEPARTMENT OF ELECTRICAL ENGINEERING
COLLEGE OF ENGINEERING
ROCHESTER INSTITUTE OF TECHNOLOGY
ROCHESTER, NEW YORK


Title of Thesis:
A Sub 1 V Bandgap Reference Circuit











I, Ashish Digvadekar, hereby grant permission to Wallace Memorial Library of the Rochester
Institute of Technology to reproduce my thesis in whole or in part. Any reproduction will not
be for commercial use or profit.


Signature _______________________________________________________________

Date
i
ACKNOWLEDGEMENT


A journey is easier when you travel together. Interdependence is certainly more valuable than
independence. I have worked on this thesis for more than a year. I owe the completion of this
thesis to a countless number of people. It is impossible to mention all the names here but I
would definitely take this opportunity to thank the following people who have guided,
encouraged, motivated and helped me through the different phases of the thesis.

First I would like to thank Dr. Moon for his valuable guidance throughout. He was always
there to answer each of my doubts, from the trivial ones to the more genuine ones. The
fruitful discussions with him were something I always looked forward to. He has also been of
great help to me in matters not concerning the thesis. I have worked with him for two and a
half years now and he inspired me both as a human being and as an advisor.

This thesis would not have initiated without Dr. Mukund. He led me into the thesis topic and
to Dr. Moon as thesis advisor. I would also like to mention the names of Mr. Clyde
Washburn and Tejasvi Das for their valuable time to set things up for me. I would like to
thank Dr. Islam and Dr. Mukund for taking time out of their busy schedule and going through
my thesis, providing their valuable insights. I will also thank the LSI Logic team for allowing
me to use their models and their inputs.




ii
I would especially like to thank my boss and senior colleagues of the Temperature Sensor
group at East Coast Labs of National Semiconductors for the knowledge they shared with
me. Thank you Mr. Eric Blom and Mr. Gary Sheehan for introducing to me the concept of
digital trimming. Thank you Jun, Stuart, Peter, and Matt for answering my endless questions.

My friends were of great help right through the thesis. First to mention is Ashish Vora who
always made valuable suggestions which have affected the outcome of the thesis. I will thank
Aakash, Vivek, Ajish and the rest for the constructive criticism.

I can never forget the efforts and sacrifices of my family. My dad for teaching me the basics
of life and the financial support, my Mom for her continuous prayers and good wishes, my
brother for shaking me up when he saw me discouraged and Palak for keeping me motivated
towards my thesis. Above all I would like to thank God. I know he is always there for me and
helps me out of all difficult situations I get myself into.





iii
ABSTRACT

This thesis proposes a novel technique for a low supply voltage temperature-independent
reference voltage. With the scaling of supply voltages, the threshold voltages don’t scale
proportionally and thus low supply reference circuits have replaced the conventional bandgap
reference circuit. The first chapter of this work discusses the conventional bandgap
references (The Widlar and Brokaw references). The terminology used in the bandgap world
is introduced here. The second chapter investigates the existing low supply voltage reference
circuits with their advantages and the limitations. A table discussing all the investigated
circuits is provided towards the end of the chapter as a summary.

Chapter Three proposes a novel technique to generate a temperature-independent voltage
which does not use an operational amplifier. This chapter also provides a mathematical
understanding for behavior of the circuit. Chapter Four talks about two variations of the
proposed architecture. These variations are designed in order to improve the performance of
the proposed circuit against power supply variations. Each one of them has its own merits
and drawbacks. Finally Chapter Five discusses the effects of process variations and transient
response of the proposed circuit. A digital trimming scheme using an EE-PROM is proposed
to manage almost all of the process variation effects on the circuit.
iv
TABLE OF CONTENTS

Acknowledgement……………………………………………………........ i
Abstract……………………………………………………………………. iii
Table of Contents…………………………………………………………. iv
List of Figures…………………………………………………………….. vi
List of Tables……………………………………………………………… viii


Introduction ____ __ Chapter # 1
1 Introduction…………………………………………………………………........ 1
1.1.1 Zener Based Voltage Reference………………………………………………… 2
1.1.2 Bandgap Voltage Reference……………………………………………………. 4
1.1 Bandgap terminology…………………………………………………………… 6
1.2 Classical Bandgap Circuits – Widlar and Brokaw……………………………. 8
1.3.1 Widlar Bandgap reference……………………………………………………… 8
1.3.2 Brokaw Bandgap reference…………………………………………………….. 10
1.4 Bandgap reference principle…………………………………………………… 12


Background of Low Supply Voltage Bandgap Reference __ Chapter # 2
2.1 Background of Low Supply Voltage Bandgap Reference………………………. 14
2.2 Resistor Divider Network…………………………………………………………. 16
2.3 Current Summing and a voltage summing Circuit….………………………….. 19
2.4 Transimpedance Amplifier……………………………………………………….. 22
2.5 Dynamic Threshold MOS (DTMOS)……………………………………………... 24
2.6 Depletion transistors………………………………………………………………. 26
2.7 Threshold Voltage based circuit………………………………………………….. 28
2.8 Bandgap using two Vbe sources………………………………………………….. 29
2.8 Low Voltage BGR Comparison …………..……………………………………… 32



v
Proposed Low Supply Bandgap Reference Circuit __ Chapter # 3
3.1 Proposed Low supply Bandgap Reference circuit……………………………... 34
3.2 Operation…………………………………………………………………………. 37
3.2.1 PTAT Current Generation……………………………………………………… 37
3.2.2 CTAT Current Generation……………………………………………………… 41
3.3 CTAT Voltage Generation at the base of current mirror transistors………... 46
3.4 Bandgap output Voltage………………………………………………………… 49

Versions of the Bandgap Reference __ Chapter # 4
4.1 Versions of the Bandgap Reference…………………………………………..... 50
4.2 Circuit Variation # 1…………………………………………………………..... 53
4.3 Circuit Variation # 2……………………………………………………………. 58
4.4 Comparison Chart………………………………………………………………. 61

Process Variations and Transient Response __ Chapter # 5
5.1 Process Variations and Transient Response………………………………….... 62
5.1.1 Process Variations………………………………………………………………… 62
5.1.2 Transient Analysis………………………………………………………………... 66

Conclusions and Future Work……………………………………………..
68
References…………………………………………………………………...
70





vi
LIST OF FIGURES

1.1 Buried Zener reference circuit…………………………………………………….. 2
1.2 Basic Bandgap Circuit…………………………………………………………….. 4
1.3 Widlar bandgap reference…………………………………………………………. 8
1.4 Brokaw bandgap reference………………………………………………………... 10
1.5 a) Vertical NPN transistor b) Vertical PNP transistor…………………………….. 12
1.6 Conventional BGR circuit…………………………………………………………. 13
2.1 BGR using resistor divider network……………………………………………… 16
2.2 Measured V
REF
characteristics of the proposed BGR…………………………….. 17
2.3 Low voltage BGR as presented by [6]……………………………………………. 18
2.4 Generated reference voltage vs temperature………………………………………. 18
2.5 Current Summing BGR……………………………………………………………. 19
2.6 Temperature variation of the BGR in the current summing circuit………………. 20
2.7 Voltage Summing BGR…………………………………………………………… 21
2.8 a) VREF vs. Vdd b) VREF vs. Temperature……………………………………… 21
2.9 Transimpedance Amplifier using BGR……………………………………………. 22
2.10 Measured VREF characteristics without trimming………………………………... 23
2.11 DTMOS cross-section…………………………………………………………….. 24
2.12 Low voltage DTMOS BGR……………………………………………………….. 25
2.13 VREF vs temperature……………………………………………………………... 25
2.14 Opamp using transistors in depletion mode……………………………………….. 26
2.15 Simulated output voltages at 27ºC at different supply voltages…………………... 27
2.16 Measured VREF vs supply voltage for various temperatures……………………. 27
2.17 Threshold Voltage BGR Concept…………………………………………………. 28
2.18 Simulated BGR Output……………………………………………………………. 28
2.19 Zero TC point……………………………………………………………………… 29
2.20 Low voltage bandgap using two Vbe sources…………………………………….. 30
2.21 Zero TC with two Vbe sources……………………………………………………. 30
2.22 Combining Vbe resistors…………………………………………………………... 31
3.1 Proposed bandgap reference in the simplest form………………………………… 35
3.2 Circuit for PTAT current generation………………………………………………. 37
3.3 PTAT current……………………………………………………………………… 39
3.4 PTAT voltage drop across the output resistor…………………………………….. 40
3.5 Variation of PN junction voltage with temperature……………………………….. 41
3.6 Circuit generating CTAT quantity………………………………………………… 42
vii
3.7 Current through the resistor network……………………………………………… 44
3.8 Voltage drop across output resistor due to the CTAT generation circuit…………. 45
3.9 Biasing Circuit…………………………………………………………………….. 46
3.10 Output from the biasing circuit……………………………………………………. 48
3.11 Bandgap output for a particular combination of resistors…………………………. 49
4.1 Voltage supply variation of the basic BGR circuit………………………………... 51
4.2 Circuit Variation # 1………………………………………………………………. 54
4.3 Threshold voltage self biasing…………………………………………………….. 54
4.4 Supply voltage for the PTAT generating part of the circuit………………………. 56
4.5 Variation of output voltage with 100 mV supply voltage variation………………. 56
4.6 Performance over temperature…………………………………………………….. 57
4.7 Circuit Variation # 2……………………...……………………………………….. 58
4.8 PSRR of Circuit Variation # 2…………………………………………………….. 59
4.9 Bandgap output voltage…………………………………………………………… 60
5.1 The resistor and transistor trim configuration for the original circuit……………. 64
5.2 Transient response of the original circuit………………………………………….. 66
5.3 Transient response for Circuit Variation # 1………………………………………. 67
5.4 Transient response for Circuit Variation # 2………………………………………. 67






viii
LIST OF TABLES

1 Comparison of low voltage bandgap references………….,………………………….. 32
2 Component parameters of the proposed circuit……………………………………….. 36
3 Comparison between the three variations……………………………………………... 61

1







¡nLroducLIon

1.1 Introduction
1.1.1 Zener Based Voltage Reference
1.1.2 Bandgap Voltage Reference
1.2 Bandgap terminology
1.3 Classical Bandgap Circuits – Widlar and Brokaw
1.3.1 Widlar Bandgap reference
1.3.2 Brokaw Bandgap reference
1.4 Bandgap reference principle
_________________________________


1.1 - INTRODUCTION

Voltage reference circuits are precision references which exhibit little dependence on supply
voltage variations and process parameters and a well defined dependence on temperature.
These references are very important for the accurate working of various circuits like data
converters, PLL’s, dynamic random access memories (DRAM’s) and oscillators. The
resolution of an A/D or D/A converter is limited by the precision of its reference voltage over
the circuit’s supply voltage and operating temperature ranges. Thus the precision voltage
reference forms an integral part of almost all circuit designs.

2
Some of the desired characteristics of a voltage reference are:-
a) Ability to be implemented in silicon.
b) Accuracy and stability over supply voltage & time.
c) Proper startup value.
d) Accurate over a wide range of temperature.

The two most popular voltage references are:-
a) Zener-based Voltage reference
b) Bandgap Voltage reference

1.1.1 Zener-based voltage reference
The simplest and the conventional form of a voltage reference is the Zener-based voltage
reference. Here the Zener diode operates in the reverse bias region and current begins to flow
in it at a specific voltage (around 6 V) and thereafter the current increases rapidly with the
increase in voltage. Thus, to use it as a reference a constant current is required. This is
provided through a resistor from a higher supply voltage.

Figure 1.1 – Buried Zener reference circuit
3
Figure 1.1 [12] shows a buried Zener voltage reference where the diode is biased by a current
source. The resistors R1 and R2 form a resistor divider network across the Zener diode. The
divided voltage is applied to the non-inverting terminal of an operational amplifier whose
output is the reference voltage. The gain of the amplifier is decided by the resistor values R4
and R3. The expression for the output is

( ) V
R
R
R R
R
Vout × +
+
=
3
4
1
2 1
2
(1.1)

They are called buried diodes as they are fabricated beneath the surface of the chip. The ones
fabricated on the surface are noisier as they can get contaminated easily. The buried diode
references are more expensive than the bandgap references but are more accurate. Buried
Zener diodes can be made with a range of voltages and have good low noise performance
(better than bandgap references), but the ones that, in combination with their temperature
compensating diodes, have a breakdown voltage just below 7 V, have the best temperature
performance.

But their biggest limitation is the minimum supply voltage required. They need a supply
voltage of at least 6 V. In today’s technology the supply voltages are always shrinking and 6
V is just not the norm. Thus these types of references are no longer used.
4
1.1.2 Bandgap Voltage Reference
A Bandgap reference circuit is one where two quantities with opposite temperature
coefficients are added with a proper weighing factor to result in a temperature coefficient of
approximately zero. This can be explained as two quantities B
1
and B
2
having opposite
temperature coefficients and choosing the coefficients c
1
and c
2
in such a way that

0
2
2
1
1
=


+


T
B
c
T
B
c (1.2)

Thus the reference voltage V
out
= c
1
V
1
+c
2
V
2
has a zero temperature coefficient.


Figure 1.2 – Basic Bandgap Circuit


5

Figure 1.2 shows a bandgap circuit in its very basic form. Here the V
be
, which has a negative
temperature coefficient is complementary to absolute temperature and the delta V
be
is
proportional to absolute temperature and a weighted addition of both results in the V
ref
with a
near zero temperature coefficient. All the terminology is discussed in the next section.
6
1.2 - BANDGAP TERMINOLOGY

a) Bandgap Voltage
Bandgap voltage of a semiconductor measured in eV refers to the potential energy difference
between the valence band and the conduction band for that semiconductor. It has a nearly
constant value and its variation with temperature is small. Each type of a semiconductor has a
unique bandgap. Typically for silicon its value is approximately 1.17 eV.

b) PTAT Voltage
PTAT stands for proportional to absolute temperature which means that the quantity varies
proportionally with absolute temperature - i.e., the quantity increases with absolute
temperature. Most of the bandgap reference circuits use the difference in the V
be
’s of two
transistors operating under same current densities as the PTAT voltage.

c) CTAT Voltage
CTAT stands for complementary to absolute temperature which means that the quantity
varies complementary to absolute temperature - i.e., the voltage decreases with absolute
temperature. Most of the bandgap reference circuits because of its linearity use the V
be
of a
transistor as the CTAT voltage.




7
d) Bandgap Reference circuit (BGR)
A bandgap reference circuit is one which does a weighted addition on the PTAT voltage with
the CTAT voltage to have an end result having a near-zero temperature coefficient. This
resulting voltage is equal to the bandgap voltage of the semiconductor at the reference
temperature.

e) Parts per million (PPM)
Reference-accuracy unit used commonly with precision voltage reference designs.
Designers typically use this measure to specify temperature coefficients and other parameters
that change little under varying conditions. For a 2.5 V reference, 1 ppm is one-millionth of
2.5 V, or 2.5 µV. If the reference is accurate to within 10 ppm, then it is extremely good
performance for any voltage reference.

f) Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ability of the circuit to maintain its output voltage as its power-supply
voltage is varied. The PSRR for a Bandgap reference circuit can be calculated by the
equation

|
|
.
|

\
|


=


OUTPUT BANDGAP
SUPPLY POWER
V
V
PSRR log 20 in dB (1.3)

8
1.3 - CLASSICAL BANDGAP CIRCUITS – WIDLAR AND BROKAW

1.3.1 Widlar Bandgap reference
The first bandgap reference was proposed by Robert Widlar in 1971 [2] as shown in Figure
1.3 below. It used conventional junction isolated bipolar technology to make a stable low
voltage (1.220 V) reference. Early MOS implementations of these voltage references were
based on the difference between the threshold voltages of enhancement and depletion mode
MOS transistors [3]. This provides low temperature coefficient (TC); however, the
drawbacks are that the output is not easy to control because of the direct dependence on the
doses of ion implantation steps and, further depletion mode transistors are not available in
most CMOS processes.


Figure 1.3 – Widlar bandgap reference[2]

9
The Widlar circuit shown above operates as explained with equations below:

3 2 4 3
R I V V
BE BE
+ = (1.4)

3 2 3 2 4 3
R I V R I V V
BE BE BE
= ∆ ¬ = − ∴ (1.5)
But,

|
|
.
|

\
|
=
|
|
.
|

\
|

|
|
.
|

\
|
= ∆
1 2
2 1
2
2
1
1
ln ln ln
S
S
Thermal
S
Thermal
S
hermalT BE
I I
I I
V
I
I
V
I
I
V V (1.6)

Assuming that V
be3
= V
be2,
this implies I
1
R
1
=I
2
R
2

|
|
.
|

\
|
=
|
|
.
|

\
|
=

= ∴
1 1
2 2
3 1 2
2 1
3 3
2
ln ln
S
S Thermal
S
S Thermal BE
I R
I R
R
V
I I
I I
R
V
R
V
I (1.7)

2 2
1 1
2 2
3
2
2 2 2
ln
BE Thermal BE
S
S
Thermal BE OUT
V KV V
I R
I R
V
R
R
V R I V + = +
|
|
.
|

\
|
= + = ∴ (1.8)

R1, R2 and R3 can be manipulated to achieve the desired value of K.

Drawbacks of the basic four-transistor circuit include the fact that the reference output
voltage cannot be changed. Also the performance of the circuit depends heavily on the
current density in Q2 which will change if the circuit is loaded.
10
1.3.2 Brokaw Bandgap reference
Paul Brokaw made his bandgap reference [13] by solving many of the problems in the
Widlar reference. Figure 1.4 below shows the Brokaw bandgap reference circuit. The circuit
has two transistors and collector current sensing to form the basic bandgap voltage. The
output voltage can be expressed as

1 1
_ _ R across Voltage V V
BE OUT
+ = (1.9)

|
|
.
|

\
|
|
|
.
|

\
|
+ = ∴
2
1
2
1
1
ln 2
A
A
q
kT
R
R
V V
BE OUT
(1.10)
Here A
1
and A
2
are the areas of Q
1
and Q
2
respectively.



Figure 1.4 – Brokaw Bandgap reference [13]

11

The reason for the voltage across R
1
having a positive temperature coefficient is that the
currents through both the transistors are equal, thus acts like a PTAT. The V
be
acts as a
CTAT. The proper weighted addition of both the quantities leads to a temperature invariant
V
out
which is the bandgap reference output.


12
1.4 - BANDGAP REFERENCE PRINCIPLE

Most of the modern bandgap reference circuits are made on the Paul Brokaw school of
thought. Thus every bandgap reference will result from the weighted addition of a PTAT
voltage with a CTAT voltage. For this they rely on well transistors. These are vertical
bipolar transistors that use wells as their bases and substrate as their collectors. These are
shown in Figure 1.5 below.

Figure 1.5 - a) Vertical NPN transistor b) Vertical PNP transistor


13
A conventional bandgap [4] reference circuit is shown in the Figure 1.6. The output of the
circuit is given by the equation:

( )
3
2 3
2
R
R R
V V V
BE BE OUT
+
∆ + = (1.11)

|
|
.
|

\
|
+ + = ∴
3
2
2
1 ln
R
R
n V V V
t BE OUT
(1.12)
Here n is the ratio of the sizes of the two bipolar junction transistors and V
t
is the thermal
voltage. The first term represents the CTAT voltage and the second term represents the
PTAT voltage.


Figure 1.6 – Conventional BGR circuit [4]

The output voltage for a conventional BGR is 1.26 V. The output here is from an opamp.
Even if we consider a simple two stage opamp, the minimum supply voltage is the output
V
out
plus the V
DSsat
drop across the output stage transistor. This is around 1.4 to 1.5 V
depending upon the technology.
14








Buckground oI ¡ow SuppIy VoILuge BGR`s
2.1 Background of Low Supply Voltage Bandgap Reference
2.2 Resistor Divider Network
2.3 Current Summing and a voltage summing Circuits
2.4 Transimpedance Amplifier
2.5 Dynamic Threshold MOS (DTMOS)
2.6 Depletion transistors
2.7 Threshold Voltage based circuit
2.8 Low Voltage BGR Comparison
_________________________________

2.1 - BACKGROUND OF LOW SUPPLY VOLTAGE BANDGAP
REFERENCES
As the technology scales, so do the supply voltages. The supply voltages recently tend to be
in the range of 0.9 V – 1.2 V. The supply voltage scales with the technology, but the
threshold voltage of the transistors does not scale at the same rate. This makes it difficult to
incorporate conventional designs of bandgap reference circuits to processes having supply
voltage near 1 V. Here arises the need to come up with new topologies of bandgap reference
to operate properly in the low supply voltages. For the low voltage bandgap reference design
the following approaches have been used:
15

1) Resistive divider networks
2) Current summing and a voltage summing circuits
3) Transimpedance amplifier
4) Dynamic Threshold MOS (DTMOS)
5) Depletion transistors
6) Threshold voltage based circuit
7) Bandgap using two V
be
sources
16
2.2 RESISTOR DIVIDER NETWORK
The resistive divider network proposed by Banba [5] is shown in the Figure 2.1. The concept
here used was to sum two currents (instead of voltages in the conventional BGR circuits).
The forward bias voltage of the diodes is defined as V
F
. One of the currents is proportional to
V
F
, which is the CTAT here, and the other current in proportional to V
T
. The circuit
configuration is shown in Figure 2.1 below. Here the diodes can be replaced with PNP
transistors available in the today’s processes.



Figure 2.1 – BGR using Resistor divider network [5]

Here,

|
|
.
|

\
|
+ =
3 2
1
4
R
dV
R
V
R V
F F
REF
(2.1)
The value of V
REF
can be adjusted by altering the values of R
4
, R
3
and R
2
.
17

The circuit was designed for a reference voltage of 515 mV. V
REF
showed a variation of 515
mV ± 1 mV for the supply variation of 2.2 to 4 V at 27°C; and 515 mV ± 3 mV for
temperature variation from 27 to 125°C as shown in Figure 2.2 below. However the
minimum supply voltage was limited to 2.1 V.


Figure – 2.2 Measured V
REF
characteristics of the proposed BGR [5]

Several modifications were proposed to the circuit presented in [5]. In one of the
modifications by Waltari [6], the sub-1 V operation is achieved by folding the circuit in
Figure 2.1 at nodes Va and Vb. The problem in this circuit is that the nodes Va and Vb are at
a voltage of 0.7 V and this is not suitable for a low voltage opamp. The voltage at these
nodes is reduced with the help of a resistor divider network as shown below in Figure 2.3.
18

Figure 2.3 – Low Voltage BGR as presented by [6]
The voltage at the nodes Va and Vb is now 150 mV – 200 mV due to the resistive divider
network of R
1a
, R
1b
, R
2a
and R
2b
. The output impedance of the current source is improved by
using cascade configuration. This also helps to maximize the PSRR of the circuit. The
simulation results are shown in Figure 2.4. The TC variation was observed to be less than
0.24%.

Figure 2.4 – Generated reference voltage versus temperature using a 0.95 V (solid curve)
and a 1.5 V (dashed curve supply voltage) [6]

19
2.3 CURRENT SUMMING AND A VOLTAGE SUMMING CIRCUITS
Ripamonti [7] talks about two different configurations capable of sub-1 V supply voltage
BGR circuits. The first technique operates by summing two currents with opposite
temperature dependence on a resistor, and the resistor value further controls the reference
voltage. The second technique sums two voltages that are first attenuated, where resistive
voltage dividers are used for the determination of the attenuation factor. The circuit that sums
two currents is given in Figure 2.5.

Figure 2.5 – Current Summing BGR [7]

The circuit is divided into three sub-blocks. The first generates current PTAT by using the
MOS operating in the sub threshold region. The second block produces current CTAT. The
third block is a resistor where both the currents are added. The major advantage of the circuit
is that the supply voltage here is the addition of the drop across the forward biased diode and
the V
DS
of the transistor, which are 0.7 V and 0.2 V respectively. Thus the supply voltage can
be as low as 0.9 V. A major drawback of the circuit is its extremely low PSRR. Figure 2.6
below shows the temperature dependence of the bandgap output.
20

Figure 2.6 – Temperature Variation of the BGR in the current summing circuit [7]

The voltage summing BGR in Figure 2.7 is also composed of three sub circuits. The only
difference between the current summing BGR and the voltage summing BGR is the third
sub-circuit. The third section is composed of a differential amplifier in a non-inverting
feedback loop. The offset voltage from the use of unmatched bipolar transistors generates the
PTAT component. The applied diode voltage is not the full base-emitter voltage, as in a
standard BGR, but a fraction. The minimum supply voltage of one path is V
T
plus a V
CE
sat,
plus the source to drain voltage of the current source. The second path’s minimum supply
voltage is a V
BE
plus the minimum voltage of the current source plus the output voltage of
the V
BE
generator. This value is equal to 1 V with the technology that was used in this study.

21

Figure 2.7 – Voltage Summing BGR [7]
Variations in reference voltage with supply voltage and temperature are plotted in Figure 2.8.
The output voltage was found to vary by less than 0.5% over the 0.9 V to 2.5 V range. In the
same range the temperature dependence varied by 2%.

Figure 2.8 a) VREF vs. Vdd b) VREF vs. Temperature [7]




22
2.4 TRANSIMPEDANCE AMPLIFIER


The conventional BGR circuit is limited by the input common mode range of the operational
amplifier. Jiang [8] proposes another improvement to the circuit described by Banba [5], as
depicted in Figure 2.9. Here resistors are used in place of input differential stage of the
opamp. They are used to obtain a PTAT current by sensing the voltage difference and the
current is summed with a current complementary to V
EB
to obtain the reference voltage. This
technique is based on the use of a Transimpedance amplifier.



Figure 2.9 – Transimpedance Amplifier using BGR [8]

The value of V
REF
here is given by

(
¸
(

¸

− +
|
|
.
|

\
|
=
2 2 2
1
1
3
ln
1
R
V
R
V
A
A
V
R
R V
B BE
T REF
(2.2)
Here A
1
and A
2
are the areas of transistors Q
1
and Q
2
respectively. The value of Vref can be
changed by choosing different values of R
1
, R
2
, and R
3
. The measured V
REF
is shown in
Figure 2.10.
23

Figure 2.10- Measured VREF characteristics without trimming [8]





24
2.5 DYNAMIC THRESHOLD MOS (DTMOS)
Annema [9] talks about another method of low power, low voltage BGR design through the
use of dynamic threshold MOS (DTMOS) devices. As we have seen, the bandgap for low
power applications can be made to appear smaller through resistive subdivision, but it is at
the expense of area. The bandgap can also be made to appear smaller if the junction is in the
presence of an electrostatic field. The electrostatic field lowers the bandgap. This method can
be implemented by replacing the normal diodes with MOS diodes that have interconnected
gates and back gates. These devices are DTMOS devices; a cross-section is shown in Figure
2.11. The use of a P-DTMOS device results in a V
G0
of 0.6 V and the temperature gradient of
VGS is approximately –1 mV/°K. These values are half the typical values of a standard
BGR.

Figure 2.11 – DTMOS Cross-section [9]

A DTMOS BGR can be designed using the same topology as a standard CMOS BGR. Figure
2.12 demonstrates such a circuit. The circuit consists of a folded cascode opamp and matched
resistors with unequal value. The DTMOS diodes are shown with the gate-substrate
connection. The input stage also utilizes DTMOS transistors, which allows operation at low
25
supply voltages. The opamp’s output stage, shaded, uses a low voltage current mirror.
Correct operation of this opamp was verified for supply voltages down to 0.7 V.


Figure 2.12 – Low Voltage DTMOS BGR [9]
The circuit’s temperature dependence is shown in Figure 2.13. The variation over the range, -
20°C to 100°C, is just 4.5 mV.



Figure 2.13 – VREF v/s temperature [9]
26
2.6 DEPLETION TRANSISTORS
Pierazzi [10] made opamp that used PMOS in the depletion mode in order to cope with the
supply voltage reduction. Thus the circuit cannot be fabricated in regular low cost CMOS
technologies that usually do not have these special devices. This opamp uses PMOS in the
weak inversion and is shown in Figure 2.14. A diode-connected PMOS transistor loads the
second gain stage. Thus, the biasing of the opamp is derived from the output voltage and thus
this maximizes the PSRR of the whole opamp but at the cost of low voltage gain.


Figure 2.14 – OpAmp using transistors in depletion mode [10]
The input transistors work in strong inversion at a supply voltage of around 1.4 V. Below this
voltage the transistors drop into a weak inversion. The bias current is reduced to a few
nanoamps at a supply voltage of 1 V. As seen from Figure 2.15 below the supply voltage of
0.9 V there is no longer enough loop gain to keep the BGR at correct bias point.
27

Figure 2.15 - Simulated output voltages at 27ºC at different supply voltages. BG1 is the curve
of our interest. [10]


The BGR was implemented in 0.35 µm CMOS technology. The measured VREF vs supply
voltage for various temperatures is shown in Figure 2.16. The measurements suggest a
minimum supply voltage of 0.9 V.



Figure 2.16 - Measured VREF vs supply voltage for various temperatures [10]

28
2.7 THRESHOLD VOLTAGE BASED CIRCUIT
Ytterdal [11] introduces the new concept of threshold voltage based voltage references. The
basic idea here is to compensate the temperature dependency of the threshold voltage of a
PMOS transistor with that of an NMOS transistor, both having a CTAT dependency. This
concept is pictorially shown in Figure 2.17. The performance of the proposed BGR is shown
to be comparable to bandgap circuits, but at the cost of more area and complexity.

Figure – 2.17 Threshold Voltage BGR Concept [11]
The simulation results for the circuit made with this technique are shown in Figure 2.18.

Figure 2.18 – Simulated BGR Output [11]
29
2.8 BANDGAP USING TWO VBE SOURCES
The work by Washburn [17] was driven by the motivation of developing a low voltage
bandgap reference circuit having low power consumption, no dependence on TC of resistors,
minimum number of critical components that need to be matched and usage of resistor arrays
that are a multiple of a single resistance value.

The work in [17] exhibits a series of attainable circuit behaviors as discussed below:
a) The ability to multiply PTAT voltage to get it to be almost equal to the CTAT voltage
near the center of the desired operating temperature range.
b) The voltage source like behavior of the multiplied PTAT voltage when dropped across a
resistor having a impedance equal to that of the resistor value.
c) If CTAT and PTAT voltages are connected as shown in Figure 2.19 then the value of the
resistor on the CTAT side can be chosen in a way to have near zero TC at the junction of
the two resistors.

Figure 2.19 - Zero TC point [17]
d) The using of two equal resistors meeting at V
bg
to generate a stiff V
be
voltage source as
shown in Figure 2.20. This is conceptually explained in Figure 2.21.


30

Figure 2.20 – Low voltage bandgap using two V
be
sources [17]


Figure 2.21 - Zero TC with two V
be
sources [17]
31
The resulting output voltage is V
bg
= 0.6 to 0.7 V depending upon the point of cancellation.
The Vbe (CTAT voltage) does not impose a limit on the voltage headroom. The headroom is
limited by the mirrors. So according to [17] the minimum supply voltage depends upon the
headroom needed for the mirrors to operate which is around 0.1 V in 90 nm technologies. So
the supply voltage required is just above the output voltage V
bg
.

[17] proposes a new resistor scheme where the resistors will be in the form of series and
parallel stripes of a single resistor as shown conceptually in Figure 2.22 below.


Figure 2.22 - Combining Vbe Resistors [17]
The proposed architecture removes the additional current path present in conventional BGR.
The output voltage is almost independent of the resistor TC’s and absolute value tolerances.
32
2.9 LOW VOLTAGE BGR COMPARISON
The work done on low supply voltage bandgap references was discussed in this chapter. All
of them have their own advantages and drawbacks. Table 1 below compares the results from
all the discussed works. This gives an overall idea on the performance of the individual
circuit compared to the others in areas like technology used, minimum supply voltage, output
voltage, ppm accuracy and the PSRR in dB.

Circuit type Technology Min. Supply
Voltage (V)
Output
Voltage (V)
Accuracy
(ppm/ºC)
PSRR
(dB)
Resistor Divider
(Banba)
0.4 µm
CMOS


2.1 V

515 mV

±59 ppm/ºC
Not
Mentioned
Resistor Divider
(Waltari)

0.6m

CMOS

0.95 V

720 mV
.24%. Not
mentioned
in ppm.

44dB at

10KHz
Current
Summing
(Ripamonti)

Not

Mentioned

0.9V

521mv
2.4%. Not
Mentioned
in ppm.

Low
Transimpedance
Amplifier
(Jiang)

1.2m

CMOS

1.2 V

1000 mV

+/- 100

ppm/˚C

20dB at

1KHZ
DTMOS
(Annema)
0.35m
CMOS
0.85 V 650 mV 57 ppm/˚C Not
Mentioned
33
Depletion
Transistors
(Peirazzi)

0.35µm

CMOS

0.9 V

510 mV

Not

Mentioned

Not

Mentioned
Threshold
Voltage Based
(Ytterdal)
0.13 µm
Digital
CMOS

0.55 V

400 mV

93 ppm/ºC

Not

Mentioned

Table 1 – Comparison of Low Voltage bandgap references

34








Proposed ¡ow SuppIy BGR CIrcuIL
3.1 Proposed Low supply Bandgap Reference circuit
3.2 Operation
3.2.1 PTAT Current Generation
3.2.2 CTAT Current Generation
3.3 CTAT Voltage Generation at the base of current mirror transistors
3.4 Bandgap output Voltage
_________________________________

3.1 PROPOSED LOW SUPPLY BANDGAP REFERENCE CIRCUIT
The proposed bandgap reference architecture is motivated by the requirement of a low supply
voltage bandgap reference. The circuit can be represented in simplest form as shown below
in Figure 3.1.

35

Figure 3.1 - Proposed bandgap reference in the simplest form
Briefly, the working of the circuit can be explained as the summation of two currents (one
PTAT and the other CTAT) across the resistor R
3
. The diode-connected BJT makes a
conventional CTAT current flow through the resistor combination R
2
and R
3
. The two diode
connected transistors M
3
and M
4
are used for biasing. The voltage at the gate of the
transistors in the current mirror is of CTAT type. This voltage at the gate of M
2
and the
combination of the PMOS with a P+ poly resistor R
1
produces a PTAT current flowing
through the combination R
1
and R
3
.
36
The circuit is designed using the LSI Logic 0.18 micron CMOS process. The parametric
values of the various components used in the circuit are mentioned in Table 2 below. Here
the resistors used are all different from each other. R
1
is P+ Poly resistor with a negative
temperature coefficient. R
2
is a P+ Poly Silicided resistor with a positive temperature
coefficient and R
3
is a Metal 1 resistor with a positive temperature coefficient.


Sr. #

Part #

Type

Value
1 M
1
PMOS W = 45 µm, L = 270 nm
2 M
2
PMOS W = 1 µm, L = 180 nm
3 M
3
PMOS W = 900 nm, L = 180 nm
4 M
4
NMOS W = 8 µm, L = 180 nm
5 R
1
P+ Poly Resistor 29.4 K
6 R
2
P+ Ploy Silicided resistor 16.92 K
7 R
3
Metal 1 Resistor 7.46 K

Table 2 – Component parameters of the proposed circuit
37
3.2 OPERATION
The operation of the circuit will be studied by dividing it into three simpler parts. The first
part will explain the generation of the PTAT current and the second will explain the
generation of the CTAT current. The third will explain the PTAT nature of the gate voltage
of the current mirror transistors M
1
& M
2
.

3.2.1 PTAT Current Generation
The most conventional way of making the PTAT quantity is using the difference in the V
be
’s
of two PN junctions having different current densities. But this technique needs an
operational amplifier to magnify the slope of the delta V
be
. Here, a new technique is used to
get the PTAT current.
Figure 3.2 below shows the circuit that generates the PTAT current.


Figure 3.2 – Circuit for PTAT current generation
38
In the figure above the current in the resistors is given by the square law equation
( )
2 '
2
1
T GS p D
V V
L
W
K I − |
.
|

\
|
= (3.1)

where K
p
= µ
0
C
OX
for the transistor M
2
& V
T
is the threshold voltage of the transistor.
( )
T GS T GS D
V V V V
L
W
Kp I 2
2
1
2 2
− + |
.
|

\
|
= ∴ (3.2)
( ) ( )
(
¸
(

¸

− +


+
|
|
.
|

\
|
− + |
.
|

\
|


|
.
|

\
|
=



T GS T GS T GS T GS OX
D
V V V V
T
V V V V
T
C
L
W
T
I
2 2
2
1
2 2
0
2 2 0
µ
µ
(3.3)
( ) ( )
(
¸
(

¸

|
.
|

\
|





− + − + |
.
|

\
|


|
.
|

\
|
=



T
V
T
V
V V V V V V
T
C
L
W
T
I
T GS
T GS T GS T GS OX
D
0
2 2
0
2 2
2
1
µ
µ
(3.4)

In the above equation (4), there are three parameters that will decide the nature of the current
versus temperature. They are . & ,
0
T
V
T
V
T
T GS





∂µ

µ
0
is the mobility of the carriers. Temperature appears explicitly in the value of surface
mobility for the MOSFET model. The temperature dependence for the mobility as explained
in [14] is determined by:
( )
( )
5 . 1
0
0 0
0
|
|
.
|

\
|
=
T
T
T
T
µ
µ (3.5)
Thus the mobility decreases with the increase in temperature.
39
T
V
GS


has a slope of around 393.09 µV/°C. This would be derived in a later section.
T
V
T


here has a slope of about -65 µV/°C as seen from simulation results for this specific
transistor size and similar biasing. Thus the value of |
.
|

\
|





T
V
T
V
T GS
is around 460 µV/°C and
has a PTAT nature.
The variation of mobility with temperature is much smaller when compared to that of (V
GS
-
V
T
) and thus the current has a PTAT nature. The variation of the current and output PTAT
voltage across temperature is shown in Figures 3.3 and 3.4 below.


Figure 3.3 – PTAT current
40

Figure 3. 4 – PTAT voltage drop across the output resistor
41
3.2.2 CTAT Current Generation
The most conventional technique for generating the CTAT (voltage/current) is through the
use of V
be
of the BJT.

Here the V
be
of the vertical PNP that is present in the technology is used. The variation of the
V
be
of the

VPNP BJT with respect to temperature is shown in Figure 3.5 below. As seen from
the Figure 3.5, the voltage varies about 253.625 mV for the temperature range of -20°C to
120°C at a slope of -1.812 mV/°C.


Figure 3.5 – Variation of PN junction voltage with temperature

This variation is too large compared to that of the PTAT current across the output resistor R
3
.
This is reduced in its value by allowing a PTAT V
GS
for the current mirror transistor M
1
. This
reduces the slope of the Vbe temperature dependence and thus the voltage is a little less
CTAT than before. Additionally, the resistor divider network of R
2
and R
3
helps in reducing
the slope of the CTAT voltage across R
3
more.
42
The circuit generating the CTAT quantity is shown in Figure 3.6 below.

Figure 3.6 – Circuit generating CTAT quantity

Neglecting the base current for the BJT we have,

|
|
.
|

\
|
=
S
BJT
thermal BE
I
I
V V ln (3.6)
where V
thermal
is the thermal voltage and I
S
is the saturation current which can be related to
the device structure by

n i n i
B
n i
S
T n B D Bn
Q
D qAn
I µ
2 2
2
' = = = (3.7)
Here n
i
is the intrinsic minority carrier concentration, Q
B
is the total base doping per unit
area, µ
n
is the average electron mobility in the base, A is the emitter base junction area and T
is the temperature. Here, the constants B and B’ involve only temperature-independent
quantities.
43
The quantities that are temperature dependent are given by

|
|
.
|

\
|
− =
=

thermal
G
i
n
n
V
V
DT n
CT
0 3 2
exp
µ
(3.8)
Here V
G0
is the bandgap voltage of silicon extrapolated to 0°K and the value of n is
approximately 1.5 as shown in equation (3.5).

C and D are temperature-independent quantities. Combining the above four equations yields

|
|
.
|

\
|
|
|
.
|

\
|
=

thermal
G
BJT thermal BE
V
V
E T I V V
0
exp ln
γ
(3.9)
E is another temperature independent constant and = 4 – n 2.5.

For our circuit, the current I
BJT
varies with temperature. We assume for the time being that
the temperature variation is known and that it can be written in the form

α
GT I
BJT
= (3.10)
Here G is another temperature-independent constant.
( ) ( ) [ ] EG T V V V
thermal G BE
ln ln
0
− − − = α γ (3.11)

In the above equation V
G0
, E & G are temperature independent quantities.

( ) ( ) [ ]
( )
( )
( ) EG
T
V
T
V
T
T
V
T
V
EG V T V
T T
V
thermal thermal thermal BE
thermal thermal
BE
ln ln
ln ln


+

+ −


=



+ −


=


γ α
γ α
γ α
(3.12)


44
( – ) has a value of approximately -2.
T
V
thermal


can be calculated as shown below.

q
kT
V
thermal
= (3.13)

Here k is Boltzmann's constant, T is absolute temperature and q is electronic charge. Thus we
have,

q
k
q
kT
T T
V
thermal
=
|
|
.
|

\
|


=


= 8.62 x 10
-5
V/°K. (3.14)

Thus the resulting value of
T
V
BE


is CTAT in nature. The value of the V
be
drop across the
output resistor R
3
across temperature is shown in Figure 3.7 below. This slope of V
be
is
exactly enough to cancel the PTAT-natured slope of the current produced by the transistor
M
2
across the same output resistor.







45
Figure 3.7 below shows the current through the resistor network



Figure 3.7 – Current through the resistor network

Figure 3.8 below shows the voltage drop across the output resistor caused by the CTAT
generation circuit.

Figure 3.8 – Voltage drop across output resistor due to the CTAT generation circuit
46
3.3 CTAT VOLTAGE GENERATION AT THE BASE OF CURRENT
MIRROR TRANSISTORS
The CTAT voltage (i.e., the PTAT V
gs
for PMOS) is generated by the biasing circuit which
consists of two diode-connected transistors M
3
and M
4
. The biasing circuit is shown in
Figure 3.9 below.


Figure 3.9 – Biasing Circuit

47
The output here can be given as

mn
mp mn
DD
OUT
g
g g
V
V
1
1 1
×
+
= (3.15)
where g
mp
and g
mn
are tranconductances of the PMOS and the NMOS transistors
respectively.

mn mp
mp DD
OUT
g g
g V
V
+
= ∴
.
(3.16)

( ) (
(
¸
(

¸

|
|
.
|

\
|
|
|
.
|

\
|


+


×
+

|
|
.
|

\
|
+
×


=



T
g
T
g
g g
g
g g T
g
V
T
V
mn
mp
mn mp
mp
mn mp
mp
DD
OUT
2
1
(3.17)
For the sake of derivation we will assume that |
.
|

\
|


= |
.
|

\
|


=
|
|
.
|

\
|


T
g
T
g
T
g
m mn
mp
.

( )
( )
mp mn
m
mn mp
DD OUT
g g
T
g
g g
V
T
V
− ×


×
+
=



2
(3.18)

In the above equation the two terms that will decide the nature of the output are
( ).
mn mp
m
g g and
T
g




Here, g
mn
> g
mp
as the transconductance for NMOS is greater than PMOS if they are similarly
sized. Here, since NMOS is much larger than PMOS we surely have g
mn
> g
mp
.

The transconductance can be calculated as

GS
D
m
V
I
g


= . (3.19)

48
Temperature dependency of g
m
can be defined as
( ) ( ) ( ) ( ) T V V T k T g
T GS m
− × = . (3.20)
As discussed earlier both V
th
and k decrease with the rise in temperature. But the effect of k
(T) is more than that of V
th
(T). Thus the overall value of g
m
reduces with the increase in
temperature. This change in g
m
is more than that of (g
mn
– g
mp
), and thus the output is of
CTAT in nature.

The variation of the output with respect to temperature is shown in Figure 3.10 below


Figure 3.10 – Output from the biasing circuit
49
3.4 BANDGAP OUTPUT
The output of the circuit can be calculated by using the current in the two branches. If we
assume the currents in the two branches to be I
1
and I
2
then the voltage V
out
can be defined as
( )
3 2 1
R I I V
OUT
+ = (3.21)

3 2
2 1
R I
R R
V
V
BE
OUT
|
|
.
|

\
|
+
+
= ∴ (3.22)
Using the above relation a desired value for V
out
can be obtained by iterating the values of
R
1
, R
2
and R
3
. The output of a particular configuration of the resistors is shown in the
Figure 3.11 below.

Figure 3.11 - Bandgap output for a particular combination of resistors
Depending on the need of the application the value of the bandgap output voltage can be
changed using different combination of resistors. The current consumption is this case was
96µA. The BJT was using 60 µA of the total current consumed. 5 µA of current was
unaccounted for in the simulation and is assumed to be the leakage current of the BJT.
50








VersIons oI LIe Bundgup ReIerence

4.1 Versions of the Bandgap Reference
4.2 Circuit Variation # 1
4.3 Circuit Variation # 2
4.4 Comparison Chart
_________________________________

4.1 VERSIONS OF THE BANDGAP REFERENCE

This section will discuss two different architectures of the bandgap reference circuit
explained in the previous section. The bandgap reference circuit explained in the previous
section varies only 900 µV over a temperature variation from -20°C to 120°C. The circuit
exhibits a very low PSRR. The Figure 4.1 below shows bandgap voltage variation over the
supply voltage variation from 950 mV to 1050 mV.
51

Figure 4.1 – Voltage supply variation of the basic BGR circuit
The PSRR of the circuit can be calculated by the equation

|
|
.
|

\
|


=


OUTPUT BANDGAP
SUPPLY POWER
V
V
PSRR log 20 in dB (4.1)
db
mV
mV
PSRR 5191 . 7
077 . 42
100
log 20 = |
.
|

\
|
= (4.2)

This circuit as shown in the figure above has a PSRR of about 7.5 dB. This is very small as
generally a good bandgap reference circuit should have a PSRR of about 20 dB. The
advantage of this configuration is that it has an accuracy of 21 ppm/ºC.




52
Two variants of the basic bandgap reference circuit will be discussed in this section. Both of
the circuits have a better PSRR than the present circuit. The first one supports a wider range
on the bandgap voltage reference with an improved PSRR. The other circuit supports only a
very low (up to 200 mV) bandgap reference output voltage but has a very good PSRR as
compared to the other two circuits.

53
4.2 - CIRCUIT VARIATION # 1
This circuit as shown in Figure 4.2 keeps the most of the configuration of the original circuit.
The basic PSRR issue in the original circuit was the fact that the PTAT generating PMOS
transistor is directly connected to the power supply. So any variation in the power supply
directly affects the output of the circuit. Whereas the CTAT generating BJT is shielded from
the power supply through the current mirror transistor. In this variation of the circuit the
PTAT generating MOS is connected to a less variable voltage as generated by the bias
circuit.


Figure 4.2 – Circuit Variation # 1
54
The biasing method used here as shown in Figure 4.3 is known as threshold voltage self
biasing. The idea here is to get the current in the transistor M5 to be almost independent of
supply voltage variations. This would make the voltage drop across the resistor R4 to be
independent of supply voltage and will thus depend only on temperature.

Figure 4.3 – Threshold voltage self biasing

If we neglect the body effects and the channel length modulation effects then we can define
the drop across the resistor as

( ) R
V
R
V
I
C L W
I
V V V
THN GS
R
OX
R
THN GS R
≈ = ¬ + = =
8
4
5
4
8 4
/
2
(If (W/L)
5
C
OX
is large) (4.3)
55
This result implies that current I
R4
will be independent of supply voltage. In practice, this is
not true due to the finite output resistance of the MOSFET’s.

The accuracy of current I
R4
is determined by the threshold voltage accuracy and the resistor
accuracy, which could vary 20%. Note also that threshold voltage’s TC and the resistor’s TC
determine the circuit’s temperature dependency. The temperature coefficient of the resistor is
positive while that of the threshold voltage is negative.

Consequently, the threshold voltage self-biasing technique provides a current with a large
negative temperature coefficient. This in the original circuit was done by the two diode
connected transistors making up the biasing circuit. The CTAT nature of this voltage is very
important to the functionality of the circuit as explained in the previous section.

The startup of the bias circuit is taken care of by the transistor M9 to avoid the zero current
initial condition. The PTAT generating PMOS is provided with a power supply by a point on
the bias circuit shown as the “Dummy Supply”. The characteristic needed in the supply is
that it should vary very little with temperature and with actual supply voltage variation. But
in this case the supply voltage has a PTAT nature as shown in Figure 4.4 below.

The biasing for the start-up circuit is provided by two diode-connected transistors as shown
in the figure. The circuit will not be affected by the PVT variations involving this two
transistor biasing circuit.
56

Figure 4.4 – Supply Voltage for the PTAT generating part of the circuit

This PTAT nature of the supply voltage results in a PTAT V
GS
for the transistor. This PTAT
V
GS
generates a PTAT current as explained in the previous chapter.

The variation of this
voltage over 100 mV supply voltage variation is about 50 mV and thus the circuit exhibits a
better PSRR compared to the original circuit.

Figure 4.5 – Variation of Output voltage with 100 mV supply voltage variation
57
The PSRR of the circuit can be calculated by the equation

|
|
.
|

\
|


=


OUTPUT BANDGAP
SUPPLY POWER
V
V
PSRR log 20 in dB (4.4)
db
mV
mV
PSRR 5269 . 8
4672 . 37
100
log 20 = |
.
|

\
|
= (4.5)
The improvement in the PSRR comes only at the cost of bandgap voltage range and accuracy
over temperature. The accuracy of the circuit as shown in Figure 4.6 below is about 96
ppm/ºC which is low as compared to the original circuit. The dummy supply voltage used
here reduces the bandgap voltage range considerably. The cancellation of the PTAT and the
CTAT quantities is also affected. This causes a reduction in accuracy over the temperature
range. In the original circuit the output varies only about 900 µV over a temperature range of
-20 °C to 120 °C. The variation for this version is around 5 mV over the temperature range of
-20 °C to 80 °C as shown in Figure 4.6 below. The current consumed by this configuration
was 114 µA.

Figure 4.6 – Performance over temperature
58
4.3 - CIRCUIT VARIATION # 2
This variation of the circuit offers a significantly improved PSRR compared to the other two
variations. This improvement in PSRR comes at the cost of lack of range in the output for the
bandgap reference circuit. The circuit configuration is shown in Figure 4.7 below.


Figure 4.7 – Circuit variation # 2
59
This variation of the original circuit is essentially the same as the first one. The only
difference is that the PTAT generation circuit here uses a NMOS transistor in the source
follower configuration. The advantage of this circuit is that the PSRR is very good but the
major disadvantage of this configuration is the range of the output voltage. It is only usable
up to 250 mV.

Figure 4.8 below shows the output voltage over supply voltage variation of 100 mV.


Figure 4.8 - PSRR of Circuit Variation # 2

The PSRR of the circuit can be calculated by the equation

|
|
.
|

\
|


=


OUTPUT BANDGAP
SUPPLY POWER
V
V
PSRR log 20 in dB (4.6)
db
mV
mV
PSRR 2 . 27
3675 . 4
100
log 20 = |
.
|

\
|
= (4.7)

60
The PSRR of 27.2 dB is very good for a bandgap reference circuit. The other advantage of
the circuit is the accuracy over temperature of about 38 ppm/ºC. The TC cancellation for this
configuration is better than that in circuit variation #1. The variation of the bandgap output
voltage over the temperature range of -20 °C to 80 °C is shown in Figure 4.9 below. The
current consumed by this configuration was 110 µA.


Figure 4.9 – Bandgap output voltage

61
4.4 - COMPARISON CHART
Table 3 below shows a parametric comparison between the three variations of the bandgap
circuit to a good bandgap reference circuit. The good bandgap reference circuit considered
here is the one by Banba [5]. As seen from the table every configuration has its own
advantages and disadvantages when compared to each other or to the good bandgap reference
circuit.

Parameter
Proposed
Circuit
Circuit
Variation –I
Circuit
Variation - II
Popular BGR
Circuit

Bandgap Output

Voltage

302 mV 460 mV 155 mV 515 mV

Output Voltage

Range

200 mV to 600
mV
200 mV to 500
mV
100 mV to 250
mV
N/A

Precision

(ppm/ºC)

21 ppm/ºC 96 ppm/ºC 38 ppm/ºC ±59 ppm/ºC

PSRR

(dB)

7.5 dB 8.5269 dB 27.2 dB N/A

Table – 3 Comparison between the three variations
62








Process VurIuLIons und TrunsIenL Response

5.1 Process Variations and Transient Response
5.1.1 Process Variations
5.1.2 Transient Analysis
_________________________________

5.1 PROCESS VARIATIONS AND TRANSIENT RESPONSE

This section will discuss about techniques to protect the circuit from resistor and transistor
process variations and the response of the circuit versus time. The process variation remedies
are explained for the original circuit. Similar remedies can also be applied to the circuit
variations as well.

5.1.1 Process Variations
The variations in the resistors and the transistors affect the circuit in this case. The process
variations in the size of the current mirror transistors can result in the alteration of the current
that they mirror and thus affect the output voltage of the circuit. The variation in the absolute
value of the resistors also affects the circuit as the output voltage relies heavily on the ratio of

63
the resistors. A digital trim [16] as shown in Figure 5.1 is used here to get the exact resistor
and transistor value required.

The limitation of this technique is that the technology should support Electrically Erasable
Programmable Read Only Memory (EEPROM). For this circuit 8 trim bits have been used.
The current in the output branch is monitored and accordingly the switches on the transistors
are controlled. If the current is too low then all the switches are closed and if it is perfect then
none are closed. The first four bits B
0
– B
3
stored in the EEPROM are devoted for transistor
trim. The EEPROM is written with the appropriate bits through a digital bus.


64

Figure 5.1 – The Resistor and transistor trim configuration for the original circuit
65
Bits B
4
– B
7
are devoted for the resistor trim. The value of the resistor is monitored by
external tests and the value is trimmed with the help of the resistor trim bits. Series resistance
of 2 K can be added in series to the output resistance.

As seen from the above discussion, extra width for transistor and extra series resistance can
be added to trim them to the exact value. But if the final value of the resistor is more than
what is needed then the resistance cannot be removed to come to the exact value. Thus here
care is taken that the resistor always comes out either exactly the same or less than the
desired value. The same care is taken for the transistors as well.


66
5.1.2 Transient Analysis
The original circuit does not have any startup circuit. The transient analysis of the circuit
shows that it does not need any startup circuit. This makes sense as if we look at the circuit:
there is no initial condition requirement and it is safe to assume that the BJT and the PMOS’s
will start in saturation region. The transient response of the original circuit is shown in Figure
5.2 below.



Figure 5.2 – Transient response of the original circuit
The two variations of the circuits are provided with startup circuits as explained in the
previous section. These startup circuits insure that the additional circuitry added to the
original circuit starts up as we want it to. The transient response of circuit variation # 1 which
uses PMOS in the output branch which is powered not by the power supply but by a point in
the additional circuitry added is shown in Figure 5.3 below.

67

Figure 5.3 – Transient response for Circuit Variation # 1

The circuit variation # 2 also has a start up circuit as mentioned in the previous section. This
variation uses an NMOS connected in the source follower configuration in the output branch.
The transient response of the circuit is shown in Figure 5.4 below.

Figure 5.4 – Transient response for Circuit Variation # 2
68
CONCLUSION AND FUTURE WORK

The goal of this work was to develop a new sub-1 V bandgap reference topology without the
use of any special devices. In this work effort is made to understand various topologies of the
existing bandgap reference circuits and identify the limitations which make these circuits
difficult to use with current processes, mainly with sub-1V technologies. A new topology for
bandgap reference was developed which did not use an operational amplifier as used in the
conventional circuits.

This new architecture used the current of a BJT to make the conventional CTAT. The PTAT
was generated with a PMOS (having PTAT V
GS
as its gate) and a P+ Poly resistor. Both the
currents were summed across a resistor to make a near-zero temperature coefficient voltage
reference. The simulation results show a bandgap output voltage of 302 mV with and
accuracy of 21 ppm/ºC. Two variations of this circuit were introduced to improve on the poor
PSRR (7.5 dB) of the proposed circuit. These variations have output voltage of 460 mV and
155 mV with and accuracy of 96 ppm/ºC and 38 ppm/ºC respectively. They have PSRR’s of
8.53 dB and 27.2 dB respectively.

A digital trimming scheme using EE-PROM was proposed to cope with the process
variations in the resistors and transistors.

69
Future Work
The future work will include developing a master circuit which will have all the advantages
of the three variations of the circuit proposed in this work. This master circuit will have a
good output voltage range, good precision and a very high PSRR.

The EE-PROM based digital trimming may not be feasible in all the technologies.
Alternative approaches not using an EE-PROM need to be developed.
70
REFERENCES


1) Widlar, R. J. “New Developments in IC Voltage Regulators,” IEEE Journal of Solid
State Circuits, Vol. SC-6, p 2-7, February 1971.

2) Pease, Robert, “The Design of Band-Gap Reference Circuits: Trials and Tribulations”,
IEEE 1990 Bipolar Circuits and Technology Meeting, pp. 214-218, 1990.

3) Nicollini, Germano and Senderowicz, Daniel, “A CMOS Bandgap Reference for
Differential Signal Processing”, IEEE Journal of Solid State Circuits, Vol. 26, pp. 41,
January 1991.

4) Gray, Paul, Meyer, Lewis, “Analysis and Design of Analog Integrated Circuits, 4
th

Edition,” John Wiley and Sons Inc., 2001.

5) Banba, Hironori, et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,”
IEEE Journal of Solid State Circuits, Vol. 34, pp. 670-674, May 1999.

6) Waltari, Mikko, and Halonen, Kari, “Reference Voltage Driver for Low-Voltage CMOS
A/D Converters,” Proceedings of ICECS 2000, Vol. 1, pp. 28-31, 2000.

7) Ripamonti, G., et al., “Low Power – Low Voltage Band Gap References for Flash-
EEPROM Integrated Circuits: Design Alternatives and Experiments,” Proceedings of
ICECS 1999, Vol.2, pp. 635-638, 1999.
71
8) Jiang, Yueming, and Lee, Edward, “Design of Low-Voltage Bandgap Reference Using
Transimpedance Amplifier,” IEEE Transactions on Circuits and Systems - II, Vol. 47,
pp. 552-555, June 2000.

9) Annema, Anne-Johan, “Low-Power Bandgap References Future DTMOST’s,” IEEE
Journal of Solid State Circuits, Vol. 34, pp. 949-955, July 1999.

10) Pierazzi, Andrea, et al., “Band-Gap Reference for near 1-V operation in standard CMOS
technology,” IEEE Custom Integrated Circuits Conference, pp. 463-466, 2001.

11) Yttedral, “CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V”,
Electronic Letters, Vol. 39, N0. 20, October 2003.

12) Miller P, Moore D, “Precision Voltage References,” Texas Instruments Analog
Applications Journal, November 1999.

13) Brokaw, A.P, “A simple three-terminal IC bandgap reference,” IEEE Journal of Solid
State Circuits, Vol. 9, pp. 388 - 393, December 1974.

14) Tsividis Y, “Operation and Modeling of the MOS Transistor – 2
nd
Edition,” Oxford
University Press,May 2003



72

15) Blalock B.,Reference
http://www.erc.msstate.edu/mpl/education/classes/ee8223/pp59-68.pdf

16) Shuhuan Yu, Yiming Chen, Weidong Guo, Xiaoqin Che, Smith, K.F., Yong-Bin Kim, “A
digital-trim controlled on-chip RC oscillator,” IEEE Midwest Symposium on Circuits and
Systems, Vol. 2, pp. 882 – 885, August 2001.

17) Washburn Clyde, “A bandgap reference for 90nm and beyond”, EE Times, page 2, Issue -
11th April.












THESIS RELEASE PERMISSION DEPARTMENT OF ELECTRICAL ENGINEERING COLLEGE OF ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY ROCHESTER, NEW YORK

Title of Thesis:

A Sub 1 V Bandgap Reference Circuit

I, Ashish Digvadekar, hereby grant permission to Wallace Memorial Library of the Rochester Institute of Technology to reproduce my thesis in whole or in part. Any reproduction will not be for commercial use or profit.

Signature _______________________________________________________________ Date

ACKNOWLEDGEMENT
A journey is easier when you travel together. Interdependence is certainly more valuable than independence. I have worked on this thesis for more than a year. I owe the completion of this thesis to a countless number of people. It is impossible to mention all the names here but I would definitely take this opportunity to thank the following people who have guided, encouraged, motivated and helped me through the different phases of the thesis.

First I would like to thank Dr. Moon for his valuable guidance throughout. He was always there to answer each of my doubts, from the trivial ones to the more genuine ones. The fruitful discussions with him were something I always looked forward to. He has also been of great help to me in matters not concerning the thesis. I have worked with him for two and a half years now and he inspired me both as a human being and as an advisor.

This thesis would not have initiated without Dr. Mukund. He led me into the thesis topic and to Dr. Moon as thesis advisor. I would also like to mention the names of Mr. Clyde Washburn and Tejasvi Das for their valuable time to set things up for me. I would like to thank Dr. Islam and Dr. Mukund for taking time out of their busy schedule and going through my thesis, providing their valuable insights. I will also thank the LSI Logic team for allowing me to use their models and their inputs.

i

I would especially like to thank my boss and senior colleagues of the Temperature Sensor group at East Coast Labs of National Semiconductors for the knowledge they shared with me. Thank you Mr. Eric Blom and Mr. Gary Sheehan for introducing to me the concept of digital trimming. Thank you Jun, Stuart, Peter, and Matt for answering my endless questions.

My friends were of great help right through the thesis. First to mention is Ashish Vora who always made valuable suggestions which have affected the outcome of the thesis. I will thank Aakash, Vivek, Ajish and the rest for the constructive criticism.

I can never forget the efforts and sacrifices of my family. My dad for teaching me the basics of life and the financial support, my Mom for her continuous prayers and good wishes, my brother for shaking me up when he saw me discouraged and Palak for keeping me motivated towards my thesis. Above all I would like to thank God. I know he is always there for me and helps me out of all difficult situations I get myself into.

ii

A table discussing all the investigated circuits is provided towards the end of the chapter as a summary. Chapter Four talks about two variations of the proposed architecture.ABSTRACT This thesis proposes a novel technique for a low supply voltage temperature-independent reference voltage. Chapter Three proposes a novel technique to generate a temperature-independent voltage which does not use an operational amplifier. Each one of them has its own merits and drawbacks. This chapter also provides a mathematical understanding for behavior of the circuit. the threshold voltages don’t scale proportionally and thus low supply reference circuits have replaced the conventional bandgap reference circuit. With the scaling of supply voltages. These variations are designed in order to improve the performance of the proposed circuit against power supply variations. Finally Chapter Five discusses the effects of process variations and transient response of the proposed circuit. The second chapter investigates the existing low supply voltage reference circuits with their advantages and the limitations. iii . A digital trimming scheme using an EE-PROM is proposed to manage almost all of the process variation effects on the circuit. The terminology used in the bandgap world is introduced here. The first chapter of this work discusses the conventional bandgap references (The Widlar and Brokaw references).

.2 Brokaw Bandgap reference…………………………………………………….4 Bandgap reference principle…………………………………………………… 12 1.5 2. Background of Low Supply Voltage Bandgap Reference 2.…………………………..……………………………………… 32 iv .8 2.. 10 1... 1.2 2.1 2..2 Classical Bandgap Circuits – Widlar and Brokaw…………………………….. Abstract…………………………………………………………………….7 2.. 26 Threshold Voltage based circuit…………………………………………………... List of Figures……………………………………………………………. 16 Current Summing and a voltage summing Circuit…..3. 19 Transimpedance Amplifier………………………………………………………. 24 Depletion transistors……………………………………………………………….1. 29 Low Voltage BGR Comparison …………. 22 Dynamic Threshold MOS (DTMOS)…………………………………………….TABLE OF CONTENTS Acknowledgement…………………………………………………….3 2.6 2. 14 Resistor Divider Network………………………………………………………….1 Zener Based Voltage Reference………………………………………………… 1.....1 Widlar Bandgap reference……………………………………………………… 8 1.3....1 Bandgap terminology…………………………………………………………… 1.. 1 2 4 6 8 1.1.8 __ Chapter # 2 Background of Low Supply Voltage Bandgap Reference………………………..4 2. List of Tables……………………………………………………………… Introduction 1 i iii iv vi viii ____ __ Chapter # 1 Introduction…………………………………………………………………..2 Bandgap Voltage Reference……………………………………………………... 28 Bandgap using two Vbe sources…………………………………………………. Table of Contents………………………………………………………….

Bandgap output Voltage………………………………………………………… 3....4 CTAT Voltage Generation at the base of current mirror transistors……….2 CTAT Current Generation……………………………………………………… 41 Versions of the Bandgap Reference 4.2... 5.. Conclusions and Future Work…………………………………………….2.1 Process Variations………………………………………………………………… 62 5.Proposed Low Supply Bandgap Reference Circuit 3.1 3..2 4. Circuit Variation # 2……………………………………………………………....1 PTAT Current Generation……………………………………………………… 3.. 68 References…………………………………………………………………..1..2 Transient Analysis………………………………………………………………. 37 37 46 49 3.. 70 v .. 34 Operation………………………………………………………………………….2 __ Chapter # 3 Proposed Low supply Bandgap Reference circuit…………………………….4 __ Chapter # 4 50 53 58 61 Versions of the Bandgap Reference…………………………………………...3 4.1 __ Chapter # 5 62 66 Process Variations and Transient Response…………………………………. Process Variations and Transient Response 5.3 3.. Comparison Chart………………………………………………………………..1 4..1. Circuit Variation # 1………………………………………………………….

LIST OF FIGURES
1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 Buried Zener reference circuit…………………………………………………….. Basic Bandgap Circuit…………………………………………………………….. Widlar bandgap reference…………………………………………………………. Brokaw bandgap reference………………………………………………………... a) Vertical NPN transistor b) Vertical PNP transistor…………………………….. Conventional BGR circuit…………………………………………………………. BGR using resistor divider network……………………………………………… Measured VREF characteristics of the proposed BGR…………………………….. Low voltage BGR as presented by [6]……………………………………………. Generated reference voltage vs temperature………………………………………. Current Summing BGR……………………………………………………………. Temperature variation of the BGR in the current summing circuit………………. Voltage Summing BGR…………………………………………………………… a) VREF vs. Vdd b) VREF vs. Temperature……………………………………… Transimpedance Amplifier using BGR……………………………………………. Measured VREF characteristics without trimming………………………………... DTMOS cross-section…………………………………………………………….. Low voltage DTMOS BGR……………………………………………………….. 2 4 8 10 12 13 16 17 18 18 19 20 21 21 22 23 24 25 25 26 27 27 28 28 29 30 30 31 35 37 39 40 41 42 vi

VREF vs temperature……………………………………………………………... Opamp using transistors in depletion mode……………………………………….. Simulated output voltages at 27ºC at different supply voltages…………………... Measured VREF vs supply voltage for various temperatures……………………. Threshold Voltage BGR Concept…………………………………………………. 2.18 Simulated BGR Output……………………………………………………………. 2.19 Zero TC point……………………………………………………………………… 2.20 Low voltage bandgap using two Vbe sources…………………………………….. 2.21 Zero TC with two Vbe sources……………………………………………………. 2.22 Combining Vbe resistors…………………………………………………………... 3.1 3.2 3.3 3.4 3.5 3.6 Proposed bandgap reference in the simplest form………………………………… Circuit for PTAT current generation………………………………………………. PTAT current……………………………………………………………………… PTAT voltage drop across the output resistor…………………………………….. Variation of PN junction voltage with temperature……………………………….. Circuit generating CTAT quantity…………………………………………………

3.7 3.8 3.9 3.10 3.11 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 5.4

Current through the resistor network……………………………………………… Voltage drop across output resistor due to the CTAT generation circuit…………. Biasing Circuit…………………………………………………………………….. Output from the biasing circuit……………………………………………………. Bandgap output for a particular combination of resistors…………………………. Voltage supply variation of the basic BGR circuit………………………………... Circuit Variation # 1………………………………………………………………. Threshold voltage self biasing…………………………………………………….. Supply voltage for the PTAT generating part of the circuit………………………. Variation of output voltage with 100 mV supply voltage variation………………. Performance over temperature…………………………………………………….. Circuit Variation # 2……………………...……………………………………….. PSRR of Circuit Variation # 2…………………………………………………….. Bandgap output voltage…………………………………………………………… The resistor and transistor trim configuration for the original circuit……………. Transient response of the original circuit………………………………………….. Transient response for Circuit Variation # 1………………………………………. Transient response for Circuit Variation # 2……………………………………….

44 45 46 48 49 51 54 54 56 56 57 58 59 60 64 66 67 67

vii

LIST OF TABLES
1 Comparison of low voltage bandgap references………….,………………………….. 32 2 Component parameters of the proposed circuit……………………………………….. 36 3 Comparison between the three variations……………………………………………... 61

viii

1.1 Introduction 1.1.1 Zener Based Voltage Reference 1.1.2 Bandgap Voltage Reference 1.2 Bandgap terminology 1.3 Classical Bandgap Circuits – Widlar and Brokaw 1.3.1 Widlar Bandgap reference 1.3.2 Brokaw Bandgap reference 1.4 Bandgap reference principle

_________________________________
1.1 - INTRODUCTION

Voltage reference circuits are precision references which exhibit little dependence on supply voltage variations and process parameters and a well defined dependence on temperature. These references are very important for the accurate working of various circuits like data converters, PLL’s, dynamic random access memories (DRAM’s) and oscillators. The resolution of an A/D or D/A converter is limited by the precision of its reference voltage over the circuit’s supply voltage and operating temperature ranges. Thus the precision voltage reference forms an integral part of almost all circuit designs.

1

d) Accurate over a wide range of temperature. b) Accuracy and stability over supply voltage & time.Some of the desired characteristics of a voltage reference are:a) Ability to be implemented in silicon. Figure 1. This is provided through a resistor from a higher supply voltage.1 Zener-based voltage reference The simplest and the conventional form of a voltage reference is the Zener-based voltage reference. to use it as a reference a constant current is required. Here the Zener diode operates in the reverse bias region and current begins to flow in it at a specific voltage (around 6 V) and thereafter the current increases rapidly with the increase in voltage.1. The two most popular voltage references are:a) Zener-based Voltage reference b) Bandgap Voltage reference 1.1 – Buried Zener reference circuit 2 . Thus. c) Proper startup value.

They need a supply voltage of at least 6 V. have the best temperature performance.1 [12] shows a buried Zener voltage reference where the diode is biased by a current source. The ones fabricated on the surface are noisier as they can get contaminated easily. in combination with their temperature compensating diodes. But their biggest limitation is the minimum supply voltage required.Figure 1. but the ones that. 3 . have a breakdown voltage just below 7 V. Thus these types of references are no longer used. Buried Zener diodes can be made with a range of voltages and have good low noise performance (better than bandgap references). The gain of the amplifier is decided by the resistor values R4 and R3.1) They are called buried diodes as they are fabricated beneath the surface of the chip. The buried diode references are more expensive than the bandgap references but are more accurate. The resistors R1 and R2 form a resistor divider network across the Zener diode. The divided voltage is applied to the non-inverting terminal of an operational amplifier whose output is the reference voltage. The expression for the output is Vout = R2 1 + R4 ×V R3 R1 + R 2 ( ) (1. In today’s technology the supply voltages are always shrinking and 6 V is just not the norm.

This can be explained as two quantities B1 and B2 having opposite temperature coefficients and choosing the coefficients c1 and c2 in such a way that c1 ∂B1 ∂B + c2 2 = 0 ∂T ∂T (1. Figure 1.2) Thus the reference voltage Vout = c1V1+c2V2 has a zero temperature coefficient.2 Bandgap Voltage Reference A Bandgap reference circuit is one where two quantities with opposite temperature coefficients are added with a proper weighing factor to result in a temperature coefficient of approximately zero.1.1.2 – Basic Bandgap Circuit 4 .

2 shows a bandgap circuit in its very basic form. Here the Vbe. All the terminology is discussed in the next section. which has a negative temperature coefficient is complementary to absolute temperature and the delta Vbe is proportional to absolute temperature and a weighted addition of both results in the Vref with a near zero temperature coefficient. 5 .Figure 1.

It has a nearly constant value and its variation with temperature is small. Most of the bandgap reference circuits because of its linearity use the Vbe of a transistor as the CTAT voltage.. Most of the bandgap reference circuits use the difference in the Vbe’s of two transistors operating under same current densities as the PTAT voltage. b) PTAT Voltage PTAT stands for proportional to absolute temperature which means that the quantity varies proportionally with absolute temperature .17 eV.1. the voltage decreases with absolute temperature. Typically for silicon its value is approximately 1.i. 6 . c) CTAT Voltage CTAT stands for complementary to absolute temperature which means that the quantity varies complementary to absolute temperature ..e.i.BANDGAP TERMINOLOGY a) Bandgap Voltage Bandgap voltage of a semiconductor measured in eV refers to the potential energy difference between the valence band and the conduction band for that semiconductor.2 .e. the quantity increases with absolute temperature. Each type of a semiconductor has a unique bandgap.

3) 7 . If the reference is accurate to within 10 ppm. Designers typically use this measure to specify temperature coefficients and other parameters that change little under varying conditions. or 2.5 µV. then it is extremely good performance for any voltage reference. e) Parts per million (PPM) Reference-accuracy unit used commonly with precision voltage reference designs. 1 ppm is one-millionth of 2. This resulting voltage is equal to the bandgap voltage of the semiconductor at the reference temperature.5 V. The PSRR for a Bandgap reference circuit can be calculated by the equation PSRR = 20 log ∆VPOWER − SUPPLY in dB ∆VBANDGAP −OUTPUT (1.d) Bandgap Reference circuit (BGR) A bandgap reference circuit is one which does a weighted addition on the PTAT voltage with the CTAT voltage to have an end result having a near-zero temperature coefficient. For a 2.5 V reference. f) Power Supply Rejection Ratio (PSRR) PSRR is defined as the ability of the circuit to maintain its output voltage as its power-supply voltage is varied.

220 V) reference. further depletion mode transistors are not available in most CMOS processes. This provides low temperature coefficient (TC).1 Widlar Bandgap reference The first bandgap reference was proposed by Robert Widlar in 1971 [2] as shown in Figure 1.3. however.CLASSICAL BANDGAP CIRCUITS – WIDLAR AND BROKAW 1.3 . It used conventional junction isolated bipolar technology to make a stable low voltage (1.3 below. Early MOS implementations of these voltage references were based on the difference between the threshold voltages of enhancement and depletion mode MOS transistors [3].1.3 – Widlar bandgap reference[2] 8 . the drawbacks are that the output is not easy to control because of the direct dependence on the doses of ion implantation steps and. Figure 1.

this implies I1R1=I2R2 ∴ I2 = II V R I ∆VBE VThermal = ln 1 S 2 = Thermal ln 2 S 2 R3 R3 I 2 I S1 R3 R1 I S1 R2 I S 2 R2 VThermal ln R3 R1 I S 1 + VBE 2 = KVThermal + V BE 2 (1. ∆VBE = I 2 R3 ∆VBE = VhermalT ln II I1 I − VThermal ln 2 = VThermal ln 1 S 2 I S1 IS2 I 2 I S1 (1.7) ∴VOUT = I 2 R2 + VBE 2 = (1. Also the performance of the circuit depends heavily on the current density in Q2 which will change if the circuit is loaded.6) Assuming that Vbe3 = Vbe2. R2 and R3 can be manipulated to achieve the desired value of K.5) ∴VBE 3 − VBE 4 = I 2 R3 But.The Widlar circuit shown above operates as explained with equations below: V BE 3 = V BE 4 + I 2 R3 (1. 9 . Drawbacks of the basic four-transistor circuit include the fact that the reference output voltage cannot be changed.8) R1.4) (1.

The circuit has two transistors and collector current sensing to form the basic bandgap voltage. Figure 1.9) ∴VOUT = V BE1 + 2 R1 kT A ln 1 R2 q A2 (1. Figure 1. The output voltage can be expressed as VOUT = V BE1 + Voltage _ across _ R1 (1.4 – Brokaw Bandgap reference [13] 10 .4 below shows the Brokaw bandgap reference circuit.3.10) Here A1 and A2 are the areas of Q1 and Q2 respectively.1.2 Brokaw Bandgap reference Paul Brokaw made his bandgap reference [13] by solving many of the problems in the Widlar reference.

The Vbe acts as a CTAT. 11 . The proper weighted addition of both the quantities leads to a temperature invariant Vout which is the bandgap reference output. thus acts like a PTAT.The reason for the voltage across R1 having a positive temperature coefficient is that the currents through both the transistors are equal.

For this they rely on well transistors. These are shown in Figure 1. Thus every bandgap reference will result from the weighted addition of a PTAT voltage with a CTAT voltage. Figure 1.5 .1.5 below. These are vertical bipolar transistors that use wells as their bases and substrate as their collectors.a) Vertical NPN transistor b) Vertical PNP transistor 12 .4 .BANDGAP REFERENCE PRINCIPLE Most of the modern bandgap reference circuits are made on the Paul Brokaw school of thought.

A conventional bandgap [4] reference circuit is shown in the Figure 1. Figure 1. This is around 1.4 to 1. Even if we consider a simple two stage opamp.6. 13 .26 V.6 – Conventional BGR circuit [4] The output voltage for a conventional BGR is 1.5 V depending upon the technology. the minimum supply voltage is the output Vout plus the VDSsat drop across the output stage transistor.12) Here n is the ratio of the sizes of the two bipolar junction transistors and Vt is the thermal voltage.11) ∴VOUT = VBE 2 + Vt ln n 1 + (1. The output of the circuit is given by the equation: VOUT = VBE 2 + ∆VBE (R3 + R2 ) R3 R2 R3 (1. The first term represents the CTAT voltage and the second term represents the PTAT voltage. The output here is from an opamp.

1 2.2 V. The supply voltage scales with the technology.8 _________________________________ 2.4 2. so do the supply voltages. For the low voltage bandgap reference design the following approaches have been used: 14 .6 2.2 2.5 2. Here arises the need to come up with new topologies of bandgap reference to operate properly in the low supply voltages.BACKGROUND OF LOW SUPPLY VOLTAGE BANDGAP REFERENCES As the technology scales.1 .3 2.2. The supply voltages recently tend to be Background of Low Supply Voltage Bandgap Reference Resistor Divider Network Current Summing and a voltage summing Circuits Transimpedance Amplifier Dynamic Threshold MOS (DTMOS) Depletion transistors Threshold Voltage based circuit Low Voltage BGR Comparison in the range of 0. This makes it difficult to incorporate conventional designs of bandgap reference circuits to processes having supply voltage near 1 V. but the threshold voltage of the transistors does not scale at the same rate.7 2.9 V – 1.

1) Resistive divider networks 2) Current summing and a voltage summing circuits 3) Transimpedance amplifier 4) Dynamic Threshold MOS (DTMOS) 5) Depletion transistors 6) Threshold voltage based circuit 7) Bandgap using two Vbe sources 15 .

which is the CTAT here.1. Here the diodes can be replaced with PNP transistors available in the today’s processes. The circuit configuration is shown in Figure 2. R3 and R2. and the other current in proportional to VT. Figure 2.2. 16 . The forward bias voltage of the diodes is defined as VF.1) The value of VREF can be adjusted by altering the values of R4. VREF = R4 VF 1 dVF + R2 R3 (2. The concept here used was to sum two currents (instead of voltages in the conventional BGR circuits). One of the currents is proportional to VF.2 RESISTOR DIVIDER NETWORK The resistive divider network proposed by Banba [5] is shown in the Figure 2.1 – BGR using Resistor divider network [5] Here.1 below.

2 to 4 V at 27°C. the sub-1 V operation is achieved by folding the circuit in Figure 2. However the minimum supply voltage was limited to 2.2 Measured VREF characteristics of the proposed BGR [5] Several modifications were proposed to the circuit presented in [5].1 V. The problem in this circuit is that the nodes Va and Vb are at a voltage of 0. The voltage at these nodes is reduced with the help of a resistor divider network as shown below in Figure 2. Figure – 2.The circuit was designed for a reference voltage of 515 mV. In one of the modifications by Waltari [6]. 17 . VREF showed a variation of 515 mV ± 1 mV for the supply variation of 2.1 at nodes Va and Vb.2 below.3.7 V and this is not suitable for a low voltage opamp. and 515 mV ± 3 mV for temperature variation from 27 to 125°C as shown in Figure 2.

This also helps to maximize the PSRR of the circuit.24%. The output impedance of the current source is improved by using cascade configuration. R2a and R2b.3 – Low Voltage BGR as presented by [6] The voltage at the nodes Va and Vb is now 150 mV – 200 mV due to the resistive divider network of R1a.Figure 2. Figure 2.4.4 – Generated reference voltage versus temperature using a 0.5 V (dashed curve supply voltage) [6] 18 .95 V (solid curve) and a 1. The simulation results are shown in Figure 2. The TC variation was observed to be less than 0. R1b.

6 below shows the temperature dependence of the bandgap output.3 CURRENT SUMMING AND A VOLTAGE SUMMING CIRCUITS Ripamonti [7] talks about two different configurations capable of sub-1 V supply voltage BGR circuits. A major drawback of the circuit is its extremely low PSRR. The second block produces current CTAT. Figure 2.9 V. which are 0.5 – Current Summing BGR [7] The circuit is divided into three sub-blocks. Figure 2. The first technique operates by summing two currents with opposite temperature dependence on a resistor. The major advantage of the circuit is that the supply voltage here is the addition of the drop across the forward biased diode and the VDS of the transistor. 19 .2 V respectively. and the resistor value further controls the reference voltage. where resistive voltage dividers are used for the determination of the attenuation factor. Thus the supply voltage can be as low as 0.2.7 V and 0. The first generates current PTAT by using the MOS operating in the sub threshold region. The third block is a resistor where both the currents are added. The circuit that sums two currents is given in Figure 2. The second technique sums two voltages that are first attenuated.5.

20 .Figure 2. The only difference between the current summing BGR and the voltage summing BGR is the third sub-circuit. The second path’s minimum supply voltage is a VBE plus the minimum voltage of the current source plus the output voltage of the VBE generator.7 is also composed of three sub circuits. The applied diode voltage is not the full base-emitter voltage. The offset voltage from the use of unmatched bipolar transistors generates the PTAT component. This value is equal to 1 V with the technology that was used in this study. The third section is composed of a differential amplifier in a non-inverting feedback loop. plus the source to drain voltage of the current source. but a fraction. as in a standard BGR. The minimum supply voltage of one path is VT plus a VCEsat.6 – Temperature Variation of the BGR in the current summing circuit [7] The voltage summing BGR in Figure 2.

7 – Voltage Summing BGR [7] Variations in reference voltage with supply voltage and temperature are plotted in Figure 2.8 a) VREF vs. In the same range the temperature dependence varied by 2%. Vdd b) VREF vs.5% over the 0.Figure 2. Figure 2.8. The output voltage was found to vary by less than 0. Temperature [7] 21 .9 V to 2.5 V range.

Jiang [8] proposes another improvement to the circuit described by Banba [5]. R2. Figure 2.2) Here A1 and A2 are the areas of transistors Q1 and Q2 respectively. This technique is based on the use of a Transimpedance amplifier. The value of Vref can be changed by choosing different values of R1.2. 22 .10.9. and R3. as depicted in Figure 2. The measured VREF is shown in Figure 2.4 TRANSIMPEDANCE AMPLIFIER The conventional BGR circuit is limited by the input common mode range of the operational amplifier. They are used to obtain a PTAT current by sensing the voltage difference and the current is summed with a current complementary to VEB to obtain the reference voltage. Here resistors are used in place of input differential stage of the opamp.9 – Transimpedance Amplifier using BGR [8] The value of VREF here is given by V REF = R3 A V V 1 VT ln 1 + BE − B A2 R2 R2 R1 (2.

10.Figure 2.Measured VREF characteristics without trimming [8] 23 .

a cross-section is shown in Figure 2. The circuit consists of a folded cascode opamp and matched resistors with unequal value. but it is at the expense of area. low voltage BGR design through the use of dynamic threshold MOS (DTMOS) devices.11 – DTMOS Cross-section [9] A DTMOS BGR can be designed using the same topology as a standard CMOS BGR. As we have seen.12 demonstrates such a circuit.5 DYNAMIC THRESHOLD MOS (DTMOS) Annema [9] talks about another method of low power. which allows operation at low 24 .2. The use of a P-DTMOS device results in a VG0 of 0. This method can be implemented by replacing the normal diodes with MOS diodes that have interconnected gates and back gates.6 V and the temperature gradient of VGS is approximately –1 mV/°K. The electrostatic field lowers the bandgap. Figure 2. These devices are DTMOS devices. The bandgap can also be made to appear smaller if the junction is in the presence of an electrostatic field. The input stage also utilizes DTMOS transistors.11. Figure 2. These values are half the typical values of a standard BGR. the bandgap for low power applications can be made to appear smaller through resistive subdivision. The DTMOS diodes are shown with the gate-substrate connection.

20°C to 100°C. Figure 2.5 mV. Figure 2.7 V.13. The variation over the range. is just 4. uses a low voltage current mirror.13 – VREF v/s temperature [9] 25 . Correct operation of this opamp was verified for supply voltages down to 0.supply voltages. shaded. The opamp’s output stage.12 – Low Voltage DTMOS BGR [9] The circuit’s temperature dependence is shown in Figure 2.

9 V there is no longer enough loop gain to keep the BGR at correct bias point.14. Figure 2.2. Thus the circuit cannot be fabricated in regular low cost CMOS technologies that usually do not have these special devices. A diode-connected PMOS transistor loads the second gain stage. The bias current is reduced to a few nanoamps at a supply voltage of 1 V.6 DEPLETION TRANSISTORS Pierazzi [10] made opamp that used PMOS in the depletion mode in order to cope with the supply voltage reduction. Thus.15 below the supply voltage of 0. As seen from Figure 2. 26 . the biasing of the opamp is derived from the output voltage and thus this maximizes the PSRR of the whole opamp but at the cost of low voltage gain.4 V. Below this voltage the transistors drop into a weak inversion.14 – OpAmp using transistors in depletion mode [10] The input transistors work in strong inversion at a supply voltage of around 1. This opamp uses PMOS in the weak inversion and is shown in Figure 2.

9 V.16 .Measured VREF vs supply voltage for various temperatures [10] 27 . The measurements suggest a minimum supply voltage of 0. BG1 is the curve of our interest. The measured VREF vs supply voltage for various temperatures is shown in Figure 2.15 . [10] The BGR was implemented in 0.Figure 2.Simulated output voltages at 27ºC at different supply voltages.35 µm CMOS technology.16. Figure 2.

17 Threshold Voltage BGR Concept [11] The simulation results for the circuit made with this technique are shown in Figure 2. Figure 2.17.2. both having a CTAT dependency. but at the cost of more area and complexity.18 – Simulated BGR Output [11] 28 .18. The performance of the proposed BGR is shown to be comparable to bandgap circuits. This concept is pictorially shown in Figure 2. Figure – 2.7 THRESHOLD VOLTAGE BASED CIRCUIT Ytterdal [11] introduces the new concept of threshold voltage based voltage references. The basic idea here is to compensate the temperature dependency of the threshold voltage of a PMOS transistor with that of an NMOS transistor.

minimum number of critical components that need to be matched and usage of resistor arrays that are a multiple of a single resistance value.Zero TC point [17] d) The using of two equal resistors meeting at Vbg to generate a stiff Vbe voltage source as shown in Figure 2.20. 29 .21.8 BANDGAP USING TWO VBE SOURCES The work by Washburn [17] was driven by the motivation of developing a low voltage bandgap reference circuit having low power consumption. c) If CTAT and PTAT voltages are connected as shown in Figure 2.19 .2. b) The voltage source like behavior of the multiplied PTAT voltage when dropped across a resistor having a impedance equal to that of the resistor value. no dependence on TC of resistors. This is conceptually explained in Figure 2. Figure 2. The work in [17] exhibits a series of attainable circuit behaviors as discussed below: a) The ability to multiply PTAT voltage to get it to be almost equal to the CTAT voltage near the center of the desired operating temperature range.19 then the value of the resistor on the CTAT side can be chosen in a way to have near zero TC at the junction of the two resistors.

21 .Figure 2.Zero TC with two Vbe sources [17] 30 .20 – Low voltage bandgap using two Vbe sources [17] Figure 2.

1 V in 90 nm technologies.22 below. The headroom is limited by the mirrors. The Vbe (CTAT voltage) does not impose a limit on the voltage headroom. 31 . Figure 2.22 .7 V depending upon the point of cancellation.Combining Vbe Resistors [17] The proposed architecture removes the additional current path present in conventional BGR. So the supply voltage required is just above the output voltage Vbg.6 to 0. So according to [17] the minimum supply voltage depends upon the headroom needed for the mirrors to operate which is around 0. The output voltage is almost independent of the resistor TC’s and absolute value tolerances.The resulting output voltage is Vbg = 0. [17] proposes a new resistor scheme where the resistors will be in the form of series and parallel stripes of a single resistor as shown conceptually in Figure 2.

This gives an overall idea on the performance of the individual circuit compared to the others in areas like technology used.1 V 515 mV ±59 ppm/ºC . ppm accuracy and the PSRR in dB.6 m CMOS 44dB at 10KHz Current Summing (Ripamonti) Transimpedance Amplifier (Jiang) DTMOS (Annema) Not Mentioned Low 1.35 m CMOS 1. output voltage.2 m CMOS 0. 2.9V 521mv Mentioned in ppm.95 V 720 mV mentioned in ppm.100 ppm/˚C 57 ppm/˚C Mentioned 0. Table 1 below compares the results from all the discussed works.24%. Circuit type Technology Min.2 V 1000 mV 20dB at 1KHZ Not Mentioned 0.85 V 650 mV 32 . +/.4%. All of them have their own advantages and drawbacks. minimum supply voltage.9 LOW VOLTAGE BGR COMPARISON The work done on low supply voltage bandgap references was discussed in this chapter. Not 0.4 µm CMOS 2. Supply Voltage (V) Output Voltage (V) Accuracy (ppm/ºC) PSRR (dB) Not Resistor Divider (Banba) Resistor Divider (Waltari) 0. Not 0.2.

Depletion Transistors (Peirazzi) Threshold Voltage Based (Ytterdal) 0.9 V 510 mV Not Mentioned Not Mentioned 0.35µm CMOS 0.13 µm Digital CMOS 0.55 V 400 mV 93 ppm/ºC Not Mentioned Table 1 – Comparison of Low Voltage bandgap references 33 .

1 PROPOSED LOW SUPPLY BANDGAP REFERENCE CIRCUIT The proposed bandgap reference architecture is motivated by the requirement of a low supply voltage bandgap reference.3 3.2 CTAT Current Generation CTAT Voltage Generation at the base of current mirror transistors Bandgap output Voltage 3.1 3.1 PTAT Current Generation 3. The circuit can be represented in simplest form as shown below in Figure 3.4 _________________________________ 3.2 Proposed Low supply Bandgap Reference circuit Operation 3. 34 .3.2.1.2.

Proposed bandgap reference in the simplest form Briefly. The diode-connected BJT makes a conventional CTAT current flow through the resistor combination R2 and R3. 35 . the working of the circuit can be explained as the summation of two currents (one PTAT and the other CTAT) across the resistor R3.Figure 3. This voltage at the gate of M2 and the combination of the PMOS with a P+ poly resistor R1 produces a PTAT current flowing through the combination R1 and R3. The two diode connected transistors M3 and M4 are used for biasing. The voltage at the gate of the transistors in the current mirror is of CTAT type.1 .

# 1 2 3 4 5 6 7 Part # M1 M2 M3 M4 R1 R2 R3 Type PMOS PMOS PMOS NMOS P+ Poly Resistor P+ Ploy Silicided resistor Metal 1 Resistor Value W = 45 µm. The parametric values of the various components used in the circuit are mentioned in Table 2 below. L = 180 nm W = 900 nm.46 K Table 2 – Component parameters of the proposed circuit 36 . L = 180 nm 29. L = 180 nm W = 8 µm. L = 270 nm W = 1 µm.92 K 7. R1 is P+ Poly resistor with a negative temperature coefficient. Sr.18 micron CMOS process.The circuit is designed using the LSI Logic 0. R2 is a P+ Poly Silicided resistor with a positive temperature coefficient and R3 is a Metal 1 resistor with a positive temperature coefficient. Here the resistors used are all different from each other.4 K 16.

1 PTAT Current Generation The most conventional way of making the PTAT quantity is using the difference in the Vbe’s of two PN junctions having different current densities. 3. The first part will explain the generation of the PTAT current and the second will explain the generation of the CTAT current. a new technique is used to get the PTAT current.2. Figure 3.2 – Circuit for PTAT current generation 37 .2 OPERATION The operation of the circuit will be studied by dividing it into three simpler parts.3. Here.2 below shows the circuit that generates the PTAT current. The third will explain the PTAT nature of the gate voltage of the current mirror transistors M1 & M2. Figure 3. But this technique needs an operational amplifier to magnify the slope of the delta Vbe.

In the figure above the current in the resistors is given by the square law equation ID = 1 ' W (VGS − VT )2 Kp 2 L (3. Temperature appears explicitly in the value of surface mobility for the MOSFET model.2) ∴ ∂µ 0 2 VGS + VT2 − 2VGS VT ∂T ( ) + µ0 ∂ 2 VGS + VT2 − 2VGS VT ∂T (3. They are ∂µ 0 ∂VGS ∂VT .4) In the above equation (4). ∴ID = ∂I D 1 W = C OX ∂T 2 L 1 W 2 Kp VGS + VT2 − 2VGS VT 2 L ( ) ( ) (3.3) ∴ ∂I D 1 W = C OX ∂T 2 L ∂µ 0 ∂VGS ∂VT 2 VGS + VT2 − 2VGS VT + 2 µ 0 (VGS − VT ) − ∂T ∂T ∂T ( ) (3. 38 . ∂T ∂T ∂T µ 0 is the mobility of the carriers. & .1) where Kp = µ 0COX for the transistor M2 & VT is the threshold voltage of the transistor. The temperature dependence for the mobility as explained in [14] is determined by: µ 0 (T ) = µ 0 (T0 ) T T0 1.5) Thus the mobility decreases with the increase in temperature.5 (3. there are three parameters that will decide the nature of the current versus temperature.

4 below. ∂T ∂VT here has a slope of about -65 µV/°C as seen from simulation results for this specific ∂T transistor size and similar biasing.3 and 3. The variation of the current and output PTAT voltage across temperature is shown in Figures 3. ∂VGS ∂VT − ∂T ∂T is around 460 µV/°C and Figure 3.∂VGS has a slope of around 393.09 µV/°C. Thus the value of has a PTAT nature. The variation of mobility with temperature is much smaller when compared to that of (VGSVT) and thus the current has a PTAT nature. This would be derived in a later section.3 – PTAT current 39 .

Figure 3. 4 – PTAT voltage drop across the output resistor 40 .

the resistor divider network of R2 and R3 helps in reducing the slope of the CTAT voltage across R3 more.5 – Variation of PN junction voltage with temperature This variation is too large compared to that of the PTAT current across the output resistor R3.812 mV/°C. This reduces the slope of the Vbe temperature dependence and thus the voltage is a little less CTAT than before. The variation of the Vbe of the VPNP BJT with respect to temperature is shown in Figure 3.2. the voltage varies about 253. Here the Vbe of the vertical PNP that is present in the technology is used. This is reduced in its value by allowing a PTAT VGS for the current mirror transistor M1.625 mV for the temperature range of -20°C to 120°C at a slope of -1. Additionally. As seen from the Figure 3.5 below. 41 .5.2 CTAT Current Generation The most conventional technique for generating the CTAT (voltage/current) is through the use of Vbe of the BJT. Figure 3.3.

Figure 3. Here.6 – Circuit generating CTAT quantity Neglecting the base current for the BJT we have.The circuit generating the CTAT quantity is shown in Figure 3. µ n is the average electron mobility in the base. the constants B and B’ involve only temperature-independent quantities.7) Here ni is the intrinsic minority carrier concentration. VBE = Vthermal ln I BJT IS (3. QB is the total base doping per unit area. A is the emitter base junction area and T is the temperature. 42 .6 below.6) where Vthermal is the thermal voltage and IS is the saturation current which can be related to the device structure by IS = qAni2 Dn = Bni2 Dn = B ' i2Tµ n n QB (3.

E & G are temperature independent quantities.5). the current IBJT varies with temperature. (3.5. ∂V BE ∂ [Vthermal (α − γ ) ln T + Vthermal ln(EG )] = ∂T ∂T (α − γ )Vthermal ∂Vthermal ∂V ∂V ∴ BE = thermal (α − γ ) ln T + + ln (EG ) ∂T ∂T T ∂T (3.The quantities that are temperature dependent are given by µ n = CT − n ni2 = DT 3 exp − VG 0 Vthermal (3.9) E is another temperature independent constant and = 4 – n For our circuit.5 as shown in equation (3.12) 43 .11) In the above equation VG0. V BE = VG 0 − Vthermal [(γ − α ) ln T − ln (EG )] (3. C and D are temperature-independent quantities. We assume for the time being that the temperature variation is known and that it can be written in the form I BJT = GT α (3. Combining the above four equations yields V BE = Vthermal ln I BJT T −γ E exp VG 0 Vthermal 2.8) Here VG0 is the bandgap voltage of silicon extrapolated to 0°K and the value of n is approximately 1.10) Here G is another temperature-independent constant.

∂Vthermal can be calculated as shown below.14) Thus the resulting value of ∂VBE is CTAT in nature. This slope of Vbe is exactly enough to cancel the PTAT-natured slope of the current produced by the transistor M2 across the same output resistor. The value of the Vbe drop across the ∂T output resistor R3 across temperature is shown in Figure 3. 44 . ∂Vthermal ∂ kT k = = = 8.( – ) has a value of approximately -2. T is absolute temperature and q is electronic charge.62 x 10-5 V/°K.13) Here k is Boltzmann' constant. ∂T ∂T q q (3.7 below. Thus we s have. ∂T Vthermal = kT q (3.

Figure 3.8 – Voltage drop across output resistor due to the CTAT generation circuit 45 .Figure 3.7 below shows the current through the resistor network Figure 3.8 below shows the voltage drop across the output resistor caused by the CTAT generation circuit.7 – Current through the resistor network Figure 3.

Figure 3. The biasing circuit is shown in Figure 3.3 CTAT VOLTAGE GENERATION AT THE BASE OF CURRENT MIRROR TRANSISTORS The CTAT voltage (i. the PTAT Vgs for PMOS) is generated by the biasing circuit which consists of two diode-connected transistors M3 and M4.9 – Biasing Circuit 46 .9 below.e.3..

∂T Here.The output here can be given as VOUT = V DD × 1 g mn (3. gmn > gmp as the transconductance for NMOS is greater than PMOS if they are similarly sized. ∴VOUT = V DD . The transconductance can be calculated as gm = ∂I D .19) 47 . Here. ∂VGS (3.15) 1 1 + g mn g mp where gmp and gmn are tranconductances of the PMOS and the NMOS transistors respectively.17) For the sake of derivation we will assume that ∂g mp ∂T ∂g mn ∂g m = . since NMOS is much larger than PMOS we surely have gmn > gmp.16) ∴ ∂VOUT = VDD ∂T ∂g mp ∂T × g mp 1 − + g mn (g g mp mp + g mn ) = 2 × ∂g mp ∂T + ∂g mn ∂T (3. ∂T ∂T (3.g mp g mp + g mn (3.18) ∴ ∂VOUT ∂g V DD = × m × (g mn − g mp ) 2 ∂T (g mp + g mn ) ∂T In the above equation the two terms that will decide the nature of the output are ∂g m and (g mp − g mn ).

The variation of the output with respect to temperature is shown in Figure 3. This change in gm is more than that of (gmn – gmp).Temperature dependency of gm can be defined as g m (T ) = k (T ) × (VGS − VT (T )) . Thus the overall value of gm reduces with the increase in temperature.10 – Output from the biasing circuit 48 .20) As discussed earlier both Vth and k decrease with the rise in temperature. (3. But the effect of k (T) is more than that of Vth (T). and thus the output is of CTAT in nature.10 below Figure 3.

49 . The BJT was using 60 µA of the total current consumed.22) ∴VOUT = VBE + I 2 R3 R1 + R2 Using the above relation a desired value for Vout can be obtained by iterating the values of R1.4 BANDGAP OUTPUT The output of the circuit can be calculated by using the current in the two branches. R2 and R3.Bandgap output for a particular combination of resistors Depending on the need of the application the value of the bandgap output voltage can be changed using different combination of resistors.11 below. The output of a particular configuration of the resistors is shown in the Figure 3. Figure 3.11 .3. If we assume the currents in the two branches to be I1 and I2 then the voltage Vout can be defined as VOUT = (I 1 + I 2 )R3 (3.21) (3. The current consumption is this case was 96µA. 5 µA of current was unaccounted for in the simulation and is assumed to be the leakage current of the BJT.

3 4.1 4. The circuit exhibits a very low PSRR. The bandgap reference circuit explained in the previous section varies only 900 µV over a temperature variation from -20°C to 120°C.2 4.4 _________________________________ 4.4.1 below shows bandgap voltage variation over the supply voltage variation from 950 mV to 1050 mV. The Figure 4. 50 .1 VERSIONS OF THE BANDGAP REFERENCE This section will discuss two different architectures of the bandgap reference circuit Versions of the Bandgap Reference Circuit Variation # 1 Circuit Variation # 2 Comparison Chart explained in the previous section.

1 – Voltage supply variation of the basic BGR circuit The PSRR of the circuit can be calculated by the equation PSRR = 20 log ∆VPOWER − SUPPLY in dB ∆VBANDGAP −OUTPUT 100mV = 7.Figure 4. The advantage of this configuration is that it has an accuracy of 21 ppm/ºC. This is very small as generally a good bandgap reference circuit should have a PSRR of about 20 dB.2) This circuit as shown in the figure above has a PSRR of about 7.5 dB.1) PSRR = 20 log (4.077 mV (4. 51 .5191db 42.

Two variants of the basic bandgap reference circuit will be discussed in this section. The first one supports a wider range on the bandgap voltage reference with an improved PSRR. The other circuit supports only a very low (up to 200 mV) bandgap reference output voltage but has a very good PSRR as compared to the other two circuits. 52 . Both of the circuits have a better PSRR than the present circuit.

Whereas the CTAT generating BJT is shielded from the power supply through the current mirror transistor.2 keeps the most of the configuration of the original circuit. So any variation in the power supply directly affects the output of the circuit.4.2 – Circuit Variation # 1 53 . In this variation of the circuit the PTAT generating MOS is connected to a less variable voltage as generated by the bias circuit.CIRCUIT VARIATION # 1 This circuit as shown in Figure 4.2 . The basic PSRR issue in the original circuit was the fact that the PTAT generating PMOS transistor is directly connected to the power supply. Figure 4.

3 is known as threshold voltage self biasing. This would make the voltage drop across the resistor R4 to be independent of supply voltage and will thus depend only on temperature. The idea here is to get the current in the transistor M5 to be almost independent of supply voltage variations. Figure 4.3) 54 .3 – Threshold voltage self biasing If we neglect the body effects and the channel length modulation effects then we can define the drop across the resistor as VR 4 = VGS 8 =V THN + 2I R 4 (W / L )5 COX I R4 = VGS 8 VTHN ≈ R R (If (W/L)5COX is large) (4.The biasing method used here as shown in Figure 4.

But in this case the supply voltage has a PTAT nature as shown in Figure 4. The PTAT generating PMOS is provided with a power supply by a point on the bias circuit shown as the “Dummy Supply”. The biasing for the start-up circuit is provided by two diode-connected transistors as shown in the figure. The CTAT nature of this voltage is very important to the functionality of the circuit as explained in the previous section. this is not true due to the finite output resistance of the MOSFET’s. In practice. Note also that threshold voltage’s TC and the resistor’s TC determine the circuit’s temperature dependency. 55 . Consequently. The circuit will not be affected by the PVT variations involving this two transistor biasing circuit. which could vary 20%.This result implies that current IR4 will be independent of supply voltage. The startup of the bias circuit is taken care of by the transistor M9 to avoid the zero current initial condition. the threshold voltage self-biasing technique provides a current with a large negative temperature coefficient.4 below. This in the original circuit was done by the two diode connected transistors making up the biasing circuit. The accuracy of current IR4 is determined by the threshold voltage accuracy and the resistor accuracy. The temperature coefficient of the resistor is positive while that of the threshold voltage is negative. The characteristic needed in the supply is that it should vary very little with temperature and with actual supply voltage variation.

Figure 4.Figure 4. The variation of this voltage over 100 mV supply voltage variation is about 50 mV and thus the circuit exhibits a better PSRR compared to the original circuit.4 – Supply Voltage for the PTAT generating part of the circuit This PTAT nature of the supply voltage results in a PTAT VGS for the transistor. This PTAT VGS generates a PTAT current as explained in the previous chapter.5 – Variation of Output voltage with 100 mV supply voltage variation 56 .

The accuracy of the circuit as shown in Figure 4. This causes a reduction in accuracy over the temperature range. The current consumed by this configuration was 114 µA. Figure 4. The variation for this version is around 5 mV over the temperature range of -20 °C to 80 °C as shown in Figure 4.6 – Performance over temperature 57 .5) The improvement in the PSRR comes only at the cost of bandgap voltage range and accuracy over temperature. The cancellation of the PTAT and the CTAT quantities is also affected.6 below.4) PSRR = 20 log (4.6 below is about 96 ppm/ºC which is low as compared to the original circuit. The dummy supply voltage used here reduces the bandgap voltage range considerably. In the original circuit the output varies only about 900 µV over a temperature range of -20 °C to 120 °C.The PSRR of the circuit can be calculated by the equation PSRR = 20 log ∆VPOWER − SUPPLY in dB ∆VBANDGAP −OUTPUT 100mV = 8.5269db 37.4672mV (4.

3 . This improvement in PSRR comes at the cost of lack of range in the output for the bandgap reference circuit. The circuit configuration is shown in Figure 4.7 – Circuit variation # 2 58 .4.7 below. Figure 4.CIRCUIT VARIATION # 2 This variation of the circuit offers a significantly improved PSRR compared to the other two variations.

Figure 4.6) PSRR = 20 log (4.8 .2db 4. Figure 4. The only difference is that the PTAT generation circuit here uses a NMOS transistor in the source follower configuration.8 below shows the output voltage over supply voltage variation of 100 mV.3675mV (4. It is only usable up to 250 mV.7) 59 .This variation of the original circuit is essentially the same as the first one.PSRR of Circuit Variation # 2 The PSRR of the circuit can be calculated by the equation PSRR = 20 log ∆VPOWER − SUPPLY in dB ∆VBANDGAP −OUTPUT 100mV = 27. The advantage of this circuit is that the PSRR is very good but the major disadvantage of this configuration is the range of the output voltage.

2 dB is very good for a bandgap reference circuit.9 – Bandgap output voltage 60 .9 below. The current consumed by this configuration was 110 µA. The other advantage of the circuit is the accuracy over temperature of about 38 ppm/ºC. The TC cancellation for this configuration is better than that in circuit variation #1. Figure 4.The PSRR of 27. The variation of the bandgap output voltage over the temperature range of -20 °C to 80 °C is shown in Figure 4.

4. Parameter Proposed Circuit Circuit Variation –I Circuit Variation .2 dB N/A Table – 3 Comparison between the three variations 61 . As seen from the table every configuration has its own advantages and disadvantages when compared to each other or to the good bandgap reference circuit. The good bandgap reference circuit considered here is the one by Banba [5].COMPARISON CHART Table 3 below shows a parametric comparison between the three variations of the bandgap circuit to a good bandgap reference circuit.II Popular BGR Circuit Bandgap Output Voltage Output Voltage Range Precision (ppm/ºC) PSRR (dB) 302 mV 460 mV 155 mV 515 mV 200 mV to 600 mV 200 mV to 500 mV 100 mV to 250 mV N/A 21 ppm/ºC 96 ppm/ºC 38 ppm/ºC ±59 ppm/ºC 7.5 dB 8.5269 dB 27.4 .

The process variations in the size of the current mirror transistors can result in the alteration of the current that they mirror and thus affect the output voltage of the circuit.5.1 Process Variations and Transient Response 5.1 PROCESS VARIATIONS AND TRANSIENT RESPONSE This section will discuss about techniques to protect the circuit from resistor and transistor process variations and the response of the circuit versus time.1 Process Variations The variations in the resistors and the transistors affect the circuit in this case. The process variation remedies are explained for the original circuit.2 Transient Analysis _________________________________ 5. Similar remedies can also be applied to the circuit variations as well. The variation in the absolute value of the resistors also affects the circuit as the output voltage relies heavily on the ratio of 62 .1.1 Process Variations 5. 5.1.1.

A digital trim [16] as shown in Figure 5. The limitation of this technique is that the technology should support Electrically Erasable Programmable Read Only Memory (EEPROM). If the current is too low then all the switches are closed and if it is perfect then none are closed. 63 . The EEPROM is written with the appropriate bits through a digital bus. For this circuit 8 trim bits have been used. The current in the output branch is monitored and accordingly the switches on the transistors are controlled. The first four bits B0 – B3 stored in the EEPROM are devoted for transistor trim.the resistors.1 is used here to get the exact resistor and transistor value required.

1 – The Resistor and transistor trim configuration for the original circuit 64 .Figure 5.

extra width for transistor and extra series resistance can be added to trim them to the exact value. Series resistance of 2 K can be added in series to the output resistance. As seen from the above discussion. 65 . Thus here care is taken that the resistor always comes out either exactly the same or less than the desired value. The value of the resistor is monitored by external tests and the value is trimmed with the help of the resistor trim bits. But if the final value of the resistor is more than what is needed then the resistance cannot be removed to come to the exact value. The same care is taken for the transistors as well.Bits B4 – B7 are devoted for the resistor trim.

5. Figure 5. This makes sense as if we look at the circuit: there is no initial condition requirement and it is safe to assume that the BJT and the PMOS’s will start in saturation region. These startup circuits insure that the additional circuitry added to the original circuit starts up as we want it to. The transient analysis of the circuit shows that it does not need any startup circuit. 66 .1.2 below. The transient response of the original circuit is shown in Figure 5. The transient response of circuit variation # 1 which uses PMOS in the output branch which is powered not by the power supply but by a point in the additional circuitry added is shown in Figure 5.2 – Transient response of the original circuit The two variations of the circuits are provided with startup circuits as explained in the previous section.2 Transient Analysis The original circuit does not have any startup circuit.3 below.

Figure 5. This variation uses an NMOS connected in the source follower configuration in the output branch. The transient response of the circuit is shown in Figure 5.3 – Transient response for Circuit Variation # 1 The circuit variation # 2 also has a start up circuit as mentioned in the previous section.4 – Transient response for Circuit Variation # 2 67 .4 below.Figure 5.

Both the currents were summed across a resistor to make a near-zero temperature coefficient voltage reference. This new architecture used the current of a BJT to make the conventional CTAT. 68 .CONCLUSION AND FUTURE WORK The goal of this work was to develop a new sub-1 V bandgap reference topology without the use of any special devices. A digital trimming scheme using EE-PROM was proposed to cope with the process variations in the resistors and transistors. These variations have output voltage of 460 mV and 155 mV with and accuracy of 96 ppm/ºC and 38 ppm/ºC respectively. A new topology for bandgap reference was developed which did not use an operational amplifier as used in the conventional circuits.53 dB and 27. mainly with sub-1V technologies. Two variations of this circuit were introduced to improve on the poor PSRR (7.2 dB respectively. They have PSRR’s of 8. The PTAT was generated with a PMOS (having PTAT VGS as its gate) and a P+ Poly resistor. The simulation results show a bandgap output voltage of 302 mV with and accuracy of 21 ppm/ºC.5 dB) of the proposed circuit. In this work effort is made to understand various topologies of the existing bandgap reference circuits and identify the limitations which make these circuits difficult to use with current processes.

Future Work The future work will include developing a master circuit which will have all the advantages of the three variations of the circuit proposed in this work. This master circuit will have a good output voltage range. good precision and a very high PSRR. The EE-PROM based digital trimming may not be feasible in all the technologies. 69 . Alternative approaches not using an EE-PROM need to be developed.

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