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Converters
Michael Douglas Seeman
Electrical Engineering and Computer Sciences
University of California at Berkeley
Technical Report No. UCB/EECS200978
http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS200978.html
May 21, 2009
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4. TITLE AND SUBTITLE
A Design Methodology for SwitchedCapacitor DCDC Converters
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13. SUPPLEMENTARY NOTES
14. ABSTRACT
Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power con verters that use a
network of switches and capacitors to e ciently convert one voltage to another. Unlike traditional
inductorbased DCDC converters, SC converters do not rely on magnetic energy storage. This fact makes
SC converters ideal for integrated implementa tions, as common integrated inductors are not yet suitable
for power electronic applications. While they are only capable of a nite number of conversion ratios, SC
converters can sup port a higher power density compared with traditional converters for a given
conversion ratio. Finally, through simple control methods, regulation over many magnitudes of output
power is possible while maintaining high e ciency. A complete, detailed methodology for SC converter
analysis, optimization and imple mentation is derived. These methods specify device choices and sizing for
each capacitor and switch in the circuit, along with the relative sizing between switches and capacitors.
This method is advantageous over previouslydeveloped analysis methods because of its simplicity and the
intuition it lends towards the design of SC converters. The strengths and weaknesses of numerous
topologies are compared amongst themselves and with magneticsbased converters. These methods are
incorporated into a MATLAB tool for converter design. This design methodology is applied to three varied
applications for SC converters. First a highvoltage hybrid converter for an autonomous micro air vehicle
is described. This converter, weighing less than 150mg, creates a supply of 200V from a single lithiumion
cell (3.7V) to supply the aircraft’s actuators. Second, a powermanagement integrated circuit (IC) is
presented for a wireless sensor node. This IC, with a target quiescent current of 1 A supplies the system
voltages of the PicoCube wireless sensor node. Finally, the initial design of a highcurrentdensity SC
voltage regulator is presented for lowfootprint microprocessor applications.
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Acknowledgement
The work in sections 5.2 and 5.4 was partially performed while at an
internship at Intel during SeptemberDecember, 2008.
The Microglider project was funded by the NSF under Grant No. IIS
0412541 and by DARPA fund #FA865005C7138.
The PicoCube project was supported by the NSF Infrastructure Grant No.
0403427 and the California Energy Commission Award DR0301. I also
thank STMicroelectronics for complimentary CMOS fabrication and those at
the Berkeley Wireless Research Center.
A Design Methodology for SwitchedCapacitor DCDC Converters
by
Michael Douglas Seeman
S.B. (Massachusetts Institute of Technology) 2004
M.S. (University of California, Berkeley) 2006
A dissertation submitted in partial satisfaction
of the requirements for the degree of
Doctor of Philosophy
in
Engineering – Electrical Engineeing and Computer Sciences
in the
GRADUATE DIVISION
of the
UNIVERSITY OF CALIFORNIA, BERKELEY
Committee in charge:
Professor Seth R. Sanders, Chair
Professor Elad Alon
Professor Paul Wright
Spring 2009
A Design Methodology for SwitchedCapacitor DCDC Converters
Copyright c 2009
by
Michael Douglas Seeman
Abstract
A Design Methodology for SwitchedCapacitor DCDC Converters
by
Michael Douglas Seeman
Doctor of Philosophy in Engineering – Electrical Engineeing and Computer Sciences
University of California, Berkeley
Professor Seth R. Sanders, Chair
Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power con
verters that use a network of switches and capacitors to eﬃciently convert one voltage to
another. Unlike traditional inductorbased DCDC converters, SC converters do not rely on
magnetic energy storage. This fact makes SC converters ideal for integrated implementa
tions, as common integrated inductors are not yet suitable for power electronic applications.
While they are only capable of a ﬁnite number of conversion ratios, SC converters can sup
port a higher power density compared with traditional converters for a given conversion
ratio. Finally, through simple control methods, regulation over many magnitudes of output
power is possible while maintaining high eﬃciency.
A complete, detailed methodology for SC converter analysis, optimization and imple
mentation is derived. These methods specify device choices and sizing for each capacitor
and switch in the circuit, along with the relative sizing between switches and capacitors.
This method is advantageous over previouslydeveloped analysis methods because of its
simplicity and the intuition it lends towards the design of SC converters. The strengths and
weaknesses of numerous topologies are compared amongst themselves and with magnetics
1
based converters. These methods are incorporated into a MATLAB tool for converter
design.
This design methodology is applied to three varied applications for SC converters. First,
a highvoltage hybrid converter for an autonomous micro air vehicle is described. This
converter, weighing less than 150mg, creates a supply of 200V from a single lithiumion cell
(3.7V) to supply the aircraft’s actuators. Second, a powermanagement integrated circuit
(IC) is presented for a wireless sensor node. This IC, with a target quiescent current of 1 µA,
supplies the system voltages of the PicoCube wireless sensor node. Finally, the initial design
of a highcurrentdensity SC voltage regulator is presented for lowfootprint microprocessor
applications.
Professor Seth R. Sanders
Dissertation Committee Chair
2
Contents
Contents i
List of Figures v
List of Tables viii
Acknowledgments ix
1 Introduction 1
1.1 SwitchedCapacitor Converters in Industry and
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 SwitchedCapacitor Converter Structure and Terminology . . . . . . . . . . 2
1.3 Preexisting SwitchedCapacitor Converter Analysis . . . . . . . . . . . . . 6
1.4 Developments in This Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Fundamental Analysis of SwitchedCapacitor Converters 10
2.1 SlowSwitching Limit Impedance . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Extension to NonLinear Capacitors . . . . . . . . . . . . . . . . . . 16
2.2 FastSwitching Limit Impedance . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Calculating Total Output Impedance . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Model Simpliﬁcation for TwoPhase Converters . . . . . . . . . . . . . . . . 24
2.5 Modeling Other Converter Loads . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5.1 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2 CurrentSource Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.3 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
i
3 Optimization of SwitchedCapacitor Converters 31
3.1 Device Cost Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Component Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1 Capacitor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.2 Switch Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.3 Optimizing Using Other Metrics . . . . . . . . . . . . . . . . . . . . 38
3.3 SystemLevel Converter Optimization . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 Converter Loss Components . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.2 Numerical Optimization . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Comparing SwitchedCapacitor Topologies 48
4.1 Converter Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Analysis of SC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.1 Ladder Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.2 Dickson Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.3 Fibonacci Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.4 SeriesParallel Topology . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.5 Doubler Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Comparison of SC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.1 Symmetrical Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4 Comparison with MagneticsBased Converters . . . . . . . . . . . . . . . . . 66
4.4.1 Switch Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.2 Reactive Element Comparison . . . . . . . . . . . . . . . . . . . . . 71
4.5 Fundamental Performance Limits . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5.1 SSL Converter Metric Limit . . . . . . . . . . . . . . . . . . . . . . . 76
4.5.2 FSL Converter Metric Limit . . . . . . . . . . . . . . . . . . . . . . . 78
5 Regulation of SwitchedCapacitor Converters 81
5.1 Output Ripple of Multiphase Converters . . . . . . . . . . . . . . . . . . . . 83
5.2 Hysteretic Feedback Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3 System Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4 A MultiRatio Converter for Portable Electronics . . . . . . . . . . . . . . . 93
5.4.1 Topology Description . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ii
5.4.2 Control Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6 HighVoltage Converters for Airborne Robotics 102
6.1 Comparison of Topologies for Lightweight HighVoltage DCDC Converters 103
6.1.1 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.2 Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1.3 Hybrid SwitchedCapacitor Boost Converter . . . . . . . . . . . . . . 112
6.2 MicroGlider Power Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7 SwitchedCapacitor Converters for Wireless Sensor Nodes 119
7.1 Application and IC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.2 Converter Architecture and Optimization . . . . . . . . . . . . . . . . . . . 123
7.3 Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.4 Synchronous Rectiﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.1 Impedance matching AC energy harvesters with diode rectiﬁers . . . 132
7.5 UltraLowPower Analog Circuits . . . . . . . . . . . . . . . . . . . . . . . . 134
7.6 System Eﬃciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
8 SwitchedCapacitor Converters for Microprocessors 142
8.1 Power Density vs. Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.2 Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
8.2.1 Dynamic Voltage Scaling Analysis . . . . . . . . . . . . . . . . . . . 147
8.2.2 Cell design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.3 Eﬃciency Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.3.1 Resonant Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8.3.2 Drain Charge Recovery . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.3.3 Reducing BottomPlate Capacitance . . . . . . . . . . . . . . . . . . 158
9 Conclusions 161
A NetworkTheoryBased Analysis for SwitchedCapacitor Converters 164
A.1 Summary of Circuit Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
A.2 Modeling SwitchedCapacitor Networks . . . . . . . . . . . . . . . . . . . . 167
A.2.1 Finding the Conversion Ratio and Component Voltages . . . . . . . 168
iii
A.2.2 Determining the Charge Multiplier Vector . . . . . . . . . . . . . . . 170
A.3 Criteria for ProperlyPosed SC Topologies . . . . . . . . . . . . . . . . . . . 176
A.4 Converter Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
A.4.1 Preparing the System . . . . . . . . . . . . . . . . . . . . . . . . . . 181
A.4.2 SinglePhase Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . 182
A.4.3 DiscreteTime Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
A.4.4 Dynamics Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
B MATLAB Package for SwitchedCapacitor Converter Design 190
B.1 Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
B.2 Visualization Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
B.3 Helper Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
B.4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
B.5 Code Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
B.5.1 evaluate loss.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
B.5.2 generate topology.m . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
B.5.3 implement topology.m . . . . . . . . . . . . . . . . . . . . . . . . . . 212
B.5.4 optimize loss.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
B.5.5 permute topologies.m . . . . . . . . . . . . . . . . . . . . . . . . . . 216
B.5.6 plot opt contour.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
B.5.7 plot regulation.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
B.5.8 techlib.m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Bibliography 225
Index 231
iv
List of Figures
1.1 An idealized 3port SC converter . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 A 3:1 ladder topology, including networks in (b) phase 1 and (c) phase 2 . . 4
1.3 Idealized 2port SC converter model . . . . . . . . . . . . . . . . . . . . . . 5
2.1 A 3:1 ladder topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Capacitor charge ﬂow in ladder converter. (a) phase 1 and (b) phase 2 . . . 12
2.3 Energy loss due to capacitor charging . . . . . . . . . . . . . . . . . . . . . 16
2.4 Nonlinear capacitor losses in a threephase converter . . . . . . . . . . . . . 17
2.5 Switch charge ﬂow in ladder converter: (a) phase 1 and (b) phase 2 . . . . . 19
2.6 Trivial SC converter used for dynamic analysis . . . . . . . . . . . . . . . . 22
2.7 Capacitor voltage waveform of trivial converter . . . . . . . . . . . . . . . . 22
2.8 Output impedance when R
SSL
≈ R
FSL
and approximations . . . . . . . . . 27
2.9 2:1 ladder converter: (a) topology (b) waveforms for current and voltage
source loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.10 SC converter with inductive load: a) phase 1 network, b) phase 2 network,
c) waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.11 Output impedance of SC converter with inductive load . . . . . . . . . . . . 30
3.1 Example SC converter optimization plot . . . . . . . . . . . . . . . . . . . . 45
3.2 Example eﬃciency contour plots of a 3:1 seriesparallel converter . . . . . . 46
4.1 Five common switchedcapacitor converter topologies in their stepup form 52
4.2 A 2:5 ladder topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 A 2:5 seriesparallel topology . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.4 Comparison of SSL and FSL converter metrics . . . . . . . . . . . . . . . . 63
4.5 Symmetric 2:5 ladder topology . . . . . . . . . . . . . . . . . . . . . . . . . 65
v
4.6 SSL metric improvement with symmetric converters . . . . . . . . . . . . . 66
4.7 Traditional magneticsbased converters . . . . . . . . . . . . . . . . . . . . . 67
4.8 FSL metrics for magneticsbased and SC converters . . . . . . . . . . . . . 70
4.9 SSL metrics for magneticsbased and SC converters . . . . . . . . . . . . . . 74
5.1 Eﬃciency during power backoﬀ; 2:1 converter . . . . . . . . . . . . . . . . . 83
5.2 Current transfer and output voltage ripple waveforms of a regulated four
phase 2:1 converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3 Output voltage ripple of an Ninterleavedphase 2:1 converter . . . . . . . . 87
5.4 Doublebound hysteresis feedback for the PicoCube application . . . . . . . 89
5.5 Lowerbound hysteretic feedback controller . . . . . . . . . . . . . . . . . . 90
5.6 Waveform from lowerbound feedbackbased converter . . . . . . . . . . . . 91
5.7 Idealized dynamics model for system modeling . . . . . . . . . . . . . . . . 92
5.8 {5, 6, 7, 8} : 7 ladder topology stage . . . . . . . . . . . . . . . . . . . . . . 94
5.9 3:1, 2:1 Dickson topology stage . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.10 Predicted eﬃciency of multiratio converter . . . . . . . . . . . . . . . . . . 97
5.11 Controller for the multiratio converter . . . . . . . . . . . . . . . . . . . . . 98
5.12 Operation regions for the multiratio converter . . . . . . . . . . . . . . . . 99
5.13 Output voltage and eﬃciency of the multiratio converter prototype . . . . 101
6.1 Three topologies for lightweight, highvoltage DCDC conversion . . . . . . 104
6.2 Available (a) capacitors by voltage and (b) inductors by current . . . . . . 106
6.3 Hybrid switchedcapacitor boost converter . . . . . . . . . . . . . . . . . . . 112
6.4 Photos of the MicroGlider and control PCB . . . . . . . . . . . . . . . . . . 117
6.5 Hybrid SC boost converter as appearing on the MicroGlider . . . . . . . . . 117
7.1 Photos and dimensions of the a) PicoCube and the b) electromechanical shaker120
7.2 Measurement and transmission power . . . . . . . . . . . . . . . . . . . . . 121
7.3 Block diagram of the converter IC . . . . . . . . . . . . . . . . . . . . . . . 122
7.4 Switchlevel diagram of a) 1:2 converter, b) 3:2 converter . . . . . . . . . . . 123
7.5 Optimization contours of the (a) 1:2 converter and (b) 3:2 converter . . . . 125
7.6 Cascode levelshift gate drive for the 1:2 ladder converter . . . . . . . . . . 127
7.7 Capacitorboost gate drive for the 3:2 converter . . . . . . . . . . . . . . . . 128
7.8 Shaker (a) design and (b) example input waveform . . . . . . . . . . . . . . 129
vi
7.9 Synchronous rectiﬁer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.10 Circuits implementing the synchronous rectiﬁer . . . . . . . . . . . . . . . . 131
7.11 Available energy via rectiﬁcation into a ﬁxed voltage source . . . . . . . . . 133
7.12 Diagram of control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.13 Schematics of analog references . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.14 Lowleakage sample and hold circuit . . . . . . . . . . . . . . . . . . . . . . 136
7.15 Photomicrograph of power interface IC . . . . . . . . . . . . . . . . . . . . . 137
7.16 SC Converter output voltage and eﬃciency, V
in
= 1.15V . . . . . . . . . . . 138
7.17 Power output and eﬃciency of synchronous rectiﬁer, V
B
= 1.2V , R
S
= 2.0kΩ,
100 Hz input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.18 Synchronous rectiﬁer waveforms (at 100 Hz) . . . . . . . . . . . . . . . . . . 140
8.1 SC converter performance versus ITRS technology node . . . . . . . . . . . 145
8.2 Tripleratio topology and its switch conﬁgurations . . . . . . . . . . . . . . 146
8.3 Eﬃciency plot of tripleratio topology in a 32nm process . . . . . . . . . . . 147
8.4 Approximate ring oscillator performance versus supply voltage . . . . . . . 149
8.5 Energy per operation using an SC converter . . . . . . . . . . . . . . . . . . 150
8.6 Nonscaling components of power loss versus cell size . . . . . . . . . . . . . 153
8.7 Drain charge recovery using a twointerleavedphase 2:1 converter . . . . . . 156
8.8 Waveforms of drain charge recovery methods . . . . . . . . . . . . . . . . . 157
8.9 Parasitic capacitance ratios for body and well capacitances . . . . . . . . . 159
A.1 An example circuit with graph representation . . . . . . . . . . . . . . . . . 165
A.2 3:1 Ladder topology, including twig designations in each phase . . . . . . . 168
A.3 Three conﬁgurations of a 2:5 seriesparallel topology . . . . . . . . . . . . . 177
A.4 An improperlyposed switchedcapacitor converter . . . . . . . . . . . . . . 179
A.5 Simulation of the dynamics of 3:1 ladder converter . . . . . . . . . . . . . . 189
B.1 Example plots from the MATLAB package . . . . . . . . . . . . . . . . . . 202
vii
List of Tables
3.1 Capacitor optimization summary for two device cost bases (twophase sim
pliﬁcations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Switch optimization summary for two device cost methods (twophase sim
pliﬁcations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1 Energy densities of common (a) capacitors and (b) inductors . . . . . . . . 73
6.1 Mass of common surfacemount components . . . . . . . . . . . . . . . . . . 105
6.2 Nchannel MOSFETs in SOT23 package . . . . . . . . . . . . . . . . . . . 105
6.3 Eﬃciency of singlestage boost converter . . . . . . . . . . . . . . . . . . . . 109
6.4 Eﬃciency of ﬂyback converter using custom transformer . . . . . . . . . . . 111
6.5 Eﬃciency of hybrid boost converter . . . . . . . . . . . . . . . . . . . . . . . 114
6.6 Eﬃciency of ladder converter with 4–10 stages at 10 mW load . . . . . . . . 116
6.7 Experimental results of the MicroGlider converter . . . . . . . . . . . . . . 118
7.1 Energy eﬃciency over sensing period . . . . . . . . . . . . . . . . . . . . . . 141
8.1 Process parameters from the ITRS roadmap . . . . . . . . . . . . . . . . . . 144
8.2 TDP and pin counts for three modern Intel microprocessors . . . . . . . . . 144
viii
Acknowledgments
I would like to thank a number of people and organizations that have helped me through my
research at UC Berkeley and in my life to date. First, I’d like to thank my parents who have
raised me to have an inquisitive mind which never stops thinking about how things work
and how to solve problems of every type. They have supported me through grade school
through college without placing excessive pressure academically or ﬁnancially, allowing me
to concentrate on what I love.
Next, I would like to thank my labmates through the various projects I have worked on
here at Berkeley. First, Seth Sanders, my advisor, and his group, including Jason Stauth,
Vincent Ng, Evan Reuzel, Mike He, Kun Wang, HahnPhuc Le, Artin der Minassians,
Mervin John and others. We have persisted in one of the smallest power electronics groups
in the country to produce outstanding work and ideas in a variety of areas of the ﬁeld.
Professors Ron Fearing and Paul Wright, and their students Erik Steltz, Rob Wood, Mike
Koplow, Christine Ho, Eli Leland, Lindsay Miller, Beth Reilly and others have been great
in our collaborations and have contributed to the diverse education I have received here.
Professors Seth Sanders and Elad Alon have been great in challenging me with numerous
ideas and fully developing our understanding of switchedcapacitor converters.
I also appreciate numerous others in the EECS department and the EEGSA which have
been great friends over the years. There are too many to list, but some include Ankur
Mehta, Bryan Brady, Sarah Bird, Kevin Petersen, Amit Lakhani, Josh Hug, Donovan Lee,
Alejandro de la Fuente, and Michael Armbrust. The days of ultimate frisbee, bar hopping
in the Mission, and numerous Wednesday afternoon social hours will always be some of my
fondest memories of Berkeley.
I would also like to thank the members of Cedar House, my residence for three and
a half years, including Tarik Bushnak, Linda Kwong, Derek Schoonmaker, Ariel Cowan,
Heather Brinesh, Emilie Le Bihan, Lisa Chen, Rachel Zeldin, Tim Keller, Julie Butler and
numerous others over the years. So many great adventures and memories; way too many
to name here.
ix
During my internship at Intel Corporation during the Fall semester, 2009, I’d like to
acknowledge those I worked with there in CTG and UMG. Some include Rinkle Jain, Pavan
Kumar, Annabelle Pratt, Tomm Aldridge, Sunil Jain and Ken Drottar, to name a few.
During this internship, I developed the lowerbound feedback method presented in section
5.2 and used to implement the SC converter prototype described in section 5.4.
Finally for support of this research, I would like to thank the sponsoring organizations
of the research. The Microglider project was funded by the National Science Foundation
under Grant No. IIS0412541. Any opinions, ﬁndings and conclusions or recommendations
expressed in this material are those of the author and do not necessarily reﬂect the views of
the National Science Foundation (NSF). I also gratefully acknowledge DARPA for support
under fund #FA865005C7138.
The PicoCube project was supported by the National Science Foundation Infrastructure
Grant No. 0403427 and the California Energy Commission Award DR0301. We would
also like to thank STMicroelectronics for complimentary CMOS fabrication. I would also
like to thank the students, faculty and sponsors of the Berkeley Wireless Research Center
(BWRC) for their support of this project.
x
xi
Chapter 1
Introduction
Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power convert
ers, using only switches and capacitors, that can eﬃciently convert one voltage to another.
Since SC converters use no inductors, they are ideal for integrated implementations, as
common integrated inductors are not suitable for power electronic applications. SC DCDC
converters also exhibit other advantages (and disadvantages) which will be further examined
in this work.
1.1 SwitchedCapacitor Converters in Industry and
Literature
Switchedcapacitor converters have been used in commercial products for many years.
These parts have been relatively simple, typically providing ﬁxedratio conversions (such
as a simple doubling, halving or inverting of the voltage). They have historically been
used in integrated circuits to provide the programming voltage for FLASH and other re
programmable memories [66], and to generate the voltages required by the RS232 serial
communication standard [30]. Additional discretecapacitor SC converter ICs provide con
version for LED lighting applications, a promising application of SC converters [31].
1
Only recently have SC converters come to market which utilize advanced techniques.
For example, the TPS60311 chip from TI is a singlecell (0.9 V to 1.8 V) to 3.3V converter
for consumer products [58]. It supports regulation through the use of two conversion ratios
and by varying switching frequency, allowing for precise regulation for IC applications.
Additionally, the chip supports an extremelylow standby power (2 µA), allowing its use in
ultralowpower applications, such as wireless sensor nodes.
The LM3352 chip from National Semiconductor[32] is a 200 mA buck/boost DCDC
converter chip. It employs an externalcapacitor design using three ﬂying capacitors which
supports multiple conversion ratios and full output regulation. These products push SC
converters into the space occupied by regulated inductorbased converters.
Improvements in PCB area utilization can be made by moving the capacitors onchip.
The MAX203E RS232 transceiver IC from Maxim uses internal capacitors to generate a
±10 V supply from a singlepolarity 5 V input. However, only a miniscule amount of power
is available from this part. This research aims to improve the power density and ﬂexibility
of onchip SC DCDC power converters.
1.2 SwitchedCapacitor Converter Structure and Terminology
A switchedcapacitor (SC) DCDC converter is a power converter which is comprised
exclusively of switches and capacitors. In general, an SC converter can have an arbitrary
number of ports, as shown in ﬁgure 1.1. Each port can be connected to a voltage source,
current source, resistive load, or any other type of circuit. A converter can be made of any
number of series subconverters, orstages, to expand the conversion ratio range.
Additionally, a singlestage SC converter can implement one or several topologies, where
the converter is denoted a multiratio converter. Each topology corresponds to a particular
conﬁguration of switches and capacitors which achieves a particular conversion ratio. By
changing the way the switches in a converter are clocked, a converter can be conﬁgured into
multiple topologies. A converter stage may also implement a number of parallel copies of
2
SwitchedCapacitor
Converter
v
1
v
2
v
3
+
+
+
i
1
i
2
i
3

 
Figure 1.1. An idealized 3port SC converter
the topology (or set of topologies), each known as an interleaved phase. By placing these
interleaved phases in parallel, and using equallyspaced interleaved clocking, output ripple
frequency will be increased and ripple magnitude will be decreased. Interleaving will be
further discussed in section 5.1. If a stage has N interleaved phases, they will be denoted
Φ
1
through Φ
N
.
Each topology consists of a collection of switches and capacitors. Each switch is turned on
during one or more phases. Each switching period consists of n nonoverlapping subdivisions
known as phases. These n phases are designated φ
1
through φ
n
. In each clock phase, the
switches conﬁgure the topology into a network of capacitors and onstate switches (modeled
as resistances). By switching through the phases, the topology performs power conversion
between its ports.
An example of a laddertype SC converter topology is shown in ﬁgure 1.2. In this
topology, the oddnumbered switches are turned on during phase 1 and the evennumbered
switches turn during in phase 2. Capacitors C4 and C5 are known as ﬂying capacitors since
their commonmode voltage moves with respect to ground. Capacitors C1, C2 and C3 have
a DC commonmode voltage (i.e. are ﬁxed with respect to ground), and are known as output
or bypass capacitors. This twoport converter exhibits a conversion ratio of threetoone,
i.e. the output is onethird of the voltage of the input under noload conditions. Likewise,
the converter multiplies charge by a factor of three.
The requirements placed on an SC topology to be wellposed are discussed in section A.3.
3
C1
C2
C3
C4
C5
S1
S2
S3
S4
S5
S6
V
IN
V
OUT
C 1
C 2
C 3
C 4
C 5
V
I N
V
O U T
C 1
C 2
C 3
C 4
C 5
V
I N
V
O U T
(a) (b) (c)
Figure 1.2. A 3:1 ladder topology, including networks in (b) phase 1 and (c) phase 2
4
First, the noload case will be examined with idealized components
1
. With a DC voltage
source applied to one of the converter’s ports (designated the input), and the remaining
ports opencircuited, the clocked converter will operate in a steadystate condition. If the
converter is properly posed, as discussed in appendix A.3, a DC voltage should appear
at the opencircuited ports, and no steadystate current should ﬂow from the input source.
Additionally, each capacitor should support a DC voltage. These criteria ensure that charge
is preserved and no shorting events occur.
To transfer charge between the input and output ports of the converter, the converter’s
capacitors must be charged and discharged, necessitating a voltage drop across the con
verter. This voltage drop is proportional to output current, and can be represented as an
output resistance. An idealized model for a twoport SC converter is shown in ﬁgure 1.3, as
discussed in references [27, 35]. The model is made up of an ideal transformer with a turns
ratio equal to the noload conversion ratio, and an output resistance R
OUT
.
m:n
v
IN
v
OUT
R
OUT
Figure 1.3. Idealized 2port SC converter model
The lowfrequency output impedance R
OUT
in ﬁgure 1.3 sets the maximum converter
power, constrained by a minimal eﬃciency objective, and also determines the openloop
load regulation properties. There are two asymptotic limits to output impedance, the slow
and fast switching limits, as related to switching frequency. The slowswitching limit (SSL)
impedance is calculated assuming that the switches and all other conductive interconnects
are ideal, and that the currents ﬂowing between input and output sources and capacitors
are impulsive, modeled as charge transfers. The SSL impedance is inversely proportional to
switching frequency. The fastswitching limit (FSL) occurs when the resistances associated
with switches, capacitors and interconnect dominate, and the capacitors act eﬀectively as
1
Ideal components include ideal capacitors and idealized switches with a ﬁnite onstate resistance and an
inﬁnite oﬀstate resistance.
5
ﬁxed voltage sources. In the FSL, current ﬂow occurs in a frequencyindependent piecewise
constant pattern. Computation of the FSL and SSL output impedances will be developed
in chapter 2.
Since the model in ﬁgure 1.3 perfectly represents the characteristics of an SC converter
using ideal capacitors and resistive switches, it can be used to develop a charge conservation
constraint. Since the output resistance does not aﬀect the ratio of input to output currents
in the model, these two currents are ﬁxed by the transformer turns ratio as:
I
IN
= −
n
m
I
OUT
(1.1)
Since this charge conservation equality holds independent of load, it can be used for further
analysis in later chapters. As this equality also holds on an integral cycle basis, it also can
be used to form an inputoutput constraint on charge ﬂow.
1.3 Preexisting SwitchedCapacitor Converter Analysis
Many papers have attempted analyses of SC converters. One of the early SC papers,
[15], introduces and analyzes what is known as the Dickson topology (see section 4.2).
However, this analysis assumes a diodebased implementation and only applies for that
speciﬁc topology family. Numerous additional references [8, 35, 67, 34] follow the same
approach and use nongeneral analysis methods to solve their particular problems. Clearly,
a moreuniﬁed and general analysis approach is needed.
Maksimovic and Dhar’s groundbreaking work in [27] develops a fundamental model of
SC converters and introduces the concept of the slowswitching limit (SSL) impedance.
It introduces a networktheoretic method for determining the conversion ratio and SSL
output impedance. Since the matrixbased methods are complex, they are not ideal for
widespread adoption, and are unnecessary for most analysis of SC converters. Additionally,
the analysis method in [27] is not entirely general, and does not address the FSL output
impedance besides suggesting its existence. The analysis work in chapter 2 takes this work
and extends its simplicity and generality.
6
1.4 Developments in This Work
The aim of this work is to present a complete analysis and design methodology for
SC converters, followed by several descriptions of SC converters being used for various
practical applications. Chapter 2 uses the fundamental descriptions from section 1.2 to
introduce charge multipliers which characterize the charge ﬂows in an SC converter. These
charge multipliers are used to ﬁnd the output impedance of an SC converter.
Chapter 3 uses the simple formulation of the output impedance of an SC converter
developed in chapter 2 to develop a method of properly sizing the capacitors and switches.
This optimization is based on costbased metrics where the total device cost (for both
capacitors and switches) is limited. This chapter also discusses the systemlevel design of a
converter by choosing the optimal switching frequency and switch area for a given design
power.
The merits of diﬀerent SC topologies are discussed in chapter 4, allowing the selection
of the best topology for a given application. The output impedances for numerous topolo
gies, including the ladder, Dickson, seriesparallel, Fibonacci and doubler topologies, are
compared in both the slowswitching and fastswitching limits. This chapter also compares
SC converters to magneticsbased DCDC converters in terms of both switch and reactive
element utilization. Finally, a fundamental limit on the performance of SC converters is
shown in both the SSL and FSL. It is shown that SC converters can achieve a higher power
density than magneticsbased converters considering both transistors and reactive elements.
The last of the analysis chapters, chapter 5 discusses the regulation of SC converters.
First, the ripple occurring at the output of an SC converter is discussed, including methods
of reducing this ripple. Next, simple hysteretic control methods are introduced involving
very little circuitry to maintain regulation. A simpliﬁed model of SC converters is developed
to model and simulate statebased control methods. Finally, a multipleratio SC converter
for portable electronics is discussed involving both automatic conversion ratio changing and
hysteretic feedback to eﬃciently regulate the output voltage.
7
Three applications of SC converters are then presented. Chapter 6 compares several
DCDC converters used to drive piezoelectric actuators for airborne robotics. The hybrid
boostswitchedcapacitor converter used for a twogram autonomous glider is presented,
including design considerations and performance results. This converter produces 200 V
from a 3.6V input at a power level of 10mW with a total component mass of 100 mg.
Chapter 7 describes power conditioning and conversion circuitry used in a cubic
centimeter wireless sensor node. A synchronous rectiﬁer eﬃciently harvests energy from
an electromagnetic energy scavenger, charging a small nickelmetalhydride cell. Two SC
converters supply the loads in the sensor at their required voltages. The design and perfor
mance of this power management IC are presented. The converter achieves an eﬃciency of
84% while consuming less than 10 µW with no load.
This work opens the door towards highperformance, highpower density SC converters.
Chapter 8 discusses using SC converters for very highpower applications using entirely
integrated converters. This chapter introduces a multipleratio converter which can be
integrated on the same die as mainstream microprocessors to supply power to individual
cores of a multicore processor. The power density of SC converters is examined with regard
to process scaling. In addition, methods of increasing the eﬃciency of highpowerdensity SC
converters are introduced. At a power density of 1 W/mm
2
, an eﬃciency of approximately
80% is predicted.
Finally, this work includes two appendices. Appendix A discusses the networktheoretic
analysis of SC converters which can be used to develop CAD tools for the analysis of SC
converters. This appendix derives the exact timebased dynamics of an SC converter from
the fundamental network matrices for the converter. It also discusses the properties of
properlyposed converters.
Appendix B describes a MATLAB package which automates the design process of a SC
converter. This package is used several times in this work as a design and visualization tool.
This work aims to present a complete and straightforward design methodology for SC
converters. This analysis method will beneﬁt designers greatly in the use of SC converters
8
for both integrated and nonintegrated applications. Three applications using SC converters
are also presented, applying the methods developed in this work.
9
Chapter 2
Fundamental Analysis of
SwitchedCapacitor Converters
With the model in ﬁgure 1.3, the converter provides an ideal dc voltage conversion ratio
under no load conditions, and all conversion losses are manifested by voltage drop associated
with nonzero load current through the output impedance [27, 35]. The resistive output
impedance accounts for capacitor charging and discharging losses and resistive conduction
losses. Additional losses due to shortcircuit current and parasitic capacitances, in addition
to gatedrive losses, can be incorporated into the model. While these parasitic losses are not
considered in the analysis in this chapter, they will be incorporated into the systemlevel
design in section 3.3. The aim in this chapter is to provide a general analysis and design
framework.
The lowfrequency output impedance R
OUT
in ﬁgure 1.3 sets the maximum converter
power, constrained by a minimal eﬃciency objective, and also determines the openloop
load regulation properties. There are two asymptotic limits to output impedance, the slow
and fast switching limits, as related to switching frequency [50, 51]. The slowswitching
limit (SSL) impedance is calculated assuming that the switches and all other conductive
interconnects are ideal, and that the currents ﬂowing between input and output sources
10
and capacitors are impulsive, modeled as charge transfers. The SSL impedance is inversely
proportional to switching frequency. The fast switching limit (FSL) occurs when the resis
tances associated with switches, capacitors and interconnect dominate, and the capacitors
act eﬀectively as ﬁxed voltage sources. In the FSL, current ﬂow occurs in a frequency
independent piecewise constant pattern. The total output impedance of the converter is a
combination of the two impedance components as examined in section 2.3.
The analysis in this chapter is targeted towards a twoport converter, such that R
OUT
is a scalar. The twophase model in [48, 51] will be extended here to multiphase converters,
as several of them have been represented in the literature [36]. In this analysis, we will be
applying DC voltage sources to both the input (V
IN
) and the output (V
OUT
). This allows
the determination of the output impedance by calculating the current ﬂowing in the circuit
for values of V
IN
and V
OUT
. The eﬀect of other loads on eﬃciency and operation will be
discussed in section 2.5.
2.1 SlowSwitching Limit Impedance
For the slowswitching limit (SSL) impedance analysis, the ﬁnite resistances of the
switches, capacitors, and interconnect are neglected. A set of charge multiplier vectors a
1
through a
n
can be derived for any standard wellposed nphase SC converter.
1
The charge
multiplier vectors correspond to charge ﬂows that occur immediately after the switches are
closed to initiate each respective phase of the SC circuit. Each element of a charge multiplier
vector corresponds to a speciﬁc capacitor or independent voltage source, and represents the
charge ﬂow into that component, normalized with respect to the output charge ﬂow. As
outlined in [27], the charge multiplier vectors can be uniquely computed using the KCL
constraints in each topological phase and the steadystate constraint that the n charge
multiplier quantities on each capacitor must sum to zero.
1
If these charge multiplier vectors cannot be uniquely determined, the converter is not wellposed. If a
consistent set of capacitor voltages can be found, an excess of DC capacitors (such as decoupling capacitors)
prevents a unique vector from being computed.
11
C 3
C 1
C 2
S 1
S 2
S 3
S 4
S 5
S 6
V
O U T
+
+
V
I N
Figure 2.1. A 3:1 ladder topology
C 3
C 1
C 2
V
O U T
+
+
V
I N
q
o u t
/ 3
q
o u t
/ 3
q
o u t
/ 3
2 q
o u t
/ 3
C 3
C 1
C 2
V
O U T
+
+
V
I N
q
o u t
/ 3
q
o u t
/ 3
2 q
o u t
/ 3
2 q
o u t
/ 3
(a) (b)
Figure 2.2. Capacitor charge ﬂow in ladder converter. (a) phase 1 and (b) phase 2
12
The charge multiplier vector a
1
is deﬁned as:
a
1
=
_
q
1
out
q
1
1
... q
1
n
q
1
in
_
/q
out
(2.1)
where each component is the ratio of charge transfer in each element during phase 1 of the
switching period to the charge delivered to the output during a full period. If charge ﬂows
into the positive terminal of the element during phase 1, the corresponding entry in the
a
1
vector is positive. Vectors a
2
through a
n
are deﬁned analogously for phases 2 through
n, respectively. The charge multiplier vector can be partitioned into output, capacitor and
input components, respectively:
a
1
=
_
a
1
out
a
1
c
a
1
in
_
(2.2)
For the ladder network example of ﬁgure 2.1, the charge multiplier vectors can be obtained
through network analysis using Kirchoﬀ’s Current Law (KCL) [27]. In this example, and in
all other examples encountered by the author, the charge multiplier vectors can be obtained
by inspection (in ﬁgure 2.2). The charge from the input source ﬂows into C1 during phase
1. In phase 2, that charge is transferred into C3. By considering alternating phases, the
charge ﬂow in each component can be found:
a
1
=
_
1/3 1/3 2/3 −1/3 −1/3
_
(2.3)
a
2
=
_
2/3 −1/3 −2/3 1/3 0
_
(2.4)
In each of these charge multiplier vectors, the ﬁrst component corresponds to the output
charge ﬂow, thus these two components must sum to one. The last component of each charge
multiplier vector corresponds to the charge ﬂow into the input source, and is nonzero during
only phase 1 in this example.
The charge multiplier vectors, the capacitor characteristics, and the switching frequency
are the only data needed to determine the output impedance under the asymptotic SSL
condition. The calculation, developed here, is based on Tellegen’s Theorem [13] which
states that for any network, any vector of branch voltages that satisﬁes KVL is orthogonal
13
to any vector of branch currents (or equivalently charge ﬂows) that satisﬁes KCL. This
theorem is applied in each of the n phases (or networks) for a nphase switched capacitor
converter operating in periodic steady state, where the input is shortcircuited and the
output is connected to an independent dc voltage source. The charge ﬂow per period (or
average current ﬂow) into the single independent source then deﬁnes the output impedance.
Application of Tellegen’s theorem to the switched capacitor converter, in each of its n
phases (or networks), yields a
j
· v
j
= 0, where v
j
is the respective steady state network
voltage vectors in phase j. Additively combining these applications of Tellegen’s theorem,
and noting that the input voltage source has value zero, yields
v
out
n
j=1
a
j
out
+
i∈caps
n
j=1
(a
j
c,i
v
j
c,i
) = 0 (2.5)
where the ﬁrst term corresponds to the constant output voltage source and the terms under
the summation correspond to the capacitor branches. Recall that a
1
out
+· · · + a
j
out
= 1 (as
each a
j
out
is normalized to q
out
) and that a
1
c,i
+· · · +a
j
c,i
= 0 for each capacitor branch, due
to charge conservation in periodic steadystate. By deﬁning ∆v
j
c,i
= v
j
c,i
−v
1
c,i
, substituting
∆v
j
c,i
into (2.5) yields:
v
out
+
i∈caps
_
_
v
1
c,i
n
j=1
a
j
c,i
+
n
j=1
a
j
c,i
∆v
j
c,i
_
_
= 0 (2.6)
v
out
+
i∈caps
n
j=1
a
j
c,i
∆v
j
c,i
= 0 (2.7)
as a
1
c,i
+· · · +a
n
c,i
= 0.
It is of direct interest here that none of the capacitor voltages need to be explicitly
calculated for this analysis. Rather, ∆v
j
c,i
can be computed from the charge ﬂows. In each
subperiod, the charge on each capacitor increases proportional to its charge multiplier:
v
j
c,i
−v
j−1
c,i
=
a
j
c,i
C
i
q
out
(2.8)
where C
i
is the capacitance value of the i
th
capacitor, assuming linear capacitors. Thus,
∆v
j
c,i
can thus be written as:
∆v
j
c,i
=
j
k=2
a
k
c,i
q
out
C
i
. (2.9)
14
Additionally, since the capacitor voltages are cyclic in steadystate, ∆v
j
c,i
can also be ex
pressed as:
∆v
j
c,i
= −
_
_
n
k=j+1
a
k
c,i
+a
1
c,i
_
_
q
out
C
i
. (2.10)
Averaging the two expressions yields:
∆v
j
c,i
=
_
_
−a
1
c,i
+
j
k=2
a
k
c,i
−
n
k=j+1
a
k
c,i
_
_
q
out
2C
i
. (2.11)
Substituting (2.11) into (2.7), an expanded equation is generated:
v
out
+
i∈caps
qout
2C
i
_
a
2
c,i
(−a
1
c,i
+a
2
c,i
−a
3
c,i
−a
4
c,i
−· · · −a
n
c,i
) +
a
3
c,i
(−a
1
c,i
+a
2
c,i
+a
3
c,i
−a
4
c,i
−· · · −a
n
c,i
) +
· · ·
a
n
c,i
(−a
1
c,i
+a
2
c,i
+a
3
c,i
+a
4
c,i
+· · · +a
n
c,i
)
_
= 0.
(2.12)
Simplifying (2.12) by expanding and combining like terms yields:
v
out
+
i∈caps
q
out
2C
i
_
−a
1
c,i
_
a
2
c,i
+· · · +a
n
c,i
_
+
_
a
2
c,i
_
2
+· · · +
_
a
n
c,i
_
2
_
= 0. (2.13)
Realizing that a
1
c,i
= −
_
a
2
c,i
+· · · +a
n
c,i
_
allows (2.13) to be further simpliﬁed:
v
out
+
i∈caps
q
out
2C
i
n
j=1
_
a
j
c,i
_
2
= 0. (2.14)
Dividing (2.14) by the output current (which can be represented as the product of
switching frequency and the periodic output charge) directly yields the average output
impedance for the slowswitching asymptotic limit:
R
SSL
= −
v
out
i
out
=
i∈caps
n
j=1
_
a
j
c,i
_
2
2C
i
f
sw
. (2.15)
This powerful result yields a simple calculation of this asymptotic output impedance
and some intuition into the operation of SC converters. The output impedance directly
models the losses in the circuit due to capacitor charging and discharging. This impedance
can be determined by simply examining the charge ﬂow in the converter without simulation
or complicated network analysis.
15
2.1.1 Extension to NonLinear Capacitors
The converter’s loss in terms of the series output impedance R
SSL
can be expressed
in terms of capacitor loss. A speciﬁc capacitor’s loss can be related to its voltage swing
during a period. While section 2.1 calculated the output impedance of a converter for
linear capacitors, the method can be extended to consider nonlinear capacitors. This
section considers the use of nonlinear lossless capacitors in a twophase converter. During
switching phase 1, the ith capacitor is charged (or discharged) from voltage v
2
i
to v
1
i
.
Analogously, during phase 2, the capacitor is then charged from voltage v
1
i
to v
2
i
. Since
the charging occurs to completion for operation in the SSL, the energy lost during each
transition can be given by the integral:
E
1
c,i
=
_
Q
C
(v
1
i
)
Q
C
(v
2
i
)
v
1
i
−Q
−1
C
(q)dq (2.16)
for the phase 1 transition, where Q
C
(v) is the capacitor’s nonlinear chargevoltage charac
teristic, presumed to be invertible. A similar expression exists for the phase 2 transition.
These two losses correspond to the two indicated regions in ﬁgure 2.3.
v
q
C
p h a s e 1
p h a s e 2
v
1
v
2
q
2
q
1
∆q
∆v
Figure 2.3. Energy loss due to capacitor charging
In the twophase case, since the total energy lost per period is simply equal to the area
of the rectangle, the loss is equivalent to that of a linear capacitor:
E
loss,i
=
_
v
1
i
−v
2
i
_ _
Q
C
(v
1
i
)Q
C
(v
2
i
)
_
= C
eq
(v
1
i
−v
2
i
)
2
(2.17)
16
v
q
Q
C
 1
( v )
( q
1
, v
1
)
( q
2
, v
2
)
( q
3
, v
3
)
v
q
Q
C
 1
( v )
( q
1
, v
1
)
( q
2
, v
2
)
( q
3
, v
3
)
(a) 1 → 2 → 3 (b) 3 → 2 → 1
Figure 2.4. Nonlinear capacitor losses in a threephase converter
where C
eq
is the linearized capacitance of the capacitor on the chord from v
1
i
to v
2
i
.
The product a
c,i
∆v
c,i
in (2.7), multiplied by the output charge, represents the energy loss
by charging and discharging capacitor i in each cycle. Since this term matches the expression
in (2.17) for energy loss, the linearized capacitance C
eq
can be directly substituted into the
output impedance equation (2.15) to ﬁnd the SSL output impedance of an SC converter
with nonlinear capacitors. This expression demonstrates that the sum of the energy lost
through the capacitors is equal to the calculated loss associated with the output impedance
for a given load.
The eﬀect of nonlinear capacitors in multiphase converters is signiﬁcantly more complex
as the loss region, such as the one in ﬁgure 2.4a, is no longer a rectangle. The integrated
loss in (2.16) must be used to determine the charging loss of each capacitor in each of the j
clock phases. While the exact SSL loss of a multiphase converter using nonlinear capacitors
will not be derived, some of the properties of such a converter will be examined.
Consider a threephase converter using a highly nonlinear capacitor with characteristics
shown in ﬁgure 2.4a. The three operating points, given by chargevoltage pairs (q
1
, v
1
),
(q
2
, v
2
) and (q
3
, v
3
) are also shown. This converter can either switch from state 1 to state
2 to state 3, and then back to state 1, or in the opposite direction. If linear capacitors are
17
used, these two methods would yield identical SSL impedances, as the sign of the charge
multiplier does not eﬀect the SSL impedance in (2.15). However, in the nonlinear case, the
area of the loss region in ﬁgure 2.4b is smaller than the loss region in ﬁgure 2.4a. Thus,
switching from state 3 to state 2 to state 1 and repeating yields lower SSL loss and a
lower SSL output impedance. This phenomenon may be used by a designer to improve the
performance of a multiphase SC converter if nonlinear capacitors are used.
2.2 FastSwitching Limit Impedance
The other asymptotic limit, the fast switching limit (FSL), is characterized by constant
current ﬂows between capacitors. The switch onstate impedances and other resistances are
suﬃciently large such that during each phase, the capacitors do not approach equilibrium.
In the asymptotic limit, the capacitor voltages are modeled as constant. The circuit loss is
related only to conduction loss in resistive elements. The concept of the FSL impedance is
introduced informally in reference [35].
The duty cycle of the converter is important when considering the FSL impedance since
currents ﬂow during the entirety of each phase. While previous analyses assumed a 50%
duty cycle [48, 51], this work will use duty cycle as an input to the model. To keep the
analysis general, a duty cycle of D
j
will be used for phase j for a converter with n phases.
Additionally, only the onstate switch resistance is considered; other parasitic resistance
(e.g. capacitor equivalent series resistance (ESR)) can be similarly incorporated into the
model if desired.
The a
j
r,i
charge multipliers are deﬁned as the charge ﬂow through switch i during phase j.
Even in the FSL, the charge ﬂows must follow the same pattern as in the SSL, constrained
by a
j
c
. For each phase, the a
j
r,i
values for the onstate switches can be determined as a
linear combination (typically by inspection) of the capacitor charge multipliers a
j
c
. The a
j
r,i
values for switches that are oﬀ are zero. The values of a
j
r,i
are independent of duty cycle
in steadystate as they simply represent the charge ﬂow through the switches that ensure
18
charge conservation on the circuit’s capacitors. The a
j
r,i
values for the switches in the ladder
converter in ﬁgure 2.1 can be determined directly. The charge ﬂows in the switches during
both phases are shown in ﬁgure 2.5, resulting in a
1
r
and a
2
r
vectors of:
a
1
r
=
_
1/3 0 1/3 0 −2/3 0
_
(2.18)
a
2
r
=
_
0 1/3 0 1/3 0 −2/3
_
(2.19)
C 3
C 1
C 2
V
O U T
+
+
V
I N
q
o u t
/ 3
q
o u t
/ 3
2 q
o u t
/ 3
S 1
S 3
S 5
C 3
C 1
C 2
V
O U T
+
+
V
I N
q
o u t
/ 3
q
o u t
/ 3
2 q
o u t
/ 3
S 2
S 4
S 6
(a) (b)
Figure 2.5. Switch charge ﬂow in ladder converter: (a) phase 1 and (b) phase 2
For positive power ﬂow (i.e. from the input to output source), the sign of each com
ponent of the a
j
r
vector indicates the direction of current ﬂow with respect to the blocking
voltage of a switch during phase j. A positive quanity indicates the switch conducts positive
current while on and blocks positive voltage while oﬀ. This switch must be implemented
using an active transistor. A negative quantity indicates the switch conducts negative cur
rent and blocks positive voltage and is suitable for diode implementation (if negative or zero
19
for all phases, and if the forward voltage drop is tolerable). For power ﬂow in the opposite
direction, the switch types reverse.
2
In the FSL, the current through the onstate switches is assumed to be constant. Given
the charge ﬂow vector, the current in each switch during each phase is easily determined:
i
j
r,i
=
1
D
j
q
r,i
f
sw
(2.20)
where q
j
r,i
is the charge ﬂow through switch i during period j occupying a ratio D
j
of the
total switching period. Substituting q
r,i
= a
r,i
q
out
and q
out
= i
out
/f
sw
into (2.20) yields:
i
j
r,i
=
a
r,i
D
j
i
out
(2.21)
The current through the switches is only dependent on the a
j
r
vectors, which is obtainable
by inspection, and the duration of each period. The network voltages never need to be
found in this analysis, simplifying computation signiﬁcantly.
The average power loss due to each individual switch is equal to the instantaneous on
state power loss multiplied by its duty cycle. Since the total loss of the SC converter in the
FSL is just the sum of the switch losses, the total circuit loss is given by:
P
FSL
=
i∈switches
n
j=1
R
i
D
j
_
2a
j
r,i
i
out
_
2
(2.22)
where R
i
is the onstate resistance of switch i.
Since the input and output charge ﬂow in the SC converter is constrained by the con
version ratio n, all the power loss in an ideal SC converter (as analyzed here) is modeled by
the output voltage drop. Thus the output impedance can be determined by equating the
actual power loss of the circuit with the apparent power loss due to the output impedance.
Since this power loss is proportional to the square of the output current, the FSL output
impedance can be obtained by inspection:
R
FSL
=
i∈switches
n
j=1
R
i
D
j
(a
j
r,i
)
2
. (2.23)
2
For multiphase converters, or converters that can be conﬁgured to implement several topologies, a
particular switch may block bilateral voltage and/or conduct bilateral current, and must be implemented
accordingly.
20
If the total switching period is split into n equal periods, the FSL output impedance can
be simpliﬁed to:
R
FSL
= n
i∈switches
n
j=1
R
i
(a
j
r,i
)
2
. (2.24)
Analogously to the SSL output impedance in (2.15), the FSL output impedance is given
simply in terms of component parameters and the switch charge multiplier coeﬃcients of
each switch. The power loss due to these conduction losses is equal to the equivalent power
loss through the output impedance. These two simple forms of the output impedance (given
in (2.15) for the SSL and (2.23) for the FSL) can be used to provide strong guidance for
the design of switchedcapacitor power converters.
2.3 Calculating Total Output Impedance
The total output impedance of a SC converter is made up of the slowswitching limit
(SSL) impedance and fastswitching limit (FSL) impedance, derived in sections 2.1 and
2.2, respectively. However, these components do not directly add to form the total output
impedance, as they are derived assuming diﬀerent operating conditions. When the SSL and
FSL impedances are nearly equal, the converter is operating in neither the SSL or FSL, so
the assumptions made for each of the two impedance calculations are not valid.
In the operating region between the SSL and FSL, the dynamics of the SC converter
play a large roll in determining the impedance. In each phase, the network of onstate
switches (modeled as resistors) and capacitors may create very complex settling dynamics for
manyelement topologies. Since the derivation of the general combined output impedance
is impractical, a simple example will be evaluated, and the results will be applied to an
approximation of total output impedance. The dynamics of an arbitrary SC converter are
developed in section A.4.
In this example, the trivial SC converter, shown in ﬁgure 2.6, will be used to examine
the output impedance between the slow and fast switching limits. The two switches (each
with onstate resistance R) and single capacitor (with capacitance C) guarantee a single
21
+ +
V
1
V
2
C
R R
S 1 S 2
Figure 2.6. Trivial SC converter used for dynamic analysis
settling time constant (τ = RC). Given a switching period T close to the time constant, the
converter will be operating in neither the SSL or FSL, so the capacitor voltage will exhibit
a waveform like the one shown in ﬁgure 2.7.
v
C
t
V
1
V
2
T / 2 T 3 T / 2 2 T 5 T / 2
∆ v
Figure 2.7. Capacitor voltage waveform of trivial converter
The ripple voltage on the capacitor is directly proportional to the charge transfer of the
circuit, so the ripple amplitude will be found ﬁrst. Since the circuit is symmetric and is
operating at a 50% duty cycle, the waveform will be symmetric about the mean of V
1
and
V
2
. The ripple height can be expressed as a decaying exponential:
∆v =
_
∆v +
V
1
−V
2
−∆v
2
_
_
1 −e
−T/2RC
_
(2.25)
Solving for ∆v yields:
∆v
_
2 −
_
1 −e
−T/2RC
__
= (V
1
−V
2
)
_
1 −e
−T/2RC
_
(2.26)
∆v = (V
1
−V
2
)
1 −e
−T/2RC
1 +e
−T/2RC
(2.27)
22
Since the charge transferred between sources V
1
and V
2
is proportional to the ripple voltage
by q
out
= C∆v, the timeaveraged current ﬂowing in the circuit is given by:
i
out
=
Cf
sw
_
1 −e
−T/2RC
_
1 +e
−T/2RC
(V
1
−V
2
). (2.28)
Finally, the output impedance is given by the ratio of output voltage to current, and by
substituting 1/f
sw
for the switching period T:
R
OUT
=
1 +e
−1/2RCfsw
Cf
sw
_
1 −e
−1/2RCfsw
_. (2.29)
This form of of the output impedance clearly shows the output impedance is not a simple
sum between the SSL and FSL output impedance components. Additionally, for networks
with more than one mode (or time constant), this expression would become prohibitively
complex. The SSL and FSL impedances can be determined by taking the limit of (2.29) as
f
sw
approaches zero and inﬁnity, respectively:
R
SSL
= lim
fsw→0
R
OUT
= lim
fsw→∞
1 +e
−1/2RCfsw
Cf
sw
_
1 −e
−1/2RCfsw
_ =
1
Cf
sw
(2.30)
R
FSL
= lim
fsw→∞
R
OUT
= lim
fsw→∞
∂
∂fsw
_
1+e
−1/2RCfsw
Cfsw
_
∂
∂fsw
_
1 −e
−1/2RCfsw
_ (2.31)
= lim
fsw→∞
1
C
_
1
2RCfsw
e
−1/2RCfsw
−
_
1 −e
−1/2RCfsw
_
_
1
2RC
e
−1/2RCfsw
= 4R. (2.32)
L’Hospital’s rule is used in (2.32) to complete the derivation. By inspection, these limits to
the general output resistance match those calculated in sections 2.1 and 2.2.
The exact output impedance formula may be diﬃcult or impossible to ﬁnd for many
converters, so an approximation would be beneﬁcial for design purposes. Besides simply
adding the two impedance components, the output impedance is often approximated as
[28]:
R
OUT
≈
_
R
2
SSL
+R
2
FSL
. (2.33)
These two approximations along with the exact output impedance for this example in (2.29)
are plotted in ﬁgure 2.8. In this evaluation, R = C = 1, but the results are representative of
any SC converter. The approximation in (2.33) is reasonably close to the modeled results,
and will be used throughout this work.
23
2.4 Model Simpliﬁcation for TwoPhase Converters
The majority of wellknown SC converter topologies are twophase converters. Previous
analysis [27, 50, 51] only considered twophase converters, so relating the analysis in sections
2.1 and 2.2 to the twophase case would be useful and beneﬁcial for the analysis later in
this work.
In a twophase converter, single a
c
and a
r
vectors can be deﬁned. Due to charge
conservation, the two capacitor charge multipliers are equal and opposite, such that we can
deﬁne:
a
c
= a
1
c
= −a
2
c
(2.34)
Similarly, since each switch is on during exactly one phase, an a
r
vector can be made with
the nonzero a
j
r,i
components.
Next, the SSL and FSL output impedance results can be similarly simpliﬁed given two
phases and the above vector deﬁnitions. Additionally, a duty cycle of 50% will be assumed.
The SSL impedance in (2.15) can be simpliﬁed to:
R
SSL
=
i∈caps
(a
c,i
)
2
C
i
f
sw
(2.35)
Similarly, the FSL impedance in (2.24) can be simpliﬁed to:
R
FSL
= 2
i∈switches
R
i
(a
r,i
)
2
(2.36)
These equations simplify the output impedance calculations derived for multiphase con
verters. Where generality will be maintained in much of the work, for speciﬁc twophase
converters, these terms and formulas will be used instead.
2.5 Modeling Other Converter Loads
The models in the previous sections only consider voltage sources attached to the ports
of an SC converter. In real converters, the load is rarely modeled as a voltage source. Numer
ous additional loads can be applied, the three addressed here include capacitive, inductive
24
and currentsource loads. These other loads either moretypically represent frequently
occuring loads or alternate loads which may improve eﬃciency.
2.5.1 Capacitive Loads
The most common load of an SC converter is a constantcurrent or resistive load with a
large output (bypass) capacitor. If the output capacitor is suﬃciently large, the load appears
like a ﬁxed voltage source at the switching frequency. If the size of the output capacitance
is limited, a ripple voltage will appear on the output due to the impulsive current transfer
occurring in the SSL. The load current discharges this output capacitor linearly between
the phase transitions. Since the output capacitor is being discharged by a current source,
the impulsive charges delivered to the output capacitor do not add to zero, but instead add
to the average output current. Since the losses due to this impulsive charging are related to
the square of the magnitude of each charge impulse, the loss is minimized if the impulses are
of equal size in each phase. When the charge delivered to the output is equal in each phase,
the linear output capacitor’s charging loss can be added to the SSL impedance calculation
by using a charge multiplier of 1/j in each of the j phases. Nonuniform charge transfer
increases the loss associated with the output capacitance, but can be reduced by using a
converter with multiple interleaved phases. The discharging of the output capacitor due to
the load current does not contribute additional loss since it is done adiabatically via the
currentsource load.
The ripple at the output of a converter can have negative eﬀects on the load (if it consists
of sensitive analog or digital circuits) or on the converter’s control circuitry. Furthermore,
a small output capacitance may have a negative eﬀect on the eﬃciency of the converter due
to the ripple voltage on this capacitance. Output voltage ripple will be further examined
in section 5.1.
25
2.5.2 CurrentSource Load
Loads that can be modeled as a current source have a promising use in SC converters.
When linear capacitors are charged via voltage sources, as in the above analysis, they lose
a substantial fraction of the transfer energy in the charging process, given by
E
LOSS
=
1
2
∆q
c
∆v
c
. (2.37)
This loss is directly equivalent to the SSL resistive loss. If the capacitors can be charged
via a series current source, the converter could be nearly 100% eﬃcient. Additionally, as
eﬃciency declines with load in the SSL with voltage source charging, the power density of
a currentsource charged converter can be dramatically improved. Reference [37] describes
a twostage SCbuck converter, where the buck converter provides a currentsourcelike
load for the SC converter. By providing this softcharging ability, the SC converter’s loss
decreases by 21%.
Figure 2.9a shows a 2:1 ladder converter. In ﬁgure 2.9b, the output voltage and ﬂying
capacitor voltage are shown for this converter based on both a voltagesource load (represen
tative of a resistorcapacitor load) and a current source load. By charging and discharging
the ﬂying capacitor via a current source, a higher eﬃciency is achieved as the SSL impedance
loss is eliminated. However, the output exhibits signiﬁcant voltage ripple. In many appli
cations, a constraint is often placed on the minimum value of the output voltage to ensure
proper operation of the load. For example, in a microprocessor, some instructions may yield
incorrect results if the supply voltage drops below the minimum voltage during execution
of that instruction. If the minimum of the output voltage is considered, the eﬃciency of
this converter is identical to the voltage source load condition.
2.5.3 Inductive Load
While current source loads have the ability to greatly increase the eﬃciency of an SC
converter, very few real loads provide the boost in eﬃciency provided by a current source
load. However, by using an inductive ﬁlter on the output, a similar eﬀect can be obtained.
26
10
−2
10
−1
10
0
10
1
10
0
10
1
10
2
Relative switching frequency
O
u
t
p
u
t
I
m
p
e
d
a
n
c
e
Plain Sum
Quadratic Sum
RC Settling
SSL
FSL
Figure 2.8. Output impedance when R
SSL
≈ R
FSL
and approximations
C 1
S 1
S 2
S 3
S 4
V
I N
V
O U T
t
t
V
C 1
V
O U T
V
I N
/ 2
V
I N
/ 2
C u r r e n t  so u r c e l o a d
V o l t a g e  so u r c e l o a d
(a) (b)
Figure 2.9. 2:1 ladder converter: (a) topology (b) waveforms for current and voltage source
loads
27
+
V
O U T
L i
L
2 R
O N
V
I N
C
+

v
C
+
V
O U T
L i
L
2 R
O N
C
+

v
C
0 0.5 1 1.5 2
0
0.2
0.4
0.6
0.8
1
1.2
Time [µ s]
V
o
l
t
a
g
e
[
V
]
,
C
u
r
r
e
n
t
[
A
]
Inductor Current [A]
Capacitor Voltage [V]
(a) (b) (c)
Figure 2.10. SC converter with inductive load: a) phase 1 network, b) phase 2 network, c)
waveforms
Since an inductor at the output holds the output current continuous, it acts similar to a
currentsource load.
Like a currentsource load, an inductive load may cause problems for implementation.
Since the output current is forced continuous, methods for keeping the current continuous
during phase switching events must be implemented. The phase dynamics are now based
on a RLC network (not an RC network), so ringing can occur during phase transitions.
This ringing can contribute to both additional losses and device stresses. Careful design
techniques must be used to prevent the ringing from destroying the transistors when using
an inductive load.
Despite the implementation diﬃculties, using an inductive load may still be beneﬁcial
for certain applications. To examine the beneﬁts of using an inductive load, a timedomain
analysis of a switching period will be performed using the topology in ﬁgure 2.9a with
an inductor and DC voltage source at the output. Figures 2.10a and 2.10b show the RC
networks formed by the topology in phases 1 and 2, respectively. These two networks can
be characterized by a diﬀerential equation speciﬁc to this topology:
d
dt
i
L
+
R
L
i
L
+
1
L
v
C
=
_
¸
_
¸
_
1
L
(V
IN
−V
OUT
) phase 1
1
L
(V
OUT
) phase 2
(2.38)
28
d
dt
v
C
=
i
L
C
(2.39)
These two RLC networks create symmetric transients during each of the two periods,
shown in ﬁgure 2.10c. In steadystate operation, the capacitor voltage waveform is sym
metric around V
IN
/2, and the inductor current reaches the same value at the end of each
phase. These relationships set up two boundary conditions:
v
C
(T/2) = V
IN
−v
C
(0) (2.40)
i
L
(T/2) = i
L
(0) (2.41)
When these boundary conditions are used to solve the diﬀerential equations for the two
phase networks, the steadystate waveforms in ﬁgure 2.10c can be reproduced. The voltage
change on the capacitor in a single phase is proportional to the output current during that
phase. Thus, the output current and output resistance can be found accordingly:
I
OUT
= f
sw
4 C
_
V
IN
2
−v
C
(0)
_
, (2.42)
R
OUT
=
_
V
IN
2
−V
OUT
_
I
OUT
. (2.43)
For a given switching frequency, capacitor values and switch onstate resistance values,
it is informative to determine the eﬀect a certain inductance has on the output impedance,
and thus converter eﬃciency. The output impedance, found using the preceding method, is
evaluated for a range of inductance values, and is shown in ﬁgure 2.11 for three values of
switch onstate resistance.
As is clear from ﬁgure 2.11, there is a critical inductance (approximately 10 nH in this
case) where the SSL output impedance component is eliminated for inductances above the
critical value. The critical inductance is given approximately by
L
crit
=
1
C
√
2πf
sw
(2.44)
29
10
−10
10
−9
10
−8
10
−7
10
−6
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Inductance [H]
O
u
t
p
u
t
I
m
p
e
d
a
n
c
e
[
Ω
]
R
ON
= 0.1
Halver, 1 MHz
C = 1 µ F
R
ON
= 0.05
R
ON
= 0.02
Figure 2.11. Output impedance of SC converter with inductive load
where f
sw
is the switching frequency and C is the value of the equivalent ﬂying capacitance.
The left asymptote corresponds to the voltage source load case, where the SSL and FSL
impedance combine to form the converter’s output impedance. The right asymptote cor
responds to the currentsource load case, where the capacitorrelated losses are eliminated
and the converter’s output impedance equals the FSL impedance.
This analysis was performed for a speciﬁc converter topology. A similar eﬀect will occur
for converters where all capacitors are charged and discharged in series with the output
(typically stepdown converters). Some topologies (especially stepup topologies) will still
exhibit lossy charging or discharging as some current paths do not include the output source.
Additionally, a resonance occurs between the ﬂying capacitors and the output inductor
for low values of switch resistance. When the resonance frequency aligns with the switch
ing frequency, little net current can be transferred each period, yielding a higher output
impedance. This phenomenon must be avoided if an inductive load is used. However, if the
pitfalls of this method are avoided, a smallvalue inductor at the output of a converter can
be used to greatly improve converter eﬃciency.
30
Chapter 3
Optimization of
SwitchedCapacitor Converters
A method of determining the output resistance of switchedcapacitor (SC) DCDC con
verters was developed in chapter 2. Expressions for evaluating the slow and fastswiching
limit output impedance were developed in terms of the switching frequency, network ar
rangement and component parameters. This general and relatively simple analysis method
creates an extremely powerful framework for SC converter design. This chapter will discuss
the device choices and sizing for each individual component in the SC networks. Based on a
costbased metric, the switches and capacitors of the SC converter can be independently op
timized. System design, including choosing the switching frequency and the relative sizing
between switches and capacitors, will be discussed in section 3.3.
The optimization procedure requires knowledge of the component working voltages,
which was not required for the output impedance analysis. The working voltage for a
capacitor is the maximum voltage on the capacitor during steadystate converter operation.
For a transistor (switch), the working voltage is the voltage it blocks during steadystate
converter operation. For opencircuit operation, these working voltages can be found by
inspection in most examples, or by the process outlined in reference [27] or in appendix
31
A. This analysis is based on combining KVL constraints for the two phase topologies, in
combination with a known source voltage. The result is the computation of vectors denoted
v
c
and v
r
for the working voltages of the capacitors and switches, respectively, ratioed to
the converter output voltage.
3.1 Device Cost Metrics
Before the performance of a converter is optimized, each component in the circuit must
be matched with a technology suitable to implement that component. To match a compo
nent with a device, a switch performance metric must be evaluated for all available device
technologies and the device with the greatest metric value chosen. The ﬁrst criteria is that
the device’s blocking voltage, given by v
c(rated)
or v
r (rated)
for capacitors and switches,
respectively, must exceed the maximum blocking voltage of the component. It is important
to note that during highload conditions, the blocking voltage of some components may
exceed the noload steadystate condition. Additionally, startup and shutdown circuitry
must ensure the transient voltages do not exceed the device ratings.
Next, a cost metric for each device technology must be developed. These metrics must
reﬂect the performance of a device for a given cost. In integrated circuits, this cost is
typically die area, but could be power loss in applications where that component is not
limiting system area. For capacitors, the performance of a device can be represented as its
energy storage as used in the application. Thus, the areal energy density capacitor metric
can be given by:
M
cap
=
C v
2
c,i
2 A
cap
(3.1)
where C is the capacitance of a test device occupying area A
cap
, and v
c,i
is the voltage that
the capacitor blocks in normal operation. Since capacitance scales linearly with area, this
metric is constant for a given technology and component in the topology. Thus, for a given
component, the device with the largest metric, while meeting the voltage rating constraint,
should be used for the design.
32
Similarly, the performance of a switch can be represented by its VA product. The
VA product represents the product of the blocking voltage and FSL onstate current. This
VA product is related to the product between a switch’s conductance and the square of its
blocking voltage, as described in section 3.2.
The cost of a switch can be represented as its die area, for arealimited integrated
applications. If the switch area in an application is not limited (i.e. if the capacitor area
dominates the switch area, as in many IC application examples), the cost of a switch can
be equated to the switching loss of the device. Thus, the optimization can use one of the
following two switch metrics:
M
sw1
=
Gv
2
r,i
A
sw
(3.2)
M
sw2
=
Gv
2
r,i
C
G
v
2
G,i
+C
D
v
2
r,i
+C
BS
v
2
B,i
(3.3)
where G is the onstate conductance of the test switch of area A
sw
, and v
r,i
is the blocking
voltage of switch i in the topology. The switch metric represents the ratio between the
performance of the switch, given by the GV
2
product, and the cost of a switch, given by
either die area or capacitive switching loss. The metrics in (3.2) and (3.3) have diﬀerent
units, representing the units of their respective costs, and must be used in an optimization
speciﬁc to that cost. In (3.3), C
G
, C
D
and C
BS
are the linearized gate, drain and source
body capacitances of the test switch, respectively. The voltages v
G,i
, v
r,i
and v
B,i
are
the peaktopeak amplitudes of the gatesource, drainsource and bodysource voltages,
respectively. When choosing a device technology for each component, the device with the
largest relevant metric, while having a suﬃcientlyhigh rated voltage, should be used for a
given component in the topology.
3.2 Component Sizing
Now that a method has been developed to choose the best device technology available
for each given component, each component must be sized relative to each other to obtain
33
the best performance for a given total device area or parasitic power loss. Given that the
losses attributed to ideal capacitors and resistive switches are reﬂected in the computation
of a single real output resistance, the components can now be optimized to minimize that
output impedance. Minimal output impedance corresponds to maximum eﬃciency for a
given power delivered, and dually, corresponds to maximum power delivery for a given
loss. This section develops optimality computations for the slow switching limit (SSL) and
fast switching limit (FSL) impedances. When optimizing over capacitances, one should
minimize the output impedance that is associated only with the capacitances, namely the
SSL impedance found in section 2.1. Analogously, when optimizing over switch sizes, one
should minimize the FSL output impedance found in section 2.2.
While the optimization can be carried out for each of the metrics in section 3.1, for sake
of brevity, the derivation will be shown for an idealized device metric as follows, and the
results using each metric will be shown in tables 3.1 and 3.2. For capacitors, their area (or
volume) is typically related to their maximum possible energy storage. Thus, the following
optimization will hold total capacitor energy storage constant using this constraint:
E
tot
=
i∈caps
1
2
C
i
_
v
c,i (rated)
_
2
. (3.4)
The energy storage cost of a capacitor is related to its rated voltage, not the maximum
voltage it sees during operation.
The switches’ areal cost metric can be idealized to a constraint on the total VA product
summed across all the switches in the converter. As proposed in section 3.1, the VA product
corresponds to the product between a switch’s conductance and the square of its blocking
voltage as described here. This GV
2
constraint can be represented as:
X
tot
=
i∈switches
G
i
_
v
r,i (rated)
_
2
. (3.5)
This VA product is related to the product between a switch’s conductance and the
square of its blocking voltage, for both discrete and integrated switches. Paralleling switches
increases total conductance, whereas placing switches in series increases voltage blocking
while decreasing conductance. To increase voltage blocking without reducing conductance,
34
the number of devices used scales quadratically, motivating the GV
2
metric. In an inte
grated application, the same total GV
2
constraint applies. Roughly, the transistor length
and nominal voltage scale linearly with process feature size. In addition, switch conductance
scales proportionally with transistor width and inversely with transistor length.
3.2.1 Capacitor Sizing
To optimize relative capacitor sizes, a Lagrange multiplier method will be used for
the equalityconstrained optimization problem. The SSL output impedance (2.15) will be
minimized while the constraint on total energy (3.4) will be held constant. A function L is
deﬁned to perform the constrained optimization:
L =
i∈caps
n
j=1
_
a
j
c,i
_
2
2C
i
+λ
_
i
1
2
(v
c,i (rated)
)
2
C
i
−E
tot
_
(3.6)
where the ﬁrst term represents the SSL output impedance (scaled by switching frequency as
it does not aﬀect the minimization) and the second term incorporates the energy constraint
in (3.4). The impedance is minimized by equating the partial derivatives of L with respect
to both C
i
and λ with zero:
∂L
∂C
i
= −
n
j=1
_
a
j
c,i
_
2
2C
2
i
+λ
1
2
_
v
c,i (rated)
_
2
= 0 (3.7)
∂L
∂λ
=
i
1
2
_
v
c,i (rated)
_
2
C
i
−E
tot
= 0 (3.8)
Note that equation (3.8) simply repeats the constraint in (3.4).
The relationship in (3.7) sets up a proportionality between C
i
, a
j
c,i
and v
c,i (rated)
. The
energy constraint can be used to ﬁnd an expression for the value of each capacitor:
C
i
=
_
n
j=1
_
a
j
c,i
_
2
v
c,i (rated)
2 E
tot
k∈caps
v
c,k (rated)
_
n
j=1
_
a
j
c,k
_
2
(3.9)
35
The optimal energy storage rating of each capacitor is proportional to the VQ product of
each capacitor:
E
i
=
v
c,i (rated)
_
n
j=1
_
a
j
c,i
_
2
k∈caps
v
c,k (rated)
_
n
j=1
_
a
j
c,k
_
2
E
tot
(3.10)
When the total energy is constrained, the optimal capacitor energies are proportional to
the product of their rated voltage and their charge multiplier coeﬃcients. In addition, the
ripple voltage on each capacitor is directly proportional to that capacitor’s rated voltage.
The optimized output impedance can be calculated by combining (2.15) and (3.9):
R
∗
SSL
=
1
4E
tot
f
sw
_
_
i∈caps
v
c,i(rated)
¸
¸
¸
_
n
j=1
_
a
j
c,i
_
2
_
_
2
(3.11)
Since many commonlyused SC topologies use only two phases, it is useful to simplify
the results in (3.9) and (3.11) using the relation a
c,i
= a
1
c,i
= −a
2
c,i
. The optimized capacitor
values and total SSL output impedance for a twophase SC converter are given by:
C
i
=
¸
¸
¸
¸
a
c,i
v
c,i (rated)
¸
¸
¸
¸
2E
tot
k
a
c,k
v
c,k (rated)

(3.12)
R
∗
SSL
=
1
2E
tot
f
sw
_
_
i∈caps
a
c,i
v
c,i (rated)

_
_
2
(3.13)
By optimizing the capacitors, the output impedance becomes proportional to the square
of the sum of the products of voltages and charge ﬂows (VA product) of each capacitor.
This optimization can improve the performance of an SC converter designed in an adhoc
manner signiﬁcantly, especially one with a large conversion ratio. For example, if a high
ratio ladder converter is designed, using this method to size the capacitors will yield a
signiﬁcant performance advantage over the converter if uniform capacitor sizes were used
instead.
36
3.2.2 Switch Sizing
Like capacitors, the switches in a SC converter can be optimized, yielding dramatic
performance increases. This optimization is carried out in the asymptotic fast switching
limit where output impedance is directly related to switch conductance. Similar to the
SSL optimization case, a Lagrange optimization function L is formed to minimize the FSL
output impedance while satisfying the constraint in (3.5):
L =
i
n
j=1
_
a
j
r,i
_
2
G
i
+λ
_
i∈switches
G
i
(v
r,i (rated)
)
2
−X
tot
_
(3.14)
The ﬁrst term corresponds to the FSL output impedance (the omission of the factor of the
number of phases denoted by n in (2.24) does not aﬀect the optimization) and the second
term corresponds to the constraint in (3.5). The minimization is performed by taking the
partial derivative of (3.14) with respect to G
i
and setting it to zero:
∂L
∂G
i
= −
n
j=1
_
a
j
r,i
_
2
G
2
i
+λ
_
v
r,i (rated)
_
2
= 0 (3.15)
Again, diﬀerentiating (3.14) with respect to λ yields the constraint in (3.5).
Manipulating equation (3.15) yields a proportionality between G
i
and the ratio between
the switch’s charge multiplier coeﬃcient and its voltage rating. This proportionality, when
combined with the GV
2
constraint in (3.5), yields an expression for the optimal conductance
of each switch:
G
∗
i
=
1
R
∗
i
=
_
n
j=1
_
a
j
r,i
_
2
v
r,i (rated)
X
tot
k
v
r,k (rated)
_
n
j=1
_
a
j
r,k
_
2
(3.16)
Comparing the optimal conductance G
i
to the optimal capacitance in (3.9) makes it evident
that the two optimizations are analogous.
The optimal FSL output impedance is obtained by substituting (3.16) into (3.17):
R
∗
FSL
=
n
X
tot
_
_
i
v
r,i (rated)
¸
¸
¸
_
n
j=1
_
a
j
r,i
_
2
_
_
2
(3.17)
37
where n is the number of phases used.
Since most of the commonlyused topologies use two phases, for the twophase case, the
optimized switch conductance in (3.16) and the optimized FSL output impedance in (3.17)
can be simpliﬁed to:
G
∗
i
=
1
R
∗
i
=
¸
¸
¸
¸
a
r,i
v
r,i(rated)
¸
¸
¸
¸
X
tot
k
a
r,k
v
r,k(rated)

(3.18)
R
∗
FSL
=
2
X
tot
_
i
a
r,i
v
r,i(rated)

_
2
. (3.19)
Similar to the optimal SSL impedance, the optimal FSL output impedance is related to the
square of the sum of the VA products. This simple form of the optimal output impedance
allows the comparison of various SC converter topologies, as performed in chapter 4.
3.2.3 Optimizing Using Other Metrics
Sections 3.2.1 and 3.2.2 present a method to optimize the relative capacitor and switch
sizing, respectively, in an SC converter. However, the optimization is performed assuming
limits on capacitor energy storage and switch VA product. If varied device technologies are
used, a more practical cost metric must be used. This optimization can also be performed
using the metrics developed in section 3.1, namely the die area and parasitic power loss
metrics. The detailed optimization using these metrics will not be shown here, since it is
nearly identical to the derivation in sections 3.2.1 and 3.2.2. The results of the optimizations,
including the relevant constraints, component sizing, and output impedance, are shown in
table 3.1 for the capacitor optimization and in table 3.2 for the switch optimization.
38
G
e
n
e
r
a
l
C
o
s
t
A
r
e
a

b
a
s
e
d
C
o
s
t
D
e
v
i
c
e
C
o
s
t
E
n
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r
g
y
s
t
o
r
a
g
e
D
i
e
a
r
e
a
C
o
s
t
C
o
n
s
t
r
a
i
n
t
E
t
o
t
=
i
1 2
C
i
_
v
c
,
i
(
r
a
t
e
d
)
_
2
A
t
o
t
=
i
A
i
D
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v
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c
e
M
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t
r
i
c
N
/
A
M
c
a
p
=
C
i
(
v
c
,
i
(
r
a
t
e
d
)
)
2
2
A
c
a
p
O
p
t
i
m
i
z
e
d
C
a
p
a
c
i
t
o
r
V
a
l
u
e
s
C
∗ i
=
¸ ¸ ¸
a
c
,
i
v
c
,
i
(
r
a
t
e
d
)
¸ ¸ ¸
2
E
t
o
t
P
k

a
c
,
k
v
c
,
k
(
r
a
t
e
d
)

C
∗ i
=
¸ ¸ ¸
a
c
,
i
v
c
,
i
(
r
a
t
e
d
)
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_
M
c
a
p
,
i
2
A
t
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t
P
k

a
c
,
k
v
c
,
k
(
r
a
t
e
d
)

√
M
c
a
p
,
k
O
p
t
i
m
i
z
e
d
O
u
t
p
u
t
I
m
p
e
d
a
n
c
e
R
∗ S
S
L
=
1
2
E
t
o
t
f
s
w
_
i

a
c
,
i
v
c
,
i
(
r
a
t
e
d
)

_
2
R
∗ S
S
L
=
1
2
A
t
o
t
f
s
w
_
i

a
c
,
i
v
c
,
i
(
r
a
t
e
d
)

√
M
c
a
p
,
i
_
2
T
a
b
l
e
3
.
1
.
C
a
p
a
c
i
t
o
r
o
p
t
i
m
i
z
a
t
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n
s
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m
m
a
r
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f
o
r
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w
o
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c
e
c
o
s
t
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a
s
e
s
(
t
w
o

p
h
a
s
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s
i
m
p
l
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ﬁ
c
a
t
i
o
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s
)
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e
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r
a
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C
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t
A
r
e
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b
a
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b
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A
P
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t
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i
G
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v
r
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(
r
a
t
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A
T
O
T
=
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A
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l
o
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s
=
i
C
G
v
2 G
,
i
+
C
D
v
2 r
,
i
+
C
B
v
2 B
,
i
D
e
v
i
c
e
M
e
t
r
i
c
N
/
A
M
s
w
1
,
i
=
G
,
i
(
v
r
,
i
(
r
a
t
e
d
)
)
2
A
s
w
M
s
w
2
,
i
=
G
,
i
(
v
r
,
i
(
r
a
t
e
d
)
)
2
C
G
v
2 G
,
i
+
C
D
v
2 r
,
i
+
C
B
v
2 B
,
i
O
p
t
i
m
i
z
e
d
S
w
i
t
c
h
C
o
n
d
u
c
t
a
n
c
e
s
G
∗ i
=
¸ ¸ ¸
a
r
,
i
v
r
,
i
(
r
a
t
)
¸ ¸ ¸
X
t
o
t
P
k

a
r
,
k
v
r
,
k
(
r
a
t
)

G
∗ i
=
¸ ¸ ¸
a
r
,
i
v
r
,
i
(
r
a
t
e
d
)
¸ ¸ ¸
A
t
o
t
√
M
s
w
1
,
i
P
k

a
r
,
k
v
r
,
k
(
r
a
t
e
d
)

√
M
s
w
1
,
k
G
∗ i
=
¸ ¸ ¸
a
r
,
i
v
r
,
i
(
r
a
t
e
d
)
¸ ¸ ¸
E
l
o
s
s
√
M
s
w
2
,
i
P
k

a
r
,
k
v
r
,
k
(
r
a
t
e
d
)

√
M
s
w
2
,
k
O
p
t
i
m
i
z
e
d
O
u
t
p
u
t
I
m
p
e
d
a
n
c
e
R
∗ F
S
L
=
2
X
t
o
t
_
i

a
r
,
i
v
r
,
i
(
r
a
t
)

_
2
R
∗ F
S
L
=
2
A
t
o
t
_
i

a
r
,
i
v
r
,
i
(
r
a
t
e
d
)

√
M
s
w
1
,
i
_
2
R
∗ F
S
L
=
2
E
l
o
s
s
_
i

a
r
,
i
v
r
,
i
(
r
a
t
e
d
)

√
M
s
w
2
,
i
_
2
T
a
b
l
e
3
.
2
.
S
w
i
t
c
h
o
p
t
i
m
i
z
a
t
i
o
n
s
u
m
m
a
r
y
f
o
r
t
w
o
d
e
v
i
c
e
c
o
s
t
m
e
t
h
o
d
s
(
t
w
o

p
h
a
s
e
s
i
m
p
l
i
ﬁ
c
a
t
i
o
n
s
)
39
Tables 3.1 and 3.2 show the form of the cost constraint, the speciﬁc device metrics, the
optimized device values and optimized output impedance of an SC converter for speciﬁc
cost metrics. The general cost columns corresponds to the idealized GV
2
cost metric which
can be used for technologyindependent converter designs or designs involving only a single
device technology. If a diﬀerent device metric must be used to account for varying device
technologies, the areabased costs and lossbased cost columns show the speciﬁc optimization
details for these specialized cost metrics.
The results shown in tables 3.1 and 3.2 show some general patterns about optimiz
ing SC converters. First, capacitance and conductance are analogous in the SSL and FSL
calculations, respectively. The value of each component (capacitance or conductance) is
proportional to the ratio between its charge multiplier and its rated blocking voltage. Ad
ditionally, if a speciﬁc cost metric is used, each component value is proportional to the
square root of that device cost metric. The die area of each component (or whichever
cost corresponds to the method used) is proportional to the charge multiplier and blocking
voltage, and proportional to the square root of the device’s cost metric.
As an example, if an integrated SC converter was made using NMOS and PMOS tran
sistors, either the areabased or lossbased cost metric can be used. Since the performance
of PMOS devices is typically inferior to that of NMOS devices, PMOS devices would ex
hibit a device metric equal to approximately half of the metric of NMOS devices. Thus,
for a converter with all identical switch charge multipliers, the optimallysized PMOS de
vices would be larger than the NMOS devices by a factor of the squareroot of two, but
their conductances would be less than the conductance of the NMOS devices by the same
squareroot of two factor.
This general componentsize optimization can be extended to any device metric as de
sired. It gives a powerful method to size the individual capacitors and switches of an SC
converter and provides substantial insight into its operation and performance. However, to
yield an optimallyperforming converter, the proper ratio of capacitance to switch size must
be chosen, as well as the switching frequency. Section 3.3 performs this optimization con
40
sidering the systemwide tradeoﬀs between switching frequency, capacitor area and switch
area.
3.3 SystemLevel Converter Optimization
In section 3.2, the sizing of individual capacitors and switches in an SC converter was
optimized independently. However, it is also critical to choose a total capacitor area, switch
area and switching frequency to globally optimize the converter. In this section, total
converter performance will be optimized for a given design point. A design point consists of
a speciﬁc output current I
OUT
and input voltage V
IN
. To examine a converter’s performance
over a range of currents and for a speciﬁc output voltage, the converter’s control method
must be also examined. Chapter 5 goes into further depth concerning issues relating to
regulation of SC converters.
In integrated circuit implementations, there are three design parameters. Parameter
A
SW
is the die area of the transistors, including drain and source regions and accounting
for appropriate design rules. Since switch area is measured in mm
2
, the switcharea cost
metric will be used in this optimization. Similarly, A
C
is the die area of the capacitors,
measured in mm
2
. The capacitor area cost metric should be used in this case, adjusting
capacitor density to account for density rules and contact areas. The ﬁnal design parameter
is the switching frequency f
SW
, measured in hertz. This optimization method can be easily
adapted for discrete implementations if desired. Such an optimization method was used in
reference [33] to design a discretecapacitor converter.
3.3.1 Converter Loss Components
The optimization method will be performed by evaluating and minimizing the total
power loss for the given design point with a constraint placed on capacitor area. Five loss
components will be evaluated as part of this power loss. The ﬁrst loss, the SSL impedance
loss is due to the power loss in the component of the output impedance related to charge
41
transfer. The basis of the SSL loss is explained in section 2.1. This component of loss can
be expressed as:
P
SSL
= I
2
OUT
1
2A
C
f
sw
_
i
a
c,i
v
c,i (rated)

_
M
cap,i
_
2
(3.20)
where the optimized output impedance using dieareabased cost metrics is used. The
twophase simpliﬁcation for the impedance components is used in this section, but the
multiphase results can be easily substituted.
The second loss is the FSL impedance loss, which is similarly the power loss due to the
FSL output impedance, described in section 2.2. Using the dieareabased cost metric, the
FSL impedance loss can be written as:
P
FSL
= I
2
OUT
2
A
SW
_
i
a
r,i
v
r,i (rated)

_
M
sw1,i
_
2
. (3.21)
With these two loss factors, it is important to note that they are only exact for operation
in the SSL and FSL asymptotes, respectively. As discussed in section 2.3, a simple addition
of the two loss factors overestimates the total loss. When the SSL and FSL losses are
comparable, they will be combined using the Euclidean norm approximation, given by
(2.33), in this section.
The ﬁnal three losses are associated with various parasitics in the converter. First,
the drain, gate and body capacitances of the transistors make up the switching loss of the
converter. This loss component can be represented as:
P
SW
= f
sw
i∈sw
_
C
G,i
v
2
G,i
+C
D,i
v
2
r,i
+C
B,i
v
2
B,i
_
(3.22)
where C
G,i
, C
D,i
and C
B,i
are the linearized gate, drain and sourceground (body) capac
itance of switch i, respectively. This loss is the basis of the lossbased cost metric used in
the device size optimization in section 3.2.3. Since each of the three parasitic capacitances
are proportional to the total switch size, the parasitic switch loss is proportional to both
switch size and switching frequency.
The second related parasitic loss is due to the bottomplate parasitic capacitance of the
capacitors. This parasitic capacitance is nonnegligible for only integrated capacitors, and
42
represents the capacitance between the physical bottom plate of a metal capacitor and the
substrate, or for MOS capacitors, the junction capacitance between the source and drain
and the substrate. In this model, the top plate capacitance, if it exists, will be lumped with
the bottomplate capacitance. If the ratio between the parasitic capacitance and the main
capacitance is denoted α, the bottomplate loss can be written as:
P
CAP
= f
sw
A
C
M
cap
α
V
2
C,B
v
2
c (rated)
(3.23)
where M
CAP
is the areal capacitor density metric developed in section 3.1 and
M
CAP
/v
2
c (rated)
represents the average capacitor density of the capacitors used. The term
V
2
C,B
is the squaredaverage voltage swing of the bottomplate voltage of the capacitors,
represented by:
V
2
C,B
=
i∈caps
A
c,i
A
tot
v
2
cb,i
(3.24)
where A
c,i
is the area associated with capacitor i, A
tot
is the total die area allocated for
capacitors, and v
cb,i
is the magnitude of the bottomplate swing voltage of capacitor i.
The ﬁnal loss is the equivalent series resistance (ESR) loss. This loss is a combination
of the resistive losses in the capacitors and metal wiring, as switch resistive loss is already
considered. This analysis will model that loss as ﬁxed, as it is not obviously related to
capacitor or switch area. The loss is given by:
P
ESR
= I
2
OUT
R
ESR
(3.25)
where R
ESR
is an equivalent resistance equal to the sum of the parasitic resistance com
ponents, weighted by the square of the ratio between the current ﬂowing through each
resistance to the output current. This method of computing the ESR loss is very simi
lar to determining the FSL output impedance in terms of weighting individual resistance
components.
3.3.2 Numerical Optimization
To ﬁnd the global optimal design, these ﬁve losses can be evaluated over the design
space (the three variables A
SW
, A
C
and f
sw
). Based on these losses, the eﬃciency of the
43
converter can be evaluated. The point which oﬀers the highest eﬃciency is the optimal and
should be the target design point. In many applications, a minimum output voltage is also
important, so an additional constraint can be formulated based on the output impedance.
Finding the optimal point in the design space can be accomplished analytically, but
the equations will quickly become unmanageable unless drastic simpliﬁcations are taken.
Thus, this analysis will be performed numerically via a MATLAB program developed as
part of this work and described in appendix B. The plots in this section are created using
this MATLAB package.
In SC converters where both the switches and capacitors are integrated onto a CMOS
IC, capacitor area becomes the primary constraint in converter performance. Thus, the
optimal capacitance is the largest available, and thus will be considered as an exogenous
variable in this optimization. The total loss of the converter is evaluated over the two
dimensional space of f
sw
(on the xaxis) and A
SW
(on the yaxis). The eﬃciency of an SC
converter is given by:
η =
V
OUT
I
OUT
V
OUT
I
OUT
+P
LOSS
(3.26)
where P
LOSS
is the total power loss given by:
P
LOSS
=
_
P
2
FSL
+P
2
SSL
+P
SW
+P
CAP
+P
ESR
. (3.27)
Equation (3.27) uses the squareroot approximation to the total output impedance as de
scribed in section 2.3.
Figure 3.1 shows a contour plot of the eﬃciency of an example converter with curves
of constant eﬃciency, when evaluated over the design space. The space is divided into ﬁve
regions, each denoting the region where each of the ﬁve losses is dominant. The optimal
point is shown as the circle near the center of the plot. This contour plot illustrates the
performance of a converter, but additionally provides insight into the limiting loss factor
of the converter and where improvements can be made. Since capacitor area is always a
limiting factor in integrated converters, the optimal point will always lie in the SSL loss
region. In ﬁgure 3.1, as the optimal point borders the SSL loss region and the ESR loss
44
10
7
10
8
10
9
10
−4
10
−3
10
−2
Switching Frequency [Hz]
S
w
i
t
c
h
A
r
e
a
[
m
m
2
]
10%
20%
40%
60%
70%
FSL Loss
SSL Loss
ESR Loss
Bottom−Plate
Capacitor
Loss
Switch Parasitic Loss
Figure 3.1. Example SC converter optimization plot
region, the metal ESR is the nextdominant loss factor. Improving the switches will only
aﬀect the eﬃciency by a small amount.
Figure 3.2 shows two example contours illustrating diﬀerent dominant losses. Both of
these plots are based on a 3:1 seriesparallel converter, discussed in section 4.2.4, designed
in a 130 nm CMOS process with metalinsulatormetal (MIM) capacitors. The converter
output is nominally 0.4 V (from an input of 1.2 V) at an output current of 5 mA. Figure
3.2a shows the design optimization using 0.4 mm
2
of capacitor area. The optimal design
point is 77% eﬃcient at a switching frequency of about 60 MHz and switch area of 400
µm
2
. The FSL loss and switch parasitic loss regions border the optimal point, along with
the SSL impedance loss region. Thus, approximately twothirds of the converter loss can be
associated with the switches. The converter’s eﬃciency can be improved by reducing switch
parasitics or otherwise improving switch performance, such as using a smaller gatelength
process. Additionally, more capacitor area can be used to reduce the switching frequency,
and thus switch loss.
45
10
7
10
8
10
9
10
−4
10
−3
10
−2
Switching Frequency [Hz]
S
w
i
t
c
h
A
r
e
a
[
m
m
2
]
40%
20%
60%
70%
70%
60%
40%
Sw i t ch Par asi t i c L oss
C ap aci t or B ot t om − Pl at e L oss
SSL L oss
F SL L oss
(a) switchlimited design
10
6
10
7
10
8
10
−4
10
−3
10
−2
10
−1
Switching Frequency [Hz]
S
w
i
t
c
h
A
r
e
a
[
m
m
2
]
40%
60%
70%
80%
85%
85%
80%
70%
60%
40%
Sw i t ch Par asi t i c L oss
C ap aci t or B ot t om − Pl at e L oss SSL L oss
F SL L oss
(b) bottomplate parasitic capacitance limited design
Figure 3.2. Example eﬃciency contour plots of a 3:1 seriesparallel converter
46
Figure 3.2b shows the same converter designed with the capacitor area increased to 10
mm
2
. The optimal design is 86% eﬃcient at a switching frequency of 4 MHz, using a switch
area of approximately 1200 µm
2
. By increasing the capacitor area by a factor of 25, the
switching frequency is reduced by a similar multiple. Since the eﬀects of switch parasitics
are signiﬁcantly reduced, switch area can be increased to reduce the onstate resistance
(FSL) loss. The optimal point now borders the SSL loss and capacitor bottomplate loss
regions. Thus, improving switch technology or increasing capacitor area will do little to
improve converter eﬃciency. If eﬃciency is to be improved, methods to reduce the bottom
plate parasitic capacitance of the MIM capacitors, or to recover some of the charge stored
on this capacitance must be used.
By numerically evaluating the ﬁve primary losses of an SC converter over the design
space, a graphical analysis method is developed to optimize the performance of a SC con
verter. Besides ﬁnding the optimal design point, the graphical method develops intuition
in the loss factors of a converter and methods of improving the eﬃciency. By ﬁrst ensuring
optimal sizing of individual components and then performing a systemwide optimization,
a fully optimal converter can be developed for any application.
47
Chapter 4
Comparing SwitchedCapacitor
Topologies
In chapter 3, a method was developed to both optimally size the individual components
of a switchedcapacitor (SC) converter and to pick the correct switch size and switching
frequency for maximum eﬃciency. However, the choice of topology has so far been presumed
as given. Choosing the correct topology for a given application and technology is key to an
eﬃcient converter.
This chapter develops metrics to compare the performance of diﬀerent converter topolo
gies. Next, a number of converters in the literature are compared using the general metrics
developed. Since the technology used to implement a converter has a large role in deter
mining the best topology, a look at the compatibility between topology choice and device
technology is also examined. The performance of switchedcapacitor converters is compared
to traditional inductorbased converters, showing that SC converters are optimal in many
applications. Finally, fundamental limits on the performance of both SC and inductorbased
power converters are derived, yielding some powerful insight on the fundamental properties
of SC converters.
48
4.1 Converter Performance Metrics
In order to compare the performance of diﬀerent converter topologies, a few metrics for
converter performance must be developed. Since the comparisons in this chapter are not
tied to a particular technology or implementation, the metrics developed here use the VA
productbased component optimization in section 3.2. Two metrics will be developed and
used, one for the slowswitching limit (SSL) where a converter’s SSL output impedance is
examined, and another for the fastswitching limit (FSL) where a converter’s FSL output
impedance is used.
Each converter metric compares the power handled by a converter to the sum of the
energy or VAbased device metrics. The power that can be extracted from an SC converter
is inversely proportional to its output impedance, and for a constant output impedance,
proportional to the square of the output voltage. Thus, the converter’s GV
2
product is
used to represent its power handling capability.
The SSL converter metric is given by:
M
SSL
=
V
2
OUT
/R
SSL
f
sw
i∈caps
C
i
v
2
c,i
/2
(4.1)
where V
OUT
is the nominal output voltage of the converter and R
SSL
is the optimized SSL
output impedance of the converter, as derived in section 3.2.1. The denominator of the
metric is simply the product between the switching frequency of the converter and the total
energy storage of the capacitors used.
Analogously, the FSL converter metric can be written as
M
FSL
=
V
2
OUT
/R
FSL
i∈switches
G
i
v
2
r,i
(4.2)
where R
FSL
is the optimized FSL output impedance of the converter, as derived in section
3.2.2. The denominator of (4.2) is simply the sum of the GV
2
products of the switches
used in the converter.
In order to quickly evaluate the performance of converter topologies, the converter
metrics will be evaluated in terms of the charge multipliers and blocking voltages. The
49
multiphase optimized output impedances, in (3.11) and (3.17), will be substituted into the
SSL and FSL metrics, given by (4.1) and (4.2), respectively. Through this substitution, the
multiphase converter metrics can be expressed as:
M
SSL
=
4 V
2
OUT
_
i∈caps
v
c,i (rated)
_
n
j=1
_
a
j
c,i
_
2
_
2
(4.3)
and
M
FSL
=
V
2
OUT
n
_
i∈sw
v
r,i (rated)
_
n
j=1
_
a
j
r,i
_
2
_
2
(4.4)
for the SSL and FSL, respectively. Since the component rated voltages are typically propor
tional to the output voltage, this metric is independent of voltage level and is just related
to the charge multipliers and the ratio of the component voltages.
Since the converters compared in this section are all twophase topologies, the SSL and
FSL metrics in (4.3) and (4.4) can be simpliﬁed for a twophase topology. The twophase
SSL and FSL converter metrics are:
M
SSL
=
2 V
2
OUT
_
i∈caps
¸
¸
a
c,i
v
c,i (rated)
¸
¸
_
2
(4.5)
and
M
FSL
=
V
2
OUT
2
_
i∈sw
¸
¸
a
r,i
v
r,i (rated)
¸
¸
_
2
(4.6)
respectively.
These two unitless converter metrics can be used to compare SC topologies at diﬀerent
conversion ratios in the switchlimited and capacitorlimted design spaces. Additionally, the
metrics can be extended towards inductorbased converters to enable a direct comparison
between inductorbased and SC DCDC converters.
4.2 Analysis of SC Topologies
Two metrics have been developed in section 4.1 to compare the performance of various
SC topologies in both the SSL and FSL. In this section, ﬁve SC topologies will be compared,
50
as shown in ﬁgure 4.1. The stepup versions of the converters will be examined here, but the
stepdown converters with the reciprocal conversion ratio exhibit the same performance as
the stepup versions. In general, a conversion ratio of 1:n will be considered, where n is an
integer. Ladder and seriesparallel topologies can be created for a general m : n conversion,
so for those topologies, a rational conversion ratio will be considered.
In the following sections, the capacitor and switch charge multipliers and blocking volt
ages for each topology are found. For this analysis, an input voltage of 1 V is assumed,
so the v
c
and v
r
numbers found are the ratio between the blocking voltage and the input
voltage. The charge multipliers and blocking voltages found in the following sections will
be substituted into (4.3) and (4.4) to ﬁnd the SSL and FSL converter metrics, respectively.
4.2.1 Ladder Topology
The ladder topology [25] is based on two sets (or ladders) of capacitors. In the analysis
of the ladder topology, a general m : n conversion ratio is assumed. For example, ﬁgure 4.2
shows a ladder converter with a 2:5 conversion ratio. One set of capacitors forms a chain
from ground (including the input and output voltage sources). These capacitors establish a
set of DC potentials at integer multiples of the input voltage divided by the conversion ratio
denominator m. The other set of capacitors (referred to as the ﬂying capacitors) shuttle
charge between the DCreferenced capacitors to equalize them. The switches are phased
alternately (oddnumbered switches in phase one, even numbered switches in phase two) to
connect the ﬂying capacitors to the DC capacitors.
The capacitor charge multipliers will be found ﬁrst, followed by the switch charge mul
tipliers. By inspection, C7 in ﬁgure 4.2 has a charge multiplier of a
c,7
 = 1 as it shuttles
charge to the output during phase one. In phase two, the charge from C7 charges C6,
causing capacitor C6 to have a charge multiplier of magnitude 1, but with an opposite sign
to the charge multiplier of C7. The charge multipliers of the capacitors between the input
and output can be found by inspection at each junction. This method yields:
a
c,7
 = a
c,6
 = 1 a
c,5
 = a
c,4
 = 2 a
c,3
 = 2. (4.7)
51
a) Ladder
C 1
C 2
C 3
S 1 S 2 S 3 S 4 S 5 S 6
V
O U T
V
I N
A
B
b) Dickson
V
I N
V
O U T
C 1 C 3
C 2
S 1 S 2
S 3 S 4
S 5 S 6 S 7 S 8
A
B
c) Fibonacci
V
I N
V
O U T
C 1 C 2 C 3
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 1 0
d) SeriesParallel
V
I N
V
O U T
C 1 C 2 C 3
S 1
S 2
S 3
S 4
S 5
S 6
S 7 S 8 S 9
S 1 0
e) Doubler
V
I N
V
O U T
C 1
C 2
C 3
S 1
S 2
S 3
S 4 S 5
S 6
S 7
S 8
Figure 4.1. Five common switchedcapacitor converter topologies in their stepup form
52
C 1
C 2
C 3
S 1 S 2 S 3 S 4 S 5 S 6
V
O U T
V
I N
C 4 C 6
C 5 C 7
S 7 S 8 S 9 S 1 0
Figure 4.2. A 2:5 ladder topology
At this point, the charge multiplier for C1, the capacitor at the lowest potential with
respect to ground, can be found. Since SC converters conserve charge between the input and
output port constrained by their conversion ratio, in (1.1), the input charge can be found
directly in terms of the output charge. If q
out
of charge is delivered to the output during
each period, then n/m· q
out
of charge is pulled from the input. Since the diﬀerence between
input and output charge must ﬂow through ground by KCL, (n/m−1) · q
out
of charge must
ﬂow into ground during each period. This examination yields the charge multiplier for C1,
and the remaining capacitor charge multipliers can be found by inspection:
a
c,1
 = a
c,2
 = (5/2 −1). (4.8)
In general, the ﬁrst 2(m−1) capacitors have charge multipliers of increasing multiples
of (n/m−1), adding up to:
2(m−1)
i=1
a
c,i
 = (n −m)(m−1). (4.9)
Similarly, the last 2(n − m) − 1 capacitors have charge multipliers of decreasing integers,
adding up to:
2n−3
i=2m−1
a
c,i
 = (n −m)
2
. (4.10)
Thus, the sum of the charge multipliers for all the capacitors in the topology is given by:
i∈caps
a
c,i
 = (n −m)(n −1). (4.11)
Since all capacitors block a voltage equal to the input voltage divided by m, or equivalently
the nominal output voltage divided by n, the SSL converter metric for the ladder converter
53
can be found directly from (4.11):
M
SSL
=
2 n
2
(n −m)
2
(n −1)
2
=
2 N
2
(N −1)
2
(n −1)
2
(4.12)
where the second equality substitutes the conversion ratio N, where N = n/m. This SSL
converter metric will be compared to that of other topologies in section 4.3.
The switch charge multipliers can be determined by looking at the charge ﬂow through
each switch with respect to the adjacent capacitor charge ﬂow. For the switches between
output (in the example in ﬁgure 4.2, switches S5 through S10), their charge multipliers are
simply equal to 1. The switch charge multipliers between ground and the input (switches S1
through S4 in the example) must be found by examining the capacitors between the input
and ground. By inspection, each of these switches has a charge multiplier of a
r
 = (n/m−1).
Thus, the sum of the charge multipliers in the topology is given by:
i∈sw
a
r,i
 = 2(n −m) + 2m(n/m−1) = 4(n −m). (4.13)
Since all switches also block a voltage equal to the input voltage divided by m, the FSL
converter metric for the ladder converter can be found directly from (4.13):
M
FSL
=
n
2
32(n −m)
2
=
N
2
32(N −1)
2
(4.14)
where N is the conversion ratio (i.e. N = n/m). At high conversion ratios, this metric
approaches an asymptote at 1/32. This FSL converter metric will be compared to that of
other topologies in section 4.3.
This topology can be modiﬁed by transforming the capacitors by placing them in parallel
instead of series. In this case, each capacitor will support a higher voltage but will have a
smaller charge multiplier. This transformation may be used to achieve a better ﬁt between
the topology and the devices available. For a 1 : n converter, if all capacitors (in each of the
two ladders) are transformed such that their bottom plates share the lowestvoltage node
of each ladder (nodes A and B in ﬁgure 4.1a), the total converter metric will remain the
same. The device utilization of this transformed converter may improve, depending on the
technology used to implement it.
54
4.2.2 Dickson Charge Pump
The Dickson topology [14, 66, 15], shown in ﬁgure 4.1b, improves upon the ladder
topology by using two oppositelyphased ﬂying ladders instead of a single ﬂying ladder
and a DC ladder. Similar to the ladder topology, the oddnumbered switches are turned
on during phase one, and the evennumbered switches turned on during phase two. This
converter is primarily useful for 1 : n ratios (or the stepdown equivalent), so this analysis
will not consider noninteger ratios. In the case where n = 2, the converter degenerates into
a simple doubler stage, so that case will not be examined here, as it is identical to the 1:2
ladder converter.
Similar to the ladder converter, capacitor C3 (the last in the sequence) has a charge
multiplier of 1. By examining the charge ﬂow at each node during each phase, it is straight
forward to determine the charge multipliers of all the capacitors. In this example, the charge
multipliers are:
a
c,1
 = 2 a
c,2
 = a
c,3
 = 1. (4.15)
For a 1 : n converter, the charge multipliers of the n − 1 capacitors increase by integer
steps every other capacitor. The capacitor charge multipliers follow the following sequence,
starting with the capacitor closest to the input source:
a
c
 = {1, 1, 2, 2, · · · } . (4.16)
Thus, the sum of the capacitor charge multipliers is given by:
i∈caps
a
c,i
 =
_
¸
_
¸
_
n
2
−1
4
n odd
n
2
4
n even
(4.17)
Capacitor C1 blocks the input voltage, while each of the other switches blocks twice the
input voltage. The sum of the product between the charge multipliers and blocking voltages
equals:
i∈caps
a
c,i
v
c,i
 =
n
2
−n
2
. (4.18)
Thus, the SSL metric for the Dickson converter is given by:
M
SSL
=
8
(n −1)
2
(4.19)
55
This SSL converter metric will be compared to that of other topologies in section 4.3.
The switch charge multipliers can again be found by evaluating Kirchoﬀ’s Current Law
(KCL) at the nodes of the topology. By inspection, switches S5 through S8 have charge
multipliers equal to 1. Additionally, the charge multipliers of switches S1, S2, S3 and S4
are:
_
a
r,1
 a
r,2
 a
r,3
 a
r,4

_
=
_
¸
_
¸
_
n−1
2
n−1
2
n−1
2
n−1
2
n odd
n
2
−1
n
2
−1
n
2
n
2
n even
(4.20)
The blocking voltages of switches S1 through S5, and the last switch in the chain (S8 in this
example) equal the input voltage, while the other switches block twice the input voltage.
The sum of the product between the charge multipliers and blocking voltages equals:
i∈sw
a
r,i
v
r,i
 = 4n −4 (4.21)
Given this sum, the FSL converter metric can easily be computed:
M
FSL
=
n
2
32(n −1)
2
(4.22)
By inspection, we see that the FSL metric for the Dickson converter is identical to the 1 : n
ladder converter. This FSL converter metric will be compared to that of other topologies
in section 4.3.
This topology can be reconﬁgured by placing the capacitors in each ladder in parallel
instead of series (i.e., placing all bottom plates of the capacitors at nodes A and B in ﬁgure
4.1b). In this case, each capacitor has a charge multiplier of 1, but increasing blocking
voltages. Thus, this version of the Dickson charge pump exhibits the same FSL and SSL
metrics as the seriescapacitor version of the circuit, but may better match a technology.
This topology is typically used to generate the programming voltage on FLASH memory
chips.
4.2.3 Fibonacci Topology
The Fibonacci topology performs the highest conversion ratio for a given number of
capacitors [27] of any twophase topology. Shown in ﬁgure 4.1c, it features a string of
56
similar threeswitch, onecapacitor cells. Each cell is phased oppositely from the one before
it. In this example, the oddnumbered switches are turned on in phase one, and the even
numbered switches are turned on in phase 2.
A Fibonacci converter with k capacitors exhibits a conversion ratio of n = F
k+2
, where
F
k+2
is the k + 2
th
Fibonacci number. For instance, with 3 capacitors, a conversion ratio
of 5 is obtained. The jth Fibonacci number, for j ≥ 1 can be expressed as:
F
j
=
φ
j
−(1 −φ)
j
√
5
= {1, 1, 2, 3, 5, 8, 13, · · · } (4.23)
where φ is the golden ratio (φ = (1 +
√
5)/2 = 1.618...).
For cell j in a kcapacitor converter, counting from the left, its capacitor blocks voltage
F
j+1
= {1, 2, 3 · · · }. Similarly, by inspection, the charge multiplier of capacitor j is F
k−j+1
.
The sum of the elementbased product of the charge multipliers and blocking voltages is
j∈caps
a
c,j
v
c,j
 =
k
j=1
F
j+1
F
k−j+1
. (4.24)
No simpliﬁed form of this sum exists, so (4.24) will be used directly to ﬁnd the SSL converter
metric:
M
SSL
=
2F
2
k+2
_
k
j=1
F
j+1
F
k−j+1
_
2
(4.25)
The conversion ratio and converter SSL metrics are evaluated for the ﬁrst eight converters,
and are as follows:
n = {2, 3, 5, 8, 13, 21, 34, 55} (4.26)
M
SSL
= {8, 2, 1.02, 0.569, 0.376, 0.262, 0.195, 0.150} (4.27)
The SSL metric for this converter is compared with others in section 4.3.
The switch blocking voltages and charge multipliers are found by inspection in terms of
the capacitor voltages and charge multipliers. The complexity of the topology prohibits a
simple closedform solution, so they will be given in terms of a generalizable sequence. For
cell j in a kcell converter, starting from the input side, the three switches in the cell have
57
the following charge multipliers and blocking voltages:
a
r
(j) =
_
F
k−j+2
F
k−j+1
F
k−j+1
_
(4.28)
v
r
(j) =
_
F
j+1
F
j+1
F
j
_
(4.29)
These cellbased charge multipliers and blocking voltages can be concatenated to form the
charge multiplier and voltage vectors for the converter, considering the output switch has
a charge multiplier of 1 and a blocking voltage of F
k
. For example, the charge multipliers
and blocking voltages for the 3cell converter in ﬁgure 4.1c are:
a
r
=
_
3 2 2 2 1 1 1 1 1 1
_
(4.30)
v
r
=
_
1 1 1 2 2 1 3 3 2 2
_
. (4.31)
The sum of the elementbased product of the charge multipliers and blocking voltages is
most easily represented as a numeric sequence computed as the product of (4.30) and (4.31):
i
a
r,i
v
r,i
= {4, 10, 24, 50, 100, 192, 360, 662, · · · } (4.32)
From this numeric sequence, the FSL converter metric can be easily calculated:
M
FSL
= {0.125, 0.045, 0.022, 0.0085, 0.0060, · · · } (4.33)
The FSL metric for this converter is compared with others in section 4.3.
4.2.4 SeriesParallel Topology
The seriesparallel topology, shown in ﬁgure 4.1d, operates by ﬁrst placing the capacitors
in parallel with the input, charging them to the input voltage (in phase one). In phase 2,
the capacitors are placed in series with the input source to transfer charge to the output.
With an (n − m) × m array of capacitors, an m : n ratio converter can be created (where
m < n). Figure 4.3 shows a seriesparallel 2 : 5 converter.
58
φ2
=1
v
r
=4
v
r
=1
v
r
=1
v
r
=1
v
r
=1
v
r
=1
v
r
=1
v
r
=1
v
r
=3
v
r
=2
v
r
=2
φ1
φ1 φ1
φ2
φ2
φ2
φ2 φ2
φ2
φ2
φ1
φ1 φ1 φ1
φ1
φ1
V
m
V
n
v
r
=3 v
r
=4
v
r
=3
v
r
=2
v
r
=1
v
r
Figure 4.3. A 2:5 seriesparallel topology
In phase one, the m·(n−m) capacitors are connected in horizontal strings of mcapacitors
to charge from the input source. In the second phase, the capacitors are connected in vertical
strings of n−m capacitors to transfer charge to the output at voltage n/m.
1
By inspection,
each capacitor supports the input voltage divided by the factor m. Since m identical strings
of capacitors charge the output source, each capacitor has a charge multiplier of 1/m. Thus,
the sum of the charge multipliervoltage products can easily be found as:
i∈caps
a
c,i
v
c,i
 =
1
m
2
· m(n −m) =
n −m
m
. (4.34)
The SSL converter metric can be found directly from (4.34):
M
SSL
=
2 n
2
(n −m)
2
=
2N
2
(N −1)
2
(4.35)
where N is the conversion ratio of the converter, equal to the ratio of n to m. This SSL
converter metric takes a simple form, and approaches an asymptote of 2 at large conversion
ratios. This converter metric is compared with others in section 4.3.
1
As discussed in section A.3, this topology as posed does not guarantee capacitor voltage balancing.
Additional switches must be added to make the converter wellposed, but they carry zero steadystate
current and are thus neglected in this section.
59
A large number of switches are needed to create an m : n seriesparallel converter.
There are (m+ 1)(n −m) switches that turn on in phase one, and m(n −m+ 1) switches
that are on in phase two. By inspection, as each capacitor has a charge multiplier of 1/m,
each switch also has a charge multiplier of 1/m. The switches not connected to one of the
rails (V
m
, V
n
or ground) support one volt, however, some of the border switches block a
higher voltage. The blocking voltages of all the switches in the 2:5 converter are indicated
in ﬁgure 4.3. Through careful accounting, the sum of the switches’ blocking voltages can
be found:
i∈sw
v
r,i
 = 2m(n −m) +n(n −1). (4.36)
Based on the uniform value of a
r,i
 = 1/m and the voltages in (4.36), the FSL converter
metric can be found:
M
FSL
=
n
2
2
_
2(n −m) +
n
m
(n −1)
_
2
(4.37)
This FSL converter metric is compared with others in section 4.3.
4.2.5 Doubler Topology
The doubler topology consists of a number of 1:2 converter stages cascaded as shown
in ﬁgure 4.1e. The oddnumbered capacitors (C1 and C3) are ﬂying capacitors that shuttle
charge up the ladder. The evennumbered capacitors are intermediate DC bypass capaci
tors. The oddnumbered switches are turned on during phase one while the evennumbered
switches are turned on during phase two. For k stages (involving 2k − 1 capacitors), the
converter achieves a conversion ratio of 1 : 2
k
.
For stage j in a kstage doubler topology, the ﬂying capacitor blocks voltage 2
j−1
and
the DC capacitor blocks voltage 2
j
. Note that the DC capacitor on the last stage is omitted.
The charge multiplier of the ﬂying capacitor in stage j is equal to a
c,2j−1
 = 2
k−j
, while
the charge multiplier of the DC capacitor is a
c,2j
 = 2
k−j−1
. For each capacitor (ﬂying and
DC), the product between its charge multiplier and blocking voltage is equal to 2
k−1
. Thus,
60
the sum of the product between the charge multipliers and the blocking voltage equals:
i∈caps
a
c,i
v
c,i
 = (2k −1)2
k−1
. (4.38)
The SSL converter metric can easily be found from (4.38):
M
SSL
=
2
2k+1
(2k −1)
2
2
2(k−1)
=
8
(2k −1)
2
(4.39)
where the conversion ratio n = 2
k
. This SSL converter metric is compared with others in
section 4.3. If multiple interleaved phases are used, the DC capacitors can be reduced in
size, increasing eﬃciency. This transformation is discussed in section 4.3.1.
The switch charge multipliers and voltages can also easily be found in terms of the
capacitor charge multipliers and voltages. In each stage, all four switches block the same
voltage and carry the same amount of charge. Thus, for stage j in a kstage converter, each
switch blocks voltage v
r,i
 = 2
j−1
and has a charge multiplier of a
r,i
 = 2
k−j
. Thus, the
product of charge multiplier and blocking voltage of each switch is 2
k−1
. Thus, the sum of
the product between the charge multipliers and the blocking voltage can easily be found:
i∈sw
a
r,i
v
r,i
 = 4k · 2
k−1
. (4.40)
The FSL converter metric can easily be found from (4.40):
M
FSL
=
2
2k
32 k
2
2
2(k−1)
=
1
8k
2
(4.41)
where the conversion ratio n = 2
k
. This FSL converter metric is compared with others in
section 4.3.
4.3 Comparison of SC Topologies
The SSL and FSL converter metrics for ﬁve SC topologies were calculated in section 4.2.
These metrics are equal to the VA product (or GV
2
product) of each converter divided
by the sum of the GV
2
products of its constitutive components. Thus, the metrics are
ideal for comparing the performance of diﬀerent topologies, where converters with a higher
61
metric will perform better than ones with a lower metric. Figure 4.4 compares the SSL
and FSL metrics for these ﬁve topologies on a logarithmic scale. At a 2 : 1 conversion
ratio, all converters degenerate into the same singlestage doubler structure, and therefore
share the same metric. At high conversion ratios, the performance of the converters diﬀers
signiﬁcantly.
The ladder and seriesparallel converters, analyzed for a general m : n conversion ratio,
are evaluated for halfinteger ratios. All other topologies are evaluated for integers or the
available ratios.
In the SSL metric comparison, shown in ﬁgure 4.4a, the seriesparallel topology has the
best (largest) metric of any of the ﬁve topologies. As predicted, it reaches an asymptote at
2 for large conversion ratios. The ladder topology is the worst, exhibiting an SSL converter
metric 100times lower at high conversion ratios. However, the ladder converter can be
fairly eﬃcient at small conversion ratios (n/m ≈ 1), as seen in section 4.4.
Since the performance metrics of the seriesparallel and ladder topologies were found for
rational conversion ratios, it is important to consider how these topologies perform as the
conversion ratio changes. The expressions for the SSL metric for the seriesparallel topology
in (4.35), and the FSL metric for the ladder topology in (4.14), are only dependent on the
conversion ratio N, not the integer numerator n or denominator m. When considering
these metrics, creating a noninteger conversion ratio does not impact eﬃciency with these
topologies. However, the FSL metric of the seriesparallel topology has a dependency on
n given in (4.37). With a large denominator m, the FSL metric approaches a new limit
inferior to the integer metric by a factor of up to two. Similarly, the SSL metric for the
ladder topology in (4.12) has a similar dependence on the value of n, but the metric does
not approach a new limit. The SSL metric for the ladder topology approaches zero as m and
n increase. These properties of the seriesparallel and ladder converters are important to
consider when making noninteger ratio converters, such as the ladder converter in section
5.4.1.
In the FSL metric comparison, the relative performance of the ﬁve converters is nearly
62
2 4 6 8 10 12 14 16 18 20
10
−3
10
−2
10
−1
10
0
10
1
Conversion Ratio
S
S
L
C
o
n
v
e
r
t
e
r
M
e
t
r
i
c
Ladder
Dickson
Fibonacci
Series−Parallel
Doubler
(a) SSL metric (capacitor limited designs)
2 4 6 8 10 12 14 16 18 20
10
−3
10
−2
10
−1
Conversion Ratio
F
S
L
C
o
n
v
e
r
t
e
r
M
e
t
r
i
c
Ladder
Dickson
Fibonacci
Series−Parallel
Doubler
(b) FSL metric (switch limited designs)
Figure 4.4. Comparison of SSL and FSL converter metrics
63
opposite that in the SSL case. The ladder and Dickson circuit both obtain the best per
formance, reaching a highconversionratio asymptote at 1/32. The seriesparallel topology
does much worse; at a conversion ratio of 1:12, it is ten times worse than the ladder con
verter. The topology choice must be based on technology compatibility and the converter
performance metrics for the arealimiting component type.
4.3.1 Symmetrical Topologies
The DC capacitors in the ladder and doubler topologies reduce the eﬃciency (and con
verter metrics) of those topologies by consuming die area (and contributing their charge
multipliers), but do not act in shuttling charge between the input and output. The perfor
mance of these topologies can be improved by eliminating the DC capacitors. The topology
can be made symmetric by using two topologies, oppositelyphased. The corresponding DC
nodes on the two converters are tied together, placing the DC capacitors in parallel. Since
the charge multipliers in the DC capacitors cancel each other out, the net charge multiplier
through the DC capacitors is now zero. During component optimization, the size of these
capacitors will be zero. Thus, their use is purely for transient absorption, and can be made
much smaller.
Since only the ladder and doubler topologies have DC capacitors, only they can be
transformed. Additionally, since no switches are eliminated, the FSL converter metric of
the transformed converters remain unchanged. For simplicity, only the original half of the
symmetrical circuit will be analyzed. For the entire topology, the number of switches and
capacitors double, but each component has half the original charge multiplier. In general,
by adding interleaved phases, the charge multipliers decrease as the number of components
increase, so the converter metrics remain the same for topologies without DC capacitors.
The symmetric ladder topology now has m− 1 capacitors between the input junction
and ground, with charge multipliers increasing at multiples of n/m − 1. Additionally, it
has n − m ﬂying capacitors connecting the input to the output. For example, the charge
multipliers of capacitors C1 through C4 in the 2:5 symmetric ladder topology, as shown in
64
V
I N
V
O U T
C 1 C 2 C 3 C 4
C 1 ’ C 2 ’ C 3 ’ C 4 ’
φ 1
φ 2
φ 2
φ 2
φ 2 φ 2
φ 2 1
φ 1
φ 1
φ 1 φ 1
φ 1
φ 2
Figure 4.5. Symmetric 2:5 ladder topology
ﬁgure 4.5, are as follows:
a
c,i
 =
_
3/2 3 2 1
_
(4.42)
where only the halfcircuit is considered, neglecting capacitors C1’ through C4’. Thus, the
sum of the switch charge multipliers is given by:
i∈caps
a
c,i
 =
m
2
(m−1)(n −m) +
(1 +n −m)(n −m)
2
. (4.43)
Since all capacitors in the ladder converter block the input voltage divided by m, the SSL
converter metric is given by:
M
SSL
=
8 n
2
(n −m)
2
(m
2
−2m+n + 1)
2
. (4.44)
The symmetric doubler converter is very simple to analyze. For a kstage converter,
there are k ﬂying capacitors (in the halfcircuit), each with a product of the charge multiplier
and blocking voltage equal to 2
k−1
. Thus, the sum of the product between the charge
multipliers and capacitor voltages equals:
i∈caps
a
c,i
v
c,i
 = k 2
k−1
. (4.45)
Based on the sum in (4.45), the SSL converter metric can be found:
M
SSL
=
8
k
2
. (4.46)
These metrics are signiﬁcantly larger than their nonsymmetric counterparts in section 4.2.
65
2 4 6 8 10 12 14 16 18 20
10
−3
10
−2
10
−1
10
0
10
1
Conversion Ratio
S
S
L
C
o
n
v
e
r
t
e
r
M
e
t
r
i
c
Ladder
Symmetric Ladder
Doubler
Symmetric Doubler
Series−Parallel
Dickson
Fibonacci
Figure 4.6. SSL metric improvement with symmetric converters
Figure 4.6 shows the SSL converter metric comparison with the symmetric ladder and
doubler converter shown. The performance of these two converters is improved substantially
over their nonsymmetric forms. For example, the performance of the symmetric ladder
equals the performance of the Dickson circuit, whereas the nonsymmetric ladder topology
was inferior by a factor of four at high conversion ratios. If the increase in component count
is not a problem, as in an IC, using a symmetrical topology can improve eﬃciency.
4.4 Comparison with MagneticsBased Converters
One of the beneﬁts of SC converters is that they can utilize transistors and reactive el
ements better than traditional magneticsbased converters for many applications. In order
to show how this beneﬁt can be achieved, this section compares SC converters to two tradi
tional magneticsbased converters. Speciﬁcally, this section examines a boost converter and
a transformerbridge converter, considering both switch and reactiveelement utilization.
66
+
V
I N
+

V
O U T
D S 1
S 2
L
m : n
+
V
I N
+

V
O U T
(a) boost converter (b) transformerbridge converter
Figure 4.7. Traditional magneticsbased converters
A boost converter, shown in ﬁgure 4.7a, consists of two power switches and a single
inductor. The output capacitor is used as a ﬁlter element. Also, note that the buck
converter is fully equivalent to the boost converter, with diﬀerences in the polarity of current
and power ﬂow [21]. As with the switchedcapacitor circuits, the output capacitor will be
neglected in the analysis. The transformerbridge converter, shown in ﬁgure 4.7b performs
a ﬁxedratio conversion, deﬁned by the turns ratio of the transformer given by m : n. Eight
switches perform the switching and rectiﬁcation at an exact 50% duty cycle. Each of these
two converters will be optimized for a given conversion ratio of N = n/m to fairly compare
with the SC converters.
4.4.1 Switch Comparison
The boost converter has a nominal conversion ratio based on the duty cycle D. The
output voltage of the boost converter is given by:
V
OUT
=
V
IN
1 −D
. (4.47)
Thus, the conversion ratio of the circuit is simply equal to 1/(1 − D) in periodic steady
state. To fairly compare this converter with a ﬁxedratio SC converter, the boost converter
will be optimized for the speciﬁc conversion ratio considered.
For this FSL analysis, strong continuous conduction will be assumed, where the inductor
current I
L
is nearly constant. This assumption gives the most favorable consideration of
67
the inductorbased converter as losses associated with ripple and inductive switching are
ignored.
First, the total GV
2
product of the switches will be constrained to X
tot
during this
optimization. Since both switches block the output voltage of the converter, a constraint is
placed on the total switch conductance:
G
1
+G
2
=
X
tot
V
2
OUT
= (1 −D)
2
X
tot
(4.48)
where the input voltage is normalized to 1. The power loss due to the switch resistance can
be found in terms of the switch conductances, the duty cycle and inductor current:
P
SW
= I
2
L
_
D
G
1
+
1 −D
G
2
_
. (4.49)
By optimizing G
1
and G
2
to minimize the switch conduction loss, the minimal loss can be
found. The optimal switch conductances are proportional to the square root of their duty
cycles. Thus, the optimal switch conductances are given by:
G
1
=
√
D
√
D +
√
1 −D
(1 −D)
2
X
tot
, G
2
=
√
1 −D
√
D +
√
1 −D
(1 −D)
2
X
tot
(4.50)
These conductance values can be substituted into (4.49) to ﬁnd the optimized switchbased
(FSL) power loss:
P
SW
=
1
X
tot
I
2
L
_
√
D +
√
1 −D
_
2
(1 −D)
2
(4.51)
Since I
L
is equal to the output current multiplied by the conversion ratio, an equivalent
FSL impedance can be determined for the boost converter:
R
FSL
=
1
X
tot
_
√
D +
√
1 −D
_
2
(1 −D)
4
. (4.52)
In terms of the conversion ratio N = 1/(1 −D), the FSL impedance is:
R
FSL
=
1
X
tot
N
3
_
√
N −1 + 1
_
2
. (4.53)
The FSL converter metric can be found by substituting (4.53) into (4.2):
M
FSL
=
1
N
_√
N −1 + 1
_
2
(4.54)
68
This FSL metric can be directly compared to the FSL converter metrics for any SC topology.
This comparison is shown in ﬁgure 4.8.
The transformerbridge converter, shown in ﬁgure 4.7b, uses eight switches at a ﬁxed
50% duty cycle. The voltage conversion is performed explicitly by the transformer turns
ratio. Thus, each switch has the same VA product, as voltage is scaled up by the conversion
ratio N and the current is scaled down by N. Without loss of generality, assume V
IN
equals
1 volt. The input switches block 1 volt, while the output switches block N volts. Thus,
the input switches have conductance 1/8, while the output switches will have conductance
1/8N
2
to keep the total switch GV
2
equal to 1. The switch conduction loss can be found
in terms of the input and output currents:
P
SW
= 4 I
2
IN
8
2
+ 4 I
2
OUT
8N
2
2
= 16
_
I
2
IN
+N
2
I
2
OUT
_
. (4.55)
Since the input current is N times larger than the output current, the FSL loss impedance
can be determined by factoring out I
2
OUT
:
R
FSL
= 32N
2
. (4.56)
The FSL converter metric can be found by substituting (4.56) into (4.2):
M
FSL
=
1
32
(4.57)
As expected, since the voltage conversion is solely handled in the transformer, the switch
based converter metric is independent of conversion ratio.
Figure 4.8 compares the FSL (switchbased) converter metrics of the boost converter
and transformerbridge converter to the ladder and seriesparallel SC topologies. The ladder
converter exhibits a superior FSL metric to the other converters at all conversion ratios.
At a conversion ratio of two, the boost performs equally well as both SC converters, but
otherwise lags behind the ladder topology. At high conversion ratios, the boost converter is
substantially inferior to either the SC ladder or transformer bridge converter. Finally the
FSL metric of the ladder topology asymptotically approaches the limit of 1/32, equal to the
transformer bridge converter.
69
1 2 3 4 5 6 7 8
10
−2
10
−1
10
0
Conversion Ratio
F
S
L
C
o
n
v
e
r
t
e
r
M
e
t
r
i
c
Boost
Transformer
SC Ladder
SC Series−Parallel
Figure 4.8. FSL metrics for magneticsbased and SC converters
At large conversion ratios, the SC ladder converter exhibits superior switch utilization
compared with a traditional boost converter. At a conversion ratio of 8, the ladder converter
bests the boost converter by a factor of 4. This performance diﬀerence is proportional to the
conversion ratio at high conversion ratios. The total VA product of the switches in a boost
converter is proportional to the power handled by the converter and the conversion ratio N.
However, the VA product for the switches in a SC ladder approaches a ﬁxed limit in the
highratio asymptote. This diﬀerence allows for the superior performance of SC converters
at high conversion ratios. For integer conversion ratios, the seriesparallel topology is only
slightly lagging with respect to the boost converter. However, the seriesparallel topology
can yield excellent performance due to its excellent performance when reactive elements are
considered, as discussed in section 4.4.2.
70
4.4.2 Reactive Element Comparison
Comparing the use of reactive elements (capacitors and inductors) between SC convert
ers and magneticsbased converters may not be straightforward, but some comparisons can
be made. The SSL metric of an SC converter compares the output resistance of the con
verter with the energy storage of the reactive elements of that converter. Thus, for a given
output power (and assumed converter eﬃciency), the requirements placed upon the reactive
elements for the SC and magneticsbased converters will be examined. Additionally, the
diﬀerences between the energy density of capacitors and inductors will be examined and
incorporated into the reactancebased converter metric.
Since both the inductor in the boost converter and the transformer in the transformer
bridge converter have similar voltsecond product requirements, the size of their respective
magnetic components will be similar.
2
Additionally, inductors are more easily analyzed and
examples of properlysized inductors can be found readily. Thus, only the boost converter
will be compared against SC converters.
First, the inductor energy storage requirements will be calculated. In each switching
period, the inductor current ramps between two values, denoted I
MIN
and I
MAX
. Since
the inductor current equals the input current, the average inductor current must equal the
average output current multiplied by the conversion ratio, assuming that energy is conserved
between the input and output of an eﬃcient DCDC converter. For a given conversion ratio
and output power, the inductor size is minimized by being on the edge of discontinuous
conduction mode (DCM), such that I
MIN
equals zero.
When the converter is operating at the edge of DCM, the peak inductor current is equal
to twice the average input current. Thus, the maximum inductor current is given by:
I
MAX
= 2 I
IN
= 2
I
OUT
1 −D
(4.58)
where D is the duty cycle of the active switch in the boost converter. The inductor current
2
While the transformer for the transformerbridge converter has nearly the same voltsecond rating as
the inductor for the boost converter, it does not need to store any energy, and thus may be smaller than the
inductors shown here. However, most DCDC converters need similar energy storage requirements as the
boost converter, including the isolated ﬂyback and forward converters.
71
ramps from zero to I
MAX
over the ﬁrst half of the switching period. Thus, the required
inductance can be found in terms of the switching frequency:
L = V
IN
D/f
sw
I
MAX
. (4.59)
By substituting (4.58) and (4.47) into (4.59), the maximum inductor energy can be found:
E
L,MAX
=
1
2
LI
2
MAX
=
1
2
V
OUT
D(1 −D)
f
sw
_
2
I
OUT
1 −D
_
(4.60)
E
L,MAX
=
D
f
sw
P
OUT
. (4.61)
Equation (4.61) represents the minimum inductor energy capacity to create a boost con
verter with a speciﬁc duty ratio, switching frequency and output power.
With SC converters, there is no hard relation between capacitor energy and output
power. As capacitor energy is decreased, the converter’s output impedance increases, yield
ing lower eﬃciency. Thus, a ﬁxed eﬃciency (in terms of capacitorbased loss) will be
assumed. In this example, an eﬃciency of 95% will be assumed, as that likely reﬂects the
switch losses of a boost converter designed on the edge of DCM.
Since the output voltage of the converter drops with the output resistance, the eﬃciency
of an SC converter is given by:
η =
nV
IN
−I
OUT
R
OUT
nV
IN
(4.62)
when considering only the SSL power loss. Thus, the required output impedance for a
certain eﬃciency η is given by:
R
OUT
= (1 −η)
nV
IN
I
OUT
(4.63)
The energy storage for a given SC topology to obtain a certain eﬃciency can be found by
substituting (4.63) into (4.1) and solving for E
TOT
:
E
tot
=
2 V
2
OUT
/R
SSL
f
sw
M
SSL
=
2 P
OUT
(1 −η) f
sw
M
SSL
. (4.64)
72
Type Manufacturer Capacitance Dimensions Energy Density
WxLxH [mm
3
] [µJ/mm
3
]
Ceramic TaiyoYuden 22 µF @ 4V 1.6x0.8x0.8 (0603) 344
TaiyoYuden 1 µF @ 35V 1.6x0.8x0.8 (0603) 1196
Tantalum Vishay 10 µF @ 4V 1.0x0.5x0.6 533
Vishay 100 µF @ 6.3V 2.4x1.45x1.1 1037
Electrolytic Kemet 100 µF @ 6.3V 7.3x4.3x2.8 45
Kemet 22 µF @ 16V 7.3x4.3x1.9 94
C.D.E. 210 mF @ 50V 76φx219 172
(a)
Type Manufacturer Inductance Dimensions Energy Density
WxLxH [mm
3
] [µJ/mm
3
]
Shielded SMT Coilcraft 10 µH @ 0.21 A 2.6x2.1x1.8 0.045
Shielded SMT Coilcraft 100 µH @ 0.10 A 3.4x3.0x2.0 0.049
Shielded Coilcraft 170 µH @ 1.0A 11x11x9.5 0.148
Shielded Murata 1 mH @ 2.4A 29.8φx21.8 0.189
(b)
Table 4.1. Energy densities of common (a) capacitors and (b) inductors
73
1 2 3 4 5 6 7 8
10
−2
10
−1
10
0
10
1
Step−up Conversion Ratio
S
S
L
C
o
n
v
e
r
t
e
r
M
e
t
r
i
c
Boost
SC Series−Parallel
SC Ladder
Figure 4.9. SSL metrics for magneticsbased and SC converters
Equation (4.64) represents the total capacitor energy to obtain a given (SSLlossbased)
eﬃciency for a given topology.
However, the comparison between inductor energy storage and capacitor energy storage
must consider the energy density of the particular energy storage devices. Since power in
ductors cannot be practically implemented ondie, a comparison between the energy storage
of discrete capacitors and inductors will be used. Table 4.1 lists the energy density for a
number of readily available capacitors and inductors. By inspection, the volumetric energy
density of capacitors exceeds the energy density of inductors by over a thousand times. The
following comparison will assume a capacitor volumetric energy density of 100 µJ/mm
3
and
a inductor volumetric energy density of 0.1 µJ/mm
3
.
Based on the reactance energy storage requirement derived in this section and the SSL
converter metrics derived in section 4.2, the output power of a converter can be compared
to the volume of its reactive element(s). The boost converter is compared to SC ladder
and seriesparallel topologies in ﬁgure 4.9. An eﬃciency of 95% was assumed for the SC
74
converters. The performance of the SC seriesparallel topology exceeds the power density of
the boost converter by nearly ﬁfty times for a given conversion ratio and physical reactance
volume, due to the signiﬁcant diﬀerence in energy density between capacitors and inductors.
The SC seriesparallel topology is an excellent candidate for IC integration as it exhibits
superior capacitor utilization and adequate switch utilization, as shown in ﬁgure 4.8. Both
the seriesparallel and ladder topologies are advantageous to magneticsbased converters at
moderate conversion ratios. The two comparisons performed in this chapter conclude that
an appropriatelydesigned switchedcapacitor converter can have a higher power density
than a traditional magneticsbased DCDC converter.
4.5 Fundamental Performance Limits
The performance of a number of SC power converters has been compared in both the
SSL and FSL in section 4.3. Additionally, several SC converters were compared with a tra
ditional boost converter and transformerbridge converter. It was found that a SC topology
performed superiorly to the traditional magneticsbased converters across a range of conver
sion ratios. These comparisons raise the question whether a fundamental maximum exists
for the performance metrics of SC converters. Based on the network analysis methods de
veloped by Wolaver in references [60, 61], we can derive a fundamental limit on both the
SSL and FSL converter metrics in terms of the conversion ratio.
A few terms used in the derivation [60, 61] must be ﬁrst explained. In steadystate
converter operation, each component dissipates an average power P, composed of an ac
power P
ac
and a dc power P
DC
. These properties apply to any circuit, not just SC converters.
The average power dissipated by an element is given by:
P = v i (4.65)
where v and i are the instantaneous voltage across and current through the element, re
spectively, and the overline represents the timeaverage of the quantity underneath the
line. This average power can be broken down into two components, dc power and ac power,
75
where the dc power is given by the product of average voltage and average current:
P
dc
= v i (4.66)
and the ac power is simply given by the remainder:
P
ac
= P −P
dc
= (v −v)(i −i). (4.67)
Switches in a DCDC converter, with very low onstate resistance and nearinﬁnite oﬀstate
resistance, have nearly zero average power. Switch power loss is a parasitic eﬀect in these
circuits. For diodes (and other passive switches), which conduct a negative current with
respect to the voltage they block, have negative dc power and positive ac power. They are
designated dc active since they absorb negative dc power. Controlled switches, conducting
a positive current while on and blocking positive voltage while oﬀ, have positive dc power
(and thus negative ac power). These switches are designated as ac active, because they
absorb negative ac power.
4.5.1 SSL Converter Metric Limit
In order to ﬁnd a limit on the SSL converter metric, a relationship between the con
version ratio and output power of the circuit and the reactances must be used. Wolaver
[60, 61] states and proves the following relation:
1
2
k∈caps
v
k
i
k
 ≥
N −1
N
P
OUT
(4.68)
where N is the current or voltage stepup ratio (whichever is greater than one), and v
k
and
i
k
are the instantaneous voltage across and current through capacitor k. For an inductor
based converter, this relation applies over all reactances in the circuit.
The SSL converter performance metric in section 4.1 considers lowload conditions where
the capacitor voltages equal their noload steadystate voltages. The capacitor voltages will
be deﬁned such that they are all positive. In this analysis, the switch voltage drops and
voltage ripple on the capacitors will also be neglected. Thus, the capacitor voltages in (4.68)
76
will be assumed constant, yielding:
1
2
k∈caps
v
k
i
k
 ≥
N −1
N
V
OUT
I
OUT
. (4.69)
In periodic steadystate, the timeaveraged capacitor current is given as the sum of the
charge ﬂows in the capacitor over each clock phase j, multiplied by the switching frequency:
i
k
 =
n
j=1
¸
¸
¸a
j
c,k
¸
¸
¸ q
out
f
sw
=
n
j=1
¸
¸
¸a
j
c,k
¸
¸
¸ I
OUT
. (4.70)
Substituting (4.70) into (4.69) yields a constraint for the capacitor parameters:
k∈caps
v
c,k
n
j=1
¸
¸
¸a
j
c,k
¸
¸
¸ ≥
2(N −1)
N
V
OUT
. (4.71)
To substitute (4.71) into the SSL converter metric, this sum must be further transformed.
A known relationship [10] between l
1
and l
2
norms can be applied to the sum of the squares
of the charge multiplier vector:
n
j=1
_
a
j
c,i
_
2
≤
_
_
n
j=1
¸
¸
¸a
j
c,i
¸
¸
¸
_
_
2
≤ n
n
j=1
_
a
j
c,i
_
2
. (4.72)
Substituting the second inequality in (4.72) into (4.71) yields:
k∈caps
v
c,k
¸
¸
¸
_
n
n
j=1
_
a
j
c,k
_
2
≥
2(N −1)
N
V
OUT
. (4.73)
After this substitution, (4.73) can be substituted into (4.5) to ﬁnd a limit on the SSL
converter metric, given by:
M
SSL
≤
nN
2
(N −1)
2
. (4.74)
where n is the number of phases in the converter and N is the (stepup) conversion ratio.
Through the application of Wolaver’s analysis of dcdc converters based on graph the
ory, a limit on the SSL converter metric of a SC converter can quickly be obtained. This
maximum limit, by inspection, equals the SSL converter metric for the seriesparallel topol
ogy for any given rational conversion ratio. Thus, the seriesparallel circuit achieves the
highest performance (in the SSL) for a given amount of capacitance of any twophase SC
topology.
77
4.5.2 FSL Converter Metric Limit
The fundamental limit on the FSL converter metric can be found via a similar method
to the SSL converter metric limit found in section 4.5.1. Since this analysis considers
DCDC converters using ideal resistive switches, it holds for all SC and magneticsbased
DCDC converters. Because the FSL converter metric examines lowload conditions, the
voltage drop across onstate switches is neglected. Thus, the average power absorbed (or
dissipated) by these switches is zero. If v
j
r,i
is denoted as the blocking voltage of switch i
during phase j, then v
j
r,i
· a
j
r,i
= 0 for all i and j.
As previously introduced, the switches in any SC converter can be divided into two
disjoint sets: the dcactive set, made up of dcactive switches, and the acactive set, made
up of acactive switches. Wolaver [60, 61] states and proves the following relation:
−
i∈R
dc
P
dc,i
≥
N −1
N
P
OUT
(4.75)
where R
dc
is the set of dcactive switches and N is the current or voltage stepup ratio of
the converter (whichever is greater than one). A corollary of (4.75) is:
−
i∈Rac
P
ac,i
≥
N −1
N
P
OUT
(4.76)
where R
ac
is the set of acactive switches and P
ac,i
is the ac power absorbed by switch i.
In this analysis, equal duty cycles will be assumed such that each subperiod has duration
T/n, where n is the number of phases. The dc power absorbed by switch i can be written
as:
P
dc,i
= v
r,i
i
r,i
=
1
n
I
OUT
n
j=1
v
j
r,i
n
j=1
a
j
r,i
(4.77)
where v
j
r,i
and a
j
r,i
are the blocking voltage and charge multiplier of switch i in clock phase j,
respectively. Since the average power of a switch is zero, the ac power dissipated by a switch
is obtained by simply negating the dc power. Since dcactive switches absorb negative dc
power and acactive switches absorb negative ac power, (4.66) and (4.67) can be substituted
into (4.75) and (4.76), respectively. Adding the two resulting equations yields a limit on
78
the sum of the products between the blocking voltages and charge multipliers:
1
n
I
OUT
i∈sw
_
_
n
j=1
v
j
r,i
n
j=1
¸
¸
¸a
j
r,i
¸
¸
¸
_
_
≥ 2
N −1
N
P
OUT
. (4.78)
To further simplify (4.78), the number of phases each switch is on must be known. Let
k
i
be the number of phases that switch i is on, where 1 ≤ k
i
≤ n −1. With this deﬁnition,
and the inequality in (4.72), (4.78) can be simpliﬁed to:
i∈sw
n −k
i
n
v
r,i
¸
¸
¸
_
k
i
n
j=1
_
a
j
r,i
_
2
≥ 2
N −1
N
V
OUT
. (4.79)
To ﬁnd the maximum metric, k
i
must be chosen to minimize the sum. Let k
∗
be the optimal
number of phases (out of n) that each switch is on, which will be optimized later. Equation
(4.79) can then be simpliﬁed to:
i∈sw
v
r,i
¸
¸
¸
_
n
j=1
_
a
j
r,i
_
2
≥ 2
n
(n −k
∗
)
√
k
∗
N −1
N
V
OUT
. (4.80)
Equation (4.80) can be substituted into (4.4) to ﬁnd the fundamental FSL converter
metric limit:
M
FSL
≤
k
∗
(n −k
∗
)
2
4 n
3
N
2
(N −1)
2
(4.81)
where n is the number of phases, k
∗
is the optimal duty cycle (number of phases for which
each switch is on), and N is the stepup conversion ratio. For a general multiphase converter,
k
∗
should be optimized to maximize this limit. By performing this optimization, the optimal
value of k
∗
is found to equal n/3, where n is the number of clock phases. If this value is
substituted into (4.81), the resulting limit equals:
M
FSL
≤
1
27 n
N
2
(N −1)
2
(4.82)
where n is the number of phases in the converter and N is the stepup conversion ratio.
For twophase converters, k
∗
= 1 by necessity, as every switch is on during one phase
and oﬀ during the other. Thus, (4.81) can be simpliﬁed for twophase converters:
M
FSL
≤
N
2
32 (N −1)
2
. (4.83)
79
This limit for the FSL converter metric sets a fundamental limit of converter performance.
The FSL converter metric for the ladder topology is equal to this fundamental limit for
twophase converters. Thus, the ladder topology and its variations utilize switches better
than any other twophase topology. These fundamental limits can be applied as well to all
DCDC converters, showing that no magneticsbased converters could have a higher FSL
metric than the ladderbased SC converter.
80
Chapter 5
Regulation of SwitchedCapacitor
Converters
While switchedcapacitor (SC) DCDC converters transform voltages at ﬁxed conver
sion ratios, many applications require output regulation to deliver a constant output voltage
against variations in line voltage and load current. Output regulation is necessary for sen
sitive loads, such as sensors or radios, where small changes in output voltage can aﬀect
functionality. Additionally, by maintaining a constant output voltage, the supply rail of the
load can be maintained at the minimum tolerable voltage, minimizing current consump
tion. In energyharvested or batteryoperated devices, minimizing current consumption by
maintaining a low but constant voltage rail can improve device lifetime signiﬁcantly. Fi
nally, in some applications, where CMOS devices are operated close to their rated voltage,
voltage regulation is required to ensure the devices are not overstressed with variation in
line voltage.
Unlike inductorbased converters, where the conversion ratio is arbitrarily set by duty
cycle, SC converters exhibit one (or several) conversion ratios. Further regulation is per
formed by modulating the output resistance of the converter in response to changing line
81
voltage or load current vary. The output of an SC converter is given by:
V
OUT
= nV
IN
−i
OUT
R
OUT
(f
sw
, D
i
G
i
). (5.1)
Equation (5.1) shows four variables that can be used to control the output voltage of an SC
converter. First, the conversion ratio n is a function of topology, but can be chosen from a
discrete set for variableratio converters, as described in section 5.4. The remaining three
variables, switching frequency f
sw
, switch duty cycle D
i
and switch conductance G
i
, aﬀect
the output resistance of the converter.
By changing the converter’s output resistance, the output voltage of the converter will
vary with the product between output current and resistance. Regulation by varying out
put resistance is lossy, as power is dissipated to create this voltage drop. At ﬁrst look, this
method of regulation is equivalent to using a linear lowdropout regulator (LDO), however,
no additional power components are used and switching losses can be reduced. Addition
ally, by modulating output resistance, the converter becomes much more sensitive to quick
changes in load, and the converter’s controller must be suﬃciently fast to handle these
transients.
Since the load range of a SC converter often varies over many orders of magnitude,
the output resistance must also be modulated over many orders of magnitude in order to
eﬀect voltage regulation. Out of the three variables aﬀecting output resistance (f
sw
, D
i
and G
i
), only switching frequency can be easily varied over the necessary range. Thus, in
the regulation schemes discussed in this chapter, switching frequency will be the primary
adjustment.
Figure 5.1 shows the eﬃciency of a 2:1 ratio converter using three control schemes. The
converter is optimized for operation at 1 amp (denoted by the star). When running the
converter open loop, ﬁxing the switching frequency and switch size at the design point, the
output voltage is unregulated and eﬃciency decreases quickly at low power levels. Using sim
ple frequency modulation (shown by the solid curve), output regulation is performed while
varying frequency roughly proportional to output power. By keeping transistor switching
loss, discussed in section 3.3.1, proportional to output power, eﬃciency is held nearly con
82
10
−3
10
−2
10
−1
10
0
60
65
70
75
80
85
90
95
100
Output Power [W]
E
f
f
i
c
i
e
n
c
y
[
%
]
No Frequency Scaling
Linear Frequency Scaling
Optimal Frequency and Switch Sizing
Figure 5.1. Eﬃciency during power backoﬀ; 2:1 converter
stant across the range of power levels. Since switch conductance losses are reduced by the
square of output current, eﬃciency at low power level is increased slightly over the eﬃciency
at the design point.
By dynamically adjusting both switch size and switching frequency as output power
varies, the optimal design at all power levels can be obtained. At low power levels, eﬃciency
increases dramatically, only limited by the capacitor bottomplate parasitic. This control
method, if practical, promises a high eﬃciency at power levels below the design point.
Additionally, varying switch size has other advantages, such as output ripple control, as
discussed in section 5.1.
5.1 Output Ripple of Multiphase Converters
The ripple at the output of an SC converter can aﬀect both the performance of the
converter and the operation of the load. Many analog and digital loads are very sensitive
83
to ripple or noise on the supply rail, so the converters supplying these loads must reduce
ripple as much as possible. However, integrated switchedcapacitor converters are infamous
for their large ripple voltage levels [6]. This section will examine the eﬀects of using an SC
converter with multiple interleaved phases on the output voltage ripple.
Output ripple in an SC converter is attributable to the impulselike charge transfer in
SSL operation. While the analysis in chapter 2 used a voltagesource load, real converters
typically have resistive loads (or currentsourcelike loads) with an output capacitor. The
output capacitor ﬁlters the impulses of charge from the SC converter while supplying a near
constant current to the load. In the worst case, where a stepup converter delivers charge
to the load once per period, and is operating solely in the SSL, the converter’s peaktopeak
output voltage ripple would equal:
V
R
=
I
OUT
f
sw
C
OUT
. (5.2)
Since the switching frequency of a converter is roughly proportional to the output current,
the output ripple amplitude will remain constant over a wide range of power levels, and is
simply related to the converter design and output capacitance.
Since practical ripple requirements dictate that the output capacitor must be large
for many applications, it adds signiﬁcantly to the die or board area requirement of the
converter. For many applications, the required output capacitance would dominate the
ﬂying capacitors. Methods of reducing the size of this capacitor are necessary for ondie
converters [6].
This section examines using multiple interleaved phases to reduce the ripple voltage
without increasing the size of the output capacitor. Just like highperformance inductor
based converters, using interleaved phases reduces the output ripple for a given switching
frequency. In an SC converter using N interleaved phases, the topology used is replicated
N times and each component linearly scaled by 1/N in size. The clock feeding each of
the interleaved phases is oﬀset by an angle of 360
◦
/N. In SSL operation, by having N
interleaved phases, the output ripple is reduced by a factor of N. A practical limit to the
number of interleaved phases used arises when the control and gatedrive power of each
84
interleaved phase becomes a signiﬁcant component to the power loss, negatively impacting
eﬃciency. Section 8.2.2 discusses the optimal sizing of an individual interleaved phase cell.
At the maximum switching frequency and load, the converter is usually designed to
operate in the region between the SSL and FSL, based on the optimization in section
3.3. In the operating region between the SSL and FSL, the currents ﬂow in exponentially
decaying patterns instead of impulses. When multiple interleaved phases are used in this
operating region, the current pulses overlap, greatly reducing the amplitude of the ripple
voltage at the output. To illustrate this eﬀect, the ripple voltage will be computed for an
Ninterleavedphase converter over a range of switching frequencies.
In examining the ripple voltage of an SC converter, a simple 2:1 stepdown converter
with four interleaved phases is considered. Each interleaved phase is an instantiation of
the 2:1 converter each phased 90 degrees apart. In each interleaved phase, each of the four
switches has an onstate resistance of R
ON
and the single ﬂying capacitor has capacitance C.
Thus, during each phase transition, an exponentiallydecaying pulse of charge is transferred
from the input to the output. The time constant τ of this decay is equal to 2 R
ON
C, as
the capacitor charges and discharges through two series switches.
Figure 5.2 shows the output voltage ripple and the current delivered to the output of the
converter in each of the four interleaved phases. In the fullload case where the switching
period is on the order of the RC time constant, the interleaved current pulses average to
a lowamplitude output current, thus dramatically reducing the output ripple. At lower
output loads and switching frequencies (in ﬁgure 5.2b), the currents in the four phases are
nearly impulsive, allowing the full SSL ripple voltage (in (5.2)) to occur at the output.
Figure 5.3 shows the output voltage ripple of the 2:1 converter as the output power
changes using either two, four or eight interleaved phases. In this example, the output
voltage is regulated at a constant 0.9 V for a 2 V input by controlling the switching frequency.
At full load (near 1A), the switching frequency is suﬃciently fast, compared to the time
constant τ = 2R
ON
C, that the ripple is only a few millivolts. At lower power levels, the
ripple voltage reaches an asymptote of approximately 25 mV with four interleaved phases,
85
0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 1 . 6 1 . 8 2
0
0 . 2
0 . 4
0 . 6
T i m e [ µ s]
P
h
a
s
e
C
u
r
r
e
n
t
s
[
A
]
0
5
1 0
1 5
2 0
2 5
3 0
O
u
t
p
u
t
R
i
p
p
l
e
[
m
V
]
(a) Full load, T = 1 µs
0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0
0
0 . 2
0 . 4
0 . 6
T i m e [ µ s]
P
h
a
s
e
C
u
r
r
e
n
t
s
[
A
]
0
1 0
2 0
3 0
O
u
t
p
u
t
R
i
p
p
l
e
[
m
V
]
(b) Onetenth load, T = 10 µs
Figure 5.2. Current transfer and output voltage ripple waveforms of a regulated fourphase
2:1 converter
86
10
−3
10
−2
10
−1
10
0
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05
R
i
p
p
l
e
V
o
l
t
a
g
e
[
V
]
Output Current [A]
N = 8
N = 4
N = 2
Figure 5.3. Output voltage ripple of an Ninterleavedphase 2:1 converter
set by (5.2). At full load, the output voltage ripple can actually be reduced by a factor of
the square of the number of interleaved phases, as the currents in each phase combine.
The output voltage ripple of an SC converter has been examined in terms of the number
of interleaved phases and the switching frequency. The use of multiple interleaved phases
reduces the size of each charge pulse and reduces the output ripple in the SSL by a factor of
N, where N is the number of interleaved phases. Additionally, near the maximum switching
frequency, the converter operation point leaves the SSL, and the output voltage ripple can
be empirically reduced by a factor of N
2
. In this region, the converter currents are no
longer impulses but instead decaying exponentials in each period. As current is delivered
to the output capacitor more uniformly, output voltage ripple is reduced. Using multiple
interleaved phases can reduce the ripple at the output of an integrated SC converter.
87
5.2 Hysteretic Feedback Methods
A traditional control method for an SC converter may include a linear compensator
and a voltagecontrolled oscillator (VCO). However, obtaining stability and good transient
response over varying load conditions using such a control method is diﬃcult and requires
sensing of the output current, as described in section 5.3. The simplest voltage regulation
method for SC converters uses hysteresis for frequency control instead of a control method
based on a smooth compensator. Two methods for hysteretic control will be presented,
the traditional hysteretic feedback scheme, using upper and lower hysteretic bounds, and
a novel lowerbound control method.Both methods use voltage references and comparators
to create and detect the voltage limits, and then change the state of the converter. By
eliminating ﬁlters in the converter control, the quiescent current of the controller can be
dramatically reduced. Additionally, as the controller has no analog state, the converter can
react to very fast loading and unloading transients.
The PicoCube power conversion IC, as described in chapter 7, utilizes a doublebound
hysteretic control scheme. A block diagram of this control scheme is shown in ﬁgure 7.12.
This converter uses small (approximately 1 nF) internal capacitors with a larger exter
nal capacitor (1 µF). Thus, the inherent ripple voltage at the output is negligible. An
internallygenerated reference voltage is used to create two hysteresis bounds, separated by
approximately 20 mV for the 2.1V rail, and 10 mV for the 0.7 V rail. When the output
voltage reaches the upper limit, the converter clock (about 30 MHz) shuts oﬀ, and the out
put capacitor is discharged by the load current. When the output voltage dips below the
lower threshold, the converter is enabled again, charging the output capacitor. Assuming
the load current remains below the current delivered to the output at maximum switching
frequency and minimum voltage levels, the output voltage will be held between the two
hysteresis limits.
Figure 5.4 shows a load transient for the PicoCube power conversion IC from experi
mental data. To the left and right of the transient, the converter runs controlled, where
the output is (roughly) constrained within the hysteresis bounds. Since the PicoCube IC
88
− 4 − 2 0 2 4 6 8 1 0 1 2 1 4
1 . 8
1 . 8 5
1 . 9
1 . 9 5
2
2 . 0 5
2 . 1
2 . 1 5
2 . 2
2 . 2 5
2 . 3
T i m e [ m s ]
O
u
t
p
u
t
V
o
l
t
a
g
e
[
V
]
I
L
= 2 µ A
I
L
= 1 m A
I
L
= 2 µ A
Figure 5.4. Doublebound hysteresis feedback for the PicoCube application
uses sampled comparators instead of continuoustime comparators, the hysteretic bound
transitions are delayed to the next clock cycle before the clock changes mode. Thus, the
exact levels of the output transitions are irregular and the ripple magnitude can exceed the
set hysteretic bounds.
In the center of the waveform, the load current exceeds what the converter can deliver
at full load at the lower hysteresis bound. The output voltage falls below the threshold,
and the converter operates at the full switching frequency of 30 MHz until the load is
reduced. This operating condition represents an unusual condition when either the load
current exceeds the design point or the input voltage falls below the minimum limit. In
the latter case, this operating condition can be detrimental to battery lifetime as excess
gate power is consumed. A lowvoltage protection circuit should be added to any system
using this type of control to prevent a rechargeable battery from being destroyed in this
condition.
In converters where the output capacitance is on the same order of magnitude as the
89
+
D Q D Q D Q
V
R E F
V
O U T
φ 1 φ 2 φ N
Figure 5.5. Lowerbound hysteretic feedback controller
ﬂying capacitors, the output ripple can be signiﬁcant. This ripple can be used directly to
control the converter. During each phase transition in an interleaved phase, a packet of
charge is delivered to the output.
1
This charge packet raises the voltage on the output
capacitor by a certain amount, proportional to the drop across the converter’s internal
output impedance. If a highspeed comparator is used to detect when the output falls
below a certain level, a hysteretictype controller can be developed. With this simple control
scheme, shown in ﬁgure 5.5, the output voltage can be held to a certain level while keeping
ripple at a minimum.
The lowerbound feedback method does have several downsides that would have to be
considered in any implementation. First, the comparator must be very fast to prevent
the output from falling signiﬁcantly below the reference. Second, if the output voltage
remains below the reference after a switching event, or starts up below the reference, the
comparator will be stuck on, preventing any switching action. Additional logic must detect
this condition and inject a suﬃcientlyfast clock to boost the output voltage above the
reference. The switching frequency using this lowerbound control method is bounded only
by comparator speed, and is highly sensitive to noise. Noise also causes an increase in
the magnitude of the voltage ripple, however the output maintains regulation regardless of
noise.
The lowerbound hysteretic feedback method is used in the multiratio converter pre
1
If a topology is chosen that transfers charge to the output during only one phase, a symmetrical topology
can be created as in section 4.3.1 which transfers charge to the output on both phases.
90
0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0 . 1 2 0 . 1 4 0 . 1 6 0 . 1 8 0 . 2
1
1 . 2
1 . 4
1 . 6
1 . 8
T i m e [ m s]
O
u
t
p
u
t
V
o
l
t
a
g
e
[
V
]
0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0 . 1 2 0 . 1 4 0 . 1 6 0 . 1 8 0 . 2
0
0 . 0 5
0 . 1
0 . 1 5
0 . 2
O
u
t
p
u
t
C
u
r
r
e
n
t
[
A
]
Figure 5.6. Waveform from lowerbound feedbackbased converter
sented in section 5.4. A discretecomponent prototype was developed with an integrated
SC converter designed for handheld applications. Figure 5.6 shows the output voltage rip
ple (with a small output capacitor) as load current varies between full load and 10% load.
At lower load currents, the ripple frequency falls proportional to the load, and the ripple
amplitude gets slightly larger, as discussed in section 5.1. For this converter to be practical
for many applications, the ripple amplitude would have to be reduced signiﬁcantly via a
larger output capacitor or multiple interleaved phases.
5.3 System Modeling
SC converters are typically regulated by varying switching frequency. This method of
regulation yields inherently nonlinear dynamics which can be diﬃcult to model. This section
will develop a simpliﬁed model of an SC converter, enabling the design and simulation
of control methods involving frequency modulation, pulsewidth modulation and switch
resistance modulation [18].
91
+
n V
I N
C
e q
R = 0 R
e q
C
O
i
O U T
( t )
Figure 5.7. Idealized dynamics model for system modeling
The simpliﬁed circuit model for an SC converter used in this section is shown in ﬁgure
5.7. This model is the simplest model including the eﬀects of both the SSL and FSL output
impedance. The model uses a single capacitor of value C
eq
to shuttle charge between the
input and output ports with a series resistance R
eq
. The output is modeled as a current
source with bypass capacitance C
O
. These equivalent component values can be found in
terms of the SSL and FSL output impedances:
C
eq
=
1
f
sw
R
SSL
, R
eq
= R
FSL
. (5.3)
While this model is suﬃcient for modeling the control of many converters, an exact dynamic
model is derived in appendix A.4. Each switching period will be modeled as a single sample
in a discretetime system. In each sample period, the output capacitor is linearly discharged
by the output current source and charged through the RC network made with the ﬂying
capacitance and series resistance. A discretetime system model can be made from this
qualitative description as follows:
V
OUT
[k + 1] = V
OUT
[k] +
1
C
O
_
−i
OUT
[k]T[k] + (nV
IN
−V
OUT
[k]) C
eq
_
1 −e
−T/2ReqCeq
__
(5.4)
where T is the duration of the switching period.
Since the primary method of regulation for SC converters is frequency modulation, the
switching period T will be the primary control handle. In this section, the switch resistance
R
eq
will be held constant, although it can be varied linearly [18]. In addition, operation in
the SSL will be assumed such that the exponential factor 1 −exp (−T/2R
eq
C
eq
) is equal to
one.
A compensator function T = f(V
OUT
−V
REF
) = f() must be constructed to implement
92
the desired control law. Since the load current can vary over many orders of magnitude,
and the relation between output voltage and period in (5.4) is nonlinear, a linear compen
sator function cannot guarantee stability and acceptable performance at all load levels. By
inspecting (5.4), if the compensator function included the output current, the system can
be made linear via feedback linearization. The use of a dynamic control method to regulate
the output voltage requires the measurement or estimation of the output current to ensure
stability and adequate performance.
If the compensator f() is in the form f() = f
2
()/I
OUT
, the system becomes linear in
terms of the new input f
2
(). While f
2
() can be chosen to yield good dynamics, additional
considerations will have to be made for a real system. For example, bounds on the switching
frequency must be used and the dynamics of a VCO must also be considered. Finally, for
correct operation, a limit to the slew rate of the output current must be made to ensure
stability of the control system.
5.4 A MultiRatio Converter for Portable Electronics
The regulation methods for SC converters discussed so far have entailed modulating the
output impedance to regulate the output voltage. These methods are inherently lossy and
are only eﬃcient near the optimal operating point of the converter. For a wide regulation
range, a diﬀerent method must be used. This section describes an SC converter designed
for a portable electronics application where the input can vary between 2.1 and 4.8 V, an
extended lithiumion battery voltage range.The output of the converter is a constant 1.2 V
to supply ICs fabricated in a deep submicron process. To ensure high (greater than 75%)
eﬃciency over this range, numerous conversion ratios, in addition to the other regulation
methods mentioned in this chapter, must be used. Multiratio regulated SC converters exist
in commercial parts [43, 32], but are designed for neither ultrahigh eﬃciency nor the use
of integrated capacitors.
93
S 1
S 2
S 1 1
S 1 2
S 1 3
S 1 4
S 1 5
S 1 6
C 1
C 6
C 7
C
O 1
C
O 6
C
O 7
C
O 8
V 8
V 7 / V
O U T
V 6
V 5 C 5
C 2
C
O 2
C
O 5
S 3
S 4
S 9
S 1 0
S 1
S 2
S 1 1
S 1 2
S 1 3
S 1 4
S 1 5
S 1 6
C 1
C 6
C 7
C
O 1
C
O 6
C
O 7
C
O 8
V 8
V 7 / V
O U T
V 6
V 5
C 5
C 2
C
O 2
C
O 5
S 3
S 4
S 9
S 1 0
(a) nominal topology (b) with transformed capacitors
Figure 5.8. {5, 6, 7, 8} : 7 ladder topology stage
5.4.1 Topology Description
To perform the conversion, a twostage converter is used. The ﬁrst stage, in ﬁgure 5.8,
is an eightrung ladder topology with an input multiplexer applying the input to one of four
taps (denoted V5 through V8). The output is taken from V7 such that the ladder converter
provides the conversion ratios 5:7, 6:7, 1:1 and 8:7. This intermediate rail is fed into the
3:1 Dickson converter, shown in ﬁgure 5.9a. By changing the way the switches are clocked,
the Dickson stage can also perform a 2:1 conversion ratio. Thus, the two stages combined
94
V
I N
V
O U T
C 1
C 2
S 1
S 2
S 3
S 4
S 5
S 6
S 7
Switch 3:1 2:1
S1 φ1 φ1
S2 φ2 φ2
S3 φ2 φ1
S4 φ1 φ2
S5 φ2 φ2
S6 φ1 ON
S7 φ2 φ1
(a) Dickson topology (b) Switch phases vs. conversion ratio
Figure 5.9. 3:1, 2:1 Dickson topology stage
can provide the conversion ratios 10:7, 12:7, 2:1, 15:7, 16:7, 18:7, 3:1 and 24:7. These eight
conversion ratios span the necessary input range nicely.
By using the twostage design, many conversion ratios can be obtained at high eﬃciency.
The ﬁrst stage, while providing ﬁne regulation, remains eﬃcient since its conversion ratios
remain close to 1:1. The ladder provides high eﬃciency at conversion ratios near 1:1, despite
its drop in eﬃciency at higher ratios, as shown in section 4.2.1. The second stage provides
the majority of the voltage conversion at relatively coarse 3:1 and 2:1 conversion ratios.
However, the eﬃciency of the Dickson converter at these conversion ratios is high.
The capacitors in the ladder converter (in ﬁgure 5.8a) only support a fraction of a volt
as shown. To achieve a better capacitor utilization, the capacitors are transformed to span
the maximum number of rungs supported by the device’s blocking voltage. The capacitor
arrangement is optimized via computer iteration to determine the conﬁguration with the
lowest average sum of the capacitor charge multipliers. In this arrangement, each switching
node remains connected to a capacitor, and each capacitor has one terminal at the node
95
shared by S13 and S14, when supported by the capacitor’s blocking voltage. The result
of this optimization is shown in ﬁgure 5.8b, and reduces the average sum of the capacitor
charge multipliers by approximately 75%. The DC capacitors can also be reconﬁgured for
optimal performance, but for this application, several of these topologies will be placed
in parallel as interleaved phases, allowing the size of the DC capacitors to be signiﬁcantly
reduced. In this manner, the ladder stage has the minimal SSL impedance for a given
capacitor die area.
The target process for this converter is a 65 nm CMOS process with the ability to accept
a 5V I/O rail. In this design, metalinsulatormetal (MIM) capacitors are considered, as
they are built in upper metal layers, and thus have low bottomplate parasitic capacitances
(approximately 0.3% to 1% of the main capacitance). Native NMOS transistors are used
for both topologies, and are cascoded to block the necessary voltage to implement switch S6
in the Dickson stage. The gate of the cascode transistor of S6 can be biased via a doubled
version of the output voltage (i.e. a constant 2.4 V). A die area of 3 mm
2
for both switches
and capacitors is considered for a 100 mW application.
Figure 5.10 shows the calculated eﬃciency of this converter. The eﬃciencies of the
optimal points for the eight conﬁgurations are shown as circles. By performing frequency
modulation, regulation is possible over the entire range of input voltage. Since the optimal
eﬃciency of the 15:7 conﬁguration is below the regulation curve, it is globally inferior, and
is thus never used.
5.4.2 Control Method
Performing output regulation with this converter is signiﬁcantly more complicated than
a singleratio converter. An interior analog loop implements a lowerbound hysteretic control
scheme to regulate the output voltage for a single conﬁguration. A block diagram of the
entire control scheme is shown in ﬁgure 5.11. The remainder of the controller is a ﬁnite
state machine (FSM) to control the conversion ratio, implemented in the digital domain.
Analog to digital converters (ADCs) convert the input voltage and output current to digital
96
2 2 . 5 3 3 . 5 4 4 . 5 5
6 5
7 0
7 5
8 0
8 5
9 0
I n p u t V o l t a g e [ V ]
1 0 : 7
1 5 : 7
1 2 : 7
1 8 : 7
2 : 1
3 : 1
1 6 : 7
2 4 : 7
E
f
f
i
c
i
e
n
c
y
[
%
]
Figure 5.10. Predicted eﬃciency of multiratio converter
values. The output current then passes through a logarithmic ﬁlter, as only its approximate
magnitude is important.
The ﬁrst component of the digital control system is the frequency counter and compara
tor. The counter counts the number of phase transitions in a given period, set by a divided
system clock. The maximum converter frequency is set by a constant maximum count. The
maximum frequency comparator X6 indicates that the input voltage fell below the nominal
range for the working conﬁguration (or ratio), so the conﬁguration must be changed to the
next lowest conversion ratio. The comparator triggers the up/down counter to decrement
the conﬁguration by one step.
As the converter conﬁguration is changed to a lower conversion ratio, the sampled input
voltage is written in a lookup table (LUT) indexed to the previous conﬁguration ratio
and output current. The LUT stores the maximum input voltage to be used for the pre
transition conﬁguration, based on the output current level. As the input voltage rises above
this threshold for a given conversion ratio, the digital comparator X10 trips and triggers
97
+
D Q D Q D Q
V
REF
V
OUT
φ 1 φ 2 φ N
in
reset
out
counter
/2
n
(~ 500MHz)
System Clock
+
decrement
up/down counter
increment
(limit 17)
Config.
Topology
f
MAX
V
IN
LUT
write d
IN
x
y
d
OUT
+
log
2
I
OUT
V
IN
Lowerbound feedback
Conversion ratio FSM
X1
X2a X2b X2n
X3
X4
X5
X6
X7
X8
X9
X10
Figure 5.11. Controller for the multiratio converter
98
2 2.5 3 3.5 4 4.5
10
−4
10
−3
10
−2
10
−1
Input Voltage [V]
O
u
t
p
u
t
C
u
r
r
e
n
t
[
A
]
1
0
:
7
1
2
:
7
2
:
1
1
6
:
7
1
8
:
7
3
:
1
2
4
:
7
10 MHz
1 MHz
100 kHz
Figure 5.12. Operation regions for the multiratio converter
the up/down counter to switch to the next highest conversion ratio. Some hysteresis is
incorporated into the system to avoid oscillation between conversion ratios. This system
ensures the use of the proper conversion ratio across the input voltage range while using
minimal digital resources. The control system could be improved by changing the maximum
switching frequency based on output current to optimize the conﬁguration transition points.
The operation of the converter, considering both switching frequency and conversion
ratio, can be examined across the space of operation. Figure 5.12 shows this space with
input voltage on one axis and output current on the other. The regions corresponding to
each conversion ratio are shown separated by the dark lines. The conversion ratio transitions
correspond to a maximum switching frequency threshold of 100 MHz. Three constant
frequency contours are also shown on this plot as narrow lines. This plot can be used to
create a feedforward control system by storing the correct conversion ratio or conﬁguration
in a ﬁxed twodimensional lookup table. The twodimensional lookup table X9 stores this
feedforward data through online training.
99
5.4.3 Experimental Results
This design was not fabricated in the intended process, but a prototype was created
using discrete components. The same voltage and power speciﬁcations were maintained,
corresponding to similar switch conductance requirements. For ease of control, Maxim
MAX4685 analog multiplexers were used for the power switches. The onstate resistance
of each of these switches varies between 0.3 – 0.5 ohms, suitable for this application. Two
interleaved phases were used for the ﬁrst stage, while four were used for the second stage to
reduce output impedance and ripple magnitude. The capacitors were scaled up by a factor
of approximately 500, from a few nanofarads to a few microfarads. Thus, the switching
frequency is similarly reduced by a factor of 500 to a few hundred kilohertz.
The control was performed using a discrete opamp, the National LMV7219, and an
FPGA board based on a Xilinx Vertex 4 for the digital portion of the control. All the
digital components of the control were implemented using Verilog. The test board also
included a programmable input regulator and programmable load resistance for automated
testing. The programmable source and load were also controlled by the same FPGA. The
control logic occupied a very small fraction of the FPGA and could easily be synthesized
and integrated onto the same IC as the power circuitry.
Figure 5.13 shows the eﬃciency and output voltage of running the converter at full
load while varying the input voltage. While the mean output voltage varies due to varying
ripple amplitude, the lower bound of the ripple is successfully regulated at 1.2 V. This is a
consequence of the lowerbound feedback mechanism working as designed. The measured
eﬃciency is between 45% and 80% for the majority of the input range. Since the gate drive
power is included, the eﬃciency is lower than it would be for an integrated converter due
to the use of the analog multiplexers as the power switches in the converter.
At low input voltages (less than 2.7 V), eﬃciency and output voltage drop signiﬁcantly
as the converter loses regulation. This phenomena can be explained due to the input being
applied to the lower taps of the ladder converter at these lower input voltage levels. The
100
2 2.5 3 3.5 4 4.5 5
0
0.2
0.4
0.6
0.8
1
1.2
Input Voltage [V]
O
u
t
p
u
t
V
o
l
t
a
g
e
[
V
]
,
E
f
f
i
c
i
e
n
c
y
Efficiency
Output Voltage (mean)
Output Voltage (lower bound)
Figure 5.13. Output voltage and eﬃciency of the multiratio converter prototype
supply to the analog multiplexers is connected to the highest rail of the ladder converter.
Since the resistance between the lowest rail (V5) and the highest rail (V8) is substantial, the
converter is signiﬁcantly loaded by the analog multiplexer supply. Thus, the intermediate
voltage rail sags too much at low input voltage levels to maintain regulation.
The prototype results illustrates the functionality of the control scheme discussed in sec
tion 5.4.2. The output voltage ripple in this prototype was excessive due to few interleaved
phases and minimal output capacitance. In an integrated converter, more interleaved phases
would be used and if the loads are not onchip, a small external bypass capacitor would be
used to further control ripple. This topology is a promising development in onchip voltage
regulation for portable electronics.
101
Chapter 6
HighVoltage Converters for
Airborne Robotics
Chapters 2 through 4 discuss the fundamentals of switchedcapacitor converters, includ
ing a method of determining their output impedance and optimizing their performance. In
addition, methods to regulate the output of SC converters was discussed in chapter 5. This
complete design methodology can be applied to numerous examples. The ﬁrst example,
described in this chapter, uses a switchedcapacitor converter to generate a high voltage
supply for a piezoelectricbased airborne robot.
Micro air vehicles (MAVs) are small aircraft (typically less than 100 grams) which
are often controlled autonomously [63]. These devices can be used for searchandrescue,
ﬁre ﬁghting, and numerous military applications. As these devices get smaller, cheaper and
more maneuverable, their application space will increase dramatically. While current MAVs
are typically ﬁxedwing aircraft or gliders, biologicallyinspired designs have been more
sparse. Insectsized devices [62] require much higher power densities than previous MAV
designs. Their implementation necessitates higher power density batteries and actuators
and lightweight, higheﬃciency power conversion. By making autonomous MAVs smaller
102
and cheaper, they can be used to distribute a dense wireless sensor network in hostile
environments.
In [65], piezoelectric actuators were found to deliver the highest power density of any
available actuator at the milligramlevel. However, these actuators, typically made with lead
zirconate titanate (PZT), require actuation voltages of 150–300V. Generating this voltage
from a typical MAV power source, a lithiumion battery at 3.7V, is a diﬃcult problem.
While the entire energy chain has been examined in [57], the power electronics design will
be examined in detail in this chapter.
Topologies for generating a high voltage at a high conversion ratio will be investigated,
using both magneticsbased and switchedcapacitorbased solutions. By comparing various
powerconversion topologies in terms of both eﬃciency and weight, an optimal design will
be developed. Three power converters for this purpose are shown in ﬁgure 6.1. For each
topology, speciﬁc discrete components are chosen to illustrate the weight, eﬃciency and
feasibility of each design. The analysis method in chapter 2 is used in part to determine
the performance of these converters.
After topologies for highratio conversion have been discussed, the MicroGlider project
will be described, including the speciﬁcs on the converter used for this project. This Mi
croGlider has a mass of two grams with an onboard lithiumpolymer battery, microcon
troller, ﬁght sensors, charge pumps, power ampliﬁers and actuators. In addition, a RFID
payload was incorporated into the wing for remote tracking.
6.1 Comparison of Topologies for Lightweight HighVoltage
DCDC Converters
This section will analyze several highvoltage DCDC converter topologies in terms of
eﬃciency and component mass. For analysis purposes, the masses of common surface
mount type devices are shown in table 6.1. This mass does not include solder or the PCB
area occupied. These two additions will increase the total weight of a properly designed
103
+
V
I N
C L K
L
V
O U T
C
+
C L K
V
I N
C
n
1
: n
2
V
O U T
(a) boost (b) ﬂyback
+
V
I N
C L K
L
V
O U T
(c) hybridswitchedcapacitor
Figure 6.1. Three topologies for lightweight, highvoltage DCDC conversion
and soldered circuit board by 50–100%. The power inductors weigh more than the other
components as they contain a substantial amount of ferrite or other ironbased material.
Next, it is important to know the available capacitance and inductance values for various
package types and working voltages (for capacitors) or saturation current (for inductors).
Graphs showing the capacitance and inductance density of several miniature surfacemount
components are shown in ﬁgure 6.2. It is interesting to note that these components have
approximately constant volumetric energy density across the range of blocking voltages or
saturation currents.
The passive actuation for the MicroGlider in section 6.2 requires an output power level
of 10 mW. However, if an insectinspired actively ﬂying robot is made, it would require
an electrical power of 111 mW per gram robot mass to provide lift [57]. Designs will be
compared for a 200V output at both 10 mW and 222 mW (for a twogram aircraft).
104
Category Package Mass Notes
Resistors
0402 0.6 mg
0603 2 mg
0805 5 mg
Capacitors
0402 2 mg
Mass measured 0603 5–6 mg
0805 15 mg
Inductors (Coilcraft)
0603PS 27 mg
0805PS 60 mg
Inductors (TaiyoYuden)
0603 11 mg Mass estimated from
0805 27 mg mechanical diagram
Silicon components
SOT23 8 mg
Mass measured SOT236 15 mg
SOT363 7 mg
Table 6.1. Mass of common surfacemount components
Voltage Level Device V
DS,max
R
DS,on
C
D
High Voltage
Supertex TN2124 240 V 15 Ω 9 pF
Supertex TN2425 250 V 3.5 Ω 25 pF
Medium Voltage
Fairchild 2N7002 60 V 5 Ω 11 pF
Zetex ZXMN6A07F 60 V 0.35 Ω 19.5 pf
Table 6.2. Nchannel MOSFETs in SOT23 package
105
(a)
1 0 1 6 2 5 5 0
0 . 0 1
0 . 1
1
1 0
W o r k i n g V o l t a g e [ V ]
C
a
p
a
c
i
t
a
n
c
e
[
µ
F
]
C e r a m i c 0 4 0 2 ( 1 . 5 m g )
C e r a m i c 0 6 0 3 ( 6 m g )
C e r a m i c 0 8 0 5 ( 1 5 m g )
(b)
100 1000
1
10
100
Saturation Current [mA]
I
n
d
u
c
t
a
n
c
e
[
µ
H
]
T
a
i
y
o
−
Y
u
d
e
n
0
6
0
3
(
1
1
m
g
)
T
a
i
y
o
−
Y
u
d
e
n
0
8
0
5
(
2
7
m
g
)
C
o
i
l
c
r
a
f
t
0
6
0
3
P
S
(
2
7
m
g
)
C
o
i
l
c
r
a
f
t
0
8
0
5
P
S
(
6
0
m
g
)
Figure 6.2. Available (a) capacitors by voltage and (b) inductors by current
106
6.1.1 Boost Converter
A boost converter, shown in ﬁgure 6.1a, is the simplest DCDC converter which can
be used to generate the 200V required to run the piezoelectric actuators. In this analysis,
operation in discontinuous conduction mode (DCM) will be assumed. In each switching
period, the transistor turns on for time t
on
and magnetizes the inductor to a peak current,
denoted I
pk
. The switch then turns oﬀ and causes the inductor current to ﬂow through
the diode, charging the output capacitor, until the inductor current reaches zero. In the
chargeup phase, the peak current can be found in terms of the inductance, battery voltage,
and ontime:
I
pk
= t
on
V
IN
L
. (6.1)
The charge delivered to the output can be similarly found in terms of the peak current:
Q
OUT
=
1
2
I
pk
t
2
=
1
2
I
pk
_
I
pk
L
V
OUT
−V
IN
_
(6.2)
where t
2
is the time that the inductor current ramps down to zero through the diode. Next,
(6.2) will be multiplied by f
sw
to obtain the output current in terms of system parameters
and peak inductor current. Then the inductance will be found in terms of peak current and
system parameters to ﬁnd the application tradeoﬀ between inductance and peak inductor
current:
L = 2
(V
OUT
−V
IN
) i
OUT
f
sw
I
2
pk
. (6.3)
Since the output voltage in this application is much larger than the input voltage, by
approximating V
OUT
−V
IN
≈ V
OUT
, (6.3) can be transformed into a relation between load
power and peak inductor energy storage:
1
2
LI
2
pk
≈
P
OUT
f
sw
. (6.4)
Thus, given an inductor peak energy and output power, the converter’s switching frequency
can be found. However, it may be more eﬃcient to run the converter at a lower peak current.
At a lower peak inductor current, while the switching frequency increases, the inductor core
loss may decrease such that the overall eﬃciency is higher. To minimize inductor mass, it
is likely that the inductor is operated near the saturation current.
107
To calculate eﬃciency, the converter losses must be analyzed. Three losses will be con
sidered in this exploratory analysis. The onstate resistance loss and drainsource capaci
tance loss of the MOSFET depends on choice of MOSFET and the other design parameters.
The inductor ESR loss of the inductor will also be considered. Since the inductor loss and
onstate resistance loss are both resistive, they will be considered together as a lumped
resistance R:
P
RES
= i
2
R = f
sw
R
_
ton+t
2
0
I
L
(t)
2
dt (6.5)
where I
L
is the inductor current. Since the inductor current ramps up linearly to I
pk
over
time t
on
, (6.5) can be integrated:
P
RES
= f
sw
R
t
on
+t
2
t
on
_
ton
0
_
t
t
on
I
pk
_
2
dt =
1
3
f
sw
(t
on
+t
2
) RI
2
pk
. (6.6)
By realizing the input current i
IN
is the timeaveraged inductor current, the input current
can be written as:
i
IN
=
1
2
I
pk
f
sw
(t
on
+t
2
) . (6.7)
A ﬁnal expression for the resistive power loss is then given by:
P
RES
=
2
3
i
IN
I
pk
R. (6.8)
Likewise, the drainsource capacitance loss of the MOSFET can be represented as:
P
CAP
= f
sw
C
D
V
2
OUT
(6.9)
since the MOSFET’s blocking voltage is approximately equal to the output voltage.
The two primary losses stated here must be optimized by choosing the inductor, MOS
FET and switching frequency. Table 6.2 shows a number of high and mediumvoltage
MOSFETs for use in these converters. Since the boost converter places a large blocking
voltage requirement on the power switch (200V), only the highvoltage switches can be used
for this application.
By choosing the highest available inductance in a series, the peak current is kept minimal
(presuming I
pk
> 2i
IN
to maintain DCM operation). For each inductor type and load, the
108
TaiyoYuden TaiyoYuden Coilcraft Coilcraft
Power Level 0603 0805 0603PS 0805PS
(11 mg) (27 mg) (27 mg) (60 mg)
10 mW
Switch Type TN2124 TN2124 TN2124 TN2124
Inductance 10 µH 47µH 47µH 330µH
Switching frequency 312 kHz 75.6 kHz 42 kHz 17 kHz
Peak Current 80 mA 75 mA 100 mA 60 mA
Power Loss 115 mW 30 mW 19.3 mw 10 mW
Eﬃciency 8.0 % 25.2% 34.2% 49.7%
220 mW
Switch Type N/A N/A TN2124 TN2124
Inductance N/A N/A 0.78µH 3.9µH
Switching frequency N/A N/A 763 kHz 456 kHz
Peak Current N/A N/A 860 mA 529 mA
Power Loss N/A N/A 824 mW 492 mW
Eﬃciency N/A N/A 21.1 % 30.9%
Table 6.3. Eﬃciency of singlestage boost converter
optimal switch type is chosen and peak current optimized to yield the optimal design. At
this optimal design point, the power loss and eﬃciency are evaluated. Table 6.3 shows the
eﬃciency of these designs. By choosing the mosteﬃcient design with a suitable component
weight (including control components), the optimal design can be obtained.
However, after inspecting the designs, none of the potential designs result in an ac
ceptable eﬃciency at an acceptable mass. Since the power switch must conduct the input
current but block the output voltage, it has a very large VA product, which results in large
switch dissipation. To improve the eﬃciency, converters that stress the power switches less
will be utilized. Two boost converter stages could be cascaded, such that the conversion
109
ratio of each converter is modest. While this method may yield increased eﬃciency, the
mass of the additional inductor and control circuitry would make the converter prohibitively
heavy. A ﬂyback converter and a hybrid switchedcapacitor converter will be used to lower
the switch stresses while using only a single magnetic element.
6.1.2 Flyback Converter
A ﬂyback converter, as shown in ﬁgure 6.1b, is a transformerbased indirect converter.
The transformation ratio n
2
/n
1
greatly lessens the switch stresses on the primaryside
switches, allowing a greater eﬃciency. When the power switch is on, the current in the
magnetizing inductance of the transformer ramps up linearly at a rate proportional to the
input voltage. When the switch turns oﬀ, the magnetizing inductance current ramps down
through the transformer to the output. In this conﬁguration, the power switch nominally
blocks a voltage equal to V
IN
+(n
1
/n
2
) V
OUT
. An additional margin must be included in the
switch voltage rating due to eﬀects of the transformer’s leakage inductance. With a turns
ratio of 1:50, and an output voltage of 200V, the reset voltage of the transformer equals 4 V.
When the reset voltage is added to the battery voltage, the power switch blocking voltage
is approximately 8 V (discounting the eﬀect of the leakage inductance), allowing the use of
a 20 V switch.
While the switch stresses are greatly reduced in a ﬂyback converter, the design of the
transformer becomes the largest issue in implementation. Power inductors are typically
customwound for a particular application from commerciallyavailable magnetic cores. In
this application, the smallest available cores must be used. For this explorative calculation,
the MicroMetals T1426A toroidal core will be used, with a mass of 77mg. Smaller cores
are available for RF and EMI applications, but their suitability for power applications is
unknown. The ungapped core exhibits a singleturn inductance of 12.5 nH and outer and
inner diameters of 3.43 and 1.70 mm, respectively.
Winding the transformer also presents great diﬃculty as the inner aperture is very
small and the turns ratio is very large. The number of turns on the primary is computed
110
10 mW 220 mW
Switch Type ZXMN6A07F ZXMN6A07F
Switching frequency 13 kHz 289 kHz
Peak current 550 mA 550 mA
Power loss 0.79 mW 17.3 mW
Eﬃciency 92.7 % 92.7 %
Table 6.4. Eﬃciency of ﬂyback converter using custom transformer
by optimizing power loss using a reasonable switching frequency. For a modest 20 primary
turns, 1000 secondary turns are necessary, requiring very ﬁnegauge wire. The feasibility
of winding such a transformer will be neglected, although it would be a nontrivial aspect
of any implementation. If 75% of the aperture is used for the secondary, at a 50% packing
factor, the secondary wire must have a diameter less than 0.033 mm. AWG 48 wire needs
to be used for the secondary, with a resistance of 21.8 Ω/m. The resistance of the secondary
would equal 240 Ω. Reﬂecting this impedance to the primary yields 96 mΩ. Similarly, the
primary winding is speciﬁed with AWG 36 wire, with a total resistance of 290 mΩ. The
total mass of these two windings equals 108 mg, dominating the mass of the converter.
The maximum magnetic ﬁeld for the toroid material is 0.6 tesla before signiﬁcant sat
uration occurs. However, for eﬃciency, the ﬁeld will be restricted to 0.2 T. This ﬂux limit
corresponds to a primary current limit of 0.96 A. However, the optimal peak current will
likely be less than this limit, as was the case for the boost converter. To ﬁnd the optimal
operating conditions for the converter, the same method as the boost converter will be used.
However, as the magnetic component is now ﬁxed, only the switches in table 6.2 can be
adjusted, along with the peak current. The eﬃciency of the ﬂyback converter, using this
transformer, is shown in table 6.4. Switch resistive and capacitive losses are considered, as
well as transformer core and copper losses.
The ﬂyback converter achieves a very high eﬃciency when compared with the boost
converter. However, the manufacturing of this transformer would be extremely diﬃcult,
111
+
V
I N
C L K
L
V
O U T
C 0
C 1 C 3 C 5
C 2 C 4 C
2 ( N  1 )
Figure 6.3. Hybrid switchedcapacitor boost converter
and its mass should be reduced further for practicality. Additionally, the mass and power
consumption of the necessary control circuitry have not been considered. Since this con
verter is impractical for prototyping (and likely manufacture), an alternative is considered
in section 6.1.3. The hybrid switchedcapacitor converter combines the low switch stress of
the ﬂyback with use of only oﬀtheshelf components.
6.1.3 Hybrid SwitchedCapacitor Boost Converter
The hybrid switchedcapacitor converter was developed to reduce the switch stresses
of the boost converter’s MOSFET while maintaining use of oﬀtheshelf components in a
single converter. A pure switchedcapacitor circuit could be designed to do the conversion,
but as the conversion ratio is large, a prohibitively large number of components would be
needed. The hybrid SCboost converter, shown in ﬁgure 6.3, uses a boost converter to
generate an intermediate voltage (about 30 V) and to drive a passive, diodebased charge
pump to generate the desired 200 V output.
For simplicity, the eﬃciency of the boost converter and SC converter will be analyzed
independently. First, the boost converter will be examined with a standard resistive load.
The method presented in section 6.1.1 will be used here when considering the devices in
table 6.2 and ﬁgure 6.2. For the lowpower converter, the Coilcraft 0603PS inductor series
will be used. Similarly, the 0805PS series will be used for the highpower case. After
optimizing the boost converter at the two power levels, the design parameters and results
are shown in the top half of table 6.5.
112
The lowratio boost converter stage is signiﬁcantly more eﬃcient than the highratio
boost converter in section 6.1.1. Due to the lower switch stresses of this design, the boost
converter exhibits high eﬃciency with modest part mass. Next, the eﬃciency SC converter
stage will be considered.
The SC converter component of this hybrid converter is a ladder converter attached to
the boost converter across the rectifying diode. The rectangular waveform across this diode
allows the charge pump to operate without any active or controlled components. Three
losses will be considered: the SSL output impedance loss, the cascaded diode voltage drop
and the diode junction capacitance loss.
The structure of the ladder topology allows each capacitor to only support the input
voltage, in this case 30V. Thus, instances of the same part can be used for all capacitors,
although for increased power capability, the capacitors near the input can be doubled up in
parallel to approximate the optimal capacitor sizings from section 3.2.1. However, we will
consider all capacitors to be identical, as that assumption yields the least mass. The SSL
impedance of the ladder converter is proportional to the sum of the squares of the capacitor
charge multipliers, as found in section 2.1:
R
SSL
=
i∈caps
(a
c,i
)
2
C f
sw
(6.10)
where N is the number of stages, C is the value of each capacitor, and f
sw
is the switching
frequency of the boost converter since the charge pump operates at the same frequency
as the boost converter. For an Nstage ladder converter, there are two chains of N − 1
capacitors, each with charge multipliers increasing by integers from 1 to N −1. By adding
the squares of these components, the SSL output impedance can be found:
R
SSL
=
1
C f
sw
2N
2
−3N
2
+N
3
(6.11)
where N is the number of stages and C is the value of each of the capacitors in the converter.
Next, diode loss will be considered. As diodes are modeled as voltage drops, not resistive
drops, the FSL impedance model cannot be used. For this converter, the BAS40DW04
diode from Diodes, inc. is used as it supplies four seriesconnected diodes in a 6pin 7 mg
113
10 mW 220 mW
Boost
Switch Type ZXMN6A07F ZXMN6A07F
Inductance 10 µH 3.3 µH
Switching frequency 45 kHz 485 kHz
Peak current 210 mA 580 mA
Power loss 1.6 mW 25.5 mW
Eﬃciency 86.4% 89.6%
Switchedcapacitor
Capacitor Type 10nF 0402 47nF 0603
Diode type BAS40DW04 BAS40DW04
Number of stages 8 7
Output Voltage 207 V 199 V
Eﬃciency 79.2% 90.1%
Total
Eﬃciency 67.9% 80.7%
Component mass 85 mg 176 mg
Table 6.5. Eﬃciency of hybrid boost converter
114
SOT363 package. These Schottky diodes exhibit a breakdown voltage of 40 V and forward
voltage of 0.35 V at 1.0 mA. Capacitor C1 in ﬁgure 6.3 is charged from capacitor C0 with a
single diode drop. In each phase, the two chains of capacitors equalize through the diodes.
Since in each phase, the onstate diodes conduct the same current in the same direction,
the diode forward drop does not yield a decreasing set of capacitor voltages. Instead, each
capacitor in the opencircuit case nominally equilibrates to the output of the boost converter
minus a single diode drop.
Finally, the diode junction capacitance loss originates from each diode turning on and
oﬀ each period, charging and discharging the parasitic junction capacitance. For the
BAS40DW04 diode, it has a cumulative junction charge of 52 pC at 30 V. Thus, for
each switching period, 1.56 nJ of energy is lost per diode. This loss is incorporated into the
numbers in table 6.6. The loading of the diode junction capacitances is incorporated into
the model as an additional output current with similar power consumption. This approx
imation overestimates the loading due to the diode capacitances, and is thus a worstcase
bound.
Table 6.6 shows the output voltage and eﬃciency of the ladder converter for a range
of stages. In these calculations, the 10 mW converter design is considered using 10 nF
0402 capacitors and a 30 V boost converter output. The output resistance is adjusted to
yield 10 mW output power at each number of stages. As the number of stages increases,
the incremental voltage gain decreases and the eﬃciency drops. For this application, eight
stages will be used, as it provides an output closest to 200 V.
The total converter eﬃciency is shown in table 6.5. The mass of the switchedcapacitor
converter adds only 50 mg to the mass of the 35 mg, 10 mW boost converter and 108 mg
to the 68 mg, 220 mW boost converter. The eﬃciency of the converter can be increased by
increasing the switching frequency (by decreasing the inductance value of the boost con
verter). The hybrid SCboost converter provides a relatively light and eﬃcient converter
for aerial robotics without the need for a heavy customwound transformer. The implemen
115
Stages Output impedance Load resistance Output voltage Eﬃciency
4 62.2 kΩ 1.3 MΩ 113.4 90.3%
5 133 kΩ 1.9 MΩ 139.0 87.5%
6 244 kΩ 2.7 MΩ 163.3 84.8%
7 404 kΩ 3.5 MΩ 186.2 82.0%
8 622 kΩ 4.3 MΩ 207.5 79.3%
9 907 kΩ 5.2 MΩ 227.5 76.5%
10 1.27 MΩ 6.0 MΩ 245.1 73.7%
Table 6.6. Eﬃciency of ladder converter with 4–10 stages at 10 mW load
tation of this hybrid SCboost converter topology will now be examined as it is used in the
MicroGlider project.
6.2 MicroGlider Power Converter
The MicroGlider is a twogram passive aircraft used for remote sensing purposes [64, 63].
A box of these gliders can be released from a piloted aircraft above territory where access
is impossible or impractical. The gliders slowly spiral down until a target or destination is
located. Then the glider steers itself to that point to position a wireless sensor node (in the
experimental prototype, an RFID tag) on the target. The glider is made with carbon ﬁber
wings and control surfaces with a carbonﬁber tube fuselage. A 20 mAh lithiumpolymer
battery is used as the power source, and is located at the front of the plane (with an attached
wire bumper) for balance. The control PCB contains all the control and power electronics
and is centrally located on the fuselage. The glider and the control PCB are shown in ﬁgure
6.4.
The MicroGlider uses a hybrid SCboost power converter to generate the 200V bias
rail for the power ampliﬁers to drive the piezoelectric actuators. The converter used is
shown in ﬁgure 6.5. A Linear Technology LT16151 boost converter controller chip was
116
(a) Carbon ﬁber MicroGlider[64] (b) Control PCB; power converter outlined
Figure 6.4. Photos of the MicroGlider and control PCB
V
I N
L
V
O U T
C 0
C 1 C 3 C 5
C 2 C 4 C 1 6
L T 1 6 1 5  1
V
I N
S W
S H D N F B
G N D
R 1
R 2
C
I N
Figure 6.5. Hybrid SC boost converter as appearing on the MicroGlider
used to generate the intermediate 30V rail and to drive the ninestage ladder topology.
An intermediate output tap was provided at seven stages in case a lower voltage, higher
eﬃciency supply was desired.
The LT16151 part automatically controls the boost controller with feedback supplied
by the resistor divider made with R1 and R2. A Coilcraft 10 µH 0603PS shielded ferrite
inductor was used for the boost converter component. When the output voltage falls below
the threshold, the inductor is magnetized through the internal switch to a trip point of
100 mA, then turned oﬀ (with a 400 ns delay). The SC ladder topology is identical to the
one discussed in section 6.1.3 using BAS40DW04 diodes and 10 nF 0402 capacitors. The
117
7 stages 9 stages
Load 10 MΩ 3.3 MΩ 10 MΩ 3.3 MΩ
Output Voltage 162.3 V 160.7 V 203 V 200 V
Output Power 2.63 mW 7.83 mW 4.12 mW 12.1 mW
Eﬃciency 51.5% 61.3% 47.5% 51.8%
Output impedance 49.2 kΩ 49 kΩ
Table 6.7. Experimental results of the MicroGlider converter
converter IC runs from an input as low as 1.0 V, suitable for a lithiumion battery, and
can output up to 35 V. With a quiescent current of 19 µA, the control circuitry does not
signiﬁcantly aﬀect eﬃciency. For a 20 V, 10 mW output, the measured eﬃciency of the
standalone boost converter is 73% [26]. The feedback network (R1 and R2) were tuned to
deliver an intermediate voltage of 31 V.
When cascading a sevenstage ladder converter with this boost converter, an overall
eﬃciency of 59.9% at an output voltage of 186 V is expected. With nine stages, the cal
culated eﬃciency and output voltage are 55.8% and 227 V, respectively. The converter
was fabricated using a 3milthick ﬂexible PCB and occupies 0.8 cm
2
of board area on the
control PCB. It was tested using a 3.5V voltage source and a resistive load.
The output voltage and eﬃciency of the fabricated converter are shown in table 6.7.
The eﬃciency and output voltage numbers are quite close to the predicted values, with
the output voltage sagging some due to the unmodeled loading from the diode junction
capacitance. The incremental output impedance numbers do not match those given in
table 6.6 as the boost controller automatically increases switching frequency as load current
increases. In conclusion, the hybrid boost converter is an eﬃcient method to generate high
voltages in a massconstrained application using oﬀtheshelf components.
118
Chapter 7
SwitchedCapacitor Converters for
Wireless Sensor Nodes
Switchedcapacitor converters exhibit many advantages over traditional inductorbased
converters for ultralowpower applications. This chapter examines the power processing
circuitry designed for a miniature energyharvested wireless sensor node (WSN). Switched
capacitor converters are ideal for WSNs as they can easily be integrated and have high
eﬃciency over a wide range of power levels.
Wireless Sensor Nodes (WSNs) are using less power and are becoming smaller as this
technology matures. Scavengedpower sensor nodes are now a reality with modern processor,
sensor and radio technology [38, 45]. While energy harvesters and their power conversion
circuits have recently been integrated on the same die [29], the power harvested is not yet
suﬃcient to power a 110 µW sensor node. By using MEMS energy harvesters [44] and
inkjet printed supercapacitors and batteries [55, 56], a highlycapable sensor node can be
made in the size of a sugar cube (1 cm
3
) [39].
The eﬃciency of the scavengerbatteryload power interface path, especially at low
power, is critical to the performance of such a sensor node. This chapter discusses the
119
design of a custom IC to perform scavengertobattery and batterytoload power conver
sion, while meeting power and size constraints of the system.
7.1 Application and IC Overview
This chapter describes a power interface integrated circuit [52, 49] for a wireless tire pres
sure sensor (TPS), running from energy scavenged from a magnetic shaker [38, 11]. Photos
of the node and scavenger are shown in ﬁg. 7.1, with dimensions indicated. The sensor
node is a modular stack of 1 cm
2
printed circuit boards connected by elastomer connectors.
Each board contains a single functional block of the system. The energy consumers, or
loads, include a TI MSP430 microcontroller, an Inﬁneon pressure and acceleration sensor,
and a custom PicoRadio radio transmitter [12]. The microcontroller and sensor run at a
minimum 2.1 V supply and the radio requires a precise 0.65 V supply. A small NiMH coin
cell with a nominal capacity of 18 mAh is used as an energy buﬀer, although the use of a
supercapacitor is also feasible. The electromagnetic shaker utilizes the rotation of the tire
to generate energy to power the sensor.
(a) (b)
Figure 7.1. Photos and dimensions of the a) PicoCube and the b) electromechanical shaker
WSNs often run at very low duty cycles to minimize power consumption. In the TPS
application, tire pressure is measured once every six seconds. Power consumption for a
120
P
o
w
e
r
[
m
W
]
1
2
3
T i m e [ m s]
5 10 15
w ak eup
acqui r e sam pl e
get r esul t
send pack et
( al t er nat i ng 1’ s & 0’ s)
2.1V r ai l
0.7V r ai l
Figure 7.2. Measurement and transmission power
single 14ms measurement/transmission period is shown in ﬁgure 7.2. Each 14ms measure
ment/transmission cycle uses approximately 29 µJ, yielding peak powers of several mW.
Node standby power is less than 1 µW resulting in a timeaveraged power consumption of
approximately 6 µW.
The performance of a selfpowered WSN is often deﬁned by the sample rate or the
number of samples per second the node can acquire and transmit. For a given ﬁxed energy
per packet, and a ﬁxed average power supply (deﬁned by the capabilities of the battery
or energy scavenger), the sample rate is highly dependent on the eﬃciency of the power
interface circuits. Since WSNs spend the vast majority of time in standby mode, power
eﬃciency at microwatt levels is critical but lacking in current solutions. This power interface
IC aims to improve this eﬃciency.
The architecture of the power interface IC is given in ﬁgure 7.3. The synchronous
rectiﬁer interfaces the electromagnetic shaker (harvester), which puts out a pulsed waveform,
to the battery. Details about its use and implementation are in section 7.4. Two switched
capacitor power converters convert the battery voltage, nominally 1.2 V, to 2.1 V for the
microcontroller and sensors and to 0.7 V to power the radio. The design of the power
121
Sy nchr onous
Rect i f i er
Scav enger
Cur r ent
Ref er ence
V ol t age
Ref er ence
Feedback
B at t er y
2.1V ( 1: 2)
Conv er t er
0.7V ( 3: 2)
Conv er t er
L i near
Regul at or
Radi o
M i cr ocont r ol l er
Sensor s
Figure 7.3. Block diagram of the converter IC
stages of these converters is detailed in section 7.2, while the gate drive techniques used are
described in section 7.3.
An ultralowpower linear regulator is used as a postregulator to moreprecisely set the
radio supply voltage to 0.65 V and to smooth the ripple from the switchedcapacitor con
verter. This linear regulator is designed with an integrated switch to disable the regulator’s
output. When the output is disabled, the regulator’s bias current is decreased substantially
to reduce quiescent power. The enable transistor is located between the output capacitor
and the load such that the output capacitor remains charged while the output is disabled.
Thus, the energy stored in the capacitor is preserved and the turnon transient response is
shortened. Finally, a hysteretic feedback controller is used to regulate output voltage and
switching frequency, and is described in section 7.5.
A number of analog blocks provide support to the power electronics by providing refer
ences and control signals. A selfbiased current source (reference) supplies bias current to
the chip via a current mirror. It is biased at 18 nA independent of V
DD
and mildly depen
dent on temperature. An ultralowpower sampled bandgap reference provides a reference
122
V
O U T
V
I N
φ 1
φ 2
φ 2
φ 1
C 1 C
O
V
IN
V
OUT
C1 C2
C
O
φ1
φ2
φ1
φ1
φ1
φ2 φ2
(a) (b)
Figure 7.4. Switchlevel diagram of a) 1:2 converter, b) 3:2 converter
voltage to both the converter feedback circuitry and the linear regulators. The design of
this voltage reference is further described in section 7.5.
The converter IC was implemented using a 0.13 µm CMOS process provided by STMi
croelectronics. The nominal 1.2V working voltage matches the battery voltage perfectly,
and the process provides 2.5 V transistors and highdensity capacitors, the latter used in
the switchedcapacitor converters.
7.2 Converter Architecture and Optimization
Two independent switchedcapacitor (SC) converters perform the power conversion be
tween the battery and the loads. A 1:2 ratio converter, shown in ﬁgure 7.4a, provides a
doubled voltage for the microcontroller and sensors. The minimum supply voltage for these
components is 2.1 V. A 3:2 ratio converter, shown in ﬁgure 7.4b, provides a lower voltage
(nominally 0.65V) to supply the radio.
The topologies are chosen to utilize the native transistors of the 0.13 µm CMOS process,
even to generate the 2.1 V rail. The beneﬁts and drawbacks of a number of SC converter
123
topologies are described in chapter 4. All power switches are implemented using triple
well NMOS transistors to minimize die area and gating and parasitic losses. Section 7.3
addresses the level shifters and other circuitry required to drive these transistors.
The transistors, capacitors and converter switching frequency of each converter are
adjusted to optimize eﬃciency while meeting constraints on output voltage, power and die
area. In chapter 3, a method to optimize transistor and capacitor sizes, and the relative
allocation of die area between transistors and capacitors, was developed. Those techniques
will be applied here to size the various components and choose the maximum switching
frequency. Under nominal operating conditions, switching frequency will be regulated via
a hysteretic control loop described in section 7.5. The converter is optimized to maximize
eﬃciency via this method while keeping the output impedance suﬃciently low such that
the required output voltage is maintained at maximum output current. A margin of error
for process tolerances needs to be included as well.
To optimize the SC converters, the total capacitor area is constrained to a prescribed
area, and the relative capacitor sizes within each converter are adjusted by the optimization
in chapter 3. Metalinsulatormetal (MIM) capacitors are used for all capacitors as they
have a relativelyhigh capacitance density and low bottomplate parasitic capacitance. Next,
the capacitor area is divided between the two converters such that both would run at the
same switching frequency (to allow for a single clock), while minimizing net loss. The two
remaining variables are the switch area (for each converter) and the switching frequency. A
numerical optimization is performed by evaluating eﬃciency and output impedance over a
range of switching frequencies and switch areas.
Figure 7.5 shows contour plots of the converter eﬃciency swept over switching frequency
and switch area for the 1:2 and 3:2 converters. Contour eﬃciencies are indicated. The
optimal design lies in a wide plateau between 90% and 92% eﬃciency. The solid straight
lines separate the space into four regions, indicating where each of the four indicated loss
mechanisms are dominant.
The two converters were designed with a slightly higher switching frequency and switch
124
10 100
100
1000
Swi tchi ng Frequency [ MHz]
S
w
i
t
c
h
A
r
e
a
[
µ
m
2
]
0.9
0.85
0.8
0.6
0.9
0.85
0.8
0.7
0.6
FSL l oss l i mi ted
Cap. bottom pl ate
l oss l i mi ted
SSL l oss l i mi ted
Swi tch parasi ti c
l oss l i mi ted
(a)
10 100
100
1000
Swi tchi ng Frequency [ MHz]
S
w
i
t
c
h
A
r
e
a
[
µ
m
2
]
0.85 0.8 0.6
0.9
0.85
0.8
0.7
0.6
0.4
FSL l oss l i mi ted
Cap. bottom pl ate
l oss l i mi ted
SSL l oss l i mi ted
Swi tch parasi ti c
l oss l i mi ted
(b)
Figure 7.5. Optimization contours of the (a) 1:2 converter and (b) 3:2 converter
125
area than optimal to ensure the output impedance was suﬃciently low across the process
corners. A nominal switching frequency of 30 MHz was chosen, along with switch areas
of 550 and 950 µm
2
for the 1:2 and 3:2 converters, respectively. The anticipated fullload
openloop eﬃciencies of these two converters are between 90% and 92% for both the 1:2
and 3:2 converters.
7.3 Gate Drive
Since both converters use only native 0.13 µm NMOS devices, driving the gates is not
trivial. Two gatedrive structures have been developed for the two SC converters.
The 1:2 ladder converter exhibits a regular structure that can be extended for higher
ratio conversions. This ladder topology can be driven with cascode levelshifters. The
cascode level shifters [40] are made with triplewell 0.13 µm devices and can translate a
signal up an arbitrary number of levels. This implementation is shown in ﬁgure 7.6 for an
intermediate stage in a ladder converter.
Each level shifter and its gate driver are powered from the local power capacitor con
nected to the relevant switch’s source. For instance, capacitor C2 in ﬁgure 7.6 powers the
circuitry to drive M2. A pair of crosscoupled inverters form a latch, regenerating the signals
at each stage. Two pulldown signals, connected to the sources of M5 and M8, toggle the
latch to either the on or oﬀ position. Two NMOS transistors (M7 and M10) then reproduce
these signals to drive the levelshifter above it.
Since all transistors in the levelshifter are 1.2V triplewell devices, shielding devices are
needed to prevent device breakdown. Cascode pairs (e.g. M5, M6 and M8, M9) are used
to shield both the NMOS pulldown transistor and the gates of the NMOS transistors. The
threshold of these cascode devices limit the minimum voltage and speed of the level shifter.
Transistor sizing and optimization is critical to ensure operation over railvoltage variation.
The top transistor in the NMOS transistor stack implementing the ladder converter is
driven based on a ﬂoating supply. The ladder structure of the power devices is continued
126
C1
C3
C4
C2
M1
M2
M3
M4
M5
M6
M8
M7
M9
M10
M11 M12
Figure 7.6. Cascode levelshift gate drive for the 1:2 ladder converter
by one or two more smaller transistors, creating higher potentials to drive each of the large
powerpath switches. The top transistor in the extended ladder is implemented using a
PMOS device and driven by the same source as the NMOS transistor beneath it.
An alternate gate drive structure is used for the 3:2 converter. Since the sources of all
the transistors in this converter (in ﬁgure 7.4b) never exceed the V
DD
rail, a moredirect
drive can be used. This chargepump gate drive, shown in ﬁgure 7.7, uses a ﬂying capacitor
charged to the 1.2V supply to directly drive the gate of a transistor with a nongrounded
source. In the 3:2 converter, six of the seven transistors are driven this way. The remaining
transistor has its source connected to ground, and is driven with an inverterchain buﬀer.
The operation of this gate drive circuit will be examined with respect to the drive signal
CLK. When CLK is low, the power transistor gate is discharged to ground via transistors
M6 and M7. Also, the ﬂying cap C1 is charged to V
OUT
via M4 and M1.
When CLK is high, C1 charges the gate of the power transistor to V
DD
+V
OUT
through
127
CLK
V
DD
V
OUT
M1
M2
C1
C2
M3
M4
M5
M6
M7
V
DD
CLK
V
G
Figure 7.7. Capacitorboost gate drive for the 3:2 converter
M2 and M5. C1 is the primary capacitor of the charge pump which charges the power
capacitor to the appropriate voltage. In addition, assist cap C2 is charged to V
OUT
via
diodeconnected M3. Capacitor C2 eliminates the diode drop of M4 while charging C1
when CLK is low.
Capacitor C1 is sized such that it dominates the gate capacitance of the power transistor,
enabling the gate to be charged to V
DD
+ V
OUT
. For each of the three gate drive circuits
(each driving two switches), a single 2 pF MIM capacitor was used. While in the onstate,
these power transistors’ sources are at V
OUT
, so their gates are driven correctly. This gate
driver, along with the cascode levelshifter for the 1:2 converter, ensure eﬃcient converter
operation using only the native 0.13 µm NMOS devices.
7.4 Synchronous Rectiﬁer
The tire pressure sensor is powered using an electromagnetic shaker. A small permanent
magnet moves inside a cylinder wrapped with a multiturn winding, shown in ﬁgure 7.8a.
The shaker axis is oriented tangential to the circumference of the wheel. The varying
gravitational force in the frame of the rotating wheel causes the magnet to fall back and
forth in the cylinder. The local centrifugal force is normal to the direction of magnet travel,
creating a normal force depending on the rotation speed. Each time the magnet falls from
128
V
P
V
B
t
v
IN
i
IN
(a) (b)
Figure 7.8. Shaker (a) design and (b) example input waveform
one side to another, a pulse of voltage is created. To charge a battery or capacitor, these
pulses must be rectiﬁed.
Simple diodebased rectiﬁers are convenient but the forward voltage drop severely im
pacts eﬃciency at low system voltages. A synchronous rectiﬁer (see ﬁgure 7.9) uses active
devices and feedback to perform the rectiﬁcation function without signiﬁcant voltage drop
and power loss [49, 19, 24, 42]. The synchronous rectiﬁer approaches the eﬃciency of an
ideal diode rectiﬁer. Since the pulse shape and amplitude are predictable by the nature of
the application, the source voltage can be matched to the battery or load voltage by simply
changing the number of turns in the single shaker winding. The number of turns on our
scavenger are optimized by trial and error to achieve the optimal opencircuit amplitude.
For this application, the optimal opencircuit amplitude was determined to be 2.5–3.0 V by
the method in section 7.4.1.
Figure 7.9 summarizes the circuits used for the synchronous rectiﬁer. The lower two
transistors of the bridge are gated complementarily from a hysteretic comparator. Hysteresis
prevents oscillation and allows the circuit to reduce bias current at zero input. Since the
magnet is usually not moving (as vehicles are usually parked), energy conservation at zero
input is critical. The threshold of the hysteretic comparator is designed to be approximately
±0.4 V.
129
+
+
+
+ 
Figure 7.9. Synchronous rectiﬁer circuit
The upper transistors of the bridge run independently and are controlled by comparators
continuously sampling the voltage across each of the switches. The delay of the rectiﬁer
depends on the bias current and the drainsource voltage diﬀerence on the switch. By
making the switch large, conduction loss is minimized, but transition time is lengthened. An
onstate drop of 2050 mV and bias current of 10 nA were targeted to achieve a compromise
between conduction loss, bias current and delay time. Additionally, a circuit was added to
reduce bias current at zeroinput conditions, as detailed below.
The circuit used to replace each of the two topside diodes in the traditional rectiﬁer is
shown in ﬁgure 7.10a. Transistor M1 is the power transistor which replaces the rectiﬁer diode
and is controlled by a twostage comparator. The body diode of M1 allows for operation
as a traditional rectiﬁer when the circuit is powered oﬀ. Transistors M2 through M5 and
transistors M6 through M9 form the ﬁrst and second stages of the comparator, respectively.
Each stage is driven by a bias current source gated by transistors M10 through M12. These
gating transistors are connected to the input voltage, allowing the bias current sources
to be shut oﬀ when the input voltage falls below the threshold voltage of the transistors.
When no mechanical energy is applied to the harvester, the input falls to zero and the
quiescent current of the rectiﬁer is greatly reduced. The bias current of the comparator is
approximately 4 nA and is reduced when the input is low.
Figure 7.10b shows the implementation of the hysteretic comparator in the synchronous
130
V
I N
V
O U T
I
B I A S
I
B I A S
I
B I A S
M 1
M 2 M 3
M 4 M 5
M 6 M 7
M 8 M 9
M 1 0 M 1 1 M 1 2
(a) Top diode replacement (PMOS)
V
D D
V
1
V
2
M 5 M 6
M 1 M 2
M 3 M 4
(a) Bottom diode replacement (NMOS)
Figure 7.10. Circuits implementing the synchronous rectiﬁer
131
rectiﬁer design. Transistors M1 and M2 form the power devices which rectify the input
signal. Their body diodes can act as standard junction diodes when the circuit is not
powered up. Transistors M3 through M6 form a comparator which measures the input
voltage and sets the state of the power devices accordingly. Since the devices must switch
when the ﬂoating input, which is connected to the oﬀstate transistor, swings below ground,
the comparator must be designed to allow a negative commonmode voltage at the input.
The input devices (M3 and M4) have their sources crosscoupled to allow the sensing of
negative voltages, limited by the forward voltage of the body diodes of these transistors.
Additionally, when both inputs are at zero volts, the circuit consumes only leakage power
because it is essentially a digital circuit.
7.4.1 Impedance matching AC energy harvesters with diode rectiﬁers
Analysis of a diode rectiﬁer is necessary to compute the optimum number of turns, and
thus the optimum peak input voltage, of the electromagnetic harvester. The synchronous
rectiﬁer is modeled as an idealdiode rectiﬁer, since its forward voltage drop is nearly neg
ligible. Figure 7.8b shows a typical waveform for a shaker transition. For simplicity, a
single halfperiod of a sinusoid will be examined. This work assumes constant amplitude
sinusoidal pulses, but the method can be extended to arbitrary waveforms. The sinusoidal
source, with amplitude V
P
and series real impedance R
S
, is connected to a battery with
voltage V
B
through an idealdiode bridge rectiﬁer. The inductance of the coil does not
contribute signiﬁcantly to the impedance of the harvester at the sub100Hz frequency of
operation. If the harvester has a natural frequency of ω and pulse repetition frequency of
f
IN
, the opencircuit input voltage over a pulse can be written as:
v
OC
(t) = V
P
cos(ωt) −π/2 ≤ ωt ≤ π/2. (7.1)
When the harvester is connected to the rectiﬁer, the input voltage will be clipped to the
battery voltage. A current will ﬂow through the rectiﬁer during a period of time where the
132
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.2
0.4
0.6
0.8
1
Battery voltage (as % of input amplitude)
F
r
a
c
t
i
o
n
o
f
e
n
e
r
g
y
r
e
c
o
v
e
r
e
d
1 kHz input
R
S
= 1 kΩ
Ideal diodes
20% diode drop
Figure 7.11. Available energy via rectiﬁcation into a ﬁxed voltage source
opencircuit voltage is greater than the battery voltage in magnitude:
−
cos
−1
_
V
B
V
P
_
ω
< t
ON
<
cos
−1
_
V
B
V
P
_
ω
. (7.2)
The current ﬂowing through the rectiﬁer in the onstate can be written as:
i
IN
=
1
R
S
(V
P
cos(ωt) −V
B
) t ∈ t
ON
. (7.3)
The energy recovered from a single pulse can be found by integrating the instantaneous
power over the conduction angle:
E
IN
=
V
B
R
S
_ 1
ω
cos
−1
“
V
B
V
P
”
−
1
ω
cos
−1
“
V
B
V
P
”
(V
P
cos(ωt) −V
B
) dt. (7.4)
E
IN
=
2 V
B
ω R
S
_
_
V
2
P
−V
2
B
−V
B
cos
−1
_
V
B
V
P
__
. (7.5)
The ideal ratio between V
P
and V
B
can be found by maximizing E
IN
with respect to
V
B
. Figure 7.11 shows the fraction of the available energy harvested plotted as the battery
voltage is varied with respect to the input amplitude. This fraction corresponds to the
energy obtained from the rectiﬁer divided by the maximum energy available through a
133
matched resistive load. Additionally, the eﬃciency is also shown in the case when diodes
(each with a drop of 10% of the input amplitude) are used for the rectiﬁer, yielding a 20%
loss while charging. The input energy, in (7.5), is compared with the energy obtained from
an ideal matchedimpedance load. This maximum singlepulse energy is given by:
E
MAX
=
π
ω
V
2
P
8 R
S
(7.6)
From this optimization, 93% of the resistivelymatchedload energy can be recovered
when the peak of the input pulse is approximately 2.5 times the battery voltage. At mi
crowatt power levels, it is not advantageous to pursue the remaining 7% by creating an
elaborate impedancematching circuit. However, if a highlyreactive harvester is used, such
as a piezoelectric bender, additional circuitry can be used to extract more energy from the
source [42].
7.5 UltraLowPower Analog Circuits
For systems with large peak power to average power ratios, switching frequency control
is essential to maintain high eﬃciencies across operating conditions. Gate drive and other
frequencydependent parasitic loss at the maximum switching frequency is approximately
200 µW for the converter, which would dominate standby power. To reduce the frequency
dependent power loss, reducing the switching frequency, as the load is reduced, is necessary.
Frequency modulation can be used to both reduce the power consumption of the system and
to regulate the output voltage of the converter. By keeping the output voltage regulated
at the lowest voltage tolerated by the load, load current consumption can be minimized.
Regulation is performed on the output voltage of each converter using a hysteretic controller.
Hysteretic (thermostatlike) feedback has advantages of being simple to implement and
inherently stable for all loads. In addition, hysteretic feedback exhibits nearinstant response
to large steps in load current, which are common in wireless sensor nodes.
However, hysteretic feedback inherently introduces ripple in the output voltage, which
can be ﬁltered by a lowdropoutvoltage regulator (LDO) for rippleintolerant loads. In our
134
Sam pl ed
V ol t age
Ref er ence
+ ∆
 ∆
+
+ S
R
Q
Conv . Cl k .
SC
Conv er t er
en
O ut put
Sy s. Cl k .
Figure 7.12. Diagram of control logic
application, the radio is sensitive to ripple and variation of its supply, so an LDO is used
for postregulation, dropping an additional 50 mV and reducing ripple by approximately 20
dB.
Figure 7.12 shows the control system. Two clocked comparators [59] compare each
converter’s output to a pair of reference thresholds every 20 µs. If the output is above
the upper threshold, the converter’s clock is disabled until the output falls below the lower
threshold. The hysteresis zone between the two thresholds causes additional ripple on the
output in excess of the ripple discussed in section 5.1.
To bias the analog circuitry on the IC, an ultralowpower current reference was used.
The topology of the reference was chosen to minimize the bias current for a given size
resistor. Fig. 7.13a shows the structure of the current reference. The circuit is designed for
deep subthreshold operation, yielding an exponential relation between the drain current
and the gatesource voltage. The reference current is set by the resistor R and the voltage
drop across it, deﬁned by the diﬀerence in gatesource voltage between M1 and M2. The
value of this resistor is nominally 500 kΩ. At room temperature, the current reference
produces a current of 18 nA, independent of supply voltage. The current reference occupies
0.004 mm
2
of die area.
A reference voltage is required to perform output voltage regulation. This function is
performed by a compact bandgap voltage reference. Even with subthreshold conduction,
microamps of current are necessary to allow for suﬃciently low process variation. To reduce
the average power consumed by this bandgap reference, it was operated at a very low duty
135
V
DD
M1
2x
M2
M3
M4
M5
M6
R
i
OUT
V
DD
+
V
REF
R3
R1 R1
R2
1x 8x
(a) Subthreshold current source (b) Lowsupply bandgap reference
Figure 7.13. Schematics of analog references
+
v
IN
sample
sample
v
OUT
Figure 7.14. Lowleakage sample and hold circuit
cycle and sampled. Since the supply voltage is below the bandgap voltage of silicon (1.2
V), a nontraditional reference structure is used.
The bandgap core (in ﬁgure 7.13b) is based on the sub1V operational circuit presented
in [5, 7] with an improved implementation described in [53, 23]. It operates below the
bandgap voltage by adding currents, proportional and complementary to absolute temper
ature (PTAT and CTAT, respectively), instead of voltages. The startup and stabilization
of the bandgap circuit was optimized for speed to minimize the duty cycle.
The sample and hold circuit was speciﬁcally designed to reduce leakage and charge
injection to keep a constant output voltage with a long period between samples. Figure 7.14
136
shows the twostage sample and hold circuit. Opposing matched PMOS transistors counter
the charge injection from turning oﬀ the sampling transistors. Thickoxide transistors were
used for the input of the follower to reduce gate tunneling current, which otherwise becomes
signiﬁcant for small sampling capacitors and long hold times if thinoxide devices were used.
Since the sampling transistors dominate the leakage rate, a twostage circuit was used. The
ﬁrst sampling capacitor discharges linearly to the input (which is at a low potential when
the bandgap reference is oﬀ). The second capacitor, discharges based on the diﬀerence
between the two capacitor voltages, forming a quadratic voltage proﬁle. This sample and
hold topology is more spaceeﬃcient than a singlestage circuit using a larger capacitor for
a given sample rate.
Figure 7.15. Photomicrograph of power interface IC
The IC was fabricated using the STMicroelectronics 0.13 µm CMOS process. The die,
shown in ﬁgure 7.15, is approximately 2 mm on a side, signiﬁcantly smaller than discrete,
oﬀtheshelf system implementations. The die area is dominated by the ﬂying capacitors
and the pad ring. The analog circuitry and power transistors occupy the 420 µm× 200 µm
region at the bottomcenter of the IC. In this IC, the leakage current was approximately 6.5
µA, a combination of analog quiescent current, ESD structure and pad ring leakage, and
component leakage.
137
10
−3
10
−2
10
−1
10
0
0.55
0.6
0.65
0.7
0.75
0.8
Output Power Level [mW]
3
:
2
C
o
n
v
e
r
t
e
r
O
u
t
p
u
t
[
V
]
3:2 Regulated
3:2 Unregulated
10
−3
10
−2
10
−1
10
0
1.9
2
2.1
2.2
2.3
2.4
1
:
2
C
o
n
v
e
r
t
e
r
O
u
t
p
u
t
[
V
]
1:2 Regulated
1:2 Unregulated
10
−3
10
−2
10
−1
10
0
0
20
40
60
80
Output Power Level [mW]
E
f
f
i
c
i
e
n
c
y
[
%
]
Unregulated
Regulated
3:2 step−down (0.7V)
1:2 step−up (2.1V)
Figure 7.16. SC Converter output voltage and eﬃciency, V
in
= 1.15V
Both switchedcapacitor converters were tested over a range of loads. The output voltage
and eﬃciency of both converters with and without regulation are shown in ﬁgure 7.16.
The eﬃciency data include the quiescent current of the chip, so nominal converteronly
eﬃciencies would be higher. The results show that the regulation function works to achieve
a constant output voltage and to dramatically improve eﬃciency at low power levels. When
an overload condition causes the output to drop below the regulation level, the output
voltage and eﬃciency are not aﬀected by the feedback, since the converter is continuously
operating at maximum switching frequency. The 3:2 converter and 1:2 converter achieve
138
0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
1
Input Voltage Amplitude [V]
O
u
t
p
u
t
P
o
w
e
r
[
m
W
]
This rectifier
Ideal diodes
0.2V diodes
Matched resistor
0.5 1 1.5 2 2.5 3 3.5 4
0
20
40
60
80
100
Input Voltage Amplitude [V]
E
f
f
i
c
i
e
n
c
y
[
%
]
Figure 7.17. Power output and eﬃciency of synchronous rectiﬁer, V
B
= 1.2V , R
S
= 2.0kΩ,
100 Hz input
peak eﬃciencies of 83.7% and 84.3%, respectively. Eﬃciency for both regulated converters
remains above 60% for output power levels in a wide range between 20 µW and 4 mW.
The performance of the synchronous rectiﬁer is evaluated using a sinusoidal voltage
source, with a 2.0 kΩ series resistance, modeling the impedance of the scavenger. The
rectiﬁer was compared to three idealized interface models: an exact impedance match (2.0
kΩ load resistor), an ideal diode rectiﬁer into a ﬁxed voltage source, and a diode bridge
rectiﬁer with a forward voltage of 0.2 volts per diode. The third interface represents a
Schottkybased diode bridge rectiﬁer, typical of an oﬀtheshelf implementation.
139
0 1 2 3 4 5 6 7 8 9 10
−3
−2
−1
0
1
2
3
Time [ms]
V
o
l
t
a
g
e
[
V
]
,
C
u
r
r
e
n
t
[
m
A
]
Input Current
Open−Circuit Voltage
Input Voltage
Figure 7.18. Synchronous rectiﬁer waveforms (at 100 Hz)
The eﬃciency and output power of the synchronous rectiﬁer, and the idealized rectiﬁers,
are plotted in ﬁgure 7.17. A battery voltage of 1.2 V was used. Results were identical at
100 Hz and 1 kHz input frequency, and both measured data were nearly identical to the
performance of the ideal rectiﬁer. The frequency range below 1 kHz includes this scavenger
and the majority of available vibrational scavengers[45]. The peak eﬃciency of 88%, relative
to the matchedimpedance case, is obtained at an input amplitude of 2.7 V. At 10 kHz
input, the peak eﬃciency drops by 10%, due to delayassociated losses. Figure 7.18 shows
the voltage and current waveforms of the rectiﬁer with a 100 Hz sinusoidal input. At this
frequency, typical of the shaker output, the comparator delays are not noticeable, yielding
maximum eﬃciency.
Compared with the ideal diode rectiﬁer (the practical maximum eﬃciency), the rectiﬁer
obtains a relative eﬃciency of 95.8%. Of this 4% overall loss, 35% can be attributed to
chipwide quiescent current and 65% to rectiﬁer conduction loss and switching delay. The
synchronous rectiﬁer has been shown to be signiﬁcantly more eﬃcient than a diodebased
rectiﬁer, and to approach ideal behavior.
140
Operation Load Power Source Power Time/cycle Energy/cycle Eﬃciency
Standby 0.5 µW 8.6 µW 5.98 s 51.5 µJ 5.8%
Wakeup 1.4 mW 1.67 mW 2.5 ms 4.18 µJ 84%
Sensing 450 µW 540 µW 6 ms 3.24 µJ 84%
Transmission 2.5 mW 3.0 mW 5.5 ms 16.5 µJ 84%
Average 6.0 µW 12.57 µW 6.0 s 75.42 µJ 47.7%
Table 7.1. Energy eﬃciency over sensing period
7.6 System Eﬃciency
Since the PicoCube operates in numerous power modes, calculating the average power
consumption is important in sizing the scavenger and determining necessary input energy.
In batteryoperated systems, this average power consumption determines battery lifetime.
Additionally, by ﬁnding the mode with the largest energy consumption, improvements can
be made where they are most useful.
The PicoCube power conversion IC was tested at all the load conditions in ﬁgure 7.2.
Standby power was tested at the smallest load power available, as shown in ﬁgure 7.16.
The eﬃciencies in each of these modes are shown in table 7.1. Over the sixsecond period,
the sensor consumes 75.42 µJ, 68% of which is consumed during idle. While the system
eﬃciency of 47.7% is reasonable for such an application, further improvement of the standby
power would greatly improve the eﬃciency. At the target standby power of 1 µW, the overall
system eﬃciency would improve to approximately 75 %. Since the ESD pad ring on this
IC consumed approximately 2.5 µW, to achieve an ultralow standby power, a design with
the processor, radio, sensors and power processing circuitry on a single design would be
necessary.
141
Chapter 8
SwitchedCapacitor Converters for
Microprocessors
Switchedcapacitor (SC) converters have been used for many lowpower applications.
Chapter 7 discussed the use of SC converters for ultralowpower wireless sensor nodes.
However, using the design and optimization methods in chapters 2 and 3 and modern CMOS
processes, the power density of SC converters can be increased. This chapter describes the
feasibility and use of SC converters for highpowerdensity microprocessor applications.
Microprocessors have always been constructed using the most modern IC technologies.
While clock speeds and computational power per watt has been steadily increasing, the sup
ply power recently reached a practical limit imposed by thermal and economic constraints.
Supply voltage has become lower with each new generation while supply currents have in
creased to keep power constant. This trend has placed severe limits on the design of voltage
regulators (VRs). The number of pins on modern microprocessors devoted to power is in
the hundreds, often twothirds of the total number of pins [46, 17, 54]. To power numerous
power domains on a microprocessor, numerous power rails are required, dividing up the
power pins and package power planes, yielding an inherent design ineﬃciency.
Furthermore, the modern multicore trend has worsened this requirement, as each core
142
can be in a diﬀerent sleep state. If each core requires a diﬀerent supply voltage, based on
its sleep state, the number of input rails becomes unmanageable. For multicore micro
processors, having a single input voltage and ondie power converters to supply each core
becomes highly desirable. Switchedcapacitor (SC) DCDC converters are ideal for ondie
power conversion as they can be highly eﬃcient even at high power densities and require
no oﬀchip components, such as inductors.
Inductorbased buck converters have been investigated for this application, using on
die inductors [16, 22] and inpackage inductors [47, 20]. However, the ondie inductors
require a very specialized custom processing step and the converters made with them still
have poor eﬃciencies. The inpackage inductor buck converters are eﬃcient, but require
magnetics in package, which requires signiﬁcant chip metal and I/O usage. This metal and
I/O usage increases the series resistance of a converter, decreasing its eﬃciency. An ondie
SC converter requires no specialized processing steps and does not increase I/O utilization.
Using a standardcellbased design, as discussed in section 8.2.2, the ESR can be minimized,
resulting in a highlyeﬃcient converter.
8.1 Power Density vs. Scaling
As CMOS technology has progressed, transistors have improved their performance by in
creasing the ratio of conductance to gate capacitance (i.e. the f
T
of a transistor). Similarly,
equivalent oxide thicknesses have shrunk, resulting in denser onchip capacitors. Combining
these factors, the power density limit of SC converters has increased with the reduction of
feature size. Using parameters from the ITRS roadmap [1] from 2003 and 2007, estimated
circuit parameters can be found for numerous process generations. Table 8.1 shows the
relevant parameters for the 90nm through 16nm technology nodes.
These parameters can be used to make idealized device models as used in the analysis
methods developed in chapters 2 through 4. These models can then be used to evaluate
the performance of an SC converter using each of these technology nodes. In ﬁgure 8.1,
143
Technology Node: 90 nm 65 nm 45 nm 32 nm 22 nm 16 nm
Equiv. Oxide Thick. [nm] 1.2 1.0 0.9 0.55 0.5 0.4
Gate Leakage [A/cm
2
] 450 600 909 1250 1820 2500
V
DD
[V] 1.2 1.1 1.0 0.95 0.9 0.7
V
TH
[mV] 200 150 94 101 99 109
I
D,leak
[µA/µm]
1
0.05 0.2 0.71 0.74 0.55 0.48
I
D,on
[µA/µm]
1
1110 1300 1510 1820 2245 2535
C
G,total
[fF/µm]
1
1.0 0.9 0.84 0.8 0.58 0.48
1
per micron width of a minimumlength transistor
Table 8.1. Process parameters from the ITRS roadmap
TDP Die Area Power Density Total Pins Power Pins
[W] [mm
2
] [W/mm
2
]
65nm Merom [46] 35–80 W 143 0.24–0.56 780 (478) 555 (288)
45nm Atom [17] 0.6 – 2 W 25 0.08 441
65nm Itanium [54] 170 W 700 0.24
Table 8.2. TDP and pin counts for three modern Intel microprocessors
the performance of a 2:1 doubler converter is compared in two ways. First, the eﬃciency
of the converter is compared if the power density is held constant at 1 W/mm
2
. Second,
the power density of the converter when scaled is examined if eﬃciency is held constant at
85%. In both cases, the output voltage is scaled to match that of the process.
As the power density of SC converters improves with scaling, the die area expansion
required for ondie power conversion becomes minimal. Converter eﬃciency must be held
high such that performance does not decrease signiﬁcantly to keep total die power dissipation
constant. Using ondie power converters, the number of power pins for a microprocessor can
be greatly decreased. Table 8.2 shows a number of modern microprocessors, including their
thermal design points (TDPs) in terms of die area and the number of supply pins used.
The number of pins assigned to the power interface is dominant in the 65nm Core 2
144
90 65 45 32 22 16
82
84
86
88
90
T echnol ogy N ode [ nm]
E
f
f
i
c
i
e
n
c
y
[
%
]
a
t
1
W
/
m
m
2
0
1
2
3
4
P
o
w
e
r
D
e
n
s
i
t
y
[
W
/
m
m
2
]
a
t
8
5
%
E
f
f
i
c
i
e
n
c
y
Figure 8.1. SC converter performance versus ITRS technology node
Duo (Merom) processor, the consumergrade Intel microprocessor. In future multicore
processors, use of onchip SC converters will enable great reduction in the number of power
pins while only modestly increasing die area and TDP. If an 85% eﬃcient converter is used
to power a 32nm mobile version of the Merom, the die area would increase approximately
13% and the design power would increase from 35W to 42W. If MIM capacitors are used,
the die area may not increase and eﬃciency can be further improved, since the capacitors
can be built on top of the processor’s transistors.
8.2 Converter Design
The topology proposed for this application is the tripleratio, nineswitch topology
shown in ﬁgure 8.2a [27].By varying how the switches are clocked, according to ﬁgure
8.2b, conversion ratios of 3:2, 2:1 and 3:1 can be obtained. With a 1.8 V input, nominal
output voltages of 1.2, 0.9 and 0.6 V can be independently obtained. When the converter’s
output impedance is considered, these three output voltages drop to approximately 1.05,
145
C 1
C 2
S 1 S 2
S 4 S 3
S 5 S 6
S 7 S 8
S 9
V
I N
V
O U T
Switch 3:2 2:1 3:1
S1 φ1 φ1 φ1
S2 φ2 φ2 φ2
S3 φ1 φ1 —
S4 — φ2 φ2
S5 φ1 φ1 —
S6 — φ2 φ2
S7 φ1 φ1 φ1
S8 φ2 φ2 φ2
S9 φ2 — φ1
(a) Tripleratio topology (b) Switch conﬁgurations
Figure 8.2. Tripleratio topology and its switch conﬁgurations
0.8 and 0.5 volts, respectively. These three voltages can be used to supply a microprocessor
in fullspeed active, lowspeed active and standby modes, respectively. By operating the
microprocessor at one of the three optimal voltages, maximum eﬃciency can be obtained.
This topology will be evaluated for a 1 W/mm
2
application using the 32nm CMOS
process using ITRSbased estimated parameters. The PMOSbased ﬂying capacitors are
created using the native oxide thickness and an approximate bottomplate capacitance ratio
of 0.75%.
1
The power density of the converter is 1 W/mm
2
at the 1.05 V design point (with
a 1.8 V input). Figure 8.3 shows the eﬃciency of the tripleratio converter across a range
of output voltages for both a resistive load and a ringoscillator load. With the resistive
load, output current scales proportionally with output voltage such that the output power
density at 1.05 V is equal to 1 W. Similarly, the ring oscillator exhibits a currentvoltage
relationship as derived in section 8.2.1.
The converter achieves greater than 80% eﬃciency at the two primary operating points
(1.05 V and 0.8 V), as shown in ﬁgure 8.3. Using the ringoscillator load model, eﬃciency
at low powers increase because the supply current is reduced signiﬁcantly over the resistive
1
This value may be optimistically low. The optimization of the bottomplate capacitance of PMOSbased
oxide capacitors is discussed in section 8.3.3.
146
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
40
50
60
70
80
90
100
Out put V ol t age [ V ]
3: 2
2: 1
3: 1
E
f
f
i
c
i
e
n
c
y
[
%
]
Ri ng Osci l l at or L oad
Resi st i v e L oad
Figure 8.3. Eﬃciency plot of tripleratio topology in a 32nm process
load case. However, since the higherconversionratio topologies are inherently less eﬃcient
than the 3:2 topology, the 3:1 design point exhibits a lower conversion eﬃciency. If processor
operation is constrained to the optimal design points, the highest power eﬃciency can be
maintained.
8.2.1 Dynamic Voltage Scaling Analysis
To examine the eﬃciency and performance of an SC converter for microprocessors, the
performance of digital circuits as supply voltage varies should be examined. Previous work
explains the advantage of dynamic voltage scaling (DVS) [9] and shows a converter to achieve
DVS for an ultralowpower processor [41]. A 31stage ring oscillator will be considered as
a representative digital circuit to consider the eﬀects of voltage scaling on both frequency
and power consumption. These relationships will be derived from fundamentals and will be
evaluated using the 32nm ITRS process node.
First, the approximate frequency of a ring oscillator will be found. The time constant
147
associated with each inverter is related to the product between onstate resistance and input
capacitance:
τ = C
GS
R
ON
=
C
G,total
(1 +W
P
/W
N
)
G
D,on
((V
DD
−V
TH
)/(V
NOM
−V
TH
))
(8.1)
where V
NOM
is the gate voltage of the transistor at its full conductance, given by G
D,on
.
The gate capacitance is increased by the ratio of the width of the PMOS transistor to the
NMOS transistor. Since deep submicron devices are compared, the transistor’s conductance
is scaled by the overdrive voltage, given by the ratio in the denominator of (8.1). If the
switching point of the inverter is half the supply, the propagation delay of an inverter can
be represented as:
t
pd
= ln(2)
C
G,total
(1 +W
P
/W
N
)
G
D,on
((V
DD
−V
TH
)/(V
NOM
−V
TH
))
. (8.2)
The frequency of the ring oscillator can be easily found from (8.2):
f
OSC
=
G
D,on
((V
DD
−V
TH
)/(V
NOM
−V
TH
))
N ln(2) C
G,total
(1 +W
P
/W
N
)
∝
V
DD
−V
TH
V
NOM
−V
TH
(8.3)
where N is the number of stages in the oscillator. The proportionality shows the normalized
switching frequency of the oscillator as it varies with supply voltage.
Now that oscillator frequency has been derived, an estimate of power consumption can
easily be determined. Since the gate capacitance is fully charged and discharged each period,
the power consumption of each gate can be written as:
P
INV
= f
OSC
C
G,total
(1 +W
P
/W
N
) V
2
DD
+V
DD
I
D,Leak
(8.4)
where I
D,leak
is the leakage power of a single inverter. The total power consumption of the
inverter can be found by multiplying (8.4) by the number of inverters in the chain. Next,
(8.3) is substituted to ﬁnd the normalized relation between power consumption and supply
power:
P
V DD
= N
_
f
OSC
C
G,total
(1 +W
P
/W
N
) V
2
DD
+V
DD
I
D,Leak
)
_
. (8.5)
The relations in (8.3) and (8.5) can be evaluated to calculate the normalized frequency,
power consumption and energy per operation as the supply voltage varies. These three
148
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Suppl y Vol tage [ V]
N
o
r
m
a
l
i
z
e
d
Q
u
a
n
t
i
t
y
Frequency
Power
Energy/Operati on
Figure 8.4. Approximate ring oscillator performance versus supply voltage
quantities are compared in ﬁgure 8.4. Frequency varies approximately linearly with supply
voltage while the power consumption varies approximately by the cube of supply voltage.
Thus, the energy per operation of a typical digital circuit varies quadratically with supply
voltage. In typical digital circuits, most switches do not switch as fast as the clock, so the
ratio of leakage to switching power will be higher than in this model.
Since energy per operation (or Watts per MIPS) is the most important ﬁgure of merit
for powerlimited microprocessors, it is informative to examine the energy per operation of
the processor model with and without the use of an SC converter. Figure 8.5 shows the
normalized energy per operation of the ring oscillator model by itself, with the SC converter
and with an ideal linear regulator supplied from 1.8V. While the SC converter increases the
energy per operation of the converter, due to its power loss, three eﬃcient points can be
identiﬁed (shown by circles). These three points represent peak converter eﬃciencies and
good solutions to the tradeoﬀ between clock frequency and instruction energy. The SC
149
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Suppl y Vol tage [ V]
N
o
r
m
a
l
i
z
e
d
E
n
e
r
g
y
p
e
r
O
p
e
r
a
t
i
o
n
Di gi tal Onl y
Wi th SC Converter
Wi th LDO f rom 1.8V
Figure 8.5. Energy per operation using an SC converter
converter provides a substantial improvement in performance over a linear regulator while
operating at these three eﬃcient points.
8.2.2 Cell design
The SC converter designed so far in this chapter has not been designed for any speciﬁc
power. The idealized model, as used so far, takes only power density (i.e. output power
divided by die area) into consideration when determining eﬃciency. While a single converter
can be made of any size, there exists an optimal size for each interleaved phase, denoted a
cell. Each cell implements the topology shown in ﬁgure 8.2. Any number of these standard
cells can be interleaved to provide the necessary load power while reducing output voltage
ripple. Ripple and highfrequency noise can also be reduced by using a highspeed parallel
linear regulator [3, 2]. By carefully designing and optimizing a standard converter cell,
designing a multiplerail power distribution network is made signiﬁcantly easier and more
ﬂexible.
150
The converter cell size (and power level) is constrained by the loss factors that do
not scale directly with cell size. If a cell has a particular optimized layout, increasing or
decreasing the cell size represents a nearperfect dimensional scaling of the layout. Thus,
the number of metal squares used in the layout remains the same regardless of cell size.
Thus, the equivalent series resistance (ESR) of the metal used in any sized converter cell
is roughly constant. This constant resistance produces a loss which is proportional to the
square of output current, motivating the smallest practical cell size.
The second constraint on cell size is the control circuitry needed in any cell which
does not scale with cell size. Level shifters and any cellbased control logic fall into this
category. As the power level of the cell decreases, this constant control power becomes a
moresigniﬁcant portion of the total power loss. To determine the optimal size of a converter
cell, these two loss factors will have to be considered.
To consider the eﬀect of metal ESR, an estimate of metal resistance must be performed.
Through a careful layout, using careful design technique, a lowresistance layout can be
made. For purposes of illustration, a constant number of metal squares will be arbitrarily
assigned to each switch, capacitor and power rail. These numbers would ideally be extracted
from the layout of a standard cell in a real design. Each switch is typically designed to have
multiple ﬁngers such that it would contribute approximately one square of metal to the
layout. A similar design methodology is carried out with the capacitors, also yielding one
metal square each. The resistance contribution due to the power rails is less obvious, so 1.5
squares of metal will be assigned to both the input and ground rails, and two squares will
be assigned to the output rail.
Next, each of these resistance contributions must be weighted by the square of the
appropriate charge multiplier to get the equivalent resistance in terms of the output cur
rent. When the 8switch, 2capacitor 2:1 conversion ratio case is considered, each switch
and capacitor resistance sees a charge multiplier of onequarter, eﬀectively dividing each
resistance by a factor of sixteen. The output rail resistance is not divided at all, while
151
the resistances of the input and ground rails are divided by a factor of four. Adding these
weighted components yields 3.375 equivalent squares of metal.
Since the upper metal layers of a process are often thicker (and have a larger pitch), they
should be used for current carrying. A sheet resistance of 25 mΩ per square will be used,
typical of an upper metal layer in a modern process. Thus, the equivalent outputreferred
ESR of this converter is approximately 85 mΩ. This resistance remains approximately
constant regardless of the size of the cell. The loss associated with this resistance can be
simply calculated by:
P
ESR
= R
eq
I
2
OUT
. (8.6)
The second sizeconstraining loss is the control and levelshifting circuitry. This loss
is primarily proportional to switching frequency, so one must assume a nominal operating
frequency, typically close to the maximum switching frequency. The maximum switching
frequency can be obtained through the numerical optimization in section 3.3.2. In this
example, a switching frequency of 400 MHz will be considered, which is the typical fullload
switching frequency of this converter designed for a power density of 1 W/mm
2
using a 32
nm process.
In an example levelshifting circuit, the total transistor width is 8 µm per driver circuit,
yielding a total levelshifter capacitance of approximately 120 fF. At a nominal frequency of
400 MHz, the power associated with the level shifter is approximately 48 µW, independent
of cell size.
To ﬁnd the optimal cell size, the power loss associated with these two elements, as a
percentage of output power, should be optimized. The fullpower case will be used: a 3:2
converter with an output voltage of 1.05 V and a power density of 1 W/mm
2
. Figure 8.6
shows the relation between these two losses and the output power over a range of cell size.
For these speciﬁc resistive and control losses, the optimal cell size is approximately 0.025
mm
2
, handling 25 mW. At this optimal cell size, the total sizedependent loss subtracts
less than 1% from the total system eﬃciency, and the optimum region is fairly broad. The
optimal cell power of 25 mW is very practical from an implementation standpoint and will
152
0 . 0 0 1 0 . 0 1 0 . 1 1
0
1
2
3
4
5
6
7
8
L
o
s
s
P
e
r
c
e
n
t
a
g
e
[
%
]
C el l Po w er [ W ]
Figure 8.6. Nonscaling components of power loss versus cell size
allow the eﬃcient powering of lowpower rails. For higherpower rails, these converters can
be distributed around the die to reduce distribution losses and spread the heat dissipation
around the die. Also, each cell can function as an interleaved phase in a higherpower
multiphase converter, which will reduce output ripple and the size requirement of the
output capacitance.
8.3 Eﬃciency Improvements
If conversion eﬃciency is a higher priority than power density or other metrics, addi
tional techniques can be used to improve the eﬃciency past that calculated in section 8.1
and chapter 3. While the SSL and FSL output impedance losses are direct functions of
the component sizing and process parameters, the parasiticbased losses can be reduced
through additional design considerations. If parasitic losses are reduced, the converter can
be reoptimized around the reduced losses, resulting in a new optimized, moreeﬃcient con
verter. First, methods of recycling charge from both the transistors’ gate and drain parasitic
153
capacitances will be discussed, followed by methods to reduce the bottomplate capacitance
of MOS capacitors.
8.3.1 Resonant Gate Drive
The gate drive loss comprises the majority of the switchrelated parasitic loss of any SC
converter. With fullyintegrated converters, this loss could represent 2035% of the loss of
the converter, when properly optimized as discussed in chapter 3. Any method to recycle
some of the gate charge can go a long way towards improving the eﬃciency of the converter.
However, as the gates of the power devices must be wellcontrolled to ensure a positive dead
time, some charge recycling methods cannot be used. For example, the capacitor shorting
method in section 8.3.2 cannot be used as it directly charges one capacitance from the
other. If that method is used for gate charge recovery, both phase 1 and phase 2 switches
would be on simultaneously, potentially allowing excessive shortcircuit currents to ﬂow in
the converter.
In macroscale twophase SC converters, using a multiplewinding transformer to per
form the gate drive allows for both source isolation and gate resonance [4]. The power
transistor gates are directly driven at the resonance between the magnetizing inductance
of the transformer and the total gate capacitance. The primary winding is driven from a
bias supply through a resonancesensing circuit using ﬁxedwidth excitation pulses. Each
gate is driven with its own secondary winding, with polarity connected according to switch
phase. Since SC converters are not particularly sensitive to duty cycle, a pure zerocentered
sine wave is applied to each gate. This ensures suﬃcient deadtime and a simple control
scheme. In [4], the resonant gate drive reduces overall converter loss by 33 percent in a
discretecomponent implementation.
In an integrated converter, creating this transformer is nearly impossible. Integrated
inductors, in addition to the metal needed to distribute the gating signal, are too resistive
to exhibit suﬃcientlyhigh quality factors to make an integrated resonant gate drive scheme
practical. Additionally, the requirement of nonoverlapping gate drive signals make SC
154
based charge sharing schemes diﬃcult to implement. Such a scheme would require a long
switch deadtime to enable several periods of charge transfer switching. For medium to
highfrequency integrated SC converters, gate energy recycling is not yet feasible.
8.3.2 Drain Charge Recovery
The drainsource parasitic capacitance of the power transistors also consumes a signif
icant fraction of the power loss in an SC converter. However, as the voltage across this
parasitic capacitance does not control the switch state, it can be manipulated more ﬂexibly
than the gate capacitance. If we assume the output and input sources are lowimpedance,
and the ﬂying capacitors are much larger than the total circuit parasitic capacitors, we
note that all the drain parasitic capacitances connect the ﬂying node associated with a
ﬂying capacitor and incremental ground. Thus, all of these parasitics, in addition to the
bottomplate parasitic capacitance of the ﬂying capacitors, are in parallel. Using a single
chargerecovery circuit per ﬂying capacitor, the eﬀects of nearly all the drain and bottom
plate capacitances will be reduced.
Using a simple 2:1 circuit as an example, such as one of the two interleaved phases
shown in ﬁgure 8.7a, drain charge recovery will be demonstrated. With a single 2:1 circuit,
the parasitic capacitance is charged during phase 1 and discharged during phase 2. If two
such circuits are interleaved, i.e. clocked 180 degrees apart, the charge recovery circuit
can transfer charge between the parasitic capacitances of each phase during the deadtime
between switching periods. In a 2:1 converter, since each interleaved phase only has a single
ﬂying capacitor, the charge recovery circuitry can connect to the bottom terminal of the
ﬂying capacitor
2
, as shown in ﬁgure 8.7a.
Two charge recovery methods will be discussed here, both shown in ﬁgure 8.7b. The ﬁrst
method, designated drain shorting, uses a single power transistor that is turned on during
the deadtime between each primary phase (thus, twice per period). This conductance path
equalizes the voltage on each of the two equivalent parasitic drain capacitances. Thus,
2
Alternately, the charge recovery circuit can be connected to each of the top nodes of the ﬂying capacitors
155
V
I N
V
I N
V
OU T
V
OU T
Char ge
Recov er y
Ci r cui t
φ 1 φ 2
φ 1
φ 1
φ 1
φ 2
φ 2
φ 2
(a) 2:1 ladder interleaved phases, noting terminals used for charge recovery
D r a i n S h o r t i n g :
R e s o n a n t D r a i n :
(b) charge recovery circuits
Figure 8.7. Drain charge recovery using a twointerleavedphase 2:1 converter
156
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.2
0.4
0.6
0.8
1
T i me [ ns]
D
r
a
i
n
V
o
l
t
a
g
e
s
gat e 2 gat e 1
D r ai n Shor t
Resonant
N o Char ge Recov er y
Figure 8.8. Waveforms of drain charge recovery methods
during the next phase, the amount of charge needed to charge the parasitic capacitance is
reduced approximately by a factor of two.
The second method, denoted resonant drain, uses an inductor to transfer the charge
from the parasitic capacitance in one interleaved phase to the opposite capacitance. If the
current path was lossless, this transfer of charge would be complete, eliminating the drain
parasitic and bottomplate parasitic loss. However, as the path resistance is ﬁnite, there
will be some loss using this method. In entirelyintegrated converters, the area cost due to
this inductor must be considered. Additionally, careful layout must be performed to ensure
this RL charge transfer network has a quality factor greater than one. If the resonant drain
method is not feasible, the drain shorting method can be used.
Figure 8.8 shows a single phase transition of the converter shown in ﬁgure 8.7a. The
size of the shorting transistor is similar to each of the power transistors in the circuit.
An inductance of 30 nH is used to transfer the charge between the 10 pF parasitic drain
capacitances. The voltage at the negative terminal of both of the ﬂying capacitors is shown
157
for each of the two recovery methods and without any charge recovery method. Both
methods cause the drain voltages to partially transition to the opposite state during the
deadtime of the primary phase clocks. The drain shorting method recovers approximately
half of the drain charge, while this implementation of the resonant charge method recovers
about 75% of the parasitic charge. In both cases, the deadtime must be suﬃciently large
to enable a chargerecovery pulse between main phase clocks.
Using either of these charge recovery methods, or any other parasitic reduction method,
modiﬁes portions of the power loss equation. Thus, when a parasitic reduction method is
used, the converter must be reoptimized while accounting for the modiﬁcations to yield a
new optimal design.
8.3.3 Reducing BottomPlate Capacitance
The previous two sections (8.3.1 and 8.3.2) discuss additional circuits that reduce the
power lost to two diﬀerent parasitic capacitances in an SC converter. This section discusses
improvements to the layout of MOSbased capacitors to reduce their bottomplate parasitic
capacitance. This improvement originates from two adjustments. First, the area of each
capacitor cell is maximized. Second, the nwell for a PMOSbased capacitor should be
biased appropriately.
MOS capacitors for SC converters are typically made using PMOSbased capacitors
3
or triplewell NMOS capacitors. This section will examine PMOSbased capacitors as they
require no special processing steps. Thus, the nwell diﬀusion capacitance of the capacitor
cell is the dominant parasitic of the capacitor. Since the capacitance of a junction is related
to both the area and perimeter of the well, but the primary oxide capacitance is only related
to area, the ratio of parasitic to primary capacitance can be minimized by making the cell
(and thus its nwell) as large and as square as the design rules for the process allow.
Next, the terminals must be biased correctly in order to minimize the parasitic capaci
tance. For maximum primary capacitance, the source and drain of the PMOSbased device
3
Assuming a pdoped substrate
158
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
Bias Voltage [V]
P
a
r
a
s
i
t
i
c
C
a
p
a
c
i
t
a
n
c
e
R
a
t
i
o
[
%
]
n−well to substrate
source to n−well
Figure 8.9. Parasitic capacitance ratios for body and well capacitances
are connected together and used as the positive terminal. The gate of the device is used
as the negative terminal. However, ﬂexibility exists in the biasing of the capacitor’s nwell.
Two junction capacitances are connected to the nwell tie: the sourcewell capacitance and
the wellsubstrate capacitance. Based on how the nwell is biased, either of these capaci
tances can act as the bottomplate capacitance of the device. Finally, if a DC voltage is
used to bias the nwell against either the substrate or source, the diﬀusion capacitance can
be made smaller. In this analysis, the source to substrate voltage remains low while the
nwell bias voltage is adjusted.
Figure 8.9 shows a graph of the ratio between the parasitic bottomplate capacitance
and the primary capacitance. A PMOSbased capacitor made with 2 µm long transistor
ﬁngers and well dimensions of 40 µm by 40 µm was simulated in a 65 nm process. One curve
shows the bottomplate parasitic if the well is tied to a DC potential above the substrate,
such that the sourcewell capacitance becomes the bottomplate capacitance. The second
curve shows the same ratio if the well was tied to a DC potential above the source, shorting
the sourcewell capacitance, such that the wellsubstrate junction capacitance becomes the
bottomplate capacitance. When the nwell is biased above the source of the transistor by
159
5 volts, the bottomplate parasitic ratio becomes 0.7%, which is an impressivelylow ratio
for a MOS capacitor.
By using these methods of reducing the bottomplate parasitic capacitance, higher power
densities can be obtained for the same eﬃciency. These parasiticreduction methods provide
the necessary eﬃciency improvements to make microprocessorlevel SC converters practical.
160
Chapter 9
Conclusions
This work has developed both fundamental analysis and practical design methods for
switchedcapacitor (SC) DCDC power converters. SC converters can be used for numerous
applications in the power conversion space, since they have numerous advantages over tra
ditional inductorbased power converters. First, since they use no inductors, SC converters
can be easily integrated on a silicon chip or into other applications where magnetics are
impractical. In section 4.4, SC converters were shown to have superior silicon and reactive
element utilization compared with traditional magneticsbased converters such as the buck
and boost converters. In chapter 7, SC converters were shown to operate eﬃciently over
many orders of magnitude of power, which is diﬃcult for many inductorbased converters.
Although inductorbased converters perform regulation highly eﬃciently, regulation is pos
sible using SC converters as discussed in chapter 5. These advantages strongly motivate the
use of SC converters in many applications.
In the analysis chapters of this work, chapters 2 through 4, a thorough but simple
analysis method was developed that predicts the output resistance and eﬃciency of an SC
converter. The foundation of this method relies on charge multipliers, the ratio of the
charge ﬂowing through a component to the output charge ﬂow. The charge multipliers for
any SC topology can be found by simple inspection or using the circuittheoretic method
discussed in appendix A. These charge multipliers allow for the simple calculation of output
161
impedance, which, in turn, allows the optimal sizing of both the capacitors and switches
in an SC converter. Systemwide switch area and switching frequency were optimized to
yield the minimal power loss at a speciﬁc design point in chapter 3. A MATLABbased
tool can automate these design methodologies to enable rapid evaluation of SC topologies
as discussed in appendix B. These design methodologies enable the optimal design of SC
converters for any application, from sensor nodes to microprocessors and more.
Three applications for SC converters were discussed in chapters 6 through 8. By using a
hybrid boostSC converter topology, a high voltage was generated with maximal eﬃciency
with a converter of minimum mass. This converter was used to control piezoelectric actu
ators on a twogram MicroGlider, as reported in chapter 6. Since many SC topologies can
be run in an openloop conﬁguration, the drive strategies for them are often simpler than
for an inductorbased converter.
Chapter 7 described a power conversion and conditioning integrated circuit used for
an energyharvesting wireless sensor node. In this application, two ondie SC converters
were used to generate system voltage rails of 2.1 and 0.7 volts from a 1.2 volt battery. SC
converters were found to be superior to inductorbased converters in miniature sensor node
systems as they can be fully integrated and they run eﬃciently down to microwatt levels.
Finally, SC converters can be used for signiﬁcantly higher power densities and higher
levels of integration than traditional magneticsbased converters. Chapter 8 describes a
speciﬁc nineswitch topology for applications in powering microprocessors. In a 32nm
process, the area required to perform ondie power conversion is approximately 13%. As
CMOS technology advances, the power density of SC converters increases, while the power
produced by typical microprocessors remains approximately constant due to thermal con
straints. Total processor die area also remains approximately constant as the number of
transistors increases to counter process scaling. Thus, if ondie SC converters are used
in the future, they will occupy an everdecreasing percentage of the die. Ondie SC con
verters are advantageous over external inductorbased converters since they can provide
local supplies for each core in a manycore processor. Additionally, SC converters can have
162
extremelyfast transient responses compared with inductorbased converters where the in
ductor current limits response time. SC converters can better respond to the fast load
transients associated with computational blocks turning on and oﬀ. SC converters may
replace inductorbased converters in even highpower, highperformance applications due
to these advantages.
Throughout this work, SC converters have been found to be simple to analyze, enabling
the creation and analysis of many topologies. The design methods developed allow intel
ligent, optimized design of SC converters for many applications. Indeed, SC converters
need not be limited to lowpower, unregulated designs but can expand to compete with
traditional converters in all realms of power conversion.
163
Appendix A
NetworkTheoryBased Analysis
for SwitchedCapacitor Converters
The analysis methods presented in chapter 2 are suﬃcient when a converter’s charge
multipliers can be found by inspection. For morecomplex topologies, or to automate the
analysis of switchedcapacitor (SC) converters, a networktheory based analysis method is
needed. In addition, by developing the theory of SC converters, a greater understanding
of the constraints behind the formulation and operation of SC converters can be obtained.
This chapter is based on reference [27] and uses the theory presented in reference [13]. The
section will ﬁrst start by summarizing the relevant circuit theory, including the fundamental
loop matrix and the fundamental cutset matrix. Next, these methods are extended to SC
converters and the capacitor charge multipliers are derived. A few theorems on properties
of SC converters are stated and proven. The dynamics of SC converters will then be
investigated from a networktheoretic standpoint.
A.1 Summary of Circuit Theory
Circuit theory is based on using speciﬁc techniques to mathematically describe electri
cal circuits. This section describes the procedure for extracting network parameters from
164
a circuit. For any electrical circuit, a directed graph (digraph) can be constructed which
represents the topology of the circuit while discarding the properties of individual circuit
elements. The reference direction of a circuit branch determines the direction of its repre
sentative branch in the digraph. The arrow on each branch represents the reference direction
of that branch. Thus, the power dissipated by a given element, denoted by index i, is given
by:
P
i
= i
i
v
i
(A.1)
From a connected digraph G, a tree T can be constructed from selected branches of the
digraph. While more than one tree can exist for any digraph, each tree T must have the
following properties:
1. T is connected (i.e. there is a path through T connecting any two nodes).
2. T contains all the nodes in digraph G.
3. T contains no loops.
Figure A.1a shows a simple electric circuit which is then represented as a digraph in
ﬁgure A.1b. Each component is transformed into a branch in the digraph where the direction
of the arrow indicates the polarity of that component.
+
V 1
S 1 S 2
C 1 C 2 I 1
V 1
C 2
C 1
S 1
S 2
I 1
(a) Circuit (b) Graph; twigs shown with dark lines
Figure A.1. An example circuit with graph representation
165
Each branch in digraph G can be categorized as either a twig if it is contained in the
tree T or a link if it is not. For a digraph with n nodes and b branches, there are n − 1
twigs and l = b −n + 1 links. Twigs and links have the following important properties:
• For each link, there is a unique path along tree T connecting the two endpoints of
the link. This link and set of twigs in the path form the fundamental loop associated
with the link.
• For each twig in T, there exists a unique set of links such that a closed path can be
drawn through the twig and the set of links such that the graph’s nodes are split into
two nonempty disjoint sets. This twig and set of links form the fundamental cut set
associated with that twig.
These fundamental loops and fundamental cut sets depend on the selection of tree T, but
again are unique given a choice of tree.
Based on the choice of tree, the branch currents i
i
and voltages v
i
can be grouped into
vectors i and v of dimension b with the links occurring ﬁrst and the twigs last. Thus,
i =
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
i
1
.
.
.
i
l
i
l+1
.
.
.
i
b
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
v =
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
v
1
.
.
.
v
l
v
l+1
.
.
.
v
b
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
(A.2)
Kirchoﬀ’s Voltage Law (KVL) states that the voltages around a closed loop sum to
zero. Thus, the voltages around any fundamental loop can be summed and set equal to
zero. Following the loop around in the direction given by the corresponding link’s direction,
each twigs’ voltage is summed positively if its direction is the same as the link’s direction,
or subtracted if its direction opposes that of the link. For each link in G, a KVL equation
can be constructed from its fundamental loop. For a digraph with l links, l equations exist,
166
which can be formed into one matrix equation:
Bv = 0. (A.3)
B is the fundamental loop matrix of size l ×b where each element is either 0, 1 or −1. Since
each fundamental loop contains only one link, B can be written in the form:
B =
_
1
l
B
t
_
(A.4)
where 1
l
is an l ×l identity matrix.
Similarly, Kirchoﬀ’s Current Law (KCL) states that the sum of currents going into a
node (or subgraph) is equal to zero. For each fundamental cut set of the digraph G, the
currents through each element in the cut set in the direction of the selected subgraph must
sum to zero. If the deﬁning twig of a cut set points from subgraph A to subgraph B, the
links in the cut set that also point from A to B are added positively. Links in the cut set
that point the opposite direction are instead subtracted. For a network with n − 1 twigs,
the n −1 fundamental cut set equations can be formed into a matrix equation:
Qi = 0 (A.5)
where Q is the fundamental cut set matrix corresponding to the digraph G and the tree T.
The fundamental cut set matrix is the dual of the fundamental loop matrix and is related
by the following relationship [13]:
Q =
_
Q
l
1
n−1
_
=
_
−B
t
1
n−1
_
(A.6)
A.2 Modeling SwitchedCapacitor Networks
This section will derive the component voltages and charge multipliers for an SC con
verter based on fundamental networktheorybased methods. In this section, only properly
posed singleinput, singleoutput twophase converters will be considered, as speciﬁed in
chapter 2. Further study of the proper formation of SC converters is presented in section
A.3.
167
+
+
V
I N
C 3
C 2
C 1
V
O U T
S 1
S 2
S 3
S 4
S 5
S 6
+
+
V
I N
C 3 C 2
C 1
V
O U T
+
+
V
I N
C 3
C 2
C 1
V
O U T
(a) Topology (b) Phase 1, twigs in bold (c) Phase 2, twigs in bold
Figure A.2. 3:1 Ladder topology, including twig designations in each phase
In this section, a 3:1 ladder converter will be used as an example, as shown in ﬁgure
A.2a. Figures A.2b and A.2c show the phase networks (i.e. capacitor conﬁgurations) in
phases 1 and 2, respectively. For each phase network, a tree T
1
or T
2
can be constructed.
The twigs in each tree are shown in bold (although the links and twigs depend on the choice
of tree). This set of links and twigs will be used as an example in the following analysis.
For a properlyposed twophase converter, it is possible to choose the trees T
1
and T
2
such
that each capacitor and output voltage source is a twig in one phase and a link in the other.
In addition, the input source is classiﬁed as a twig in both phases. This section considers
only properlyposed twophase, twoport SC converters.
A.2.1 Finding the Conversion Ratio and Component Voltages
For each phase, a fundamental loop matrix can be constructed based on that phase’s
network. Unlike section A.1, the voltages will not be sorted linkﬁrst, as that sorting is not
168
consistent between phases. Instead, the voltage vector will be deﬁned as:
v =
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
.
.
.
v
ck
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
. (A.7)
From the two phase networks, two KVL equations based on the fundamental loop ma
trices are obtained as follows:
B
1
v = 0 B
2
v = 0 (A.8)
To ﬁnd the nominal conversion ratio and component voltages, the output current is assumed
to be zero, so each capacitor must maintain a constant voltage in steady state. Thus, the
phasebased KVL equations in (A.7) must hold simultaneously.
B v =
_
¸
_
B
1
B
2
_
¸
_v = 0 (A.9)
For example, the B matrix and the corresponding KVL equation for the threecapacitor
ladder converter would be:
_
¸
¸
¸
¸
¸
¸
¸
_
−1 1 0 1 1
0 0 1 −1 0
0 −1 0 1 0
0 0 −1 0 1
_
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
v
c2
v
c3
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= 0 (A.10)
By inspection, the matrix in (A.10) has rank 4. Thus, this KVL equation has a single
degree of freedom, which corresponds to the input voltage. All voltages in the unloaded
circuit can be found in terms of the input voltage by manipulating (A.10).
In order to ﬁnd the converter voltages in terms of the input voltage, the B matrix will
169
be partitioned as follows:
_
¸
¸
¸
¸
¸
¸
¸
_
−1 1 0 1 1
0 0 1 −1 0
0 −1 0 1 0
0 0 −1 0 1
_
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
v
c2
v
c3
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
=
_
b
in
B
c
_
_
¸
¸
¸
¸
_
V
IN
v
c
V
OUT
_
¸
¸
¸
¸
_
= 0 (A.11)
From (A.11), the capacitor and output voltage vector can be found simply by solving
(A.12), since B
c
is square and fullrank for properlyposed converters:
B
c
_
¸
_
v
c
V
out
_
¸
_ = −b
in
V
IN
. (A.12)
This method can be used to ﬁnd the capacitor voltages and output voltage for the 3:1
ladder converter in terms of the input voltage:
_
¸
¸
¸
¸
¸
¸
¸
_
v
c1
v
c2
v
c3
V
out
_
¸
¸
¸
¸
¸
¸
¸
_
= −
_
¸
¸
¸
¸
¸
¸
¸
_
1 0 1 1
0 1 −1 0
−1 0 1 0
0 −1 0 1
_
¸
¸
¸
¸
¸
¸
¸
_
−1
_
¸
¸
¸
¸
¸
¸
¸
_
−1
0
0
0
_
¸
¸
¸
¸
¸
¸
¸
_
V
IN
=
_
¸
¸
¸
¸
¸
¸
¸
_
1/3
1/3
1/3
1/3
_
¸
¸
¸
¸
¸
¸
¸
_
V
IN
. (A.13)
Thus, each of the capacitors in the circuit supports onethird of the input voltage, and the
converter has a conversion ratio of 1/3. While these numbers can easily be determined by
inspection, for more complicated converters or for use in an automated design tool, this
method can be used to determine conversion ratio and component voltages.
A.2.2 Determining the Charge Multiplier Vector
So far, unloaded SC networks have been considered where capacitor voltages are con
stant and no current ﬂows in the converter. When the load current is nonzero, the capacitor
voltages change during phase transitions, but reach a periodicsteadystate pattern under
constant line and load operating conditions. The charge multipliers, the ratio of charge ﬂow
170
in a component to the output charge ﬂow, is derived here, based on a network theoretic
formulation. As in section 2.1, this analysis will assume operation in slowswitching limit
(SSL) and will thus neglect the small onstate resistance of the switches in the converter.
To transfer charge between input and output, charge must be transferred between the
capacitors. In steady state, the capacitor voltages are in periodic steady state. Because
operation in the SSL is being considered, there is an impulsive charge transfer, represented
by ∆q
2
during the transition from phase 1 to phase 2, and another charge transfer ∆q
1
during the opposite transition. Over an entire clock period, no net current ﬂows in each
capacitor, and thus ∆q
1
and ∆q
2
obey the following relationship:
∆q
1
c
= −∆q
2
c
(A.14)
where ∆q
1
c
and ∆q
2
c
are the components of ∆q
1
and ∆q
2
, respectively, that correspond
to the capacitors. Since ∆q is an integrated current (charge ﬂow), it must satisfy KCL for
each phase transition:
Q
j
∆q
j
= 0 (A.15)
where Q
j
is the fundamental cutset matrix for the transition in phase j, and can be found
by using the methods in section A.1 or from the identity in equation A.6.
By examining the fundamental cutsets for the phase 1 and 2 networks in ﬁgures A.2b
and A.2c, respectively, the KCL equations for the ladder converter can be found:
_
¸
¸
¸
¸
_
0 −1 0 0 1
0 −1 1 1 0
1 1 0 0 0
_
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆q
1
c1
∆q
1
c2
∆q
1
c3
∆Q
1
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= 0
_
¸
¸
¸
¸
_
0 0 1 0 1
0 1 0 1 0
1 0 0 0 0
_
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
2
IN
∆q
2
c1
∆q
2
c2
∆q
2
c3
∆Q
2
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= 0
(A.16)
Using the identity in equation A.14, the two KCL equations in (A.16) can be combined to
form a system of equations including both ∆Q
1
OUT
and ∆Q
2
OUT
. Since the charge multipliers
represent the charge ﬂows in terms of the output current, the following transformation will
171
be used to convert ∆Q
OUT
and ∆Q
OUT,diff
= ∆Q
OUT,2
−∆Q
OUT,1
:
_
¸
_
∆Q
OUT,diff
∆Q
OUT
_
¸
_ = T
Q
∆q =
_
¸
_
−1 1
1 1
_
¸
_
_
¸
_
∆Q
1
OUT
∆Q
2
OUT
_
¸
_ (A.17)
This transformation can then be applied to (A.16) to create a single KCL matrix equation:
Q∆q =
_
¸
_
Q
1
Q
2
_
¸
_
_
¸
_
I
T
Q
−1
_
¸
_ ∆q = 0 (A.18)
Substituting (A.16) into (A.18) in the case of the ladder converter yields:
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
0 0 −1 0 0 −1/2 1/2
0 0 −1 1 1 0 0
1 0 1 0 0 0 0
0 0 0 −1 0 1/2 1/2
0 0 −1 0 −1 0 0
0 1 0 0 0 0 0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆Q
2
IN
∆q
1
c1
∆q
1
c2
∆q
1
c3
∆Q
OUT,diff
∆Q
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= 0 (A.19)
The transformed twophase fundamental cutset matrix Q for the ladder converter has
a rank of 6. The single degree of freedom in this equation corresponds to the output current
∆Q
OUT
. To solve the charge ﬂows in terms of the output current, Q will be partitioned as
follows:
Q∆q =
_
Q
C
q
out
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆Q
2
IN
∆q
c
∆Q
OUT,diff
∆Q
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
. (A.20)
Since Q
C
is square and fullrank for properlyposed converters, as discussed in section
172
A.3, the currents are fully speciﬁed by the topology, and can be found by:
Q
C
_
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆Q
2
IN
∆q
c
∆Q
OUT,diff
_
¸
¸
¸
¸
¸
¸
¸
_
= −q
out
∆Q
OUT
. (A.21)
Using the ladder converter example KCL equations in (A.19), the current ﬂow in the
converter can be found as:
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
0 0 0 −1 0 1/2
0 0 −1 0 −1 0
0 1 0 0 0 0
0 0 −1 0 0 −1/2
0 0 −1 1 1 0
1 0 1 0 0 0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
−1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆Q
2
IN
∆q
c1
∆q
c2
∆q
c3
∆Q
OUT,diff
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= −
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
1/2
0
0
1/2
0
0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
OUT
(A.22)
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
1
IN
∆Q
2
IN
∆q
c1
∆q
c2
∆q
c3
∆Q
2
OUT
−∆Q
1
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
−1/3
0
1/3
2/3
−1/3
1/3
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
∆Q
OUT
. (A.23)
Equation (A.22) determines the charge ﬂows in the converter in terms of the output current.
Thus, the charge multipliers for the capacitors can easily be determined by extracting the
terms in (A.23) corresponding to the capacitors:
_
¸
¸
¸
¸
_
a
c1
a
c2
a
c,3
_
¸
¸
¸
¸
_
=
_
¸
¸
¸
¸
_
1/3
2/3
−1/3
_
¸
¸
¸
¸
_
. (A.24)
The methods in this chapter develop a straightforward circuit theory based method
for determining component voltages and charge multipliers for any SC converter. This
173
method can be used for complex topologies where determining the values by inspection is
inconvenient. Additionally, if a computerbased SC analysis program is needed, this method
can be used.
Switch Charge Multiplier Vectors
To determine the SSL charge multipliers, the resistance drops across the converter’s
switches were neglected. However, in the FSL, the switch onstate resistance is the dominant
converter loss. Since the currents in the circuit are still constrained by the topology, as in
section A.2.2, the capacitor charge ﬂows are the same as calculated above.
When the open and closed switches are added to the phase networks of a converter, they
can be incorporated in both the KVL and KCL equations to determine their charge ﬂows
and blocking voltages. In each of the phase networks, the closed switches are usually twigs,
as they connect two nodes which ordinarily would be the same node in a capacitoronly
tree.
1
The current through an onstate switch can be related to the capacitor currents by
ﬁnding the fundamental cutset corresponding to that switch during the phase which it is
on. The resulting equation relates the currents in this switch to the currents through the
link capacitors. Two matrix equations can be constructed representing the currents through
the onstate switches in each phase:
i
1
r
= Q
1
RC
i
1
c
i
2
r
= Q
2
RC
i
2
c
(A.25)
The Q
1
RC
and Q
2
RC
matrices are deﬁned to include rows of zeros corresponding to the
oﬀstate switches to ease the dynamics calculation in section A.4. The two phasebased
switch fundamental cutset matrix relations for the 3:1 ladder converter, in ﬁgure A.2, are
1
Some switches in some topologies may be redundant from a graph theory perspective and are thus
designated links.
174
as follows:
i
1
r
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
1 0 0 0
0 0 0 0
−1 1 0 0
0 0 0 0
0 −1 0 0
0 0 0 0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
_
i
1
c1
i
1
c2
i
1
c3
i
1
OUT
_
¸
¸
¸
¸
¸
¸
¸
_
, i
2
r
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
0 0 0 0
0 0 −1 0
0 0 0 0
0 0 1 −1
0 0 0 0
0 0 0 1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
_
i
2
c1
i
2
c2
i
2
c3
i
2
OUT
_
¸
¸
¸
¸
¸
¸
¸
_
(A.26)
To ﬁnd the corresponding charge multiplier for each switch, the switch fundamental cutset
matrix where the corresponding row is nonzero is multiplied with the capacitor charge
multipliers, and the output charge during that phase substituted for I
OUT
:
a
j
r
= Q
j
RC
_
¸
¸
¸
¸
¸
¸
¸
_
a
j
c1
a
j
c2
a
j
c3
i
j
OUT
/I
OUT
_
¸
¸
¸
¸
¸
¸
¸
_
, a
r
= a
1
r
+a
2
r
. (A.27)
Since the open switches connect two nodes that are already included in the tree, open
state switches are always links. The voltages across these openstate switches can be calcu
lated in terms of the capacitor and input and output source voltages in the circuit, neglecting
the voltage across the onstate switches. Fundamental loop equations can be created in
volving each oﬀstate switch and the twig capacitors and sources.
2
The switch blocking
voltages can be found through the following KVLlike equations involving two phasebased
switch fundamental loop matrices:
v
1
r
= B
1
RC
v
c
v
2
r
= B
2
RC
v
c
(A.28)
The two phasebased switch fundamental loop matrix relations for the 3:1 ladder converter,
2
If switch drops were included, the switch blocking voltage may vary slightly, depending on load.
175
in ﬁgure A.2, are as follows:
v
1
r
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
0 0 0 0 0
1 0 0 −1 −1
0 0 0 0 0
0 0 0 1 0
0 0 0 0 0
0 0 0 0 1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
v
c2
v
c3
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
, v
2
r
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
1 −1 −1 0 0
0 0 0 0 0
0 1 0 0 0
0 0 0 0 0
0 0 1 0 0
0 0 0 0 0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
v
c2
v
c3
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
(A.29)
Since the voltages on the sources and capacitors are nearly constant in typical operation,
the DC values of voltage, calculated in section A.2.1, are used in (A.29).
These matrices are used to ﬁnd the currents through and voltages across the switches
in the converter. They are also used to calculate converter dynamics in section A.4.
A.3 Criteria for ProperlyPosed SC Topologies
While the assumption that properlyposed converters has been used throughout this
work, little examination has been made on what properties a properlyposed converter has.
First, the converters have been formulated to have a single input and output voltage source
while eliminating unnecessary bypass (DC) capacitors. The following analysis will examine
the fundamental loop matrix B
C
, in (A.11) and the fundamental cutset matrix Q
C
, in
(A.20). In the example in the previous section, the 3:1 ladder converter, these two matrices
have been square and invertible. This criterium ensures that a converter is properlyposed.
This section examines converters that are not properlyposed and modiﬁcations that can
be used to make a converter properlyposed.
The next example will consider the 2:5 seriesparallel topology, shown in ﬁgure 4.3. As
shown, the two phase networks are shown in ﬁgures A.3ab. The twig assignments for each
network are shown in bold. By inspection, and the analysis in section 4.2.4, all formulations
in ﬁgure A.3 perform the desired power conversion, however, only one is properlyposed (or
176
+ +
V
I N
V
O U T
C 1 C 2 C 3
C 4 C 5 C 6
+ +
V
I N
V
O U T
C 1
C 2
C 3
C 4
C 5
C 6
(a) Phase 1, original (b) Phase 2, original
+ +
V
I N
V
O U T
C 1 C 2 C 3
C 4 C 5 C 6
+ +
V
I N
V
O U T
C 1
C 2
C 3
C 4
C 5
C 6
(c) Phase 1, 1 set equalizing switches (d) Phase 2, 1 set equalizing switches
+ +
V
I N
V
O U T
C 1 C 2 C 3
C 4 C 5 C 6
+ +
V
I N
V
O U T
C 1
C 2
C 3
C 4
C 5
C 6
(e) Phase 1, 2 sets equalizing switches (f) Phase 2, 2 sets equalizing switches
Figure A.3. Three conﬁgurations of a 2:5 seriesparallel topology
177
wellposed). In the ﬁrst case, there are an excessive number of twigs in the two phase
networks. With excessive twigs, the KVL equation is underconstrained (as there are few
links to contribute equations). Since KVL cannot be solved, the DC voltages on each
capacitor cannot be explicitly solved, but only a few relationships between the voltages
can be found. Additionally, the fundamental cutset matrix is no longer square, so the
KCL equations may be overconstrained. While the converter can operate eﬀectively, there
is no guarantee on the capacitor voltages remaining below their limits, and therefore the
converter is not properlyposed.
Figures A.3cd show the networks if additional switches are connected in phase 2, as
shown. These equalize the voltages between the capacitors in phase 2. In this conﬁguration,
both the fundamental loop matrix and fundamental cutset matrix are square and fullrank.
Thus, this converter is inherently properlyposed. Another indication that this converter is
properlyposed is that each capacitor (and the output source) can be made a twig in one
phase and a link in the other.
Figures A.3ef show the phase networks if equalizing switches are added for both phase
1 and phase 2. In this case, the two networks have excessive links. As the dual of the ﬁrst
problem, capacitor currents are not constrained by the topology since the KCL equations
are underconstrained. Instead, the capacitor currents are set in terms of the capacitor
values with a few constraints from the KCL equations. The fundamental loop matrix is
no longer square, resulting in overconstrained KVL equations. Since the KCL equation is
underconstrained and the KVL equation is overconstrained, this converter is not properly
posed.
Next, a converter will be presented that is not properlyposed. Figure A.4 shows a con
verter which is a 1:3 seriesparallel converter in parallel with a 1:2 seriesparallel converter.
The conversion ratio of this converter is undeﬁned, as currents ﬂow in the converter while
unloaded. While it is clear by inspection that there is no steadystate zerocurrent solution
to this converter, a look at the criteria deﬁned in this section is useful.
First, as C3 is never a twig in either of the two phase trees, it is evident that there are too
178
+ +
V
I N
V
O U T
C 1 C 2 C 3
φ 1 φ 1 φ 1
φ 1 1 1
φ 2
φ 2
φ 2
φ 2
φ 2
(a) Topology
+ +
V
I N
C 1 C 2 C 3 V
O U T
+ +
V
I N
V
O U T
C 1
C 2
C 3
(b) Phase 1 capacitor conﬁguration (c) Phase 2 capacitor conﬁguration
Figure A.4. An improperlyposed switchedcapacitor converter
179
many links in the phase trees. This suggests the KVL equations may be overconstrained.
First, the fundamental loop equations will be written for both phases, and the equivalent
of (A.10) will be formed:
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
−1 1 0 0 0
−1 0 1 0 0
−1 0 0 1 0
0 −1 −1 1 0
−1 −1 −1 0 1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
V
IN
v
c1
v
c2
v
c3
V
OUT
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
= 0 (A.30)
where the ﬁrst three rows correspond to phase 1, setting all the capacitor voltages equal
to the input voltage. The last two rows correspond to phase 2. By inspection, since row
4 equates the voltage on capacitor C3 to the sum of the voltage on C1 and C2, no general
solution exists. In fact, as this matrix B has rank 5, it is invertible, and thus no degrees
of freedom in the solution exists. The only solution to (A.30) corresponds to all voltages
equalling zero. These observations independently show that this converter is not properly
posed.
Using the methods in this section, a systematic method of determining whether an SC
converter is properlyposed, and thus suitable for analysis, has been developed.
A.4 Converter Dynamics
This section develops an exact model of the dynamics of an SC converter using the
circuittheory based analysis method developed in section A.2. In each clock period, the
converter forms an RC network based on the circuit’s capacitors and onstate switches,
modeled as resistances. The voltage on each capacitor approaches a steadystate value
during each phase. In the next phase, another RC network is formed with its own dynamics.
Thus, an SC converter can be modeled as a continuoustime, timedependent linear system,
as can other switchedmode converters. If the system is integrated through a switching
period, an alternate discretetime linear system can be constructed where the sample time
180
corresponds to the period of the converter. The continuoustime and discretetime linear
systems will be found in terms of the fundamental network theory parameters found in
section A.2.
A.4.1 Preparing the System
In this section, the complete dynamics of a converter will be considered. In particular,
the ideal voltage source at the output port will be replaced with a current source in parallel
with a capacitor. This replacement moreaccurately describes most converter implemen
tations and allows for the simulation of output voltage dynamics. In a properlyposed
converter, this capacitor will be a link in one phase and a twig in another, like the original
voltagesource load. The current source load is a link in both phases. The current through
the output capacitor ∆Q
COUT,2
is equal to half the ripple current at the output, denoted
∆Q
OUT,2
−∆Q
OUT,1
in (A.17). The output capacitor voltage is added to the voltage vec
tor, replacing the output voltage component. The state voltage vector v will be deﬁned as
follows:
v
C
=
_
¸
¸
¸
¸
¸
¸
¸
_
v
c1
v
c2
v
c3
v
cout
_
¸
¸
¸
¸
¸
¸
¸
_
(A.31)
where the output voltage of the converter is equal to the fourth element of this vector.
Since the fundamental loop matrix B is used in determining system dynamics in each
phase, its separate phase components B
1
and B
2
from (A.9) will be used. For consistency,
the rows of B
j
must be ordered according to the link used for each fundamental loop. For
example, in phase 1 of the 3:1 ladder converter, the fundamental loop of C1 should be
the ﬁrst row of B
1
, followed by the fundamental loop of C2. Each of the fundamental loop
matrices B
j
can be subdivided into two components. The ﬁrst matrix B
j
c
corresponds to the
capacitor elements and vector b
j
IN
corresponds to the input source. The properlyordered
181
and segmented fundamental loop matrices for the 3:1 converter are as follows:
B
1
=
_
¸
_
−1 1 0 1 1
0 0 1 −1 0
_
¸
_, B
2
=
_
¸
_
0 −1 0 1 0
0 0 −1 0 1
_
¸
_. (A.32)
The switch fundamental cutset matrices Q
j
RC
will be simpliﬁed by eliminating the
columns of zeros which correspond to twig capacitors. These reduced switch cutset matrices
will be denoted Q
j
RCx
to distinguish them from the full matrices. The reduced switch cut
set matrices for the 3:1 ladder converter example are given as follows:
Q
1
RCx
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
1 0
0 0
−1 1
0 0
0 −1
0 0
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
, Q
2
RCx
=
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
0 0
−1 0
0 0
1 −1
0 0
0 1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
(A.33)
Next, a vector q
OUT
will represent the connection of the output current source, which
has a 1 in the last position and zeros elsewhere:
q
OUT
=
_
0 0 0 1
_
. (A.34)
Finally, diagonal matrices R and C will be deﬁned containing switch onstate resistance
and capacitor values, respectively.
A.4.2 SinglePhase Dynamics
The next step is to calculate the dynamics of a single phase network of an SC converter.
Section A.4.1 deﬁned the relevant singlephase network matrices used in this section. For
simplicity of the explanation, the speciﬁc phase superscripts are omitted in this section with
the understanding that the appropriate superscripts are used for each phase’s dynamics.
The converter dynamics are determined by calculating the state vector v given the system
state and output current.
182
First, the resistive drops of the onstate switches must be determined. If the current
through the links is given by i
L
, the currents through the onstate switches can be found
using (A.26):
i
r
= Q
RCx
i
L
. (A.35)
Equation (A.35) can then be multiplied by R to determine the resistive voltage drops,
denoted v
r
, across the switches.
The fundamental loop matrix B determines the voltage around each fundamental loop
in the circuit. Since B only accounts for the input source and capacitor voltages, the error
in the KVL equation in A.11 is equal to the switchrelated voltage drops in the circuit. The
switchrelated voltage drops around each fundamental loop in the phase network can be
found in terms of the resistive voltage drops v
r
. Since the columns of Q
RCx
represent the
presence and orientation of each switch in each fundamental loop, it can be used to ﬁnd the
switchbased resistive voltage drop around each fundamental loop:
v
r
, loop = Q
RCx
v
r
. (A.36)
This loop voltage can be equated to the loop resistive drops by:
B v = b
IN
V
IN
+B
C
v
C
= −Q
RCx
RQ
RCx
i
L
. (A.37)
The link currents can be found directly in terms of the capacitor state and input voltage
by solving (A.37) for i
L
:
i
L
= −
_
Q
RCx
RQ
RCx
_
−1
(B
C
v
C
+b
IN
V
IN
) . (A.38)
The circuit currents can be found by multiplying the link currents by the transpose of
the fundamental loop matrix B. As the currents in the links represent the currents in each
fundamental loop, the transpose of B is used to ﬁnd the currents in all capacitors. Since
the output current and the output capacitor current are lumped in the last parameter of
the state vector, the output voltage must be subtracted from the currents to obtain the
capacitor currents as follows:
i
C
= −B
C
_
Q
RCx
RQ
RCx
_
−1
(B
C
v
C
+b
IN
V
IN
) −q
OUT
I
OUT
. (A.39)
183
Similarly, the input current is found by using the component b
IN
from (A.11):
i
IN
= −b
IN
_
Q
RCx
RQ
RCx
_
−1
(B
C
v
C
+b
IN
V
IN
) . (A.40)
Finally, since the capacitor currents are known, the derivative of the capacitor voltages can
be obtained by simply multiplying by the inverse of the capacitance matrix:
˙ v
C
= −C
−1
_
B
C
_
Q
RCx
RQ
RCx
_
−1
(B
C
v
C
+b
IN
V
IN
) +q
OUT
I
OUT
_
. (A.41)
Now that the deﬁning diﬀerential equation for a single phase network of an SC converter
has been found, a standardform linear system will be created from (A.41). The continuous
time standardform linear system is given in the following form:
˙ v
C
= Av
C
+B
_
¸
_
V
IN
I
OUT
_
¸
_ (A.42)
_
¸
_
v
OUT
i
IN
_
¸
_ = Cv
C
+D
_
¸
_
V
IN
I
OUT
_
¸
_. (A.43)
From (A.39) and (A.40), the following values of A, B, C and D can be extracted:
A = −C
−1
B
C
_
Q
RCx
RQ
RCx
_
−1
B
C
(A.44)
B =
_
−C
−1
B
C
_
Q
RCx
RQ
RCx
_
−1
b
IN
−C
−1
q
OUT
_
(A.45)
C =
_
¸
_
q
OUT
−b
IN
_
Q
RCx
RQ
RCx
_
−1
B
C
_
¸
_ (A.46)
D =
_
¸
_
0 0
−b
IN
_
Q
RCx
RQ
RCx
_
−1
b
IN
0
_
¸
_ (A.47)
The previous six equations fully describe a linear system describing the dynamics of a
single converter clock phase. For any properlyposed twophase converter, the matrices A
1
,
A
2
, B
1
, B
2
, C
1
, C
2
, D
1
and D
2
can be formed from the fundamental matrices developed
184
in section A.2. For the 3:1 ladder converter example, the eight linear system matrices can
be found using the following resistor and capacitor matrices, optimized in chapter 3:
C =
_
¸
¸
¸
¸
¸
¸
¸
_
1
2
1
5
_
¸
¸
¸
¸
¸
¸
¸
_
· 10
−6
R =
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
.2
.2
.2
.2
.1
.1
_
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
¸
_
(A.48)
A
1
=
_
¸
¸
¸
¸
¸
¸
¸
_
−3.75 −2.5 −1.25 −3.75
−1.25 −2.5 1.25 −1.25
−1.25 2.5 −3.75 −1.25
−0.75 −0.5 −0.25 −0.75
_
¸
¸
¸
¸
¸
¸
¸
_
· 10
6
, A
2
=
_
¸
¸
¸
¸
¸
¸
¸
_
−3.75 −2.5 3.75 2.5
−1.25 −2.5 1.25 2.5
3.75 2.5 −3.75 −2.5
0.5 1 −0.5 −1
_
¸
¸
¸
¸
¸
¸
¸
_
· 10
6
(A.49)
B
1
=
_
¸
¸
¸
¸
¸
¸
¸
_
3.75 0
1.25 0
1.25 0
0.75 −0.2
_
¸
¸
¸
¸
¸
¸
¸
_
· 10
6
, B
2
=
_
¸
¸
¸
¸
¸
¸
¸
_
0 0
0 0
0 0
0 −0.2
_
¸
¸
¸
¸
¸
¸
¸
_
· 10
6
(A.50)
C
1
=
_
¸
_
0 0 0 1
3.75 2.5 1.25 3.75
_
¸
_, C
2
=
_
¸
_
0 0 0 1
0 0 0 0
_
¸
_ (A.51)
D
1
=
_
¸
_
0 0
−3.75 0
_
¸
_, D
2
= 0 (A.52)
These system parameters can be used to perform a continuoustime simulation of the
SC converter using MATLAB’s ode23 or similar ODE solver. While this ODE representa
tion and a SPICE simulation yield identical results, the dimension of the ODE problem is
signiﬁcantly reduced.
185
A.4.3 DiscreteTime Model
The timedependent continuoustime linear model for a SC converter, as developed
in section A.4.2, is useful for simulating an SC converter. However, for use in converter
controllers, a discretetime model may be more appropriate. The sample time for this
discretetime model is a single switching period, incorporating all n clock phases in sequence.
For purpose of illustration, this analysis will be performed for a singleinput, single
output twophase converter, although it can be extended for a multiphase converter. A
switching period of T is assumed, where each of the two clock phases takes up precisely
half of this switching period. The system will be sampled at the instant of time before the
phase 2 to phase 1 transition. The capacitor voltage vector at this time is denoted v
C
[k]
at sample k. The input voltage and output current of the converter will be considered
constant during each switching period, and denoted as V
IN
[k] and I
OUT
[k], respectively, for
the duration between sample k and sample k + 1. Similarly, the output voltage at sample
k will be denoted V
OUT
[k]. In the discretetime system, the input current will be excluded
from the system output vector for simplicity.
Let the system state at time kT be v
C
[k]. To ﬁnd v
C
[k + 1], the system must be
integrated from time kT to time (k + 1)T. First, the system will be integrated using the
phase 1 system parameters to time (k + 1/2)T. This integration is given by [10] by:
v
C
((k + 1/2)T) = e
A
1
T/2
v
C
(kT) +
_
T/2
0
e
A
1
(T/2−τ)
B
1
u(τ)dτ (A.53)
where u(t) is the input vector comprising of the input voltage and output current. While
(A.53) looks like the solution to a singlevariable state integration, it utilizes the matrix
exponential, given by the Taylor expansion:
e
A
= I +
1
1!
A+
1
2!
AA+
1
3!
AAA+· · · . (A.54)
Since u(t) = u[k] from t = kT to t = (k + 1)T, (A.53) can be simpliﬁed as follows:
v
C
((k + 1/2)T) = e
A
1
T/2
v
C
(kT) +
_
T/2
0
e
A
1
τ
dτ B
1
u[k]. (A.55)
186
Similarly, if the state v
C
((k +1/2)T) is known, the state at time (k +1)T can be found as
follows:
v
C
((k + 1)T) = e
A
2
T/2
v
C
((k + 1/2)T) +
_
T/2
0
e
A
2
τ
dτ B
2
u[k]. (A.56)
Now, (A.55) and (A.56) can be combined to ﬁnd the state sample k + 1 from the state at
sample k:
v
C
[k + 1] = e
A
2 T
2
e
A
1 T
2
v
C
[k] +e
A
2 T
2
_
T/2
0
e
A
1
τ
dτ B
1
u[k] +
_
T/2
0
e
A
2
τ
dτ B
2
u[k]. (A.57)
This deﬁnite integral of the matrix exponential above is given by:
_
T/2
0
e
Aτ
dτ =
T
2
+
1
2!
A
_
T
2
_
2
+
1
3!
A
2
_
T
2
_
3
· · · . (A.58)
Since A is not necessarily invertible, (A.58) does not necessarily have a closed form.
While (A.57) describes the system, it is useful to put the system in the standard state
space form for a discretetime linear system. The standard form of a discretetime system
is given by:
v
C
[k + 1] = A
D
v
C
[k] +B
D
_
¸
_
V
IN
[k]
I
OUT
[k]
_
¸
_ (A.59)
where the output of the system is given by:
V
OUT
[k] = q
OUT
v
C
[k]. (A.60)
The discretetime linear system model parameters A
D
and B
D
can be extracted from (A.57)
in terms of the continuoustime system parameters:
A
D
= e
A
2 T
2
e
A
1 T
2
(A.61)
B
D
= e
A
2 T
2
_
T/2
0
e
A
1
τ
dτ B
1
+
_
T/2
0
e
A
2
τ
dτ B
2
. (A.62)
The continuoustime system parameters for the 3:1 ladder converter example found
in section A.4.2 can be used to ﬁnd the discretetime linear system parameters. In this
187
example, a switching frequency of 1 MHz is used such that T = 10
−6
. The discretetime
system parameters for the ladder converter are given approximately as follows:
A
D
=
_
¸
¸
¸
¸
¸
¸
¸
_
0.1276 −0.0912 −0.0030 −0.2889
−0.2023 0.2949 0.1332 0.3628
0.0519 0.1562 0.1176 −0.5316
−0.1242 0.0229 0.0011 0.6498
_
¸
¸
¸
¸
¸
¸
¸
_
(A.63)
B
D
=
_
¸
¸
¸
¸
¸
¸
¸
_
0.4185 0.0020
0.1375 −0.0725
0.4020 0.0564
0.1501 −0.1564
_
¸
¸
¸
¸
¸
¸
¸
_
(A.64)
The output voltage is simply the last element of the state vector.
The discretetime linear system found in this section can be used to implement a state
space controller for an SC converter. In addition, once the discretetime parameters are
found, the system can be simulated with very little processor eﬀort.
A.4.4 Dynamics Simulation
The 3:1 ladder converter, shown in ﬁgure A.2, is simulated using both the continuous
time timedependent linear system model, developed in section A.4.2, and the discretetime
timeindependent linear system model, developed in section A.4.3. The startup transient of
the converter is simulated where the input voltage is a constant 3 volts, the output current
a constant 300 mA and each capacitor is initially discharged. A switching frequency of 1
MHz is used.
Figure A.5 plots the four capacitor voltages (where the output capacitor is labeled)
using both the continuoustime and discretetime models. In addition, the results of a
SPICE simulation of the ideal converter is overlaid using gray lines. The discretetime model
results are shown as dots for each switching period, matching exactly with the continuous
time model (shown with solid lines). The calculated model matches well with the SPICE
188
0 1 2 3 4 5 6 7 8 9 1 0
0
0 . 5
1
1 . 5
2
2 . 5
T i m e [ µ s ]
C
a
p
a
c
i
t
o
r
V
o
l
t
a
g
e
s
[
V
]
O u t p u t V o l t a g e
C 1
C 3
C 2
S P I C E
C o n t i n u o u s − t i m e M o d e l
Figure A.5. Simulation of the dynamics of 3:1 ladder converter
simulation; the only diﬀerence stems from the diﬀerence in initial conditions between the
two simulations.
The circuittheory based dynamic model for SC converter is straightforward to develop
from the fundamental matrices describing an SC converter. The linear models can be used to
replace SPICE for circuit simulations of ideal SC converters and to create highperformance
controllers.
189
Appendix B
MATLAB Package for
SwitchedCapacitor Converter
Design
Chapters 2, 3 and 4 develop a thorough design methodology for switchedcapacitor (SC)
DCDC converters. Designing an SC converter by these methods involve ﬁrst choosing the
correct topology and ﬁnding its charge multipliers and matching components with device
technologies. Each capacitor and switch is then sized relative to the other capacitors and
switches, respectively. Finally, the total switch area, switching frequency and capacitor area
must be chosen to optimize performance. Automating this manystep process is strongly
desirable in order to speed up the design process. Additionally, computerbased visualization
is an important part of the design process as seen in chapters 3 and 8. This appendix
describes (and gives source listings for) a set of MATLAB programs that automate the design
and optimization of an SC converter. This package has been used to generate many of the
contour and regulation eﬃciency plots in this work. The ﬁrst section describes the functions
which form the backbone of the analysis, including functions to formulate topologies, assign
device technologies to speciﬁc components in the technologies, and evaluate the loss for
190
an implemented topology for speciﬁc operating conditions. The second section discusses
functions which perform certain analyses on SC topologies. The third section includes
functions which are utilitarian in nature and used with other functions, followed by a section
describing how to use the package for a practical example. Finally, source listings of all the
functions are given.
1
B.1 Core Functions
The three functions in this section, generate topology, implement topology and
evaluate loss, form the core of the design package. These functions respectively specify
the idealized topology structure, assign and size devices for each component, and evaluate
the loss of the converter at a certain operating point.
The ﬁrst function, generate topology, takes a string descriptor of a topology type
(given in section 4.2) and a conversion ratio, and creates a topology data structure specifying
the properties of the topology. The charge multipliers and blocking voltages are generated
based on the formulas in section 4.2. The function is given by:
topology = generate_topology (topology_name, num [, denom])
topology name a quoted name of the SC topology (i.e. ’SeriesParallel’, ’Ladder’)
num a decimal version of the stepup ratio of the converter. Must be a
rational number
denom nominal output voltage of the converter. If this parameter is included,
num must be an integer, and the conversion ratio is equal to num/denom.
topology returns a structure containing the charge multipliers and voltages of
the individual components in the converter
The output structure, topology, has the following members:
1
The source code is provided digitally at http://www.mikeseeman.com/thesis.
191
topName a quoted name of the SC topology (i.e. ’SeriesParallel’, ’Ladder’), as
provided by generate topology
ac a row vector containing the charge multiplier for each capacitor (not
including the output source)
vc a row vector containing the nominal blocking voltages for each capacitor
vcb a row vector containing the nominal amplitude of the voltage ripple on
the bottom plate parasitic of each capacitor
ar a row vector containing the charge multiplier for each switch
vr a row vector containing the nominal blocking voltage of each switch
vrb a row vector containing the nominal amplitude of the voltage ripple on
the sourcesubstrate capacitance of each switch
Mssl the idealized slowswitchinglimit converter metric, given in (4.5)
Mfsl the idealized fastswitchinglimit converter metric, given in (4.6)
ratio the nominal conversion ratio of the converter (greater than one for a
stepup converter)
This topology structure is fed into the function implement topology to choose and
size devices to implement each component in the topology. The function is used as follows:
implementation = implement_topology (topology, Vin, switchTechs, capTechs,
compMetric)
topology topology structure, generated from generate topology
Vin maximum input voltage of converter, used for component voltage com
patibility
switchTechs a row vector of switch technology structures that are available for com
ponent implementation. A description of this structure follows.
capTechs a row vector of capacitor technology structures that are available for
component implementation. A description of this structure follows.
192
compMetric an integer specifying which metric to use when selecting switch tech
nologies. 1 (default) speciﬁes the areabased metric, while 2 selects the
parasiticlossbased metric.
implementation returns a structure containing the technology structures for the selected
devices, plus the relative sizing of each device.
The implementation structure returned by implement topology contains the following
members:
topology the structure generated by generate topology, passed to
implement topology
capacitors a row vector containing the capacitor technology structure for each
capacitor in the converter
switches a row vector containing the switch technology structure for each switch
in the converter
cap size a row vector containing the relative sizes of each capacitor in the con
verter. If this vector was multiplied by the size of each technology
dependent unit cell, the total capacitor area would equal one square
meter.
switch size a row vector containing the relative sizes of each switch in the converter.
If this vector was multiplied by the size of each technologydependent
unit cell, the total switch area would equal one square meter.
The technology structures are contained in a library ﬁle, and executed before running
implement topology. The techlib.m ﬁle includes the structures for the ITRSbased ide
alized devices discussed in section 8.1. Each structure is devoted to a single device in a
speciﬁc technology. Any number of these structures can be applied to implement topology
to choose for implementing a topology. Each structure contains data on an arbitrarilysized
representative unit cell. The capacitor structure has the following members:
tech name a string describing the process technology (i.e. ITRS 90nm)
193
dev name a string describing the particular device (i.e. Thinoxide PMOS oxide
capacitor)
capacitance The capacitance (in F) of the unit cell device
area The die area, increased by any density rules, of the unit cell device (in
m
2
)
bottom cap The bottomplate parasitic capacitance of the unit cell device (in F)
esr The equivalent series resistance (ESR) of the unit cell device (in ohms)
rating The maximum blocking voltage of the capacitor (in V)
Similarly, the switch technology structure has the following elements:
tech name a string describing the process technology (i.e. ITRS 90nm)
dev name a string describing the particular device (i.e. Native 90nm NMOS tran
sistor)
area The die area of the unitcell switch, accounting for density rules (in
m
2
)
conductance The conductance of the unitcell switch, at very low V
DS
and full V
GS
(in S)
gate rating The nominal gate drive voltage of the switch (at which the conductance
was measured) (in V)
drain rating The maximum blocking voltage of the device (in V)
gate cap The average gate capacitance of the unit cell at the rated gate voltage
(in F)
drain cap The average drain capacitance of the unit cell at the nominal blocking
voltage (in F)
body cap The linearized sourcesubstrate capacitance of the unit cell at an aver
age sourcesubstrate voltage (in F)
To evaluate the loss of an implemented converter, a ﬂexible approach must be taken.
194
When investigating the design space with a contour plot, as in section 3.3.2, the output
voltage is not constrained (it is a dependent or endogenous variable). However, when
regulation is considered, the switching frequency is instead unconstrained. The function
evaluate loss takes all system parameters as an input; unspeciﬁed ones should be passed
as an empty array ([]). All inputs, except for the implementation structure, can be either a
scalar, row vector, column vector or matrix. Each is internally expanded into a matrix with
a twodimensional parameter space, according to the inputs. At each point, the unspeciﬁed
(endogenous) variables are found and the converter loss is found.
performance = evaluate_loss (imp, Vin, Vout, Iout, fsw, Asw, Ac)
imp implementation structure for a single topology, generated from
implement topology
Vin input voltage to the converter (in V)
Vout converter output voltage (in V), set to [] for unregulated converters
Iout output current (in A)
fsw converter switching frequency (in Hz), set to [] for regulated converters
Asw switch die area (in m
2
)
Ac capacitor die area (in m
2
)
evaluate loss returns a single data structure denoted performance. Each of the fol
lowing members is a matrix the size of the input parameter range. Each matrix element is
the result of evaluating the converter at the speciﬁc operating condition.
Vout the actual average output voltage of the converter. If Vout is speciﬁed,
it is not changed.
fsw the actual switching frequency of the converter. If fsw is speciﬁed, it is
not changed.
195
is possible a matrix where each element is 0 or 1. 1 indicates that the output
voltage can be produced for a ﬁnite switching frequency; 0 indicates
that no solution exists for the input conditions. When output voltage
is unconstrained, as in the unregulated case, is possible is always 1.
efficiency numerical eﬃciency of the converter, does not exceed 1
total loss the total power dissipated in the converter (in W)
impedance total outputreferred impedance (in ohms)
dominant loss a code indicating the dominant loss component at the current design
point
dominant text a string referring to the dominant loss component at the current design
point
These three functions perform the backbone of the analysis functions in the next section.
The code listings for the previous sections are in section B.5
B.2 Visualization Functions
Two functions are included in the package which use the functions in section B.1
to create plots which aid in the development of SC converters. The ﬁrst function,
plot opt contour, plots an eﬃciency contour plot over a twodimensional space of switch
ing frequency and switch area for a given input voltage and output current. The second
function, plot regulation plots the eﬃciency of one or more SC converter topologies as
either the input or output voltage is swept across a range while the other is held constant.
Regulation is performed by varying switching frequency.
plot_opt_contour (topology, ratio, Vin, Iout, Ac, switches, capacitors,
[esr, [optMethod, [pointPlots, [plotAxes]]]])
196
topology A string naming the SC topology used (i.e. ’Ladder’) or a topology or
implementation structure
ratio A rational conversion ratio for the topology named in topology. This
parameter is ignored if topology is a structure
Vin The scalar input voltage for the converter (in V)
Iout The scalar output current of the converter (in A)
Ac The scalar total die area used for the capacitors (in m
2
)
switches A row vector of switch technology structures; see implement topology.
When an implementation structure is passed into topology, this value
can be [].
capacitors A row vector of capacitor technology structures; see
implement topology
esr Additional metalrelated series resistance to add to the analysis (default
= 0 ohms)
optMethod an integer specifying which metric to use when selecting switch tech
nologies. 1 (default) speciﬁes the areabased metric, while 2 selects the
parasiticlossbased metric.
plotPoints an integer specifying the number of plots in each dimension to evaluate
the loss to create the contour plot. A larger number results in smoother
contours (default: 100)
plotAxes A fourelement row vector specifying the desired plot axes (calcu
lated automatically by default). It is in the form [log
10
(f
sw,min
),
log
10
(f
sw,max
), log
10
(A
SW,min
), log
10
(A
SW,max
)], where switching fre
quency is in Hz and switch area in m
2
.
An example using plot opt contour and plot regulation is given in section B.4.
Function plot regulation is given by:
plot_regulation (topologies, Vin, Vout, Iout, Ac, switches, capacitors,
197
[esr, [idesign]])
topologies A column vector of topologies to be evaluated over regulation. Each el
ement can either be a twoelement row vector in the form [{’Topology’}
{ratio}], a topology structure or implementation structure.
Vin Input voltage, either a scalar or vector (in V)
Vout Output voltage, either a scalar or vector (in V)
Iout Output current, either as a scalar for constant output currents, or as a
vector if the load current varies with either load or line voltage (in A)
Ac The scalar total die area used for the capacitors (in m
2
)
switches A row vector of switch technology structures; see implement topology
capacitors A row vector of capacitor technology structures; see
implement topology
esr Additional metalrelated series resistance to add to the analysis (default
= 0 ohms)
idesign A row vector (each element corresponding to a topology) or scalar
specifying the current for which each topology should be optimized for
(in A). If omitted, idesign is chosen automatically by interpolating the
output current at the nominal conversion ratio.
plot regulation plots the eﬃciency of a number of topologies over a range of either
input or output voltages. Either the input or output voltage should be speciﬁed as a
vector of sample points; this is used as the xaxis for the plot. The ratios according to
each converter are noted next to the optimal point of each converter. The sizing of each
topology is optimized independently for the nominal operating point. This optimization
may not ideally represent an actual converter.
198
B.3 Helper Functions
Two helper functions are included to perform utilitarian tasks. Function optimize loss
is used by plot opt contour and plot regulation for ﬁnding the mosteﬃcient operating
point for a given input voltage and output current. Function permute topologies combines
sets of topologies in cascade to form new hybrid topologies for use with the other functions.
These functions are described as follows.
[performance, fsw, Asw] = optimize_loss (implementation, Vin, Iout, Ac)
implementation an implementation structure created by implement topology or simi
lar method
Vin the scalar input voltage for the optimization (in V)
Iout the scalar output current for optimization (in A)
Ac the scalar capacitor die area (in m
2
)
performance the performance structure, as returned by evaluate loss, at the op
timal point
fsw the optimal switching frequency (in Hz)
Asw the optimal switch die area (in m
2
)
newtops = permute_topologies (topologies1, topologies2)
topologies1 A column vector of m [{’Topology’} {ratio}] pairs or topology struc
tures, each representing a topology that can be used in the ﬁrst position
(attached to the input source)
topologies2 A column vector of n [{’Topology’} {ratio}] pairs or topology struc
tures, each representing a topology that can be used in the second
position (attached to the output of the ﬁrst topology and supplies the
output source)
199
newtops A column vector of length m · n containing topology structures, all
combinations of the ﬁrst topologies and second topologies are included
Function permute topologies cascades two converters, each of which can be a variable
ratio converter, into a larger variableratio converter, such as the converter in section
5.4, representing all of the possible combinations. The resulting vector can be used with
plot regulation to obtain a regulation curve for the variableratio converter.
B.4 Example
The twostage variableratio SC converter discussed in section 5.4 will be used to demon
strate the abilities of this package. Before any of the following code is run, the script con
taining the technology structures (techlib.m) should be run to load these structures into
memory. This example will use the 65 nm process example from the ITRS roadmap. First,
the vectors with the ﬁrst and second stage topologies will be deﬁned:
topologies1 = [ generate_topology(’Ladder’, 8, 7);
generate_topology(’Ladder’, 7, 7);
generate_topology(’Ladder’, 6, 7);
generate_topology(’Ladder’, 5, 7) ];
topologies2 = [ {’Dickson’} {1/3};
{’Dickson’} {1/2} ];
Note the two methods of deﬁning the topology vectors; either works for the methods
in this section. It is important to note that the arrangement of capacitors in the ladder
topologies is not optimal for this application. Superior performance can be obtained by
creating topology structures with the charge multipliers and blocking voltages from the
optimized topologies.
Next, the two topology vectors will be cascaded and permuted:
cascaded_tops = permute_topologies (topologies1, topologies2);
200
As one of the switches in the Dickson converter must block twice the output voltage (of
1.2V), a cascode device will be created. It consists of two native NMOS devices in series,
used to block twice the voltage. Additionally, a highvoltage capacitor will be created
(usually, a thickoxide device would be used, in this case, a series device would be used
solely for analysis purposes).
itrs65cc = itrs65n; % copy topologies
itrs65cc.area = itrs65n.area * 2;
itrs65cc.conductance = itrs65n.conductance / 2;
itrs65cc.drain_rating = itrs65n.drain_rating * 2;
itrs65cc.drain_cap = itrs65n.drain_cap * 2 + itrs65n.gate_cap;
thickcap = itrs65cap;
thickcap.capacitance = itrs65cap.capacitance / 2;
thickcap.area = itrs65cap.area * 2;
thickcap.rating = itrs65cap.rating * 2;
Using these new devices, the regulation eﬃciency plot can be created. The input voltage
is swept from 2 V to 5 V at an output current of 100 mA and a capacitor die area of 10 mm
2
.
Again, it is important to note that the arrangement of capacitors in the ladder topologies is
not optimal for this application. Superior performance can be obtained by creating topology
structures with the charge multipliers and blocking voltages from the optimized topologies.
The result from plot regulation is shown in ﬁgure B.1a.
Vin = 2:.01:5;
plot_regulation (cascaded_tops, Vin, 1.2, 0.1, 10e6, ...
[itrs65n itrs65cc], [itrs65cap thickcap]);
Next, the design point of the 16:7 conﬁguration will be examined. First, this topology
structure will be created:
topology = permute_topologies( [generate_topology(’Ladder’, 7, 8)], ...
[generate_topology(’Dickson’, 1/2)]));
Next, the contour plot will be created using the same modiﬁed devices as shown above.
An input voltage of 3.35 V will be used, as it is close to the optimal point on the pre
vious plot. The optional axis parameter is used to bettercenter the plot. The results of
plot opt contour are shown in ﬁgure B.1b.
201
2 2 . 5 3 3 . 5 4 4 . 5 5
3 0
4 0
5 0
6 0
7 0
8 0
9 0
1 0 0
I n p u t V o l t a g e [ V ]
2 4 : 7
1 6 : 7
3 : 1
2 : 1
1 8 : 7
1 2 : 7
1 5 : 7
1 0 : 7
E
f
f
i
c
i
e
n
c
y
[
%
]
(a) plot regulation
10
7
10
8
10
9
10
10
10
−3
10
−2
10
−1
10
0
Switching Frequency [Hz]
S
w
i
t
c
h
A
r
e
a
[
m
m
2
]
I
OUT
=0.1A, A
c
=10 mm
2
, Eff =67.3 %
0
.
0
5
0
.
0
5
0
.
0
5
0
.0
5
0.05
0.05
0
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1
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1
0.1
0
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4
(b) plot opt contour
Figure B.1. Example plots from the MATLAB package
202
plot_opt_contour (topology, 1, 3.35, 0.1, 10e6, [itrs65n itrs65cc], ...
[itrs65cap thickcap], 0, 1, 100, [7 10 9 6]);
This MATLAB package enables quick design and application space investigation using
SC converters. The eﬃciency of a converter can be estimated in very little time, and
the design can be rapidly iterated to achieve the best architecture for a given application.
However, as many approximations are used in the analysis, devicelevel circuit simulations
(e.g. SPICE) are necessary for a moreprecise estimate of eﬃciency.
203
B.5 Code Listings
The source code is provided digitally at http://www.mikeseeman.com/thesis.
B.5.1 evaluate loss.m
1 function performance = evaluate_loss (imp, Vin, Vout, Iout, fsw, Asw, Ac)
% evaluate_loss: evaluates the loss and other peformance metrics for a
% specific size and operating condition of a implemented SC converter
%
5 % imp: implementation generated from implement_topology
% Vin: converter input voltage for this calc [V]
% Vout: converter output voltage for this calc [V]
% Iout: converter output current for this calc [A]
% fsw: switching frequency [Hz]
10 % Asw: switch area [m^2]
% Ac: capacitor area [m^2]
%
% Either fsw (in case of regulation) or Vout (in case of openloop
% control) should be set to [] and will be found by this function.
15 %
% Created: 4/15/08, Last Modified: 4/15/09
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
20
% Break implementation into components for brevity
ac = imp.topology.ac;
vc = imp.topology.vc;
vcb = imp.topology.vcb;
25 ar = imp.topology.ar;
vr = imp.topology.vr;
vrb = imp.topology.vrb;
ratio = imp.topology.ratio;
30 caps = imp.capacitors;
cap_size = imp.cap_size;
switches = imp.switches;
sw_size = imp.switch_size;
35 % Process (and expand) input parameters
paramdim = max(size(Vin), max(size(Vout), max(size(Iout), max(size(fsw),...
max(size(Asw), size(Ac))))));
type = 0; % undefined: 0not yet set; 1vout; 2fsw
40 Vin = expand_input(Vin, paramdim);
if (size(Vout) == [0 0])
type = 1;
Vout = zeros(paramdim);
else
204
45 Vout = expand_input(Vout, paramdim);
end
Iout = expand_input(Iout, paramdim);
if (size(fsw) == [0 0])
if (type == 1)
50 error(’Both fsw and Vout cannot be undefined’);
else
type = 2;
fsw = zeros(paramdim);
end
55 else
fsw = expand_input(fsw, paramdim);
end
Asw = expand_input(Asw, paramdim);
Ac = expand_input(Ac, paramdim);
60
%%%%%%%%%%%%%%%%%%%%%%%%%% Start Analysis %%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Calculate SSL output resistance:
Rssl_alpha = 0;
65 for i=1:size(caps,2),
if (ac(i) > 0),
Rssl_alpha = Rssl_alpha + (ac(i)^2)/(caps(i).capacitance*cap_size(i));
end
end
70
% Calculate FSL output resistance:
Rfsl_alpha = 0;
for i=1:size(switches,2),
75 if (ar(i) > 0),
Rfsl_alpha = Rfsl_alpha + 2*(ar(i)^2)/...
(switches(i).conductance*sw_size(i));
end
end
80 Rfsl = Rfsl_alpha./Asw;
% Calculate additional ESR loss:
Resr_alpha = 0;
for i=1:size(caps,2),
85 if (isfield(caps(i),’esr’)),
if (ac(i) > 0),
Resr_alpha = Resr_alpha + 4*(ac(i)^2)*(caps(i).esr/cap_size(i));
end
end
90 end
Resr = Resr_alpha./Ac;
if (isfield(imp, ’esr’)),
Resr = Resr + imp.esr;
end
95
% Find the unknown (endogenous) variable
if (type == 1)
205
% Vout is unknown
Rssl = Rssl_alpha ./ (fsw.*Ac);
100
% Calculate total output resistance:
Rout = sqrt(Rssl.^2 + (Rfsl + Resr).^2);
Vout = Vin*ratio  Rout.*Iout;
Pout = Vout.*Iout;
105 is_prac = ones(paramdim);
elseif (type == 2)
% fsw is unknown
% Calculate needed output impedance and switching frequency to match
% output voltage
110 % is_prac is 1 if a finite fsw which satisfies Iout, Vin, Vout exists
Rreq = (Vin*ratio  Vout)./Iout;
is_prac = ((Rreq > 0) & (Rfsl+Resr < Rreq));
Rssl = real(sqrt(Rreq.^2  (Rfsl+Resr).^2));
115 fsw = Rssl_alpha ./ (Rssl .* Ac);
% Calculate total output resistance:
Rout = sqrt(Rssl.^2 + (Rfsl + Resr).^2);
Pout = Vout.*Iout;
120 else
error(’Either Vout or fsw must be []’);
end
% Calculate resistance losses:
125 Pssl = Rssl.*Iout.^2;
Pfsl = Rfsl.*Iout.^2;
Pesr = Resr.*Iout.^2;
Pres = Rout.*Iout.^2;
130 % Calculate Caprelated Parasitic loss:
Pc_alpha = 0;
for i=1:size(caps,2),
Pc_alpha = Pc_alpha + (caps(i).bottom_cap*cap_size(i)) * (vcb(i))^2;
135 end
Pc = Pc_alpha.*fsw.*Ac.*Vin.^2;
% Calculate Switchrelated Parasitic loss:
140 Psw_alpha = 0;
Pg_alpha = 0;
for i=1:size(switches,2),
% Assume switch is driven at full gate_rating voltage
Vgssw = switches(i).gate_rating;
145 Pg_alpha = Pg_alpha + (switches(i).gate_cap*sw_size(i)) * (Vgssw)^2;
Psw_alpha = Psw_alpha + ((switches(i).drain_cap*sw_size(i)) * (vr(i))^2 + ...
(switches(i).body_cap*sw_size(i)) * (vrb(i))^2);
end
Psw = (Psw_alpha.*Vin.^2 + Pg_alpha).*fsw.*Asw;
150
206
% Calculate total loss, efficiency, etc...
Ploss = Pres + Pc + Psw;
eff = Pout./(Pout+Ploss);
IND = [];
155 for i=1:size(Pssl,1),
[temp, ind] = max([Pssl(i,:); Pfsl(i,:); Pesr(i,:); Pc(i,:); Psw(i,:)]);
IND = [IND; ind];
end
%[temp, ind] = max([Pssl Pfsl Pc Psw]);
160 texts = [{’SSL Loss’} {’FSL Loss’} {’ESR Loss’} {’BottomPlate’}...
{’Switch Parasitic’}];
% create structure  list unknown system parameters
performance.Vout = Vout;
165 performance.fsw = fsw;
performance.is_possible = is_prac;
% list performance
performance.efficiency = eff;
170 performance.total_loss = Ploss;
performance.impedance = Rout;
performance.dominant_loss = IND;
performance.dominant_text = texts(IND);
175 % Subfunction that turns input into a (maxsize) matrix
function result = expand_input (input, maxsize)
if (size(input) == [1 1])
% scalar input
180 result = input * ones(maxsize);
elseif (size(input) == [1 maxsize(2)])
% row vector input
result = ones(maxsize(1),1) * input;
elseif (size(input) == [maxsize(1) 1])
185 % column vector input
result = input * ones(1, maxsize(2));
elseif (size(input) == maxsize)
% input already a properlysized matrix
result = input;
190 elseif (size(input) == [0 0])
error(’Only fsw or Vout can be empty’);
result = 0;
else
% input is not properly sized
195 error(’All inputs must have the same number of rows and columns (if not 1)’);
result = 0;
end
B.5.2 generate topology.m
1 function result = generate_topology (topology_name, num, den)
207
% generate_topology: Topology charge and voltage multiplier generation
%
% result = generate_topology (topology_name, num [, den])
5 % topology_name: Name of SC topology {Ladder, Dickson, CockcroftWalton,
% Doubler, SeriesParallel, Fibonacci}
% num, den: the ratio of output voltage to input voltage. If denom is
% omitted, num is a rational number. Otherwise, both are integers.
% num/den is the stepup conversion ratio of the converter.
10 %
% result: structure with charge multiplier and voltage vectors for
% capacitors and switches.
%
% Created 4/14/08, Last Modified 4/15/09
15 % Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
% if a straight ratio passed in, break it up into numerator and denominator
20 if nargin < 3,
[num, den] = rat(num, .001);
end
% generate ac’s for stepup only, at first, v’s in terms of input voltage
25 flip = 0;
if (num/den < 1),
t = den; den = num; num = t;
flip = 1; % indicate that the converter has been ’flipped’
end
30
%%%%%%%%%%%%%%%%%% SeriesParallel %%%%%%%%%%%%%%%%%%%%%%%%%%
if (strcmpi(topology_name,’SeriesParallel’)),
n = num;
m = den;
35 N = n;
% SSL values
ac = ones(1,m*(nm))/m;
vc = ones(1,m*(nm))/m;
vcb = [];
40 for i=1:m,
for j=1:(nm),
vcb = [vcb (i+j1)/m];
end
end
45 % FSL values
vr = [];
vrb = [];
for i = 1:m,
for j = 1:(nm+1),
50 if (j == 1),
vr = [vr i/m];
vrb = [vrb (i+j1)/m];
elseif (j == (nm+1)),
vr = [vr (nm1+i)/m];
208
55 vrb = [vrb (i+j2)/m];
else
vr = [vr 1/m];
vrb = [vrb (i+j1)/m];
end
60 end
end
for i=1:m+1,
for j=1:nm,
if (i==1),
65 vr = [vr j/m];
elseif (i==(m+1)),
vr = [vr (m1+j)/m];
else
vr = [vr 1/m];
70 end
if ((i==1)  (i==(m+1))),
vrb = [vrb 0];
else
vrb = [vrb (i+j2)/m];
75 end
end
end
ar = ones(size(vr))/m;
80 %%%%%%%%%%%%%%%%%% Ladder %%%%%%%%%%%%%%%%%%%%%%%%%%
elseif (strcmpi(topology_name,’Ladder’)),
n = num;
m = den;
N = n;
85 % SSL values
ac = [];
vc = [];
vcb = [];
90 for j=1:(nm1),
ac = [ac j j];
vc = [vc 1/m 1/m];
vcb = [vcb 1/m 0];
end
95 ac = [ac (nm)];
vc = [vc 1/m];
vcb = [vcb 1/m];
for j=(m1):1:1,
ac = [ac ones(1,2)*(j*(n/m1))];
100 vc = [vc 1/m 1/m];
vcb = [vcb 1/m 0];
end
% FSL values
105 ar = [ones(1,2*(nm)) (n/m1)*ones(1,2*m)];
vr = ones(1,2*n)/m;
vrb = mod(0:(2*n1),2)/m;
209
%%%%%%%%%%%%%%%%%% Dickson %%%%%%%%%%%%%%%%%%%%%%%%%%
110 elseif (strcmpi(topology_name,’Dickson’)),
if (den ~= 1)
error(’SWITCHCAP:nonIntegerRatio’,...
’the Dickson topology supports integer ratios only’);
end
115 N = num;
% SSL values
ac = ones(1,N1);
vc = [];
vcb = ones(1,N1);
120 for j=1:(N1),
vc = [vc j];
end
% FSL values
if (N == 2),
125 vr = ones(1,4);
ar = ones(1,4);
vrb = [0 1 0 1];
else,
vr = [ones(1,5) 2*ones(1,N2), 1];
130 ar = [floor((j+1)/2)*[1 1] floor((j)/2)*[1 1] ones(1,N)];
vrb = [0 1 0 1 ones(1,N)];
end
%%%%%%%%%%%%%%%%%% CockcroftWalton %%%%%%%%%%%%%%%%%%%%%%%%%%
135 elseif (strcmpi(topology_name, ’CockcroftWalton’)),
if (den ~= 1)
error(’SWITCHCAP:nonIntegerRatio’,...
’the CockcroftWalton topology supports integer ratios only’);
end
140 N = num;
% SSL values
ac = [];
vc = [1 2*ones(1,N2)];
vcb = ones(1,N1);
145 for j=1:(N1),
ac = [floor((j+1)/2) ac];
end
% FSL values
if (N == 2),
150 vr = ones(1,4);
ar = ones(1,4);
vrb = [0 1 0 1];
else,
vr = [ones(1,5) 2*ones(1,N2) 1];
155 ar = [floor((j+1)/2)*[1 1] floor((j)/2)*[1 1] ones(1,N)];
vrb = [0 1 0 1 ones(1,N)];
end
%%%%%%%%%%%%%%%%%% Doubler %%%%%%%%%%%%%%%%%%%%%%%%%%
160 elseif (strcmpi(topology_name,’Doubler’)),
210
if (den ~= 1)
error(’SWITCHCAP:nonIntegerRatio’,...
’the Doubler topology supports integer ratios only’);
end
165 n = ceil(log2(num));
N = 2^n;
if (N ~= num),
error(’SWITCHCAP:badRatio’,...
’the doubler topology supports conversion ratios ~ 2^n’);
170 end
% SSL values
ac = [];
vc = [];
175 vcb = [];
for j=1:(2*n1),
ac = [2^floor((j1)/2) ac];
vc = [vc 2^floor(j/2)];
vcb = [vcb 2^floor(j/2)*mod(j,2)];
180 end
% FSL values
ar = [];
vr = [];
vrb = [];
185 for j=1:n,
ar = [ar ones(1,4)*2^(j1)];
vr = [vr ones(1,4)*2^(nj)];
vrb = [vrb [0 1 0 1]*2^(nj)];
end
190
%%%%%%%%%%%%%%%%%% Fibonacci %%%%%%%%%%%%%%%%%%%%%%%%%%
elseif (strcmpi(topology_name,’Fibonacci’)),
if (den ~= 1)
error(’SWITCHCAP:nonIntegerRatio’,...
195 ’the Fibonacci topology supports integer ratios only’);
end
i = 2;
while (fibfun(i) < num),
i = i+1;
200 end
if (fibfun(i) > num)
error(’SWITCHCAP:badRatio’,...
’the fibonacci topology supports ratios of F_n or 1/F_n only’);
end
205 N = fibfun(i);
% SSL Calculation
ac = [];
vc = [];
210 vcb = [];
for j = 2:i1,
ac = [fibfun(j1) ac];
vc = [vc fibfun(j)];
211
vcb = [vcb fibfun(j1)];
215 end
% FSL Calculation
ar = [1];
vr = [];
vrb = [0];
220 for j = 2:i1,
ar = [fibfun(j) fibfun(j1) fibfun(j1) ar];
vr = [vr fibfun(j) fibfun(j) fibfun(j1)];
vrb = [vrb fibfun(j1) 0 fibfun(j1)];
end
225 vr = [vr fibfun(i2)];
end
ratio = num/den;
230 % Compute ideal metrics
Mssl = 2*ratio^2/(ac*vc’)^2;
Mfsl = ratio^2/(2*(ar*vr’)^2);
if (flip == 1),
235 ac = ac/ratio;
vc = vc/ratio;
vcb = vcb/ratio;
ar = ar/ratio;
vr = vr/ratio;
240 vrb = vrb/ratio;
ratio = 1/ratio;
end
result.topName = topology_name;
245 result.ac = ac;
result.vc = vc;
result.vcb = vcb; % bottom plate voltage vector
result.ar = ar;
result.vr = vr;
250 result.vrb = vrb; % body swing voltage, for NMOS
result.Mssl = Mssl;
result.Mfsl = Mfsl;
result.ratio = ratio;
B.5.3 implement topology.m
1 function implementation = implement_topology(topology, Vin, switchTechs,...
capTechs, compMetric)
% implement_topology: matches components with switches and components in
% the topology.
5 % implementation = implement_topology(topology, Vin, switchTechs,
% capTechs, compMetric)
% topology: structure created by generate_topology
% Vin: input voltage of converter
212
% switchTechs: an array of technology structures available for switch use
10 % capTechs: an array of technology structures available for cap use
% compMetric: a metric (1=area, 2=loss) used for determining the best
% component (1=default)
% Created 4/15/08, Last Modified: 4/15/09
% Copyright 20082009, Mike Seeman, UC Berkeley
15 % May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
% Break out components of topology structure
ratio = topology.ratio;
20 ac = topology.ac;
ar = topology.ar;
vc = topology.vc*Vin;
vr = topology.vr*Vin;
vcb = topology.vcb*Vin;
25 vrb = topology.vrb*Vin;
if (nargin < 5)
compMetric=1;
end
30
switch_assign = [];
cap_assign = [];
switch_rel_size = [];
cap_rel_size = [];
35
% Assign Capacitors
for i=1:size(ac,2),
Mc = 0;
Cc = 0; % cap cost;
40 for j=1:size(capTechs,2),
if (vc(i) <= capTechs(j).rating),
% Cap could work ... let’s see if it’s good
% Use arealimited metric, which is usually applicable
C = capTechs(j).area;
45 M = capTechs(j).capacitance*vc(i)^2/C;
if (M > Mc)
if (Mc == 0),
cap_assign = [cap_assign capTechs(j)];
else
50 cap_assign(i) = capTechs(j);
end
Mc = M;
Cc = C;
end
55 end
end
% check to make sure a suitable device exists
if (Mc == 0),
error(strcat(’No capacitors meet the voltage requirement of: ’,...
60 num2str(vc(i))));
end
213
% determine relative device size
if (ac(i) == 0),
cap_rel_size = [cap_rel_size 0]; % avoid divide by 0
65 else
cap_rel_size = [cap_rel_size (ac(i)*vc(i))/...
(sqrt(Mc)*cap_assign(i).area)];
end
70 end
% Assign Switches
for i=1:size(ar,2),
75 Msw = 0;
Csw = 0; % switch cost;
for j=1:size(switchTechs,2),
if (vr(i) <= switchTechs(j).drain_rating),
% Switch could work ... let’s see if it’s good
80 if (compMetric == 2), % loss metric
% assume full gate drive
C = switchTechs(j).gate_cap*switchTechs(j).gate_rating^2 + ...
switchTechs(j).drain_cap*vr(i)^2 + ...
switchTechs(j).body_cap*vrb(i)^2;
85 M = switchTechs(j).conductance*vr(i)^2/C;
else % area metric
C = switchTechs(j).area;
M = switchTechs(j).conductance*vr(i)^2/C;
end
90 if (M > Msw)
if (Msw == 0),
switch_assign = [switch_assign switchTechs(j)];
else
switch_assign(i) = switchTechs(j);
95 end
Msw = M;
Csw = C;
end
end
100 end
% check to make sure a suitable device exists
if (Msw == 0),
error(strcat(’No switches meet the voltage requirement of: ’,...
num2str(vr(i))));
105 end
% determine relative device size
if (ar(i) == 0),
switch_rel_size = [switch_rel_size 0];
else
110 if (compMetric == 2),
switch_rel_size = [switch_rel_size (ar(i)*vr(i))/...
(sqrt(Msw)*switch_assign(i).conductance)];
else
switch_rel_size = [switch_rel_size (ar(i)*vr(i))/...
214
115 (sqrt(Msw)*switch_assign(i).area)];
end
end
end
120 % Scale Caps for unit area:
cap_area = 0;
for i=1:size(ac,2),
cap_area = cap_area + cap_rel_size(i)*cap_assign(i).area;
125 end
cap_size = cap_rel_size./(cap_area+1e30);
% Scale Switches for unit area:
130 sw_area = 0;
for i=1:size(ar,2),
sw_area = sw_area + switch_rel_size(i)*switch_assign(i).area;
end
switch_size = (switch_rel_size.*(sw_area > 0))./(sw_area+(sw_area == 0));
135
% Create implementation structure
implementation.topology = topology;
implementation.capacitors = cap_assign;
implementation.switches = switch_assign;
140 implementation.cap_size = cap_size;
implementation.switch_size = switch_size;
B.5.4 optimize loss.m
1 function [performance, fsw, Asw] = optimize_loss (implementation, Vin, ...
Iout, Ac)
% optimize_loss: Finds the optimal design point for given conditions
% Michael Seeman, UC Berkeley
5 %
% optimize_loss(implementation, Vout, Iout, Ac)
% implementation: implementation generated from implement_topology
% Vin: converter input voltage for this calc [V]
% Iout: converter output current for this calc [A]
10 % Ac: capacitor area [m^2]
%
% Returns: performance structure from evaluate_loss and optimal switching
% frequency and switch area
%
15 % Created 4/14/08, Last modified: 4/15/09
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
20 options = optimset(’fmincon’);
options = optimset(options, ’TolFun’, 1e11, ’MaxIter’, 400000, ...
215
’Display’, ’off’, ’LargeScale’, ’off’);
opt_design = fmincon(@evaluate_loss_opt, [10 10], [], [], [], [], ...
[1 100], [100 1], [], options, implementation, Vin, Iout, Ac);
25 fsw = exp(opt_design(1));
Asw = exp(opt_design(2));
performance = evaluate_loss(implementation, Vin, [], Iout, fsw, Asw, Ac);
30 % Minimization helper function
function ploss = evaluate_loss_opt (param, implementation, Vin, Iout, Ac)
p = evaluate_loss (implementation, Vin, [], Iout, exp(param(1)), ...
exp(param(2)), Ac);
35 ploss = p.total_loss;
B.5.5 permute topologies.m
1 function newtops = permute_topologies (topologies1, topologies2)
% newtops = permute_topologies(topologies1, topologies2)
% topologies1, topologies2: column vectors of either topology
% structures or [{’Topology Name’} {ratio}] pairs
5 %
% For two vectors of topologies, returns a vector of topologies
% consisting of every permutation of topologies in the first vector
% connected in series (cascaded) with the topologies in the second
% vector.
10 %
% Created 10/08, Last modified: 4/15/09
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
15
newtops = [];
for m=1:size(topologies1,1),
for n=1:size(topologies2,1),
20 % returns an (n*m) vector of topology structures
top1 = topologies1(m,:);
top2 = topologies2(n,:);
if ((size(top1,2) == 1) & (size(top2,2) == 1)),
newtops = [newtops; cascade_topologies(top1, 1, top2, 1)];
25 elseif ((size(top1,2) == 2) & (size(top2,2) == 1)),
newtops = [newtops; cascade_topologies(cell2mat(top1(1)), ...
cell2mat(top1(2)), top2, 1)];
elseif ((size(top1,2) == 1) & (size(top2,2) == 2)),
newtops = [newtops; cascade_topologies(top1, 1, ...
30 cell2mat(top2(1)), cell2mat(top2(2)))];
elseif ((size(top1,2) == 2) & (size(top2,2) == 2)),
newtops = [newtops; cascade_topologies(cell2mat(top1(1)), ...
cell2mat(top1(2)), cell2mat(top2(1)), ...
cell2mat(top2(2)))];
216
35 end
end
end
%  Helper: cascade_topologies
40 function newtop = cascade_topologies(topology1, ratio1, topology2, ratio2)
% cascade_topologies: Combine two topologies into a single topology where
% the two topologies are cascaded in a series fashion where topology1
% interfaces with the input and topology2 interfaces with the output
45 if (ischar(topology1)),
topology1 = generate_topology(topology1, ratio1);
end
if (ischar(topology2)),
50 topology2 = generate_topology(topology2, ratio2);
end
ratio1 = topology1.ratio;
ratio2 = topology2.ratio;
55
% scale topology2.v* by ratio1, scale topology1.a* by ratio2
newtop.topName = strcat(topology1.topName, ’ > ’, topology2.topName);
newtop.ac = [topology1.ac.*ratio2 topology2.ac];
newtop.ar = [topology1.ar.*ratio2 topology2.ar];
60 newtop.vc = [topology1.vc topology2.vc.*ratio1];
newtop.vcb = [topology1.vcb topology2.vcb.*ratio1];
newtop.vr = [topology1.vr topology2.vr.*ratio1];
newtop.vrb = [topology1.vrb topology2.vrb.*ratio1];
newtop.ratio = topology1.ratio*topology2.ratio;
65 newtop.Mssl = 2*newtop.ratio^2/(newtop.ac*newtop.vc’)^2;
newtop.Mfsl = newtop.ratio^2/(2*(newtop.ar*newtop.vr’)^2);
B.5.6 plot opt contour.m
1 function plot_opt_contour(topology, ratio, Vin, Iout, Ac, switches, ...
capacitors, esr, optMethod, plotPoints, plotAxes)
% plot_opt_contour: Plot optimization contour, including lossdominant regions
% Michael Seeman, UC Berkeley
5 %
% plot_opt_contour(topology, ratio, Vout, Pout, Ac, switches, capacitors
% [esr, [optMethod, [plotPoints, [plotAxes]]]])
% topology: The chosen topology to plot contour (a string), or a
% topology structure or implementation structure
10 % ratio: The stepup ratio of the converter. If a stepdown
% converter is desired, use a fractional ratio (ie. 1/8).
% Ignored for topology as a structure
% Vout: Output voltage of converter (in V)
% Iout: Output current of converter (in A)
15 % Ac: Capacitor area constraint (in m^2). fsw and Ac will be swept
% switches: a row vector of switch technology structures
217
% capacitors: a row vector of capacitor technology structures
% esr: the outputreferred constant esr of requisite metal (ie, bond
% wires). Default = 0
20 % optMethod: specifies constraint on switch optimization (1=area
% (default), 2=parasitic loss)
% plotPoints: specifies grid size for contour plot. (default=100)
% plotAxes: A row vector giving the desired range of the plot, in log
% input (ie, [6 9 6 3] goes from 1MHz1GHz, 1mm^21000mm^2).
25 %
% Created 4/14/08, Last modified: 4/15/09
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
30
% Fix unspecified parameters:
if nargin < 7, error(’plot_opt_contour requires at least seven inputs’);
end
if nargin < 10, plotPoints=100;
35 if nargin < 9, optMethod=1;
if nargin < 8, esr = 0;
end, end, end
if (ischar(topology)),
40 % topology is a string
topology = generate_topology(topology, ratio);
imp = implement_topology(topology, Vin, switches, capacitors, optMethod);
elseif (isfield(topology, ’topology’)),
% topology is an implementation structure
45 imp = topology;
topology = imp.topology;
ratio = topology.ratio;
else
% topology is a topology structure
50 ratio = topology.ratio;
imp = implement_topology(topology, Vin, switches, capacitors, optMethod);
end
% Constant series resistance, output referred
55 imp.esr = esr;
% Find optimal point for auto axis scaling
[opt_perf, fsw_opt, Asw_opt] = optimize_loss(imp, Vin, Iout, Ac);
opt_perf.Vout
60 if (nargin < 11),
fsw_min = floor(log10(fsw_opt)1);
fsw_max = ceil(log10(fsw_opt)+1);
Asw_min = floor(log10(Asw_opt)1);
Asw_max = ceil(log10(Asw_opt)+1);
65 else
fsw_min = plotAxes(1);
fsw_max = plotAxes(2);
Asw_min = plotAxes(3);
Asw_max = plotAxes(4);
218
70 end
[fsw, Asw] = meshgrid(logspace(fsw_min,fsw_max,plotPoints),...
logspace(Asw_min,Asw_max,plotPoints));
75 p = evaluate_loss(imp, Vin, [], Iout, fsw, Asw, Ac);
[maxeff1, min1] = max(p.efficiency);
[maxeff, min2] = max(maxeff1’);
min1 = min1(min2);
80 [c,h] = contour(fsw, Asw*1e6, p.efficiency, ...
[.05 .1 .2 .4 .6 .7 .8 .85 .9 .92 .94 .96 .98 1], ’b’);
clabel(c,h);
hold on;
contour(fsw, Asw*1e6, p.dominant_loss, [1.5 2.5 3.5 4.5], ’k’);
85 loglog(fsw(min1,min2), Asw(min1,min2)*1e6, ’bo’);
hold off;
xlabel(’Switching Frequency [Hz]’);
ylabel(’Switch Area [mm^2]’);
title(strcat(’I_{OUT} = ’, num2str(Iout), ’A, A_{c} = ’, num2str(Ac*1e6),...
90 ’ mm^2, Eff = ’, num2str(maxeff*100,3), ’ %’));
set(gca,’Xscale’,’log’)
set(gca,’Yscale’,’log’)
B.5.7 plot regulation.m
1 function plot_regulation(topologies, Vin, Vout, Iout, Ac, switches, ...
capacitors, esr, idesign)
% plot_regulation: Plot efficiency vs. input/output voltage based on fswbased
% regulation
5 % Michael Seeman, UC Berkeley
%
% plot_regulation2(topologies, Vin, Vout, Pout, Ac, switches, capacitors
% [noplot, [esr, [optMethod]]])
% topologies: A matrix of topologies and ratios:
10 % [{’SeriesParallel’} {1/2};
% {’Ladder’} {1/3}]
% or a column vector of topology or implementation structures
% Vin: Input voltage of converter (could be a vector)
% Vout: Output voltage of converter (a vector if Vin is a scalar)
15 % Iout: Matching vector of output currents [A]
% Ac: Capacitor area constraint (in m^2). fsw will be swept, Asw
% will be chosen automatically
% switches: a row vector of switch technology structures
% capacitors: a row vector of capacitor technology structures
20 % esr: the outputreferred constant esr of requisite metal (ie, bond
% wires). Default = 0
% idesign: a vector (size = number of topologies) containing the
% nominal design current for each topology
%
25 % Created 6/30/08, Last modified: 4/15/09
219
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
30 % Fix unspecified parameters:
if nargin < 7, error(’plot_opt_contour needs at least seven input arguments’);
end
if nargin < 8, esr = 0; end
optMethod = 1;
35
type = 0; % 1 = Vout, 2 = Vin swept
if (size(Vout,2) > 1)
type = 1;
indim = size(Vout,2);
40 xval = Vout;
end
if (size(Vin,2) > 1)
if (type == 1),
error(’Cannot sweep both Vin and Vout’);
45 end
type = 2;
indim = size(Vin,2);
xval = Vin;
end
50
numtops = size(topologies,1); % number of topologies
EFF = zeros(numtops, indim);
ASW = [];
55 pkeff = [];
pkv = [];
RATIO = [];
FSW = [];
60 Vin_nom = Vin;
for t=1:numtops,
if (iscell(topologies(t,1))),
% this topology is a string and ratio
65 top = topologies(t,1);
ratio = cell2mat(topologies(t,2));
topology = generate_topology(top, ratio);
if (type == 2), Vin_nom = Vout/ratio; end
imp = implement_topology(topology, Vin_nom, switches, capacitors, ...
70 optMethod);
elseif ((size(topologies,2) == 1) && (isfield(topologies(t), ’topology’))),
% implementation structure
imp = topologies(t);
topology = imp.topology;
75 ratio = topology.ratio;
if (type == 2), Vin_nom = Vout/ratio; end
elseif (size(topologies,2) == 1),
topology = topologies(t);
220
ratio = topology.ratio;
80 if (type == 2), Vin_nom = Vout/ratio; end
imp = implement_topology(topology, Vin_nom, switches, capacitors, ...
optMethod);
else
error(’Unknown topology element’);
85 end
% add topology ratio to vector for plot annotation
RATIO = [RATIO ratio];
90 % calculate nominal design current
if (nargin < 9)
if ((type == 1) & (size(Iout,2) == indim))
Iout_nom = interp1(Vout, Iout, Vin*ratio, ’linear’, ’extrap’);
else
95 Iout_nom = max(Iout);
end
else
if (size(idesign,2) > 1), Iout_nom = idesign(t);
else, Iout_nom = idesign; end
100 end
% Constant series resistance, output referred
imp.esr = esr;
105 % Find optimal point for base
[opt_perf, fsw_opt, Asw_opt] = optimize_loss(imp, Vin_nom, Iout_nom, Ac);
% ASW(t) = Asw_opt;
p(t) = evaluate_loss(imp, Vin, Vout, Iout, [], Asw_opt, Ac);
110 EFF(t,:) = p(t).efficiency.*p(t).is_possible;
% FREQ(t,:) = p(t).fsw;
[y,i] = max(EFF(t,:));
pkeff(t) = y;
pkv(t) = xval(i);
115 end
[maxeff, mind] = max(EFF);
% for i=1:size(FREQ,2),
% fsw(i) = FREQ(mind(i),i);
120 % end
plot(xval, EFF*100,’b:’, xval, maxeff*100, ’b’, pkv, pkeff*100, ’bo’);
if (type == 1),
xlabel(’Output Voltage [V]’);
125 elseif (type == 2),
xlabel(’Input Voltage [V]’);
end
% add labels representing conversion ratios
for i=1:size(pkv,2),
130 [n, m] = rat(RATIO(i), .001);
text(pkv(i)*1.01, pkeff(i)*100+1, strcat(num2str(m), ’:’, num2str(n)));
221
end
ylabel(’Efficiency [%]’);
B.5.8 techlib.m
1 % Technology Library
% Copyright 20082009, Mike Seeman, UC Berkeley
% May be freely used and modified but never sold. The original author
% must be cited in all derivative work.
5
%  Oxide Capacitors
% 90 nm Oxide Capacitors
itrs90cap.tech_name = ’ITRS 90nm’;
10 itrs90cap.dev_name = ’ITRS 90nm Oxide Capacitor’;
itrs90cap.capacitance = 40^2*1e15*.7/.09;
itrs90cap.area = (40e6*40e6); % in m^2
itrs90cap.bottom_cap = 135.3e15; % in F
itrs90cap.esr = 0; % in ohms
15 itrs90cap.rating = 1.2; % in V
% 65 nm Oxide Capacitors
itrs65cap.tech_name = ’ITRS 65nm’;
20 itrs65cap.dev_name = ’ITRS 65nm Oxide Capacitor’;
itrs65cap.capacitance = 40^2*.9e15*.6/.065;
itrs65cap.area = (40e6*40e6); % in m^2
itrs65cap.bottom_cap = 135.3e15; % in F
itrs65cap.esr = 0; % in ohms
25 itrs65cap.rating = 1.2; % in V
% 45 nm Oxide Capacitors
itrs45cap.tech_name = ’ITRS 45nm’;
30 itrs45cap.dev_name = ’ITRS 45nm Oxide Capacitor’;
itrs45cap.capacitance = 40^2*.84e15*.5/.045;
itrs45cap.area = (40e6*40e6); % in m^2
itrs45cap.bottom_cap = 135.3e15; % in F
itrs45cap.esr = 0; % in ohms
35 itrs45cap.rating = 1.2; % in V
% 32 nm Oxide Capacitors
itrs32cap.tech_name = ’ITRS 32nm’;
40 itrs32cap.dev_name = ’ITRS 32nm Oxide Capacitor’;
itrs32cap.capacitance = 40^2*.8e15*.45/.032;
itrs32cap.area = (40e6*40e6); % in m^2
itrs32cap.bottom_cap = 135.3e15; % in F
itrs32cap.esr = 0; % in ohms
45 itrs32cap.rating = 1.2; % in V
222
% 22 nm Oxide Capacitors
itrs22cap.tech_name = ’ITRS 22nm’;
50 itrs22cap.dev_name = ’ITRS 22nm Oxide Capacitor’;
itrs22cap.capacitance = 40^2*.58e15*.4/.022;
itrs22cap.area = (40e6*40e6); % in m^2
itrs22cap.bottom_cap = 135.3e15; % in F
itrs22cap.esr = 0; % in ohms
55 itrs22cap.rating = 1.2; % in V
% 16 nm Oxide Capacitors
itrs16cap.tech_name = ’ITRS 16nm’;
60 itrs16cap.dev_name = ’ITRS 16nm Oxide Capacitor’;
itrs16cap.capacitance = 40^2*.48e15*.35/.016;
itrs16cap.area = (40e6*40e6); % in m^2
itrs16cap.bottom_cap = 135.3e15; % in F
itrs16cap.esr = 0; % in ohms
65 itrs16cap.rating = 1.2; % in V
% Filler HV cap
fillercap.tech_name = ’ITRS 16nm’;
70 fillercap.dev_name = ’ITRS 16nm Oxide Capacitor’;
fillercap.capacitance = 40^2*.48e15*.35/.016*.01;
fillercap.area = (40e6*40e6); % in m^2
fillercap.bottom_cap = 135.3e15; % in F
fillercap.esr = 0; % in ohms
75 fillercap.rating = 12; % in V
%  Switch models
% 90 nm switch
80
itrs90n.tech_name = ’ITRS 90 nm’;
itrs90n.dev_name = ’ITRS 90 nm NMOS native transistor’;
itrs90n.area = 1e6 * 90e9 / .4; % in m^2
itrs90n.conductance = 1.11e3; % in S
85 itrs90n.gate_rating = 1.25; % in V
itrs90n.drain_rating = 1.25;
itrs90n.gate_cap = 1e15;
itrs90n.drain_cap = .33*itrs90n.gate_cap;
itrs90n.body_cap = .2*itrs90n.gate_cap;
90
% 65 nm switch
itrs65n.tech_name = ’ITRS 65 nm’;
itrs65n.dev_name = ’ITRS 65 nm NMOS native transistor’;
95 itrs65n.area = 1e6 * 65e9 / .35; % in m^2
itrs65n.conductance = 1.3e3; % in S
itrs65n.gate_rating = 1.25; % in V
itrs65n.drain_rating = 1.25;
itrs65n.gate_cap = .9e15;
223
100 itrs65n.drain_cap = .33*itrs65n.gate_cap;
itrs65n.body_cap = .2*itrs65n.gate_cap;
% 45 nm switch
105 itrs45n.tech_name = ’ITRS 45 nm’;
itrs45n.dev_name = ’ITRS 45 nm NMOS native transistor’;
itrs45n.area = 1e6 * 45e9 / .35; % in m^2
itrs45n.conductance = 1.51e3; % in S
itrs45n.gate_rating = 1.25; % in V
110 itrs45n.drain_rating = 1.25;
itrs45n.gate_cap = .84e15;
itrs45n.drain_cap = .33*itrs45n.gate_cap;
itrs45n.body_cap = .2*itrs45n.gate_cap;
115 % 32 nm switch
itrs32n.tech_name = ’ITRS 32 nm’;
itrs32n.dev_name = ’ITRS 32 nm NMOS native transistor’;
itrs32n.area = 1e6 * 32e9 / .3; % in m^2
120 itrs32n.conductance = 1.82e3; % in S
itrs32n.gate_rating = 1.25; % in V
itrs32n.drain_rating = 1.25;
itrs32n.gate_cap = .8e15;
itrs32n.drain_cap = .33*itrs32n.gate_cap;
125 itrs32n.body_cap = .2*itrs32n.gate_cap;
% 22 nm switch
itrs22n.tech_name = ’ITRS 22 nm’;
130 itrs22n.dev_name = ’ITRS 22 nm NMOS native transistor’;
itrs22n.area = 1e6 * 22e9 / .3; % in m^2
itrs22n.conductance = 2.245e3; % in S
itrs22n.gate_rating = 1.25; % in V
itrs22n.drain_rating = 1.25;
135 itrs22n.gate_cap = .58e15;
itrs22n.drain_cap = .33*itrs22n.gate_cap;
itrs22n.body_cap = .2*itrs22n.gate_cap;
% 16 nm switch
140
itrs16n.tech_name = ’ITRS 16 nm’;
itrs16n.dev_name = ’ITRS 16 nm NMOS native transistor’;
itrs16n.area = 1e6 * 16e9 / .25; % in m^2
itrs16n.conductance = 2.535e3; % in S
145 itrs16n.gate_rating = 1.25; % in V
itrs16n.drain_rating = 1.25;
itrs16n.gate_cap = .48e15;
itrs16n.drain_cap = .33*itrs16n.gate_cap;
itrs16n.body_cap = .2*itrs16n.gate_cap;
224
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Index
analysis code, see MATLAB code
bandgap reference, see voltage reference
boost converter
comparison with SC, 67
for aerial robotics, 107
bottomplate capacitance
reducing, 159
charge multiplier vector, 11, 18, 173
for switches, 176
charge multipliers, 161
meaning of sign, 20
code, see MATLAB code
constraints, optimization
capacitor energy, 34
diearea, 40
parasitic loss, 40
contour plot, optimization, 44
converter metric, see metric, converter
current reference, 135
device cost metric, see metric, device
Dickson topology, 55
digraph, 165
doubler topology, 60
drain charge recovery, 157
dynamic voltage scaling (DVS), 147
energy harvesting, 119
energy per operation, 148
example
charge multipliers, 13, 19
fastswitching limit (FSL), 5, 18, 21
optimized output impedance, 38
Fibonacci topology, 56
FLASH; applications, 1
ﬂyback converter, 110
transformer design, 111
ﬂying capacitor, 3
FSL, see fastswitching limit (FSL)
fundamental cut set matrix, 167
fundamental limit
FSL Metric, 78
SSL Metric, 76
fundamental loop matrix, 167
gate drive
cascode, 126
charge pump, 127
hybrid SCboost converter, 112
hysteretic feedback, 88
lowerbound, 90
inductive load, 26
impedance improvement, 29
interleaved phases, 3, 84
KCL equation, 171
KVL equation, 169
ladder topology, 51
linear system
continuous time, 185
discrete time, 188
link, 166
load type; SC converter, 11, 25
capacitive, 25
current source, 26
inductive, see inductive load
lowdropout regulator (LDO), 135
magneticsbased converters, 66
mass, component, 103
MATLAB code, 191
evaluate loss, 195, 204
generate topology, 191, 207
implement topology, 192, 212
231
optimize loss, 199, 215
permute topologies, 200, 216
plot opt contour, 196, 217
plot regulation, 197, 219
techlib, 222
metric, converter
FSL, 49
SSL, 49
metric, device, 32
for capacitors, 32
for switches, 33
lossbased, 33
Michael Seeman, see awesome
Micro air vehicle (MAV), 102
MicroGlider, 103, 116
hybrid SCboost converter, 116
microprocessor power, 142
converter cell size, 150
dynamic voltage scaling, 147
energy per operation, 148
integrated buck converters, 143
manycore, 143
SC topology, 146
technology scaling, 143
multiratio converter, 146
optimization constraints, see constraints,
optimization
optimization contour, 44
output impedance
approximation, 23
FSL, 21
optimized FSL, 38
optimized SSL, 36
total, 21, 23
twophase, 24
phase, 3
PicoCube, 120
system eﬃciency, 141
power density
components by mass, 104
prior work, 1, 6, 103
regulation, 81
eﬃciency improvement, 83
hysteretic, 88
variableratio topologies, 93
resonant drain, 157
resonant gate drive, 155
ripple voltage, output, 84
interleaved phases, 85
RS232; applications, 1
sample and hold, 137
SC converter, see switchedcapacitor con
verter
seriesparallel topology, 58
shaker, electromagnetic, 121
slowswitching limit (SSL), 5, 6, 10
eliminating impedance with induc
tors, 30
optimized output impedance, 36
softcharging, 26
SSL, see slowswitching limit (SSL)
switchedcapacitor converter, 2
load, 11
phase, 3
stage, 2
topology, 2
symmetrical topologies, 64
synchronous rectiﬁer, 129
eﬃciency, 139
impedance matching, 133
technology scaling, 143
Tellegen’s Theorem, 13
topology, 2
Dickson, 55
doubler, 60
Fibonacci, 56
ladder, 51
seriesparallel, 58
symmetrical, 64
tree, 166
trivial converter, 21
twig, 166
twophase simpliﬁcations, 24
VA product
in a highratio boost converter, 109
voltage reference, 136
sample and hold, 137
well biasing, 159
wireless sensor node (WSN), 119
232
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A Design Methodology for SwitchedCapacitor DCDC Converters
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Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power con verters that use a network of switches and capacitors to e ciently convert one voltage to another. Unlike traditional inductorbased DCDC converters, SC converters do not rely on magnetic energy storage. This fact makes SC converters ideal for integrated implementa tions, as common integrated inductors are not yet suitable for power electronic applications. While they are only capable of a nite number of conversion ratios, SC converters can sup port a higher power density compared with traditional converters for a given conversion ratio. Finally, through simple control methods, regulation over many magnitudes of output power is possible while maintaining high e ciency. A complete, detailed methodology for SC converter analysis, optimization and imple mentation is derived. These methods specify device choices and sizing for each capacitor and switch in the circuit, along with the relative sizing between switches and capacitors. This method is advantageous over previouslydeveloped analysis methods because of its simplicity and the intuition it lends towards the design of SC converters. The strengths and weaknesses of numerous topologies are compared amongst themselves and with magneticsbased converters. These methods are incorporated into a MATLAB tool for converter design. This design methodology is applied to three varied applications for SC converters. First a highvoltage hybrid converter for an autonomous micro air vehicle is described. This converter, weighing less than 150mg, creates a supply of 200V from a single lithiumion cell (3.7V) to supply the aircraft’s actuators. Second, a powermanagement integrated circuit (IC) is presented for a wireless sensor node. This IC, with a target quiescent current of 1 A supplies the system voltages of the PicoCube wireless sensor node. Finally, the initial design of a highcurrentdensity SC voltage regulator is presented for lowfootprint microprocessor applications.
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Copyright 2009, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement The work in sections 5.2 and 5.4 was partially performed while at an internship at Intel during SeptemberDecember, 2008. The Microglider project was funded by the NSF under Grant No. IIS0412541 and by DARPA fund #FA865005C7138. The PicoCube project was supported by the NSF Infrastructure Grant No. 0403427 and the California Energy Commission Award DR0301. I also thank STMicroelectronics for complimentary CMOS fabrication and those at the Berkeley Wireless Research Center.
A Design Methodology for SwitchedCapacitor DCDC Converters by Michael Douglas Seeman S.B. (Massachusetts Institute of Technology) 2004 M.S. (University of California, Berkeley) 2006
A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering – Electrical Engineeing and Computer Sciences in the GRADUATE DIVISION of the UNIVERSITY OF CALIFORNIA, BERKELEY
Committee in charge: Professor Seth R. Sanders, Chair Professor Elad Alon Professor Paul Wright
Spring 2009
A Design Methodology for SwitchedCapacitor DCDC Converters Copyright c 2009 by Michael Douglas Seeman .
as common integrated inductors are not yet suitable for power electronic applications. Finally. While they are only capable of a ﬁnite number of conversion ratios. detailed methodology for SC converter analysis. Chair Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power converters that use a network of switches and capacitors to eﬃciently convert one voltage to another. along with the relative sizing between switches and capacitors.Abstract A Design Methodology for SwitchedCapacitor DCDC Converters by Michael Douglas Seeman Doctor of Philosophy in Engineering – Electrical Engineeing and Computer Sciences University of California. SC converters can support a higher power density compared with traditional converters for a given conversion ratio. SC converters do not rely on magnetic energy storage. optimization and implementation is derived. The strengths and weaknesses of numerous topologies are compared amongst themselves and with magnetics 1 . This fact makes SC converters ideal for integrated implementations. Sanders. through simple control methods. These methods specify device choices and sizing for each capacitor and switch in the circuit. This method is advantageous over previouslydeveloped analysis methods because of its simplicity and the intuition it lends towards the design of SC converters. regulation over many magnitudes of output power is possible while maintaining high eﬃciency. A complete. Berkeley Professor Seth R. Unlike traditional inductorbased DCDC converters.
a highvoltage hybrid converter for an autonomous micro air vehicle is described. First. Finally.based converters. supplies the system voltages of the PicoCube wireless sensor node. the initial design of a highcurrentdensity SC voltage regulator is presented for lowfootprint microprocessor applications. Professor Seth R.7V) to supply the aircraft’s actuators. These methods are incorporated into a MATLAB tool for converter design. a powermanagement integrated circuit (IC) is presented for a wireless sensor node. Sanders Dissertation Committee Chair 2 . This converter. This IC. creates a supply of 200V from a single lithiumion cell (3. with a target quiescent current of 1 µA. weighing less than 150mg. Second. This design methodology is applied to three varied applications for SC converters.
5 Extension to NonLinear Capacitors . . . . . . . . . . . . . . . Preexisting SwitchedCapacitor Converter Analysis . .2 1. . . . . . . 2. . . . . . . . . . . . . . .1 2. . . . . . . . . . . . . . . . . Model Simpliﬁcation for TwoPhase Converters . FastSwitching Limit Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5. . . . . . . . . . . . . i v viii ix 1 1 2 6 7 10 11 16 18 21 24 24 25 26 26 2 Fundamental Analysis of SwitchedCapacitor Converters 2. . . .4 2. .2 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modeling Other Converter Loads . . .2 2. . . .3 1. . . . . . . . . . . . . . .1 SlowSwitching Limit Impedance . . . . . . . . . Calculating Total Output Impedance . . . . . . . . SwitchedCapacitor Converter Structure and Terminology . . . . .1 1. . . . . . . . . . . . . . . . . .1 2. .3 2. . . . . . . . . . . . . . . .1. . . . . . . . . CurrentSource Load . . . . .3 Capacitive Loads . . . . . . . . . . . . . . . . . .5. . . . . . .5. . . . .Contents Contents List of Figures List of Tables Acknowledgments 1 Introduction 1. .4 SwitchedCapacitor Converters in Industry and Literature . . . i . . . . 2. . . . Developments in This Work . . Inductive Load . . . . . . . .
. . . . .2 SSL Converter Metric Limit . 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analysis of SC Topologies . . .3 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . SeriesParallel Topology . . . . . . . . . . . . . . . . . .1 Symmetrical Topologies .5 Fundamental Performance Limits . . . . . . . . . . Switch Sizing . . . . . . . . .4. Hysteretic Feedback Methods . . . . . . . . . . . . . System Modeling . . . . . 31 32 33 35 37 38 41 41 43 48 49 50 51 55 56 58 60 61 64 66 67 71 75 76 78 81 83 88 91 93 94 SystemLevel Converter Optimization . . . . .3 Capacitor Sizing . . . . . . . . . . . . . . . . 5 Regulation of SwitchedCapacitor Converters 5. . . . .1 4. . . . . .1 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . .2 4. . . . . . . . . . . . . . 4. . . . . .2 Converter Loss Components . . .4. . . .5. . . . .3.4 Output Ripple of Multiphase Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5. . . . . 4. . . . . . . .1 4. . . . . . . .2 Switch Comparison . . . . . FSL Converter Metric Limit . . . . . . . . . . . . . . . . . . . . . . Fibonacci Topology . .2 Device Cost Metrics . . . . . . . . . . . . Doubler Topology . . . . . . . .1 4. . .2. . . . . . . .1 3. . . . . . . .2.3 Ladder Topology . . . . . . . . . . . Numerical Optimization . . . . .2. . 5. . . . . . . . .2. . . .3. . . ii . . . . . . . . . . .4 Comparison with MagneticsBased Converters . . . . . . . . . Component Sizing . . . . . . . . . . . . . .1 Topology Description .2 5. . . . . . . A MultiRatio Converter for Portable Electronics . . . . . . . . . . . . . . . . . . . . .1 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . . . . . 4 Comparing SwitchedCapacitor Topologies 4. . . . . . Comparison of SC Topologies . . .1 3. . . . . . . . . .2. . . . . .5 4. . . . . . . . . . . . . . . . . . . . . . . . . . .2. . .3 Optimization of SwitchedCapacitor Converters 3. . . . 4. . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . Reactive Element Comparison . . . . .2 Converter Performance Metrics . . . . . . . . . . . . 4. . . . . . . . . . . . . . . . . . . . . . . 4. . . . . . .5. . . . . .1 4. Dickson Charge Pump . . . . . . . . . . . . . . . . . . . . .4 4. . . . . . . . Optimizing Using Other Metrics . . . . . . .3. . . . . . . . . . . . . . . . . . .2. . . .2 3.3 3. . .
. . . . . . . .3. . . . 96 100 102 103 107 110 112 116 119 120 123 126 128 132 134 141 142 143 145 147 150 153 154 155 158 161 164 164 167 168 6 HighVoltage Converters for Airborne Robotics 6. . . . . . .1.3 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Finding the Conversion Ratio and Component Voltages . . . . . . . . . . . . . . . . . . . . .3 Resonant Gate Drive . . . . . . .2. . . . . Hybrid SwitchedCapacitor Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . A.3 Control Method . . . . . . . . . . . . . . . . . . A. .1 6. . . . . . . . .1 Comparison of Topologies for Lightweight HighVoltage DCDC Converters 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7. . . . . . . . 8. . . . . . . . . . . . . . . . . . . .2 Power Density vs. . . Drain Charge Recovery .3 6. . . . . . . .4. . . . . . . . .5. . . . . . . . . . . . . .2 8. . .4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii . . . . .2 Modeling SwitchedCapacitor Networks . . . . . . Converter Design . . . . . . . .2. . .2 5. . . . .4. .3.5 7. . . . . . . . . . . . . . . . . . . . 9 Conclusions A NetworkTheoryBased Analysis for SwitchedCapacitor Converters A. . . . . . . . . . . . . . . .4 Application and IC Overview . . . . . . . . . Cell design . . . System Eﬃciency . . . . .1 Summary of Circuit Theory . . . . . Experimental Results . . . . . .2. . . . . . . . . . . . . Gate Drive . . . . . . . . . . . . . . . . . MicroGlider Power Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . Eﬃciency Improvements . . . . . . . . . . . . . . . . . . . . . . 7. . . . . 8 SwitchedCapacitor Converters for Microprocessors 8.1 8.1 8. . . . . . . . . . . . . . . . .2 Boost Converter . . . . . . . . . . . . . . 8. . . . . . . . . . . . . .1 7.2 6. UltraLowPower Analog Circuits .6 Impedance matching AC energy harvesters with diode rectiﬁers . .2 8. Synchronous Rectiﬁer . . . . . .3 Dynamic Voltage Scaling Analysis . .1. . . . .1 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scaling . . . . . . . . Flyback Converter . . . . Reducing BottomPlate Capacitance . . .3. . . . . . . . . . 7 SwitchedCapacitor Converters for Wireless Sensor Nodes 7. . . . Converter Architecture and Optimization . . . .1 7. . . . . . . . . . . . . . .
. B. . . . . B MATLAB Package for SwitchedCapacitor Converter Design B.4 Example . . . . . . . . . .2 generate topology. . . . . A. . . . . . . . . . . . . . . . . . . . . .4 Converter Dynamics . . . . . . . A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. . . . . . . . . . . . . A. . .3 Criteria for ProperlyPosed SC Topologies . . . . . . . . . . . . . . . . . . . .m . . . . . . . . . . . . . . . . . . . . . .4 Dynamics Simulation . . .5 permute topologies. . . .m . . . . . . .m . . . . . . . . . . . .4. .5. . . .5.6 plot opt contour. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 DiscreteTime Model . . . .4. . . . . .2 SinglePhase Dynamics . . . . . . . . . . . B. . .A. . . . . . . . . . . . . . .3 Helper Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. . . . . . . . . . .2 Determining the Charge Multiplier Vector . . . . . . . . . . . .3 implement topology. . B. . . . . . . . . . . . B. . . . .5.8 techlib. . . . . . . .m . . . . . . . . . . . . . . B. . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Visualization Functions . . . . . .m . . . B. . . . . . . . .4 optimize loss. . . . . Bibliography Index 170 176 180 181 182 186 188 190 191 196 199 200 204 204 207 212 215 216 217 219 222 225 231 iv . . . . . . . . . . . . . . A. .1 Core Functions . . . . .1 Preparing the System . . . . . . . . . . .5. . . . . . .7 plot regulation. . . . . . . . . . . . . . . . . .m . . B. . . . . . . B. . . . . . . . . . . . .1 evaluate loss. . . . . . .m . . . . . . . .5 Code Listings . . . . . . . . . . . . . . .5. . . . . . . . . . .4. . .5. .5. . . . . B. . . . . . . . . . . . . . . . . . B. . . . . . . . . . . . . . A. . . . .m . . B. . . . . .4. . . . . . . . . . . . .5. . . . . . . .2. . . . . . . . . . . .
. . . . . . . . . . 2:1 ladder converter: (a) topology (b) waveforms for current and voltage source loads . . . . . . . .11 Output impedance of SC converter with inductive load . . Five common switchedcapacitor converter topologies in their stepup form A 2:5 ladder topology . . . . . .5 Example SC converter optimization plot . . . . . . . . . . . . . . . Trivial SC converter used for dynamic analysis . . . Idealized 2port SC converter model . . . . . . Example eﬃciency contour plots of a 3:1 seriesparallel converter . . . . . . . . . . . . . . . . . . 3 4 5 12 12 16 17 19 22 22 27 27 28 30 45 46 52 53 59 63 65 2. . . . . . . . . . .2 1. .4 4. . . . . . . . . . . . . . . . . . . . Capacitor charge ﬂow in ladder converter. . . . .1 1. . . . . . . . .3 2. A 3:1 ladder topology . .List of Figures 1. . . . . . . . . . . . . . . . .6 2. . . . . .5 2. . . . . A 2:5 seriesparallel topology . . . . . . . . . . . . . .2 2. . . .2 4. . . . . . . . .3 4. . . . . . . . . b) phase 2 network. . . . . . . . . . . . . . . (a) phase 1 and (b) phase 2 . . . . . . . 3. . c) waveforms . .1 3. .1 2. . . . . . . .9 An idealized 3port SC converter . . . . Capacitor voltage waveform of trivial converter . . . . . . . . . . Symmetric 2:5 ladder topology . . . . . . . . including networks in (b) phase 1 and (c) phase 2 . Switch charge ﬂow in ladder converter: (a) phase 1 and (b) phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . Output impedance when RSSL ≈ RF SL and approximations . . . . . . . . .4 2. . . . . . . . . Nonlinear capacitor losses in a threephase converter . . . . 2. . . .7 2. . . . . . . . . . . . . . . . . .3 2. . . . .8 2. . . . . . . . . A 3:1 ladder topology. . . . . . .2 4. . . . . . . . . . . .10 SC converter with inductive load: a) phase 1 network. . . . . . . . . . . . . . . . . . . Comparison of SSL and FSL converter metrics . . . . . . . . . . . . Energy loss due to capacitor charging . . . v . . . .1 4. . . . . . . . . . . .
.4 5. . . . . . Cascode levelshift gate drive for the 1:2 ladder converter . . . . . . . . . . . . . . . . . . . .11 Controller for the multiratio converter . . . . . . . . . .9 5. . . . . . . . highvoltage DCDC conversion . Idealized dynamics model for system modeling . . . . . . . Lowerbound hysteretic feedback controller . . . . . . . . . . . . . . . . . . . . . . 5. . . . . .2 5.2 6. . . . . . . Capacitorboost gate drive for the 3:2 converter . . . .7 4. . . . . .8 Three topologies for lightweight. . . . . . . . . . . 6. Eﬃciency during power backoﬀ. . . . . . Waveform from lowerbound feedbackbased converter . . . . . . . . . . . . . . . . 121 122 123 125 127 128 129 vi . . .13 Output voltage and eﬃciency of the multiratio converter prototype . . . . . . .1 7. . . .4. . . .8 5. . . . .1 6. . . . . . . . . .4 7. . . .8 4. Photos of the MicroGlider and control PCB . Traditional magneticsbased converters . . . . . . . . . 6. . .4 6. Shaker (a) design and (b) example input waveform . . . . . . . . . . . Block diagram of the converter IC . . . . .6 5. . . . . . Hybrid switchedcapacitor boost converter . . . . . . . . . . .7 5. . . . . . . . . . . . .5 7. . . . 5. . . . . {5. . . . . . . . . . . . .1 5. . Available (a) capacitors by voltage and (b) inductors by current . . . . . . . . . .10 Predicted eﬃciency of multiratio converter . . . 8} : 7 ladder topology stage . . . . Optimization contours of the (a) 1:2 converter and (b) 3:2 converter . . . . Output voltage ripple of an N interleavedphase 2:1 converter . . 5. . . . .5 7. . . . . . . Switchlevel diagram of a) 1:2 converter. . . . . . . . . . . . Hybrid SC boost converter as appearing on the MicroGlider . . . . . . . . . . . . . FSL metrics for magneticsbased and SC converters . . . . 2:1 converter . . Photos and dimensions of the a) PicoCube and the b) electromechanical shaker120 Measurement and transmission power . . . . . . . . . . . . . . . . . Doublebound hysteresis feedback for the PicoCube application . . . . . . . . . . . .6 7. . . . . 2:1 Dickson topology stage . . . . . . 3:1. . . . . .9 SSL metric improvement with symmetric converters . 5. . . . .7 7. . . . . . . . .2 7. . 66 67 70 74 83 86 87 89 90 91 92 94 95 97 98 99 101 104 106 112 117 117 SSL metrics for magneticsbased and SC converters . .3 5. . . . . . 7. Current transfer and output voltage ripple waveforms of a regulated fourphase 2:1 converter . . . . . . . . . . .3 7. . . . . . . .3 6. . . . . . . . . . . . .5 5. . . . . . . . b) 3:2 converter . . . . . .12 Operation regions for the multiratio converter . . . . . . . . .6 4. . . . . . . . . . . . . . . . . . . . . . . .
.7 8. . . . . . . . . . . . . . . . . . . . . . .13 Schematics of analog references . . .15V . 7. . . A. . . . . . . . . . . . . . . . .8 8. . . . . . 130 131 133 135 136 136 137 138 139 140 145 146 147 149 150 153 156 157 159 165 168 177 179 189 202 7.5 8. 7. . . . A. . . . . . . . . .9 SC converter performance versus ITRS technology node . . . . . . . . . . . . . . . 8. . . . . . . . . . . Vin = 1. 7. . . . . . . . . . . . . . . . . A. . . . . . Tripleratio topology and its switch conﬁgurations . . . . . . . .16 SC Converter output voltage and eﬃciency.9 Synchronous rectiﬁer circuit . . . . . . . . . . . . . .14 Lowleakage sample and hold circuit . . . . . . .2 3:1 Ladder topology. . . . A. . . . . . . . . . . . . .3 Three conﬁgurations of a 2:5 seriesparallel topology . . .1 An example circuit with graph representation . . . . . . . . . . . . . . including twig designations in each phase . . . . . . . . . . . . 100 Hz input . . . . . . . 7. 7. . . . . . . . . . . . . . Approximate ring oscillator performance versus supply voltage . .4 An improperlyposed switchedcapacitor converter . . . .2 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Photomicrograph of power interface IC . B. . . . . . . . . . . . . . . . 7. . . . RS = 2. . . . 7. . . . . . Parasitic capacitance ratios for body and well capacitances . . A. Waveforms of drain charge recovery methods . . . . . . . . . . . . . . . . . . . . . . . Nonscaling components of power loss versus cell size . . . . . VB = 1. . . . . . . . .10 Circuits implementing the synchronous rectiﬁer . . . . .18 Synchronous rectiﬁer waveforms (at 100 Hz) . . . . . .1 8. . . . . . . . . Energy per operation using an SC converter . . .11 Available energy via rectiﬁcation into a ﬁxed voltage source . . vii . . . . . . Eﬃciency plot of tripleratio topology in a 32nm process . .5 Simulation of the dynamics of 3:1 ladder converter . . . . . . . . . . .3 8. . . .2V . .6 8. . 7. . . .4 8. . . . . .7. . . Drain charge recovery using a twointerleavedphase 2:1 converter . . . . . . . . .17 Power output and eﬃciency of synchronous rectiﬁer. . .1 Example plots from the MATLAB package . . . . . . . . .0kΩ.12 Diagram of control logic . . . . . . . . . . . .
. . . . .6 6.1 3. . .2 6. Mass of common surfacemount components . . . . . . . . . . . . . . . . . . . .2 Energy eﬃciency over sensing period . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 73 105 105 109 111 114 116 118 141 144 144 4. . . . . . . . . . Energy densities of common (a) capacitors and (b) inductors . . . . . .1 6. . .1 8. . . . . . . . . . . . . . . . . . . . . . . . . .2 Capacitor optimization summary for two device cost bases (twophase simpliﬁcations) . . Eﬃciency of singlestage boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8. . Process parameters from the ITRS roadmap . . . . . . . . . . . . . . . Switch optimization summary for two device cost methods (twophase simpliﬁcations) . . . . . . . . . . . . Eﬃciency of ﬂyback converter using custom transformer . . . . Eﬃciency of hybrid boost converter . . .7 7. . .4 6. . . . TDP and pin counts for three modern Intel microprocessors . . . viii . . . .1 6. . . . . . . . . . . . . . . .3 6. . . . . . . . . . . . . . . Experimental results of the MicroGlider converter . . . . . .List of Tables 3. Nchannel MOSFETs in SOT23 package .5 6. . . . . . . . . . Eﬃciency of ladder converter with 4–10 stages at 10 mW load . . . . . . . . . . . . . . . . . . . . . . .
Mike Koplow. and Michael Armbrust. So many great adventures and memories. Artin der Minassians. Ariel Cowan. Tim Keller. my advisor. Mervin John and others. Donovan Lee. Alejandro de la Fuente.Acknowledgments I would like to thank a number of people and organizations that have helped me through my research at UC Berkeley and in my life to date. way too many to name here. Linda Kwong. HahnPhuc Le. Rachel Zeldin. Professors Seth Sanders and Elad Alon have been great in challenging me with numerous ideas and fully developing our understanding of switchedcapacitor converters. Sarah Bird. Bryan Brady. Rob Wood. Julie Butler and numerous others over the years. Evan Reuzel. bar hopping in the Mission. Derek Schoonmaker. and his group. including Tarik Bushnak. including Jason Stauth. Kun Wang. Vincent Ng. They have supported me through grade school through college without placing excessive pressure academically or ﬁnancially. We have persisted in one of the smallest power electronics groups in the country to produce outstanding work and ideas in a variety of areas of the ﬁeld. Lisa Chen. but some include Ankur Mehta. First. There are too many to list. Beth Reilly and others have been great in our collaborations and have contributed to the diverse education I have received here. Christine Ho. Seth Sanders. ix . The days of ultimate frisbee. Emilie Le Bihan. Lindsay Miller. First. Mike He. I would also like to thank the members of Cedar House. Josh Hug. I also appreciate numerous others in the EECS department and the EEGSA which have been great friends over the years. Heather Brinesh. I’d like to thank my parents who have raised me to have an inquisitive mind which never stops thinking about how things work and how to solve problems of every type. and their students Erik Steltz. Professors Ron Fearing and Paul Wright. I would like to thank my labmates through the various projects I have worked on here at Berkeley. allowing me to concentrate on what I love. my residence for three and a half years. Kevin Petersen. and numerous Wednesday afternoon social hours will always be some of my fondest memories of Berkeley. Next. Eli Leland. Amit Lakhani.
ﬁndings and conclusions or recommendations expressed in this material are those of the author and do not necessarily reﬂect the views of the National Science Foundation (NSF). Pavan Kumar. x . 2009. Any opinions. IIS0412541. I also gratefully acknowledge DARPA for support under fund #FA865005C7138. Finally for support of this research. Sunil Jain and Ken Drottar. Tomm Aldridge. I would like to thank the sponsoring organizations of the research. During this internship. Annabelle Pratt. I’d like to acknowledge those I worked with there in CTG and UMG. The PicoCube project was supported by the National Science Foundation Infrastructure Grant No. faculty and sponsors of the Berkeley Wireless Research Center (BWRC) for their support of this project.During my internship at Intel Corporation during the Fall semester.4. The Microglider project was funded by the National Science Foundation under Grant No.2 and used to implement the SC converter prototype described in section 5. I would also like to thank the students. I developed the lowerbound feedback method presented in section 5. to name a few. Some include Rinkle Jain. We would also like to thank STMicroelectronics for complimentary CMOS fabrication. 0403427 and the California Energy Commission Award DR0301.
xi .
typically providing ﬁxedratio conversions (such as a simple doubling. they are ideal for integrated implementations. using only switches and capacitors. Additional discretecapacitor SC converter ICs provide conversion for LED lighting applications. 1. that can eﬃciently convert one voltage to another. 1 . They have historically been used in integrated circuits to provide the programming voltage for FLASH and other reprogrammable memories [66]. and to generate the voltages required by the RS232 serial communication standard [30].Chapter 1 Introduction Switchedcapacitor (SC) DCDC power converters are a subset of DCDC power converters. halving or inverting of the voltage). SC DCDC converters also exhibit other advantages (and disadvantages) which will be further examined in this work. These parts have been relatively simple. a promising application of SC converters [31]. as common integrated inductors are not suitable for power electronic applications. Since SC converters use no inductors.1 SwitchedCapacitor Converters in Industry and Literature Switchedcapacitor converters have been used in commercial products for many years.
Additionally. 1. It supports regulation through the use of two conversion ratios and by varying switching frequency.1. It employs an externalcapacitor design using three ﬂying capacitors which supports multiple conversion ratios and full output regulation. In general.8 V) to 3. resistive load. This research aims to improve the power density and ﬂexibility of onchip SC DCDC power converters.3V converter for consumer products [58]. The LM3352 chip from National Semiconductor[32] is a 200 mA buck/boost DCDC converter chip. orstages. Each port can be connected to a voltage source. A converter can be made of any number of series subconverters. These products push SC converters into the space occupied by regulated inductorbased converters. A converter stage may also implement a number of parallel copies of 2 . By changing the way the switches in a converter are clocked. or any other type of circuit.2 SwitchedCapacitor Converter Structure and Terminology A switchedcapacitor (SC) DCDC converter is a power converter which is comprised exclusively of switches and capacitors. Improvements in PCB area utilization can be made by moving the capacitors onchip. Additionally. only a miniscule amount of power is available from this part. allowing its use in ultralowpower applications. Each topology corresponds to a particular conﬁguration of switches and capacitors which achieves a particular conversion ratio. to expand the conversion ratio range. an SC converter can have an arbitrary number of ports. For example. the chip supports an extremelylow standby power (2 µA). such as wireless sensor nodes. The MAX203E RS232 transceiver IC from Maxim uses internal capacitors to generate a ±10 V supply from a singlepolarity 5 V input. a singlestage SC converter can implement one or several topologies.9 V to 1. the TPS60311 chip from TI is a singlecell (0. a converter can be conﬁgured into multiple topologies. where the converter is denoted a multiratio converter. allowing for precise regulation for IC applications. as shown in ﬁgure 1. However. current source.Only recently have SC converters come to market which utilize advanced techniques.
e.e. This twoport converter exhibits a conversion ratio of threetoone. output ripple frequency will be increased and ripple magnitude will be decreased. and using equallyspaced interleaved clocking. and are known as output or bypass capacitors. the topology performs power conversion between its ports. The requirements placed on an SC topology to be wellposed are discussed in section A. If a stage has N interleaved phases. 3 . These n phases are designated φ1 through φn . Each topology consists of a collection of switches and capacitors. the converter multiplies charge by a factor of three. An example of a laddertype SC converter topology is shown in ﬁgure 1.3. In this topology.i1 + v1 SwitchedCapacitor Converter i3 + v3  i2 + v 2 Figure 1. Interleaving will be further discussed in section 5.1. An idealized 3port SC converter the topology (or set of topologies). Capacitors C1. are ﬁxed with respect to ground).2. the oddnumbered switches are turned on during phase 1 and the evennumbered switches turn during in phase 2. the output is onethird of the voltage of the input under noload conditions. the switches conﬁgure the topology into a network of capacitors and onstate switches (modeled as resistances). Capacitors C4 and C5 are known as ﬂying capacitors since their commonmode voltage moves with respect to ground. they will be denoted Φ1 through ΦN . each known as an interleaved phase. i. By switching through the phases. Each switch is turned on during one or more phases. Each switching period consists of n nonoverlapping subdivisions known as phases. C2 and C3 have a DC commonmode voltage (i. By placing these interleaved phases in parallel.1. In each clock phase. Likewise.
A 3:1 ladder topology.VIN S1 C1 S2 C4 S3 C2 S4 C5 S5 C3 S6 VIN VIN C1 C1 C4 C4 C2 C2 C5 VOUT C5 VOUT VOUT C3 C3 (a) (b) (c) Figure 1. including networks in (b) phase 1 and (c) phase 2 4 .2.
each capacitor should support a DC voltage. 35]. The slowswitching limit (SSL) impedance is calculated assuming that the switches and all other conductive interconnects are ideal. a DC voltage should appear at the opencircuited ports. The model is made up of an ideal transformer with a turns ratio equal to the noload conversion ratio. These criteria ensure that charge is preserved and no shorting events occur. Additionally. The SSL impedance is inversely proportional to switching frequency. If the converter is properly posed. To transfer charge between the input and output ports of the converter. There are two asymptotic limits to output impedance. capacitors and interconnect dominate. the slow and fast switching limits. and also determines the openloop load regulation properties. With a DC voltage source applied to one of the converter’s ports (designated the input). and the capacitors act eﬀectively as Ideal components include ideal capacitors and idealized switches with a ﬁnite onstate resistance and an inﬁnite oﬀstate resistance. and that the currents ﬂowing between input and output sources and capacitors are impulsive. The fastswitching limit (FSL) occurs when the resistances associated with switches.3.3 sets the maximum converter power. necessitating a voltage drop across the converter. modeled as charge transfers. the clocked converter will operate in a steadystate condition. This voltage drop is proportional to output current.First.3. the noload case will be examined with idealized components1 . Idealized 2port SC converter model The lowfrequency output impedance ROU T in ﬁgure 1. ROUT v OUT m:n vIN Figure 1. constrained by a minimal eﬃciency objective. the converter’s capacitors must be charged and discharged. and the remaining ports opencircuited. and no steadystate current should ﬂow from the input source. as discussed in references [27. as discussed in appendix A.3. as related to switching frequency. and can be represented as an output resistance. 1 5 . An idealized model for a twoport SC converter is shown in ﬁgure 1. and an output resistance ROU T .
Since the output resistance does not aﬀect the ratio of input to output currents in the model. One of the early SC papers. As this equality also holds on an integral cycle basis.2). it can be used to develop a charge conservation constraint. it also can be used to form an inputoutput constraint on charge ﬂow. a moreuniﬁed and general analysis approach is needed.3 perfectly represents the characteristics of an SC converter using ideal capacitors and resistive switches. current ﬂow occurs in a frequencyindependent piecewise constant pattern. However.1) Since this charge conservation equality holds independent of load. Numerous additional references [8. It introduces a networktheoretic method for determining the conversion ratio and SSL output impedance. and does not address the FSL output impedance besides suggesting its existence. they are not ideal for widespread adoption. Since the matrixbased methods are complex. Maksimovic and Dhar’s groundbreaking work in [27] develops a fundamental model of SC converters and introduces the concept of the slowswitching limit (SSL) impedance. 34] follow the same approach and use nongeneral analysis methods to solve their particular problems. this analysis assumes a diodebased implementation and only applies for that speciﬁc topology family. Clearly. 1.3 Preexisting SwitchedCapacitor Converter Analysis Many papers have attempted analyses of SC converters. introduces and analyzes what is known as the Dickson topology (see section 4. 6 . and are unnecessary for most analysis of SC converters. it can be used for further analysis in later chapters. The analysis work in chapter 2 takes this work and extends its simplicity and generality. these two currents are ﬁxed by the transformer turns ratio as: IIN = − n IOU T m (1. the analysis method in [27] is not entirely general. 35. 67. In the FSL. Additionally. [15].ﬁxed voltage sources. Computation of the FSL and SSL output impedances will be developed in chapter 2. Since the model in ﬁgure 1.
a multipleratio SC converter for portable electronics is discussed involving both automatic conversion ratio changing and hysteretic feedback to eﬃciently regulate the output voltage. This chapter also compares SC converters to magneticsbased DCDC converters in terms of both switch and reactiveelement utilization. a fundamental limit on the performance of SC converters is shown in both the SSL and FSL. allowing the selection of the best topology for a given application. The last of the analysis chapters. are compared in both the slowswitching and fastswitching limits. This chapter also discusses the systemlevel design of a converter by choosing the optimal switching frequency and switch area for a given design power. including methods of reducing this ripple. This optimization is based on costbased metrics where the total device cost (for both capacitors and switches) is limited.1. Dickson. Chapter 3 uses the simple formulation of the output impedance of an SC converter developed in chapter 2 to develop a method of properly sizing the capacitors and switches. Fibonacci and doubler topologies. 7 . The output impedances for numerous topologies. Finally. These charge multipliers are used to ﬁnd the output impedance of an SC converter. simple hysteretic control methods are introduced involving very little circuitry to maintain regulation.4 Developments in This Work The aim of this work is to present a complete analysis and design methodology for SC converters. Finally.2 to introduce charge multipliers which characterize the charge ﬂows in an SC converter. Chapter 2 uses the fundamental descriptions from section 1. followed by several descriptions of SC converters being used for various practical applications. It is shown that SC converters can achieve a higher power density than magneticsbased converters considering both transistors and reactive elements. A simpliﬁed model of SC converters is developed to model and simulate statebased control methods. including the ladder. The merits of diﬀerent SC topologies are discussed in chapter 4. the ripple occurring at the output of an SC converter is discussed. chapter 5 discusses the regulation of SC converters. seriesparallel. Next. First.
Appendix B describes a MATLAB package which automates the design process of a SC converter. This appendix derives the exact timebased dynamics of an SC converter from the fundamental network matrices for the converter. including design considerations and performance results. In addition. Chapter 6 compares several DCDC converters used to drive piezoelectric actuators for airborne robotics. At a power density of 1 W/mm2 . A synchronous rectiﬁer eﬃciently harvests energy from an electromagnetic energy scavenger. Chapter 8 discusses using SC converters for very highpower applications using entirelyintegrated converters. This converter produces 200 V from a 3. methods of increasing the eﬃciency of highpowerdensity SC converters are introduced. this work includes two appendices.Three applications of SC converters are then presented. The converter achieves an eﬃciency of 84% while consuming less than 10 µW with no load. Finally. This chapter introduces a multipleratio converter which can be integrated on the same die as mainstream microprocessors to supply power to individual cores of a multicore processor. This analysis method will beneﬁt designers greatly in the use of SC converters 8 . The hybrid boostswitchedcapacitor converter used for a twogram autonomous glider is presented. an eﬃciency of approximately 80% is predicted. Chapter 7 describes power conditioning and conversion circuitry used in a cubiccentimeter wireless sensor node. This work aims to present a complete and straightforward design methodology for SC converters. Appendix A discusses the networktheoretic analysis of SC converters which can be used to develop CAD tools for the analysis of SC converters. The design and performance of this power management IC are presented. This package is used several times in this work as a design and visualization tool. This work opens the door towards highperformance.6V input at a power level of 10mW with a total component mass of 100 mg. Two SC converters supply the loads in the sensor at their required voltages. It also discusses the properties of properlyposed converters. highpower density SC converters. The power density of SC converters is examined with regard to process scaling. charging a small nickelmetalhydride cell.
9 . applying the methods developed in this work.for both integrated and nonintegrated applications. Three applications using SC converters are also presented.
The slowswitching limit (SSL) impedance is calculated assuming that the switches and all other conductive interconnects are ideal. can be incorporated into the model. constrained by a minimal eﬃciency objective. 51]. The resistive output impedance accounts for capacitor charging and discharging losses and resistive conduction losses. and all conversion losses are manifested by voltage drop associated with nonzero load current through the output impedance [27. 35].3. The aim in this chapter is to provide a general analysis and design framework. the converter provides an ideal dc voltage conversion ratio under no load conditions. the slow and fast switching limits. and that the currents ﬂowing between input and output sources 10 . as related to switching frequency [50. There are two asymptotic limits to output impedance. While these parasitic losses are not considered in the analysis in this chapter. they will be incorporated into the systemlevel design in section 3. Additional losses due to shortcircuit current and parasitic capacitances. The lowfrequency output impedance ROU T in ﬁgure 1. in addition to gatedrive losses.Chapter 2 Fundamental Analysis of SwitchedCapacitor Converters With the model in ﬁgure 1.3 sets the maximum converter power. and also determines the openloop load regulation properties.3.
In the FSL. modeled as charge transfers. current ﬂow occurs in a frequencyindependent piecewise constant pattern. capacitors. If a consistent set of capacitor voltages can be found. Each element of a charge multiplier vector corresponds to a speciﬁc capacitor or independent voltage source.1 The charge multiplier vectors correspond to charge ﬂows that occur immediately after the switches are closed to initiate each respective phase of the SC circuit. and the capacitors act eﬀectively as ﬁxed voltage sources. the charge multiplier vectors can be uniquely computed using the KCL constraints in each topological phase and the steadystate constraint that the n charge multiplier quantities on each capacitor must sum to zero.1 SlowSwitching Limit Impedance For the slowswitching limit (SSL) impedance analysis. and interconnect are neglected. 2. The eﬀect of other loads on eﬃciency and operation will be discussed in section 2. The twophase model in [48. capacitors and interconnect dominate. such that ROU T is a scalar. A set of charge multiplier vectors a1 through an can be derived for any standard wellposed nphase SC converter.5. 51] will be extended here to multiphase converters. an excess of DC capacitors (such as decoupling capacitors) prevents a unique vector from being computed. The total output impedance of the converter is a combination of the two impedance components as examined in section 2. the ﬁnite resistances of the switches. This allows the determination of the output impedance by calculating the current ﬂowing in the circuit for values of VIN and VOU T . the converter is not wellposed.3. In this analysis. The fast switching limit (FSL) occurs when the resistances associated with switches. normalized with respect to the output charge ﬂow. The analysis in this chapter is targeted towards a twoport converter. 11 . 1 If these charge multiplier vectors cannot be uniquely determined. The SSL impedance is inversely proportional to switching frequency. and represents the charge ﬂow into that component. as several of them have been represented in the literature [36]. As outlined in [27].and capacitors are impulsive. we will be applying DC voltage sources to both the input (VIN ) and the output (VOU T ).
2. A 3:1 ladder topology qout/3 C1 C1 qout/3 VIN + qout/3 qout/3 VIN + C3 2qout/3 C2 C3 2qout/3 C2 qout/3 + 2qout/3 + VOUT VOUT (a) (b) Figure 2. Capacitor charge ﬂow in ladder converter.1. (a) phase 1 and (b) phase 2 12 .S1 S2 C1 S3 VIN + C3 S4 C2 S5 + VOUT S6 Figure 2.
1) where each component is the ratio of charge transfer in each element during phase 1 of the switching period to the charge delivered to the output during a full period.1.The charge multiplier vector a1 is deﬁned as: a1 = 1 1 1 1 qout q1 . the charge multiplier vectors can be obtained through network analysis using Kirchoﬀ’s Current Law (KCL) [27]. the corresponding entry in the a1 vector is positive. any vector of branch voltages that satisﬁes KVL is orthogonal 13 . is based on Tellegen’s Theorem [13] which states that for any network. By considering alternating phases. The charge from the input source ﬂows into C1 during phase 1. the ﬁrst component corresponds to the output charge ﬂow. thus these two components must sum to one. Vectors a2 through an are deﬁned analogously for phases 2 through n. qn qin /qout (2. capacitor and input components.2). The charge multiplier vector can be partitioned into output. In phase 2. The charge multiplier vectors.2) For the ladder network example of ﬁgure 2. developed here. respectively. The last component of each charge multiplier vector corresponds to the charge ﬂow into the input source. respectively: a1 = 1 1 a1 out ac ain (2. and the switching frequency are the only data needed to determine the output impedance under the asymptotic SSL condition. the capacitor characteristics. The calculation...4) In each of these charge multiplier vectors. that charge is transferred into C3. the charge ﬂow in each component can be found: a1 = 1/3 1/3 2/3 −1/3 −1/3 (2.3) a2 = 2/3 −1/3 −2/3 1/3 0 (2. the charge multiplier vectors can be obtained by inspection (in ﬁgure 2. If charge ﬂows into the positive terminal of the element during phase 1. and in all other examples encountered by the author. and is nonzero during only phase 1 in this example. In this example.
In each subperiod.i aj + c.i = aj c. where the input is shortcircuited and the output is connected to an independent dc voltage source.9) 14 . yields n n vout j=1 aj + out i∈caps j=1 j (aj vc. and noting that the input voltage source has value zero. Rather.i can be computed from the charge ﬂows. substituting j ∆vc. Ci (2. due out c.i n n j aj ∆vc. Application of Tellegen’s theorem to the switched capacitor converter. Additively combining these applications of Tellegen’s theorem. Thus. j ∆vc.i j j 1 to charge conservation in periodic steadystate. By deﬁning ∆vc. in each of its n phases (or networks). Recall that a1 + · · · + aj = 1 (as out out each aj is normalized to qout ) and that a1 + · · · + aj = 0 for each capacitor branch.i qout .7) as a1 c.i (2.i = vc. assuming linear capacitors. where v j is the respective steady state network voltage vectors in phase j.i into (2.5) yields: vout + i∈caps 1 vc.i = 0 c. yields aj · v j = 0. The charge ﬂow per period (or average current ﬂow) into the single independent source then deﬁnes the output impedance.i (2.i + ··· + an c.5) where the ﬁrst term corresponds to the constant output voltage source and the terms under the summation correspond to the capacitor branches.i ) = 0 c.8) where Ci is the capacitance value of the ith capacitor. It is of direct interest here that none of the capacitor voltages need to be explicitly j calculated for this analysis.i c.to any vector of branch currents (or equivalently charge ﬂows) that satisﬁes KCL.6) vout + i∈caps j=1 j aj ∆vc.i − vc.i = 0 c.i = 0. This theorem is applied in each of the n phases (or networks) for a nphase switched capacitor converter operating in periodic steady state. the charge on each capacitor increases proportional to its charge multiplier: j j−1 vc.i Ci qout (2.i − vc.i .i can thus be written as: j j ∆vc.i j=1 n j=1 (2. ∆vc.i = k=2 ak c.
i c. 2Ci (2. (2. This impedance can be determined by simply examining the charge ﬂow in the converter without simulation or complicated network analysis.i c.i = − k=j+1 n ak + a1 c.i c.14) Dividing (2.11) ak − c.j Additionally. c. (2.i ··· an (−a1 + a2 + a3 + a4 + · · · + an ) = 0.i c. 15 .i c.i qout .i k=2 k=j+1 Substituting (2.i c.i 2 2Ci fsw .i 2Ci 2 + · · · + an c.15) This powerful result yields a simple calculation of this asymptotic output impedance and some intuition into the operation of SC converters.i j n ak c.i c.12) Simplifying (2.13) Realizing that a1 = − a2 + · · · + an allows (2.i c.i c. The output impedance directly models the losses in the circuit due to capacitor charging and discharging.i (2.7).11) into (2.i c.i vout + i∈caps qout 2Ci n aj c.i can also be ex pressed as: j ∆vc.i c.i c.i c. ∆vc.13) to be further simpliﬁed: c.12) by expanding and combining like terms yields: vout + i∈caps qout −a1 a2 + · · · + an + a2 c.i c.i c.i c.i c. an expanded equation is generated: vout + qout i∈caps 2Ci a2 (−a1 + a2 − a3 − a4 − · · · − an ) + c.i c.i qout .i = −a1 + c.i c.i j=1 2 = 0.i 2 = 0.i c.i c.10) Averaging the two expressions yields: j ∆vc. since the capacitor voltages are cyclic in steadystate. Ci (2. (2.14) by the output current (which can be represented as the product of switching frequency and the periodic output charge) directly yields the average output impedance for the slowswitching asymptotic limit: vout = =− iout n i∈caps j=1 RSSL aj c.i a3 (−a1 + a2 + a3 − a4 − · · · − an ) + c.
A speciﬁc capacitor’s loss can be related to its voltage swing during a period.i 1 QC (vi ) = 2 QC (vi ) 1 vi − Q−1 (q)dq C (2. During 2 1 switching phase 1. These two losses correspond to the two indicated regions in ﬁgure 2. While section 2. v v1 phase 1 ∆v phase 2 v2 C q2 q1 q ∆q Figure 2. This section considers the use of nonlinear lossless capacitors in a twophase converter. 1 2 Analogously. the method can be extended to consider nonlinear capacitors.1 calculated the output impedance of a converter for linear capacitors. the energy lost during each transition can be given by the integral: 1 Ec. the loss is equivalent to that of a linear capacitor: 1 2 Eloss.3. Since the charging occurs to completion for operation in the SSL.2. A similar expression exists for the phase 2 transition. the ith capacitor is charged (or discharged) from voltage vi to vi .16) for the phase 1 transition.1.3. Energy loss due to capacitor charging In the twophase case. where QC (v) is the capacitor’s nonlinear chargevoltage characteristic.17) 16 . the capacitor is then charged from voltage vi to vi . since the total energy lost per period is simply equal to the area of the rectangle.1 Extension to NonLinear Capacitors The converter’s loss in terms of the series output impedance RSSL can be expressed in terms of capacitor loss. during phase 2.i = vi − vi 1 2 1 2 QC (vi )QC (vi ) = Ceq (vi − vi )2 (2. presumed to be invertible.
v 1 ). v3) (q2. represents the energy loss by charging and discharging capacitor i in each cycle. If linear capacitors are 17 .7). such as the one in ﬁgure 2. the linearized capacitance Ceq can be directly substituted into the output impedance equation (2. v1) (q1. is no longer a rectangle.v QC1(v) (q3. This expression demonstrates that the sum of the energy lost through the capacitors is equal to the calculated loss associated with the output impedance for a given load. some of the properties of such a converter will be examined. v 2 ) and (q 3 . v1) q (a) 1 → 2 → 3 (b) 3 → 2 → 1 q Figure 2. and then back to state 1. Since this term matches the expression in (2.4a. Nonlinear capacitor losses in a threephase converter 1 2 where Ceq is the linearized capacitance of the capacitor on the chord from vi to vi .i in (2.17) for energy loss. The integrated loss in (2. multiplied by the output charge. v 3 ) are also shown.4a.15) to ﬁnd the SSL output impedance of an SC converter with nonlinear capacitors. v2) v QC1(v) (q3. Consider a threephase converter using a highly nonlinear capacitor with characteristics shown in ﬁgure 2.4. (q 2 .16) must be used to determine the charging loss of each capacitor in each of the j clock phases. The product ac. v3) (q2. or in the opposite direction. The three operating points. v2) (q1. While the exact SSL loss of a multiphase converter using nonlinear capacitors will not be derived. given by chargevoltage pairs (q 1 .i ∆vc. This converter can either switch from state 1 to state 2 to state 3. The eﬀect of nonlinear capacitors in multiphase converters is signiﬁcantly more complex as the loss region.
The concept of the FSL impedance is introduced informally in reference [35]. the area of the loss region in ﬁgure 2. r. The circuit loss is related only to conduction loss in resistive elements.i in steadystate as they simply represent the charge ﬂow through the switches that ensure 18 . constrained by aj . the capacitor voltages are modeled as constant. However. is characterized by constant current ﬂows between capacitors.g. The duty cycle of the converter is important when considering the FSL impedance since currents ﬂow during the entirety of each phase. Additionally. This phenomenon may be used by a designer to improve the performance of a multiphase SC converter if nonlinear capacitors are used. these two methods would yield identical SSL impedances. The switch onstate impedances and other resistances are suﬃciently large such that during each phase. the charge ﬂows must follow the same pattern as in the SSL.4b is smaller than the loss region in ﬁgure 2. the fast switching limit (FSL). a duty cycle of Dj will be used for phase j for a converter with n phases. capacitor equivalent series resistance (ESR)) can be similarly incorporated into the model if desired. switching from state 3 to state 2 to state 1 and repeating yields lower SSL loss and a lower SSL output impedance. For each phase. the aj values for the onstate switches can be determined as a r.i c values for switches that are oﬀ are zero. in the nonlinear case.2 FastSwitching Limit Impedance The other asymptotic limit. the capacitors do not approach equilibrium.i Even in the FSL. Thus. In the asymptotic limit.4a. only the onstate switch resistance is considered. The aj r. The aj charge multipliers are deﬁned as the charge ﬂow through switch i during phase j. this work will use duty cycle as an input to the model. other parasitic resistance (e.15). 2. The values of aj are independent of duty cycle r.used. While previous analyses assumed a 50% duty cycle [48.i c linear combination (typically by inspection) of the capacitor charge multipliers aj . 51]. To keep the analysis general. as the sign of the charge multiplier does not eﬀect the SSL impedance in (2.
1 can be determined directly. This switch must be implemented using an active transistor.e.19) S1 qout/3 C1 C1 S3 VIN + S2 qout/3 C3 VIN + qout/3 C3 S4 C2 qout/3 C2 S5 2qout/3 + VOUT S6 + VOUT 2qout/3 (a) (b) Figure 2. from the input to output source). Switch charge ﬂow in ladder converter: (a) phase 1 and (b) phase 2 For positive power ﬂow (i.18) a2 = r 0 1/3 0 1/3 0 −2/3 (2.i converter in ﬁgure 2.5. the sign of each component of the aj vector indicates the direction of current ﬂow with respect to the blocking r voltage of a switch during phase j. The aj values for the switches in the ladder r. A positive quanity indicates the switch conducts positive current while on and blocks positive voltage while oﬀ. A negative quantity indicates the switch conducts negative current and blocks positive voltage and is suitable for diode implementation (if negative or zero 19 . The charge ﬂows in the switches during both phases are shown in ﬁgure 2. resulting in a1 and a2 vectors of: r r a1 = r 1/3 0 1/3 0 −2/3 0 (2.charge conservation on the circuit’s capacitors.5.
for all phases, and if the forward voltage drop is tolerable). For power ﬂow in the opposite direction, the switch types reverse.2 In the FSL, the current through the onstate switches is assumed to be constant. Given the charge ﬂow vector, the current in each switch during each phase is easily determined: ij = r,i 1 qr,i fsw Dj (2.20)
j where qr,i is the charge ﬂow through switch i during period j occupying a ratio Dj of the
total switching period. Substituting qr,i = ar,i qout and qout = iout /fsw into (2.20) yields: ij = r,i ar,i iout Dj (2.21)
The current through the switches is only dependent on the aj vectors, which is obtainable r by inspection, and the duration of each period. The network voltages never need to be found in this analysis, simplifying computation signiﬁcantly. The average power loss due to each individual switch is equal to the instantaneous onstate power loss multiplied by its duty cycle. Since the total loss of the SC converter in the FSL is just the sum of the switch losses, the total circuit loss is given by:
n
PF SL =
i∈switches j=1
Ri 2aj iout r,i Dj
2
(2.22)
where Ri is the onstate resistance of switch i. Since the input and output charge ﬂow in the SC converter is constrained by the conversion ratio n, all the power loss in an ideal SC converter (as analyzed here) is modeled by the output voltage drop. Thus the output impedance can be determined by equating the actual power loss of the circuit with the apparent power loss due to the output impedance. Since this power loss is proportional to the square of the output current, the FSL output impedance can be obtained by inspection:
n
RF SL =
i∈switches j=1
2
Ri j 2 (a ) . Dj r,i
(2.23)
For multiphase converters, or converters that can be conﬁgured to implement several topologies, a particular switch may block bilateral voltage and/or conduct bilateral current, and must be implemented accordingly.
20
If the total switching period is split into n equal periods, the FSL output impedance can be simpliﬁed to:
n
RF SL = n
i∈switches j=1
Ri (aj )2 . r,i
(2.24)
Analogously to the SSL output impedance in (2.15), the FSL output impedance is given simply in terms of component parameters and the switch charge multiplier coeﬃcients of each switch. The power loss due to these conduction losses is equal to the equivalent power loss through the output impedance. These two simple forms of the output impedance (given in (2.15) for the SSL and (2.23) for the FSL) can be used to provide strong guidance for the design of switchedcapacitor power converters.
2.3
Calculating Total Output Impedance
The total output impedance of a SC converter is made up of the slowswitching limit (SSL) impedance and fastswitching limit (FSL) impedance, derived in sections 2.1 and 2.2, respectively. However, these components do not directly add to form the total output impedance, as they are derived assuming diﬀerent operating conditions. When the SSL and FSL impedances are nearly equal, the converter is operating in neither the SSL or FSL, so the assumptions made for each of the two impedance calculations are not valid. In the operating region between the SSL and FSL, the dynamics of the SC converter play a large roll in determining the impedance. In each phase, the network of onstate switches (modeled as resistors) and capacitors may create very complex settling dynamics for manyelement topologies. Since the derivation of the general combined output impedance is impractical, a simple example will be evaluated, and the results will be applied to an approximation of total output impedance. The dynamics of an arbitrary SC converter are developed in section A.4. In this example, the trivial SC converter, shown in ﬁgure 2.6, will be used to examine the output impedance between the slow and fast switching limits. The two switches (each with onstate resistance R) and single capacitor (with capacitance C) guarantee a single 21
S1 R V1 +
S2 R C + V2
Figure 2.6. Trivial SC converter used for dynamic analysis settling time constant (τ = RC). Given a switching period T close to the time constant, the converter will be operating in neither the SSL or FSL, so the capacitor voltage will exhibit a waveform like the one shown in ﬁgure 2.7.
vC V1
∆v V2 T/2 T 3T/2 2T 5T/2 t
Figure 2.7. Capacitor voltage waveform of trivial converter The ripple voltage on the capacitor is directly proportional to the charge transfer of the circuit, so the ripple amplitude will be found ﬁrst. Since the circuit is symmetric and is operating at a 50% duty cycle, the waveform will be symmetric about the mean of V1 and V2 . The ripple height can be expressed as a decaying exponential: ∆v = Solving for ∆v yields: ∆v 2 − 1 − e−T /2RC = (V1 − V2 ) 1 − e−T /2RC (2.26) ∆v + V1 − V2 − ∆v 2 1 − e−T /2RC (2.25)
∆v = (V1 − V2 ) 22
1 − e−T /2RC 1 + e−T /2RC
(2.27)
Since the charge transferred between sources V1 and V2 is proportional to the ripple voltage by qout = C∆v, the timeaveraged current ﬂowing in the circuit is given by: iout = Cfsw 1 − e−T /2RC (V1 − V2 ). 1 + e−T /2RC (2.28)
Finally, the output impedance is given by the ratio of output voltage to current, and by substituting 1/fsw for the switching period T : ROU T = 1 + e−1/2RCfsw . Cfsw 1 − e−1/2RCfsw (2.29)
This form of of the output impedance clearly shows the output impedance is not a simple sum between the SSL and FSL output impedance components. Additionally, for networks with more than one mode (or time constant), this expression would become prohibitively complex. The SSL and FSL impedances can be determined by taking the limit of (2.29) as fsw approaches zero and inﬁnity, respectively: RSSL = lim ROU T = lim
fsw →0
1 + e−1/2RCfsw 1 = −1/2RCfsw fsw →∞ Cfsw 1 − e Cfsw
∂ ∂fsw lim fsw →∞ ∂ ∂fsw 1+e−1/2RCfsw Cfsw
(2.30)
RF SL = lim ROU T =
fsw →∞ 1 C
1 − e−1/2RCfsw = 4R.
(2.31)
= lim
fsw →∞
1 −1/2RCfsw − 1 − e−1/2RCfsw 2RCfsw e 1 −1/2RCfsw 2RC e
(2.32)
L’Hospital’s rule is used in (2.32) to complete the derivation. By inspection, these limits to the general output resistance match those calculated in sections 2.1 and 2.2. The exact output impedance formula may be diﬃcult or impossible to ﬁnd for many converters, so an approximation would be beneﬁcial for design purposes. Besides simply adding the two impedance components, the output impedance is often approximated as [28]: ROU T ≈
2 2 RSSL + RF SL .
(2.33)
These two approximations along with the exact output impedance for this example in (2.29) are plotted in ﬁgure 2.8. In this evaluation, R = C = 1, but the results are representative of any SC converter. The approximation in (2.33) is reasonably close to the modeled results, and will be used throughout this work. 23
2.4
Model Simpliﬁcation for TwoPhase Converters
The majority of wellknown SC converter topologies are twophase converters. Previous analysis [27, 50, 51] only considered twophase converters, so relating the analysis in sections 2.1 and 2.2 to the twophase case would be useful and beneﬁcial for the analysis later in this work. In a twophase converter, single ac and ar vectors can be deﬁned. Due to charge conservation, the two capacitor charge multipliers are equal and opposite, such that we can deﬁne: ac = a1 = −a2 c c (2.34)
Similarly, since each switch is on during exactly one phase, an ar vector can be made with the nonzero aj components. r,i Next, the SSL and FSL output impedance results can be similarly simpliﬁed given two phases and the above vector deﬁnitions. Additionally, a duty cycle of 50% will be assumed. The SSL impedance in (2.15) can be simpliﬁed to: RSSL =
i∈caps
(ac,i )2 Ci fsw
(2.35)
Similarly, the FSL impedance in (2.24) can be simpliﬁed to: RF SL = 2
i∈switches
Ri (ar,i )2
(2.36)
These equations simplify the output impedance calculations derived for multiphase converters. Where generality will be maintained in much of the work, for speciﬁc twophase converters, these terms and formulas will be used instead.
2.5
Modeling Other Converter Loads
The models in the previous sections only consider voltage sources attached to the ports of an SC converter. In real converters, the load is rarely modeled as a voltage source. Numerous additional loads can be applied, the three addressed here include capacitive, inductive 24
the impulsive charges delivered to the output capacitor do not add to zero. a small output capacitance may have a negative eﬀect on the eﬃciency of the converter due to the ripple voltage on this capacitance.and currentsource loads. but instead add to the average output current. When the charge delivered to the output is equal in each phase. If the output capacitor is suﬃciently large. The ripple at the output of a converter can have negative eﬀects on the load (if it consists of sensitive analog or digital circuits) or on the converter’s control circuitry. Furthermore. the loss is minimized if the impulses are of equal size in each phase. 2. Since the losses due to this impulsive charging are related to the square of the magnitude of each charge impulse. the load appears like a ﬁxed voltage source at the switching frequency. Output voltage ripple will be further examined in section 5. If the size of the output capacitance is limited. The discharging of the output capacitor due to the load current does not contribute additional loss since it is done adiabatically via the currentsource load. a ripple voltage will appear on the output due to the impulsive current transfer occurring in the SSL.1 Capacitive Loads The most common load of an SC converter is a constantcurrent or resistive load with a large output (bypass) capacitor. but can be reduced by using a converter with multiple interleaved phases. the linear output capacitor’s charging loss can be added to the SSL impedance calculation by using a charge multiplier of 1/j in each of the j phases. Nonuniform charge transfer increases the loss associated with the output capacitance.5. Since the output capacitor is being discharged by a current source.1. 25 . These other loads either moretypically represent frequentlyoccuring loads or alternate loads which may improve eﬃciency. The load current discharges this output capacitor linearly between the phase transitions.
9a shows a 2:1 ladder converter. a higher eﬃciency is achieved as the SSL impedance loss is eliminated. By providing this softcharging ability. the power density of a currentsource charged converter can be dramatically improved.3 Inductive Load While current source loads have the ability to greatly increase the eﬃciency of an SC converter.2. 2 (2. If the minimum of the output voltage is considered.37) This loss is directly equivalent to the SSL resistive loss. 26 . where the buck converter provides a currentsourcelike load for the SC converter. a similar eﬀect can be obtained. given by 1 ELOSS = ∆qc ∆vc . Figure 2. Reference [37] describes a twostage SCbuck converter. When linear capacitors are charged via voltage sources. However. very few real loads provide the boost in eﬃciency provided by a current source load. some instructions may yield incorrect results if the supply voltage drops below the minimum voltage during execution of that instruction. 2. by using an inductive ﬁlter on the output. in a microprocessor. the eﬃciency of this converter is identical to the voltage source load condition. a constraint is often placed on the minimum value of the output voltage to ensure proper operation of the load. By charging and discharging the ﬂying capacitor via a current source.9b. the output voltage and ﬂying capacitor voltage are shown for this converter based on both a voltagesource load (representative of a resistorcapacitor load) and a current source load. the converter could be nearly 100% eﬃcient. as eﬃciency declines with load in the SSL with voltage source charging. they lose a substantial fraction of the transfer energy in the charging process. Additionally. as in the above analysis.2 CurrentSource Load Loads that can be modeled as a current source have a promising use in SC converters.5. In ﬁgure 2.5. For example. In many applications. the SC converter’s loss decreases by 21%. If the capacitors can be charged via a series current source. However. the output exhibits signiﬁcant voltage ripple.
9.10 2 Plain Sum Quadratic Sum RC Settling SSL FSL Output Impedance 10 1 10 −2 10 0 10 10 Relative switching frequency −1 0 10 1 Figure 2. 2:1 ladder converter: (a) topology (b) waveforms for current and voltage source loads 27 . Output impedance when RSSL ≈ RF SL and approximations VIN VC1 S1 VIN/2 S2 C1 S3 VOUT Currentsource load VOUT t Voltagesource load VIN/2 S4 t (a) (b) Figure 2.8.
Since the output current is forced continuous.10.5 2 (a) (b) (c) Figure 2. b) phase 2 network. To examine the beneﬁts of using an inductive load. methods for keeping the current continuous during phase switching events must be implemented. Figures 2. This ringing can contribute to both additional losses and device stresses.2 0 0 0. an inductive load may cause problems for implementation.10b show the RC networks formed by the topology in phases 1 and 2. a timedomain analysis of a switching period will be performed using the topology in ﬁgure 2. SC converter with inductive load: a) phase 1 network. Careful design techniques must be used to prevent the ringing from destroying the transistors when using an inductive load. respectively.6 0. c) waveforms Since an inductor at the output holds the output current continuous.2 1 0. These two networks can be characterized by a diﬀerential equation speciﬁc to this topology: 1 (VIN − VOU T ) phase 1 d R 1 L i L + i L + vC = 1 dt L L (VOU T ) phase 2 L (2.8 0.5 Capacitor Voltage [V] 2RON L iL + vC  C VOUT 2RON + Inductor Current [A] VOUT 1 Time [µs] 1. it acts similar to a currentsource load. so ringing can occur during phase transitions.4 0. Despite the implementation diﬃculties.VIN vC C L iL + Voltage [V].10a and 2.38) 28 . Current [A] + 1. using an inductive load may still be beneﬁcial for certain applications. The phase dynamics are now based on a RLC network (not an RC network). Like a currentsource load.9a with an inductor and DC voltage source at the output.
The voltage change on the capacitor in a single phase is proportional to the output current during that phase.11 for three values of switch onstate resistance.43) For a given switching frequency. capacitor values and switch onstate resistance values.10c can be reproduced. In steadystate operation.d iL vC = dt C (2. (2.11.40) iL (T /2) = iL (0) (2. and is shown in ﬁgure 2. Thus.44) C 29 . and the inductor current reaches the same value at the end of each phase. and thus converter eﬃciency.10c. shown in ﬁgure 2. the output current and output resistance can be found accordingly: IOU T = fsw 4 C VIN − vC (0) .42) ROU T = VIN 2 − VOU T IOU T . The output impedance. As is clear from ﬁgure 2. it is informative to determine the eﬀect a certain inductance has on the output impedance. 2 (2. found using the preceding method. is evaluated for a range of inductance values. the capacitor voltage waveform is symmetric around VIN /2. These relationships set up two boundary conditions: vC (T /2) = VIN − vC (0) (2.41) When these boundary conditions are used to solve the diﬀerential equations for the two phase networks.39) These two RLC networks create symmetric transients during each of the two periods. there is a critical inductance (approximately 10 nH in this case) where the SSL output impedance component is eliminated for inductances above the critical value. the steadystate waveforms in ﬁgure 2. The critical inductance is given approximately by Lcrit = 1 √ 2πfsw (2.
30 .4 0. little net current can be transferred each period.15 0. The left asymptote corresponds to the voltage source load case.1 Ω RON = 0.1 0. This phenomenon must be avoided if an inductive load is used. Some topologies (especially stepup topologies) will still exhibit lossy charging or discharging as some current paths do not include the output source. Output impedance of SC converter with inductive load where fsw is the switching frequency and C is the value of the equivalent ﬂying capacitance. When the resonance frequency aligns with the switching frequency.02 Ω 10 10 Inductance [H] 10 −7 10 −6 Figure 2.05 Ω RON = 0. However.11.35 Output Impedance [Ω] 0. This analysis was performed for a speciﬁc converter topology. yielding a higher output impedance.05 0 −10 10 −9 −8 Halver. where the capacitorrelated losses are eliminated and the converter’s output impedance equals the FSL impedance. where the SSL and FSL impedance combine to form the converter’s output impedance.25 0. The right asymptote corresponds to the currentsource load case. 1 MHz C = 1 µF RON = 0. if the pitfalls of this method are avoided. Additionally.0. A similar eﬀect will occur for converters where all capacitors are charged and discharged in series with the output (typically stepdown converters). a resonance occurs between the ﬂying capacitors and the output inductor for low values of switch resistance. a smallvalue inductor at the output of a converter can be used to greatly improve converter eﬃciency.3 0.2 0.
the working voltage is the voltage it blocks during steadystate converter operation. This chapter will discuss the device choices and sizing for each individual component in the SC networks. or by the process outlined in reference [27] or in appendix 31 . the switches and capacitors of the SC converter can be independently optimized. which was not required for the output impedance analysis.and fastswichinglimit output impedance were developed in terms of the switching frequency. these working voltages can be found by inspection in most examples. will be discussed in section 3. This general and relatively simple analysis method creates an extremely powerful framework for SC converter design. including choosing the switching frequency and the relative sizing between switches and capacitors. network arrangement and component parameters. Expressions for evaluating the slow.3. The working voltage for a capacitor is the maximum voltage on the capacitor during steadystate converter operation. For a transistor (switch). System design. The optimization procedure requires knowledge of the component working voltages. Based on a costbased metric.Chapter 3 Optimization of SwitchedCapacitor Converters A method of determining the output resistance of switchedcapacitor (SC) DCDC converters was developed in chapter 2. For opencircuit operation.
the performance of a device can be represented as its energy storage as used in the application. while meeting the voltage rating constraint. Additionally. a cost metric for each device technology must be developed. To match a component with a device. the blocking voltage of some components may exceed the noload steadystate condition.1) where C is the capacitance of a test device occupying area Acap . The result is the computation of vectors denoted vc and vr for the working voltages of the capacitors and switches. this metric is constant for a given technology and component in the topology. given by vc (rated) or vr (rated) for capacitors and switches. These metrics must reﬂect the performance of a device for a given cost. Next. for a given component. each component in the circuit must be matched with a technology suitable to implement that component. and vc. The ﬁrst criteria is that the device’s blocking voltage. startup and shutdown circuitry must ensure the transient voltages do not exceed the device ratings.A. respectively.i is the voltage that the capacitor blocks in normal operation. Since capacitance scales linearly with area. in combination with a known source voltage. respectively. 3.i 2 Acap (3. This analysis is based on combining KVL constraints for the two phase topologies. Thus. the device with the largest metric. Thus. In integrated circuits. the areal energy density capacitor metric can be given by: Mcap = 2 C vc. For capacitors. a switch performance metric must be evaluated for all available device technologies and the device with the greatest metric value chosen.1 Device Cost Metrics Before the performance of a converter is optimized. 32 . but could be power loss in applications where that component is not limiting system area. must exceed the maximum blocking voltage of the component. It is important to note that during highload conditions. should be used for the design. this cost is typically die area. ratioed to the converter output voltage.
2) Msw2 = 2 G vr. the performance of a switch can be represented by its VA product. and vr. for arealimited integrated applications.i 2 2 2 CG vG. as in many IC application examples).i + CD vr. vr.2. The voltages vG. The cost of a switch can be represented as its die area.2 Component Sizing Now that a method has been developed to choose the best device technology available for each given component. the device with the largest relevant metric. When choosing a device technology for each component. and must be used in an optimization speciﬁc to that cost. should be used for a given component in the topology.i is the blocking voltage of switch i in the topology. In (3. respectively. This VA product is related to the product between a switch’s conductance and the square of its blocking voltage.2) and (3. drain and sourcebody capacitances of the test switch.3) have diﬀerent units.3) where G is the onstate conductance of the test switch of area Asw .i (3. each component must be sized relative to each other to obtain 33 .e.i and vB. drainsource and bodysource voltages. 3. CD and CBS are the linearized gate. The metrics in (3.i . given by the GV2 product. if the capacitor area dominates the switch area. the cost of a switch can be equated to the switching loss of the device. CG .i are the peaktopeak amplitudes of the gatesource. while having a suﬃcientlyhigh rated voltage.i Asw (3.Similarly. representing the units of their respective costs. respectively. as described in section 3. given by either die area or capacitive switching loss.i + CBS vB. the optimization can use one of the following two switch metrics: Msw1 = 2 G vr. and the cost of a switch.3). Thus. The VA product represents the product of the blocking voltage and FSL onstate current. If the switch area in an application is not limited (i. The switch metric represents the ratio between the performance of the switch.
34 . When optimizing over capacitances. Thus. This section develops optimality computations for the slow switching limit (SSL) and fast switching limit (FSL) impedances. one should minimize the FSL output impedance found in section 2. when optimizing over switch sizes.2. (3. To increase voltage blocking without reducing conductance.1. namely the SSL impedance found in section 2. Minimal output impedance corresponds to maximum eﬃciency for a given power delivered. Paralleling switches increases total conductance. While the optimization can be carried out for each of the metrics in section 3.the best performance for a given total device area or parasitic power loss. for sake of brevity. This GV2 constraint can be represented as: Xtot = i∈switches Gi vr. the following optimization will hold total capacitor energy storage constant using this constraint: Etot = i∈caps 1 Ci vc. The switches’ areal cost metric can be idealized to a constraint on the total VA product summed across all the switches in the converter.5) This VA product is related to the product between a switch’s conductance and the square of its blocking voltage.1 and 3. one should minimize the output impedance that is associated only with the capacitances. As proposed in section 3.2.i (rated) 2 2 . not the maximum voltage it sees during operation. and the results using each metric will be shown in tables 3. the derivation will be shown for an idealized device metric as follows. the VA product corresponds to the product between a switch’s conductance and the square of its blocking voltage as described here. Given that the losses attributed to ideal capacitors and resistive switches are reﬂected in the computation of a single real output resistance. for both discrete and integrated switches. corresponds to maximum power delivery for a given loss.1. their area (or volume) is typically related to their maximum possible energy storage. Analogously.i (rated) 2 . and dually.1. the components can now be optimized to minimize that output impedance. (3. For capacitors. whereas placing switches in series increases voltage blocking while decreasing conductance.4) The energy storage cost of a capacitor is related to its rated voltage.
switch conductance scales proportionally with transistor width and inversely with transistor length. The c.k (rated) n j=1 vc.i (rated) 2 =0 (3. In an integrated application.4) will be held constant.7) ∂L = ∂λ i 1 v 2 c. the same total GV2 constraint applies.7) sets up a proportionality between Ci . motivating the GV2 metric.i 2 Ci = 2 Etot k∈caps vc. a Lagrange multiplier method will be used for the equalityconstrained optimization problem.1 Capacitor Sizing To optimize relative capacitor sizes. aj and vc. the transistor length and nominal voltage scale linearly with process feature size.i energy constraint can be used to ﬁnd an expression for the value of each capacitor: n j=1 aj c.i 2Ci 2 +λ i 1 (v )2 Ci − Etot 2 c.i (rated) (3.i (rated) . The impedance is minimized by equating the partial derivatives of L with respect to both Ci and λ with zero: ∂L =− ∂Ci n j=1 aj c.the number of devices used scales quadratically. The SSL output impedance (2.9) 35 . Roughly.i (rated) 2 Ci − Etot = 0 (3.8) Note that equation (3.4).6) where the ﬁrst term represents the SSL output impedance (scaled by switching frequency as it does not aﬀect the minimization) and the second term incorporates the energy constraint in (3. A function L is deﬁned to perform the constrained optimization: n L= i∈caps j=1 aj c.i 2Ci2 2 +λ 1 v 2 c. The relationship in (3.i (rated) aj c.15) will be minimized while the constraint on total energy (3.k 2 (3.8) simply repeats the constraint in (3.4).2. 3. In addition.
if a highratio ladder converter is designed.i(rated) j=1 (3.k (rated) n j=1 n j=1 2 aj c. 36 . The optimized capacitor c.k 2 Etot (3.i vc. using this method to size the capacitors will yield a signiﬁcant performance advantage over the converter if uniform capacitor sizes were used instead.i (rated) ∗ RSSL = 2Etot ac. it is useful to simplify the results in (3.i values and total SSL output impedance for a twophase SC converter are given by: Ci = ac. the output impedance becomes proportional to the square of the sum of the products of voltages and charge ﬂows (VA product) of each capacitor.11) using the relation ac.k (rated)  k 2 ac. For example. the optimal capacitor energies are proportional to the product of their rated voltage and their charge multiplier coeﬃcients.i c. especially one with a large conversion ratio. the ripple voltage on each capacitor is directly proportional to that capacitor’s rated voltage.12) 1 2Etot fsw (3.The optimal energy storage rating of each capacitor is proportional to the VQ product of each capacitor: vc.i (rated) Ei = k∈caps vc.15) and (3.13) By optimizing the capacitors.i (rated)  i∈caps (3.k vc. The optimized output impedance can be calculated by combining (2.10) When the total energy is constrained.9) and (3. This optimization can improve the performance of an SC converter designed in an adhoc manner signiﬁcantly.i aj c.9): ∗ RSSL = 1 4Etot fsw i∈caps n 2 aj c.i 2 vc.i vc.i = a1 = −a2 .11) Since many commonlyused SC topologies use only two phases. In addition.
i Gi 2 +λ i∈switches Gi (vr.16) into (3.5).3.5): n L= i j=1 aj r.k (rated) n j=1 vr. Manipulating equation (3. yields an expression for the optimal conductance of each switch: 1 G∗ = ∗ = i Ri n j=1 aj r.k 2 (3. Similar to the SSL optimization case.9) makes it evident that the two optimizations are analogous.i (rated) )2 − Xtot (3.i G2 i 2 + λ vr.i (rated) 2 =0 (3. The minimization is performed by taking the partial derivative of (3.5). when combined with the GV2 constraint in (3.i 2 vr.17): ∗ RF SL = n Xtot n 2 aj r.2 Switch Sizing Like capacitors.15) Again.14) The ﬁrst term corresponds to the FSL output impedance (the omission of the factor of the number of phases denoted by n in (2.i (rated) aj r. yielding dramatic performance increases. the switches in a SC converter can be optimized. This optimization is carried out in the asymptotic fast switching limit where output impedance is directly related to switch conductance.16) Comparing the optimal conductance Gi to the optimal capacitance in (3. diﬀerentiating (3. This proportionality.2. The optimal FSL output impedance is obtained by substituting (3.15) yields a proportionality between Gi and the ratio between the switch’s charge multiplier coeﬃcient and its voltage rating.5).24) does not aﬀect the optimization) and the second term corresponds to the constraint in (3. a Lagrange optimization function L is formed to minimize the FSL output impedance while satisfying the constraint in (3.i (rated) i j=1 (3.17) 37 .i 2 Xtot k vr.14) with respect to Gi and setting it to zero: ∂L =− ∂Gi n j=1 aj r.14) with respect to λ yields the constraint in (3.
16) and the optimized FSL output impedance in (3. the optimized switch conductance in (3. the optimal FSL output impedance is related to the square of the sum of the VA products. the optimization is performed assuming limits on capacitor energy storage and switch VA product.1. If varied device technologies are used.2. The results of the optimizations. 3.18) ∗ RF SL 2 = Xtot ar.where n is the number of phases used.17) can be simpliﬁed to: G∗ = i ar.3 Optimizing Using Other Metrics Sections 3. 38 . as performed in chapter 4.2 present a method to optimize the relative capacitor and switch sizing. since it is nearly identical to the derivation in sections 3.2.1 for the capacitor optimization and in table 3. component sizing.k(rated)  k 2 (3. namely the die area and parasitic power loss metrics. and output impedance.i 1 ∗ = v Ri r. This simple form of the optimal output impedance allows the comparison of various SC converter topologies.k vr.19) Similar to the optimal SSL impedance. including the relevant constraints.1 and 3. The detailed optimization using these metrics will not be shown here. are shown in table 3.i(rated) Xtot ar.i vr.i(rated)  i . a more practical cost metric must be used. (3.2. Since most of the commonlyused topologies use two phases.2. This optimization can also be performed using the metrics developed in section 3.1 and 3. However. in an SC converter. for the twophase case.2. respectively.2 for the switch optimization.2.
i vr.k vc.k (rated)  Optimized Capacitor Values Mcap.i (rated) ) 2 2 2 CG vG.i 2 2 + CD vr.i vr.i + CB vB.i(rat) P Xtot k ar.i vr.1.i Impedance Table 3.i vc.i 1 2Etot fsw i ac.i (rated)  Conductances ∗ RF SL Msw2.k vr.i vc.i (rated) 2Etot ac.i 2 Device Metric Switch √ Msw2.i +CD vr.i (rated) 2 Areabased Cost Die area 2 Device Cost 1 i 2 Ci Cost Constraint N/A Ci∗ = P k Atot = Mcap = Ci (vc.i Optimized √ 2 G∗ i Msw1.2.i vr.k = 2 ∗ RF SL ar.i (rated) P Eloss = G.i i Gi Areabased Cost Die area 2 Lossbased Cost Parasiticcapacitance loss i Ai 2 Device Cost vr.i 2 Table 3.k vr.i +CB vB.k Optimized Output Impedance ac.i vc. Capacitor optimization summary for two device cost bases (twophase simpliﬁcations) 39 General Cost VA Product Xtot = N/A G∗ i = vr.i (rated) Cost Constraint AT OT = Msw1.i = Msw1.i vr.i ∗ RF SL = 2 Eloss i ar.i = G∗ i = ar.i (rated)  Mcap.k (rated)  k √ √ Mcap.i (rated) P Eloss k Msw2.k(rat)  ar.k (rated)  G.i ar.i (rated) ) Asw Atot k 2 i CG vG.i ar.k Optimized Output = 2 Xtot i ar.i (rated)  2 1 2Atot fsw i ∗ RSSL = ∗ RSSL = Ci∗ = ac.i(vr.i vc.i (rated)  2 √ Msw2.k vr.i (rated) P 2Atot ac.k (rated)  √ √ ar.General Cost Energy storage Etot = vc.i(vr.i (rated) ) 2Acap i Ai Device Metric ac.k vc.i(rat)  = 2 Atot i √ Msw1. Switch optimization summary for two device cost methods (twophase simpliﬁcations) .
The results shown in tables 3. and proportional to the square root of the device’s cost metric. The value of each component (capacitance or conductance) is proportional to the ratio between its charge multiplier and its rated blocking voltage. to yield an optimallyperforming converter. if an integrated SC converter was made using NMOS and PMOS transistors. PMOS devices would exhibit a device metric equal to approximately half of the metric of NMOS devices. respectively. either the areabased or lossbased cost metric can be used.1 and 3. It gives a powerful method to size the individual capacitors and switches of an SC converter and provides substantial insight into its operation and performance. As an example. but their conductances would be less than the conductance of the NMOS devices by the same squareroot of two factor. the proper ratio of capacitance to switch size must be chosen. If a diﬀerent device metric must be used to account for varying device technologies. as well as the switching frequency. if a speciﬁc cost metric is used.3 performs this optimization con 40 . First. the areabased costs and lossbased cost columns show the speciﬁc optimization details for these specialized cost metrics. each component value is proportional to the square root of that device cost metric. the optimized device values and optimized output impedance of an SC converter for speciﬁc cost metrics. Since the performance of PMOS devices is typically inferior to that of NMOS devices. The general cost columns corresponds to the idealized GV2 cost metric which can be used for technologyindependent converter designs or designs involving only a single device technology. the optimallysized PMOS devices would be larger than the NMOS devices by a factor of the squareroot of two.Tables 3. for a converter with all identical switch charge multipliers. However.1 and 3. The die area of each component (or whichever cost corresponds to the method used) is proportional to the charge multiplier and blocking voltage.2 show the form of the cost constraint. This general componentsize optimization can be extended to any device metric as desired. the speciﬁc device metrics. capacitance and conductance are analogous in the SSL and FSL calculations. Thus.2 show some general patterns about optimizing SC converters. Additionally. Section 3.
3. the SSL impedance loss is due to the power loss in the component of the output impedance related to charge 41 . Parameter ASW is the die area of the transistors. switch area and switching frequency to globally optimize the converter. This optimization method can be easily adapted for discrete implementations if desired. The ﬁrst loss. AC is the die area of the capacitors. Five loss components will be evaluated as part of this power loss. A design point consists of a speciﬁc output current IOU T and input voltage VIN . the sizing of individual capacitors and switches in an SC converter was optimized independently.sidering the systemwide tradeoﬀs between switching frequency. Such an optimization method was used in reference [33] to design a discretecapacitor converter. In this section. adjusting capacitor density to account for density rules and contact areas. including drain and source regions and accounting for appropriate design rules.3 SystemLevel Converter Optimization In section 3. 3. To examine a converter’s performance over a range of currents and for a speciﬁc output voltage. The ﬁnal design parameter is the switching frequency fSW .2. measured in hertz. Similarly. Chapter 5 goes into further depth concerning issues relating to regulation of SC converters. the switcharea cost metric will be used in this optimization. there are three design parameters. measured in mm2 . capacitor area and switch area. In integrated circuit implementations. 3. the converter’s control method must be also examined. it is also critical to choose a total capacitor area. However. The capacitor area cost metric should be used in this case.1 Converter Loss Components The optimization method will be performed by evaluating and minimizing the total power loss for the given design point with a constraint placed on capacitor area. Since switch area is measured in mm2 . total converter performance will be optimized for a given design point.
transfer.i and CB. This loss component can be represented as: PSW = fsw i∈sw 2 2 2 CG. drain and sourceground (body) capacitance of switch i.3.33).2. The basis of the SSL loss is explained in section 2.22) where CG. When the SSL and FSL losses are comparable.2.i (3.i + CD.21) With these two loss factors. Using the dieareabased cost metric.3. a simple addition of the two loss factors overestimates the total loss. gate and body capacitances of the transistors make up the switching loss of the converter. As discussed in section 2. respectively. but the multiphase results can be easily substituted.i (rated)  i Mcap.i vr.i 2 . described in section 2. Since each of the three parasitic capacitances are proportional to the total switch size. The ﬁnal three losses are associated with various parasitics in the converter. they will be combined using the Euclidean norm approximation.i (rated)  Msw1. and 42 .1.i vc. The second related parasitic loss is due to the bottomplate parasitic capacitance of the capacitors.i (3. CD. This component of loss can be expressed as: PSSL = 2 IOU T 2 1 2AC fsw ac.20) where the optimized output impedance using dieareabased cost metrics is used. The second loss is the FSL impedance loss. First. the drain. respectively. which is similarly the power loss due to the FSL output impedance. This loss is the basis of the lossbased cost metric used in the device size optimization in section 3.i vB. given by (2. in this section.i are the linearized gate.i + CB. (3. the parasitic switch loss is proportional to both switch size and switching frequency. it is important to note that they are only exact for operation in the SSL and FSL asymptotes.i vr.i . The twophase simpliﬁcation for the impedance components is used in this section.i vG. This parasitic capacitance is nonnegligible for only integrated capacitors. the FSL impedance loss can be written as: PF SL = 2 IOU T 2 ASW i ar.
3. This method of computing the ESR loss is very similar to determining the FSL output impedance in terms of weighting individual resistance components. the eﬃciency of the 43 .3.25) where RESR is an equivalent resistance equal to the sum of the parasitic resistance components.23) where MCAP is the areal capacitor density metric developed in section 3. AC and fsw ). these ﬁve losses can be evaluated over the design space (the three variables ASW . The loss is given by: 2 PESR = IOU T RESR (3. This analysis will model that loss as ﬁxed. will be lumped with the bottomplate capacitance. the top plate capacitance. the junction capacitance between the source and drain and the substrate. Atot is the total die area allocated for capacitors. if it exists.2 Numerical Optimization To ﬁnd the global optimal design.B 2 vc (rated) (3.B is the squaredaverage voltage swing of the bottomplate voltage of the capacitors.i is the area associated with capacitor i. and vcb. as it is not obviously related to capacitor or switch area. If the ratio between the parasitic capacitance and the main capacitance is denoted α. The term 2 VC. The ﬁnal loss is the equivalent series resistance (ESR) loss.B = i∈caps Ac. Based on these losses. or for MOS capacitors. the bottomplate loss can be written as: PCAP = fsw AC Mcap α 2 VC.i (3.24) where Ac.1 and 2 MCAP /vc (rated) represents the average capacitor density of the capacitors used.represents the capacitance between the physical bottom plate of a metal capacitor and the substrate. represented by: 2 VC. weighted by the square of the ratio between the current ﬂowing through each resistance to the output current.i is the magnitude of the bottomplate swing voltage of capacitor i.i 2 v Atot cb. This loss is a combination of the resistive losses in the capacitors and metal wiring. as switch resistive loss is already considered. In this model.
The optimal point is shown as the circle near the center of the plot. Thus. Since capacitor area is always a limiting factor in integrated converters. Thus. capacitor area becomes the primary constraint in converter performance. The total loss of the converter is evaluated over the twodimensional space of fsw (on the xaxis) and ASW (on the yaxis). but the equations will quickly become unmanageable unless drastic simpliﬁcations are taken. In SC converters where both the switches and capacitors are integrated onto a CMOS IC.3. In many applications. this analysis will be performed numerically via a MATLAB program developed as part of this work and described in appendix B. Figure 3. (3. a minimum output voltage is also important. The eﬃciency of an SC converter is given by: η= VOU T IOU T VOU T IOU T + PLOSS (3. but additionally provides insight into the limiting loss factor of the converter and where improvements can be made.27) Equation (3.1. so an additional constraint can be formulated based on the output impedance. In ﬁgure 3. the optimal point will always lie in the SSL loss region.26) where PLOSS is the total power loss given by: PLOSS = 2 2 PF SL + PSSL + PSW + PCAP + PESR . The point which oﬀers the highest eﬃciency is the optimal and should be the target design point. Finding the optimal point in the design space can be accomplished analytically.converter can be evaluated. as the optimal point borders the SSL loss region and the ESR loss 44 .27) uses the squareroot approximation to the total output impedance as described in section 2. when evaluated over the design space. The plots in this section are created using this MATLAB package.1 shows a contour plot of the eﬃciency of an example converter with curves of constant eﬃciency. The space is divided into ﬁve regions. the optimal capacitance is the largest available. and thus will be considered as an exogenous variable in this optimization. each denoting the region where each of the ﬁve losses is dominant. This contour plot illustrates the performance of a converter.
more capacitor area can be used to reduce the switching frequency. such as using a smaller gatelength process. and thus switch loss. Example SC converter optimization plot region. along with the SSL impedance loss region.1.2a shows the design optimization using 0. discussed in section 4.4. the metal ESR is the nextdominant loss factor. Thus. approximately twothirds of the converter loss can be associated with the switches. designed in a 130 nm CMOS process with metalinsulatormetal (MIM) capacitors. The converter’s eﬃciency can be improved by reducing switch parasitics or otherwise improving switch performance.10 −2 Switch Parasitic Loss Switch Area [mm2] 10 −3 SSL Loss ESR Loss 70% 60% Capacitor Bottom−Plate Loss 40% 10 −4 FSL Loss 20% 10% 7 8 9 10 10 Switching Frequency [Hz] 10 Figure 3. Both of these plots are based on a 3:1 seriesparallel converter.4 V (from an input of 1. Additionally. Figure 3. Figure 3. Improving the switches will only aﬀect the eﬃciency by a small amount.2 shows two example contours illustrating diﬀerent dominant losses.4 mm2 of capacitor area.2 V) at an output current of 5 mA. The converter output is nominally 0. The optimal design point is 77% eﬃcient at a switching frequency of about 60 MHz and switch area of 400 µm2 . 45 . The FSL loss and switch parasitic loss regions border the optimal point.2.
10 −2 40% 60% Switch Parasitic Loss Switch Area [mm2] 10 −3 70% SSL Loss 70% 60% Capacitor Bottom−Plate Loss 10 −4 40% FSL Loss 20% 10 7 10 Switching Frequency [Hz] (a) switchlimited design 8 10 9 10 −1 40% 60% 70% Switch Parasitic Loss 80% Switch Area [mm2] 10 −2 85% SSL Loss Capacitor Bottom−Plate Loss 85% 80% 70% 10 −3 FSL Loss 60% 40% 7 8 10 −4 10 6 10 Switching Frequency [Hz] 10 (b) bottomplate parasitic capacitance limited design Figure 3. Example eﬃciency contour plots of a 3:1 seriesparallel converter 46 .2.
or to recover some of the charge stored on this capacitance must be used. the switching frequency is reduced by a similar multiple. a fully optimal converter can be developed for any application. Besides ﬁnding the optimal design point. By ﬁrst ensuring optimal sizing of individual components and then performing a systemwide optimization. By increasing the capacitor area by a factor of 25. If eﬃciency is to be improved. methods to reduce the bottomplate parasitic capacitance of the MIM capacitors. By numerically evaluating the ﬁve primary losses of an SC converter over the design space.Figure 3.2b shows the same converter designed with the capacitor area increased to 10 mm2 . Thus. Since the eﬀects of switch parasitics are signiﬁcantly reduced. The optimal point now borders the SSL loss and capacitor bottomplate loss regions. a graphical analysis method is developed to optimize the performance of a SC converter. the graphical method develops intuition in the loss factors of a converter and methods of improving the eﬃciency. using a switch area of approximately 1200 µm2 . improving switch technology or increasing capacitor area will do little to improve converter eﬃciency. switch area can be increased to reduce the onstate resistance (FSL) loss. The optimal design is 86% eﬃcient at a switching frequency of 4 MHz. 47 .
the choice of topology has so far been presumed as given. Since the technology used to implement a converter has a large role in determining the best topology. However.Chapter 4 Comparing SwitchedCapacitor Topologies In chapter 3. Choosing the correct topology for a given application and technology is key to an eﬃcient converter. a method was developed to both optimally size the individual components of a switchedcapacitor (SC) converter and to pick the correct switch size and switching frequency for maximum eﬃciency. The performance of switchedcapacitor converters is compared to traditional inductorbased converters. 48 . a look at the compatibility between topology choice and device technology is also examined. showing that SC converters are optimal in many applications. Next. fundamental limits on the performance of both SC and inductorbased power converters are derived. Finally. yielding some powerful insight on the fundamental properties of SC converters. This chapter develops metrics to compare the performance of diﬀerent converter topologies. a number of converters in the literature are compared using the general metrics developed.
i /2 (4. a few metrics for converter performance must be developed. and for a constant output impedance. the metrics developed here use the VA productbased component optimization in section 3. as derived in section 3.i (4. the converter metrics will be evaluated in terms of the charge multipliers and blocking voltages. the FSL converter metric can be written as MF SL = 2 VOU T /RF SL 2 i∈switches Gi vr. Analogously.2. The SSL converter metric is given by: MSSL = 2 VOU T /RSSL 2 fsw i∈caps Ci vc. Each converter metric compares the power handled by a converter to the sum of the energy. Two metrics will be developed and used. The 49 . The power that can be extracted from an SC converter is inversely proportional to its output impedance. The denominator of the metric is simply the product between the switching frequency of the converter and the total energy storage of the capacitors used. proportional to the square of the output voltage.2.1) where VOU T is the nominal output voltage of the converter and RSSL is the optimized SSL output impedance of the converter.2) where RF SL is the optimized FSL output impedance of the converter.2. Since the comparisons in this chapter are not tied to a particular technology or implementation. as derived in section 3.1. and another for the fastswitching limit (FSL) where a converter’s FSL output impedance is used.4. the converter’s GV2 product is used to represent its power handling capability.2.2) is simply the sum of the GV2 products of the switches used in the converter. The denominator of (4. one for the slowswitching limit (SSL) where a converter’s SSL output impedance is examined. In order to quickly evaluate the performance of converter topologies.1 Converter Performance Metrics In order to compare the performance of diﬀerent converter topologies.or VAbased device metrics. Thus.
1 to compare the performance of various SC topologies in both the SSL and FSL. in (3. respectively.multiphase optimized output impedances. respectively.i (rated) n j=1 2 (4. Additionally.17).i for the SSL and FSL.6) i∈sw 4.3) aj c. the SSL and FSL metrics in (4.i 2 and MF SL = n 2 VOU T i∈sw vr.3) and (4. Through this substitution.5) ac.i (rated) 2 VOU T and MF SL = respectively. Since the converters compared in this section are all twophase topologies. In this section. the multiphase converter metrics can be expressed as: MSSL = 2 4 VOU T i∈caps vc. The twophase SSL and FSL converter metrics are: MSSL = i∈caps 2 2 VOU T 2 (4. These two unitless converter metrics can be used to compare SC topologies at diﬀerent conversion ratios in the switchlimited and capacitorlimted design spaces.1) and (4.i (rated) 2 (4.2). will be substituted into the SSL and FSL metrics. this metric is independent of voltage level and is just related to the charge multipliers and the ratio of the component voltages.2 Analysis of SC Topologies Two metrics have been developed in section 4.i vr.4) can be simpliﬁed for a twophase topology.i (rated) n j=1 2 2 (4. ﬁve SC topologies will be compared.4) aj r. 2 ar.11) and (3. Since the component rated voltages are typically proportional to the output voltage. the metrics can be extended towards inductorbased converters to enable a direct comparison between inductorbased and SC DCDC converters. given by (4. 50 .i vc.
By inspection.4  = 2 51 ac.2 has a charge multiplier of ac. For example. The charge multipliers and blocking voltages found in the following sections will be substituted into (4.2. (4. an input voltage of 1 V is assumed. causing capacitor C6 to have a charge multiplier of magnitude 1.7) . In phase two.5  = ac.4) to ﬁnd the SSL and FSL converter metrics. respectively. a general m : n conversion ratio is assumed. The other set of capacitors (referred to as the ﬂying capacitors) shuttle charge between the DCreferenced capacitors to equalize them.as shown in ﬁgure 4. ﬁgure 4. In the following sections. a rational conversion ratio will be considered. These capacitors establish a set of DC potentials at integer multiples of the input voltage divided by the conversion ratio denominator m.2 shows a ladder converter with a 2:5 conversion ratio. 4.7  = 1 as it shuttles charge to the output during phase one. Ladder and seriesparallel topologies can be created for a general m : n conversion. The capacitor charge multipliers will be found ﬁrst. The switches are phased alternately (oddnumbered switches in phase one. followed by the switch charge multipliers. For this analysis. C7 in ﬁgure 4. where n is an integer.6  = 1 ac.1 Ladder Topology The ladder topology [25] is based on two sets (or ladders) of capacitors.3) and (4. This method yields: ac. even numbered switches in phase two) to connect the ﬂying capacitors to the DC capacitors. One set of capacitors forms a chain from ground (including the input and output voltage sources). so the vc and vr numbers found are the ratio between the blocking voltage and the input voltage. The charge multipliers of the capacitors between the input and output can be found by inspection at each junction. so for those topologies. In general. the charge from C7 charges C6. but with an opposite sign to the charge multiplier of C7. the capacitor and switch charge multipliers and blocking voltages for each topology are found. In the analysis of the ladder topology.1. The stepup versions of the converters will be examined here.7  = ac.3  = 2. but the stepdown converters with the reciprocal conversion ratio exhibit the same performance as the stepup versions. a conversion ratio of 1:n will be considered.
1. Five common switchedcapacitor converter topologies in their stepup form 52 .C1 B S1 A S2 VIN C2 S3 C2 S4 C3 VOUT S5 S6 a) Ladder S2 b) Dickson S3 A S1 B S4 VOUT S5 VIN C3 VOUT S4 C2 S5 S7 C3 S8 S6 S9 S10 S6 S7 S8 C1 VIN S1 C1 c) Fibonacci S2 S3 VIN S1 C1 S7 S2 S3 C2 S8 S4 S5 VOUT d) SeriesParallel C3 S9 S6 S10 VIN S1 C1 e) Doubler VOUT S4 C2 S3 S5 C3 S6 S7 S8 S2 Figure 4.
If qout of charge is delivered to the output during each period. Since SC converters conserve charge between the input and output port constrained by their conversion ratio. Since the diﬀerence between input and output charge must ﬂow through ground by KCL.i  = (n − m)2 . A 2:5 ladder topology At this point.8) In general.9) Similarly. can be found. then n/m · qout of charge is pulled from the input. adding up to: 2n−3 ac. the charge multiplier for C1. the sum of the charge multipliers for all the capacitors in the topology is given by: ac. i=1 (4. the SSL converter metric for the ladder converter 53 .i  = (n − m)(m − 1). This examination yields the charge multiplier for C1.10) Thus. the last 2(n − m) − 1 capacitors have charge multipliers of decreasing integers. adding up to: 2(m−1) ac.i  = (n − m)(n − 1). the input charge can be found directly in terms of the output charge.2.2  = (5/2 − 1). i=2m−1 (4. (4. or equivalently the nominal output voltage divided by n.11) Since all capacitors block a voltage equal to the input voltage divided by m. (n/m − 1) · qout of charge must ﬂow into ground during each period.1  = ac.1). and the remaining capacitor charge multipliers can be found by inspection: ac.C1 C3 C5 C7 VOUT S1 S2 S3 C2 S4 VIN S5 C4 S6 S7 C6 S8 S9 S10 Figure 4. the ﬁrst 2(m − 1) capacitors have charge multipliers of increasing multiples of (n/m − 1). in (1. i∈caps (4. the capacitor at the lowest potential with respect to ground.
This transformation may be used to achieve a better ﬁt between the topology and the devices available.3.2. Thus. The device utilization of this transformed converter may improve. By inspection.e. N = n/m).12) where the second equality substitutes the conversion ratio N . i∈sw (4. For a 1 : n converter.1a). The switch charge multipliers between ground and the input (switches S1 through S4 in the example) must be found by examining the capacitors between the input and ground. where N = n/m. In this case. switches S5 through S10). this metric approaches an asymptote at 1/32.11): MSSL = 2 n2 2 N2 = (n − m)2 (n − 1)2 (N − 1)2 (n − 1)2 (4. This topology can be modiﬁed by transforming the capacitors by placing them in parallel instead of series.13) Since all switches also block a voltage equal to the input voltage divided by m. each capacitor will support a higher voltage but will have a smaller charge multiplier. the total converter metric will remain the same. 54 .13): MF SL = N2 n2 = 32(n − m)2 32(N − 1)2 (4. The switch charge multipliers can be determined by looking at the charge ﬂow through each switch with respect to the adjacent capacitor charge ﬂow.can be found directly from (4. depending on the technology used to implement it. the sum of the charge multipliers in the topology is given by: ar.3. This FSL converter metric will be compared to that of other topologies in section 4. For the switches between output (in the example in ﬁgure 4. This SSL converter metric will be compared to that of other topologies in section 4. their charge multipliers are simply equal to 1. if all capacitors (in each of the two ladders) are transformed such that their bottom plates share the lowestvoltage node of each ladder (nodes A and B in ﬁgure 4. the FSL converter metric for the ladder converter can be found directly from (4. At high conversion ratios. each of these switches has a charge multiplier of ar  = (n/m−1).14) where N is the conversion ratio (i.i  = 2(n − m) + 2m(n/m − 1) = 4(n − m).
(4. Similar to the ladder converter.i  = n2 n even i∈caps 4 (4.1b. In this example. and the evennumbered switches turned on during phase two. 1.2 Dickson Charge Pump The Dickson topology [14.1  = 2 ac. · · · } . the sum of the capacitor charge multipliers is given by: n2 −1 n odd 4 ac.4. the SSL metric for the Dickson converter is given by: MSSL = 8 (n − 1)2 (4. 15].19) 55 . shown in ﬁgure 4.2  = ac. capacitor C3 (the last in the sequence) has a charge multiplier of 1. the charge multipliers of the n − 1 capacitors increase by integer steps every other capacitor. so this analysis will not consider noninteger ratios.i  = i∈caps n2 − n . By examining the charge ﬂow at each node during each phase. the charge multipliers are: ac. This converter is primarily useful for 1 : n ratios (or the stepdown equivalent).2. the oddnumbered switches are turned on during phase one.3  = 1. improves upon the ladder topology by using two oppositelyphased ﬂying ladders instead of a single ﬂying ladder and a DC ladder. 66.15) For a 1 : n converter. the converter degenerates into a simple doubler stage.16) (4.18) Thus. Similar to the ladder topology. while each of the other switches blocks twice the input voltage.i vc. as it is identical to the 1:2 ladder converter. The sum of the product between the charge multipliers and blocking voltages equals: ac. so that case will not be examined here. In the case where n = 2. 2. The capacitor charge multipliers follow the following sequence.17) Capacitor C1 blocks the input voltage. starting with the capacitor closest to the input source: ac  = {1. it is straightforward to determine the charge multipliers of all the capacitors. Thus. 2. 2 (4.
placing all bottom plates of the capacitors at nodes A and B in ﬁgure 4.1c.3.3  ar.e. switches S5 through S8 have charge multipliers equal to 1.21) Given this sum.i vr.20) −1 −1 The blocking voltages of switches S1 through S5. while the other switches block twice the input voltage. This topology can be reconﬁgured by placing the capacitors in each ladder in parallel instead of series (i. By inspection. The switch charge multipliers can again be found by evaluating Kirchoﬀ’s Current Law (KCL) at the nodes of the topology. The sum of the product between the charge multipliers and blocking voltages equals: ar.1  ar.i  = 4n − 4 i∈sw (4.3. Thus.. it features a string of 56 . this version of the Dickson charge pump exhibits the same FSL and SSL metrics as the seriescapacitor version of the circuit. This FSL converter metric will be compared to that of other topologies in section 4.2  ar. but may better match a technology. Additionally. In this case. we see that the FSL metric for the Dickson converter is identical to the 1 : n ladder converter.3 Fibonacci Topology The Fibonacci topology performs the highest conversion ratio for a given number of capacitors [27] of any twophase topology. This topology is typically used to generate the programming voltage on FLASH memory chips.1b).This SSL converter metric will be compared to that of other topologies in section 4. each capacitor has a charge multiplier of 1. S2.22) By inspection. S3 and S4 are: ar. the FSL converter metric can easily be computed: MF SL = n2 32(n − 1)2 (4. the charge multipliers of switches S1. and the last switch in the chain (S8 in this example) equal the input voltage.4  = n−1 2 n 2 n−1 2 n 2 n−1 2 n 2 n−1 2 n 2 n odd n even (4. Shown in ﬁgure 4. but increasing blocking voltages.2. 4.
13.569. 5. so (4. where Fk+2 is the k + 2th Fibonacci number. For cell j in a kcell converter.26) MSSL = {8. the oddnumbered switches are turned on in phase one..25) The conversion ratio and converter SSL metrics are evaluated for the ﬁrst eight converters.j vc. The complexity of the topology prohibits a simple closedform solution. (4. 2. 0. Similarly. (4.similar threeswitch. 21. 0. starting from the input side. 8. for j ≥ 1 can be expressed as: φj − (1 − φ)j √ = {1. In this example. 0. 2. 1. and are as follows: n = {2.02. the three switches in the cell have 57 . 8. onecapacitor cells. For instance. 34.618. 3 · · · }. 0.3. Fj = (4. 3.150} The SSL metric for this converter is compared with others in section 4.376. 55} (4. 13. 1..23) For cell j in a kcapacitor converter.195.).262.24) No simpliﬁed form of this sum exists. The sum of the elementbased product of the charge multipliers and blocking voltages is k ac. with 3 capacitors. so they will be given in terms of a generalizable sequence. 0.27) The switch blocking voltages and charge multipliers are found by inspection in terms of the capacitor voltages and charge multipliers.j  = j∈caps j=1 Fj+1 Fk−j+1 . a conversion ratio of 5 is obtained. by inspection. the charge multiplier of capacitor j is Fk−j+1 . and the evennumbered switches are turned on in phase 2. Each cell is phased oppositely from the one before it. A Fibonacci converter with k capacitors exhibits a conversion ratio of n = Fk+2 . 3. · · · } 5 √ where φ is the golden ratio (φ = (1 + 5)/2 = 1. 5. its capacitor blocks voltage Fj+1 = {1. counting from the left. 2. The jth Fibonacci number.24) will be used directly to ﬁnd the SSL converter metric: MSSL = 2 2Fk+2 k j=1 Fj+1 Fk−j+1 2 (4.
With an (n − m) × m array of capacitors. 100.31) The sum of the elementbased product of the charge multipliers and blocking voltages is most easily represented as a numeric sequence computed as the product of (4. 24. 0. Figure 4.0060.3. 192. shown in ﬁgure 4. the capacitors are placed in series with the input source to transfer charge to the output. · · · } i (4.the following charge multipliers and blocking voltages: ar (j) = Fk−j+2 Fk−j+1 Fk−j+1 (4.30) and (4. 662.4 SeriesParallel Topology The seriesparallel topology.3 shows a seriesparallel 2 : 5 converter. the FSL converter metric can be easily calculated: MF SL = {0.30) vr = 1 1 1 2 2 1 3 3 2 2 . For example. 58 . the charge multipliers and blocking voltages for the 3cell converter in ﬁgure 4. 50. (4. 10.32) From this numeric sequence.1d. 0. considering the output switch has a charge multiplier of 1 and a blocking voltage of Fk .i vr.2. (4. operates by ﬁrst placing the capacitors in parallel with the input. · · · } The FSL metric for this converter is compared with others in section 4.045. 0.1c are: ar = 3 2 2 2 1 1 1 1 1 1 (4.31): ar.022.i = {4.125.29) These cellbased charge multipliers and blocking voltages can be concatenated to form the charge multiplier and voltage vectors for the converter. charging them to the input voltage (in phase one). In phase 2. 360.28) vr (j) = Fj+1 Fj+1 Fj (4. an m : n ratio converter can be created (where m < n). 0.0085.33) 4.
3.35) where N is the conversion ratio of the converter. the capacitors are connected in vertical strings of n−m capacitors to transfer charge to the output at voltage n/m.Vn φ2 v =3 r φ1 v =3 r φ2 φ1 Vm φ1 v =1 r φ2 v =1 r φ1 φ2 v =1 r φ1 v =1 r φ2 v =1 r φ1 v =1 r φ2 v =2 r φ1 φ2 v =1 r φ1 v =2 r φ2 v =4 r φ1 vr=4 vr=1 vr=1 vr=2 vr=3 Figure 4. In the second phase. this topology as posed does not guarantee capacitor voltage balancing. Additional switches must be added to make the converter wellposed. 2 m m (4. each capacitor has a charge multiplier of 1/m. but they carry zero steadystate current and are thus neglected in this section. and approaches an asymptote of 2 at large conversion ratios. 1 59 . 1 By inspection.34) The SSL converter metric can be found directly from (4. This SSL converter metric takes a simple form. This converter metric is compared with others in section 4. each capacitor supports the input voltage divided by the factor m.i vc. the sum of the charge multipliervoltage products can easily be found as: ac. As discussed in section A.i  = i∈caps 1 n−m · m(n − m) = . the m·(n−m) capacitors are connected in horizontal strings of m capacitors to charge from the input source. Thus.3.3. Since m identical strings of capacitors charge the output source.34): MSSL = 2 n2 2N 2 = (n − m)2 (N − 1)2 (4. equal to the ratio of n to m. A 2:5 seriesparallel topology In phase one.
Note that the DC capacitor on the last stage is omitted. and m(n − m + 1) switches that are on in phase two. The switches not connected to one of the rails (Vm . For stage j in a kstage doubler topology.36) Based on the uniform value of ar. while the charge multiplier of the DC capacitor is ac. By inspection.A large number of switches are needed to create an m : n seriesparallel converter. 4. however.2j  = 2k−j−1 . the FSL converter metric can be found: MF SL = n2 2 2(n − m) + n m (n − 1) 2 (4. the sum of the switches’ blocking voltages can be found: vr.2.3. Through careful accounting. Vn or ground) support one volt. There are (m + 1)(n − m) switches that turn on in phase one. For k stages (involving 2k − 1 capacitors).i  = 1/m and the voltages in (4. i∈sw (4. For each capacitor (ﬂying and DC). The oddnumbered capacitors (C1 and C3) are ﬂying capacitors that shuttle charge up the ladder.37) This FSL converter metric is compared with others in section 4. the ﬂying capacitor blocks voltage 2j−1 and the DC capacitor blocks voltage 2j . The oddnumbered switches are turned on during phase one while the evennumbered switches are turned on during phase two. each switch also has a charge multiplier of 1/m. the product between its charge multiplier and blocking voltage is equal to 2k−1 .i  = 2m(n − m) + n(n − 1). The charge multiplier of the ﬂying capacitor in stage j is equal to ac.36). 60 . The blocking voltages of all the switches in the 2:5 converter are indicated in ﬁgure 4. as each capacitor has a charge multiplier of 1/m. the converter achieves a conversion ratio of 1 : 2k . Thus.2j−1  = 2k−j .1e. some of the border switches block a higher voltage. The evennumbered capacitors are intermediate DC bypass capacitors.3.5 Doubler Topology The doubler topology consists of a number of 1:2 converter stages cascaded as shown in ﬁgure 4.
38) The SSL converter metric can easily be found from (4.41) where the conversion ratio n = 2k . Thus. In each stage. the sum of the product between the charge multipliers and the blocking voltage can easily be found: ar. for stage j in a kstage converter.40) The FSL converter metric can easily be found from (4. Thus.i  = (2k − 1)2k−1 . i∈caps (4. Thus.i  = 4k · 2k−1 . increasing eﬃciency. Thus.39) where the conversion ratio n = 2k .1. all four switches block the same voltage and carry the same amount of charge. This transformation is discussed in section 4.i  = 2k−j .3. This FSL converter metric is compared with others in section 4.38): MSSL = 8 22k+1 = 2 22(k−1) (2k − 1)2 (2k − 1) (4. This SSL converter metric is compared with others in section 4.the sum of the product between the charge multipliers and the blocking voltage equals: ac. If multiple interleaved phases are used. The switch charge multipliers and voltages can also easily be found in terms of the capacitor charge multipliers and voltages.i vr.40): MF SL = 22k 1 = 2 2 22(k−1) 8k 32 k (4.i vc.i  = 2j−1 and has a charge multiplier of ar. each switch blocks voltage vr. These metrics are equal to the VA product (or GV2 product) of each converter divided by the sum of the GV2 products of its constitutive components.3. the DC capacitors can be reduced in size. where converters with a higher 61 . 4.2.3.3 Comparison of SC Topologies The SSL and FSL converter metrics for ﬁve SC topologies were calculated in section 4. the product of charge multiplier and blocking voltage of each switch is 2k−1 . the metrics are ideal for comparing the performance of diﬀerent topologies. i∈sw (4.
37).12) has a similar dependence on the value of n.metric will perform better than ones with a lower metric. are only dependent on the conversion ratio N . not the integer numerator n or denominator m. it reaches an asymptote at 2 for large conversion ratios. analyzed for a general m : n conversion ratio. However.35). However. creating a noninteger conversion ratio does not impact eﬃciency with these topologies. such as the ladder converter in section 5. The expressions for the SSL metric for the seriesparallel topology in (4. As predicted.4. shown in ﬁgure 4. All other topologies are evaluated for integers or the available ratios. all converters degenerate into the same singlestage doubler structure. the SSL metric for the ladder topology in (4. In the SSL metric comparison. Similarly. are evaluated for halfinteger ratios. and therefore share the same metric. The ladder topology is the worst.4 compares the SSL and FSL metrics for these ﬁve topologies on a logarithmic scale.1. Figure 4.14). as seen in section 4. the relative performance of the ﬁve converters is nearly 62 .4a. Since the performance metrics of the seriesparallel and ladder topologies were found for rational conversion ratios. the FSL metric of the seriesparallel topology has a dependency on n given in (4. the FSL metric approaches a new limit inferior to the integer metric by a factor of up to two. and the FSL metric for the ladder topology in (4. but the metric does not approach a new limit. The ladder and seriesparallel converters. The SSL metric for the ladder topology approaches zero as m and n increase.4. the seriesparallel topology has the best (largest) metric of any of the ﬁve topologies. When considering these metrics. the ladder converter can be fairly eﬃcient at small conversion ratios (n/m ≈ 1). the performance of the converters diﬀers signiﬁcantly. In the FSL metric comparison. exhibiting an SSL converter metric 100times lower at high conversion ratios. At high conversion ratios. it is important to consider how these topologies perform as the conversion ratio changes. With a large denominator m. At a 2 : 1 conversion ratio. These properties of the seriesparallel and ladder converters are important to consider when making noninteger ratio converters.
4.10 1 10 SSL Converter Metric 0 10 −1 10 −2 10 −3 Ladder Dickson Fibonacci Series−Parallel Doubler 2 4 6 8 10 12 Conversion Ratio 14 16 18 20 (a) SSL metric (capacitor limited designs) 10 −1 FSL Converter Metric 10 −2 10 −3 Ladder Dickson Fibonacci Series−Parallel Doubler 2 4 6 8 10 12 Conversion Ratio 14 16 18 20 (b) FSL metric (switch limited designs) Figure 4. Comparison of SSL and FSL converter metrics 63 .
the net charge multiplier through the DC capacitors is now zero.3. The topology can be made symmetric by using two topologies. it is ten times worse than the ladder converter. The ladder and Dickson circuit both obtain the best performance. oppositelyphased. and can be made much smaller.1 Symmetrical Topologies The DC capacitors in the ladder and doubler topologies reduce the eﬃciency (and converter metrics) of those topologies by consuming die area (and contributing their charge multipliers). The topology choice must be based on technology compatibility and the converter performance metrics for the arealimiting component type. The seriesparallel topology does much worse. so the converter metrics remain the same for topologies without DC capacitors. placing the DC capacitors in parallel. it has n − m ﬂying capacitors connecting the input to the output. For the entire topology. For simplicity. only the original half of the symmetrical circuit will be analyzed. but do not act in shuttling charge between the input and output. Thus. at a conversion ratio of 1:12. the charge multipliers of capacitors C1 through C4 in the 2:5 symmetric ladder topology. In general. Since only the ladder and doubler topologies have DC capacitors. Additionally. the number of switches and capacitors double. the FSL converter metric of the transformed converters remain unchanged. During component optimization. Additionally. but each component has half the original charge multiplier. 4. with charge multipliers increasing at multiples of n/m − 1. The symmetric ladder topology now has m − 1 capacitors between the input junction and ground. only they can be transformed. Since the charge multipliers in the DC capacitors cancel each other out.opposite that in the SSL case. The corresponding DC nodes on the two converters are tied together. For example. as shown in 64 . reaching a highconversionratio asymptote at 1/32. the charge multipliers decrease as the number of components increase. their use is purely for transient absorption. by adding interleaved phases. The performance of these topologies can be improved by eliminating the DC capacitors. since no switches are eliminated. the size of these capacitors will be zero.
the SSL converter metric can be found: MSSL = 8 . Thus.2. i∈caps (4. the sum of the product between the charge multipliers and capacitor voltages equals: ac. are as follows: ac.5.45).43) Since all capacitors in the ladder converter block the input voltage divided by m.i  = 3/2 3 2 1 (4. 2 2 (4.46) These metrics are signiﬁcantly larger than their nonsymmetric counterparts in section 4. there are k ﬂying capacitors (in the halfcircuit). each with a product of the charge multiplier and blocking voltage equal to 2k−1 .44) The symmetric doubler converter is very simple to analyze. k2 (4.i vc. Symmetric 2:5 ladder topology ﬁgure 4.42) where only the halfcircuit is considered. (n − m)2 (m2 − 2m + n + 1)2 (4.45) Based on the sum in (4. Thus. 65 . For a kstage converter.i  = i∈caps (1 + n − m)(n − m) m (m − 1)(n − m) + .5.C1 φ1 φ2 φ1 φ2 C1’ VIN φ1 φ2 C2 φ1 C3 C4 φ2 φ2 φ1 φ2 C2’ C3’ φ1 φ2 φ1 VOUT C4’ Figure 4. the SSL converter metric is given by: MSSL = 8 n2 .i  = k 2k−1 . the sum of the switch charge multipliers is given by: ac. neglecting capacitors C1’ through C4’.
66 . If the increase in component count is not a problem. SSL metric improvement with symmetric converters Figure 4. Speciﬁcally. 4. the performance of the symmetric ladder equals the performance of the Dickson circuit.4 Comparison with MagneticsBased Converters One of the beneﬁts of SC converters is that they can utilize transistors and reactive elements better than traditional magneticsbased converters for many applications. this section examines a boost converter and a transformerbridge converter. considering both switch and reactiveelement utilization. In order to show how this beneﬁt can be achieved.6. For example.6 shows the SSL converter metric comparison with the symmetric ladder and doubler converter shown. this section compares SC converters to two traditional magneticsbased converters. as in an IC. whereas the nonsymmetric ladder topology was inferior by a factor of four at high conversion ratios. The performance of these two converters is improved substantially over their nonsymmetric forms. using a symmetrical topology can improve eﬃciency.10 1 10 SSL Converter Metric 0 10 −1 10 −2 10 −3 Ladder Symmetric Ladder Doubler Symmetric Doubler Series−Parallel Dickson Fibonacci 2 4 6 8 10 12 Conversion Ratio 14 16 18 20 Figure 4.
For this FSL analysis. shown in ﬁgure 4.4. Eight switches perform the switching and rectiﬁcation at an exact 50% duty cycle. The output voltage of the boost converter is given by: VOU T = VIN . 1−D (4. Also.1 Switch Comparison The boost converter has a nominal conversion ratio based on the duty cycle D. Each of these two converters will be optimized for a given conversion ratio of N = n/m to fairly compare with the SC converters. As with the switchedcapacitor circuits. shown in ﬁgure 4. where the inductor current IL is nearly constant. The transformerbridge converter. The output capacitor is used as a ﬁlter element.7.47) Thus. Traditional magneticsbased converters A boost converter. 4. To fairly compare this converter with a ﬁxedratio SC converter. deﬁned by the turns ratio of the transformer given by m : n. the conversion ratio of the circuit is simply equal to 1/(1 − D) in periodic steady state. strong continuous conduction will be assumed. with diﬀerences in the polarity of current and power ﬂow [21]. the output capacitor will be neglected in the analysis. This assumption gives the most favorable consideration of 67 .7b performs a ﬁxedratio conversion.+ L VIN + S2 D S1 + VOUT VIN + VOUT m:n  (a) boost converter (b) transformerbridge converter Figure 4. consists of two power switches and a single inductor.7a. the boost converter will be optimized for the speciﬁc conversion ratio considered. note that the buck converter is fully equivalent to the boost converter.
(4.51) Since IL is equal to the output current multiplied by the conversion ratio.50) These conductance values can be substituted into (4. the duty cycle and inductor current: 2 PSW = IL D 1−D + G1 G2 .2): MF SL = √ 1 N −1+1 2 (4. a constraint is placed on the total switch conductance: G1 + G2 = Xtot = (1 − D)2 Xtot 2 VOU T (4. Thus. an equivalent FSL impedance can be determined for the boost converter: √ RF SL 1 = Xtot D+ √ 1−D 2 (1 − D)4 .52) In terms of the conversion ratio N = 1/(1 − D). the minimal loss can be found.49) By optimizing G1 and G2 to minimize the switch conduction loss.49) to ﬁnd the optimized switchbased (FSL) power loss: PSW = 1 2 I Xtot L √ √ 2 D+ 1−D (1 − D)2 (4. (4.53) into (4.the inductorbased converter as losses associated with ripple and inductive switching are ignored.48) where the input voltage is normalized to 1. Since both switches block the output voltage of the converter. the optimal switch conductances are given by: √ √ D 1−D 2 G1 = √ (1 − D) Xtot . The optimal switch conductances are proportional to the square root of their duty cycles. (4.53) The FSL converter metric can be found by substituting (4. the FSL impedance is: RF SL = √ 1 N3 N −1+1 Xtot 2 . the total GV2 product of the switches will be constrained to Xtot during this optimization.54) N 68 . The power loss due to the switch resistance can be found in terms of the switch conductances. G2 = √ (1 − D)2 Xtot √ √ D+ 1−D D+ 1−D (4. First.
2): MF SL = 1 32 (4. Thus. The ladder converter exhibits a superior FSL metric to the other converters at all conversion ratios. At high conversion ratios. each switch has the same VA product. equal to the transformer bridge converter. Thus. uses eight switches at a ﬁxed 50% duty cycle.56) into (4. the switchbased converter metric is independent of conversion ratio.8.8 compares the FSL (switchbased) converter metrics of the boost converter and transformerbridge converter to the ladder and seriesparallel SC topologies.This FSL metric can be directly compared to the FSL converter metrics for any SC topology.57) As expected. the FSL loss impedance 2 can be determined by factoring out IOU T : RF SL = 32N 2 . The FSL converter metric can be found by substituting (4. the boost performs equally well as both SC converters. shown in ﬁgure 4. as voltage is scaled up by the conversion ratio N and the current is scaled down by N . Figure 4.7b. At a conversion ratio of two.55) Since the input current is N times larger than the output current. This comparison is shown in ﬁgure 4. The switch conduction loss can be found in terms of the input and output currents: 2 PSW = 4 IIN 8N 2 8 2 2 2 + 4 IOU T = 16 IIN + N 2 IOU T . the boost converter is substantially inferior to either the SC ladder or transformer bridge converter. 2 2 (4. The transformerbridge converter. while the output switches block N volts. 69 . Finally the FSL metric of the ladder topology asymptotically approaches the limit of 1/32. The voltage conversion is performed explicitly by the transformer turns ratio. but otherwise lags behind the ladder topology. the input switches have conductance 1/8. while the output switches will have conductance 1/8N 2 to keep the total switch GV2 equal to 1. The input switches block 1 volt. Without loss of generality. since the voltage conversion is solely handled in the transformer. assume VIN equals 1 volt.56) (4.
This performance diﬀerence is proportional to the conversion ratio at high conversion ratios. 70 . At a conversion ratio of 8. the VA product for the switches in a SC ladder approaches a ﬁxed limit in the highratio asymptote.10 0 FSL Converter Metric 10 −1 10 −2 Boost Transformer SC Ladder SC Series−Parallel 1 2 3 4 5 Conversion Ratio 6 7 8 Figure 4. This diﬀerence allows for the superior performance of SC converters at high conversion ratios. For integer conversion ratios. the ladder converter bests the boost converter by a factor of 4. However. the seriesparallel topology is only slightly lagging with respect to the boost converter. as discussed in section 4.8. the seriesparallel topology can yield excellent performance due to its excellent performance when reactive elements are considered. The total VA product of the switches in a boost converter is proportional to the power handled by the converter and the conversion ratio N . FSL metrics for magneticsbased and SC converters At large conversion ratios. However.2. the SC ladder converter exhibits superior switch utilization compared with a traditional boost converter.4.
the diﬀerences between the energy density of capacitors and inductors will be examined and incorporated into the reactancebased converter metric. For a given conversion ratio and output power. and thus may be smaller than the inductors shown here. the requirements placed upon the reactive elements for the SC and magneticsbased converters will be examined. it does not need to store any energy. 2 Additionally. inductors are more easily analyzed and examples of properlysized inductors can be found readily. However. The SSL metric of an SC converter compares the output resistance of the converter with the energy storage of the reactive elements of that converter. In each switching period. Thus. The inductor current 2 While the transformer for the transformerbridge converter has nearly the same voltsecond rating as the inductor for the boost converter. the maximum inductor current is given by: IM AX = 2 IIN = 2 IOU T 1−D (4.4. the inductor energy storage requirements will be calculated. 71 .2 Reactive Element Comparison Comparing the use of reactive elements (capacitors and inductors) between SC converters and magneticsbased converters may not be straightforward. the average inductor current must equal the average output current multiplied by the conversion ratio. but some comparisons can be made. Since both the inductor in the boost converter and the transformer in the transformerbridge converter have similar voltsecond product requirements. Thus. the inductor size is minimized by being on the edge of discontinuous conduction mode (DCM).58) where D is the duty cycle of the active switch in the boost converter. When the converter is operating at the edge of DCM. First. only the boost converter will be compared against SC converters. for a given output power (and assumed converter eﬃciency). the size of their respective magnetic components will be similar. Since the inductor current equals the input current. assuming that energy is conserved between the input and output of an eﬃcient DCDC converter. denoted IM IN and IM AX . Additionally. such that IM IN equals zero. the inductor current ramps between two values. most DCDC converters need similar energy storage requirements as the boost converter. Thus. the peak inductor current is equal to twice the average input current.4. including the isolated ﬂyback and forward converters.
60) EL. Thus.63) The energy storage for a given SC topology to obtain a certain eﬃciency can be found by substituting (4. the required output impedance for a certain eﬃciency η is given by: ROU T = (1 − η) n VIN IOU T (4.63) into (4. Thus. there is no hard relation between capacitor energy and output power.47) into (4. the maximum inductor energy can be found: 1 2 1 D (1 − D) EL.61) represents the minimum inductor energy capacity to create a boost converter with a speciﬁc duty ratio. fsw (4. the eﬃciency of an SC converter is given by: η= n VIN − IOU T ROU T n VIN (4. the converter’s output impedance increases.61) Equation (4. a ﬁxed eﬃciency (in terms of capacitorbased loss) will be assumed.59). the required inductance can be found in terms of the switching frequency: L = VIN D/fsw .M AX = D POU T .M AX = L IM AX = VOU T 2 2 fsw 2 IOU T 1−D (4.ramps from zero to IM AX over the ﬁrst half of the switching period. an eﬃciency of 95% will be assumed.1) and solving for ET OT : Etot = 2 2 VOU T /RSSL 2 POU T = . yielding lower eﬃciency.62) when considering only the SSL power loss. IM AX (4. As capacitor energy is decreased. switching frequency and output power. Thus. In this example. Since the output voltage of the converter drops with the output resistance. as that likely reﬂects the switch losses of a boost converter designed on the edge of DCM.58) and (4.64) 72 .59) By substituting (4. fsw MSSL (1 − η) fsw MSSL (4. With SC converters.
8 Table 4.0x0.4x3.3V 22 µF @ 16V 210 mF @ 50V (a) 1.8x0.9 76φx219 Dimensions WxLxH [mm3 ] Tantalum Vishay Vishay Electrolytic Kemet Kemet C.6 2.8 3.4A (b) 2.10 A 170 µH @ 1.4x1.5 29.045 0.049 0.3V 100 µF @ 6.6x0. Energy densities of common (a) capacitors and (b) inductors 73 .E.6x0.8x0.0 11x11x9.0x2.6x2.8 7.8 (0603) 1.3x2.45x1.21 A 100 µH @ 0.8φx21.3x4.3x1.1 7.D.0A 1 mH @ 2.189 Ceramic TaiyoYuden TaiyoYuden 22 µF @ 4V 1 µF @ 35V 10 µF @ 4V 100 µF @ 6.1.148 0.5x0.Type Manufacturer Capacitance Dimensions WxLxH [mm3 ] Energy Density [µJ/mm3 ] 344 1196 533 1037 45 94 172 Energy Density [µJ/mm3 ] 0.1x1.8 (0603) 1. Type Manufacturer Inductance Shielded SMT Shielded SMT Shielded Shielded Coilcraft Coilcraft Coilcraft Murata 10 µH @ 0.3x4.
However. the output power of a converter can be compared to the volume of its reactive element(s). the comparison between inductor energy storage and capacitor energy storage must consider the energy density of the particular energy storage devices.9. a comparison between the energy storage of discrete capacitors and inductors will be used. SSL metrics for magneticsbased and SC converters Equation (4.1 µJ/mm3 . An eﬃciency of 95% was assumed for the SC 74 .9. Table 4. The boost converter is compared to SC ladder and seriesparallel topologies in ﬁgure 4. By inspection. Since power inductors cannot be practically implemented ondie. Based on the reactance energy storage requirement derived in this section and the SSL converter metrics derived in section 4.64) represents the total capacitor energy to obtain a given (SSLlossbased) eﬃciency for a given topology.1 lists the energy density for a number of readily available capacitors and inductors.10 1 SSL Converter Metric 10 0 10 −1 10 −2 Boost SC Series−Parallel SC Ladder 1 2 3 4 5 Step−up Conversion Ratio 6 7 8 Figure 4. the volumetric energy density of capacitors exceeds the energy density of inductors by over a thousand times.2. The following comparison will assume a capacitor volumetric energy density of 100 µJ/mm3 and a inductor volumetric energy density of 0.
4. This average power can be broken down into two components. Both the seriesparallel and ladder topologies are advantageous to magneticsbased converters at moderate conversion ratios. These comparisons raise the question whether a fundamental maximum exists for the performance metrics of SC converters. The two comparisons performed in this chapter conclude that an appropriatelydesigned switchedcapacitor converter can have a higher power density than a traditional magneticsbased DCDC converter. dc power and ac power. not just SC converters. The average power dissipated by an element is given by: P = vi (4. due to the signiﬁcant diﬀerence in energy density between capacitors and inductors. 61] must be ﬁrst explained. 61]. several SC converters were compared with a traditional boost converter and transformerbridge converter.converters. we can derive a fundamental limit on both the SSL and FSL converter metrics in terms of the conversion ratio. as shown in ﬁgure 4. It was found that a SC topology performed superiorly to the traditional magneticsbased converters across a range of conversion ratios. The SC seriesparallel topology is an excellent candidate for IC integration as it exhibits superior capacitor utilization and adequate switch utilization. In steadystate converter operation. respectively. The performance of the SC seriesparallel topology exceeds the power density of the boost converter by nearly ﬁfty times for a given conversion ratio and physical reactance volume.8. Based on the network analysis methods developed by Wolaver in references [60.65) where v and i are the instantaneous voltage across and current through the element.5 Fundamental Performance Limits The performance of a number of SC power converters has been compared in both the SSL and FSL in section 4. and the overline represents the timeaverage of the quantity underneath the line. Additionally. each component dissipates an average power P . A few terms used in the derivation [60. 75 . These properties apply to any circuit.3. composed of an ac power Pac and a dc power PDC .
where the dc power is given by the product of average voltage and average current: Pdc = v i and the ac power is simply given by the remainder: Pac = P − Pdc = (v − v)(i − i). (4.67) (4.66)
Switches in a DCDC converter, with very low onstate resistance and nearinﬁnite oﬀstate resistance, have nearly zero average power. Switch power loss is a parasitic eﬀect in these circuits. For diodes (and other passive switches), which conduct a negative current with respect to the voltage they block, have negative dc power and positive ac power. They are designated dc active since they absorb negative dc power. Controlled switches, conducting a positive current while on and blocking positive voltage while oﬀ, have positive dc power (and thus negative ac power). These switches are designated as ac active, because they absorb negative ac power.
4.5.1
SSL Converter Metric Limit
In order to ﬁnd a limit on the SSL converter metric, a relationship between the conversion ratio and output power of the circuit and the reactances must be used. Wolaver [60, 61] states and proves the following relation: 1 2 vk ik  ≥
k∈caps
N −1 POU T N
(4.68)
where N is the current or voltage stepup ratio (whichever is greater than one), and vk and ik are the instantaneous voltage across and current through capacitor k. For an inductorbased converter, this relation applies over all reactances in the circuit. The SSL converter performance metric in section 4.1 considers lowload conditions where the capacitor voltages equal their noload steadystate voltages. The capacitor voltages will be deﬁned such that they are all positive. In this analysis, the switch voltage drops and voltage ripple on the capacitors will also be neglected. Thus, the capacitor voltages in (4.68)
76
will be assumed constant, yielding: 1 2 vk ik  ≥
k∈caps
N −1 VOU T IOU T . N
(4.69)
In periodic steadystate, the timeaveraged capacitor current is given as the sum of the charge ﬂows in the capacitor over each clock phase j, multiplied by the switching frequency:
n n
ik  =
j=1
aj qout fsw = c,k
j=1
aj IOU T . c,k
(4.70)
Substituting (4.70) into (4.69) yields a constraint for the capacitor parameters:
n
vc,k
k∈caps j=1
aj ≥ c,k
2(N − 1) VOU T . N
(4.71)
To substitute (4.71) into the SSL converter metric, this sum must be further transformed. A known relationship [10] between l1 and l2 norms can be applied to the sum of the squares of the charge multiplier vector:
n
aj c,i
2
n j=1
2 aj ≤ n c,i
n
≤
aj c,i
j=1
2
.
(4.72)
j=1
Substituting the second inequality in (4.72) into (4.71) yields:
n
vc,k
k∈caps
n
j=1
aj c,k
2
≥
2(N − 1) VOU T . N
(4.73)
After this substitution, (4.73) can be substituted into (4.5) to ﬁnd a limit on the SSL converter metric, given by: MSSL ≤ n N2 . (N − 1)2 (4.74)
where n is the number of phases in the converter and N is the (stepup) conversion ratio. Through the application of Wolaver’s analysis of dcdc converters based on graph theory, a limit on the SSL converter metric of a SC converter can quickly be obtained. This maximum limit, by inspection, equals the SSL converter metric for the seriesparallel topology for any given rational conversion ratio. Thus, the seriesparallel circuit achieves the highest performance (in the SSL) for a given amount of capacitance of any twophase SC topology. 77
4.5.2
FSL Converter Metric Limit
The fundamental limit on the FSL converter metric can be found via a similar method to the SSL converter metric limit found in section 4.5.1. Since this analysis considers DCDC converters using ideal resistive switches, it holds for all SC and magneticsbased DCDC converters. Because the FSL converter metric examines lowload conditions, the voltage drop across onstate switches is neglected. Thus, the average power absorbed (or
j dissipated) by these switches is zero. If vr,i is denoted as the blocking voltage of switch i j during phase j, then vr,i · aj = 0 for all i and j. r,i
As previously introduced, the switches in any SC converter can be divided into two disjoint sets: the dcactive set, made up of dcactive switches, and the acactive set, made up of acactive switches. Wolaver [60, 61] states and proves the following relation: −
i∈Rdc
Pdc,i ≥
N −1 POU T N
(4.75)
where Rdc is the set of dcactive switches and N is the current or voltage stepup ratio of the converter (whichever is greater than one). A corollary of (4.75) is: −
i∈Rac
Pac,i ≥
N −1 POU T N
(4.76)
where Rac is the set of acactive switches and Pac,i is the ac power absorbed by switch i. In this analysis, equal duty cycles will be assumed such that each subperiod has duration T /n, where n is the number of phases. The dc power absorbed by switch i can be written as: Pdc,i = vr,i ir,i 1 = IOU T n
n j vr,i j=1 j=1 n
aj r,i
(4.77)
j where vr,i and aj are the blocking voltage and charge multiplier of switch i in clock phase j, r,i
respectively. Since the average power of a switch is zero, the ac power dissipated by a switch is obtained by simply negating the dc power. Since dcactive switches absorb negative dc power and acactive switches absorb negative ac power, (4.66) and (4.67) can be substituted into (4.75) and (4.76), respectively. Adding the two resulting equations yields a limit on
78
the sum of the products between the blocking voltages and charge multipliers: n n 1 N −1 j IOU T POU T . vr,i aj ≥ 2 r,i n N
i∈sw j=1 j=1
(4.78)
To further simplify (4.78), the number of phases each switch is on must be known. Let ki be the number of phases that switch i is on, where 1 ≤ ki ≤ n − 1. With this deﬁnition, and the inequality in (4.72), (4.78) can be simpliﬁed to: n − ki vr,i n
n
ki
j=1
aj r,i
2
≥2
i∈sw
N −1 VOU T . N
(4.79)
To ﬁnd the maximum metric, ki must be chosen to minimize the sum. Let k ∗ be the optimal number of phases (out of n) that each switch is on, which will be optimized later. Equation (4.79) can then be simpliﬁed to:
n
vr,i
i∈sw j=1
aj r,i
2
≥2
n N −1 √ VOU T . ∗ ) k∗ N (n − k
(4.80)
Equation (4.80) can be substituted into (4.4) to ﬁnd the fundamental FSL converter metric limit: MF SL ≤ k ∗ (n − k ∗ )2 N2 4 n3 (N − 1)2 (4.81)
where n is the number of phases, k ∗ is the optimal duty cycle (number of phases for which each switch is on), and N is the stepup conversion ratio. For a general multiphase converter, k ∗ should be optimized to maximize this limit. By performing this optimization, the optimal value of k ∗ is found to equal n/3, where n is the number of clock phases. If this value is substituted into (4.81), the resulting limit equals: MF SL ≤ 1 N2 27 n (N − 1)2 (4.82)
where n is the number of phases in the converter and N is the stepup conversion ratio. For twophase converters, k ∗ = 1 by necessity, as every switch is on during one phase and oﬀ during the other. Thus, (4.81) can be simpliﬁed for twophase converters: MF SL ≤ N2 . 32 (N − 1)2 79 (4.83)
This limit for the FSL converter metric sets a fundamental limit of converter performance. The FSL converter metric for the ladder topology is equal to this fundamental limit for twophase converters. Thus, the ladder topology and its variations utilize switches better than any other twophase topology. These fundamental limits can be applied as well to all DCDC converters, showing that no magneticsbased converters could have a higher FSL metric than the ladderbased SC converter.
80
Unlike inductorbased converters. Further regulation is performed by modulating the output resistance of the converter in response to changing line 81 . minimizing current consumption by maintaining a low but constant voltage rail can improve device lifetime signiﬁcantly. the supply rail of the load can be maintained at the minimum tolerable voltage. In energyharvested or batteryoperated devices. in some applications. by maintaining a constant output voltage.Chapter 5 Regulation of SwitchedCapacitor Converters While switchedcapacitor (SC) DCDC converters transform voltages at ﬁxed conversion ratios. voltage regulation is required to ensure the devices are not overstressed with variation in line voltage. Output regulation is necessary for sensitive loads. where the conversion ratio is arbitrarily set by duty cycle. minimizing current consumption. many applications require output regulation to deliver a constant output voltage against variations in line voltage and load current. such as sensors or radios. Finally. SC converters exhibit one (or several) conversion ratios. Additionally. where small changes in output voltage can aﬀect functionality. where CMOS devices are operated close to their rated voltage.
Di Gi ). aﬀect the output resistance of the converter. and the converter’s controller must be suﬃciently fast to handle these transients. At ﬁrst look.voltage or load current vary. the output voltage of the converter will vary with the product between output current and resistance. as described in section 5. First. Out of the three variables aﬀecting output resistance (fsw . Regulation by varying output resistance is lossy. discussed in section 3. as power is dissipated to create this voltage drop.1 shows the eﬃciency of a 2:1 ratio converter using three control schemes. Since the load range of a SC converter often varies over many orders of magnitude.4. When running the converter open loop. (5. switch duty cycle Di and switch conductance Gi . by modulating output resistance. The remaining three variables.3. this method of regulation is equivalent to using a linear lowdropout regulator (LDO). Thus.1. The output of an SC converter is given by: VOU T = n VIN − iOU T ROU T (fsw . Additionally. but can be chosen from a discrete set for variableratio converters. By changing the converter’s output resistance.1) Equation (5. only switching frequency can be easily varied over the necessary range. output regulation is performed while varying frequency roughly proportional to output power. Di and Gi ). proportional to output power. in the regulation schemes discussed in this chapter. Figure 5. switching frequency fsw . The converter is optimized for operation at 1 amp (denoted by the star). the conversion ratio n is a function of topology. no additional power components are used and switching losses can be reduced. By keeping transistor switching loss. however. ﬁxing the switching frequency and switch size at the design point. eﬃciency is held nearly con82 . the output voltage is unregulated and eﬃciency decreases quickly at low power levels. the output resistance must also be modulated over many orders of magnitude in order to eﬀect voltage regulation. switching frequency will be the primary adjustment. Using simple frequency modulation (shown by the solid curve).1) shows four variables that can be used to control the output voltage of an SC converter. the converter becomes much more sensitive to quick changes in load.
100 95 90 Efficiency [%] 85 80 75 70 65 60 −3 10 No Frequency Scaling Linear Frequency Scaling Optimal Frequency and Switch Sizing 10 −2 10 Output Power [W] −1 10 0 Figure 5. 2:1 converter stant across the range of power levels.1. if practical. such as output ripple control. Additionally. the optimal design at all power levels can be obtained. 5. This control method.1. as discussed in section 5. eﬃciency increases dramatically. promises a high eﬃciency at power levels below the design point. Many analog and digital loads are very sensitive 83 . varying switch size has other advantages. only limited by the capacitor bottomplate parasitic. By dynamically adjusting both switch size and switching frequency as output power varies. At low power levels. eﬃciency at low power level is increased slightly over the eﬃciency at the design point.1 Output Ripple of Multiphase Converters The ripple at the output of an SC converter can aﬀect both the performance of the converter and the operation of the load. Since switch conductance losses are reduced by the square of output current. Eﬃciency during power backoﬀ.
it adds signiﬁcantly to the die or board area requirement of the converter. and is simply related to the converter design and output capacitance. the topology used is replicated N times and each component linearly scaled by 1/N in size. Methods of reducing the size of this capacitor are necessary for ondie converters [6]. The clock feeding each of the interleaved phases is oﬀset by an angle of 360◦ /N . The output capacitor ﬁlters the impulses of charge from the SC converter while supplying a nearconstant current to the load. the output ripple is reduced by a factor of N . In SSL operation. Since practical ripple requirements dictate that the output capacitor must be large for many applications. While the analysis in chapter 2 used a voltagesource load. Just like highperformance inductorbased converters. using interleaved phases reduces the output ripple for a given switching frequency. so the converters supplying these loads must reduce ripple as much as possible. Output ripple in an SC converter is attributable to the impulselike charge transfer in SSL operation. the output ripple amplitude will remain constant over a wide range of power levels. where a stepup converter delivers charge to the load once per period. real converters typically have resistive loads (or currentsourcelike loads) with an output capacitor. This section examines using multiple interleaved phases to reduce the ripple voltage without increasing the size of the output capacitor. This section will examine the eﬀects of using an SC converter with multiple interleaved phases on the output voltage ripple. integrated switchedcapacitor converters are infamous for their large ripple voltage levels [6]. In the worst case. For many applications. and is operating solely in the SSL. A practical limit to the number of interleaved phases used arises when the control and gatedrive power of each 84 . the converter’s peaktopeak output voltage ripple would equal: VR = IOU T . by having N interleaved phases. However. the required output capacitance would dominate the ﬂying capacitors. fsw COU T (5.2) Since the switching frequency of a converter is roughly proportional to the output current. In an SC converter using N interleaved phases.to ripple or noise on the supply rail.
In each interleaved phase. the currents ﬂow in exponentiallydecaying patterns instead of impulses. Figure 5. In examining the ripple voltage of an SC converter. that the ripple is only a few millivolts. Thus. the ripple voltage reaches an asymptote of approximately 25 mV with four interleaved phases. allowing the full SSL ripple voltage (in (5. the output voltage is regulated at a constant 0. At lower power levels. based on the optimization in section 3. a simple 2:1 stepdown converter with four interleaved phases is considered. during each phase transition. In this example. Each interleaved phase is an instantiation of the 2:1 converter each phased 90 degrees apart.9 V for a 2 V input by controlling the switching frequency. compared to the time constant τ = 2RON C. thus dramatically reducing the output ripple.2 discusses the optimal sizing of an individual interleaved phase cell. Section 8. At full load (near 1A). At the maximum switching frequency and load. an exponentiallydecaying pulse of charge is transferred from the input to the output. the interleaved current pulses average to a lowamplitude output current. At lower output loads and switching frequencies (in ﬁgure 5.3. In the operating region between the SSL and FSL. To illustrate this eﬀect.interleaved phase becomes a signiﬁcant component to the power loss. the current pulses overlap. In the fullload case where the switching period is on the order of the RC time constant.2)) to occur at the output. the switching frequency is suﬃciently fast. the converter is usually designed to operate in the region between the SSL and FSL. When multiple interleaved phases are used in this operating region.2. The time constant τ of this decay is equal to 2 RON C. Figure 5.3 shows the output voltage ripple of the 2:1 converter as the output power changes using either two. four or eight interleaved phases.2b). the currents in the four phases are nearly impulsive. as the capacitor charges and discharges through two series switches.2 shows the output voltage ripple and the current delivered to the output of the converter in each of the four interleaved phases. negatively impacting eﬃciency. the ripple voltage will be computed for an N interleavedphase converter over a range of switching frequencies. 85 . each of the four switches has an onstate resistance of RON and the single ﬂying capacitor has capacitance C. greatly reducing the amplitude of the ripple voltage at the output.
4 0.8 1 Time [µs] 1.4 0.6 1.6 Phase Currents [A] Output Ripple [mV] Output Ripple [mV] 0 0.2. T = 1 µs 30 20 10 0.2 0 0 2 4 6 8 10 Time [µs] 12 14 16 18 20 (b) Onetenth load. Current transfer and output voltage ripple waveforms of a regulated fourphase 2:1 converter 86 .2 0 0 0.2 1.4 1.2 0.4 0. T = 10 µs Figure 5.8 2 (a) Full load.6 Phase Currents [A] 0 0.6 0.30 25 20 15 10 5 0.
As current is delivered to the output capacitor more uniformly. near the maximum switching frequency.015 0. Using multiple interleaved phases can reduce the ripple at the output of an integrated SC converter.0. Additionally.02 0. Output voltage ripple of an N interleavedphase 2:1 converter set by (5. the output voltage ripple can actually be reduced by a factor of the square of the number of interleaved phases.025 0. In this region.01 0.2).005 0 −3 10 10 −2 N=4 N=8 10 Output Current [A] −1 10 0 Figure 5.045 0.03 0. At full load. 87 . output voltage ripple is reduced. where N is the number of interleaved phases. and the output voltage ripple can be empirically reduced by a factor of N 2 . the converter currents are no longer impulses but instead decaying exponentials in each period. The output voltage ripple of an SC converter has been examined in terms of the number of interleaved phases and the switching frequency. as the currents in each phase combine. The use of multiple interleaved phases reduces the size of each charge pulse and reduces the output ripple in the SSL by a factor of N . the converter operation point leaves the SSL.035 0.04 Ripple Voltage [V] N=2 0.3.05 0.
1V rail. Figure 5.4 shows a load transient for the PicoCube power conversion IC from experimental data.Both methods use voltage references and comparators to create and detect the voltage limits. Assuming the load current remains below the current delivered to the output at maximum switching frequency and minimum voltage levels. as described in section 5. By eliminating ﬁlters in the converter control. When the output voltage dips below the lower threshold. When the output voltage reaches the upper limit. the inherent ripple voltage at the output is negligible. Additionally. The PicoCube power conversion IC.12. utilizes a doublebound hysteretic control scheme. the quiescent current of the controller can be dramatically reduced. Two methods for hysteretic control will be presented. where the output is (roughly) constrained within the hysteresis bounds. To the left and right of the transient. Thus. However. and then change the state of the converter. the converter clock (about 30 MHz) shuts oﬀ. An internallygenerated reference voltage is used to create two hysteresis bounds.5. as described in chapter 7. separated by approximately 20 mV for the 2.3. and the output capacitor is discharged by the load current. and a novel lowerbound control method. using upper and lower hysteretic bounds. The simplest voltage regulation method for SC converters uses hysteresis for frequency control instead of a control method based on a smooth compensator. charging the output capacitor. A block diagram of this control scheme is shown in ﬁgure 7. Since the PicoCube IC 88 . obtaining stability and good transient response over varying load conditions using such a control method is diﬃcult and requires sensing of the output current. This converter uses small (approximately 1 nF) internal capacitors with a larger external capacitor (1 µF). the converter runs controlled. the output voltage will be held between the two hysteresis limits. and 10 mV for the 0.2 Hysteretic Feedback Methods A traditional control method for an SC converter may include a linear compensator and a voltagecontrolled oscillator (VCO). as the controller has no analog state.7 V rail. the converter can react to very fast loading and unloading transients. the traditional hysteretic feedback scheme. the converter is enabled again.
the hysteretic bound transitions are delayed to the next clock cycle before the clock changes mode.4.9 1.95 1. This operating condition represents an unusual condition when either the load current exceeds the design point or the input voltage falls below the minimum limit. In converters where the output capacitance is on the same order of magnitude as the 89 . and the converter operates at the full switching frequency of 30 MHz until the load is reduced.2 Output Voltage [V] IL = 2 µ A IL = 2 µ A 2.15 2. Doublebound hysteresis feedback for the PicoCube application uses sampled comparators instead of continuoustime comparators.85 1. the load current exceeds what the converter can deliver at full load at the lower hysteresis bound. The output voltage falls below the threshold. this operating condition can be detrimental to battery lifetime as excess gate power is consumed.3 2.1 2. Thus. A lowvoltage protection circuit should be added to any system using this type of control to prevent a rechargeable battery from being destroyed in this condition.8 −4 −2 0 2 4 6 Time [ms] 8 10 12 14 IL = 1 mA Figure 5. the exact levels of the output transitions are irregular and the ripple magnitude can exceed the set hysteretic bounds.05 2 1. In the latter case.25 2. In the center of the waveform.2.
the comparator must be very fast to prevent the output from falling signiﬁcantly below the reference.5. the output voltage can be held to a certain level while keeping ripple at a minimum. proportional to the drop across the converter’s internal output impedance. or starts up below the reference. a hysteretictype controller can be developed. + VREF 90 . First. and is highly sensitive to noise. With this simple control scheme. Lowerbound hysteretic feedback controller ﬂying capacitors.φ1 VOUT D Q D Q φ2 D Q φN Figure 5. Additional logic must detect this condition and inject a suﬃcientlyfast clock to boost the output voltage above the reference. however the output maintains regulation regardless of noise. Noise also causes an increase in the magnitude of the voltage ripple. The lowerbound hysteretic feedback method is used in the multiratio converter pre1 If a topology is chosen that transfers charge to the output during only one phase.1 which transfers charge to the output on both phases.3. This ripple can be used directly to control the converter. Second. The lowerbound feedback method does have several downsides that would have to be considered in any implementation. the output ripple can be signiﬁcant. the comparator will be stuck on. The switching frequency using this lowerbound control method is bounded only by comparator speed. a packet of charge is delivered to the output. if the output voltage remains below the reference after a switching event. If a highspeed comparator is used to detect when the output falls below a certain level.5. a symmetrical topology can be created as in section 4. shown in ﬁgure 5. During each phase transition in an interleaved phase.1 This charge packet raises the voltage on the output capacitor by a certain amount. preventing any switching action.
6 1. and the ripple amplitude gets slightly larger.1 0.04 0. 5.16 0. A discretecomponent prototype was developed with an integrated SC converter designed for handheld applications.15 0.18 Figure 5. as discussed in section 5. Waveform from lowerbound feedbackbased converter sented in section 5.02 0.1 0. the ripple frequency falls proportional to the load.2 Output Current [A] 0 0.8 Output Voltage [V] 1. 91 .06 0.12 Time [ms] 0.6 shows the output voltage ripple (with a small output capacitor) as load current varies between full load and 10% load. pulsewidth modulation and switch resistance modulation [18]. This section will develop a simpliﬁed model of an SC converter.3 System Modeling SC converters are typically regulated by varying switching frequency.4 1. This method of regulation yields inherently nonlinear dynamics which can be diﬃcult to model.4.08 0.1. At lower load currents. the ripple amplitude would have to be reduced signiﬁcantly via a larger output capacitor or multiple interleaved phases. enabling the design and simulation of control methods involving frequency modulation. Figure 5.2 1 0.14 0.6.2 0.1. For this converter to be practical for many applications.05 0 0.
although it can be varied linearly [18].nVIN + R=0 Req Ceq CO iOUT(t) Figure 5.4) where T is the duration of the switching period. This model is the simplest model including the eﬀects of both the SSL and FSL output impedance. the output capacitor is linearly discharged by the output current source and charged through the RC network made with the ﬂying capacitance and series resistance. A compensator function T = f (VOU T −VREF ) = f ( ) must be constructed to implement 92 . These equivalent component values can be found in terms of the SSL and FSL output impedances: Ceq = 1 . In this section.7.4. Idealized dynamics model for system modeling The simpliﬁed circuit model for an SC converter used in this section is shown in ﬁgure 5.3) While this model is suﬃcient for modeling the control of many converters. (5. operation in the SSL will be assumed such that the exponential factor 1 − exp (−T /2Req Ceq ) is equal to one.7. the switch resistance Req will be held constant. The model uses a single capacitor of value Ceq to shuttle charge between the input and output ports with a series resistance Req . The output is modeled as a current source with bypass capacitance CO . In addition. In each sample period. Each switching period will be modeled as a single sample in a discretetime system. the switching period T will be the primary control handle. Since the primary method of regulation for SC converters is frequency modulation. an exact dynamic model is derived in appendix A. fsw RSSL Req = RF SL . A discretetime system model can be made from this qualitative description as follows: VOU T [k + 1] = VOU T [k] + 1 −iOU T [k]T [k] + (nVIN − VOU T [k]) Ceq 1 − e−T /2Req Ceq CO (5.
if the compensator function included the output current. numerous conversion ratios.4) is nonlinear. 5. For example.4). additional considerations will have to be made for a real system. an extended lithiumion battery voltage range. bounds on the switching frequency must be used and the dynamics of a VCO must also be considered. the system can be made linear via feedback linearization. By inspecting (5.the desired control law. Since the load current can vary over many orders of magnitude.4 A MultiRatio Converter for Portable Electronics The regulation methods for SC converters discussed so far have entailed modulating the output impedance to regulate the output voltage. must be used. but are designed for neither ultrahigh eﬃciency nor the use of integrated capacitors. While f2 ( ) can be chosen to yield good dynamics. To ensure high (greater than 75%) eﬃciency over this range.8 V. For a wide regulation range. This section describes an SC converter designed for a portable electronics application where the input can vary between 2. Multiratio regulated SC converters exist in commercial parts [43. If the compensator f ( ) is in the form f ( ) = f2 ( )/IOU T . and the relation between output voltage and period in (5.The output of the converter is a constant 1. The use of a dynamic control method to regulate the output voltage requires the measurement or estimation of the output current to ensure stability and adequate performance.2 V to supply ICs fabricated in a deep submicron process. the system becomes linear in terms of the new input f2 ( ). in addition to the other regulation methods mentioned in this chapter. These methods are inherently lossy and are only eﬃcient near the optimal operating point of the converter. for correct operation. Finally.1 and 4. 93 . a diﬀerent method must be used. 32]. a limit to the slew rate of the output current must be made to ensure stability of the control system. a linear compensator function cannot guarantee stability and acceptable performance at all load levels.
V8 S16 CO8 S15 C7 S14 CO7 S13 C6 S12 CO6 S11 C5 S10 CO5 S9 S9 V5 C5 S10 S11 V6 C6 S12 S13 V7/VOUT S14 C7 S15 S16
V8 CO8 V7/VOUT CO7 V6 CO6 V5 CO5
C2 S4 CO2 S3 C1 S2 CO1 S1 S1 C1 S2 CO1 S3 C2 S4 CO2
(a) nominal topology
(b) with transformed capacitors
Figure 5.8. {5, 6, 7, 8} : 7 ladder topology stage
5.4.1
Topology Description
To perform the conversion, a twostage converter is used. The ﬁrst stage, in ﬁgure 5.8, is an eightrung ladder topology with an input multiplexer applying the input to one of four taps (denoted V5 through V8). The output is taken from V7 such that the ladder converter provides the conversion ratios 5:7, 6:7, 1:1 and 8:7. This intermediate rail is fed into the 3:1 Dickson converter, shown in ﬁgure 5.9a. By changing the way the switches are clocked, the Dickson stage can also perform a 2:1 conversion ratio. Thus, the two stages combined
94
VIN S7
Switch
S6
3:1 φ1 φ2 φ2 φ1 φ2 φ1 φ2
2:1 φ1 φ2 φ1 φ2 φ2 ON φ1
S1 S2
S5 C1 S1 S3
C2 VOUT
S3 S4 S5 S6
S2
S4
S7
(a) Dickson topology
(b) Switch phases vs. conversion ratio
Figure 5.9. 3:1, 2:1 Dickson topology stage can provide the conversion ratios 10:7, 12:7, 2:1, 15:7, 16:7, 18:7, 3:1 and 24:7. These eight conversion ratios span the necessary input range nicely. By using the twostage design, many conversion ratios can be obtained at high eﬃciency. The ﬁrst stage, while providing ﬁne regulation, remains eﬃcient since its conversion ratios remain close to 1:1. The ladder provides high eﬃciency at conversion ratios near 1:1, despite its drop in eﬃciency at higher ratios, as shown in section 4.2.1. The second stage provides the majority of the voltage conversion at relatively coarse 3:1 and 2:1 conversion ratios. However, the eﬃciency of the Dickson converter at these conversion ratios is high. The capacitors in the ladder converter (in ﬁgure 5.8a) only support a fraction of a volt as shown. To achieve a better capacitor utilization, the capacitors are transformed to span the maximum number of rungs supported by the device’s blocking voltage. The capacitor arrangement is optimized via computer iteration to determine the conﬁguration with the lowest average sum of the capacitor charge multipliers. In this arrangement, each switching node remains connected to a capacitor, and each capacitor has one terminal at the node
95
shared by S13 and S14, when supported by the capacitor’s blocking voltage. The result of this optimization is shown in ﬁgure 5.8b, and reduces the average sum of the capacitor charge multipliers by approximately 75%. The DC capacitors can also be reconﬁgured for optimal performance, but for this application, several of these topologies will be placed in parallel as interleaved phases, allowing the size of the DC capacitors to be signiﬁcantly reduced. In this manner, the ladder stage has the minimal SSL impedance for a given capacitor die area. The target process for this converter is a 65 nm CMOS process with the ability to accept a 5V I/O rail. In this design, metalinsulatormetal (MIM) capacitors are considered, as they are built in upper metal layers, and thus have low bottomplate parasitic capacitances (approximately 0.3% to 1% of the main capacitance). Native NMOS transistors are used for both topologies, and are cascoded to block the necessary voltage to implement switch S6 in the Dickson stage. The gate of the cascode transistor of S6 can be biased via a doubled version of the output voltage (i.e. a constant 2.4 V). A die area of 3 mm2 for both switches and capacitors is considered for a 100 mW application. Figure 5.10 shows the calculated eﬃciency of this converter. The eﬃciencies of the optimal points for the eight conﬁgurations are shown as circles. By performing frequency modulation, regulation is possible over the entire range of input voltage. Since the optimal eﬃciency of the 15:7 conﬁguration is below the regulation curve, it is globally inferior, and is thus never used.
5.4.2
Control Method
Performing output regulation with this converter is signiﬁcantly more complicated than a singleratio converter. An interior analog loop implements a lowerbound hysteretic control scheme to regulate the output voltage for a single conﬁguration. A block diagram of the entire control scheme is shown in ﬁgure 5.11. The remainder of the controller is a ﬁnite state machine (FSM) to control the conversion ratio, implemented in the digital domain. Analog to digital converters (ADCs) convert the input voltage and output current to digital 96
90
2:1 12:7 16:7 18:7 3:1 24:7
85
Efficiency [%]
80 10:7
15:7
75
70
65
2
2.5
3
3.5 Input Voltage [V]
4
4.5
5
Figure 5.10. Predicted eﬃciency of multiratio converter values. The output current then passes through a logarithmic ﬁlter, as only its approximate magnitude is important. The ﬁrst component of the digital control system is the frequency counter and comparator. The counter counts the number of phase transitions in a given period, set by a divided system clock. The maximum converter frequency is set by a constant maximum count. The maximum frequency comparator X6 indicates that the input voltage fell below the nominal range for the working conﬁguration (or ratio), so the conﬁguration must be changed to the next lowest conversion ratio. The comparator triggers the up/down counter to decrement the conﬁguration by one step. As the converter conﬁguration is changed to a lower conversion ratio, the sampled input voltage is written in a lookup table (LUT) indexed to the previous conﬁguration ratio and output current. The LUT stores the maximum input voltage to be used for the pretransition conﬁguration, based on the output current level. As the input voltage rises above this threshold for a given conversion ratio, the digital comparator X10 trips and triggers
97
φ1 VOUT
+
φ2 D Q
X2b
φN D Q
X2n
D
Q
X2a
Topology Config.
VREF
X1
Lowerbound feedback Conversion ratio FSM in System Clock (~ 500MHz) /2n
X4
X3
counter out
+
up/down counter
X5
reset
fMAX
decrement
X6 (limit 17)
VIN write IOUT log2
X8
+
increment
X7 X10
dIN dOUT
x y VIN LUT
X9
Figure 5.11. Controller for the multiratio converter
98
The operation of the converter. 99 .12. Some hysteresis is incorporated into the system to avoid oscillation between conversion ratios. Figure 5. The regions corresponding to each conversion ratio are shown separated by the dark lines. The control system could be improved by changing the maximum switching frequency based on output current to optimize the conﬁguration transition points.12 shows this space with input voltage on one axis and output current on the other.5 Figure 5. The conversion ratio transitions correspond to a maximum switching frequency threshold of 100 MHz. This system ensures the use of the proper conversion ratio across the input voltage range while using minimal digital resources. Three constantfrequency contours are also shown on this plot as narrow lines. considering both switching frequency and conversion ratio. Operation regions for the multiratio converter the up/down counter to switch to the next highest conversion ratio. This plot can be used to create a feedforward control system by storing the correct conversion ratio or conﬁguration in a ﬁxed twodimensional lookup table.5 Input Voltage [V] 4 4. The twodimensional lookup table X9 stores this feedforward data through online training.10 −1 10:7 12:7 2:1 16:7 18:7 3:1 Output Current [A] 10 −2 24:7 10 MHz 1 MHz 10 −3 100 kHz 10 −4 2 2. can be examined across the space of operation.5 3 3.
Thus.4.5 ohms. Since the gate drive power is included. from a few nanofarads to a few microfarads. and an FPGA board based on a Xilinx Vertex 4 for the digital portion of the control.5. while four were used for the second stage to reduce output impedance and ripple magnitude. This phenomena can be explained due to the input being applied to the lower taps of the ladder converter at these lower input voltage levels. The control was performed using a discrete opamp. Two interleaved phases were used for the ﬁrst stage. The capacitors were scaled up by a factor of approximately 500. eﬃciency and output voltage drop signiﬁcantly as the converter loses regulation.3 – 0. the eﬃciency is lower than it would be for an integrated converter due to the use of the analog multiplexers as the power switches in the converter. The onstate resistance of each of these switches varies between 0.7 V). For ease of control. At low input voltages (less than 2. All the digital components of the control were implemented using Verilog. The 100 . While the mean output voltage varies due to varying ripple amplitude.3 Experimental Results This design was not fabricated in the intended process.13 shows the eﬃciency and output voltage of running the converter at full load while varying the input voltage. the lower bound of the ripple is successfully regulated at 1. The programmable source and load were also controlled by the same FPGA. The measured eﬃciency is between 45% and 80% for the majority of the input range. The control logic occupied a very small fraction of the FPGA and could easily be synthesized and integrated onto the same IC as the power circuitry. The test board also included a programmable input regulator and programmable load resistance for automated testing. corresponding to similar switch conductance requirements. The same voltage and power speciﬁcations were maintained. the switching frequency is similarly reduced by a factor of 500 to a few hundred kilohertz. but a prototype was created using discrete components. Figure 5.2 V. suitable for this application. the National LMV7219. Maxim MAX4685 analog multiplexers were used for the power switches. This is a consequence of the lowerbound feedback mechanism working as designed.
the intermediate voltage rail sags too much at low input voltage levels to maintain regulation. This topology is a promising development in onchip voltage regulation for portable electronics.2 Output Voltage [V]. more interleaved phases would be used and if the loads are not onchip. Output voltage and eﬃciency of the multiratio converter prototype supply to the analog multiplexers is connected to the highest rail of the ladder converter. Thus. the converter is signiﬁcantly loaded by the analog multiplexer supply.6 0.4. 101 .8 0.2.13. Since the resistance between the lowest rail (V5) and the highest rail (V8) is substantial.5 Input Voltage [V] 4 4. In an integrated converter.5 5 Figure 5. Efficiency Output Voltage (lower bound) 1 0.4 0. a small external bypass capacitor would be used to further control ripple.Output Voltage (mean) 1. The prototype results illustrates the functionality of the control scheme discussed in section 5.5 3 3. The output voltage ripple in this prototype was excessive due to few interleaved phases and minimal output capacitance.2 0 Efficiency 2 2.
cheaper and more maneuverable. including a method of determining their output impedance and optimizing their performance. Their implementation necessitates higher power density batteries and actuators and lightweight. In addition. and numerous military applications. Micro air vehicles (MAVs) are small aircraft (typically less than 100 grams) which are often controlled autonomously [63].Chapter 6 HighVoltage Converters for Airborne Robotics Chapters 2 through 4 discuss the fundamentals of switchedcapacitor converters. While current MAVs are typically ﬁxedwing aircraft or gliders. By making autonomous MAVs smaller 102 . uses a switchedcapacitor converter to generate a high voltage supply for a piezoelectricbased airborne robot. their application space will increase dramatically. Insectsized devices [62] require much higher power densities than previous MAV designs. biologicallyinspired designs have been more sparse. methods to regulate the output of SC converters was discussed in chapter 5. As these devices get smaller. higheﬃciency power conversion. These devices can be used for searchandrescue. The ﬁrst example. This complete design methodology can be applied to numerous examples. ﬁre ﬁghting. described in this chapter.
an optimal design will be developed. For each topology. require actuation voltages of 150–300V. microcontroller. The analysis method in chapter 2 is used in part to determine the performance of these converters. speciﬁc discrete components are chosen to illustrate the weight. power ampliﬁers and actuators. Three power converters for this purpose are shown in ﬁgure 6. these actuators. In addition. 6. piezoelectric actuators were found to deliver the highest power density of any available actuator at the milligramlevel. While the entire energy chain has been examined in [57]. a lithiumion battery at 3. they can be used to distribute a dense wireless sensor network in hostile environments. the masses of common surfacemount type devices are shown in table 6. a RFID payload was incorporated into the wing for remote tracking. In [65].1 Comparison of Topologies for Lightweight HighVoltage DCDC Converters This section will analyze several highvoltage DCDC converter topologies in terms of eﬃciency and component mass. These two additions will increase the total weight of a properly designed 103 . By comparing various powerconversion topologies in terms of both eﬃciency and weight. Topologies for generating a high voltage at a high conversion ratio will be investigated. For analysis purposes. is a diﬃcult problem. typically made with lead zirconate titanate (PZT). charge pumps. including the speciﬁcs on the converter used for this project. This mass does not include solder or the PCB area occupied. the MicroGlider project will be described. Generating this voltage from a typical MAV power source.1. After topologies for highratio conversion have been discussed.and cheaper. ﬁght sensors. using both magneticsbased and switchedcapacitorbased solutions. However.7V.1. the power electronics design will be examined in detail in this chapter. eﬃciency and feasibility of each design. This MicroGlider has a mass of two grams with an onboard lithiumpolymer battery.
Graphs showing the capacitance and inductance density of several miniature surfacemount components are shown in ﬁgure 6. highvoltage DCDC conversion and soldered circuit board by 50–100%. The power inductors weigh more than the other components as they contain a substantial amount of ferrite or other ironbased material. it is important to know the available capacitance and inductance values for various package types and working voltages (for capacitors) or saturation current (for inductors). if an insectinspired actively ﬂying robot is made.2 requires an output power level of 10 mW. The passive actuation for the MicroGlider in section 6. it would require an electrical power of 111 mW per gram robot mass to provide lift [57].1.2.n1 : n2 L VOUT VIN + + VOUT C CLK C VIN CLK (a) boost (b) ﬂyback L VOUT VIN + CLK (c) hybridswitchedcapacitor Figure 6. However. Next. Three topologies for lightweight. Designs will be compared for a 200V output at both 10 mW and 222 mW (for a twogram aircraft). It is interesting to note that these components have approximately constant volumetric energy density across the range of blocking voltages or saturation currents. 104 .
5 Ω 5Ω 0.max 240 V 250 V 60 V 60 V RDS.on 15 Ω 3.2.5 pf Medium Voltage Zetex ZXMN6A07F Table 6.6 mg 2 mg 5 mg 2 mg 5–6 mg 15 mg 27 mg 60 mg 11 mg 27 mg 8 mg 15 mg 7 mg Notes Resistors 0603 0805 0402 Capacitors 0603 0805 0603PS Mass measured Inductors (Coilcraft) 0805PS 0603 Inductors (TaiyoYuden) 0805 SOT23 Silicon components SOT236 SOT363 mechanical diagram Mass estimated from Mass measured Table 6. Mass of common surfacemount components Voltage Level High Voltage Device Supertex TN2124 Supertex TN2425 Fairchild 2N7002 VDS. Nchannel MOSFETs in SOT23 package 105 .Category Package 0402 Mass 0.35 Ω CD 9 pF 25 pF 11 pF 19.1.
5 mg) 0.10 Capacitance [µ F] 1 Ceramic 0805 (15 mg) Ceramic 0603 (6 mg) 0.2.1 Ceramic 0402 (1.01 10 (a) 100 Inductance [µH] 16 25 Working Voltage [V] 50 Ta 10 iyo Ta −Y ud en 06 03 iyo −Y Co il ud en 08 05 cra ft 0 Co il 60 3P cra ft 0 (11 mg (27 S( 80 5P 27 S( ) mg ) mg ) 60 mg ) 1 (b) 100 Saturation Current [mA] 1000 Figure 6. Available (a) capacitors by voltage and (b) inductors by current 106 .
6. operation in discontinuous conduction mode (DCM) will be assumed. 107 . is the simplest DCDC converter which can be used to generate the 200V required to run the piezoelectric actuators.1. while the switching frequency increases. To minimize inductor mass.4) Thus. Then the inductance will be found in terms of peak current and system parameters to ﬁnd the application tradeoﬀ between inductance and peak inductor current: L=2 (VOU T − VIN ) iOU T .2) where t2 is the time that the inductor current ramps down to zero through the diode. In the chargeup phase. the converter’s switching frequency can be found. (6. (6. shown in ﬁgure 6. However. given an inductor peak energy and output power. battery voltage. it is likely that the inductor is operated near the saturation current.3) Since the output voltage in this application is much larger than the input voltage. In each switching period. by approximating VOU T − VIN ≈ VOU T .1 Boost Converter A boost converter. At a lower peak inductor current. L (6. the peak current can be found in terms of the inductance. the transistor turns on for time ton and magnetizes the inductor to a peak current. Next.3) can be transformed into a relation between load power and peak inductor energy storage: 1 2 POU T LI ≈ . charging the output capacitor. denoted Ipk .1) The charge delivered to the output can be similarly found in terms of the peak current: QOU T = 1 1 Ipk t2 = Ipk 2 2 Ipk L VOU T − VIN (6. The switch then turns oﬀ and causes the inductor current to ﬂow through the diode. 2 fsw Ipk (6. and ontime: Ipk = ton VIN . the inductor core loss may decrease such that the overall eﬃciency is higher. until the inductor current reaches zero. In this analysis.1a. 2 pk fsw (6.2) will be multiplied by fsw to obtain the output current in terms of system parameters and peak inductor current. it may be more eﬃcient to run the converter at a lower peak current.
Since the inductor loss and onstate resistance loss are both resistive. the drainsource capacitance loss of the MOSFET can be represented as: 2 PCAP = fsw CD VOU T (6. The onstate resistance loss and drainsource capacitance loss of the MOSFET depends on choice of MOSFET and the other design parameters.To calculate eﬃciency.2 shows a number of high.9) since the MOSFET’s blocking voltage is approximately equal to the output voltage. the peak current is kept minimal (presuming Ipk > 2iIN to maintain DCM operation). the converter losses must be analyzed. MOSFET and switching frequency.6) By realizing the input current iIN is the timeaveraged inductor current. (6.and mediumvoltage MOSFETs for use in these converters. The inductor ESR loss of the inductor will also be considered.7) Likewise. only the highvoltage switches can be used for this application. 3 (6. 3 (6.5) where IL is the inductor current.8) (6. Table 6.5) can be integrated: PRES = fsw R ton + t2 ton ton 0 t ton 2 Ipk dt = 1 2 fsw (ton + t2 ) R Ipk . Since the boost converter places a large blocking voltage requirement on the power switch (200V). the 108 . By choosing the highest available inductance in a series. 2 A ﬁnal expression for the resistive power loss is then given by: PRES = 2 iIN Ipk R. Three losses will be considered in this exploratory analysis. For each inductor type and load. they will be considered together as a lumped resistance R: ton +t2 PRES = i2 R = fsw R 0 IL (t)2 dt (6. The two primary losses stated here must be optimized by choosing the inductor. Since the inductor current ramps up linearly to Ipk over time ton . the input current can be written as: 1 iIN = Ipk fsw (ton + t2 ) .
However.3 shows the eﬃciency of these designs.78µH 763 kHz 860 mA 824 mW 21. none of the potential designs result in an acceptable eﬃciency at an acceptable mass.3 mw 34. such that the conversion 109 . To improve the eﬃciency. Eﬃciency of singlestage boost converter optimal switch type is chosen and peak current optimized to yield the optimal design. By choosing the mosteﬃcient design with a suitable component weight (including control components).1 % TN2124 3.3. after inspecting the designs. it has a very large VA product. which results in large switch dissipation.7% Table 6.0 % TN2124 47µH 75.6 kHz 75 mA 30 mW 25. converters that stress the power switches less will be utilized.2% TN2124 330µH 17 kHz 60 mA 10 mW 49. Table 6. the optimal design can be obtained. the power loss and eﬃciency are evaluated.9µH 456 kHz 529 mA 492 mW 30.9% TN2124 10 µH 312 kHz 80 mA 115 mW 8.TaiyoYuden Power Level 0603 (11 mg) TaiyoYuden 0805 (27 mg) Coilcraft 0603PS (27 mg) Coilcraft 0805PS (60 mg) 10 mW Switch Type Inductance Switching frequency Peak Current Power Loss Eﬃciency 220 mW Switch Type Inductance Switching frequency Peak Current Power Loss Eﬃciency N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A TN2124 0. Since the power switch must conduct the input current but block the output voltage.2% TN2124 47µH 42 kHz 100 mA 19. At this optimal design point. Two boost converter stages could be cascaded.
While the switch stresses are greatly reduced in a ﬂyback converter. the reset voltage of the transformer equals 4 V. With a turns ratio of 1:50. The transformation ratio n2 /n1 greatly lessens the switch stresses on the primaryside switches. is a transformerbased indirect converter. allowing the use of a 20 V switch. the MicroMetals T1426A toroidal core will be used.70 mm. the power switch nominally blocks a voltage equal to VIN +(n1 /n2 ) VOU T . with a mass of 77mg. respectively.43 and 1. When the reset voltage is added to the battery voltage.1. In this application. Winding the transformer also presents great diﬃculty as the inner aperture is very small and the turns ratio is very large. An additional margin must be included in the switch voltage rating due to eﬀects of the transformer’s leakage inductance. as shown in ﬁgure 6. the current in the magnetizing inductance of the transformer ramps up linearly at a rate proportional to the input voltage. The ungapped core exhibits a singleturn inductance of 12. the design of the transformer becomes the largest issue in implementation. the magnetizing inductance current ramps down through the transformer to the output. 6.2 Flyback Converter A ﬂyback converter.5 nH and outer and inner diameters of 3. A ﬂyback converter and a hybrid switchedcapacitor converter will be used to lower the switch stresses while using only a single magnetic element. In this conﬁguration. While this method may yield increased eﬃciency. When the power switch is on. the mass of the additional inductor and control circuitry would make the converter prohibitively heavy. the smallest available cores must be used. Power inductors are typically customwound for a particular application from commerciallyavailable magnetic cores. but their suitability for power applications is unknown. When the switch turns oﬀ. the power switch blocking voltage is approximately 8 V (discounting the eﬀect of the leakage inductance). The number of turns on the primary is computed 110 .ratio of each converter is modest. and an output voltage of 200V. allowing a greater eﬃciency. For this explorative calculation. Smaller cores are available for RF and EMI applications.1b.
The ﬂyback converter achieves a very high eﬃciency when compared with the boost converter.2 can be adjusted. as the magnetic component is now ﬁxed. This ﬂux limit corresponds to a primary current limit of 0.10 mW Switch Type Switching frequency Peak current Power loss Eﬃciency ZXMN6A07F 13 kHz 550 mA 0.3 mW 92. The total mass of these two windings equals 108 mg.033 mm. The eﬃciency of the ﬂyback converter. using this transformer. although it would be a nontrivial aspect of any implementation. However. as well as transformer core and copper losses. the ﬁeld will be restricted to 0. dominating the mass of the converter. the same method as the boost converter will be used. along with the peak current. However. with a total resistance of 290 mΩ.4. the primary winding is speciﬁed with AWG 36 wire.2 T. the optimal peak current will likely be less than this limit.7 % Table 6. the manufacturing of this transformer would be extremely diﬃcult. However. The maximum magnetic ﬁeld for the toroid material is 0.4. with a resistance of 21.96 A.6 tesla before signiﬁcant saturation occurs. 111 . Switch resistive and capacitive losses are considered. To ﬁnd the optimal operating conditions for the converter. is shown in table 6. Reﬂecting this impedance to the primary yields 96 mΩ.79 mW 92. The resistance of the secondary would equal 240 Ω. However. The feasibility of winding such a transformer will be neglected. as was the case for the boost converter. at a 50% packing factor. AWG 48 wire needs to be used for the secondary. For a modest 20 primary turns. for eﬃciency. If 75% of the aperture is used for the secondary. only the switches in table 6.7 % 220 mW ZXMN6A07F 289 kHz 550 mA 17. Eﬃciency of ﬂyback converter using custom transformer by optimizing power loss using a reasonable switching frequency. 1000 secondary turns are necessary. Similarly.8 Ω/m. requiring very ﬁnegauge wire. the secondary wire must have a diameter less than 0.
6.1 will be used here when considering the devices in table 6. Additionally.3. For the lowpower converter. A pure switchedcapacitor circuit could be designed to do the conversion. shown in ﬁgure 6.C1 L C3 C5 VOUT VIN + CLK C0 C2 C4 C2(N1) Figure 6. Hybrid switchedcapacitor boost converter and its mass should be reduced further for practicality. uses a boost converter to generate an intermediate voltage (about 30 V) and to drive a passive. the eﬃciency of the boost converter and SC converter will be analyzed independently. 112 . The hybrid switchedcapacitor converter combines the low switch stress of the ﬂyback with use of only oﬀtheshelf components.3.5.3 Hybrid SwitchedCapacitor Boost Converter The hybrid switchedcapacitor converter was developed to reduce the switch stresses of the boost converter’s MOSFET while maintaining use of oﬀtheshelf components in a single converter.1. The hybrid SCboost converter. the boost converter will be examined with a standard resistive load.1. the mass and power consumption of the necessary control circuitry have not been considered. For simplicity.3. a prohibitively large number of components would be needed. the 0805PS series will be used for the highpower case.1.2. After optimizing the boost converter at the two power levels. but as the conversion ratio is large. Since this converter is impractical for prototyping (and likely manufacture). The method presented in section 6. Similarly. an alternative is considered in section 6. the design parameters and results are shown in the top half of table 6. First. the Coilcraft 0603PS inductor series will be used. diodebased charge pump to generate the desired 200 V output.2 and ﬁgure 6.
By adding the squares of these components. Due to the lower switch stresses of this design. there are two chains of N − 1 capacitors. the cascaded diode voltage drop and the diode junction capacitance loss. as that assumption yields the least mass. the BAS40DW04 diode from Diodes.1: RSSL = i∈caps (ac.11) where N is the number of stages and C is the value of each of the capacitors in the converter. The structure of the ladder topology allows each capacitor to only support the input voltage. the FSL impedance model cannot be used. The rectangular waveform across this diode allows the charge pump to operate without any active or controlled components. the SSL output impedance can be found: RSSL = 1 2N 2 − 3N 2 + N C fsw 3 (6. However. the capacitors near the input can be doubled up in parallel to approximate the optimal capacitor sizings from section 3. For this converter. as found in section 2.1. Thus. and fsw is the switching frequency of the boost converter since the charge pump operates at the same frequency as the boost converter. Next. although for increased power capability. Next. Three losses will be considered: the SSL output impedance loss. C is the value of each capacitor. the boost converter exhibits high eﬃciency with modest part mass.1.The lowratio boost converter stage is signiﬁcantly more eﬃcient than the highratio boost converter in section 6. For an N stage ladder converter. diode loss will be considered. in this case 30V. each with charge multipliers increasing by integers from 1 to N − 1. The SC converter component of this hybrid converter is a ladder converter attached to the boost converter across the rectifying diode. As diodes are modeled as voltage drops. not resistive drops. the eﬃciency SC converter stage will be considered.10) where N is the number of stages.i )2 C fsw (6. we will consider all capacitors to be identical.1. instances of the same part can be used for all capacitors.2. inc. is used as it supplies four seriesconnected diodes in a 6pin 7 mg 113 . The SSL impedance of the ladder converter is proportional to the sum of the squares of the capacitor charge multipliers.
5.4% 10nF 0402 BAS40DW04 8 207 V 79.9% ZXMN6A07F 10 µH 45 kHz 220 mW ZXMN6A07F 3.6% 47nF 0603 BAS40DW04 7 199 V 90.7% 176 mg Table 6.6 mW 86.5 mW 89.2% 67.10 mW Switch Type Inductance Switching frequency Boost Peak current Power loss Eﬃciency Capacitor Type Diode type Switchedcapacitor Number of stages Output Voltage Eﬃciency Eﬃciency Total Component mass 85 mg 210 mA 1.3 µH 485 kHz 580 mA 25. Eﬃciency of hybrid boost converter 114 .1% 80.
as it provides an output closest to 200 V. The eﬃciency of the converter can be increased by increasing the switching frequency (by decreasing the inductance value of the boost converter). This approximation overestimates the loading due to the diode capacitances. Capacitor C1 in ﬁgure 6. For the BAS40DW04 diode. Since in each phase. the diode junction capacitance loss originates from each diode turning on and oﬀ each period. Table 6. the diode forward drop does not yield a decreasing set of capacitor voltages.5. This loss is incorporated into the numbers in table 6. for each switching period. In these calculations.SOT363 package. it has a cumulative junction charge of 52 pC at 30 V. The output resistance is adjusted to yield 10 mW output power at each number of stages. The loading of the diode junction capacitances is incorporated into the model as an additional output current with similar power consumption. 220 mW boost converter. and is thus a worstcase bound.3 is charged from capacitor C0 with a single diode drop.6. the onstate diodes conduct the same current in the same direction. The mass of the switchedcapacitor converter adds only 50 mg to the mass of the 35 mg. These Schottky diodes exhibit a breakdown voltage of 40 V and forward voltage of 0. The total converter eﬃciency is shown in table 6.6 shows the output voltage and eﬃciency of the ladder converter for a range of stages. Thus. 10 mW boost converter and 108 mg to the 68 mg. eight stages will be used. Instead. Finally. For this application.56 nJ of energy is lost per diode. the two chains of capacitors equalize through the diodes. The implemen 115 . 1. charging and discharging the parasitic junction capacitance. the incremental voltage gain decreases and the eﬃciency drops.0 mA. each capacitor in the opencircuit case nominally equilibrates to the output of the boost converter minus a single diode drop. The hybrid SCboost converter provides a relatively light and eﬃcient converter for aerial robotics without the need for a heavy customwound transformer. the 10 mW converter design is considered using 10 nF 0402 capacitors and a 30 V boost converter output.35 V at 1. In each phase. As the number of stages increases.
5% 73. Then the glider steers itself to that point to position a wireless sensor node (in the experimental prototype. The gliders slowly spiral down until a target or destination is located.7 MΩ 3. The glider and the control PCB are shown in ﬁgure 6. an RFID tag) on the target.6.3 MΩ 5.3% 87.3 MΩ 1.5 MΩ 4.0% 79.7% Table 6. The control PCB contains all the control and power electronics and is centrally located on the fuselage.4 139. A 20 mAh lithiumpolymer battery is used as the power source.5 227.Stages 4 5 6 7 8 9 10 Output impedance 62.27 MΩ Load resistance 1. A box of these gliders can be released from a piloted aircraft above territory where access is impossible or impractical.2 207.2 MΩ 6.9 MΩ 2. and is located at the front of the plane (with an attached wire bumper) for balance.5% 84.8% 82.1 Eﬃciency 90. The converter used is shown in ﬁgure 6. 6.2 kΩ 133 kΩ 244 kΩ 404 kΩ 622 kΩ 907 kΩ 1. The MicroGlider uses a hybrid SCboost power converter to generate the 200V bias rail for the power ampliﬁers to drive the piezoelectric actuators. 63].4. A Linear Technology LT16151 boost converter controller chip was 116 . The glider is made with carbon ﬁber wings and control surfaces with a carbonﬁber tube fuselage.0 MΩ Output voltage 113.0 163.5 245.5. Eﬃciency of ladder converter with 4–10 stages at 10 mW load tation of this hybrid SCboost converter topology will now be examined as it is used in the MicroGlider project.3% 76.3 186.2 MicroGlider Power Converter The MicroGlider is a twogram passive aircraft used for remote sensing purposes [64.
(a) Carbon ﬁber MicroGlider[64] (b) Control PCB. When the output voltage falls below the threshold. The 117 . An intermediate output tap was provided at seven stages in case a lower voltage. power converter outlined Figure 6. highereﬃciency supply was desired. then turned oﬀ (with a 400 ns delay).1.5. The SC ladder topology is identical to the one discussed in section 6. the inductor is magnetized through the internal switch to a trip point of 100 mA. Photos of the MicroGlider and control PCB C1 VIN L VOUT VIN SW C3 C5 R1 C0 R2 FB CIN LT16151 SHDN GND C2 C4 C16 Figure 6. Hybrid SC boost converter as appearing on the MicroGlider used to generate the intermediate 30V rail and to drive the ninestage ladder topology.3 using BAS40DW04 diodes and 10 nF 0402 capacitors. The LT16151 part automatically controls the boost controller with feedback supplied by the resistor divider made with R1 and R2. A Coilcraft 10 µH 0603PS shielded ferrite inductor was used for the boost converter component.4.
5% 3. The eﬃciency and output voltage numbers are quite close to the predicted values. the hybrid boost converter is an eﬃcient method to generate high voltages in a massconstrained application using oﬀtheshelf components.3 V 2. the calculated eﬃciency and output voltage are 55. respectively. With nine stages.9% at an output voltage of 186 V is expected. The output voltage and eﬃciency of the fabricated converter are shown in table 6.7 stages Load Output Voltage Output Power Eﬃciency Output impedance 10 MΩ 162.83 mW 61.8 cm2 of board area on the control PCB.7 V 7.1 mW 51. with the output voltage sagging some due to the unmodeled loading from the diode junction capacitance. With a quiescent current of 19 µA.3% 9 stages 10 MΩ 203 V 4.2 kΩ 49 kΩ Table 6.7. In conclusion. The feedback network (R1 and R2) were tuned to deliver an intermediate voltage of 31 V. and can output up to 35 V. an overall eﬃciency of 59.63 mW 51. When cascading a sevenstage ladder converter with this boost converter. the control circuitry does not signiﬁcantly aﬀect eﬃciency.3 MΩ 200 V 12.5V voltage source and a resistive load.6 as the boost controller automatically increases switching frequency as load current increases. For a 20 V. It was tested using a 3.3 MΩ 160. The incremental output impedance numbers do not match those given in table 6.0 V.7.5% 3. The converter was fabricated using a 3milthick ﬂexible PCB and occupies 0. suitable for a lithiumion battery.8% 49. Experimental results of the MicroGlider converter converter IC runs from an input as low as 1. 118 . 10 mW output.8% and 227 V.12 mW 47. the measured eﬃciency of the standalone boost converter is 73% [26].
While energy harvesters and their power conversion circuits have recently been integrated on the same die [29]. the power harvested is not yet suﬃcient to power a 110 µW sensor node. Switchedcapacitor converters are ideal for WSNs as they can easily be integrated and have high eﬃciency over a wide range of power levels. This chapter examines the power processing circuitry designed for a miniature energyharvested wireless sensor node (WSN). This chapter discusses the 119 . Wireless Sensor Nodes (WSNs) are using less power and are becoming smaller as this technology matures.Chapter 7 SwitchedCapacitor Converters for Wireless Sensor Nodes Switchedcapacitor converters exhibit many advantages over traditional inductorbased converters for ultralowpower applications. The eﬃciency of the scavengerbatteryload power interface path. especially at low power. Scavengedpower sensor nodes are now a reality with modern processor. By using MEMS energy harvesters [44] and inkjet printed supercapacitors and batteries [55. 45]. 56]. sensor and radio technology [38. a highlycapable sensor node can be made in the size of a sugar cube (1 cm3 ) [39]. is critical to the performance of such a sensor node.
65 V supply. include a TI MSP430 microcontroller. tire pressure is measured once every six seconds. an Inﬁneon pressure and acceleration sensor.1 V supply and the radio requires a precise 0. Power consumption for a 120 .design of a custom IC to perform scavengertobattery and batterytoload power conversion. running from energy scavenged from a magnetic shaker [38. 11]. or loads. In the TPS application. (a) (b) Figure 7. while meeting power and size constraints of the system. Each board contains a single functional block of the system. A small NiMH coin cell with a nominal capacity of 18 mAh is used as an energy buﬀer.1 Application and IC Overview This chapter describes a power interface integrated circuit [52. The electromagnetic shaker utilizes the rotation of the tire to generate energy to power the sensor. 7. The sensor node is a modular stack of 1 cm2 printed circuit boards connected by elastomer connectors.1.1. Photos of the node and scavenger are shown in ﬁg. The microcontroller and sensor run at a minimum 2. The energy consumers. 7. and a custom PicoRadio radio transmitter [12]. with dimensions indicated. 49] for a wireless tire pressure sensor (TPS). Photos and dimensions of the a) PicoCube and the b) electromechanical shaker WSNs often run at very low duty cycles to minimize power consumption. although the use of a supercapacitor is also feasible.
4. The performance of a selfpowered WSN is often deﬁned by the sample rate or the number of samples per second the node can acquire and transmit. Since WSNs spend the vast majority of time in standby mode.3. Measurement and transmission power single 14ms measurement/transmission period is shown in ﬁgure 7. The design of the power 121 . the sample rate is highly dependent on the eﬃciency of the power interface circuits. and a ﬁxed average power supply (deﬁned by the capabilities of the battery or energy scavenger).2 V.7V rail get result 2 2. Two switchedcapacitor power converters convert the battery voltage. The synchronous rectiﬁer interfaces the electromagnetic shaker (harvester).2. Node standby power is less than 1 µW resulting in a timeaveraged power consumption of approximately 6 µW.2. which puts out a pulsed waveform.7 V to power the radio. yielding peak powers of several mW. power eﬃciency at microwatt levels is critical but lacking in current solutions. Details about its use and implementation are in section 7.send packet (alternating 1’s & 0’s) wakeup 3 Power [mW] 0. The architecture of the power interface IC is given in ﬁgure 7.1V rail 1 acquire sample 5 Time [ms] 10 15 Figure 7. nominally 1.1 V for the microcontroller and sensors and to 0. to 2. For a given ﬁxed energy per packet. Each 14ms measurement/transmission cycle uses approximately 29 µJ. to the battery. This power interface IC aims to improve this eﬃciency.
Finally. and is described in section 7.65 V and to smooth the ripple from the switchedcapacitor converter. while the gate drive techniques used are described in section 7. A number of analog blocks provide support to the power electronics by providing references and control signals. the regulator’s bias current is decreased substantially to reduce quiescent power. It is biased at 18 nA independent of VDD and mildly dependent on temperature.5. A selfbiased current source (reference) supplies bias current to the chip via a current mirror. the energy stored in the capacitor is preserved and the turnon transient response is shortened. An ultralowpower linear regulator is used as a postregulator to moreprecisely set the radio supply voltage to 0.Scavenger Current Reference Synchronous Rectifier Voltage Reference 0. Thus.1V (1:2) Converter Linear Regulator Radio Battery Microcontroller Sensors Figure 7.7V (3:2) Converter Feedback 2. This linear regulator is designed with an integrated switch to disable the regulator’s output. a hysteretic feedback controller is used to regulate output voltage and switching frequency. An ultralowpower sampled bandgap reference provides a reference 122 .3.2. The enable transistor is located between the output capacitor and the load such that the output capacitor remains charged while the output is disabled.3. When the output is disabled. Block diagram of the converter IC stages of these converters is detailed in section 7.
the latter used in the switchedcapacitor converters. shown in ﬁgure 7.2V working voltage matches the battery voltage perfectly. The beneﬁts and drawbacks of a number of SC converter 123 . shown in ﬁgure 7. A 3:2 ratio converter. b) 3:2 converter voltage to both the converter feedback circuitry and the linear regulators. The design of this voltage reference is further described in section 7. The converter IC was implemented using a 0.5. The nominal 1.13 µm CMOS process. provides a lower voltage (nominally 0. The minimum supply voltage for these components is 2.2 Converter Architecture and Optimization Two independent switchedcapacitor (SC) converters perform the power conversion between the battery and the loads. Switchlevel diagram of a) 1:2 converter.1 V. and the process provides 2. even to generate the 2.4.5 V transistors and highdensity capacitors.13 µm CMOS process provided by STMicroelectronics. provides a doubled voltage for the microcontroller and sensors. A 1:2 ratio converter.4b. The topologies are chosen to utilize the native transistors of the 0.65V) to supply the radio. 7.VOUT φ1 VIN φ2 VIN φ1 C1 CO φ1 φ2 φ1 φ2 VOUT C1 φ1 C2 φ1 φ2 φ2 CO (a) (b) Figure 7.1 V rail.4a.
Those techniques will be applied here to size the various components and choose the maximum switching frequency. All power switches are implemented using triplewell NMOS transistors to minimize die area and gating and parasitic losses. A numerical optimization is performed by evaluating eﬃciency and output impedance over a range of switching frequencies and switch areas.topologies are described in chapter 4. while minimizing net loss. switching frequency will be regulated via a hysteretic control loop described in section 7. the capacitor area is divided between the two converters such that both would run at the same switching frequency (to allow for a single clock). Metalinsulatormetal (MIM) capacitors are used for all capacitors as they have a relativelyhigh capacitance density and low bottomplate parasitic capacitance. The solid straight lines separate the space into four regions. Contour eﬃciencies are indicated. To optimize the SC converters.3 addresses the level shifters and other circuitry required to drive these transistors. power and die area. The optimal design lies in a wide plateau between 90% and 92% eﬃciency. Under nominal operating conditions.5. A margin of error for process tolerances needs to be included as well. was developed. the total capacitor area is constrained to a prescribed area.5 shows contour plots of the converter eﬃciency swept over switching frequency and switch area for the 1:2 and 3:2 converters. Next. capacitors and converter switching frequency of each converter are adjusted to optimize eﬃciency while meeting constraints on output voltage. and the relative capacitor sizes within each converter are adjusted by the optimization in chapter 3. indicating where each of the four indicated loss mechanisms are dominant. In chapter 3. The two remaining variables are the switch area (for each converter) and the switching frequency. The two converters were designed with a slightly higher switching frequency and switch 124 . a method to optimize transistor and capacitor sizes. The converter is optimized to maximize eﬃciency via this method while keeping the output impedance suﬃciently low such that the required output voltage is maintained at maximum output current. and the relative allocation of die area between transistors and capacitors. Figure 7. The transistors. Section 7.
bottom plate loss limited 100 0.85 0. bottom plate loss limited 100 0.7 0.5.9 0.9 Cap.6 0.4 10 Switching Frequency [MHz] (b) 100 Figure 7.85 100 0.6 1000 Switch Area [µm2] 0. Optimization contours of the (a) 1:2 converter and (b) 3:2 converter 125 .7 FSL loss limited Cap.85 0.8 Switch parasitic loss limited 0.8 FSL loss limited 10 Switching Frequency [MHz] (a) 0.9 SSL loss limited 0.8 0.6 0.85 0.0.8 Switch parasitic loss limited 0.6 Switch Area [µm2] 1000 SSL loss limited 0.
3 Gate Drive Since both converters use only native 0. respectively. M6 and M8. The 1:2 ladder converter exhibits a regular structure that can be extended for higher ratio conversions. along with switch areas of 550 and 950 µm2 for the 1:2 and 3:2 converters. Two pulldown signals. The anticipated fullload openloop eﬃciencies of these two converters are between 90% and 92% for both the 1:2 and 3:2 converters. The cascode level shifters [40] are made with triplewell 0. driving the gates is not trivial. connected to the sources of M5 and M8. capacitor C2 in ﬁgure 7. The top transistor in the NMOS transistor stack implementing the ladder converter is driven based on a ﬂoating supply. Since all transistors in the levelshifter are 1. M5. 7. This implementation is shown in ﬁgure 7.6 powers the circuitry to drive M2. Two NMOS transistors (M7 and M10) then reproduce these signals to drive the levelshifter above it.g. The ladder structure of the power devices is continued 126 .area than optimal to ensure the output impedance was suﬃciently low across the process corners. shielding devices are needed to prevent device breakdown. Cascode pairs (e. The threshold of these cascode devices limit the minimum voltage and speed of the level shifter. A nominal switching frequency of 30 MHz was chosen. Two gatedrive structures have been developed for the two SC converters. regenerating the signals at each stage. For instance. This ladder topology can be driven with cascode levelshifters. Transistor sizing and optimization is critical to ensure operation over railvoltage variation.13 µm NMOS devices.2V triplewell devices. toggle the latch to either the on or oﬀ position. A pair of crosscoupled inverters form a latch.6 for an intermediate stage in a ladder converter. Each level shifter and its gate driver are powered from the local power capacitor connected to the relevant switch’s source. M9) are used to shield both the NMOS pulldown transistor and the gates of the NMOS transistors.13 µm devices and can translate a signal up an arbitrary number of levels.
a moredirect drive can be used. shown in ﬁgure 7.6.M4 C4 C3 M11 M3 C2 M2 M6 C1 M1 M5 M8 M7 M10 M9 M12 Figure 7. and is driven with an inverterchain buﬀer. The top transistor in the extended ladder is implemented using a PMOS device and driven by the same source as the NMOS transistor beneath it. creating higher potentials to drive each of the large powerpath switches. six of the seven transistors are driven this way. This chargepump gate drive. An alternate gate drive structure is used for the 3:2 converter. The operation of this gate drive circuit will be examined with respect to the drive signal CLK. When CLK is low.2V supply to directly drive the gate of a transistor with a nongrounded source. Cascode levelshift gate drive for the 1:2 ladder converter by one or two more smaller transistors. In the 3:2 converter. When CLK is high. C1 charges the gate of the power transistor to VDD + VOU T through 127 . uses a ﬂying capacitor charged to the 1. Also.4b) never exceed the VDD rail. the ﬂying cap C1 is charged to VOU T via M4 and M1. the power transistor gate is discharged to ground via transistors M6 and M7. Since the sources of all the transistors in this converter (in ﬁgure 7.7. The remaining transistor has its source connected to ground.
Capacitor C2 eliminates the diode drop of M4 while charging C1 when CLK is low. A small permanent magnet moves inside a cylinder wrapped with a multiturn winding. shown in ﬁgure 7. a single 2 pF MIM capacitor was used.7. so their gates are driven correctly. For each of the three gate drive circuits (each driving two switches). Capacitor C1 is sized such that it dominates the gate capacitance of the power transistor. C1 is the primary capacitor of the charge pump which charges the power capacitor to the appropriate voltage.8a. Capacitorboost gate drive for the 3:2 converter M2 and M5. assist cap C2 is charged to VOU T via diodeconnected M3. The local centrifugal force is normal to the direction of magnet travel. creating a normal force depending on the rotation speed. ensure eﬃcient converter operation using only the native 0. This gate driver. 7. Each time the magnet falls from 128 . The shaker axis is oriented tangential to the circumference of the wheel.4 Synchronous Rectiﬁer The tire pressure sensor is powered using an electromagnetic shaker. While in the onstate. In addition.13 µm NMOS devices.VOUT VDD M2 C1 CLK M1 M3 CLK M4 C2 M6 M5 VDD VG M7 Figure 7. these power transistors’ sources are at VOU T . The varying gravitational force in the frame of the rotating wheel causes the magnet to fall back and forth in the cylinder. along with the cascode levelshifter for the 1:2 converter. enabling the gate to be charged to VDD + VOU T .
9 summarizes the circuits used for the synchronous rectiﬁer. 19. A synchronous rectiﬁer (see ﬁgure 7. 42]. Since the pulse shape and amplitude are predictable by the nature of the application.5–3. The synchronous rectiﬁer approaches the eﬃciency of an ideal diode rectiﬁer. 129 .9) uses active devices and feedback to perform the rectiﬁcation function without signiﬁcant voltage drop and power loss [49. a pulse of voltage is created. Since the magnet is usually not moving (as vehicles are usually parked). Hysteresis prevents oscillation and allows the circuit to reduce bias current at zero input. the source voltage can be matched to the battery or load voltage by simply changing the number of turns in the single shaker winding. Shaker (a) design and (b) example input waveform one side to another. The threshold of the hysteretic comparator is designed to be approximately ±0. For this application. The number of turns on our scavenger are optimized by trial and error to achieve the optimal opencircuit amplitude.4 V. these pulses must be rectiﬁed.VP iIN VB vIN t (a) (b) Figure 7. energy conservation at zeroinput is critical. Simple diodebased rectiﬁers are convenient but the forward voltage drop severely impacts eﬃciency at low system voltages. To charge a battery or capacitor. The lower two transistors of the bridge are gated complementarily from a hysteretic comparator. 24.0 V by the method in section 7.4.8. the optimal opencircuit amplitude was determined to be 2.1. Figure 7.
as detailed below. Figure 7. The bias current of the comparator is approximately 4 nA and is reduced when the input is low. respectively. Transistors M2 through M5 and transistors M6 through M9 form the ﬁrst and second stages of the comparator. These gating transistors are connected to the input voltage. Additionally. the input falls to zero and the quiescent current of the rectiﬁer is greatly reduced. bias current and delay time. An onstate drop of 2050 mV and bias current of 10 nA were targeted to achieve a compromise between conduction loss.+ + +  Figure 7. a circuit was added to reduce bias current at zeroinput conditions. The circuit used to replace each of the two topside diodes in the traditional rectiﬁer is shown in ﬁgure 7. Transistor M1 is the power transistor which replaces the rectiﬁer diode and is controlled by a twostage comparator. The body diode of M1 allows for operation as a traditional rectiﬁer when the circuit is powered oﬀ. Each stage is driven by a bias current source gated by transistors M10 through M12. conduction loss is minimized. The delay of the rectiﬁer depends on the bias current and the drainsource voltage diﬀerence on the switch. but transition time is lengthened. Synchronous rectiﬁer circuit The upper transistors of the bridge run independently and are controlled by comparators continuously sampling the voltage across each of the switches.9.10a. allowing the bias current sources to be shut oﬀ when the input voltage falls below the threshold voltage of the transistors. When no mechanical energy is applied to the harvester.10b shows the implementation of the hysteretic comparator in the synchronous 130 + . By making the switch large.
VIN M1 M2 M3 M6 M7 VOUT M4 M5 M8 M9 M10 IBIAS IBIAS M11 IBIAS M12 (a) Top diode replacement (PMOS) VDD M5 M6 V1 M1 M3 M4 V2 M2 (a) Bottom diode replacement (NMOS) Figure 7. Circuits implementing the synchronous rectiﬁer 131 .10.
swings below ground. limited by the forward voltage of the body diodes of these transistors. when both inputs are at zero volts. A current will ﬂow through the rectiﬁer during a period of time where the 132 . and thus the optimum peak input voltage. Since the devices must switch when the ﬂoating input. the comparator must be designed to allow a negative commonmode voltage at the input. is connected to a battery with voltage VB through an idealdiode bridge rectiﬁer. The sinusoidal source. with amplitude VP and series real impedance RS .rectiﬁer design. 7. Transistors M1 and M2 form the power devices which rectify the input signal. Figure 7. the opencircuit input voltage over a pulse can be written as: vOC (t) = VP cos(ωt) − π/2 ≤ ωt ≤ π/2. the circuit consumes only leakage power because it is essentially a digital circuit. Additionally. This work assumes constant amplitude sinusoidal pulses. of the electromagnetic harvester.8b shows a typical waveform for a shaker transition. (7. If the harvester has a natural frequency of ω and pulse repetition frequency of fIN . For simplicity.1 Impedance matching AC energy harvesters with diode rectiﬁers Analysis of a diode rectiﬁer is necessary to compute the optimum number of turns. the input voltage will be clipped to the battery voltage. which is connected to the oﬀstate transistor. The input devices (M3 and M4) have their sources crosscoupled to allow the sensing of negative voltages. since its forward voltage drop is nearly negligible. The synchronous rectiﬁer is modeled as an idealdiode rectiﬁer.4. Their body diodes can act as standard junction diodes when the circuit is not powered up.1) When the harvester is connected to the rectiﬁer. The inductance of the coil does not contribute signiﬁcantly to the impedance of the harvester at the sub100Hz frequency of operation. a single halfperiod of a sinusoid will be examined. Transistors M3 through M6 form a comparator which measures the input voltage and sets the state of the power devices accordingly. but the method can be extended to arbitrary waveforms.
6 0.3 0. Figure 7.11.1 1 kHz input RS = 1 kΩ Fraction of energy recovered Ideal diodes 20% diode drop 0. (7.9 1 Figure 7.2) The current ﬂowing through the rectiﬁer in the onstate can be written as: iIN = 1 (VP cos(ωt) − VB ) RS t ∈ tON .3) The energy recovered from a single pulse can be found by integrating the instantaneous power over the conduction angle: EIN = VB RS 1 ω cos−1 “ VB VP VB VP ” ” (VP 1 − ω cos−1 “ cos(ωt) − VB ) dt.8 0. This fraction corresponds to the energy obtained from the rectiﬁer divided by the maximum energy available through a 133 .2 0.5) The ideal ratio between VP and VB can be found by maximizing EIN with respect to VB .4 0.4) EIN = 2 VB ω RS 2 2 VP − VB − VB cos−1 VB VP .11 shows the fraction of the available energy harvested plotted as the battery voltage is varied with respect to the input amplitude.6 0.1 0. (7. Available energy via rectiﬁcation into a ﬁxed voltage source opencircuit voltage is greater than the battery voltage in magnitude: cos−1 − ω VB VP cos−1 < tON < ω VB VP .7 Battery voltage (as % of input amplitude) 0. (7.8 0.4 0.2 0 0 0. (7.5 0.
is compared with the energy obtained from an ideal matchedimpedance load.5 times the battery voltage. However. In addition. hysteretic feedback exhibits nearinstant response to large steps in load current. 7. which are common in wireless sensor nodes. such as a piezoelectric bender. Regulation is performed on the output voltage of each converter using a hysteretic controller.6) From this optimization. This maximum singlepulse energy is given by: EM AX = 2 π VP ω 8 RS (7. switching frequency control is essential to maintain high eﬃciencies across operating conditions. Hysteretic (thermostatlike) feedback has advantages of being simple to implement and inherently stable for all loads. in (7.matched resistive load. To reduce the frequencydependent power loss. which would dominate standby power. which can be ﬁltered by a lowdropoutvoltage regulator (LDO) for rippleintolerant loads. yielding a 20% loss while charging. if a highlyreactive harvester is used. However. Frequency modulation can be used to both reduce the power consumption of the system and to regulate the output voltage of the converter. load current consumption can be minimized. At microwatt power levels. The input energy. By keeping the output voltage regulated at the lowest voltage tolerated by the load. hysteretic feedback inherently introduces ripple in the output voltage.5 UltraLowPower Analog Circuits For systems with large peak power to average power ratios.5). it is not advantageous to pursue the remaining 7% by creating an elaborate impedancematching circuit. as the load is reduced. the eﬃciency is also shown in the case when diodes (each with a drop of 10% of the input amplitude) are used for the rectiﬁer. 93% of the resistivelymatchedload energy can be recovered when the peak of the input pulse is approximately 2. reducing the switching frequency. is necessary. In our 134 . Additionally. additional circuitry can be used to extract more energy from the source [42]. Gate drive and other frequencydependent parasitic loss at the maximum switching frequency is approximately 200 µW for the converter.
Even with subthreshold conduction. the converter’s clock is disabled until the output falls below the lower threshold.1.12. If the output is above the upper threshold. yielding an exponential relation between the drain current and the gatesource voltage. the radio is sensitive to ripple and variation of its supply. dropping an additional 50 mV and reducing ripple by approximately 20 dB. 7.Sys. To bias the analog circuitry on the IC. The topology of the reference was chosen to minimize the bias current for a given size resistor. microamps of current are necessary to allow for suﬃciently low process variation. Figure 7. This function is performed by a compact bandgap voltage reference. the current reference produces a current of 18 nA. Clk. it was operated at a very low duty 135 . an ultralowpower current reference was used. To reduce the average power consumed by this bandgap reference. The circuit is designed for deep subthreshold operation. Fig. independent of supply voltage. Diagram of control logic application. Two clocked comparators [59] compare each converter’s output to a pair of reference thresholds every 20 µs. Clk.12 shows the control system. The value of this resistor is nominally 500 kΩ. The reference current is set by the resistor R and the voltage drop across it. The hysteresis zone between the two thresholds causes additional ripple on the output in excess of the ripple discussed in section 5. +∆ Sampled Voltage Reference ∆ + + R en SC Converter Output S Q Figure 7.004 mm2 of die area. deﬁned by the diﬀerence in gatesource voltage between M1 and M2. so an LDO is used for postregulation. A reference voltage is required to perform output voltage regulation.13a shows the structure of the current reference. At room temperature. Conv. The current reference occupies 0.
proportional and complementary to absolute temperature (PTAT and CTAT.14 136 .14. respectively).VDD VDD M4 M5 M6 + M3 M2 R M1 2x iOUT VREF R3 R1 1x 8x R2 R1 (a) Subthreshold current source (b) Lowsupply bandgap reference Figure 7. a nontraditional reference structure is used. 7] with an improved implementation described in [53.2 V). instead of voltages. Figure 7. The sample and hold circuit was speciﬁcally designed to reduce leakage and charge injection to keep a constant output voltage with a long period between samples. Schematics of analog references sample vIN sample + vOUT Figure 7. Lowleakage sample and hold circuit cycle and sampled. 23].13. The startup and stabilization of the bandgap circuit was optimized for speed to minimize the duty cycle. The bandgap core (in ﬁgure 7. Since the supply voltage is below the bandgap voltage of silicon (1.13b) is based on the sub1V operational circuit presented in [5. It operates below the bandgap voltage by adding currents.
a combination of analog quiescent current. The second capacitor. The die. The ﬁrst sampling capacitor discharges linearly to the input (which is at a low potential when the bandgap reference is oﬀ).15. Thickoxide transistors were used for the input of the follower to reduce gate tunneling current. a twostage circuit was used. and component leakage. forming a quadratic voltage proﬁle. Opposing matched PMOS transistors counter the charge injection from turning oﬀ the sampling transistors. Figure 7. The die area is dominated by the ﬂying capacitors and the pad ring. Photomicrograph of power interface IC The IC was fabricated using the STMicroelectronics 0.shows the twostage sample and hold circuit. signiﬁcantly smaller than discrete. In this IC. oﬀtheshelf system implementations.13 µm CMOS process. 137 . Since the sampling transistors dominate the leakage rate. ESD structure and pad ring leakage.15. discharges based on the diﬀerence between the two capacitor voltages. which otherwise becomes signiﬁcant for small sampling capacitors and long hold times if thinoxide devices were used. is approximately 2 mm on a side. The analog circuitry and power transistors occupy the 420 µm× 200 µm region at the bottomcenter of the IC. the leakage current was approximately 6.5 µA. shown in ﬁgure 7. This sample and hold topology is more spaceeﬃcient than a singlestage circuit using a larger capacitor for a given sample rate.
6 0. The eﬃciency data include the quiescent current of the chip.0.15V Both switchedcapacitor converters were tested over a range of loads.7 0.1 2 1.16.55 3:2 Regulated 1:2 Unregulated 2. the output voltage and eﬃciency are not aﬀected by the feedback. The results show that the regulation function works to achieve a constant output voltage and to dramatically improve eﬃciency at low power levels. When an overload condition causes the output to drop below the regulation level.7V) 1:2 step−up (2.75 .8 3:2 Unregulated 3:2 Converter Output [V] 0. so nominal converteronly eﬃciencies would be higher. since the converter is continuously operating at maximum switching frequency. The 3:2 converter and 1:2 converter achieve 138 1:2 Converter Output [V] 0.2 1:2 Regulated 2. Vin = 1. SC Converter output voltage and eﬃciency.65 0.1V) 0 −3 10 10 −2 10 Output Power Level [mW] −1 10 0 Figure 7. The output voltage and eﬃciency of both converters with and without regulation are shown in ﬁgure 7.16.4 2.3 2.9 10 80 −3 10 −2 10 Output Power Level [mW] −1 10 0 Efficiency [%] 60 Regulated 40 Unregulated 20 3:2 step−down (0.
5 3 Input Voltage Amplitude [V] 3. VB = 1. an ideal diode rectiﬁer into a ﬁxed voltage source. The third interface represents a Schottkybased diode bridge rectiﬁer. Eﬃciency for both regulated converters remains above 60% for output power levels in a wide range between 20 µW and 4 mW .5 0 0.5 2 2. typical of an oﬀtheshelf implementation. respectively.5 1 1.2V . Power output and eﬃciency of synchronous rectiﬁer.5 3 Input Voltage Amplitude [V] 3.0 kΩ series resistance. RS = 2.2 volts per diode.7% and 84. and a diode bridge rectiﬁer with a forward voltage of 0.17.0 kΩ load resistor). with a 2. modeling the impedance of the scavenger.5 100 80 1 1.5 2 2. The performance of the synchronous rectiﬁer is evaluated using a sinusoidal voltage source.5 4 Figure 7.5 4 Efficiency [%] 60 40 20 0 0. 100 Hz input peak eﬃciencies of 83.2V diodes Matched resistor 0. The rectiﬁer was compared to three idealized interface models: an exact impedance match (2.3%. 139 .1 Output Power [mW] This rectifier Ideal diodes 0.0kΩ.
2 V was used. At 10 kHz input. Compared with the ideal diode rectiﬁer (the practical maximum eﬃciency).7 V. are plotted in ﬁgure 7. yielding maximum eﬃciency.17. Synchronous rectiﬁer waveforms (at 100 Hz) The eﬃciency and output power of the synchronous rectiﬁer. relative to the matchedimpedance case. and the idealized rectiﬁers. 140 . the rectiﬁer obtains a relative eﬃciency of 95. Of this 4% overall loss. A battery voltage of 1.8%. typical of the shaker output. due to delayassociated losses.3 2 Input Voltage Open−Circuit Voltage Voltage [V]. 35% can be attributed to chipwide quiescent current and 65% to rectiﬁer conduction loss and switching delay. The peak eﬃciency of 88%. is obtained at an input amplitude of 2. Results were identical at 100 Hz and 1 kHz input frequency. At this frequency. The synchronous rectiﬁer has been shown to be signiﬁcantly more eﬃcient than a diodebased rectiﬁer. and to approach ideal behavior. Current [mA] 1 0 Input Current −1 −2 −3 0 1 2 3 4 5 6 Time [ms] 7 8 9 10 Figure 7. Figure 7. The frequency range below 1 kHz includes this scavenger and the majority of available vibrational scavengers[45]. and both measured data were nearly identical to the performance of the ideal rectiﬁer. the comparator delays are not noticeable. the peak eﬃciency drops by 10%.18.18 shows the voltage and current waveforms of the rectiﬁer with a 100 Hz sinusoidal input.
the sensor consumes 75. Standby power was tested at the smallest load power available.67 mW 540 µW 3.4 mW 450 µW 2.98 s 2.Operation Load Power Source Power Time/cycle Energy/cycle Eﬃciency Standby Wakeup Sensing Transmission Average 0.5 mW 6. Additionally. Since the ESD pad ring on this IC consumed approximately 2. At the target standby power of 1 µW.5 µW 1. further improvement of the standby power would greatly improve the eﬃciency.42 µJ.1. the overall system eﬃciency would improve to approximately 75 %. this average power consumption determines battery lifetime.6 µW 1. sensors and power processing circuitry on a single design would be necessary. Energy eﬃciency over sensing period 7.5 µW.2. improvements can be made where they are most useful.6 System Eﬃciency Since the PicoCube operates in numerous power modes.57 µW 5.0 s 51.0 mW 12.5 µJ 4. as shown in ﬁgure 7. by ﬁnding the mode with the largest energy consumption.16. In batteryoperated systems. calculating the average power consumption is important in sizing the scavenger and determining necessary input energy.5 ms 6.24 µJ 16. The PicoCube power conversion IC was tested at all the load conditions in ﬁgure 7.18 µJ 3.7% Table 7. The eﬃciencies in each of these modes are shown in table 7. 68% of which is consumed during idle.5 µJ 75. While the system eﬃciency of 47.8% 84% 84% 84% 47.7% is reasonable for such an application. Over the sixsecond period.1. a design with the processor.5 ms 6 ms 5. to achieve an ultralow standby power. 141 .42 µJ 5.0 µW 8. radio.
54]. Supply voltage has become lower with each new generation while supply currents have increased to keep power constant.Chapter 8 SwitchedCapacitor Converters for Microprocessors Switchedcapacitor (SC) converters have been used for many lowpower applications. Furthermore. using the design and optimization methods in chapters 2 and 3 and modern CMOS processes. While clock speeds and computational power per watt has been steadily increasing. the modern multicore trend has worsened this requirement. The number of pins on modern microprocessors devoted to power is in the hundreds. This chapter describes the feasibility and use of SC converters for highpowerdensity microprocessor applications. This trend has placed severe limits on the design of voltage regulators (VRs). dividing up the power pins and package power planes. often twothirds of the total number of pins [46. as each core 142 . However. numerous power rails are required. the supply power recently reached a practical limit imposed by thermal and economic constraints. To power numerous power domains on a microprocessor. the power density of SC converters can be increased. yielding an inherent design ineﬃciency. 17. Microprocessors have always been constructed using the most modern IC technologies. Chapter 7 discussed the use of SC converters for ultralowpower wireless sensor nodes.
Scaling As CMOS technology has progressed. Using parameters from the ITRS roadmap [1] from 2003 and 2007. Combining these factors. 20]. resulting in a highlyeﬃcient converter. the ESR can be minimized.can be in a diﬀerent sleep state. the fT of a transistor). decreasing its eﬃciency. In ﬁgure 8. 8.1. the power density limit of SC converters has increased with the reduction of feature size. These models can then be used to evaluate the performance of an SC converter using each of these technology nodes. the ondie inductors require a very specialized custom processing step and the converters made with them still have poor eﬃciencies. 22] and inpackage inductors [47. For multicore microprocessors. using ondie inductors [16. Inductorbased buck converters have been investigated for this application. If each core requires a diﬀerent supply voltage. but require magnetics in package.e. Similarly. Switchedcapacitor (SC) DCDC converters are ideal for ondie power conversion as they can be highly eﬃcient even at high power densities and require no oﬀchip components. However.2.1 shows the relevant parameters for the 90nm through 16nm technology nodes. equivalent oxide thicknesses have shrunk. based on its sleep state. resulting in denser onchip capacitors. These parameters can be used to make idealized device models as used in the analysis methods developed in chapters 2 through 4. having a single input voltage and ondie power converters to supply each core becomes highly desirable. 143 . which requires signiﬁcant chip metal and I/O usage. An ondie SC converter requires no specialized processing steps and does not increase I/O utilization. such as inductors. as discussed in section 8. Table 8. transistors have improved their performance by increasing the ratio of conductance to gate capacitance (i.2. Using a standardcellbased design. This metal and I/O usage increases the series resistance of a converter. the number of input rails becomes unmanageable. estimated circuit parameters can be found for numerous process generations. The inpackage inductor buck converters are eﬃcient.1 Power Density vs.
As the power density of SC converters improves with scaling.8 22 nm 0.95 101 0.1.08 0.5 1820 0.2 shows a number of modern microprocessors.9 909 1. [nm] Gate Leakage [A/cm2 ] VDD [V] VT H [mV] ID. Process parameters from the ITRS roadmap TDP [W] 65nm Merom [46] 45nm Atom [17] 65nm Itanium [54] 35–80 W 0. The number of pins assigned to the power interface is dominant in the 65nm Core 2 144 .05 1110 1.7 109 0.4 2500 0.6 – 2 W 170 W Die Area [mm2 ] 143 25 700 Power Density Total Pins Power Pins [W/mm2 ] 0.9 45 nm 0.84 32 nm 0. Table 8.0 94 0. Converter eﬃciency must be held high such that performance does not decrease signiﬁcantly to keep total die power dissipation constant.0 600 1.2 1300 0. Second.24 780 (478) 441 555 (288) Table 8.2 200 0.74 1820 0.on [µA/µm]1 CG. the number of power pins for a microprocessor can be greatly decreased. Using ondie power converters.2.Technology Node: Equiv.55 1250 0. including their thermal design points (TDPs) in terms of die area and the number of supply pins used. the output voltage is scaled to match that of the process.58 16 nm 0.0 65 nm 1.24–0.71 1510 0.9 99 0.total [fF/µm]1 90 nm 1. TDP and pin counts for three modern Intel microprocessors the performance of a 2:1 doubler converter is compared in two ways.1 150 0.48 1 per micron width of a minimumlength transistor Table 8. the die area expansion required for ondie power conversion becomes minimal. First.55 2245 0.2 450 1. In both cases. the eﬃciency of the converter is compared if the power density is held constant at 1 W/mm2 .leak [µA/µm]1 ID.48 2535 0.56 0. Oxide Thick. the power density of the converter when scaled is examined if eﬃciency is held constant at 85%.
When the converter’s output impedance is considered. these three output voltages drop to approximately 1. use of onchip SC converters will enable great reduction in the number of power pins while only modestly increasing die area and TDP.8 V input. nominal output voltages of 1.6 V can be independently obtained. SC converter performance versus ITRS technology node Duo (Merom) processor. 145 .05. conversion ratios of 3:2. If MIM capacitors are used. the die area would increase approximately 13% and the design power would increase from 35W to 42W. since the capacitors can be built on top of the processor’s transistors.2a [27].90 4 Power Density [W/mm2] at 85% Efficiency Efficiency [%] at 1 W/mm2 88 3 86 2 84 1 82 90 65 45 32 Technology Node [nm] 22 0 16 Figure 8. In future multicore processors. nineswitch topology shown in ﬁgure 8. the consumergrade Intel microprocessor. If an 85% eﬃcient converter is used to power a 32nm mobile version of the Merom. With a 1.By varying how the switches are clocked. the die area may not increase and eﬃciency can be further improved.2 Converter Design The topology proposed for this application is the tripleratio. 0. according to ﬁgure 8.2. 8.2b. 2:1 and 3:1 can be obtained.9 and 0.1.
respectively.3.05 V and 0.8 V input).3 shows the eﬃciency of the tripleratio converter across a range of output voltages for both a resistive load and a ringoscillator load. as shown in ﬁgure 8.5 volts. Using the ringoscillator load model.3.75%. eﬃciency at low powers increase because the supply current is reduced signiﬁcantly over the resistive 1 This value may be optimistically low. lowspeed active and standby modes.8 and 0. Figure 8. output current scales proportionally with output voltage such that the output power density at 1. the ring oscillator exhibits a currentvoltage relationship as derived in section 8. This topology will be evaluated for a 1 W/mm2 application using the 32nm CMOS process using ITRSbased estimated parameters. These three voltages can be used to supply a microprocessor in fullspeed active. The PMOSbased ﬂying capacitors are created using the native oxide thickness and an approximate bottomplate capacitance ratio of 0.3. maximum eﬃciency can be obtained.2. The converter achieves greater than 80% eﬃciency at the two primary operating points (1.8 V).2.Switch 3:2 φ1 φ2 φ1 — φ1 — φ1 φ2 φ2 2:1 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 — 3:1 φ1 φ2 — φ2 — φ2 φ1 φ2 φ1 VIN S1 S2 C1 S3 S9 S5 S6 C2 S7 VOUT S1 S2 S3 S4 S5 S6 S7 S4 S8 S8 S9 (a) Tripleratio topology (b) Switch conﬁgurations Figure 8. Similarly. Tripleratio topology and its switch conﬁgurations 0.05 V is equal to 1 W. 146 .05 V design point (with a 1. respectively. With the resistive load. The optimization of the bottomplate capacitance of PMOSbased oxide capacitors is discussed in section 8.1.1 The power density of the converter is 1 W/mm2 at the 1. By operating the microprocessor at one of the three optimal voltages.
100 Ring Oscillator Load Resistive Load 90 2:1 3:2 80 Efficiency [%] 3:1 70 60 50 40 0. However. the 3:1 design point exhibits a lower conversion eﬃciency.8 Output Voltage [V] 0.3. First. the highest power eﬃciency can be maintained.9 1 1. Eﬃciency plot of tripleratio topology in a 32nm process load case.1 1. the approximate frequency of a ring oscillator will be found.5 0. The time constant 147 . 8. These relationships will be derived from fundamentals and will be evaluated using the 32nm ITRS process node.2. since the higherconversionratio topologies are inherently less eﬃcient than the 3:2 topology.7 0.4 0.1 Dynamic Voltage Scaling Analysis To examine the eﬃciency and performance of an SC converter for microprocessors. A 31stage ring oscillator will be considered as a representative digital circuit to consider the eﬀects of voltage scaling on both frequency and power consumption. If processor operation is constrained to the optimal design points.2 Figure 8. the performance of digital circuits as supply voltage varies should be examined.6 0.3 0. Previous work explains the advantage of dynamic voltage scaling (DVS) [9] and shows a converter to achieve DVS for an ultralowpower processor [41].
leak is the leakage power of a single inverter.3) is substituted to ﬁnd the normalized relation between power consumption and supply power: 2 PV DD = N fOSC CG. the propagation delay of an inverter can be represented as: tpd = ln(2) CG. an estimate of power consumption can easily be determined.total (1 + WP /WN ) VDD + VDD ID. The proportionality shows the normalized switching frequency of the oscillator as it varies with supply voltage. the transistor’s conductance is scaled by the overdrive voltage.4) where ID.4) by the number of inverters in the chain.2): fOSC = GD.1) where VN OM is the gate voltage of the transistor at its full conductance. Next. Now that oscillator frequency has been derived. (8. These three 148 . (8.total (1 + WP /WN ) .total (1 + WP /WN ) VDD + VDD ID. The total power consumption of the inverter can be found by multiplying (8.3) where N is the number of stages in the oscillator.on . power consumption and energy per operation as the supply voltage varies. If the switching point of the inverter is half the supply. The gate capacitance is increased by the ratio of the width of the PMOS transistor to the NMOS transistor.5) can be evaluated to calculate the normalized frequency. given by GD. Since the gate capacitance is fully charged and discharged each period.total (1 + WP /WN ) VN OM − VT H (8.on ((VDD − VT H )/(VN OM − VT H )) VDD − VT H ∝ N ln(2) CG. Since deep submicron devices are compared.on ((VDD − VT H )/(VN OM − VT H )) (8.2) The frequency of the ring oscillator can be easily found from (8.Leak (8.total (1 + WP /WN ) GD.5) The relations in (8.associated with each inverter is related to the product between onstate resistance and input capacitance: τ = CGS RON = CG. given by the ratio in the denominator of (8.3) and (8. the power consumption of each gate can be written as: 2 PIN V = fOSC CG. GD.on ((VDD − VT H )/(VN OM − VT H )) (8.1).Leak ) .
it is informative to examine the energy per operation of the processor model with and without the use of an SC converter.4.8V.5 0.9 1 1.6 1. Frequency varies approximately linearly with supply voltage while the power consumption varies approximately by the cube of supply voltage. These three points represent peak converter eﬃciencies and good solutions to the tradeoﬀ between clock frequency and instruction energy.8 0. three eﬃcient points can be identiﬁed (shown by circles). Thus. Approximate ring oscillator performance versus supply voltage quantities are compared in ﬁgure 8.4 0.2 Figure 8. so the ratio of leakage to switching power will be higher than in this model. While the SC converter increases the energy per operation of the converter.2 Normalized Quantity Frequency Power Energy/Operation 1 0.7 0.6 0.4.1.3 0. Since energy per operation (or Watts per MIPS) is the most important ﬁgure of merit for powerlimited microprocessors. due to its power loss.5 shows the normalized energy per operation of the ring oscillator model by itself. In typical digital circuits.6 0. Figure 8.4 0. with the SC converter and with an ideal linear regulator supplied from 1. the energy per operation of a typical digital circuit varies quadratically with supply voltage.1 1. most switches do not switch as fast as the clock.8 Supply Voltage [V] 0.2 0 0. The SC 149 .4 1.
4 1. Ripple and highfrequency noise can also be reduced by using a highspeed parallel linear regulator [3. denoted a cell. output power divided by die area) into consideration when determining eﬃciency. takes only power density (i. 8.2 0 0.e. Energy per operation using an SC converter converter provides a substantial improvement in performance over a linear regulator while operating at these three eﬃcient points.2 1 0. 150 .1. designing a multiplerail power distribution network is made signiﬁcantly easier and more ﬂexible.3 0.4 0.5.6 0.2 Figure 8.8 Supply Voltage [V] 0.2.2 Cell design The SC converter designed so far in this chapter has not been designed for any speciﬁc power. Each cell implements the topology shown in ﬁgure 8.5 0.2.7 0.8 0. By carefully designing and optimizing a standard converter cell.9 1 1. Any number of these standard cells can be interleaved to provide the necessary load power while reducing output voltage ripple. there exists an optimal size for each interleaved phase. The idealized model.8V 1.1 1.6 0.8 1.6 Normalized Energy per Operation Digital Only With SC Converter With LDO from 1.4 0. as used so far. 2]. While a single converter can be made of any size.
each of these resistance contributions must be weighted by the square of the appropriate charge multiplier to get the equivalent resistance in terms of the output current. These numbers would ideally be extracted from the layout of a standard cell in a real design. Thus.5 squares of metal will be assigned to both the input and ground rails. Thus. an estimate of metal resistance must be performed. To consider the eﬀect of metal ESR. A similar design methodology is carried out with the capacitors. The output rail resistance is not divided at all. using careful design technique. a lowresistance layout can be made. the number of metal squares used in the layout remains the same regardless of cell size. while 151 . increasing or decreasing the cell size represents a nearperfect dimensional scaling of the layout. For purposes of illustration. this constant control power becomes a moresigniﬁcant portion of the total power loss. The second constraint on cell size is the control circuitry needed in any cell which does not scale with cell size. and two squares will be assigned to the output rail. also yielding one metal square each. so 1. motivating the smallest practical cell size. When the 8switch. Level shifters and any cellbased control logic fall into this category. the equivalent series resistance (ESR) of the metal used in any sized converter cell is roughly constant. As the power level of the cell decreases. Each switch is typically designed to have multiple ﬁngers such that it would contribute approximately one square of metal to the layout. capacitor and power rail. This constant resistance produces a loss which is proportional to the square of output current. If a cell has a particular optimized layout. each switch and capacitor resistance sees a charge multiplier of onequarter. eﬀectively dividing each resistance by a factor of sixteen.The converter cell size (and power level) is constrained by the loss factors that do not scale directly with cell size. these two loss factors will have to be considered. Through a careful layout. a constant number of metal squares will be arbitrarily assigned to each switch. To determine the optimal size of a converter cell. Next. 2capacitor 2:1 conversion ratio case is considered. The resistance contribution due to the power rails is less obvious.
the equivalent outputreferred ESR of this converter is approximately 85 mΩ. and the optimum region is fairly broad. which is the typical fullload switching frequency of this converter designed for a power density of 1 W/mm2 using a 32 nm process. handling 25 mW.025 mm2 . the total sizedependent loss subtracts less than 1% from the total system eﬃciency. For these speciﬁc resistive and control losses. In an example levelshifting circuit.375 equivalent squares of metal. The fullpower case will be used: a 3:2 converter with an output voltage of 1. the power associated with the level shifter is approximately 48 µW. they should be used for current carrying. Thus. independent of cell size. a switching frequency of 400 MHz will be considered. the total transistor width is 8 µm per driver circuit. In this example.the resistances of the input and ground rails are divided by a factor of four. This loss is primarily proportional to switching frequency. The maximum switching frequency can be obtained through the numerical optimization in section 3. To ﬁnd the optimal cell size.2.05 V and a power density of 1 W/mm2 . should be optimized. (8. Since the upper metal layers of a process are often thicker (and have a larger pitch). as a percentage of output power. typically close to the maximum switching frequency.6) The second sizeconstraining loss is the control and levelshifting circuitry. At this optimal cell size. Adding these weighted components yields 3. Figure 8. A sheet resistance of 25 mΩ per square will be used. At a nominal frequency of 400 MHz.3. yielding a total levelshifter capacitance of approximately 120 fF. the optimal cell size is approximately 0. the power loss associated with these two elements. The optimal cell power of 25 mW is very practical from an implementation standpoint and will 152 . The loss associated with this resistance can be simply calculated by: 2 PESR = Req IOU T .6 shows the relation between these two losses and the output power over a range of cell size. This resistance remains approximately constant regardless of the size of the cell. typical of an upper metal layer in a modern process. so one must assume a nominal operating frequency.
8 7 6 Loss Percentage [%] 5 4 3 2 1 0 0. First. which will reduce output ripple and the size requirement of the output capacitance. resulting in a new optimized.3 Eﬃciency Improvements If conversion eﬃciency is a higher priority than power density or other metrics. these converters can be distributed around the die to reduce distribution losses and spread the heat dissipation around the die. the converter can be reoptimized around the reduced losses. methods of recycling charge from both the transistors’ gate and drain parasitic 153 .1 1 Figure 8. additional techniques can be used to improve the eﬃciency past that calculated in section 8. each cell can function as an interleaved phase in a higherpower multiphase converter. moreeﬃcient converter.001 0. 8.6. If parasitic losses are reduced. For higherpower rails.01 Cell Power [W] 0. Nonscaling components of power loss versus cell size allow the eﬃcient powering of lowpower rails. While the SSL and FSL output impedance losses are direct functions of the component sizing and process parameters.1 and chapter 3. the parasiticbased losses can be reduced through additional design considerations. Also.
8. In an integrated converter. Integrated inductors. followed by methods to reduce the bottomplate capacitance of MOS capacitors. in addition to the metal needed to distribute the gating signal. this loss could represent 2035% of the loss of the converter. If that method is used for gate charge recovery. creating this transformer is nearly impossible. In [4].3. the capacitor shorting method in section 8. potentially allowing excessive shortcircuit currents to ﬂow in the converter. the resonant gate drive reduces overall converter loss by 33 percent in a discretecomponent implementation.1 Resonant Gate Drive The gate drive loss comprises the majority of the switchrelated parasitic loss of any SC converter. with polarity connected according to switch phase. However. are too resistive to exhibit suﬃcientlyhigh quality factors to make an integrated resonant gate drive scheme practical. Each gate is driven with its own secondary winding. some charge recycling methods cannot be used. The primary winding is driven from a bias supply through a resonancesensing circuit using ﬁxedwidth excitation pulses. This ensures suﬃcient deadtime and a simple control scheme. For example. as the gates of the power devices must be wellcontrolled to ensure a positive deadtime. a pure zerocentered sine wave is applied to each gate. the requirement of nonoverlapping gate drive signals make SC154 . both phase 1 and phase 2 switches would be on simultaneously. when properly optimized as discussed in chapter 3.2 cannot be used as it directly charges one capacitance from the other. With fullyintegrated converters. The power transistor gates are directly driven at the resonance between the magnetizing inductance of the transformer and the total gate capacitance. Since SC converters are not particularly sensitive to duty cycle. using a multiplewinding transformer to perform the gate drive allows for both source isolation and gate resonance [4].capacitances will be discussed. Additionally. Any method to recycle some of the gate charge can go a long way towards improving the eﬃciency of the converter.3. In macroscale twophase SC converters.
drain charge recovery will be demonstrated. gate energy recycling is not yet feasible. The ﬁrst method. With a single 2:1 circuit. twice per period). However.7a. This conductance path equalizes the voltage on each of the two equivalent parasitic drain capacitances.2 Drain Charge Recovery The drainsource parasitic capacitance of the power transistors also consumes a significant fraction of the power loss in an SC converter. If two such circuits are interleaved. For medium.e. i. we note that all the drain parasitic capacitances connect the ﬂying node associated with a ﬂying capacitor and incremental ground. such as one of the two interleaved phases shown in ﬁgure 8. Using a single chargerecovery circuit per ﬂying capacitor. and the ﬂying capacitors are much larger than the total circuit parasitic capacitors. are in parallel. uses a single power transistor that is turned on during the deadtime between each primary phase (thus. since each interleaved phase only has a single ﬂying capacitor. the charge recovery circuitry can connect to the bottom terminal of the ﬂying capacitor2 . the eﬀects of nearly all the drain and bottom plate capacitances will be reduced. in addition to the bottomplate parasitic capacitance of the ﬂying capacitors. as shown in ﬁgure 8.based charge sharing schemes diﬃcult to implement. the parasitic capacitance is charged during phase 1 and discharged during phase 2. In a 2:1 converter. designated drain shorting. all of these parasitics.7b. clocked 180 degrees apart.7a. both shown in ﬁgure 8. the charge recovery circuit can transfer charge between the parasitic capacitances of each phase during the deadtime between switching periods. 8. Two charge recovery methods will be discussed here.3. 2 Alternately. the charge recovery circuit can be connected to each of the top nodes of the ﬂying capacitors 155 . it can be manipulated more ﬂexibly than the gate capacitance. Thus.to highfrequency integrated SC converters. If we assume the output and input sources are lowimpedance. Thus. as the voltage across this parasitic capacitance does not control the switch state. Using a simple 2:1 circuit as an example. Such a scheme would require a long switch deadtime to enable several periods of charge transfer switching.
Drain charge recovery using a twointerleavedphase 2:1 converter 156 .7.VIN φ1 VIN φ2 φ2 VOUT φ1 Charge Recovery Circuit φ1 VOUT φ2 φ2 φ1 (a) 2:1 ladder interleaved phases. noting terminals used for charge recovery Drain Shorting: Resonant Drain: (b) charge recovery circuits Figure 8.
the drain shorting method can be used.1 0. Additionally. Waveforms of drain charge recovery methods during the next phase.5 1 1. the amount of charge needed to charge the parasitic capacitance is reduced approximately by a factor of two.8 Resonant 0. denoted resonant drain. uses an inductor to transfer the charge from the parasitic capacitance in one interleaved phase to the opposite capacitance.7a. An inductance of 30 nH is used to transfer the charge between the 10 pF parasitic drain capacitances. If the resonant drain method is not feasible. The size of the shorting transistor is similar to each of the power transistors in the circuit.8 shows a single phase transition of the converter shown in ﬁgure 8. However.5 2 2. careful layout must be performed to ensure this RL charge transfer network has a quality factor greater than one.4 0. this transfer of charge would be complete.5 Time [ns] 3 3.6 Drain Voltages 0. In entirelyintegrated converters. the area cost due to this inductor must be considered.8. If the current path was lossless.2 0 Drain Short No Charge Recovery gate 1 gate 2 0 0. The voltage at the negative terminal of both of the ﬂying capacitors is shown 157 . Figure 8. The second method. eliminating the drain parasitic and bottomplate parasitic loss. there will be some loss using this method. as the path resistance is ﬁnite.5 5 Figure 8.5 4 4.
modiﬁes portions of the power loss equation.3. the deadtime must be suﬃciently large to enable a chargerecovery pulse between main phase clocks. the source and drain of the PMOSbased device 3 Assuming a pdoped substrate 158 . In both cases. the area of each capacitor cell is maximized. Since the capacitance of a junction is related to both the area and perimeter of the well.2) discuss additional circuits that reduce the power lost to two diﬀerent parasitic capacitances in an SC converter. MOS capacitors for SC converters are typically made using PMOSbased capacitors3 or triplewell NMOS capacitors. The drain shorting method recovers approximately half of the drain charge. the nwell diﬀusion capacitance of the capacitor cell is the dominant parasitic of the capacitor. Thus. This section will examine PMOSbased capacitors as they require no special processing steps. the ratio of parasitic to primary capacitance can be minimized by making the cell (and thus its nwell) as large and as square as the design rules for the process allow. Next. while this implementation of the resonant charge method recovers about 75% of the parasitic charge. the converter must be reoptimized while accounting for the modiﬁcations to yield a new optimal design.3. For maximum primary capacitance. but the primary oxide capacitance is only related to area. Second.3 Reducing BottomPlate Capacitance The previous two sections (8. the terminals must be biased correctly in order to minimize the parasitic capacitance. This improvement originates from two adjustments.3. Both methods cause the drain voltages to partially transition to the opposite state during the deadtime of the primary phase clocks. 8.1 and 8. This section discusses improvements to the layout of MOSbased capacitors to reduce their bottomplate parasitic capacitance. the nwell for a PMOSbased capacitor should be biased appropriately. Thus. or any other parasitic reduction method. when a parasitic reduction method is used. Using either of these charge recovery methods.for each of the two recovery methods and without any charge recovery method. First.
ﬂexibility exists in the biasing of the capacitor’s nwell.9. A PMOSbased capacitor made with 2 µm long transistor ﬁngers and well dimensions of 40 µm by 40 µm was simulated in a 65 nm process.9 shows a graph of the ratio between the parasitic bottomplate capacitance and the primary capacitance. Figure 8. the diﬀusion capacitance can be made smaller. The gate of the device is used as the negative terminal. However. Finally. the source to substrate voltage remains low while the nwell bias voltage is adjusted. Parasitic capacitance ratios for body and well capacitances are connected together and used as the positive terminal. In this analysis. Two junction capacitances are connected to the nwell tie: the sourcewell capacitance and the wellsubstrate capacitance. When the nwell is biased above the source of the transistor by 159 . if a DC voltage is used to bias the nwell against either the substrate or source. either of these capacitances can act as the bottomplate capacitance of the device. shorting the sourcewell capacitance. The second curve shows the same ratio if the well was tied to a DC potential above the source. such that the sourcewell capacitance becomes the bottomplate capacitance. Based on how the nwell is biased. One curve shows the bottomplate parasitic if the well is tied to a DC potential above the substrate. such that the wellsubstrate junction capacitance becomes the bottomplate capacitance.10 Parasitic Capacitance Ratio [%] 8 6 source to n−well 4 2 n−well to substrate 0 0 1 2 3 4 5 6 Bias Voltage [V] 7 8 9 10 Figure 8.
These parasiticreduction methods provide the necessary eﬃciency improvements to make microprocessorlevel SC converters practical.7%. higher power densities can be obtained for the same eﬃciency. 160 . By using these methods of reducing the bottomplate parasitic capacitance.5 volts. the bottomplate parasitic ratio becomes 0. which is an impressivelylow ratio for a MOS capacitor.
which is diﬃcult for many inductorbased converters. In chapter 7. chapters 2 through 4. since they use no inductors. The foundation of this method relies on charge multipliers. SC converters can be easily integrated on a silicon chip or into other applications where magnetics are impractical. SC converters can be used for numerous applications in the power conversion space. SC converters were shown to operate eﬃciently over many orders of magnitude of power. In section 4. These charge multipliers allow for the simple calculation of output 161 . In the analysis chapters of this work.4. The charge multipliers for any SC topology can be found by simple inspection or using the circuittheoretic method discussed in appendix A. SC converters were shown to have superior silicon and reactive element utilization compared with traditional magneticsbased converters such as the buck and boost converters. regulation is possible using SC converters as discussed in chapter 5. These advantages strongly motivate the use of SC converters in many applications.Chapter 9 Conclusions This work has developed both fundamental analysis and practical design methods for switchedcapacitor (SC) DCDC power converters. a thorough but simple analysis method was developed that predicts the output resistance and eﬃciency of an SC converter. the ratio of the charge ﬂowing through a component to the output charge ﬂow. Although inductorbased converters perform regulation highly eﬃciently. since they have numerous advantages over traditional inductorbased power converters. First.
SC converters can have 162 .2 volt battery. the power density of SC converters increases. allows the optimal sizing of both the capacitors and switches in an SC converter. two ondie SC converters were used to generate system voltage rails of 2. as reported in chapter 6. if ondie SC converters are used in the future. SC converters can be used for signiﬁcantly higher power densities and higher levels of integration than traditional magneticsbased converters. which. Total processor die area also remains approximately constant as the number of transistors increases to counter process scaling. Chapter 8 describes a speciﬁc nineswitch topology for applications in powering microprocessors. A MATLABbased tool can automate these design methodologies to enable rapid evaluation of SC topologies as discussed in appendix B. Additionally. Finally. while the power produced by typical microprocessors remains approximately constant due to thermal constraints. In this application.impedance. Three applications for SC converters were discussed in chapters 6 through 8. Since many SC topologies can be run in an openloop conﬁguration. In a 32nm process. As CMOS technology advances. This converter was used to control piezoelectric actuators on a twogram MicroGlider.1 and 0. These design methodologies enable the optimal design of SC converters for any application. in turn. Systemwide switch area and switching frequency were optimized to yield the minimal power loss at a speciﬁc design point in chapter 3. By using a hybrid boostSC converter topology. they will occupy an everdecreasing percentage of the die. Ondie SC converters are advantageous over external inductorbased converters since they can provide local supplies for each core in a manycore processor.7 volts from a 1. SC converters were found to be superior to inductorbased converters in miniature sensor node systems as they can be fully integrated and they run eﬃciently down to microwatt levels. the area required to perform ondie power conversion is approximately 13%. a high voltage was generated with maximal eﬃciency with a converter of minimum mass. the drive strategies for them are often simpler than for an inductorbased converter. Chapter 7 described a power conversion and conditioning integrated circuit used for an energyharvesting wireless sensor node. Thus. from sensor nodes to microprocessors and more.
Indeed.extremelyfast transient responses compared with inductorbased converters where the inductor current limits response time. SC converters can better respond to the fast load transients associated with computational blocks turning on and oﬀ. 163 . enabling the creation and analysis of many topologies. SC converters need not be limited to lowpower. optimized design of SC converters for many applications. highperformance applications due to these advantages. unregulated designs but can expand to compete with traditional converters in all realms of power conversion. SC converters may replace inductorbased converters in even highpower. The design methods developed allow intelligent. SC converters have been found to be simple to analyze. Throughout this work.
The dynamics of SC converters will then be investigated from a networktheoretic standpoint. a networktheory based analysis method is needed. a greater understanding of the constraints behind the formulation and operation of SC converters can be obtained.1 Summary of Circuit Theory Circuit theory is based on using speciﬁc techniques to mathematically describe electrical circuits. A few theorems on properties of SC converters are stated and proven. by developing the theory of SC converters. The section will ﬁrst start by summarizing the relevant circuit theory. This section describes the procedure for extracting network parameters from 164 . Next. For morecomplex topologies. or to automate the analysis of switchedcapacitor (SC) converters. A. This chapter is based on reference [27] and uses the theory presented in reference [13]. In addition. including the fundamental loop matrix and the fundamental cutset matrix.Appendix A NetworkTheoryBased Analysis for SwitchedCapacitor Converters The analysis methods presented in chapter 2 are suﬃcient when a converter’s charge multipliers can be found by inspection. these methods are extended to SC converters and the capacitor charge multipliers are derived.
1. Each component is transformed into a branch in the digraph where the direction of the arrow indicates the polarity of that component.e. a directed graph (digraph) can be constructed which represents the topology of the circuit while discarding the properties of individual circuit elements. is given by: Pi = ii vi (A. The arrow on each branch represents the reference direction of that branch. For any electrical circuit.1) From a connected digraph G. twigs shown with dark lines Figure A.a circuit. An example circuit with graph representation 165 . While more than one tree can exist for any digraph. The reference direction of a circuit branch determines the direction of its representative branch in the digraph. 3. Figure A. T is connected (i.1a shows a simple electric circuit which is then represented as a digraph in ﬁgure A. S2 S1 C2 S1 V1 + C1 S2 C2 C1 I1 V1 I1 (a) Circuit (b) Graph. denoted by index i. T contains all the nodes in digraph G. Thus. T contains no loops. the power dissipated by a given element. a tree T can be constructed from selected branches of the digraph.1b. 2. there is a path through T connecting any two nodes). each tree T must have the following properties: 1.
• For each twig in T. but again are unique given a choice of tree. . ib vb Kirchoﬀ’s Voltage Law (KVL) states that the voltages around a closed loop sum to zero. . . Following the loop around in the direction given by the corresponding link’s direction. the voltages around any fundamental loop can be summed and set equal to zero. . Twigs and links have the following important properties: • For each link. . . there exists a unique set of links such that a closed path can be drawn through the twig and the set of links such that the graph’s nodes are split into two nonempty disjoint sets. Thus. there are n − 1 twigs and l = b − n + 1 links. Based on the choice of tree. This link and set of twigs in the path form the fundamental loop associated with the link.2) il+1 vl+1 .Each branch in digraph G can be categorized as either a twig if it is contained in the tree T or a link if it is not. For a digraph with l links. i1 v1 . . 166 . Thus. there is a unique path along tree T connecting the two endpoints of the link. each twigs’ voltage is summed positively if its direction is the same as the link’s direction. . For a digraph with n nodes and b branches. For each link in G. . a KVL equation can be constructed from its fundamental loop. l equations exist. the branch currents ii and voltages vi can be grouped into vectors i and v of dimension b with the links occurring ﬁrst and the twigs last. This twig and set of links form the fundamental cut set associated with that twig. or subtracted if its direction opposes that of the link. . These fundamental loops and fundamental cut sets depend on the selection of tree T. il vl i= v= (A.
Kirchoﬀ’s Current Law (KCL) states that the sum of currents going into a node (or subgraph) is equal to zero. If the deﬁning twig of a cut set points from subgraph A to subgraph B.4) where Q is the fundamental cut set matrix corresponding to the digraph G and the tree T.3) B is the fundamental loop matrix of size l × b where each element is either 0. only properlyposed singleinput. For a network with n − 1 twigs. Similarly. For each fundamental cut set of the digraph G. (A. the currents through each element in the cut set in the direction of the selected subgraph must sum to zero. Further study of the proper formation of SC converters is presented in section A. 1 or −1. Links in the cut set that point the opposite direction are instead subtracted. as speciﬁed in chapter 2. In this section.which can be formed into one matrix equation: Bv = 0. 167 . B can be written in the form: B= where 1l is an l × l identity matrix.6) A. Since each fundamental loop contains only one link. singleoutput twophase converters will be considered. The fundamental cut set matrix is the dual of the fundamental loop matrix and is related by the following relationship [13]: Q= Ql 1n−1 = −Bt 1n−1 (A. the links in the cut set that also point from A to B are added positively.2 Modeling SwitchedCapacitor Networks This section will derive the component voltages and charge multipliers for an SC converter based on fundamental networktheorybased methods.5) 1l B t (A.3. the n − 1 fundamental cut set equations can be formed into a matrix equation: Qi = 0 (A.
respectively. a fundamental loop matrix can be constructed based on that phase’s network.2c show the phase networks (i.1 Finding the Conversion Ratio and Component Voltages For each phase. as shown in ﬁgure A. twigs in bold Figure A. the voltages will not be sorted linkﬁrst.2a. Unlike section A. For each phase network. For a properlyposed twophase converter.2.S1 C1 S2 C1 S3 + VIN S4 C2 S5 C3 VIN + C2 C3 VIN + C1 C3 VOUT S6 + VOUT + C2 + VOUT (a) Topology (b) Phase 1. as that sorting is not 168 . The twigs in each tree are shown in bold (although the links and twigs depend on the choice of tree).1. a 3:1 ladder converter will be used as an example.2. Figures A. A. capacitor conﬁgurations) in phases 1 and 2. 3:1 Ladder topology. This set of links and twigs will be used as an example in the following analysis. twigs in bold (c) Phase 2.e. a tree T1 or T2 can be constructed. the input source is classiﬁed as a twig in both phases. This section considers only properlyposed twophase.2b and A. it is possible to choose the trees T1 and T2 such that each capacitor and output voltage source is a twig in one phase and a link in the other. In addition. twoport SC converters. including twig designations in each phase In this section.
In order to ﬁnd the converter voltages in terms of the input voltage. Instead.8) To ﬁnd the nominal conversion ratio and component voltages. which corresponds to the input voltage. the output current is assumed to be zero. v= .consistent between phases. Thus. the B matrix and the corresponding KVL equation for the threecapacitor ladder converter would be: −1 0 0 0 VIN v c1 0 1 −1 0 vc2 −1 0 1 0 vc3 0 −1 0 1 VOU T 1 0 1 1 =0 (A.10). the phasebased KVL equations in (A. the B matrix will 169 . so each capacitor must maintain a constant voltage in steady state.7) From the two phase networks. Thus. two KVL equations based on the fundamental loop matrices are obtained as follows: B1v = 0 B2v = 0 (A.9) For example. v = 0 (A. .10) has rank 4. the voltage vector will be deﬁned as: VIN v c1 .10) By inspection. All voltages in the unloaded circuit can be found in terms of the input voltage by manipulating (A. this KVL equation has a single degree of freedom. vck VOU T (A.7) must hold 1 B Bv = B2 simultaneously. . the matrix in (A.
each of the capacitors in the circuit supports onethird of the input voltage. the ratio of charge ﬂow 170 . and the converter has a conversion ratio of 1/3. the capacitor and output voltage vector can be found simply by solving (A.12).11). Vout (A.2. for more complicated converters or for use in an automated design tool. this method can be used to determine conversion ratio and component voltages. 0 1/3 0 1/3 (A. While these numbers can easily be determined by inspection. since Bc is square and fullrank for properlyposed converters: vc Bc = −bin VIN .12) This method can be used to ﬁnd the capacitor voltages and output voltage for the 3:1 ladder converter in terms of the input voltage: vc1 1 0 1 1 −1 −1 1/3 vc2 vc3 Vout 0 1 −1 0 = − −1 0 1 0 0 −1 0 1 0 1/3 VIN = VIN . the capacitor voltages change during phase transitions. unloaded SC networks have been considered where capacitor voltages are constant and no current ﬂows in the converter.11) From (A. A.13) Thus. The charge multipliers.be partitioned as follows: −1 0 0 0 VIN v c1 0 1 −1 0 vc2 −1 0 1 0 vc3 0 −1 0 1 VOU T 1 0 1 1 = bin Bc VIN v =0 c VOU T (A. but reach a periodicsteadystate pattern under constant line and load operating conditions. When the load current is nonzero.2 Determining the Charge Multiplier Vector So far.
1. charge must be transferred between the capacitors.15) where Qj is the fundamental cutset matrix for the transition in phase j. no net current ﬂows in each capacitor. To transfer charge between input and output. that correspond to the capacitors. Over an entire clock period. it must satisfy KCL for each phase transition: Qj ∆q j = 0 (A. the two KCL equations in (A.16) Using the identity in equation A. is derived here. and another charge transfer ∆q1 during the opposite transition. the capacitor voltages are in periodic steady state. and thus ∆q1 and ∆q2 obey the following relationship: 1 2 ∆qc = −∆qc (A.in a component to the output charge ﬂow. In steady state. and can be found by using the methods in section A. respectively.2b and A.14) 1 2 where ∆qc and ∆qc are the components of ∆q 1 and ∆q 2 . the following transformation will 171 . respectively. based on a network theoretic formulation.2c. Because operation in the SSL is being considered. this analysis will assume operation in slowswitching limit (SSL) and will thus neglect the small onstate resistance of the switches in the converter. As in section 2. represented by ∆q2 during the transition from phase 1 to phase 2.14. Since the charge multipliers OU OU represent the charge ﬂows in terms of the output current. there is an impulsive charge transfer. Since ∆q is an integrated current (charge ﬂow).6. the KCL equations for the ladder converter can be found: 2 1 ∆QIN ∆QIN 2 1 0 0 1 0 1 ∆qc1 0 −1 0 0 1 ∆qc1 0 1 0 1 0 ∆q 2 = 0 0 −1 1 1 0 ∆q 1 = 0 c2 c2 2 1 1 0 0 0 0 ∆qc3 1 1 0 0 0 ∆qc3 ∆Q2 T ∆Q1 T OU OU (A.16) can be combined to form a system of equations including both ∆Q1 T and ∆Q2 T .1 or from the identity in equation A. By examining the fundamental cutsets for the phase 1 and 2 networks in ﬁgures A.
17) This transformation can then be applied to (A.dif f −1 1 ∆QOU T = TQ ∆q = 1 1 ∆QOU T ∆Q2 T OU (A. Q ∆q = QC qout ∆Q2 IN ∆qc ∆QOU T.19) The transformed twophase fundamental cutset matrix Q for the ladder converter has a rank of 6.dif f ∆QOU T (A. The single degree of freedom in this equation corresponds to the output current ∆QOU T .1 : 1 ∆QOU T. To solve the charge ﬂows in terms of the output current.2 − ∆QOU T.20) Since QC is square and fullrank for properlyposed converters.18) Q1 I Q ∆q = ∆q = 0 Q2 TQ −1 Substituting (A.18) in the case of the ladder converter yields: 0 0 −1 0 1 0 0 0 0 0 ∆Q1 IN =0 −1/2 1/2 ∆Q2 IN 0 −1 1 1 0 0 1 ∆qc1 0 1 0 0 0 0 1 ∆qc2 0 0 −1 0 1/2 1/2 1 ∆qc3 0 −1 0 −1 0 0 ∆QOU T. Q will be partitioned as follows: ∆Q1 IN .dif f = ∆QOU T.be used to convert ∆QOU T and ∆QOU T.16) to create a single KCL matrix equation: (A.16) into (A.dif f 1 0 0 0 0 0 ∆QOU T (A. as discussed in section 172 .
A. 2/3 −1/3 1/3 (A. the charge multipliers for the capacitors can easily be determined by extracting the terms in (A.22) determines the charge ﬂows in the converter in terms of the output current.19). ∆qc ∆QOU T. the currents are fully speciﬁed by the topology. the current ﬂow in the converter 0 0 0 0 0 1 can be found as: 0 0 −1 0 0 0 1 0 −1 1/2 −1 0 0 0 0 −1/2 1 0 0 0 0 ∆Q1 IN ∆Q2 IN ∆qc1 ∆qc2 ∆qc3 ∆Q2 T − ∆Q1 T OU OU ∆Q1 IN ∆Q2 IN ∆qc1 ∆qc2 ∆qc3 ∆QOU T.21) Using the ladder converter example KCL equations in (A.22) 0 −1 0 −1 0 1 −1/3 0 1/3 = ∆QOU T .dif f (A. (A.dif f 1/2 0 0 = − ∆QOU T 1/2 0 0 0 −1 1 0 (A. and can be found by: ∆Q1 IN 2 ∆QIN QC = −qout ∆QOU T .23) Equation (A.3 −1/3 .24) The methods in this chapter develop a straightforward circuit theory based method for determining component voltages and charge multipliers for any SC converter.3.23) corresponding to the capacitors: ac1 1/3 a = 2/3 c2 ac. Thus. This 173 .
method can be used for complex topologies where determining the values by inspection is inconvenient. Switch Charge Multiplier Vectors To determine the SSL charge multipliers. the closed switches are usually twigs. the resistance drops across the converter’s switches were neglected. The two phasebased switch fundamental cutset matrix relations for the 3:1 ladder converter.2.2. 174 . they can be incorporated in both the KVL and KCL equations to determine their charge ﬂows and blocking voltages. as they connect two nodes which ordinarily would be the same node in a capacitoronly tree. are 1 Some switches in some topologies may be redundant from a graph theory perspective and are thus designated links. When the open and closed switches are added to the phase networks of a converter.2. Additionally. Two matrix equations can be constructed representing the currents through the onstate switches in each phase: i1 = Q 1 i1 r RC c i2 = Q 2 i2 r RC c (A. the switch onstate resistance is the dominant converter loss. However. in the FSL. in ﬁgure A. the capacitor charge ﬂows are the same as calculated above.4.1 The current through an onstate switch can be related to the capacitor currents by ﬁnding the fundamental cutset corresponding to that switch during the phase which it is on. The resulting equation relates the currents in this switch to the currents through the link capacitors. Since the currents in the circuit are still constrained by the topology. In each of the phase networks. this method can be used.25) The Q1 and Q2 matrices are deﬁned to include rows of zeros corresponding to the RC RC oﬀstate switches to ease the dynamics calculation in section A. if a computerbased SC analysis program is needed. as in section A.
neglecting the voltage across the onstate switches.2 The switch blocking voltages can be found through the following KVLlike equations involving two phasebased switch fundamental loop matrices: 1 1 vr = BRC vc 2 2 vr = BRC vc (A. openstate switches are always links. 2 If switch drops were included. depending on load. the switch fundamental cutset matrix where the corresponding row is nonzero is multiplied with the capacitor charge multipliers. the switch blocking voltage may vary slightly. 0 0 2 = ir 0 0 0 0 −1 0 0 0 0 0 0 0 1 −1 0 0 0 0 0 0 0 1 i2 c1 i2 c2 i2 c3 i2 T OU (A. 175 .28) The two phasebased switch fundamental loop matrix relations for the 3:1 ladder converter.27) Since the open switches connect two nodes that are already included in the tree. . The voltages across these openstate switches can be calculated in terms of the capacitor and input and output source voltages in the circuit. and the output charge during that phase substituted for IOU T : aj c1 j ac2 aj = Qj ar = a1 + a2 .26) To ﬁnd the corresponding charge multiplier for each switch.as follows: 1 0 1 = ir 0 0 0 0 0 0 −1 1 0 0 0 0 0 0 0 −1 0 0 0 0 0 0 i1 c1 i1 c2 i1 c3 i1 T OU . RC r r r j ac3 j iOU T /IOU T (A. Fundamental loop equations can be created involving each oﬀstate switch and the twig capacitors and sources.
however. The following analysis will examine the fundamental loop matrix BC .4.1. 2 = vr 1 −1 −1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 VIN v c1 vc2 vc3 VOU T (A. First.3 perform the desired power conversion. The next example will consider the 2:5 seriesparallel topology. and the analysis in section 4.3 Criteria for ProperlyPosed SC Topologies While the assumption that properlyposed converters has been used throughout this work. these two matrices have been square and invertible. In the example in the previous section.3. This section examines converters that are not properlyposed and modiﬁcations that can be used to make a converter properlyposed. the two phase networks are shown in ﬁgures A. the converters have been formulated to have a single input and output voltage source while eliminating unnecessary bypass (DC) capacitors.2.3ab. These matrices are used to ﬁnd the currents through and voltages across the switches in the converter. They are also used to calculate converter dynamics in section A. shown in ﬁgure 4. 0 1 0 1 = vr 0 0 0 are as follows: 0 0 0 0 0 −1 −1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 VIN v c1 vc2 vc3 VOU T . only one is properlyposed (or 176 .29). The twig assignments for each network are shown in bold. A. all formulations in ﬁgure A. As shown. in (A.11) and the fundamental cutset matrix QC . By inspection. calculated in section A.4.in ﬁgure A. the 3:1 ladder converter.29) Since the voltages on the sources and capacitors are nearly constant in typical operation. the DC values of voltage. in (A. This criterium ensures that a converter is properlyposed. little examination has been made on what properties a properlyposed converter has.2.2. are used in (A.20).
2 sets equalizing switches (f) Phase 2. 1 set equalizing switches C3 C1 VIN + C6 C5 C4 + C2 C3 + C2 VOUT C1 C4 C5 C6 VIN + VOUT (e) Phase 1. original (b) Phase 2. 2 sets equalizing switches Figure A.3. Three conﬁgurations of a 2:5 seriesparallel topology 177 . original C3 C1 VIN + C6 C5 C4 + C2 C3 + C2 VOUT C1 C4 C5 C6 VIN + VOUT (c) Phase 1. 1 set equalizing switches (d) Phase 2.C3 C1 VIN + C6 C5 C4 + C2 C3 + C2 VOUT C1 C4 C5 C6 VIN + VOUT (a) Phase 1.
wellposed). In the ﬁrst case, there are an excessive number of twigs in the two phase networks. With excessive twigs, the KVL equation is underconstrained (as there are few links to contribute equations). Since KVL cannot be solved, the DC voltages on each capacitor cannot be explicitly solved, but only a few relationships between the voltages can be found. Additionally, the fundamental cutset matrix is no longer square, so the KCL equations may be overconstrained. While the converter can operate eﬀectively, there is no guarantee on the capacitor voltages remaining below their limits, and therefore the converter is not properlyposed. Figures A.3cd show the networks if additional switches are connected in phase 2, as shown. These equalize the voltages between the capacitors in phase 2. In this conﬁguration, both the fundamental loop matrix and fundamental cutset matrix are square and fullrank. Thus, this converter is inherently properlyposed. Another indication that this converter is properlyposed is that each capacitor (and the output source) can be made a twig in one phase and a link in the other. Figures A.3ef show the phase networks if equalizing switches are added for both phase 1 and phase 2. In this case, the two networks have excessive links. As the dual of the ﬁrst problem, capacitor currents are not constrained by the topology since the KCL equations are underconstrained. Instead, the capacitor currents are set in terms of the capacitor values with a few constraints from the KCL equations. The fundamental loop matrix is no longer square, resulting in overconstrained KVL equations. Since the KCL equation is underconstrained and the KVL equation is overconstrained, this converter is not properlyposed. Next, a converter will be presented that is not properlyposed. Figure A.4 shows a converter which is a 1:3 seriesparallel converter in parallel with a 1:2 seriesparallel converter. The conversion ratio of this converter is undeﬁned, as currents ﬂow in the converter while unloaded. While it is clear by inspection that there is no steadystate zerocurrent solution to this converter, a look at the criteria deﬁned in this section is useful. First, as C3 is never a twig in either of the two phase trees, it is evident that there are too
178
φ2 VIN
+
φ1 C1 φ2
φ1 C2
φ2 φ2
φ1 C3
φ2
+
VOUT
φ1
φ1
φ1
(a) Topology
C2 C3 VIN
+
C1
C2
C3
VOUT
+
C1
+ +
VIN
VOUT
(b) Phase 1 capacitor conﬁguration
(c) Phase 2 capacitor conﬁguration
Figure A.4. An improperlyposed switchedcapacitor converter
179
many links in the phase trees. This suggests the KVL equations may be overconstrained. First, the fundamental loop equations will be written for both phases, and the equivalent of (A.10) will be formed: −1 1 0 0 0 VIN −1 0 1 0 0 vc1 −1 0 0 1 0 vc2 0 −1 −1 1 0 vc3 VOU T −1 −1 −1 0 1 =0
(A.30)
where the ﬁrst three rows correspond to phase 1, setting all the capacitor voltages equal to the input voltage. The last two rows correspond to phase 2. By inspection, since row 4 equates the voltage on capacitor C3 to the sum of the voltage on C1 and C2, no general solution exists. In fact, as this matrix B has rank 5, it is invertible, and thus no degrees of freedom in the solution exists. The only solution to (A.30) corresponds to all voltages equalling zero. These observations independently show that this converter is not properlyposed. Using the methods in this section, a systematic method of determining whether an SC converter is properlyposed, and thus suitable for analysis, has been developed.
A.4
Converter Dynamics
This section develops an exact model of the dynamics of an SC converter using the circuittheory based analysis method developed in section A.2. In each clock period, the converter forms an RC network based on the circuit’s capacitors and onstate switches, modeled as resistances. The voltage on each capacitor approaches a steadystate value during each phase. In the next phase, another RC network is formed with its own dynamics. Thus, an SC converter can be modeled as a continuoustime, timedependent linear system, as can other switchedmode converters. If the system is integrated through a switching period, an alternate discretetime linear system can be constructed where the sample time
180
corresponds to the period of the converter. The continuoustime and discretetime linear systems will be found in terms of the fundamental network theory parameters found in section A.2.
A.4.1
Preparing the System
In this section, the complete dynamics of a converter will be considered. In particular, the ideal voltage source at the output port will be replaced with a current source in parallel with a capacitor. This replacement moreaccurately describes most converter implementations and allows for the simulation of output voltage dynamics. In a properlyposed converter, this capacitor will be a link in one phase and a twig in another, like the original voltagesource load. The current source load is a link in both phases. The current through the output capacitor ∆QCOU T,2 is equal to half the ripple current at the output, denoted ∆QOU T,2 − ∆QOU T,1 in (A.17). The output capacitor voltage is added to the voltage vector, replacing the output voltage component. The state voltage vector v will be deﬁned as follows: v c1 vc2 = vc3 vcout
vC
(A.31)
where the output voltage of the converter is equal to the fourth element of this vector. Since the fundamental loop matrix B is used in determining system dynamics in each phase, its separate phase components B 1 and B 2 from (A.9) will be used. For consistency, the rows of B j must be ordered according to the link used for each fundamental loop. For example, in phase 1 of the 3:1 ladder converter, the fundamental loop of C1 should be the ﬁrst row of B 1 , followed by the fundamental loop of C2. Each of the fundamental loop
j matrices B j can be subdivided into two components. The ﬁrst matrix Bc corresponds to the
capacitor elements and vector bj corresponds to the input source. The properlyordered IN
181
and segmented fundamental loop matrices for the 3:1 converter are as follows: −1 1 0 1 1 0 −1 0 1 0 B1 = B2 = , . 0 0 1 −1 0 0 0 −1 0 1
(A.32)
The switch fundamental cutset matrices Qj RC will be simpliﬁed by eliminating the columns of zeros which correspond to twig capacitors. These reduced switch cutset matrices will be denoted Qj RCx to distinguish them from the full matrices. The reduced switch cutset matrices for the 3:1 ladder converter example are given as follows: 0 0 1 0 0 −1 0 0 0 −1 1 0 1 2 , QRCx = QRCx = 0 1 −1 0 0 −1 0 0 0 0 0 1
(A.33)
Next, a vector qOU T will represent the connection of the output current source, which has a 1 in the last position and zeros elsewhere: qOU T = 0 0 0 1 . (A.34)
Finally, diagonal matrices R and C will be deﬁned containing switch onstate resistance and capacitor values, respectively.
A.4.2
SinglePhase Dynamics
The next step is to calculate the dynamics of a single phase network of an SC converter. Section A.4.1 deﬁned the relevant singlephase network matrices used in this section. For simplicity of the explanation, the speciﬁc phase superscripts are omitted in this section with the understanding that the appropriate superscripts are used for each phase’s dynamics. The converter dynamics are determined by calculating the state vector v given the system state and output current. 182
the currents through the onstate switches can be found using (A. Since the output current and the output capacitor current are lumped in the last parameter of the state vector. As the currents in the links represent the currents in each fundamental loop. it can be used to ﬁnd the switchbased resistive voltage drop around each fundamental loop: vr . (A. the error in the KVL equation in A. the output voltage must be subtracted from the currents to obtain the capacitor currents as follows: iC = −BC −1 QRCx R QRCx (BC vC + bIN VIN ) − qOU T IOU T . Since the columns of QRCx represent the presence and orientation of each switch in each fundamental loop. the transpose of B is used to ﬁnd the currents in all capacitors. If the current through the links is given by iL . denoted vr .First. (A. the resistive drops of the onstate switches must be determined. loop = QRCx vr .35) Equation (A.37) (A.37) for iL : iL = − QRCx R QRCx −1 (BC vC + bIN VIN ) . (A. Since B only accounts for the input source and capacitor voltages. This loop voltage can be equated to the loop resistive drops by: B v = bIN VIN + BC vC = −QRCx R QRCx iL .26): ir = QRCx iL . The switchrelated voltage drops around each fundamental loop in the phase network can be found in terms of the resistive voltage drops vr .38) The circuit currents can be found by multiplying the link currents by the transpose of the fundamental loop matrix B.35) can then be multiplied by R to determine the resistive voltage drops.36) The link currents can be found directly in terms of the capacitor state and input voltage by solving (A. across the switches.11 is equal to the switchrelated voltage drops in the circuit. 183 (A.39) . The fundamental loop matrix B determines the voltage around each fundamental loop in the circuit.
47) The previous six equations fully describe a linear system describing the dynamics of a single converter clock phase. the following values of A. B. C 2 .11): iIN = −bIN −1 QRCx R QRCx (BC vC + bIN VIN ) . a standardform linear system will be created from (A. iIN IOU T From (A.39) and (A. A2 .45) qOU T −bIN QRCx R QRCx 0 −1 BC (A.42) QRCx R QRCx BC (A. D 1 and D 2 can be formed from the fundamental matrices developed 184 . B 1 . since the capacitor currents are known. the derivative of the capacitor voltages can be obtained by simply multiplying by the inverse of the capacitance matrix: v˙ = −C −1 BC C −1 QRCx R QRCx (BC vC + bIN VIN ) + qOU T IOU T .41) Now that the deﬁning diﬀerential equation for a single phase network of an SC converter has been found. The continuoustime standardform linear system is given in the following form: VIN v˙ = A vC + B C IOU T (A. (A.40) Finally.Similarly. B 2 . For any properlyposed twophase converter.40).41). the input current is found by using the component bIN from (A. C 1 . (A. the matrices A1 .44) B= −C −1 BC C= D= QRCx R QRCx −1 bIN −C −1 qOU T (A.46) −bIN QRCx R QRCx −1 bIN 0 0 (A. C and D can be extracted: A = −C −1 BC −1 (A.43) vOU T VIN = C vC + D .
25 0 0 0 6 1 = 2 = B B · 10 .1 .25 −0.75 −1.5 −1.25 −2.2 −6 C= R= (A.2 5 .5 6 2 = A · 10 3.in section A.50) (A. For the 3:1 ladder converter example. · 106 0 0 1.5 −0.5 −1.25 2.25 2.75 −2.75 2.25 3. −3.75 −2.25 −1.75 0 0 0 0 D1 = 0 0 .75 0 D2 = 0 (A.5 −3.51) (A.75 −0.25 −2.75 2.75 −0.25 −3. While this ODE representation and a SPICE simulation yield identical results.75 6 · 10 .5 1.1 −3.5 1 −0.48) · 10 1 .5 −1 (A.25 −0.75 −2.2 1 . 185 .2 0 −0.5 1. the dimension of the ODE problem is signiﬁcantly reduced.5 0.25 0 0.5 −3.49) 3. the eight linear system matrices can be found using the following resistor and capacitor matrices.25 1 = A −1. −3.5 3.2. optimized in chapter 3: .75 2.2 2 .5 1.2 0 0 1 0 0 0 0 1 C1 = .52) These system parameters can be used to perform a continuoustime simulation of the SC converter using MATLAB’s ode23 or similar ODE solver.75 −1.75 0 0 0 1. C2 = 3.
A. (A. as developed in section A. this analysis will be performed for a singleinput. In the discretetime system. although it can be extended for a multiphase converter. However. where each of the two clock phases takes up precisely half of this switching period. is useful for simulating an SC converter. incorporating all n clock phases in sequence. 1 (A.3 DiscreteTime Model The timedependent continuoustime linear model for a SC converter. respectively. for use in converter controllers. singleoutput twophase converter. The system will be sampled at the instant of time before the phase 2 to phase 1 transition. The input voltage and output current of the converter will be considered constant during each switching period. given by the Taylor expansion: eA = I + 1 1 1 A + AA + AAA + ··· . 1! 2! 3! (A.4. First. Similarly. the system must be integrated from time kT to time (k + 1)T . This integration is given by [10] by: vC ((k + 1/2)T ) = eA 1 T /2 T /2 vC (kT ) + 0 eA 1 (T /2−τ ) B1 u(τ )dτ (A. for the duration between sample k and sample k + 1. For purpose of illustration. the input current will be excluded from the system output vector for simplicity.55) 186 . The sample time for this discretetime model is a single switching period. and denoted as VIN [k] and IOU T [k].54) Since u(t) = u[k] from t = kT to t = (k + 1)T . To ﬁnd vC [k + 1]. A switching period of T is assumed.2. a discretetime model may be more appropriate.53) can be simpliﬁed as follows: vC ((k + 1/2)T ) = eA 1 T /2 T /2 vC (kT ) + 0 eA τ dτ B1 u[k].4. While (A. The capacitor voltage vector at this time is denoted vC [k] at sample k. the output voltage at sample k will be denoted VOU T [k].53) where u(t) is the input vector comprising of the input voltage and output current.53) looks like the solution to a singlevariable state integration. it utilizes the matrix exponential. the system will be integrated using the phase 1 system parameters to time (k + 1/2)T . Let the system state at time kT be vC [k].
4. In this 187 . it is useful to put the system in the standard statespace form for a discretetime linear system.58) Since A is not necessarily invertible.56) Now.61) BD = eA 2T 2 T /2 0 eA τ dτ B1 + 0 1 T /2 eA τ dτ B2 .58) does not necessarily have a closed form. 2 (A.57) in terms of the continuoustime system parameters: AD = eA 2T 2 eA 1T 2 (A.57) describes the system.62) The continuoustime system parameters for the 3:1 ladder converter example found in section A. (A. (A. 2 (A. if the state vC ((k + 1/2)T ) is known.57) 2 This deﬁnite integral of the matrix exponential above is given by: T /2 eAτ dτ = 0 T 1 + A 2 2! T 2 2 + 1 2 A 3! T 2 3 ··· .60) The discretetime linear system model parameters AD and BD can be extracted from (A.56) can be combined to ﬁnd the state sample k + 1 from the state at sample k: vC [k + 1] = eA 2T 2 eA 1T 2 vC [k] + eA 2T 2 T /2 0 eA τ dτ B1 u[k] + 0 1 T /2 eA τ dτ B2 u[k]. The standard form of a discretetime system is given by: (A.55) and (A. the state at time (k + 1)T can be found as follows: vC ((k + 1)T ) = eA 2 T /2 T /2 vC ((k + 1/2)T ) + 0 eA τ dτ B2 u[k].Similarly. (A. (A.2 can be used to ﬁnd the discretetime linear system parameters.59) VIN [k] vC [k + 1] = AD vC [k] + BD IOU T [k] where the output of the system is given by: VOU T [k] = qOUT vC [k]. While (A. (A.
In addition.2023 0.3628 AD = 0. the output current a constant 300 mA and each capacitor is initially discharged.63) BD 0. Figure A. and the discretetime timeindependent linear system model. developed in section A. once the discretetime parameters are found.1176 −0.0229 0. The calculated model matches well with the SPICE 188 .example.0725 = 0.1562 0.3.4. the system can be simulated with very little processor eﬀort.0030 −0. In addition.1375 −0.4.2889 −0.1332 0.0912 −0. The discretetime system parameters for the ladder converter are given approximately as follows: 0. developed in section A.2.0519 −0. shown in ﬁgure A.2.4.6498 (A. The discretetime linear system found in this section can be used to implement a statespace controller for an SC converter.1501 −0. is simulated using both the continuoustime timedependent linear system model.1276 −0. A switching frequency of 1 MHz is used.0564 0.0011 0.2949 0.1242 0.5316 0. The startup transient of the converter is simulated where the input voltage is a constant 3 volts.4185 0. A.5 plots the four capacitor voltages (where the output capacitor is labeled) using both the continuoustime and discretetime models. the results of a SPICE simulation of the ideal converter is overlaid using gray lines. The discretetime model results are shown as dots for each switching period.0020 0.4020 0. matching exactly with the continuoustime model (shown with solid lines).64) The output voltage is simply the last element of the state vector.4 Dynamics Simulation The 3:1 ladder converter.1564 (A. a switching frequency of 1 MHz is used such that T = 10−6 .
The linear models can be used to replace SPICE for circuit simulations of ideal SC converters and to create highperformance controllers.5 Output Voltage 0 0 1 2 3 4 5 Time [µs] 6 7 8 9 10 Figure A.2. the only diﬀerence stems from the diﬀerence in initial conditions between the two simulations. Simulation of the dynamics of 3:1 ladder converter simulation. 189 .5. The circuittheory based dynamic model for SC converter is straightforward to develop from the fundamental matrices describing an SC converter.5 2 Capacitor Voltages [V] C1 SPICE Continuous−time Model 1.5 1 C3 C2 0.
The ﬁrst section describes the functions which form the backbone of the analysis. Automating this manystep process is strongly desirable in order to speed up the design process. Each capacitor and switch is then sized relative to the other capacitors and switches. computerbased visualization is an important part of the design process as seen in chapters 3 and 8. assign device technologies to speciﬁc components in the technologies. Designing an SC converter by these methods involve ﬁrst choosing the correct topology and ﬁnding its charge multipliers and matching components with device technologies. including functions to formulate topologies. the total switch area.Appendix B MATLAB Package for SwitchedCapacitor Converter Design Chapters 2. and evaluate the loss for 190 . Finally. 3 and 4 develop a thorough design methodology for switchedcapacitor (SC) DCDC converters. This appendix describes (and gives source listings for) a set of MATLAB programs that automate the design and optimization of an SC converter. This package has been used to generate many of the contour and regulation eﬃciency plots in this work. Additionally. respectively. switching frequency and capacitor area must be chosen to optimize performance.
mikeseeman. The function is given by: topology = generate_topology (topology_name. topology returns a structure containing the charge multipliers and voltages of the individual components in the converter The output structure.e. generate topology. takes a string descriptor of a topology type (given in section 4. source listings of all the functions are given. denom]) topology name num a quoted name of the SC topology (i. ’SeriesParallel’.an implemented topology for speciﬁc operating conditions. and evaluate the loss of the converter at a certain operating point. num must be an integer. The charge multipliers and blocking voltages are generated based on the formulas in section 4.1 B. num [. implement topology and evaluate loss. and creates a topology data structure specifying the properties of the topology. If this parameter is included. The ﬁrst function. 191 .2.1 Core Functions The three functions in this section. The third section includes functions which are utilitarian in nature and used with other functions. form the core of the design package. has the following members: 1 The source code is provided digitally at http://www. topology.2) and a conversion ratio. generate topology. Must be a rational number denom nominal output voltage of the converter. Finally. These functions respectively specify the idealized topology structure. The second section discusses functions which perform certain analyses on SC topologies.com/thesis. followed by a section describing how to use the package for a practical example. ’Ladder’) a decimal version of the stepup ratio of the converter. and the conversion ratio is equal to num/denom. assign and size devices for each component.
topName a quoted name of the SC topology (i. ’Ladder’). A description of this structure follows. 192 .6) the nominal conversion ratio of the converter (greater than one for a stepup converter) This topology structure is fed into the function implement topology to choose and size devices to implement each component in the topology. as provided by generate topology ac a row vector containing the charge multiplier for each capacitor (not including the output source) vc vcb a row vector containing the nominal blocking voltages for each capacitor a row vector containing the nominal amplitude of the voltage ripple on the bottom plate parasitic of each capacitor ar vr vrb a row vector containing the charge multiplier for each switch a row vector containing the nominal blocking voltage of each switch a row vector containing the nominal amplitude of the voltage ripple on the sourcesubstrate capacitance of each switch Mssl Mfsl ratio the idealized slowswitchinglimit converter metric. generated from generate topology maximum input voltage of converter. compMetric) topology Vin topology structure. given in (4.5) the idealized fastswitchinglimit converter metric.e. given in (4. A description of this structure follows. The function is used as follows: implementation = implement_topology (topology. capTechs. ’SeriesParallel’. Vin. used for component voltage compatibility switchTechs a row vector of switch technology structures that are available for component implementation. capTechs a row vector of capacitor technology structures that are available for component implementation. switchTechs.
while 2 selects the parasiticlossbased metric.m ﬁle includes the structures for the ITRSbased idealized devices discussed in section 8. the total switch area would equal one square meter. Each structure contains data on an arbitrarilysized representative unit cell. the total capacitor area would equal one square meter. ITRS 90nm) 193 .1. The techlib. implementation returns a structure containing the technology structures for the selected devices. If this vector was multiplied by the size of each technologydependent unit cell. switch size a row vector containing the relative sizes of each switch in the converter. passed to implement topology capacitors a row vector containing the capacitor technology structure for each capacitor in the converter switches a row vector containing the switch technology structure for each switch in the converter cap size a row vector containing the relative sizes of each capacitor in the converter. The technology structures are contained in a library ﬁle. The capacitor structure has the following members: tech name a string describing the process technology (i.compMetric an integer specifying which metric to use when selecting switch technologies. plus the relative sizing of each device. Each structure is devoted to a single device in a speciﬁc technology.e. Any number of these structures can be applied to implement topology to choose for implementing a topology. 1 (default) speciﬁes the areabased metric. If this vector was multiplied by the size of each technologydependent unit cell. The implementation structure returned by implement topology contains the following members: topology the structure generated by generate topology. and executed before running implement topology.
accounting for density rules (in m2 ) conductance The conductance of the unitcell switch. ITRS 90nm) a string describing the particular device (i. of the unit cell device (in m2 ) bottom cap esr rating The bottomplate parasitic capacitance of the unit cell device (in F) The equivalent series resistance (ESR) of the unit cell device (in ohms) The maximum blocking voltage of the capacitor (in V) Similarly.dev name a string describing the particular device (i.e. Native 90nm NMOS transistor) area The die area of the unitcell switch. at very low VDS and full VGS (in S) gate rating The nominal gate drive voltage of the switch (at which the conductance was measured) (in V) drain rating gate cap The maximum blocking voltage of the device (in V) The average gate capacitance of the unit cell at the rated gate voltage (in F) drain cap The average drain capacitance of the unit cell at the nominal blocking voltage (in F) body cap The linearized sourcesubstrate capacitance of the unit cell at an average sourcesubstrate voltage (in F) To evaluate the loss of an implemented converter. Thinoxide PMOS oxide capacitor) capacitance area The capacitance (in F) of the unit cell device The die area.e. a ﬂexible approach must be taken. increased by any density rules. the switch technology structure has the following elements: tech name dev name a string describing the process technology (i. 194 .e.
195 . unspeciﬁed ones should be passed as an empty array ([]). Each matrix element is the result of evaluating the converter at the speciﬁc operating condition.2. set to [] for unregulated converters output current (in A) converter switching frequency (in Hz). Vout the actual average output voltage of the converter. the switching frequency is instead unconstrained. Asw. it is not changed. performance = evaluate_loss (imp. when regulation is considered. Ac) implementation structure for a single topology. as in section 3. If Vout is speciﬁed. the unspeciﬁed (endogenous) variables are found and the converter loss is found. The function evaluate loss takes all system parameters as an input. All inputs. can be either a scalar. If fsw is speciﬁed. Vin. At each point. generated from implement topology Vin Vout Iout fsw Asw Ac input voltage to the converter (in V) converter output voltage (in V). the output voltage is not constrained (it is a dependent or endogenous variable). column vector or matrix. Iout.3. Vout. except for the implementation structure. However. it is not changed. row vector. fsw the actual switching frequency of the converter.When investigating the design space with a contour plot. fsw. according to the inputs. Each of the following members is a matrix the size of the input parameter range. set to [] for regulated converters switch die area (in m2 ) capacitor die area (in m2 ) imp evaluate loss returns a single data structure denoted performance. Each is internally expanded into a matrix with a twodimensional parameter space.
efficiency total loss impedance dominant loss numerical eﬃciency of the converter. 1 indicates that the output voltage can be produced for a ﬁnite switching frequency. Iout.5 B.is possible a matrix where each element is 0 or 1. is possible is always 1. [optMethod. The second function.1 to create plots which aid in the development of SC converters. Ac. does not exceed 1 the total power dissipated in the converter (in W) total outputreferred impedance (in ohms) a code indicating the dominant loss component at the current design point dominant text a string referring to the dominant loss component at the current design point These three functions perform the backbone of the analysis functions in the next section. plot_opt_contour (topology. [plotAxes]]]]) 196 . switches. plots an eﬃciency contour plot over a twodimensional space of switching frequency and switch area for a given input voltage and output current. as in the unregulated case. [pointPlots. plot opt contour. [esr. plot regulation plots the eﬃciency of one or more SC converter topologies as either the input or output voltage is swept across a range while the other is held constant. The ﬁrst function. The code listings for the previous sections are in section B. Regulation is performed by varying switching frequency. When output voltage is unconstrained.2 Visualization Functions Two functions are included in the package which use the functions in section B. Vin. ratio. 0 indicates that no solution exists for the input conditions. capacitors.
log10 (ASW. 1 (default) speciﬁes the areabased metric.max ). ’Ladder’) or a topology or implementation structure ratio A rational conversion ratio for the topology named in topology. capacitors A row vector of capacitor technology structures.e.topology A string naming the SC topology used (i. log10 (fsw. Ac. Function plot regulation is given by: plot_regulation (topologies. switches. An example using plot opt contour and plot regulation is given in section B. plotPoints an integer specifying the number of plots in each dimension to evaluate the loss to create the contour plot.min ). When an implementation structure is passed into topology. see implement topology. 197 .min ). where switching frequency is in Hz and switch area in m2 .4. Vin. log10 (ASW. this value can be []. Vout. capacitors. It is in the form [log10 (fsw. This parameter is ignored if topology is a structure Vin Iout Ac switches The scalar input voltage for the converter (in V) The scalar output current of the converter (in A) The scalar total die area used for the capacitors (in m2 ) A row vector of switch technology structures. see implement topology esr Additional metalrelated series resistance to add to the analysis (default = 0 ohms) optMethod an integer specifying which metric to use when selecting switch technologies.max )]. Iout. while 2 selects the parasiticlossbased metric. A larger number results in smoother contours (default: 100) plotAxes A fourelement row vector specifying the desired plot axes (calculated automatically by default).
Each element can either be a twoelement row vector in the form [{’Topology’} {ratio}]. either a scalar or vector (in V) Output current. either a scalar or vector (in V) Output voltage. either as a scalar for constant output currents. this is used as the xaxis for the plot. [idesign]]) A column vector of topologies to be evaluated over regulation. This optimization may not ideally represent an actual converter. a topology structure or implementation structure. The sizing of each topology is optimized independently for the nominal operating point. or as a vector if the load current varies with either load or line voltage (in A) Ac switches capacitors The scalar total die area used for the capacitors (in m2 ) A row vector of switch technology structures. If omitted. see implement topology A row vector of capacitor technology structures. see topologies implement topology esr Additional metalrelated series resistance to add to the analysis (default = 0 ohms) idesign A row vector (each element corresponding to a topology) or scalar specifying the current for which each topology should be optimized for (in A). idesign is chosen automatically by interpolating the output current at the nominal conversion ratio. Vin Vout Iout Input voltage. Either the input or output voltage should be speciﬁed as a vector of sample points. The ratios according to each converter are noted next to the optimal point of each converter. 198 .[esr. plot regulation plots the eﬃciency of a number of topologies over a range of either input or output voltages.
Asw] = optimize_loss (implementation. each representing a topology that can be used in the second position (attached to the output of the ﬁrst topology and supplies the output source) 199 . [performance. Function optimize loss is used by plot opt contour and plot regulation for ﬁnding the mosteﬃcient operating point for a given input voltage and output current.B. Ac) implementation an implementation structure created by implement topology or similar method Vin Iout Ac the scalar input voltage for the optimization (in V) the scalar output current for optimization (in A) the scalar capacitor die area (in m2 ) the performance structure. as returned by evaluate loss. topologies2) topologies1 A column vector of m [{’Topology’} {ratio}] pairs or topology structures. These functions are described as follows. Iout. fsw.3 Helper Functions Two helper functions are included to perform utilitarian tasks. at the optimal point fsw Asw the optimal switching frequency (in Hz) the optimal switch die area (in m2 ) performance newtops = permute_topologies (topologies1. each representing a topology that can be used in the ﬁrst position (attached to the input source) topologies2 A column vector of n [{’Topology’} {ratio}] pairs or topology structures. Function permute topologies combines sets of topologies in cascade to form new hybrid topologies for use with the other functions. Vin.
First. This example will use the 65 nm process example from the ITRS roadmap. Next.4 Example The twostage variableratio SC converter discussed in section 5.newtops A column vector of length m · n containing topology structures.4. 200 . either works for the methods in this section. 7. Before any of the following code is run. Note the two methods of deﬁning the topology vectors. 7). 6. such as the converter in section 5. generate_topology(’Ladder’. generate_topology(’Ladder’. generate_topology(’Ladder’. Superior performance can be obtained by creating topology structures with the charge multipliers and blocking voltages from the optimized topologies. 8. all combinations of the ﬁrst topologies and second topologies are included Function permute topologies cascades two converters. 5. 7). into a larger variableratio converter. It is important to note that the arrangement of capacitors in the ladder topologies is not optimal for this application. representing all of the possible combinations. the vectors with the ﬁrst and second stage topologies will be deﬁned: topologies1 = [ generate_topology(’Ladder’. each of which can be a variableratio converter. the script containing the technology structures (techlib.4 will be used to demonstrate the abilities of this package. topologies2 = [ {’Dickson’} {1/3}. The resulting vector can be used with plot regulation to obtain a regulation curve for the variableratio converter. the two topology vectors will be cascaded and permuted: cascaded_tops = permute_topologies (topologies1. {’Dickson’} {1/2} ].m) should be run to load these structures into memory. B. 7) ]. 7). topologies2).
2. 201 . thickcap. itrs65cc = itrs65n. Additionally. used to block twice the voltage. It consists of two native NMOS devices in series. a highvoltage capacitor will be created (usually. Next. The input voltage is swept from 2 V to 5 V at an output current of 100 mA and a capacitor die area of 10 mm2 .01:5.drain_rating = itrs65n. First.area * 2.1. Superior performance can be obtained by creating topology structures with the charge multipliers and blocking voltages from the optimized topologies.capacitance = itrs65cap. . itrs65cc. thickcap = itrs65cap... 8)]. as it is close to the optimal point on the previous plot. The results of plot opt contour are shown in ﬁgure B. a thickoxide device would be used. itrs65cc. the regulation eﬃciency plot can be created. 0.area * 2. in this case.area = itrs65cap. Vin = 2:. 1. An input voltage of 3. itrs65cc. The result from plot regulation is shown in ﬁgure B. 1/2)])).conductance / 2. this topology structure will be created: topology = permute_topologies( [generate_topology(’Ladder’. Using these new devices.rating = itrs65cap.drain_cap * 2 + itrs65n.35 V will be used.. plot_regulation (cascaded_tops.2V). thickcap. 10e6. a cascode device will be created.capacitance / 2. it is important to note that the arrangement of capacitors in the ladder topologies is not optimal for this application.As one of the switches in the Dickson converter must block twice the output voltage (of 1. the contour plot will be created using the same modiﬁed devices as shown above. Next.1a.area = itrs65n.drain_rating * 2.drain_cap = itrs65n. [itrs65n itrs65cc]. .rating * 2. % copy topologies itrs65cc.. The optional axis parameter is used to bettercenter the plot.conductance = itrs65n. thickcap. [generate_topology(’Dickson’. a series device would be used solely for analysis purposes). [itrs65cap thickcap]). 7. Vin. Again.gate_cap.1b. the design point of the 16:7 conﬁguration will be examined.
4 10 −2 0.100 90 80 Efficiency [%] 2:1 3:1 70 60 12:7 16:7 18:7 24:7 10:7 15:7 50 40 30 2 2.05 0.1A.05 0.1 10 −3 0. Eff =67.05 0.1 Switch Area [mm2] 10 −1 0.05 0.05 7 10 10 8 10 Switching Frequency [Hz] 9 10 10 (b) plot opt contour Figure B.5 Input Voltage [V] (a) plot regulation 4 4.1 0.2 0.2 0. Example plots from the MATLAB package 202 .3 % 0.1.5 3 3. Ac =10 mm2. 2 0.1 0 IOUT =0.5 5 10 0.1 0.05 0.
1. . [itrs65cap thickcap]. 0.plot_opt_contour (topology. However. [itrs65n itrs65cc]. 203 . 100.35.1. 1. This MATLAB package enables quick design and application space investigation using SC converters. 0. devicelevel circuit simulations (e. 3. and the design can be rapidly iterated to achieve the best architecture for a given application.. 10e6. The eﬃciency of a converter can be estimated in very little time. SPICE) are necessary for a moreprecise estimate of eﬃciency..g. as many approximations are used in the analysis. [7 10 9 6]).
.capacitors..topology. else 20 25 30 35 40 204 . % Break implementation into components for brevity ac = imp.mikeseeman. Last Modified: 4/15/09 % Copyright 20082009. Vout.topology. sw_size = imp.com/thesis.1 1 evaluate loss.vr. B.topology. max(size(Vout).ar. if (size(Vout) == [0 0]) type = 1. vcb = imp. 2fsw Vin = expand_input(Vin. ar = imp.5 Code Listings The source code is provided digitally at http://www. type = 0. Vout = zeros(paramdim).topology. 1vout..vrb. size(Ac)))))). UC Berkeley % May be freely used and modified but never sold. % undefined: 0not yet set.m 5 10 15 function performance = evaluate_loss (imp. switches = imp. Ac) % evaluate_loss: evaluates the loss and other peformance metrics for a % specific size and operating condition of a implemented SC converter % % imp: implementation generated from implement_topology % Vin: converter input voltage for this calc [V] % Vout: converter output voltage for this calc [V] % Iout: converter output current for this calc [A] % fsw: switching frequency [Hz] % Asw: switch area [m^2] % Ac: capacitor area [m^2] % % Either fsw (in case of regulation) or Vout (in case of openloop % control) should be set to [] and will be found by this function.5.cap_size. vrb = imp. vr = imp. max(size(Iout). Mike Seeman. Iout. cap_size = imp. % % Created: 4/15/08.ac.B. Vin.vcb.topology. % Process (and expand) input parameters paramdim = max(size(Vin).switches. ratio = imp. max(size(fsw). caps = imp. vc = imp. The original author % must be cited in all derivative work.ratio.vc. max(size(Asw). paramdim). Asw. fsw.switch_size.topology.topology.
esr/cap_size(i)). end Asw = expand_input(Asw. fsw = zeros(paramdim).45 50 55 Vout = expand_input(Vout. paramdim). if (isfield(caps(i). if (size(fsw) == [0 0]) if (type == 1) error(’Both fsw and Vout cannot be undefined’).2). %%%%%%%%%%%%%%%%%%%%%%%%%% Start Analysis %%%%%%%%%%%%%%%%%%%%%%%%%%%% % Calculate SSL output resistance: Rssl_alpha = 0.2).. paramdim). Rfsl_alpha = Rfsl_alpha + 2*(ar(i)^2)/. paramdim). for i=1:size(switches.capacitance*cap_size(i))./Ac. (switches(i)./Asw.’esr’)). for i=1:size(caps. end Iout = expand_input(Iout. if (ac(i) > 0). else type = 2. if (ac(i) > 0). for i=1:size(caps. end end Rfsl = Rfsl_alpha.2). ’esr’)). Rssl_alpha = Rssl_alpha + (ac(i)^2)/(caps(i).conductance*sw_size(i)). end end end Resr = Resr_alpha. Ac = expand_input(Ac.esr. end % Find the unknown (endogenous) variable if (type == 1) 60 65 70 75 80 85 90 95 205 . end end % Calculate FSL output resistance: Rfsl_alpha = 0. Resr_alpha = Resr_alpha + 4*(ac(i)^2)*(caps(i). % Calculate additional ESR loss: Resr_alpha = 0.. Resr = Resr + imp. paramdim). if (isfield(imp. paramdim). end else fsw = expand_input(fsw. if (ar(i) > 0).
*Vin.^2.* Ac).*Iout.^2).2). end Pc = Pc_alpha.^2.. Psw_alpha = Psw_alpha + ((switches(i).gate_rating.^2. % Calculate Caprelated Parasitic loss: Pc_alpha = 0.*Ac. Pc_alpha = Pc_alpha + (caps(i).% Vout is unknown Rssl = Rssl_alpha .Vout). 105 110 115 120 125 130 135 145 150 206 ./ (Rssl ./Iout.*Asw. elseif (type == 2) % fsw is unknown % Calculate needed output impedance and switching frequency to match % output voltage % is_prac is 1 if a finite fsw which satisfies Iout. Pg_alpha = Pg_alpha + (switches(i). is_prac = ((Rreq > 0) & (Rfsl+Resr < Rreq)).*Iout.. Pg_alpha = 0. end Psw = (Psw_alpha. Vout exists Rreq = (Vin*ratio .*Iout.^2 + (Rfsl + Resr). % Calculate total output resistance: Rout = sqrt(Rssl.*Ac).(Rfsl+Resr). else error(’Either Vout or fsw must be []’).gate_cap*sw_size(i)) * (Vgssw)^2.^2).*Iout.drain_cap*sw_size(i)) * (vr(i))^2 + .*fsw. for i=1:size(switches. Pesr = Resr. Vout = Vin*ratio . end % Calculate resistance losses: Pssl = Rssl.Rout.^2)).body_cap*sw_size(i)) * (vrb(i))^2).^2.*Iout. 100 % Calculate total output resistance: Rout = sqrt(Rssl.*Vin. % Calculate Switchrelated Parasitic loss: 140 Psw_alpha = 0./ (fsw. fsw = Rssl_alpha . is_prac = ones(paramdim).^2 + Pg_alpha).*fsw. (switches(i).bottom_cap*cap_size(i)) * (vcb(i))^2. % Assume switch is driven at full gate_rating voltage Vgssw = switches(i).2).*Iout.^2 .*Iout. for i=1:size(caps.^2 + (Rfsl + Resr). Pout = Vout. Pfsl = Rfsl. Pout = Vout.^2. Pres = Rout. Rssl = real(sqrt(Rreq. Vin.
fsw = fsw.. Ploss = Pres + Pc + Psw. elseif (size(input) == [maxsize(1) 1]) % column vector input result = input * ones(1.list unknown system parameters performance. den) 207 .1) * input. elseif (size(input) == [1 maxsize(2)]) % row vector input result = ones(maxsize(1). else % input is not properly sized error(’All inputs must have the same number of rows and columns (if not 1)’). Psw(i. % Subfunction that turns input into a (maxsize) matrix function result = expand_input (input. performance.:)]). [temp. % list performance performance. % create structure . texts = [{’SSL Loss’} {’FSL Loss’} {’ESR Loss’} {’BottomPlate’}. maxsize) if (size(input) == [1 1]) % scalar input result = input * ones(maxsize).. maxsize(2)). IND = [IND. performance. result = 0. ind] = max([Pssl(i.dominant_loss = IND.dominant_text = texts(IND).2 1 generate topology.is_possible = is_prac.:).5.m function result = generate_topology (topology_name. efficiency. performance. etc.:). num. {’Switch Parasitic’}].1).:). IND = [].total_loss = Ploss.impedance = Rout./(Pout+Ploss). result = 0. for i=1:size(Pssl.. performance.:). ind] = max([Pssl Pfsl Pc Psw]). end 165 170 175 180 185 190 195 B. elseif (size(input) == [0 0]) error(’Only fsw or Vout can be empty’). Pfsl(i. eff = Pout. Pc(i.155 160 % Calculate total loss. Pesr(i. elseif (size(input) == maxsize) % input already a properlysized matrix result = input. performance.Vout = Vout. performance. end %[temp.. ind].efficiency = eff.
elseif (j == (nm+1)).5 10 15 % generate_topology: Topology charge and voltage multiplier generation % % result = generate_topology (topology_name. both are integers. vr = [vr i/m]. CockcroftWalton.m*(nm))/m. for i=1:m. den] = rat(num. % if a straight ratio passed in. % indicate that the converter has been ’flipped’ end %%%%%%%%%%%%%%%%%% SeriesParallel %%%%%%%%%%%%%%%%%%%%%%%%%% if (strcmpi(topology_name. if (num/den < 1). 20 25 30 35 40 45 50 208 . for i = 1:m. Dickson. . at first. break it up into numerator and denominator if nargin < 3. flip = 1. [num. % Doubler. num is a rational number. UC Berkeley % May be freely used and modified but never sold. Mike Seeman. vrb = []. vcb = []. n = num. SeriesParallel. den]) % topology_name: Name of SC topology {Ladder. if (j == 1). t = den. end end % FSL values vr = []. N = n. den: the ratio of output voltage to input voltage. % % Created 4/14/08. % num/den is the stepup conversion ratio of the converter. vcb = [vcb (i+j1)/m]. vc = ones(1. m = den. v’s in terms of input voltage flip = 0. % % result: structure with charge multiplier and voltage vectors for % capacitors and switches. % SSL values ac = ones(1. for j=1:(nm). num = t.m*(nm))/m.001). vr = [vr (nm1+i)/m]. for j = 1:(nm+1). vrb = [vrb (i+j1)/m]. Otherwise. Last Modified 4/15/09 % Copyright 20082009. den = num. Fibonacci} % num. The original author % must be cited in all derivative work.’SeriesParallel’)). num [. If denom is % omitted. end % generate ac’s for stepup only.
vcb = []. end if ((i==1)  (i==(m+1))).’Ladder’)). end end end for i=1:m+1. else vrb = [vrb (i+j2)/m]. % SSL values ac = [].2)/m. vc = [vc 1/m 1/m].2*(nm)) (n/m1)*ones(1. vc = [vc 1/m].55 vrb = [vrb (i+j2)/m].2*n)/m. for j=1:(nm1). end % FSL values ar = [ones(1. m = den.2)*(j*(n/m1))]. for j=(m1):1:1. vrb = mod(0:(2*n1). for j=1:nm. vrb = [vrb (i+j1)/m]. N = n.2*m)]. end ac = [ac (nm)]. ac = [ac ones(1. vcb = [vcb 1/m]. vr = [vr (m1+j)/m]. vr = ones(1. else vr = [vr 1/m]. 60 65 70 75 80 85 90 95 100 105 209 . vc = []. vc = [vc 1/m 1/m]. n = num. vcb = [vcb 1/m 0]. ac = [ac j j]. vr = [vr j/m]. %%%%%%%%%%%%%%%%%% Ladder %%%%%%%%%%%%%%%%%%%%%%%%%% elseif (strcmpi(topology_name. else vr = [vr 1/m]. end end end ar = ones(size(vr))/m. vcb = [vcb 1/m 0]. elseif (i==(m+1)). if (i==1). vrb = [vrb 0].
110 115 120 125 130 %%%%%%%%%%%%%%%%%% Dickson %%%%%%%%%%%%%%%%%%%%%%%%%% elseif (strcmpi(topology_name.N)]. ’CockcroftWalton’)).N2). % SSL values ac = ones(1. end % FSL values if (N == 2). ac = [floor((j+1)/2) ac]. vrb = [0 1 0 1].5) 2*ones(1. vr = ones(1. vrb = [0 1 0 1 ones(1. if (den ~= 1) error(’SWITCHCAP:nonIntegerRatio’. 135 140 145 150 155 160 210 . vr = [ones(1.’Doubler’)).4). for j=1:(N1). vr = [ones(1. ’the CockcroftWalton topology supports integer ratios only’).N1). ar = [floor((j+1)/2)*[1 1] floor((j)/2)*[1 1] ones(1.5) 2*ones(1. end N = num.. for j=1:(N1). % SSL values ac = []. vc = []. ar = ones(1.. end % FSL values if (N == 2).. else. 1]. vrb = [0 1 0 1 ones(1.N)]. vcb = ones(1. end %%%%%%%%%%%%%%%%%% CockcroftWalton %%%%%%%%%%%%%%%%%%%%%%%%%% elseif (strcmpi(topology_name.. ar = ones(1.4).N)]. vc = [1 2*ones(1. end %%%%%%%%%%%%%%%%%% Doubler %%%%%%%%%%%%%%%%%%%%%%%%%% elseif (strcmpi(topology_name.4). if (den ~= 1) error(’SWITCHCAP:nonIntegerRatio’.. vcb = ones(1.N)]. vrb = [0 1 0 1].4). ar = [floor((j+1)/2)*[1 1] floor((j)/2)*[1 1] ones(1.N2)]. else.N2) 1]. ’the Dickson topology supports integer ratios only’).’Dickson’)).. end N = num.N1). vr = ones(1. vc = [vc j].N1).
4)*2^(j1)].2)]. ’the fibonacci topology supports ratios of F_n or 1/F_n only’). vrb = []. end i = 2. end % FSL values ar = []..4)*2^(nj)]. vc = []. ’the doubler topology supports conversion ratios ~ 2^n’). vc = []. vc = [vc fibfun(j)]. vr = [vr ones(1. if (den ~= 1) error(’SWITCHCAP:nonIntegerRatio’.. i = i+1. vc = [vc 2^floor(j/2)]. vr = []... end n = ceil(log2(num)).. 175 180 185 190 195 200 205 210 211 . error(’SWITCHCAP:badRatio’. for j=1:n. ’the Fibonacci topology supports integer ratios only’).. ’the Doubler topology supports integer ratios only’)... % SSL Calculation ac = []. end N = fibfun(i).’Fibonacci’)).. vrb = [vrb [0 1 0 1]*2^(nj)].. ac = [2^floor((j1)/2) ac]. for j=1:(2*n1). ar = [ar ones(1. ac = [fibfun(j1) ac]. for j = 2:i1.. vcb = []. N = 2^n. end if (fibfun(i) > num) error(’SWITCHCAP:badRatio’.. while (fibfun(i) < num). vcb = [vcb 2^floor(j/2)*mod(j. if (N ~= num). end % SSL values ac = [].165 170 if (den ~= 1) error(’SWITCHCAP:nonIntegerRatio’. vcb = []. end %%%%%%%%%%%%%%%%%% Fibonacci %%%%%%%%%%%%%%%%%%%%%%%%%% elseif (strcmpi(topology_name.
vrb = vrb.5. Vin.ar = ar. result.ratio = ratio. for j = 2:i1. 235 240 245 250 B.. result. Mfsl = ratio^2/(2*(ar*vr’)^2). % bottom plate voltage vector result. for NMOS result. Vin.topName = topology_name. vrb = vrb/ratio. compMetric) % implement_topology: matches components with switches and components in % the topology. result.3 1 implement topology. % body swing voltage.Mssl = Mssl.Mfsl = Mfsl. vrb = [vrb fibfun(j1) 0 fibfun(j1)]. vr = []. result.. capTechs. vcb = vcb/ratio. % capTechs. vr = [vr fibfun(j) fibfun(j) fibfun(j1)]. end % FSL Calculation ar = [1]. switchTechs. result. vr = vr/ratio.ac = ac.vcb = vcb. ac = ac/ratio. if (flip == 1). result.vc = vc. compMetric) % topology: structure created by generate_topology % Vin: input voltage of converter 212 . vc = vc/ratio.215 220 225 end vcb = [vcb fibfun(j1)]. ar = ar/ratio.m 5 function implementation = implement_topology(topology.. 230 % Compute ideal metrics Mssl = 2*ratio^2/(ac*vc’)^2. end result. vrb = [0]. % implementation = implement_topology(topology. result. switchTechs. ar = [fibfun(j) fibfun(j1) fibfun(j1) ar]. end vr = [vr fibfun(i2)].vr = vr. ratio = num/den. ratio = 1/ratio.
if (M > Mc) if (Mc == 0). let’s see if it’s good % Use arealimited metric.2).2). else cap_assign(i) = capTechs(j).. 35 % Assign Capacitors for i=1:size(ac. num2str(vc(i)))).10 15 % switchTechs: an array of technology structures available for switch use % capTechs: an array of technology structures available for cap use % compMetric: a metric (1=area. error(strcat(’No capacitors meet the voltage requirement of: ’. % Cap could work .ac. end 20 25 30 switch_assign = []. Cc = C. vcb = topology. vc = topology. Last Modified: 4/15/09 % Copyright 20082009.capacitance*vc(i)^2/C. if (vc(i) <= capTechs(j). end 40 45 50 55 60 213 .vc*Vin. cap_assign = [cap_assign capTechs(j)].. Cc = 0.vcb*Vin. end Mc = M. cap_rel_size = []. ac = topology.. M = capTechs(j).ratio. UC Berkeley % May be freely used and modified but never sold.ar. % cap cost.rating). switch_rel_size = []. Mike Seeman. 2=loss) used for determining the best % component (1=default) % Created 4/15/08. Mc = 0. % Break out components of topology structure ratio = topology. vr = topology. if (nargin < 5) compMetric=1.vrb*Vin. cap_assign = []. for j=1:size(capTechs. ar = topology.area. which is usually applicable C = capTechs(j).vr*Vin. end end end % check to make sure a suitable device exists if (Mc == 0).. The original author % must be cited in all derivative work. vrb = topology..
65 % determine relative device size if (ac(i) == 0).. switch_rel_size = [switch_rel_size (ar(i)*vr(i))/. 214 .. end if (M > Msw) if (Msw == 0)... % switch cost. switchTechs(j).gate_rating^2 + ...drain_cap*vr(i)^2 + . for j=1:size(switchTechs. Csw = C. end end 70 75 80 85 90 95 100 105 110 % Assign Switches for i=1:size(ar. (sqrt(Mc)*cap_assign(i). switch_rel_size = [switch_rel_size 0].. (sqrt(Msw)*switch_assign(i). else switch_rel_size = [switch_rel_size (ar(i)*vr(i))/.conductance*vr(i)^2/C.conductance*vr(i)^2/C. cap_rel_size = [cap_rel_size 0]. else switch_assign(i) = switchTechs(j). switchTechs(j). % Switch could work . % loss metric % assume full gate drive C = switchTechs(j). else % area metric C = switchTechs(j).2).conductance)]. M = switchTechs(j).. switch_assign = [switch_assign switchTechs(j)].gate_cap*switchTechs(j). M = switchTechs(j). Csw = 0..2).area)]. if (vr(i) <= switchTechs(j). end end end % check to make sure a suitable device exists if (Msw == 0).. % avoid divide by 0 else cap_rel_size = [cap_rel_size (ac(i)*vc(i))/. num2str(vr(i)))). else if (compMetric == 2). error(strcat(’No switches meet the voltage requirement of: ’. Msw = 0.body_cap*vrb(i)^2.. let’s see if it’s good if (compMetric == 2). end % determine relative device size if (ar(i) == 0)... end Msw = M.area.drain_rating)...
’MaxIter’. Asw] = optimize_loss (implementation.. implementation. Vin.switches = switch_assign.cap_size = cap_size.m 5 10 15 function [performance. % Scale Switches for unit area: 125 130 sw_area = 0. fsw. options = optimset(options.4 1 optimize loss. options = optimset(’fmincon’).capacitors = cap_assign.area. for i=1:size(ar. % Scale Caps for unit area: cap_area = 0. UC Berkeley % May be freely used and modified but never sold.2). The original author % must be cited in all derivative work. 400000.*(sw_area > 0)). 135 140 B.area)]../(sw_area+(sw_area == 0)). end cap_size = cap_rel_size. implementation. implementation. UC Berkeley % % optimize_loss(implementation. 1e11.. . Ac) % optimize_loss: Finds the optimal design point for given conditions % Michael Seeman. end switch_size = (switch_rel_size./(cap_area+1e30). Mike Seeman. implementation. Ac) % implementation: implementation generated from implement_topology % Vin: converter input voltage for this calc [V] % Iout: converter output current for this calc [A] % Ac: capacitor area [m^2] % % Returns: performance structure from evaluate_loss and optimal switching % frequency and switch area % % Created 4/14/08. Last modified: 4/15/09 % Copyright 20082009. Vout.5. Iout.2). Iout. .topology = topology. for i=1:size(ac. ’TolFun’.115 end end end 120 (sqrt(Msw)*switch_assign(i). % Create implementation structure implementation..area. 20 215 . cap_area = cap_area + cap_rel_size(i)*cap_assign(i). sw_area = sw_area + switch_rel_size(i)*switch_assign(i).switch_size = switch_size.
[]. exp(param(2)). Iout.. Ac) p = evaluate_loss (implementation.m 5 10 function newtops = permute_topologies (topologies1. cell2mat(top2(2)))]. topologies2) % newtops = permute_topologies(topologies1. 30 %.2) == 2) & (size(top2. top2. UC Berkeley % May be freely used and modified but never sold. [100 1]. The original author % must be cited in all derivative work. elseif ((size(top1. Vin.2) == 1) & (size(top2. newtops = [newtops. 1)]. cell2mat(top1(2)).. elseif ((size(top1. Iout.Minimization helper function function ploss = evaluate_loss_opt (param. []. top2 = topologies2(n.:). Vin.2) == 1)). Last modified: 4/15/09 % Copyright 20082009. topologies2) % topologies1. 15 20 25 30 216 . cell2mat(top2(1)).. Ac). . Asw = exp(opt_design(2)). 35 B. cell2mat(top1(2)). 1. returns a vector of topologies % consisting of every permutation of topologies in the first vector % connected in series (cascaded) with the topologies in the second % vector. 1. newtops = [].. implementation. top2. newtops = [newtops. ’off’.. Vin. Mike Seeman. [].:). topologies2: column vectors of either topology % structures or [{’Topology Name’} {ratio}] pairs % % For two vectors of topologies. cell2mat(top2(1)). cascade_topologies(cell2mat(top1(1)).1). [1 100].. fsw. ploss = p.2) == 2) & (size(top2. Asw.. elseif ((size(top1.2) == 2)). . Iout.2) == 1)). Iout. []. if ((size(top1. cell2mat(top2(2)))].5 1 permute topologies. % returns an (n*m) vector of topology structures top1 = topologies1(m. cascade_topologies(cell2mat(top1(1)). cascade_topologies(top1. []..5. options. 1)]. % % Created 10/08. newtops = [newtops.. for n=1:size(topologies2. []..total_loss.2) == 1) & (size(top2. implementation.25 ’Display’. [10 10]. exp(param(1)). cascade_topologies(top1. []. fsw = exp(opt_design(1)). ’LargeScale’.1). ’off’). Vin. . newtops = [newtops. for m=1:size(topologies1.2) == 2)). . .. .. performance = evaluate_loss(implementation. Ac). Ac). opt_design = fmincon(@evaluate_loss_opt.
Helper: cascade_topologies function newtop = cascade_topologies(topology1.Mfsl = newtop. . Ac.5. topology2.topName). capacitors % [esr.ac]..vr’)^2).ac.35 end end end 40 % .ratio^2/(newtop.*ratio2 topology2. ratio2 = topology2..ratio^2/(2*(newtop.vrb = [topology1.vc’)^2.vc. newtop. including lossdominant regions % Michael Seeman. [optMethod.topName.ar]. scale topology1.ar. ratio.vcb. [plotPoints.ratio*topology2. newtop. % Ignored for topology as a structure % Vout: Output voltage of converter (in V) % Iout: Output current of converter (in A) % Ac: Capacitor area constraint (in m^2). UC Berkeley % % plot_opt_contour(topology. switches.*ratio1]. newtop.ratio. ratio2).vcb = [topology1. [plotAxes]]]]) % topology: The chosen topology to plot contour (a string).vrb. end if (ischar(topology2)).6 1 plot opt contour. capacitors.vcb topology2. Iout.ar = [topology1.vc topology2.ac = [topology1. newtop. Ac.vr. fsw and Ac will be swept % switches: a row vector of switch technology structures 217 .vc = [topology1.vrb topology2. topology2. use a fractional ratio (ie.a* by ratio2 newtop. end ratio1 = topology1. newtop. 1/8). plotAxes) % plot_opt_contour: Plot optimization contour. optMethod. or a % topology structure or implementation structure % ratio: The stepup ratio of the converter.m 5 10 15 function plot_opt_contour(topology.ratio = topology1. 60 65 B. ratio. newtop. ratio1. newtop. topology2 = generate_topology(topology2.Mssl = 2*newtop. 45 50 55 % scale topology2. Vout.ac*newtop.*ratio1].vr topology2. topology1 = generate_topology(topology1.*ratio1]. If a stepdown % converter is desired.ratio. newtop. esr.ratio.*ratio1].v* by ratio1. ’ > ’. ratio2) % cascade_topologies: Combine two topologies into a single topology where % the two topologies are cascaded in a series fashion where topology1 % interfaces with the input and topology2 interfaces with the output if (ischar(topology1)). newtop. Vin. switches. plotPoints.topName = strcat(topology1.vr = [topology1.ar*newtop.*ratio2 topology2. ratio1). Pout.
Asw_max = ceil(log10(Asw_opt)+1). output referred imp.ratio. 1mm^21000mm^2). (default=100) plotAxes: A row vector giving the desired range of the plot. error(’plot_opt_contour requires at least seven inputs’). The original author 30 % Fix unspecified parameters: if nargin < 7.ratio. fsw_max = ceil(log10(fsw_opt)+1). Asw_opt] = optimize_loss(imp.20 25 % % % % % % % % % % % % % capacitors: a row vector of capacitor technology structures esr: the outputreferred constant esr of requisite metal (ie. % topology is an implementation structure imp = topology. end % Constant series resistance. switches. if nargin < 9. in log input (ie. Vin. esr = 0. switches. plotPoints=100. Created 4/14/08. UC Berkeley May be freely used and modified but never sold. must be cited in all derivative work. optMethod). else fsw_min = plotAxes(1). capacitors. 35 40 45 50 55 60 65 218 . optMethod=1. 2=parasitic loss) plotPoints: specifies grid size for contour plot. Vin. Iout. imp = implement_topology(topology. ’topology’)).topology. else % topology is a topology structure ratio = topology. fsw_opt. fsw_max = plotAxes(2). Last modified: 4/15/09 Copyright 20082009.Vout if (nargin < 11). Mike Seeman. Vin. capacitors. end. fsw_min = floor(log10(fsw_opt)1). Asw_min = plotAxes(3). end if (ischar(topology)). topology = imp. end if nargin < 10.esr = esr. ratio). optMethod). imp = implement_topology(topology. [6 9 6 3] goes from 1MHz1GHz. Ac). if nargin < 8. bond wires). end. opt_perf. elseif (isfield(topology. Asw_min = floor(log10(Asw_opt)1). % Find optimal point for auto axis scaling [opt_perf. Default = 0 optMethod: specifies constraint on switch optimization (1=area (default). Asw_max = plotAxes(4). ratio = topology. % topology is a string topology = generate_topology(topology.
Pout.h). Vout. Vin. Ac. min1 = min1(min2).85 . title(strcat(’I_{OUT} = ’. Last modified: 4/15/09 219 .plotPoints)). ’b’). Vin. idesign) % plot_regulation: Plot efficiency vs. [c. min1] = max(p..h] = contour(fsw.. . Asw*1e6.’Yscale’. []. Vin.’log’) 80 85 90 B.5 3. [1.1 .m 5 10 15 20 25 function plot_regulation(topologies. hold off. ’k’).7 1 plot regulation.7 . hold on. A_{c} = ’. num2str(Iout). Vout. . ylabel(’Switch Area [mm^2]’). fsw. Iout. loglog(fsw(min1. Asw*1e6. capacitors.. p.5.efficiency).8 . switches. xlabel(’Switching Frequency [Hz]’).min2)*1e6.98 1].’log’) set(gca.Asw_max...5 2. input/output voltage based on fswbased % regulation % Michael Seeman. min2] = max(maxeff1’). switches.05 .dominant_loss. Asw] = meshgrid(logspace(fsw_min. logspace(Asw_min. num2str(maxeff*100. ’A. ’bo’).5]. UC Berkeley % % plot_regulation2(topologies. [esr. Ac).’Xscale’... [maxeff1. bond % wires).plotPoints).6 . capacitors % [noplot. clabel(c. 75 p = evaluate_loss(imp. ’ mm^2. fsw will be swept. Eff = ’. p..96 . Iout. set(gca.5 4. Default = 0 % idesign: a vector (size = number of topologies) containing the % nominal design current for each topology % % Created 6/30/08. num2str(Ac*1e6). Asw(min1. % {’Ladder’} {1/3}] % or a column vector of topology or implementation structures % Vin: Input voltage of converter (could be a vector) % Vout: Output voltage of converter (a vector if Vin is a scalar) % Iout: Matching vector of output currents [A] % Ac: Capacitor area constraint (in m^2)..9 .92 . [.fsw_max. [maxeff.. ’ %’)).efficiency.94 . contour(fsw. Asw % will be chosen automatically % switches: a row vector of switch technology structures % capacitors: a row vector of capacitor technology structures % esr: the outputreferred constant esr of requisite metal (ie.4 . esr. Ac. [optMethod]]]) % topologies: A matrix of topologies and ratios: % [{’SeriesParallel’} {1/2}.70 end [fsw. Asw.min2).2 .3).
indim). topology = imp. % implementation structure imp = topologies(t). Mike Seeman. indim = size(Vout. error(’Cannot sweep both Vin and Vout’). The original author % Fix unspecified parameters: if nargin < 7.topology. esr = 0. indim = size(Vin.1))). capacitors. ratio). xval = Vin. optMethod). for t=1:numtops.ratio.2) == 1) && (isfield(topologies(t). ratio = cell2mat(topologies(t. Vin_nom.2)). = [].2). % 1 = Vout. ’topology’))). elseif ((size(topologies. end if nargin < 8. if (iscell(topologies(t. % number of topologies 35 40 45 50 55 60 Vin_nom = Vin. topology = generate_topology(top. error(’plot_opt_contour needs at least seven input arguments’).2) > 1) type = 1. = []. UC Berkeley May be freely used and modified but never sold.2) == 1). ratio = topology.1). 65 70 75 220 . end type = 2. switches. Vin_nom = Vout/ratio.2). . % this topology is a string and ratio top = topologies(t. if (type == 2).2) > 1) if (type == 1). Vin_nom = Vout/ratio. type = 0. end imp = implement_topology(topology. if (type == 2).% % % 30 Copyright 20082009.1).. must be cited in all derivative work. EFF = ASW = pkeff pkv = RATIO FSW = zeros(numtops. [].. []. end elseif (size(topologies. xval = Vout. end optMethod = 1. topology = topologies(t). []. 2 = Vin swept if (size(Vout. end if (size(Vin. end numtops = size(topologies.
2). % end plot(xval.esr = esr. end % add topology ratio to vector for plot annotation RATIO = [RATIO ratio].:)).:) = p(t). []. pkv.*p(t). fsw_opt. num2str(n))). 120 125 130 221 . switches. . xlabel(’Output Voltage [V]’). pkv(t) = xval(i). Iout. Asw_opt] = optimize_loss(imp. FREQ(t. xval.:) = p(t). if (type == 1). Vin*ratio.efficiency. Vin_nom. 105 % % Find optimal point for base [opt_perf. Iout_nom = idesign. ’extrap’). ’bo’).2) > 1). maxeff*100. Vout. Iout_nom. end end % Constant series resistance. p(t) = evaluate_loss(imp.i] = max(EFF(t.. EFF*100. xlabel(’Input Voltage [V]’). end else if (size(idesign. mind] = max(EFF). Iout. Asw_opt.2) == indim)) Iout_nom = interp1(Vout.2). % for i=1:size(FREQ.is_possible. else error(’Unknown topology element’). output referred imp.001). text(pkv(i)*1. [n. m] = rat(RATIO(i). elseif (type == 2).fsw. 110 % 115 end [maxeff. end % add labels representing conversion ratios for i=1:size(pkv. % fsw(i) = FREQ(mind(i). Vin_nom.ratio. else. pkeff*100. Vin_nom = Vout/ratio. 90 95 100 % calculate nominal design current if (nargin < 9) if ((type == 1) & (size(Iout.01. end imp = implement_topology(topology.i). if (type == 2). ’linear’.. pkeff(i)*100+1.80 85 ratio = topology. . ’:’. strcat(num2str(m). ASW(t) = Asw_opt. Ac). optMethod). else Iout_nom = max(Iout). capacitors. [y.’b:’. pkeff(t) = y. Vin. Iout_nom = idesign(t). ’b’. EFF(t. Ac).
5.capacitance = 40^2*.capacitance = 40^2*1e15*.bottom_cap = 135.45/.9e15*. % in m^2 itrs65cap. % in F itrs65cap.end ylabel(’Efficiency [%]’).2.2.esr = 0. % in ohms itrs32cap.3e15. itrs45cap. itrs65cap. % in V % 32 nm Oxide Capacitors itrs32cap. itrs65cap. itrs90cap.2.tech_name = ’ITRS 65nm’. itrs90cap. itrs90cap.area = (40e6*40e6). itrs32cap. % in V The original author 5 10 15 20 25 30 35 40 45 222 .bottom_cap = 135.3e15.rating = 1.rating = 1.3e15.7/.capacitance = 40^2*. % in m^2 itrs32cap. % in F itrs32cap.esr = 0. itrs32cap.5/. % in F itrs90cap.09.capacitance = 40^2*.area = (40e6*40e6).dev_name = ’ITRS 65nm Oxide Capacitor’. % in ohms itrs90cap. % .tech_name = ’ITRS 32nm’. B.Oxide Capacitors % 90 nm Oxide Capacitors itrs90cap.bottom_cap = 135. itrs32cap. % in V % 65 nm Oxide Capacitors itrs65cap. % in m^2 itrs45cap. Mike Seeman. % in F itrs45cap.bottom_cap = 135. itrs45cap.area = (40e6*40e6).032.065.2.esr = 0. UC Berkeley % May be freely used and modified but never sold. % in m^2 itrs90cap.esr = 0.tech_name = ’ITRS 45nm’.area = (40e6*40e6). % in ohms itrs45cap. itrs45cap. % must be cited in all derivative work.8e15*. % in V % 45 nm Oxide Capacitors itrs45cap.dev_name = ’ITRS 90nm Oxide Capacitor’.rating = 1.3e15.dev_name = ’ITRS 45nm Oxide Capacitor’.6/.84e15*.tech_name = ’ITRS 90nm’.dev_name = ’ITRS 32nm Oxide Capacitor’.8 1 techlib.rating = 1. itrs65cap. % in ohms itrs65cap.m % Technology Library % Copyright 20082009.045.
% in m^2 fillercap. % in m^2 itrs22cap.esr = 0.4/. % in F itrs16cap. % in F fillercap. % in ohms itrs22cap. itrs90n.016*. itrs16cap.gate_cap. % in S itrs65n. % 65 nm switch itrs65n.25. % in V % 16 nm Oxide Capacitors itrs16cap.% 22 nm Oxide Capacitors itrs22cap.rating = 1.9e15.35. itrs65n.rating = 12. % in m^2 itrs65n.gate_cap = .48e15*. % in ohms fillercap.capacitance = 40^2*.rating = 1.016. % in m^2 itrs90n.gate_rating = 1.3e15.dev_name = ’ITRS 22nm Oxide Capacitor’. itrs90n.tech_name = ’ITRS 90 nm’.capacitance = 40^2*.33*itrs90n. % in V % Filler HV cap fillercap.drain_cap = .dev_name = ’ITRS 65 nm NMOS native transistor’. % in F itrs22cap.gate_cap = 1e15.drain_rating = 1.01.3e3.esr = 0.dev_name = ’ITRS 16nm Oxide Capacitor’.25.022.conductance = 1.4.25.area = (40e6*40e6).gate_cap.2. % in S itrs90n.3e15. itrs16cap.bottom_cap = 135. % in V itrs65n.dev_name = ’ITRS 16nm Oxide Capacitor’.tech_name = ’ITRS 16nm’.Switch models % 90 nm switch 80 itrs90n.drain_rating = 1.area = (40e6*40e6).35/. itrs22cap. 50 55 60 65 70 75 85 90 95 223 . fillercap.11e3. itrs16cap.bottom_cap = 135.tech_name = ’ITRS 65 nm’. itrs65n.tech_name = ’ITRS 22nm’.25.conductance = 1. % in V % .35/. fillercap. itrs22cap. % in ohms itrs16cap. % in V itrs90n. % in m^2 itrs16cap.area = 1e6 * 65e9 / .2*itrs90n.dev_name = ’ITRS 90 nm NMOS native transistor’. itrs90n.2.capacitance = 40^2*. itrs90n.area = (40e6*40e6).esr = 0.body_cap = .48e15*. fillercap.area = 1e6 * 90e9 / .58e15*.bottom_cap = 135. itrs22cap.tech_name = ’ITRS 16nm’. itrs90n.gate_rating = 1. itrs65n.3e15.
48e15. % 16 nm switch 115 120 125 130 135 140 itrs16n.drain_rating = 1.tech_name = ’ITRS 16 nm’.conductance = 1. itrs32n.gate_cap. % in V itrs16n. itrs16n.gate_cap.51e3. itrs32n. itrs32n.body_cap = .drain_rating = 1. 145 224 .dev_name = ’ITRS 45 nm NMOS native transistor’.area = 1e6 * 22e9 / .3.tech_name = ’ITRS 32 nm’.gate_cap = .25.gate_cap.33*itrs22n.conductance = 2.tech_name = ’ITRS 45 nm’. % in m^2 itrs16n. % in V itrs22n.82e3.dev_name = ’ITRS 22 nm NMOS native transistor’.gate_cap.25. itrs45n. % 32 nm switch itrs32n.84e15.gate_cap. % in S itrs22n. % in S itrs32n. % in V itrs32n. itrs16n.drain_cap = .25.25.25.25.25. itrs45n.245e3.drain_cap = .25.area = 1e6 * 16e9 / . % in m^2 itrs32n.gate_cap.gate_cap.535e3. itrs45n.58e15.gate_rating = 1.35.body_cap = . % in S itrs16n.33*itrs32n.area = 1e6 * 45e9 / .25. itrs16n.gate_cap.100 itrs65n.gate_cap = .body_cap = .gate_cap = .body_cap = .gate_cap.conductance = 1.drain_cap = .33*itrs65n. itrs16n.3.conductance = 2.dev_name = ’ITRS 32 nm NMOS native transistor’.gate_rating = 1.drain_rating = 1.2*itrs32n.8e15. itrs45n.drain_rating = 1.drain_cap = .2*itrs45n. itrs65n. itrs32n. itrs16n. itrs22n. % in V itrs45n. % in m^2 itrs45n. itrs22n.33*itrs16n.dev_name = ’ITRS 16 nm NMOS native transistor’.gate_rating = 1. % 22 nm switch itrs22n. itrs32n.body_cap = .tech_name = ’ITRS 22 nm’. % in m^2 itrs22n. itrs45n.gate_cap.2*itrs16n.drain_cap = .33*itrs45n. itrs22n.area = 1e6 * 32e9 / .2*itrs22n. % 45 nm switch 105 110 itrs45n. itrs22n.gate_rating = 1. % in S itrs45n.gate_cap = . itrs22n.2*itrs65n.
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device Dickson topology. 135 magneticsbased converters. 204 generate topology. 56 FLASH. 21 optimized output impedance. 25 capacitive. 207 implement topology. 195. 26 inductive. 148 example charge multipliers. 60 drain charge recovery. 165 doubler topology. 176 charge multipliers. 88 lowerbound. 3. see voltage reference boost converter comparison with SC. 212 231 . 25 current source. 169 ladder topology. 40 contour plot. 159 charge multiplier vector. 84 KCL equation. see fastswitching limit (FSL) fundamental cut set matrix. 18. 5. 147 energy harvesting. 126 charge pump. 110 transformer design. 78 SSL Metric. 11. 127 hybrid SCboost converter. optimization capacitor energy. 20 code. 171 KVL equation. 90 inductive load. 66 mass. 18. 11. 3 FSL. 76 fundamental loop matrix. 40 parasitic loss. 51 linear system continuous time. 157 dynamic voltage scaling (DVS). 111 ﬂying capacitor. optimization. 135 device cost metric. 185 discrete time. 173 for switches. 119 energy per operation. SC converter. 103 MATLAB code. 167 gate drive cascode. converter current reference. 1 ﬂyback converter. 34 diearea. 188 link. see inductive load lowdropout regulator (LDO). 55 digraph. 67 for aerial robotics. applications. see MATLAB code bandgap reference. see metric. 161 meaning of sign. 38 Fibonacci topology. 192. 112 hysteretic feedback.Index analysis code. 13. see MATLAB code constraints. see metric. 107 bottomplate capacitance reducing. 19 fastswitching limit (FSL). 26 impedance improvement. 191 evaluate loss. 166 load type. 191. 44 converter metric. 167 fundamental limit FSL Metric. 29 interleaved phases. component.
142 converter cell size. 26 SSL. 49 metric.optimize loss. converter FSL. 24 VA product in a highratio boost converter. device. 44 output impedance approximation. 23 twophase. 6. 6. see slowswitching limit (SSL) switchedcapacitor converter. 10 eliminating impedance with inductors. 2 load. 93 232 resonant drain. 143 SC topology. 32 for switches. 116 hybrid SCboost converter. see awesome Micro air vehicle (MAV). 147 energy per operation. 121 slowswitching limit (SSL). 2 topology. see constraints. electromagnetic. 116 microprocessor power. 3 PicoCube. 2 symmetrical topologies. optimization optimization contour. 166 twophase simpliﬁcations. 36 total. 21. 81 eﬃciency improvement. 217 plot regulation. 23 FSL. 32 for capacitors. 58 symmetrical. 143 Tellegen’s Theorem. 64 synchronous rectiﬁer. 49 SSL. 109 voltage reference. 137 well biasing. 11 phase. output. 21 twig. 64 tree. 5. 2 Dickson. 84 interleaved phases. see switchedcapacitor converter seriesparallel topology. 155 ripple voltage. 58 shaker. 143 multiratio converter. 88 variableratio topologies. 157 resonant gate drive. 199. 136 sample and hold. 150 dynamic voltage scaling. 148 integrated buck converters. 137 SC converter. 146 technology scaling. 102 MicroGlider. 159 wireless sensor node (WSN). 143 manycore. 129 eﬃciency. 38 optimized SSL. 104 prior work. 85 RS232. 166 trivial converter. 139 impedance matching. 13 topology. 219 techlib. 216 plot opt contour. 36 softcharging. 83 hysteretic. 1. 30 optimized output impedance. 196. 133 technology scaling. 215 permute topologies. 197. 24 phase. 33 Michael Seeman. 21 optimized FSL. 1 sample and hold. 200. 60 Fibonacci. 55 doubler. 103. 119 . 56 ladder. 103 regulation. 3 stage. 222 metric. 146 optimization constraints. 120 system eﬃciency. 51 seriesparallel. applications. 33 lossbased. 141 power density components by mass.
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