MOS Device: Basics

- MOSFET & Modeling -

Overseas Design Support Center

Hiroo Masuda
October, 2007

Chapter 1

©2007. Renesas Technology Corp., All rights reserved.

Introduction
Why we need to learn MOS Devices? How the MOSFET model is used? What is Key issue in MOSFET & Model?

These are basic questions for people who starts working in Semiconductor Industry. Firstly, let’s try to answer the questions before starting lecture on MOSFET & Modeling.

2

©2007. Renesas Technology Corp., All rights reserved.

Why we need to learn MOSFET & Model?
Integrated Circuits (IC) are everywhere, now! - Radio, TV, Mobile Phone, Camera, Computer, Car , Lamp ….. Integrated Circuit is the product of “INTEGRATION” of: - Knowledge - Science - Technology - and Dream It is composed of Transistors, that is MOSFETs. Millions of MOSFETs are integrated in a small chip say 5mm*5mm size. So, to understand MOSFET; it is the basic knowledge in working at industry, not only Semiconductor but also IT, Car Industries etc.
3 ©2007. Renesas Technology Corp., All rights reserved.

LSI is Everywhere: Foundation of Industrial Society
Micro Controller PlayStation (game) Data Communicate Windows PC Mobile Mobile Phone E-mail, E-tag Camera, TV

LSI
Life Pace Maker Robot Sensor, Monitor Environmental Car Hybrid Car Navigation Anti-crash Control Gas Control

4

©2007. Renesas Technology Corp., All rights reserved.

Short Quiz
(1) How many ICs in a mobile phone? (2) How many ICs in a hybrid car? (3) How much sales price of G2 mobile processor from Renesas? (4) How much production cost of G2?

5

©2007. Renesas Technology Corp., All rights reserved.

How the MOSFET model is used?
In designing Logic circuits In designing Analog circuit To develop Standard Cell Library To compromise LSI (Large Scale Integration) performance & cost And more….! MOS model is “Interpreter” between Process and Design! All the process information can be described through MOS model and its parameters.

6

©2007. Renesas Technology Corp., All rights reserved.

What is Key issue in MOSFET & Model?
To understand basic MOSFET I-V characteristics. (operation) To know updated small size effects down to 90nm process. To depict MOSFET model parameters as their relationship to MOS process information. To become used to utilize circuit simulators (SPICE), in your daily LSI design works.

7

©2007. Renesas Technology Corp., All rights reserved.

Education level of this course
University Under Graduate School Level of Physics University Under Graduate School of Math. & Statistics Recommend to have studied at EE (Electronics Engineering) Department course such as; Electronics Circuit Theory Semiconductor Physics -

8

©2007. Renesas Technology Corp., All rights reserved.

Lecture organization
Chapter 1: Basics - Semiconductor Physics (basics) - PN Diode - MOS Diode - MOSFET - CMOS (Complimentary MOS) - Scale Down of MOSFET - Quiz and Homework In this Lecture, we learn Chapter 1, - Especially MOSFET electrical operation Chapter 2: BSIM - Compact MOS I-V Model - ….. Chapter 3: Charge Model - …… Chapter 4: Variability - …… Chapter 5: Analog CMOS - ……

9

©2007. Renesas Technology Corp., All rights reserved.

Useful References
Semiconductor Physics and Device : Grove: Physics and technology of semiconductor devices, John Wiley & Sons,
Inc., 1967.

Sze; Physics of semiconductor devices (2nd Edition), John-Wiley & Sons, Inc., 1981. Compact MOS Model: Arora: MOSFET model for VLSI circuit design, Springer-Verlag, 1993. Tsividis:Operation and modeling of the MOS transistor, McGraw-Hill, 1987. BSIM4.2.1MOSFET Model User’s Manual: (U.C. Berkeley, CA, 2001). MOS Circuits: Cobbold: Theory and application of field-effect transistor, Wiley–Interscience
1970. Razavi: Design of analog CMOS integrated circuits, McGraw-Hill, 2001.
10 ©2007. Renesas Technology Corp., All rights reserved.

Chapter 1: Basics
In this Chapter, we learn : (1) Materials used in LSI ; brief summary (2) What is semiconductor? Intrinsic and extrinsic semiconductor (3) Carrier (electron and hole) transport dynamics (4) Most simple devices: Diodes PN diode and its role MOS diode and its electrical properties (5) MOSFET basic I-V characteristics (6) CMOS (Complimentary MOS) (7) Scaled-down and related Small Size effects (8) Futures on MOS Devices

11

©2007. Renesas Technology Corp., All rights reserved.

(1) Materials used in LSI
Various Material Structure: a)Amorphous Not well defined structure b)Poly Crystal Many small crystal c)Crystal Long range 3D order of atoms Example: a): SiO2, SiN, Amorphous Si, …. b): Poly Si, Metal (Al, Cu), TaO, …. c): Si, Ge, GaAs. ….

Crystal lattice & Bonding to neighbors; this structure determines electrical nature of semiconductor crystal.
12 ©2007. Renesas Technology Corp., All rights reserved.

LSI Structure: Type of materials
Poly Crystal (Cu, W)

Amorphous (SiO2, SiN)

Crystal (Silicon) MOSFETs
13 ©2007. Renesas Technology Corp., All rights reserved.

Poly crystal: Cupper Metal
Poly-crystal material is a group of small crystals. The electrical properties are determined by: - Crystal size - Crystal Boundary - Boundary with other material In General: - Mechanically tough (strong) compared with crystal body
Cu interconnect structure
14 ©2007. Renesas Technology Corp., All rights reserved.

Silicon Crystal Key Properties
(1) Silicon is everywhere! - Stones - Sand at sea shore - ・・・ Unlimited resources on earth. Silicon Crystal (2) Very high melting temp. (1400oC) Therefore, very stable material. (3) Oxidized Silicon (SiO2) shows extremely good insulator & stable Silicon is an ideal semiconductor material for LSI

15

©2007. Renesas Technology Corp., All rights reserved.

Type of Conductor (Electrical property)
a) Good Conductor (Metal:Cu, Al) Electron (e-) free from atomic bound; b) Semiconductor (Si, Ge, GaAs) e- loosely bounded; c) Insulator(SiO2, SiN) e- tightly bounded;
10-6 10-4 10-2 1 102 104 106 108

ρ ≈ 10 −5 Ω ⋅ cm

ρ ≈ 101 ~ 105 Ω ⋅ cm

ρ ≈ 1016 Ω ⋅ cm
1010 1012 1014 1016 1018

Cu, Al, W, TiSi

Ge 10Ω Si Wafer

Si

GaAs

SiO2, SiN

16

©2007. Renesas Technology Corp., All rights reserved.

To understand electrical properties of Material, we need to know Band Theory! What we need to know is not so much, a couple of key images are required.
1. Electrical current is due to “Electron” movement in material. 2. To get more current, (1) many free Electrons and their (2) faster movement (mobility) are necessary requirement. High speed switching of circuits, High frequency operation.

17

©2007. Renesas Technology Corp., All rights reserved.

Continued…
3. How many free Electrons in the Silicon? Energy Band Theory determine it! Behind the Theory, “Quantum Electronics” “Quantum Electronics” says Electron can stay only preassigned Energy Levels in silicon. … 4. How fast the Electrons moves in Silicon? Electron Scattering determine it ! Many Scattering mechanisms….. Phonon scattering (electrons & lattice-atoms) Surface scattering (electrons & surface-roughness) etc.

18

©2007. Renesas Technology Corp., All rights reserved.

(2) What is semiconductor ?
Two Type of Semiconductor structures Intrinsic semiconductor Extrinsic semiconductor (P-Type and N-Type) Intrinsic Semiconductor (Pure Silicon) Determine basic Band structure and temperature dependence Extrinsic Semiconductor (with Impurity atoms) Determine practically “How many Free Electrons” Therefore, Impurity is very important pieces, just like spices in Viet Nam delicious foods!

19

©2007. Renesas Technology Corp., All rights reserved.

Conduction Band and Valence Band determine “How many electrons in Si”
Firstly, Band Theory determine energy-levels, in which electrons can stay! In semiconductors, the conduction band is the range of electron energy, higher than that of the valence band. Electrons stay in conduction band move freely under the influence of an applied electric field and thus constitute an electric current. Open Electron Energy

Filled

Let’s see detail For: -Metal -Silicon -Insulator

20

©2007. Renesas Technology Corp., All rights reserved.

Band Structure (Metal, S/C, Insulator)
Semiconductor (S/C) is something between Metal and Insulator. One case the good electrical conductor, the other like insulator (no current conduction), which means it forms electrical “switch”. It can be done by introducing small amount of impurities in Si crystal! Conduction Band 1.1 eV for Si Valence Band 8 eV for SiO2 Forbidden Band Valence Band Metal
21

Conduction Band

Semiconductor

Insulator

©2007. Renesas Technology Corp., All rights reserved.

(2-1) Intrinsic Semiconductor (No impurity dopant) : Energy band structure
Rooms in which Electron can stay: ~ Nc(E) Probability of Existence for electron as a function of electron-energy Electron density (numbers of electrons)

22

©2007. Renesas Technology Corp., All rights reserved.

Band theory tells us “how many free electrons existing in Silicon (Intrinsic)
One unclear parameter is Fermi Energy (Ef). What is this physical meaning?
Fermi (Energy) level is just like Sea-surface-level of “electron sea”. Happy electron who successfully jumps up the Rock, they become a Free-Electrons. They work hard to carry current in Silicon! What happen at high Temperature (rough sea waves) Answer: generate more free Hole.
23 ©2007. Renesas Technology Corp., All rights reserved.

Free Electrons

Sea level (Fermi level) Rock (Band gap) Water of Electrons

Temperature effect on: Intrinsic carrier density ni(T)
ni: Intrinsic carrier density (Temp. dependent) For Silicon @300K (27oC) ni=1.5X1010 cm-3 @400K ni=2.0X1013 cm-3 @500K ni=1.0X1015 cm-3

(After Textbook of Sze)

-MOSFET: ni is used to calculate Vth(φF(ni)) -PN diode: ni is used to calculate Vbi or φBi -In equilibrium: np=ni2
24 ©2007. Renesas Technology Corp., All rights reserved.

(2-2) Extrinsic Semiconductor (With impurity dopant): Energy band structure (N-Type)
Dopant: N-Type: P, As, Sb ; P-Type: B Impurity dope is a “magical spice” to change S/C into devices
Rooms Probability Electron density

25

©2007. Renesas Technology Corp., All rights reserved.

Band theory tells us “N-Type Extrinsic Silicon generate a lot of Free Electrons”
In Extrinsic (N-Type Impurity is added) semiconductor, the Fermi Level moves-up near Conduction Band!
Many more Free Electrons! Sea level (Fermi level) Rock (Band gap) Water of Electrons

At sea-surface-level close to the Rock’s upper surface, a lot of electrons are thrown upon. Happy free electrons carry much more current!

What happen in “P-Type Extrinsic Silicon ? Answer: generate a lot of free Hole.
26 ©2007. Renesas Technology Corp., All rights reserved.

Equations: Fermi level (Intrinsic & Extrinsic)
Fermi level: (0) Definition: E at which

f (E) =

1 1 = exp (E − E f ) kT + 1 2

[

]

(1) Intrinsic Fermi level:

⎛ mh ⎞ 1 3 E f = (EV + EC ) + kT ln⎜ ⎟ ⎜m ⎟ 2 4 ⎝ e⎠

(2) Extrinsic Fermi level: - N-Type

⎛ NC ⎞ E f = EC − kT ln⎜ ⎜N ⎟ ⎟ ⎝ D⎠

- P-Type

⎛ NV ⎞ E f = EV + kT ln⎜ ⎜N ⎟ ⎟ ⎝ A⎠

27

©2007. Renesas Technology Corp., All rights reserved.

Equations: Band structure: Density of state (free rooms)
Density of State: - Conduction band;

NC (E) =

4π (2me )3 2 E − EC h3

- Valence band;

NV ( E ) =

4π (2mh )3 2 EV − E h3

Note: NC=2.8X1019 cm-3 , NV=1.0X1019 cm-3 @27oC Fermi-Dirack statistics:

1 f (E) = exp (E − E f ) kT + 1

[

]

Ef: Fermi energy level, strong function on ND, NA

28

©2007. Renesas Technology Corp., All rights reserved.

Show Time !
Metal Electron moves freely Semiconductor Crystal Energy Band Electron Movement

29

©2007. Renesas Technology Corp., All rights reserved.

Different from Silicon, Cupper (Cu) atoms allow the electrons move freely within the solid Cu.

Cu
29+

Cu
29+

Cu

29+

Cu

29+

Cu

29+

Cu
29+

Cu
29+

Cu
29+

Cu
29+

-

Cu

29+

Cu

29+

-

Cu
29+

Cu
29+

Cu
29+

Cu

29+

-

-

-

As the result, Cu becomes good conductor.

Why there are many free electrons in Cupper material?
30 ©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Silicon crystal
Si
14+

Si
14+

Si
14+

Si
14+

Si
14+

Since 4 valence electrons of silicon are used to form the covalent bond, very few electrons moves freely.Therefore, the resistivity is very high.
-

-

- Si Si
14+

- Si Si
14+

- Si Si
14+

- Si
14+

- Si
14+

Conduction Band Electron Energy
-

-

14+

14+

14+

- Si
14+

- Si
14+

-

-

Band Gap

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

Intrinsic Semiconductor

31

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Let’s add Boron ion of III Group to intrinsic silicon, and see what happens.
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band
-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

-

B5+ -

III group element becomes “Acceptor” for silicon.

32

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

At first, remove one silicon atom from lattice.
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band
-

- Si 14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

-

B5+ -

III group element becomes “Acceptor” for silicon.

33

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Si
14+

Si
14+

Si
14+

Si
14+

Add Boron atom instead of removed silicon.
-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- B
5+

- Si
14+

- Si
14+

-

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band
-

Acceptor state
-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

-

34

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Si
14+

Si
14+

Si
14+

Si
14+

Acceptor catches a electron and the “hole” is generated.
-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- B
5+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band
-

Acceptor state
-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

35

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Let’s add Phosphor ion of V Group to intrinsic silicon, and see what happens.
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band
-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

P15+
-

V Group element becomes “Donor” for silicon.

36

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Remove one silicon atom from lattice.
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

Conduction Band Donor state

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

P15+
-

V Group element becomes “Donor” for silicon.

37

©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Add P element instead of removed silicon.
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

-

- Si
14+

- Si
14+

- P15+ Si 14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

-

Conduction Band Donor state

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

V Group element becomes “Donor” for silicon.
38 ©2007. Renesas Technology Corp., All rights reserved.

Doped Silicon
Si
14+

Excess valence electron becomes free electron(carrier).
14+

Si
14+

Si
14+

-

-

-

Si

Si

14+

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

-

-

- Si
14+

- Si
14+

- P15+ Si 14+

- Si
14+

- Si
14+

-

-

- Si
14+

- Si
14+

- Si
14+

- Si
14+

-

Electron Energy

-

-

Conduction Band Donor state

- Si
14+

- Si
14+

- Si
14+

- Si
14+

- Si
14+

Valence Band

-

-

-

-

-

-

-

From 1 donor, 1 free electron is generated. Thus, between electron density n and donor density ND, the relationship n=ND is established.
39 ©2007. Renesas Technology Corp., All rights reserved.

Summary on Free Electrons in Silicon
-

Intrinsic semiconductor
ni=1.5X1010 cm-3 @300K (27oC) Large Temperature dependent

- Extrinsic semiconductor
1)

Fully ionized (in case of shallow level dopants)
n-Type: n=ND, p=ni2/ND Ef=Ec-kt ln(2.8x1019cm-3/ND) p-Type: p=NA, n=ni2/NA Ef=Ev+kt ln(1.0x1019cm-3/NA )

2)

40

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) Why ni of GaAs, Si and Ge shows quite different values. (See Figure in page 24) (2) In Figure in page 16, you can see resistivity value of intrinsic semiconductor (GaAs, Si and Ge) @ room temperature. How this observation relates to (1)? (3) Intrinsic Si has slightly higher Ef (Fermi energy level) over Ei (=(Ec+Ev)/2). How high is it? Assume mh/me=2. (4) Extrinsic Si with NA (p-type impurity) =1015 cm-3; tell the electron and hole concentrations (n and p) of the material @ room temp. (5) Location of Ef of (6)?

41

©2007. Renesas Technology Corp., All rights reserved.

(3) Carrier transport mechanism: “How fast the free electron moves ?”
Carrier (e-, h+) movement 1) Drift (Moving force = Electric field “E”) 2) Diffusion (Moving force = Carrier density gradient “ ∂ n / ∂ x ” ) Current equations
Drift Diffusion

⎛ ∂n⎞ - Current Equation: I n = q A⎜ μ n n E + Dn ⎟ ⎜ ∂x⎟ ⎠ ⎝
- Einstein’s Relation:
Dn ≈ kT μ n = 0.025μ n q

⎛ ∂ p⎞ ⎟ I p = q A⎜ μ p p E + D p ⎜ ∂x⎟ ⎝ ⎠
Dp ≈ kT μ p = 0.025μ p q

MOS on-current: MOS sub-Vth current: BJT minority carrier at Base:
42

Drift current Diffusion current Diffusion current

©2007. Renesas Technology Corp., All rights reserved.

How fast e- and h+ move: Mobility (μn, μp)
Note: Carrier mobility (μn, μp) is complicated “EFFECTIVE” physical parameter. Many empirical effect (Scattering mechanisms) are solely implemented into this parameter “mobility”. Brief comment on carrier transport: - Two types of carrier transport mechanisms: e- in vacuum, Constant electric field E: e- in S/C, Constant electric field E:

Const. Acceleration Const. velocity

In S/C (semiconductor), various carrier scatterings cause above observation… Constant carrier mobility in electric field (moving force).

43

©2007. Renesas Technology Corp., All rights reserved.

Carrier scattering mechanism
- Thermal movement (vibration) of atoms scatter the moving carrier (Phonon scattering) - MOS structure; surface (@ SiO2-Si interface) potential roughness disturb the carrier movement (Surface scattering) - Impurities; which cause disturbance of periodic potential structure in Si crystal (Impurity scattering) - Defects; crystal imperfection cause also the disturbance of periodic potential structure (Defect scattering) -Other carrier’s charge scatters the moving carrier, e-/e-, e-/h+ scattering (Carrier/carrier scattering) In MOSFET, Surface scattering and carrier velocity saturation (Phonon scattering) are the two major scattering mechanisms. Degrade the MOSFET current (Ids) in Shrunk MOSFETs!
44 ©2007. Renesas Technology Corp., All rights reserved.

About MOSFET (short break)
- Electrons (e-) are induced at Si/SiO2 interface by gate electric field (+Vg)…… Surface scattering effect significant - The e- move from Source to Drain by drain bias (+Vd)…… Velocity saturation effect (Phonon scattering) dominate
Gate(+Vg) Source (GND) N+
SiO2

Drain (+Vd)

e- e- e- e- e-

N+

P-Sub.

Silicon

Bulk (GND)
45 ©2007. Renesas Technology Corp., All rights reserved.

NMOS Structure

Mobility: Depends on drift field (Phonon Scattering)
When you drop a small stone in water tank, the stone moves down in the water with “Constant Speed”. This happens because negative-force due to friction with water works. The same phenomena happens on Electron movement in crystal.

Frictional force Gravity force

Stone sinking in Water
46 ©2007. Renesas Technology Corp., All rights reserved.

Mobility: Depends on temperature (phonon scattering)
At High temperature, crystal atoms vibrate heavily and interrupt more the movement of Electrons. So, higher temperature results in lower carrier mobility ( less current=slow switching). Note; LSI can be used in North Pole (-20oC) and/or Viet Nam (40oC). We need to guarantee our LSIs work perfectly at any location in the world!
47 ©2007. Renesas Technology Corp., All rights reserved.

Mobility: Depends on surface field (Surface Scattering)
In MOSFET, carrier mobility is degraded to ½ of bulk one’s. MOS operate at the E⊥=105 ~ 106 V/cm @90nm device E⊥(max)=1.2V/2nmX(εox/εsi)=1.9X 106 V/cm
C a r r ie r M o b ilit y (c m 2 / V .s e c ) 1400 1200 1000 800 600 400 200 0 0 1 2 3 4 5 6 Vertical Electric Field Log [E⊥(V/cm)] 7 Electron hole
MOSFET Operates in This region

48

©2007. Renesas Technology Corp., All rights reserved.

Mobility: Depends on impurity concentration (Impurity Scattering)
@90nm MOSFETs, channel impurity concentration is some 1017 cm -3.

1017cm -3

1017cm -3

49

©2007. Renesas Technology Corp., All rights reserved.

Summary of carrier transport
- Carrier transport equation ⎛ ∂n⎞ ⎟ I n = q A⎜ μ n n E + Dn General Eq.: ⎜ ∂x⎟ ⎝ ⎠ MOSFET Eq.:

I n ≈ q A μn n E

- Carrier mobility (μ) determine MOSFET current (switching speed): (1) μn, μp are characterized from various scattering mechanisms (2) In MOSFET, phonon & surface scatterings are major ones … the μ degraded due to carrier velocity saturation (vs) & surface scattering (3) In shrunk MOS, vs(n)=vs(p)= 107cm/sec, @ critical field; Ecrit.=2X104V/cm! Note: In 90nm process, E=1.2V/100nm=1.2X105 V/cm>>Ecrit. These scatterings degrade mobility by a factor of ~4 compared to bulk.

50

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) Current flow direction of e- and h+ along applied electric field E? (2) What kind of carrier transport mechanisms (type of movement), in case of MOSFET? What is the moving force of them? (3) In conductive material the carrier moves at constant velocity. Why it comes? (4) In case (3), what happen when electric field E (in the material) is changed say to double? (5) When electric field E is increased to very large value, what kind of phenomena may happen? (6) Tell three scattering mechanism which degrade carrier transport velocity. Which mechanism may affect on (5)?

51

©2007. Renesas Technology Corp., All rights reserved.

(4) How many types of Devices on LSI ?
So far, we learned “Semiconductor Physics”, it’s a basic knowledge to understand Devices. - How many electrons in semiconductor material - How fast the electron moves in the semiconductor material Now we start learning “Semiconductor Devices”. Typical device used in LSI is categorized with: - Two terminal Devices: Diode - Three terminal Devices: Transistor Diode: we have “PN-Diode” and “MOS-Diode”. Transistor: we have: “MOSFET; Metal Oxide Semiconductor Field Effect Transistor” “BJT; Bipolar Junction Transistor” We will learn the operation of “PN-Diode”, “MOS-Diode” and “MOSFET”.
52 ©2007. Renesas Technology Corp., All rights reserved.

Symbols of Devices Used in LSI
MOS Transistor
Broadly used owing to the properties of high-speed, lowvoltage, and high-integration.
Gate Source Drain Gate Source Drain

nMOS
Collector Base Emitter

pMOS

Bipolar Transistor
Used in RF and analog applications owing to its high-driveability.

Collector Base Emitter

npn

pnp

Other devices
PN-Diode, capacitors, resistors etc.

Anode

Cathode

MOS: Metal Oxide Semiconductor
53 ©2007. Renesas Technology Corp., All rights reserved.

(4-1) PN-diode or PN-junction
Firstly, the most important Device is PN-diode, within many sophisticated semiconductor devices. It gives Electrical Rectifier element by itself. Also it is the basic element of BJT (Bipolar Junction Transistor) and IC (Integrated Circuit) invented by Schockley and Noice, respectively. In MOSFET, it works as Device Isolation element in CMOS IC, which achieves updated Highly integrated LSI.

IC: Integrated Circuit, LSI: Large Scale Integration

54

©2007. Renesas Technology Corp., All rights reserved.

Historical BJT Integrated Circuit invention
PN-diode, BJT and Resistors are integrated on a same material (chip). This is done by using various PN-junctions on chip!

PN-Diode

BJT

Resistor
55 ©2007. Renesas Technology Corp., All rights reserved.

PN-diode is used for Electrical Isolation in CMOS Devices
PN-Diode works as Device Isolation structure in CMOS-LSI It also used as Capacitor element. Many PN-Diodes are un-intentionally formed in CMOS as shown below.

56

©2007. Renesas Technology Corp., All rights reserved.

Current Flow through PN-Diode
PN-Diode allows the current flow only one direction, from P to N. It forms electrical rectifier. Note: In MOS-LSI, PN-Diodes are always “Reverse Biased” to electrically isolate NMOS and PMOS.
P N V: Applied Voltage N P V: Applied Voltage

I: current I Reverse Biased No current For V>0 +V
57 ©2007. Renesas Technology Corp., All rights reserved.

I: current I Forward Biased Current flows For V>0 +V

Bias dependency: Equilibrium, Reverse bias, Forward bias

58

©2007. Renesas Technology Corp., All rights reserved.

Show Time !
PN-Diode or PN-Junction : Electrons and Holes in PN-diode Movement of Electrons and Holes Related Current Flow Change of Depletion Layer Width

59

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
When donor ions are added to silicon, free electrons whose number is same to donors and ionized donors are generated.

+ - + -

+ + + - -

+ + -

+ -

+ Donor ion - Free electron

60

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
When acceptor ions are added to silicon, holes whose number is same to acceptors and ionized acceptors are generated.

+ + -

+ + -

+ + + + -

+

+

+

+

+ +

+

+

-

Ef Ec Ev

+ Donor ion - Free electron

- Acceptor ion
+ Hole Ec Ev Ef

61

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
The electron density and hole density at the region where p-type and n-type semiconductors combine rapidly change. Therefore, electrons and holes near the junction(Flashed electrons and holes) try to diffuse into the opposite region. Let’s combine these two semiconductors.

+ + -

+ + -

+ + + + -

+

+

+

+

+ +

+

+

-

+ Donor ion - Free electron Ec Ef Ev

- Acceptor ion
+ Hole Ec Ev Ef

62

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
The electrons and holes diffusing to the opposite region disappear by the recombination. Direction of electron diffusion Direction of hole diffusion

+ + -

+ + -

+ + + + -

+

+

+

+

+ +

+

+

-

+ Donor ion - Free electron Ec Ef Ev

- Acceptor ion
+ Hole Ec Ev Ef

63

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
The region where carriers does not exist(depletion region) is formed.

+ + -

+ + -

+ + + + -

+

+

+

+

+ +

+

-

+ Donor ion - Free electron Ec Ef Ev

- Acceptor ion
+ Hole Ec Ev Ef

Depletion Region Since electrons and holes recombine one by one, the number of disappeared electron and hole is same.Then, the same number of donor ions and acceptor ions remain in the depletion region.
64 ©2007. Renesas Technology Corp., All rights reserved.

PN Junction
Since charges (donor ions and acceptor ions) exist in the depletion region, the electric field is generated in the depletion region.

The electric filed is generated shown by the arrow. + + + + + + + -

+ -

+

+

+

+

+ +

+

-

+ Donor ion - Free electron

- Acceptor ion
+ Hole

Depletion Region
Note that outside the depletion region, the number of impurity and carrier (ex. donors and electrons) are same, the total charge is zero. So there is no electric field.

65

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
Further diffusion of carrier make the depletion region wider, then the electric field within the depletion region becomes stronger.

+ + -

+ + -

+ + + + -

+

+

+

+

+ +

+

-

+ Donor ion - Free electron Ec Ef Ev

- Acceptor ion
+ Hole

Ev Depletion Region
Depletion region becomes wider.

Ef

66

©2007. Renesas Technology Corp., All rights reserved.

PN Junction
The electric field is generated with the direction to suppress the diffusion of carriers. Direction of electron diffusion Direction of hole diffusion

+ + -

+ + -

+ + + +

-

+

-

+

+

+ +

+

-

+ Donor ion - Free electron

- Acceptor ion
+ Hole

The larger electric field suppress the carrier diffusion and the equilibrium condition is reached. The potential difference produced by the electric field is the diffusion potential. (Built-in potential)
67 ©2007. Renesas Technology Corp., All rights reserved.

PN Junction Diode(Forward Bias)
Current Built-in Potential

Voltage

N-Type + + - + + - + -

P-Type + + +

-

- -+ + -

+ +

-

+

Ammeter 0 Voltmeter

68

©2007. Renesas Technology Corp., All rights reserved.

PN Junction Diode(Forward Bias)
Current

Voltage

N-Type + -+ - + - + - + -

P-Type + + +

-

+

-+

+ + - ++ + - +

-

Ammeter 0 The current slightly flows. Depletion width becomes narrow. Voltmeter Electrons flow to right and Holes to left.

69

©2007. Renesas Technology Corp., All rights reserved.

PN Junction Diode(Forward Bias)
Current

Voltage

N-Type + + - + + - + -

P-Type + +

+ -

+

-

- + - + + + -

Ammeter 0 Voltmeter Depletion width becomes narrow. Electrons flow to right and Holes to left.

70

©2007. Renesas Technology Corp., All rights reserved.

PN Junction Diode(Reverse Bias)
Current

Voltage

N-Type + + + - + + + + + - +

P-Type

- - -

+

- + + -

-

+

-

Ammeter 0 Voltmeter Depletion width becomes wide.

71

©2007. Renesas Technology Corp., All rights reserved.

PN Junction Diode(Reverse Bias)
Current

Voltage

N-Type + + + + - + + + + + - + +

P-Type

- -- - + - + - - + + -

Ammeter 0 Voltmeter Depletion width becomes wide.

72

©2007. Renesas Technology Corp., All rights reserved.

Summary of PN-diode
In MOS devices, the P-N junction is used as isolate devices. It is sufficient to consider only the negative biased P-N junction, “parasite C elements”.

73

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) Why PN diode is useful in Integrated Circuit? (2) How the built-in voltage φBi is formed? (3) Calculate φBi and Wdep @ NA=1015 cm-3, ND=1020 cm-3 and @ NA=1017 cm-3, ND=1020 cm-3 (4) Depict I-V curve when forward biased V=0 to 1V

74

©2007. Renesas Technology Corp., All rights reserved.

(4-2) MOS-diode or MOS-capacitor
Before you study MOSFET electrical operation, MOS-diode is another key device to learn, as well as PN-diode. MOS: which stands for Metal-Oxide-Semiconductor, a two terminal device (therefore Diode). A bit difference compared with MOSFET.
Metal Oxide Semiconductor Metal Oxide N+ N+ Semiconductor (P-Type)

MOS-Diode
75 ©2007. Renesas Technology Corp., All rights reserved.

MOSFET

MOS-Diode Basics
What happens when Metal, Oxide, and Semiconductor are joined together? - Joining three materials makes Ef (Fermi-Energy) at the same level - Therefore, the S/C band can be bent at the silicon surface due to the work function difference (Efm - Ef) between the metal and the substrate silicon.

M

Ef

76

©2007. Renesas Technology Corp., All rights reserved.

Band diagram at Equilibrium
Note: In MOS structure, Electrical field is generated in the oxide, at which the voltage applied across the oxide is "qφMS“ the work-function difference.

φS φM

77

©2007. Renesas Technology Corp., All rights reserved.

What happen if we apply Gate Bias ?
In MOS(P-type Si) Diode: (1) Apply “–” Voltage to the Gate: Positive charge (holes) are induced at Si/SiO2 interface (2) Apply “+” Voltage to the Gate: Negative charge (electrons) are induced at Si/SiO2 interface How change in band diagram during Gate Bias from “-” to “+” ? Interesting change is happen!

78

©2007. Renesas Technology Corp., All rights reserved.

Biasing: Accumulation, Flat-band, Inversion
Accumu. Flat Band Depletion Inversion

-

Gate Bias (Vg)

+
Inversion

++V

Accumulation (h+) charge

Depletion charge

Gate

Gate

Inversion (e-) charge
79 ©2007. Renesas Technology Corp., All rights reserved.

How change in C-V characteristics: (Ideal MOS-Diode C-V curve)
Accumu. FlatBand Depletion Inversion

-

Gate Bias (Vg)

+

Cox

Cox Cfb

Cox Cd

Cox Cd(2φf)

80

©2007. Renesas Technology Corp., All rights reserved.

Key Physical Features
In the MOS diode, φf (the Fermi level) matches in the equilibrium condition. MOS-Diode has three operational region (Accumulation, Depletion, and Inversion) Important characteristic values in the MOS-diode: Flat-band voltage Threshold voltage where,
Note: MOS Diode determines “Vth” the important MOSFET parameter !
81 ©2007. Renesas Technology Corp., All rights reserved.

This is an important Parameter of MOSFET

Difference in C-V Curves: Between MOS-Diode and MOSFET

MOS-Diode: In inversion region, Ctot is determined with seriesconnection of Cox & Cdep MOSFET: In inversion region, Ctot is determined with Cox only. Cdep is short-circuited by Source/Drain connected with body substrate.
Inversion Inversion

Vth

82

©2007. Renesas Technology Corp., All rights reserved.

Show Time !
MOS-Diode or MOS-Capacitor Electrons at Surface (Silicon/SiO2 interface) Depletion Layer at Silicon Surface C-V Characteristics of MOS-Diode How changes the above quantities as Gate bias? Accumulation condition Depletion condition Inversion condition

83

©2007. Renesas Technology Corp., All rights reserved.

MOS (Metal Oxide Semiconductor)Capacitor

Insulator: Oxide

Metal electrode:Metal (Gate electrode)

Semiconductor substrate

84

©2007. Renesas Technology Corp., All rights reserved.

Operation of MOS Capacitor(In case of P-Type substrate)
Accumulation
Vg<0V
+ + + + + + + + + + + + ー ー ー ー + ー + ー + ー + ー

Depletion
Gate electrode Gate insulator
ー ー ー ー

Inversion
Gate electrode Gate insulator

Vg>0V

Vg>>0V
ー ー ー

Gate electrode Gate insulator

- - - - - - - - - - - -

ー+

+ ー

+ ー

+ ー

+ + + + ー ー ー ー + + + ー ー ー ー + + + B+ ー ー ー +

+ + + ー ー ー ー ー ー ー ー+ + + + + + + + + ー ー ー ー ー ー ー ー + + + + + + + + ー ー ー ー ー ー ー ー + + + + + + + + ー ー ー ー ー ー ー ー Silicon substrate Silicon substrate+ ー ー B+ + + + + + B+ ー ー ー ー

Silicon substrate

Accumulation Capacitance
Oxide capacitance

Depletion

Inversion

Series capacitance of Oxide and Depletion layer

Gate Voltage 85 ©2007. Renesas Technology Corp., All rights reserved.

Operation of MOS Capacitor(2)
Accumulation
Vg<0V
+ + + + + + + + + + + + ー ー ー ー + + + ー ー ー ー+ + + + + ー ー ー ー + + + + ー ー ー ー + + + + ー ー ー ー + + + B+ ー ー ー

Depletion
Vg>0V
ー ー ー ー ー ー
+ ー

Inversion
Vg>>0V Capacitance
- - - - - - - - - - - -

Gate electrode Gate insulator Silicon substrate

ー ー
+ ー

ー ー
+ ー

ー ー
+ ー

Depletion Inversion Accumulation
Oxide capacitance

+ + + ー ー ー ー+ + + + + ー ー ー ー + + + + ー ー ー ー + + + + ー ー ー ー + + + B+ ー ー ー

+ + + + ー ー ー ー + + + + ー ー ー ー + + + B+ ー ー ー

Low Frequency

Gate electrode

P-Type substrate

Series Capacitance of Oxide and depletion layer
--+ + + + + + + + +

High Frequency

Ec
Vg<0V

Voltage
+ + + + + + + +

Ei Ef Vg>0V ++ + + + + + + + + + + Ev +

Vg>>0V

C=ε・S/d Q=C・V

Cg

Cg

Cd

Cg

86

©2007. Renesas Technology Corp., All rights reserved.

Summary of MOS-diode
MOS structure is very simple structure. It induce N+ Inversion Layer at Si surface below the Metal-Gate. Gate bias voltage at which the Inversion Layer appears at Si surface is one of the important parameters related switching voltage in MOSFET (Threshold voltage). MOS capacitance shows bias-dependent, which can be used as MOS Varactor (Variable Capacitor).

87

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) Depict band structure of: accumulation, flat band, depletion and inversion conditions. (2) Draw charge diagram at inversion condition. (3) Why we can assume Fermi level is constant at equilibrium? (4) Explain the difference between C-V curves of MOS diode and MOSFET. (5) How the inversion charge is generated under the gate; in the case of MOS diode and MOSFET?

88

©2007. Renesas Technology Corp., All rights reserved.

(5) MOSFET: Basic structure
Electrodes: Source: Source of Electrons (pin from which current flows out) Drain: Electron Drain (pin from which current flows in) Gate: Control gate for electron flow Substrate: Fixed silicon substrate bias Structural parameters: Planar dimensions = Lg, Leff, and W Longitudinal dimensions = Tox, Xj, and ρsub Operation: The conductance between source and drain is controlled by the gate voltage. Features 1) Input resistance = completely capacitive. It allows direct circuit connection. 2) Utilization of silicon surface (channel) conduction. It gives easy to isolate devices, which is ideal as highly integrated LSI and VLSI device.
89 ©2007. Renesas Technology Corp., All rights reserved.

MOSFET 3D-Image and Typical I-V Curve
Gate electrode Gate insulator Source Drain
Vd>0

N+ N+ L b P-Su

Drain current Id

Threshold voltage(Vth) Electrically determined

Gate voltage Vg

L:Channel length W:Channel width

90

©2007. Renesas Technology Corp., All rights reserved.

Basic and Updated MOSFET structure
Gate N-type Poly Source N-type Gate Oxide Drain N-type Source n+ Side wall spacer gate Silicide(CoSi 2) Drain N+ n+ N-

P-type substrate PN Junction

PH

MOS capacitor

Substrate (P)

NMOS (Basic structure)
By applying voltage to gate, charges are induced at the capacitor. The charges are pull out by Drain.
91 ©2007. Renesas Technology Corp., All rights reserved.

NMOS (Advanced structure)
N+: Diffusion layer(Highly doped N-type)
N-: Lower doped diffusion layer to relax the electric field at PN junction edge

PH: p-type diffusion layer to suppress short channel effect

MOSFET operation: I-V characteristics
Key Characters of MOSFET:
1) Voltage controlled device. 2) Can be used as a switching element. Ids = 0 (VGS' < VTH), Ids > 0 (VGS' VTH) 3) Ids VGS‘ 2 characteristics Saturation property of drain current. 4) Bi-directional Symmetry even if source and drain are reversed. Can be used as transfer gate (switch)

92

©2007. Renesas Technology Corp., All rights reserved.

Try! Simple I-V model Formulation: Gradual channel approximation

The basics are:
- Capacitor equation (How many free electrons ?): Qn =CV - Lateral drift current (How fast they move ?): I = Qn v= Qn μE 1) Capacitance Equation Qn = QG – QB≒-Cox (VGS' - φS), φS =2 φF 2) Drift current Ids = QnμWE(y), Here W is channel width
93 ©2007. Renesas Technology Corp., All rights reserved.

Some mathematics …..(Important!)

Gate (Vgs) Channel

Y D (Vds)

S(=0V)

Φs(y) E(y)= - d Φs(y)/dy X P-type Substrate

Φs(y): Channel potential @ Y=y E(y): Electric field in the channel

94

©2007. Renesas Technology Corp., All rights reserved.

Continued …
The integration results in:

This is the basic MOSFET I-V Equation. Schematic view of the I-V characteristics shows a parabolic based curve (see left Figure).
95 ©2007. Renesas Technology Corp., All rights reserved.

1-st order physical I-V Model: Hofstein model

In the 0-th order model, we neglect bulk charge (QB). More accurate approach is to consider the bulk charge. It brigs a new charge equation as follow:

96

©2007. Renesas Technology Corp., All rights reserved.

MOSFET I-V characteristics
By using similar derivation process, we can get the I-V equation, as follow:

97

©2007. Renesas Technology Corp., All rights reserved.

How different ? Between simple and 1-st order models
1-st order model is more accurate physically: It results in an early pinch-off voltage and less drain current
Pinch-off Voltage

simple 1-st

simple

1-st

98

©2007. Renesas Technology Corp., All rights reserved.

Show Time !
MOSFET Operation Electrons Band Structure I-V Characteristics The above physical quantities are changed by: Gate Bias Voltage = Vg Drain Bias Voltage = Vd

99

©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Gate characteristics: Id-Vg
Vd(ex. 1.2V)
Ammeter

M O

S
0

Vg(0V)
Voltmeter

Drain current Id

Vd>0

Threshold voltage(Vth)

Gate voltage Vg 100 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Gate characteristics
Vd(ex. 1.2V) qVg M O S
0 Ammeter

Vg(<Vth)
Voltmeter

Drain current Id

Vd>0

Threshold voltage(Vth)

The current under Vth is called sub-threshold current. This is one of leakage currents.

Gate voltage Vg 101 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Gate characteristics
Vd(ex. 1.2V) qVg M O S
0 Ammeter

Vg(=Vth)
Voltmeter

Drain current Id

Vd>0

Threshold voltage(Vth)

Gate voltage Vg 102 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Gate characteristics
Vd(ex. 1.2V) qVg M O S
0 Ammeter

Vg(>Vth)
Voltmeter

Drain current Id

Vd>0

Threshold voltage(Vth)

Gate voltage Vg 103 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Gate characteristics
Vd(ex. 1.2V) qVg M O S
0 Ammeter

Vg(>>Vth)
Voltmeter

Drain current Id

Vd>0

Threshold voltage(Vth)

Gate voltage Vg 104 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics : Id-Vd
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

If Vg<Vth, even if Vd>0, there is no current(except leakage).
105 ©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

Apply Vg=Vg3 and see what happens.

106

©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

107

©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

108

©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

When Vd=Vg-Vth, it is called “pinch-off point”.
109

©2007. Renesas Technology Corp., All rights reserved.

Operation of N-channel MOS(NMOS)FET - Drain characteristics
Ammeter

Vd
0

Linear

Saturation Vg4

Vg G S Leff

Drain current Id

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

voltmeter

D

After pinch-off, the current becomes constant. Electrons are attracted by Drain field and flow through the depletion region.
110 ©2007. Renesas Technology Corp., All rights reserved.

Summary of basic MOSFET & I-V Characters
MOSFET is ideal device for LSI: Small size Easy to isolate each others in highly integrated MOSFETs Capacitive input allows direct circuit connections Others: Low power (CMOS) Easy to shrink sizes (Scaling) ….. Will be discussed later MOSFET I-V Characteristics: Parabolic voltage dependency of Ids (to Vgs and Vds) Switching can be determined by “Vth” Current drivability is in proportion to “W/L” (geometry parameters)
111 ©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) What is the charged carrier in NMOS? It flows from ( ) to ( ). Current flows from ( ) to ( ). (2) What is the charged carrier in PMOS? It flows from ( ) to ( ). Current flows from ( ) to ( ). (3) When you design MOS Layout (determine L, W), How you can do to get double of drain current Ids? (4) Why CMOS becomes popular device in LSI? (5) How you can control Vth of NMOS? If you want increase Vth by 0.1V, what is the best way to do in processing? (6) How you can measure Vth?

112

©2007. Renesas Technology Corp., All rights reserved.

(6) CMOS (Complimentary MOSFET)
We have learned N-channel MOSFET (NMOS) and its operation, so far. Current carrier is Electron! The same model for P-channel MOSFET (PMOS) can be derived by just changing Impurity type and biasing polarity. Current carrier is Hole in PMOS! CMOS is circuit composed with both NMOS and PMOS: It provide ideal switch (charging & discharging) Low power circuit can be achieved with CMOS All the updated LSIs are fabricated with CMOS process!
113 ©2007. Renesas Technology Corp., All rights reserved.

CMOS Structure
CMOS stands for Complementary MOS and both NMOS and PMOS transistors are formed on the same substrate.

p+ Source/Drain

n + Source/Drain

N well
P-sub.

P well

P channel MOSFET(PMOS) N channel MOSFET(NMOS)
114 ©2007. Renesas Technology Corp., All rights reserved.

Characteristics of CMOS
Linear region Drain current Id Saturation region Vg4

Vg3 Vg2 Vg1 Vg<Vth Drain voltage Vd

pMOS : Vg < 0

nMOS : Vg > 0
Note: The mobility of hole is smaller than that of electron (~1/2). So if we want to design NMOS and PMOS with same drivability, Wp should be larger than Wn. Wp,Wn: Gate width of PMOS and NMOS.
115 ©2007. Renesas Technology Corp., All rights reserved.

CMOS Inverter Circuit
<CMOS inverter Structure >
Input

Circuit schematic

Power supply VDD (1.5V)

Power supply
(1.5V) Gate

Output Input Output

GND
Gate

=
n+
Source

p+
Source

p+
Drain

n+
Drain

n-well
pMOS

p-well
nMOS

Cell symbol

GND

Simplest logic circuit with a pair of pMOS and nMOS transistors
116 ©2007. Renesas Technology Corp., All rights reserved.

Current Characteristics
Drain current (- Ids)
Input

Power supply VDD (1.5V)

) e (Vi n voltag

pMOS Input voltage (Vin) Output voltage (Vout)

0 0

Drain voltage+1.5 ( Vout)
n)

1.5

Drain current (Ids)

GND

0 0

Inverter characteristics are defined by current characteristics of both transistors.
117 ©2007. Renesas Technology Corp., All rights reserved.

Input v

nMOS

oltage (Vi

Drain voltage (Vout) 1.5

Behavior
Power supply VDD (1.5V)

Input (Vin)

Output (Vout)

Changed from 0 to 1.5V

GND

Drain current (Ids)

0 0
Output voltage (Vout)

1.5

Output voltages (Vout) are determined by intersection points ( mark) of pMOS and nMOS current curves.
118

©2007. Renesas Technology Corp., All rights reserved.

I/O Characteristics
Power supply VDD (1.5V)

1.5 Output voltage (Vout) Vth of nMOS (Vthn)

Input
(Vin)

Output (Vout)

Changed from 0 to 1.5V

GND

Changed from 1.5 to 0V

Vth of pMOS (Vthp)

0 Input voltage (Vin)

1.5

Signal logically inverted from input appears at output: inverter

119

©2007. Renesas Technology Corp., All rights reserved.

Ideal switch operation of CMOS
When Vin swings from 1 to 0, PMOS=ON and NMOS=OFF When Vin swings from 0 to 1, NMOS=ON and PMOS=OFF It gives ideal switching operation.
Power supply VDD (1.5V)

Charging Vin

Input
(Vin)

Output (Vout)

Discharging Vin

Changed from 0 to 1.5V

GND

Changed from 1.5 to 0V

120

©2007. Renesas Technology Corp., All rights reserved.

Another Merits of CMOS Inverter
Drain current (Ids) transition
1.5 Output voltage (Vout)

transition

Steady State Idirect=0

0 0
Output voltage (Vout)

1.5

0

Input voltage (Vin) and : steady state

1.5

Complementary Operation
Either nMOS or pMOS is ON in steady state: no direct current flow. Input and output voltages swing from 0 to 1.5v (VDD).

121

©2007. Renesas Technology Corp., All rights reserved.

Logical Threshold Voltage
Power supply VDD (1.5V)

1.5 Output voltage (Vout)
Vo

ut

=

V in

Logical threshold voltage
VLT

Input
(Vin)

Output (Vout)

Changed from 0 to 1.5V

GND

Changed from 1.5 to 0V

noise margin to GND 0

noise margin to VDD

Input voltage (Vin)

1.5

To set logical threshold voltage of each gate at the same level is important to secure noise margin: VLT = VDD/2
122 ©2007. Renesas Technology Corp., All rights reserved.

Features of CMOS Circuit

Advantage (1) Low power dissipation (2) Wide operating voltage range (3) Large noise margin (4) Wide operating temperature

Disadvantage (1) Subject to Latch up (2) Complicated wafer process (3) Large device area

123

©2007. Renesas Technology Corp., All rights reserved.

Summary of CMOS
CMOS is the device we are using now, since it provide perfect complimentary operation for digital switching. Low power, say in Mobile Phone, can be achieved with only CMOS device and circuits. If you know NMOS operation and model equation, PMOS is a simple (but sometimes confusing) extension. Structure: Just replace N⇔P-Type impurities Biasing: Just changing polarity NMOS; Vs=0, Vd>0, Vg>0, Vth>0, Vb≦0 PMOS; Vs=0, Vd<0, Vg<0, Vth<0, Vb≧0

124

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) Tell CMOS’s best advantage over NMOS or PMOS circuits. (2) Tell CMOS’s worst disadvantage over NMOS or PMOS circuits. (3) How many masked-doping is required to form the structure of p.118. (4) How many masked-doping is required to form the NMOS structure (only) of p.118.

125

©2007. Renesas Technology Corp., All rights reserved.

(7) Scaled-down of MOSFET

Why we need scale-down MOSFET and Process?
Better LSI performances: High speed Low power High integration and functionality: Many functions Many logics Many MOSFETs Low cost: Small chip Many chips/wafer

126

©2007. Renesas Technology Corp., All rights reserved.

Shrunk an MOSFET: Trend of scale-down in dimensions
Metal Insulator

Historically, LSI performance has been improved by Scaledown (Shrunk) of MOSFET and Process. New LSI technology development totally rely on this trend. Now in 2007, we are developing 45nm technology.

Example of Shrinking MOSFET
127 ©2007. Renesas Technology Corp., All rights reserved.

Scaling rules
k: scaling factor
To keep voltage constant (Old) One side of length (X) Gate oxide thickness (tox) Power supply voltage (V) Electric field strength (E) Electric current (I) Capacity (C) Delay time (Td) Power consumption (P) Power density (P/X2) 1/k 1/k 1 k k 1/k 1/k2 k k3 To keep electric field Constant (Now) 1/k 1/k 1/k
G

scaling

1 1/k 1/k 1/k 1/k2 1 S

G
S D

D

1/k 1
I ∝ V2/ tox Td ∝ CV/ I P ∝ fCV2=CV2/ Td
Success history of semiconductor development !! However…

The effects of scaling are prominent in establishing high speed, low power consumption, and high density. Till now, these effects have been realized by continuously developed process generations.
128 ©2007. Renesas Technology Corp., All rights reserved.

Trend of Scaling & Power Supply Voltage
10
12V 5μm 3μm 2μm

10
Gate length 1.2μm 0.8μm 0.5μm 0.35μm 0.25μm 0.18μm 0.15μm 3.3V 0.13μm 2.5V 90nm
1.8V 1.5V 1.2V 1.0V

Gate length (mm)

1

5V Power supply voltage

5

.1

0
'76 '79 '82 '85 '88 '91 '94 '97 2000 2003

Year
After 0.35 µm generation, power supply voltage has been reduced to maintain electric field constant in gate oxide.
129 ©2007. Renesas Technology Corp., All rights reserved.

Voltage (v)

Updated sub-100nm MOSFET Structure

NiSi
N+ Poly-Si Gate

Lg=55nm
100nm

N+ Diffusion P-Type Substrate

130

©2007. Renesas Technology Corp., All rights reserved.

Limitation on Scaling Rule
1. Some items are not fully scaled
L: 1.0um -> 0.06um (1/17) Tox: 20nm -> 1.5nm (1/13) Vdd: 5V -> 1.2V (1/4)

2. Drivability
I: I/W: 1/k 1

3. Un-scalable factors
Vth S factor Surface potential…. Short Channel Effect becomes glowing
131 ©2007. Renesas Technology Corp., All rights reserved.

Drawbacks: Short Channel Effect
Gate

0V

Source

1.5V
Drain

0V

Source Gate

1.5V
Drain

n+

n+

n+

n+

Channel is controlled by gate

Channel is controlled by gate and drain

1. Increase in off state leakage current
- Vth decrease (roll off) - S factor increase - Vth is varied by drain voltage (Vth decrease)

2. Ids does not increase in proportion to 1/L How to prevent?
132 ©2007. Renesas Technology Corp., All rights reserved.

To overcome short channel effect: Impurity profile control becomes key issue

Silicide(CoSi2) Side wall spacer gate

Source n+

Drain N+ n+ N-

To prevent Vth related problems (leakage current): - lateral P+ diffusions at S/D ends (PH layer) The newly introduced P+ impurities mitigate drain electric field effect, which results in a better Vth control.

PH

Substrate (P)

NMOS (Advanced structure)

133

©2007. Renesas Technology Corp., All rights reserved.

Another Drawbacks: Reliability
Gate

0V

Source

1.5V
Drain

0V

Source Gate

1.5V
Drain

n+
Negligible gate leak Small local drain field

n+

n+

n+

Increased gate leak to breakdown Large local drain field

1. Gate oxide breakdown
- Increased gate leak current - No MOSFET action (short circuited) Functional failure during operation

2. Hot electron causes Isub and Vth-shift during operation
Long term performance degradation

How to prevent?
134 ©2007. Renesas Technology Corp., All rights reserved.

To overcome Reliability problems: Impurity profiling and Material are key issue
Silicide(CoSi2) Side wall spacer

gate Source
New Material

Drain

To prevent gate oxide breakdown (gate leakage current): - New materials for gate oxide SiON, High-K(in Research) To prevent hot carrier effect: - N- diffusion at S/D ends mitigate local drain field

n+

PH N-

N+ n+

Substrate (P)

NMOS (Advanced structure)

135

©2007. Renesas Technology Corp., All rights reserved.

Final Show Time!
MOSFET Operation of 130nm NMOS (Device Simulation)
Ids-Vds Characteristics Change in Potential Distribution inside NMOS Change in Electron Distribution inside NMOS Change in Hole Distribution inside NMOS Ids-Vgs Characteristics Change in Potential Distribution inside NMOS Change in Electron Distribution inside NMOS Change in Hole Distribution inside NMOS

136

©2007. Renesas Technology Corp., All rights reserved.

MOSFET Structure of 130nm NMOS

130nm

Gate

Source

Drain

137

©2007. Renesas Technology Corp., All rights reserved.

Ids-Vds Characteristics Vgs= 1.5V, Vds=0 – 2V

Vgs=2V

Actual curve Ideal curve

Something happen?

138

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=0.0V

139

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=0.2V

140

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=0.4V

141

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=0.6V

142

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=0.8V

143

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=1.0V

144

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=1.2V

145

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=1.4V

146

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=1.6V

147

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=1.8V

148

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs= 1.5V, Vds=2.0V

149

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=0.0V

150

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=0.2V

151

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=0.4V

152

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=0.6V

153

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=0.8V

154

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=1.0V

155

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=1.2V

156

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=1.4V

157

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=1.6V

158

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=1.8V

159

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs= 1.5V, Vds=2.0V

160

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=0.0V

161

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=0.2V

162

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=0.4V

163

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=0.6V

164

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=0.8V

165

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=1.0V

166

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=1.2V

167

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=1.4V

168

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=1.6V

169

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=1.8V

170

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs= 1.5V, Vds=2.0V

171

©2007. Renesas Technology Corp., All rights reserved.

Ids-Vgs Characteristics Vgs= 0 – 2V, Vds= 1.5V

172

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=0.0V, Vds= 1.5V

173

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=0.2V, Vds= 1.5V

174

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=0.4V, Vds= 1.5V

175

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=0.6V, Vds= 1.5V

176

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=0.8V, Vds= 1.5V

177

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=1.0V, Vds= 1.5V

178

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=1.2V, Vds= 1.5V

179

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=1.4V, Vds= 1.5V

180

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=1.6V, Vds= 1.5V

181

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=1.8V, Vds= 1.5V

182

©2007. Renesas Technology Corp., All rights reserved.

Potential Distribution Vgs=2.0V, Vds= 1.5V

183

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=0.0V, Vds= 1.5V

184

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=0.2V, Vds= 1.5V

185

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=0.4V, Vds= 1.5V

186

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=0.6V, Vds= 1.5V

187

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=0.8V, Vds= 1.5V

188

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=1.0V, Vds= 1.5V

189

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=1.2V, Vds= 1.5V

190

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=1.4V, Vds= 1.5V

191

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=1.6V, Vds= 1.5V

192

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=1.8V, Vds= 1.5V

193

©2007. Renesas Technology Corp., All rights reserved.

Electron Distribution Vgs=2.0V, Vds= 1.5V

194

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=0.0V, Vds= 1.5V

195

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=0.2V, Vds= 1.5V

196

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=0.4V, Vds= 1.5V

197

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=0.6V, Vds= 1.5V

198

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=0.8V, Vds= 1.5V

199

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=1.0V, Vds= 1.5V

200

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=1.2V, Vds= 1.5V

201

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=1.4V, Vds= 1.5V

202

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=1.6V, Vds= 1.5V

203

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=1.8V, Vds= 1.5V

204

©2007. Renesas Technology Corp., All rights reserved.

Hole Distribution Vgs=2.0V, Vds= 1.5V

205

©2007. Renesas Technology Corp., All rights reserved.

(8) Futures on MOS devices
To continue scale-down trend, various researches have been conducted.
Material science: Gate oxide material (High-K) Interlayer dielectric (Low-K) Device science: SOI-MOS Strained MOS Fin-FET

In this lecture, we have learned “Semiconductor Devices”, however
interconnect issue is also very important. This is because the speedperformance is known to be limited interconnect delay (R and C) rather than MOSFET drivability.
206 ©2007. Renesas Technology Corp., All rights reserved.

Example of Future MOSFET
Many challenge and new ideas, for continuous improvement of MOS devices and LSI performances.
Gate Source SiO2 Si
SOI-MOS - Thin Si-film as active area - Buried SiO2 to reduce Capacitance Fin-FET - Thin Si-film vertically - Surrounded gate increases W - Reduces short-channel effect

Drain Source Gate Drain

207

©2007. Renesas Technology Corp., All rights reserved.

Sub-100nm Interconnect Structure
Scaled interconnect also requires technology challenges such as: Low resistive metal (Al Cu), Reliability in Electro Migration etc.

208

©2007. Renesas Technology Corp., All rights reserved.

MOS Device supports LSI products: Example in Renesas
< Layout plot of SoC chip for Digital Still Camera (DSC)>
SoC: System on Chip

AD/DA converter

CCD: Charge Coupled Device

CCD I/F + image processor Display controller MPEG4 Processing unit

DSP: Digital Signal Processor JPEG: Joint Photographic Experts Group MPEG: Moving Picture Experts Group USB: Universal Serial Bus PLL: Phase Locked Loop

30
DSP

JPEG Processing Million=30,000,000 unit

MOS Devices in this Chip!
CPU + peripheral

USB PLL

Wide variety of functional units are integrated on a single chip to configure an SoC 209 ©2007. Renesas Technology Corp., All rights reserved.

Lecture Summary on MOS Devices: Basics
We have learned MOS Devices in this seminar, in a quick manner. If you want to know deep in MOS devices, another couple of seminars will be necessary, with hard self-learning of Textbooks. Following area will be helpful for your future learning: Compact MOSFET Modeling for circuit simulation MOS device variability and its design methodology Reliability of MOS Devices Analog MOS devices and circuits etc. Hoping you to challenge the above topics next time.

210

©2007. Renesas Technology Corp., All rights reserved.

Quiz
(1) What is the general approach to shrink MOS structure? (2) Why it has been successful, so far? (3) List up the problems on MOSFET scaling down. (4) How the process engineer overcome the each problem? (5) If carrier (electron, hole) moves in velocity saturation in short channel MOS, further shrink in L does not increase Ids. What is the physical reason? (6) Even in the condition of (5), people prefer to shrink L. Why it comes?

211

©2007. Renesas Technology Corp., All rights reserved.

212

©2007. Renesas Technology Corp., All rights reserved.

Appendix
1. 2. 3. 4. 5. 6. 7. 8. 9. List of Symbols Physical Constant Properties of Si, Ge, GaAs and SiO2 Physical Parameters of Silicon Equations in Semiconductor Physics Equations in PN-Diode Equations in MOS-Diode Equations in MOSFET (Simple) Equations in MOSFET (First-order)

213

©2007. Renesas Technology Corp., All rights reserved.

1. List of symbols
Symbol a c C E EC EF Eg EV F(E) I J k kT L mo m* n ni N NA NC Lattice constant Speed of light in vacuum Capacitance Energy Bottom of conduction band Fermi energy level Energy bandgap Top of valence band Fermi-Dirack distribution function Current Current density Boltzmann constant Thermal energy Length (channel length) Electron rest mass Effective mass Density of free electron Intrinsic density Doping concentration Accepter impurity density Effective density states in conduction band Description

(After Textbook of Sze)
Unit m m/s F eV eV eV eV eV A A/m2 J/K eV m kg kg m-3 m-3 m-3 m-3 m-3

214

©2007. Renesas Technology Corp., All rights reserved.

Continued…
Symbol ND NV p q R t T v vth V Vbi VFB Vth εo εs or εsi εI or εox μn μp ρ φm Ω Donor impurity concentration Effective density of states in valence band Density of free hole Magnitude of electronic charge Resistance time Absolute temperature Carrier velocity Thermal velocity Voltage Built-in voltage Flat band voltage Threshold voltage Permittivity in vacuum Semiconductor permittivity Insulator permittivity Electron mobility Hole mobility Resistivity Metal work function Ohm Description m-3 m-3 m-3 C Ω s K m/s m/s V V V V F/m F/m F/m m2/V.s m2/V.s Ω-m V Ω Unit

215

©2007. Renesas Technology Corp., All rights reserved.

2. Physical constant
Quantity Elementary charge Electron rest mass Electron volt Permittivity in vacuum Speed of light Thermal voltage @300K Symbol q mo eV εo c kT/q Value 1.60X10-19 C 0.911X10-30 kg 1.60X10-19 J 8.85X10-12 F/m 3.00X108 m/s 0.0259 V

216

©2007. Renesas Technology Corp., All rights reserved.

3. Properties of Ge, Si, GaAs and SiO2

(After Textbook of Grove) 217 ©2007. Renesas Technology Corp., All rights reserved.

Continued …..

218

©2007. Renesas Technology Corp., All rights reserved.

4. Key Physical Parameters of Silicon
Molecular Number ( /cm3) Crystal Structure Lattice Constant a (nm) Material Density (g/cm3) Energy Gap (eV) Density of State: Conduction Band Nc(cm-3) Valence Band Nv(cm-3) Intrinsic Carrier Density ni (cm-3) Intrinsic Carrier Mobility: Elec. (cm2/V.sec) Hole (cm2/V.sec) Permittivity ε(si) Thermal Conductance kth(W/cm.℃) Thermal Expansion Constant (/℃) Melting Temperature (℃) 5.00X1022 Diamond 0.543 2.33 1.11 2.8X1019 1.04X1019 1.45X1010 1350 480 11.7 1.5 2.5X10-6 1415

219

©2007. Renesas Technology Corp., All rights reserved.

5. Equations of Semiconductor Physics

(After Textbook of Grove) 220 ©2007. Renesas Technology Corp., All rights reserved.

6. Equations of PN-Diode

(After Textbook of Grove) 221 ©2007. Renesas Technology Corp., All rights reserved.

7. Equations of MOS-Diode
Metal and semiconductor workfunction difference (φMS) Flat-band Voltage (VFB) Physical Threshold Voltage (Vth) MOS Capacitance at Accumulation Condition
⎡ ⎣ kT ⎛ N C ⎞⎤ ln⎜ ⎜ N ⎟⎥ q ⎝ A ⎟⎦ ⎠

φMS = χ M − ⎢ χ Si + E g ( Si ) −

VFB = φMS −

QSS CO
QB kT ⎛ N A ⎞ ⎟ , QB = 2ε S qN A (2φF ) , φF = ln⎜ CO q ⎜ ni ⎟ ⎠ ⎝

Vth = VFB + 2φF

C Acc = CO
C FB = CO 1 , LD = kTε S q2 N A

MOS Capacitance at Flat-Band
Condition

1+

ε S LD ε OX TOX

MOS Capacitance at Inversion
Condition

C Inv = CO

1+

ε S Wm ε OX TOX

, Wm =

4kTε S ln ( N A ni ) q2 N A

222

©2007. Renesas Technology Corp., All rights reserved.

8. Equations of MOSFET (simple)
Linear region Current-voltage characteristics Saturation voltage Drain conductance Mutual conductance Max. frequency
I ds = V W ⎛ μ nCo ⎜Vg − Vth − d 2 L ⎝ ⎞ ⎟Vd ⎠

Saturation region

I ds =

1W μ nCo (Vg − Vth )2 2 L

VDsat = Vg − Vth

gd =

1W μ nCo (Vg − Vth − Vd ) 2 L
W μ nCoVd L
g m μ nVd = 2 CG L

gd = 0
gm = W μ nCo (Vg − Vth ) L

gm =
fO =

g m μ n (Vg − Vth ) = fO = CG L2

223

©2007. Renesas Technology Corp., All rights reserved.

9. Equations of MOSFET (First-order)

gm CG

gm CG

(After Textbook of Grove) 224 ©2007. Renesas Technology Corp., All rights reserved.

FIN !
October, 2007

©2007. Renesas Technology Corp., All rights reserved.

Sign up to vote on this title
UsefulNot useful

Master Your Semester with Scribd & The New York Times

Special offer for students: Only $4.99/month.

Master Your Semester with a Special Offer from Scribd & The New York Times

Cancel anytime.