First revision documentation by Cliff Cummings

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First revision documentation by Cliff Cummings

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You are on page 1of 8

Clifford E. Cummings

Sunburst Design, Inc.

15870 SW Breccia Drive

Beaverton, OR 97007

cliffc@sunburst-design.com

Abstract input changes is shorter than a procedural assignment

delay, a continuous assignment delay, or gate delay, a

Design engineers frequently build Verilog models previously scheduled but unrealized output event is

with behavioral delays. Most hardware description replaced with a newly scheduled output event.

languages permit a wide variety of delay coding styles but Transport delay models propagate all signals to an

very few of the permitted coding styles actually model output after any input signals change. Scheduled output

realistic hardware delays. Some of the most common value changes are queued for transport delay models.

delay modeling styles are very poor representations of Reject & Error delay models propagate all signals

real hardware. This paper examines commonly used that are greater than the error setting, propagate unknown

delay modeling styles and indicates which styles behave values for signals that fall between the reject & error

like real hardware, and which do not. settings, and do not propagate signals that fall below the

reject setting.

1.0 Introduction For most Verilog simulators, reject and error settings

are specified as a percentage of propagation delay in

multiples of 10%.

One of the most common behavioral Verilog coding

styles used to model combinational logic is to place

delays to the left of blocking procedural assignments Pure inertial delay example using reject/error switches.

inside of an always block. This coding style is flawed as it Add the Verilog command line options:

can either easily produce the wrong output value or can

propagate inputs to an output in less time than permitted +pulse_r/100 +pulse_e/100

by the model specifications. reject all pulses less than 100% of propagation delay.

This paper details delay-modeling styles using

continuous assignments with delays, and procedural Pure transport delay example using reject/error switches.

assignments using blocking and nonblocking assignments Add the Verilog command line options:

with delays on either side of the assignment operator.

To help understand delay modeling, the next section +pulse_r/0 +pulse_e/0

also includes a short description on inertial and transport pass all pulses greater than 0% of propagation delay.

delays, and Verilog command line switches that are

commonly used to simulate a model that is neither a fully Semi-realistic delay example using reject/error switches.

inertial-delay model nor a fully transport-delay model. Add the Verilog command line options:

+pulse_r/30 +pulse_e/70

2.0 Inertial and transport delay modeling reject pulses less than 30%, propagate unknowns for

pulses between 30-70% and pass all pulses greater

Inertial delay models only propagate signals to an than 70% of propagation delay.

output after the input signals have remained unchanged

(been stable) for a time period equal to or greater than the

Rev 1.1 To Verilog Behavioral Models

module adder_t1 (co, sum, a, b, ci);

3.0 Blocking assignment delay models output co;

output [3:0] sum;

Adding delays to the left-hand-side (LHS) or right- input [3:0] a, b;

hand-side (RHS) of blocking assignments (as shown in input ci;

Figure 1) to model combinational logic is very common reg co;

among new and even experienced Verilog users, but the reg [3:0] sum;

practice is flawed.

always @(a or b or ci)

#12 {co, sum} = a + b + ci;

always @(a) Procedural blocking endmodule

y = ~a; assignment - no delay

Figure 2 - LHS Blocking Assignment

always @(a) Procedural blocking Adding delays to the left hand side (LHS) of any

#5 y = ~a; assignment - LHS delay sequence of blocking assignments to model

combinational logic is also flawed.

The adder_t7a example shown in Figure 4 places

always @(a) Procedural blocking the delay on the first blocking assignment and no delay on

y = #5 ~a; assignment - RHS delay the second assignment. This will have the same flawed

behavior as the adder_t1 example.

Figure 1 - Blocking Assignments with Delays The adder_t7b example, also shown in Figure 4,

places the delay on the second blocking assignment and

For the adder_t1 example shown in Figure 2, the no delay on the first. This model will sample the inputs on

outputs should be updated 12ns after input changes. If the the first input change and assign the outputs to a

a input changes at time 15 as shown in Figure 3, then if temporary location until after completion of the specified

the a, b and ci inputs all change during the next 9ns, the blocking delay. Then the outputs will be written with the

outputs will be updated with the latest values of a, b and old temporary output values that are no longer valid.

ci. This modeling style has just permitted the ci input to Other input changes within the 12ns delay period will not

propagate a value to the sum and carry outputs after be evaluated, which means old erroneous values will

only 3ns instead of the required 12ns propagation delay. remain on the outputs until more input changes occur.

always block after last input change

0 12 15 17 19 21 24 27 29 31 33 36

a 0 A 2 F

b 0 3

ci 0 1

sum X 0 3

co X 0 1

Rev 1.1 To Verilog Behavioral Models

These adders do not model any known hardware. also flawed.

For the adder_t6 example shown in Figure 5, the

Modeling Guideline: do not place delays on the LHS of

outputs should be updated 12ns after input changes. If the

blocking assignments to model combinational logic. This

is a bad coding style. a input changes at time 15, the RHS input values will be

sampled and the outputs will be updated with the sampled

Testbench Guideline: placing delays on the LHS of value, while all other a, b and ci input changes during

blocking assignments in a testbench is reasonable since the next 12ns will not be evaluated. This means old

the delay is just being used to time-space sequential input erroneous values will remain on the outputs until more

stimulus events. input changes occur.

The same problem exists with multiple blocking

module adder_t7a (co, sum, a, b, ci); assignments when delays are placed on the RHS of the

output co; assignment statements. The adder_t11a and

output [3:0] sum;

input [3:0] a, b; adder_t11b examples shown in Figure 6 demonstrate

input ci; the same flawed behavior as the adder_t6 example .

reg co; None of the adder examples with delays on the RHS

reg [3:0] sum; of blocking assignments behave like any known

reg [4:0] tmp; hardware.

always @(a or b or ci) begin Modeling Guideline: do not place delays on the RHS of

#12 tmp = a + b + ci; blocking assignments to model combinational logic. This

{co, sum} = tmp; is a bad coding style.

end

endmodule Testbench Guideline: do not place delays on the RHS of

blocking assignments in a testbench.

module adder_t7b (co, sum, a, b, ci); General Guideline: placing a delay on the RHS of any

output co; blocking assignment is both confusing and a poor coding

output [3:0] sum; style. This Verilog coding practice should be avoided.

input [3:0] a, b;

input ci;

module adder_t11a (co, sum, a, b, ci);

reg co;

output co;

reg [3:0] sum;

output [3:0] sum;

reg [4:0] tmp;

input [3:0] a, b;

input ci;

always @(a or b or ci) begin

reg co;

tmp = a + b + ci;

reg [3:0] sum;

#12 {co, sum} = tmp;

reg [4:0] tmp;

end

endmodule

always @(a or b or ci) begin

Figure 4 - Multiple LHS Blocking Assignments tmp = #12 a + b + ci;

{co, sum} = tmp;

end

3.1 RHS blocking delays endmodule

Adding delays to the right hand side (RHS) of

blocking assignments to model combinational logic is module adder_t11b (co, sum, a, b, ci);

output co;

module adder_t6 (co, sum, a, b, ci); output [3:0] sum;

output co; input [3:0] a, b;

output [3:0] sum; input ci;

input [3:0] a, b; reg co;

input ci; reg [3:0] sum;

reg co; reg [4:0] tmp;

reg [3:0] sum;

always @(a or b or ci) begin

always @(a or b or ci) tmp = a + b + ci;

{co, sum} = #12 a + b + ci; {co, sum} = #12 tmp;

endmodule end

endmodule

Figure 5 - RHS Blocking Assignment

Figure 6 - Multiple RHS Blocking Assignments

Rev 1.1 To Verilog Behavioral Models

Testbench Guideline: nonblocking assignments are less

4.0 Nonblocking assignment delay models efficient to simulate than blocking assignments; therefore,

in general, placing delays on the LHS of nonblocking

assignments for either modeling or testbench generation is

discouraged.

always @(a) Procedural nonblocking

y <= ~a; assignment - no delay

4.1 RHS nonblocking delays

always @(a) Procedural nonblocking Adding delays to the right hand side (RHS) of

#5 y <= ~a; assignment - LHS delay nonblocking assignments (as shown in Figure 9) will

accurately model combinational logic with transport

delays.

always @(a) Procedural nonblocking In the adder_t3 example shown in Figure 9, if the

y <= #5 ~a; a input changes at time 15 as shown in Figure 10 (next

assignment - RHS delay

page), then all inputs will be evaluated and new output

values will be queued for assignment 12ns later.

Figure 7 - Nonblocking Assignments with Delays Immediately after the outputs have been queued

(scheduled for future assignment) but not yet assigned,

Adding delays to the left-hand-side (LHS) of the always block will again be setup to trigger on the next

nonblocking assignments (as shown in Figure 7) to model input event. This means that all input events will queue

combinational logic is flawed. new values to be placed on the outputs after a 12ns delay.

The same problem exists in the adder_t2 example This coding style models combinational logic with

shown in Figure 8 (nonblocking assignments) that existed transport delays.

in the adder_t1 example shown in Figure 2 (blocking

assignments). If the a input changes at time 15, then if the module adder_t3 (co, sum, a, b, ci);

a, b and ci inputs all change during the next 9ns, the output co;

outputs will be updated with the latest values of a, b and output [3:0] sum;

input [3:0] a, b;

ci. This modeling style permitted the ci input to input ci;

propagate a value to the sum and carry outputs after reg co;

only 3ns instead of the required 12ns propagation delay. reg [3:0] sum;

output co; {co, sum} <= #12 a + b + ci;

output [3:0] sum; endmodule

input [3:0] a, b;

input ci; Figure 9 - RHS Nonblocking Assignment

reg co;

reg [3:0] sum;

Recommended Application: Use this coding style to

always @(a or b or ci) model behavioral delay-line logic.

#12 {co, sum} <= a + b + ci;

endmodule

Modeling Guideline: place delays on the RHS of

nonblocking assignments only when trying to model

Figure 8 - LHS Nonblocking Assignment transport output-propagation behavior. This coding style

will accurately model delay lines and combinational logic

It can similarly be shown that adding delays to the with pure transport delays; however, this coding style

left hand side (LHS) of any sequence of nonblocking generally causes slower simulations.

assignments to model combinational logic is also flawed.

Testbench Guideline: This coding style is often used in

Adders modeled with LHS nonblocking assignments

testbenches when stimulus must be scheduled on future

do not model any known hardware.

clock edges or after a set delay, while not blocking the

Modeling Guideline: do not place delays on the LHS of assignment of subsequent stimulus events in the same

nonblocking assignments to model combinational logic. procedural block.

This is a bad coding style.

Rev 1.1 To Verilog Behavioral Models

Trigger the

always block

0 12 15 17 19 21 24 27 29 31 33 36

a F

0 A 2

b 3

0

ci 0

sum 2

X 0 A D 5

co 1

X 0

4.2 Multiple RHS nonblocking delays output co;

output [3:0] sum;

Adding delays to the right hand side (RHS) of

input [3:0] a, b;

multiple sequential nonblocking assignments to model input ci;

combinational logic is flawed, unless all of the RHS input reg co;

identifiers are listed in the sensitivity list, including reg [3:0] sum;

intermediate temporary values that are only assigned and reg [4:0] tmp;

used inside the always block, as shown in Figure 11.

For the adder_t9c and adder_t9d examples always @(a or b or ci or tmp) begin

shown in Figure 11, the nonblocking assignments are tmp <= #12 a + b + ci;

{co, sum} <= tmp;

executed in parallel and after tmp is updated, since tmp end

is in the sensitivity list, the always block will again be endmodule

triggered, evaluate the RHS equations and update the

LHS equations with the correct values (on the second pass

through the always block). module adder_t9d (co, sum, a, b, ci);

output co;

Modeling Guideline: in general, do not place delays on output [3:0] sum;

the RHS of nonblocking assignments to model input [3:0] a, b;

combinational logic. This coding style can be confusing input ci;

and is not very simulation efficient. It is a common and reg co;

sometimes useful practice to place delays on the RHS of reg [3:0] sum;

reg [4:0] tmp;

nonblocking assignments to model clock-to-output

behavior on sequential logic. always @(a or b or ci or tmp) begin

Testbench Guideline: there are some multi-clock design tmp <= a + b + ci;

{co, sum} <= #12 tmp;

verification suites that benefit from using multiple

end

nonblocking assignments with RHS delays; however, this endmodule

coding style can be confusing, therefore placing delays on

the RHS of nonblocking assignments in testbenches is not Figure 11 - Multiple Nonblocking Assignments

generally recommended. with Delays

Rev 1.1 To Verilog Behavioral Models

module adder_t4 (co, sum, a, b, ci);

5.0 Continuous assignment delay models output co;

output [3:0] sum;

input [3:0] a, b;

input ci;

Continuous assign #12 {co, sum} = a + b + ci;

assign y = ~a;

assignment - no delay endmodule

Continuous

assign #5 y = ~a;

assignment - LHS delay

will cause any future scheduled output-event (output

value with corresponding assignment time) to be replaced

Illegal continuous with a new output-event.

assign y = #5 ~a;

assignment - RHS delay Figure 14 shows the output waveforms for a

simulation run on the adder_t4 code shown in Figure

13. The first a-input change occurs at time 15, which

causes an output event to be scheduled for time 27, but a

assign y <= ~a; Illegal continuous

change on the b-input and two more changes on the a-

nonblocking assignment

input at times 17, 19 and 21 respectively, cause three new

output events to be scheduled. Only the last output event

Figure 12 - Continuous Assignments with Delays actually completes and the outputs are assigned at time

33.

Adding delays to continuous assignments (as shown Continuous assignments do not "queue up" output

in Figure 12) accurately models combinational logic with assignments, they only keep track of the next output value

inertial delays and is a recommended coding style. and when it will occur; therefore, continuous assignments

For the adder_t4 example shown in Figure 13, the model combinational logic with inertial delays.

outputs do not change until 12ns after the last input

change (12ns after all inputs have been stable). Any

sequence of input changes that occur less than 12ns apart

Trigger the

assign statement

0 12 15 17 19 21 24 27 29 31 33 36

a F

0 A 2

b 3

0

ci 0

sum 2

X 0

co 1

X 0

Rev 1.1 To Verilog Behavioral Models

with inertial delays.

5.1 Multiple continuous assignments For the adder_t5 example shown in Figure 16, the

It can similarly be shown that modeling logic tmp variable is updated after any and all input events.

functionality by adding delays to continuous assignments, The continuous assignment outputs do not change until

whose outputs are used to drive the inputs of other 12ns after the last change on the tmp variable. Any

continuous assignments with delays, as shown in Figure sequence of always block input changes will cause tmp to

15, also accurately models combinational logic with change, which will cause a new output event on to be

inertial delays. scheduled on the continuous assignment outputs. The

continuous assignment outputs will not be updated until

module adder_t10a (co, sum, a, b, ci); tmp remains unchanged for 12ns. This coding style

output co; models combinational logic with inertial delays.

output [3:0] sum;

input [3:0] a, b; Modeling Guideline: Use continuous assignments with

input ci; delays to model simple combinational logic. This coding

wire [4:0] tmp; style will accurately model combinational logic with

inertial delays.

assign tmp = a + b + ci;

assign #12 {co, sum} = tmp; Modeling Guideline: Use always blocks with no delays

endmodule to model complex combinational logic that are more

easily rendered using Verilog behavioral constructs such

module adder_t10b (co, sum, a, b, ci); as "case-casez-casex", "if-else", etc. The outputs from the

output co; no-delay always blocks can be driven into continuous

output [3:0] sum; assignments to apply behavioral delays to the models.

input [3:0] a, b;

input ci;

This coding style will accurately model complex

wire [4:0] tmp; combinational logic with inertial delays.

Testbench Guideline: Continuous assignments can be

assign #12 tmp = a + b + ci;

assign {co, sum} = tmp;

used anywhere in a testbench to drive stimulus values

endmodule onto input ports and bi-directional ports of instantiated

models.

Figure 15 - Multiple Continuous Assignments

6.0 Conclusions

5.2 Mixed no-delay always blocks and Any delay added to statements inside of an always

continuous assignments block does not accurately model the behavior of real

Modeling logic functionality in an always block with hardware and should not be done. The one exception is to

no delays, then passing the always block intermediate carefully add delays to the right hand side of nonblocking

values to a continuous assignment with delays as, shown assignments, which will accurately model transport

in Figure 16, will accurately model combinational logic delays, generally at the cost of simulator performance.

Adding delays to any sequence of continuous

assignments, or modeling complex logic with no delays

module adder_t5 (co, sum, a, b, ci);

inside of an always block and driving the always block

output co;

output [3:0] sum; outputs through continuous assignments with delays, both

input [3:0] a, b; accurately model inertial delays and are recommended

input ci; coding styles for modeling combinational logic.

reg [4:0] tmp;

tmp = a + b + ci;

Author & Contact Information

end

Cliff Cummings, President of Sunburst Design, Inc., is an

assign #12 {co, sum} = tmp; independent EDA consultant and trainer with 19 years of

endmodule ASIC, FPGA and system design experience and nine

years of Verilog, synthesis and methodology training

Figure 16 - No-Delay Always Block & Continuous

experience.

Assignment

Rev 1.1 To Verilog Behavioral Models

Mr. Cummings, a member of the IEEE 1364 Verilog

Standards Group (VSG) since 1994, chaired the VSG

Behavioral Task Force, which was charged with

proposing enhancements to the Verilog language. Mr.

Cummings is also a member of the IEEE Verilog

Synthesis Interoperability Working Group.

Mr. Cummings holds a BSEE from Brigham Young

University and an MSEE from Oregon State University.

This paper can be downloaded from the web site:

www.sunburst-design.com/papers

Rev 1.1 To Verilog Behavioral Models

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