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65nm CMOS Process Technology

Paul Kim Senior Manager, Foundry Services Fujitsu Microelectronics America, Inc.

Leading-edge Technology

Fujitsu 65nm

New 300mm Fabs Mie, Japan


300mm Fab No.2
Process 65nm/90nm CMOS Logic Structural Features Seismic-vibration control construction Clean room area: 24,000 sq. meters Production Capacity 10,000 wafers per month (FY07 projection) Maximum capacity of 25,000 wafers per month Planned Start of Operation April 2007

300mm Fab No.1


Process 90nm/65nm CMOS Logic Structural Features Seismic-control construction Clean room area: 12,000 sq. meters Production Capacity 15,000 wafers per month (FY06) Start of Operation April 2005

February 7, 2006

DesignCon 2006

Leading-edge Technology

Fujitsu 65nm

CMOS Technology Roadmap

1000

Physical Gate Length (nm)

180nm 180nm

500 200 100


CS90 CS80 / 80A

130nm 130nm

90nm 90nm 65nm 65nm 45nm 45nm

CS90A CS100A CS200A

CS100/CS100A (90nm) L actual=40-80nm SiOC (k:2.9) low-k Dual Damascene Cu CS200/CS200A (65nm) L actual=30-50nm NCS (Nano-Clustering Silica)

50
CS100HP

20 10 1998 2000 2002 2004

CS200

2006

2008

2010

Year (Production Start)


February 7, 2006

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Proven Track Record of 90nm Complex Designs and Products

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Proven Track Record of 90nm Complex Designs and Products continued


350-450 250-350 200-250 100-200 50-100 20-50 0 5 10 Tape Out Number
High End Low Power

Low-power Products Multimedia processor Digital AV products Others

February 7, 2006

Chip Size (mm2)

High-performance Products PC CPU (Transmeta) Large-scale FPGA (Lattice) Others

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Leading-edge Technology

Fujitsu 65nm

65nm, CS200 / 200A Features

Features
Ultra-high-speed performance (CS200) LG = 30nm, on-current enhance Compared to 90nm technology, CS200 offers: 1.3 times faster speed 0.6 times lower power 2 times higher density 3 variations of Vth on a chip (CS200A) (1.8V & 2.5V) or (1.8V & 3.3V) I/O combination available 11-layer copper interconnects with robust, very low K ILD

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Fujitsu 65nm

CS200 / 200A Transistor Variations

CS200: Ultra High Speed CS200A: Wide Speed Range + Low Power Consumption

Large

HS-Tr Server/ Network STD-Tr HVt-Tr Mobile Computing STD-Tr Digital Consumer

CS200

Leakage current

CS200A

HS-Tr

High End Server

LL-Tr Cellular Phone

HS:High speed STD:Standard LL:Low leakage

Speed
February 7, 2006

Fast
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Fujitsu 65nm

Leading-edge Transistors

Large

Performance
90nm node 65nm node 45nm node

Small

Leakage

tpd P

Fast
February 7, 2006

Propagation Delay
8

Slow
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Leading-edge Technology

Fujitsu 65nm

Ultra-Thin Gate Insulator / Mobility Improvement


Surface Cleaning
Normalized gm ( mobility)
2.0E-3

1nm-thick Gate Oxide

Poly-Si Nitrided-SiO2

40% increase

1.5E-3

1.0E-3

After optimize

5.0E-4

Si substrate

Before
0.0 -0.5 1.5 3.5 5.5

Electric Field [MV/cm]

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Speed Performance Improvements

65nm CS200 (ps/gate) Inverter 2-input NAND 2-input NAND + 200 grid interconnect load 5.7 8.7 23.1

90nm CS100 Delay (ps/gate) Improvement 7.0 11.4 30.8 19% 24% 25%

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High-Performance Competitive Transistors

Ion vs Ioff Characteristics of nMOSFETs


10-6

Ioff (A/um)

10-7

Company 1) B Company 2) 70nA/m A

Fujitsu
10-8
Ref. 1, 2) 2004 Symposium on VLSI Technology

Vd=1.0V

10-9 0.7

0.8

0.9

1.0 1.1 Ion (uA/um)

1.2

1.3

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Leading-edge Technology

Fujitsu 65nm

Advanced Cu and Low-k

Four Generations of Experience

Dielectric constant High Low

CS80/80A 6-Cu layers ILD FSG

CS90A 7-Cu layers ILD hybrid low-k CS100/100A/150 10-Cu layers ILD full low-k CS200/200A/250 11-Cu layers ILD hybrid Ultra-low K

ILD: Inter-layer Dielectric

180nm node
February 7, 2006

130nm node
12

90nm node

65nm node
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Fujitsu 65nm

Fujitsus Low-k Leads ITRS


500 <2.7 <2.4 3.0

k
2.5 <2.1 <1.9 2.0

400

Width [nm]

300
Intermediate Wire Pitch

200

1.5

130nm 130nm 100 90nm 90nm 65nm 65nm 45nm 45nm


CMOS Technology Node

1.0 32nm 32nm 2015 CS300 Full - NCS

0 2000 CS90 SiLK TM/SiO

2005 CS100 Full- SiOC

2010 CS200 NCS/ SiOC

Products Year
2

K=2.7/4.1
February 7, 2006

K=2.9/2.9
13

K=2.25/2.9

K=2.25/2.25
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Low-k Advantages of 65nm

Ultra low-k impacts on speed and power dissipation

CS100A (90nm) with SiOC/SiOC Rsh: 90m/sq., C: 56fF/1000 grid CS200A (65nm) with SiOC/SiOC Rsh: 150m/sq., C: 52fF/1000 grid CS200A (65nm) with NCS/SiOC Rsh: 150m/sq., C: 40fF/1000 grid

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Fujitsu 65nm

11-Layer Copper Interconnects


Cu 11-layer Stack-via Chain

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The Fujitsu Ecosystem


Application Application & Software & Software Packaging, Packaging, Assembly Assembly & Test & Test Process Process Technology Technology Design Design Methodology Methodology EDA Design Design Services Services 3rd Party Design Houses IP IP Development Development & Support & Support 3rd Party IP Vendors Support Support Library Library Development Development 3rd Party Library Vendors

3rd Party Test Houses

Vendors

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Leading-edge Technology

Fujitsu 65nm

Fujitsu Technology Access

Flexible collaboration models provide easy access to Fujitsus leading-edge process for the development of highly complex silicon products

ASIC Flow
Customer Fujitsu

COT Flow
Customer Fujitsu

Custom Flow
Customer Fujitsu

RTL Design

Logical Synthesis DFT Insertion Formal Verification Floorplanning Physical Synthesis Clock Tree Synthesis Routing Timing & SI Verification STA / ECO Physical Verification Test Validation

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Design Flow & Methodology

Reference design flow - Fujitsus leading-edge design methodology focuses on timing, signal and power integrity closure Support for both Cadence SOCEncounterTM and Synopsys GalaxyTM platforms In-house CAD software development augments leading third-party EDA solutions Ensures silicon correlation and a fast path to silicon success by combining Fujitsus strengths in process, CAD tool and methodology development with design experience and expertise Production proven flows used on 100+ multi-million-gate designs at 180, 130 and 90nm Constantly updated and improved to address all issues at each process node

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Leading-edge Technology

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Fujitsu Design Services

Library and tool support Methodology development and support High-speed I/O design and expertise Vertical expertise and IP cores RTL design Synthesis and physical synthesis Design partitioning and floorplanning Static timing analysis Test insertion and ATPG generation Place and route Timing and SI closure Formal verification Physical verification Test and product engineering
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Fujitsu Worldwide Design Centers

Global Presence
Local design centers around the world provide design services for all phases of the development process

Skilled engineering teams experienced in development of large complex designs at 130nm and below 100+ multi-million gate designs taped out
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Leading-edge Technology

Fujitsu 65nm

Summary

Fujitsu Objective Helping customers accelerate their innovation, differentiate their products and enhance their competitive advantage, therefore helping them succeed Leading-edge technologies Strength in process technologies 90nm, 65nm and beyond Partnerships and customer collaborations Flexible customer engagements and close collaborations Early customer engagements Tailored support and services to meet customer needs System-level LSI solutions ASIC and ASSP/SoC, including10GbE switch chip and WiMAX SoC Full design and development environments and support
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DesignCon 2006