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1, JANUARY 2010


New Resonant Step-Down/Up Converters
Masoud Jabbari, Student Member, IEEE, and Hosein Farzanehfard, Member, IEEE
Abstract—This paper presents two new resonant step-down/up converters, where all active elements operate under soft-switching condition independent of load and operating voltages. One of the proposed converters has positive voltage gain and the other has negative voltage gain. Although, the proposed topologies are similar to that of the single ended primary inductor converter, operations of the proposed converters are completely different. In fact, the inductors and coupling capacitor create resonant networks. Thereby, not only soft-switching condition is achieved, but also the passive components size is reduced considerably. Experimental results from a 250 W laboratory prototype verify the presented operation and theoretical analysis of the proposed converters. Index Terms—Resonant converter, soft-switching, step-down/up converter, zero current switching (ZCS).

I. INTRODUCTION OFT-SWITCHING techniques are developed to reduce switching losses and electromagnetic interference (EMI). At soft-switching condition, switching frequency can be increased to enhance the converter power density. This condition is commonly attained by zero voltage switching (ZVS) and zero current switching (ZCS) [1]–[3]. An insulated gate bipolar transistor (IGBT) is a proper switch for power applications. ZCS technique is compatible with the IGBT characteristics because tailing-current losses are eliminated. Since conduction losses of IGBT are mainly a function of the average rather than the rms current, higher peak-to-average due to the sinusoidal current waveforms of the resonant converters is not detrimental [1], [4], and [5]. In order to decrease current stresses, unnecessary energy circulation should be prevented and hence unidirectional switches are employed [1]–[3]. Conventional buck-boost-type converters include the basic pulsewidth modulation (PWM) buck-boost and C´ k converters, u which provide negative voltage gain, and, single ended primary inductor converter (SEPIC) and Zeta converters which provide positive voltage gain [6]–[29]. These converters are widely employed as power supplies [9]–[29] and PFC regulators [6]–[8]. In C´ k, SEPIC, and Zeta converters, the coupling u capacitor is the main energy storage element and thus its voltage should be almost constant. A significant disadvantage is the requirement of a large capacitor with a high ripple-currentcarrying capability [1]. Various methods have been presented in the literature to provide soft-switching condition for the SEPIC converter [6]–[29]. Almost all of these methods preserve the


Fig. 1.

(a) Proposed noninverting. (b) Inverting step down/up converters.

Manuscript received January 20, 2009; revised June 7, 2009. Current version published January 29, 2010. Recommended for publication by Associate Editor M. Vitelli. The authors are with the Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 84154, Iran (e-mail: jabbari.; Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 10.1109/TPEL.2009.2028734

overall operation of the SEPIC converter while attempting to achieve soft-switching condition by adding auxiliary elements. The number of added elements is between 2 for quasi-resonant type [2], [3] and 7 in complex cells [18], [19]. However, the number of elements of a converter is one of the most important considerations, since it greatly affects on the converter cost and volume. In this paper, two new resonant step-down/up dc–dc converters are presented where both have exactly the same operation except the sign of voltage gain [Fig. 1(a) and (b)]. All switches are turned on and off at ZCS and the diode operates at ZCS or ZVS. In view of step down/up voltage gain with positive output voltage polarity and the general topology of the proposed circuit as shown in Fig. 1(a), it is very similar to the SEPIC converter with only one extra switch at input. The coupling capacitor Cr which still provides magnetic isolation, is now a resonant capacitor and hence its capacity becomes much less than that of the conventional SEPIC converter. Consequently, the operation of the proposed converters is completely different than the conventional SEPIC converter. In other words, in the proposed converters, Cr and inductors constitute resonance networks. The transistors Q1 and Q2 , which in fact construct a half-bridge structure, are unidirectional switches and thus energy does not return to source. Moreover, the inductor L1 eliminates the spiky current flowing through the on switch and the output capacitance of the off switch. The converters can operate at DCM and CCM where soft-switching condition is always attained independent of load and operating voltages. In the proposed topologies, soft-switching condition is provided by adding only one extra element, and current stresses and size of the passive components are considerably reduced. All these merits are obtained only at the cost of relatively higher voltage stress of one of the switches. However, in comparison to current stress and energy

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At t2 . Q2 is turned on at ZCS and the polarity of vr starts reversing until it reaches −VO at t3 vr (t) = (2 + A) cos VS ω √r (t − t2 ) α (11) (12) (13) (14) In the converter of Fig. Duration of this interval is determined by the controller. its parasitic capacitor has been absorbed by Cr . all stray inductors and the switches parasitic inductances are absorbed by L1 and L2 . two states at discontinuous conduction mode (DCM) and two states at continuous conduction mode (CCM). Any time during this mode Q2 can be turned off at ZVZCS. t4 − t 3 = ωr A 4) Mode IV (t4 − t5 ): In this mode. To simplify the analysis. fr = = ωr = √ Tr 2π Lr Cr α= Zr = r= A= Lr /Cr R Zr |VO | . it is assumed that the converter is in steady state. all elements are ideal. so that proper voltage regulation is attained (deadtime control). 2. C and Cr are set in parallel with D. α≤1 Lr 1 1 ωr . These conditions are viewed for the current of L2 which is defined as resonance current. 1) Mode I (t1 − t2 ): At t1 . 1. L1 + L2 (7) ωr 2VS + VO sin √ (t − t2 ) ir (t) = − √ αZr α √ α A t3 − t 2 = π − cos−1 ωr 2+A 2VS √ 1 + A. the voltage across L2 is as (7). DCM Operation with α < A/(1 + A) Fig. Q1 is turned on at ZCS and Cr is charged through a resonance with L1 and L2 . VOL. By turning Q1 on at t = t1 . ANALYSIS OF THE CONVERTERS Both proposed converters have four operating conditions. II. JANUARY 2010 circulation. These . 25. ir reaches zero and Q1 is turned off at ZCS. DCM operation with α < A/(1 + A). ir . In comparison with the conventional SEPIC converter. In other words. and all semiconductor devices are off. 1(a). 2 illustrates key waveforms of the converter at DCM condition with α < A/(1 + A). ir (t3 ) = − √ αZr A. The entire energy absorbed by Cr in Mode I is now pumped to the output ir (t) = ir (t3 ) + VO (t − t3 ) L2 (15) (16) √ √ 2 α 1+A . an LC filter can be added at the input to make the source current continuous if deemed necessary. Thus D does not turn on if vL 2 (t+ ) < VO . In the following discussions. Since the diode is turned on at ZVS. At this time vr has reached 2VS + VO vr (t) = 1 − (1 + A) cos(ωr (t − t1 )) VS ir (t) = t2 − t1 = VS + VO sin(ωr (t − t1 )) Zr Tr . assume that the resonance voltage vr is −VO . The modal analysis is as follows. The magnitude of ir decreases linearly until at t4 it reaches zero. the input current is discontinuous. when Q2 is turned on. and output capacitor C is large enough such that the output voltage is constant during one switching cycle. According to the equivalent circuits of each operating mode. all switches are off and the load is supplied by the output capacitor. voltage stress does not produce extra conduction losses. VS (1) (2) (3) (4) (5) (6) Fig. Considering the major advantages created by this topology. Following definitions are made: Lr = L1 + L2 L2 . NO. 2) Mode II (t2 − t3 ): At t2 . or α < A/(1 + A) 1 vL 2 (t+ ) = 1 L2 (VS + VO ) . At this time D is turned off at ZCS.250 IEEE TRANSACTIONS ON POWER ELECTRONICS. 1(a) is considered. 2 (8) (9) (10) 3) Mode III (t3 − t4 ): At t3 . Thus. the proposed converters are suitable for high current applications but not suitable for high voltage purposes. the converter of Fig. hence vr stays constant at −VO and ir is diverted to the diode since C is much larger than Cr . the diode D becomes forward biased at ZVS.

(13). except a short interval from t2 to t3 . and defining S as (18). By substituting (9) in (17). DCM operation with α > A/(1 + A). the proposed converters operate at DCM in which operating modes depend on A and α. maximum attainable voltage gain Am is obtained as (20). sin(ωr (t − t2 )) cos(ωr (t − t2 )) . By substituting TS = t4 − t1 in (18) and applying (10). where Q1 is turned on prior to zerocrossing instant of ir . In other words. except (22). A is obtained as (19) VS i1 dt = TS TS 2 VO dt R 4) Mode IV (t4 − t5 ): Similar to Mode III for the case of α < A/(1 + A) ir (t) = ir (t4 ) + VO (t − t4 ). 4. VO (t − t1 ). Deep-CCM Operation This condition. α (25) (26) features are common characteristics in the all-remaining states as discussed in the following paragraphs. Equation (22) is now replaced by (28) ir (t) = ir (t1 ) + D. By eliminating deadtime. D is turned off at ZCS. The diode D also conducts and thus ir increases linearly until at t2 reaches i1 . L2 (27) (17) r fS π fr (18) √ S2 2 + 4S . during t5 to t6 . L2 ω √ r (t − t1 ) 1−α ω √ r (t − t1 ) 1−α (21) (22) (23) 2) Mode II (t2 − t3 ): At t2 . Q1 is turned on at ZCS and Cr is charged through a resonance with L1 . This equation is required for the converter design √ √ 2 Am αAm π 1 + Am 1 1 − cos−1 r= . (24) 3) Mode III (t3 − t4 ): Similar to Mode II for the case of α < A/(1 + A) vr (t) = vr (t3 ) cos vr (t3 ) sin ir (t) = − √ αZr ω √r (t − t3 ) α ω √r (t − t3 ) . 3. simultaneously Cr is charged and load is supplied by both VS and current of L2 . 1) Mode I (t1 − t2 ): At t1 . other equations and all modes are exactly the same as the DCM condition with α > A/(1 + A) illustrated previously. L2 (28) S = 2RCr fS = 2 S= A S+ ⇒A= 1+A In the absence of deadtime (Mode IV). ir goes positive within on time duration of Q1 and thus i1 intersects ir at t2 . charge is transmitted to the load and therefore lower output voltage ripple and current stresses are achieved. Duration of . As shown in Fig. (19) 5) Mode V (t5 − t6 ): The same as Mode IV for the case of α < A/(1 + A). At deep-CCM. where ir is always nonpositive and Q2 is turned on after zero-crossing instant of ir . CCM Operation When switching pattern includes deadtime. and the resonance current which is now equal to i1 continues via Q1 until at t3 it reaches zero and thereby Q1 is turned off at ZCS   VS − vr (t2 ) ir (t) ir (t2 )  Zr = vr (t) − VS Zr ir (t2 ) vr (t2 ) − VS × Fig.JABBARI AND FARZANEHFARD: NEW RESONANT STEP-DOWN/UP CONVERTERS 251 this mode is obtained form ir (t2 ) = i1 (t2 ) vr (t) = (1 − A) − cos VS VS sin i1 (t) = √ 1 − αZr ir (t) = VO (t − t1 ) . is illustrated in Fig. 5. At steady state. DCM Operation with α > A/(1 + A) Operation of the converter at DCM with α > A/(1 + A) is shown in Fig. 1+ √ + 1 + Am 2 Am 2 2 + Am α (20) B. deep-CCM. the converter voltage gain A can be calculated by satisfying energy conservation principle in one switching −1 cycle as (17) where fS = TS is the switching frequency. and (16). C. the converter operates at its maximum power handling capability where the switching frequency is also at maximum. At this condition. CCM operation is achieved independent of A and α. 3.

and Q2 is turned on at ZCS. Thus. ir (t4 ) = − √ αZr 4) Mode IV (t4 − t5 ): Similar to Mode III for the case of α < A/(1 + A) ir (t) = ir (t4 ) + VO (t − t4 ) L2 (40) (41) √ √ 2 α 1−A . − 4Am ax + 4 (45) Fig. maximum attainable voltage gain Am at deepCCM is given by (42). and Cr is charged. Q1 is turned on at ZCS. Since Am ax is determined. (43) is obtained. NO. t5 − t4 = ωr A Similar to (20). 5. constrain of deep-CCM is achieved as (44) √ √ √ π 1−α 1−A 2 α > · (43) ωr A ωr π 2 A2 . CCM operation. i1 reaches zero and then Q1 is turned off at ZCS vr (t) = (1 − A) − cos VS i1 (t) = √ VS sin 1 − αZr √ ωr (t − t1 ) 1−α (29) (30) ω √ r (t − t1 ) 1−α ir (t) = ir (t1 ) + √ t2 − t1 = VO (t − t1 ) L2 π 1−α . (42) m 2 Am 2 2 − Am State of deep-CCM can be achieved if (t7 − t4 ) > (t6 − t5 ). or increasing the source voltage. By decreasing the load. 1) Mode I (t1 − t2 ): At t1 . At t2 . the converter voltage gain at deep-CCM is A = Am as (42) where Am is always less than unity.252 IEEE TRANSACTIONS ON POWER ELECTRONICS. the right side of (44) is ascending. VO 3) Mode III (t3 − t4 ): Similar to Mode II for the case of α < A/(1 + A) vr (t) = (2 − A) cos VS ω √r (t − t3 ) α (36) (37) (38) (39) Fig. ωr 2VS − VO ir (t) = − √ sin √ (t − t3 ) αZr α √ α A t4 − t 3 = π − cos−1 ωr 2−A √ 2VS 1 − A. D is turned off at ZCS. . Since the converter output power is not increased by reducing the interval t4 to t5 . JANUARY 2010 2) Mode II (t2 − t3 ): At t3 . VS ir (t) = ir (t2 ) + t3 − t2 = − VO (t − t2 ) L2 (33) (34) (35) L2 ir (t2 ) . deep-CCM can be only one point of operation. By using (32) and (41). ωr Although deep-CCM can be only one point of operation. By simplifying this inequality. 4. (44) π 2 A2 − 4A + 4 For A < 1. vr (t) = (2 − A) = cte. As a result. Operation at deep-CCM. ir reaches zero. minimum of α is obtained as (45). it provides a good insight to design of the converter. 25. √ √ π 1 − Am Am 1 + r = αA2 − cos−1 . VOL. The converter is designed such that it sets at deep-CCM at its maximum output power. energy is transferred to the load. 1. deep-CCM can be achieved by choosing α ≥ αm in α> αm in = (31) (32) π 2 A2 ax m π 2 A2 ax m .

Then the energy which was absorbed by Cr is delivered to the output as well. VI. operation of the proposed non-inverting converter [Fig. the control circuit is simple and voltage regulation is easily attained by controlling TC . the converter voltage gain is increased. 6. r = 0. 9. This value is obtained for the worst case (Pout = 25 W and VS = 372 V). At deep-CCM. After an interval equal to TC (control time). beginning of switching pattern can be set at turn-on instant of Q2 . there is no limitation for Am and. maximum switching frequency is 78 kHz. In DCM with α > A/(1 + A). respectively. this switch is turned off. Am ax is determined and thus r is obtained by equating Am = Am ax . both converters have almost similar topologies and provide a non-inverting voltage gain. the converter can operate as a step-down/up regulator similar to that of DCM but with lower stresses and output voltage ripple. In CCM. Voltage regulation. When the zero-crossing instant of Q1 current is detected. By substituting these values in (5). and efficiency versus output power are illustrated in Figs. and in CCM (right). Employed switches are Q1 = APT27GA90K. the condition α > A/(1 + A) is always held.725 is obtained. is turned off when its current crosses zero. 7 and 8. Using Tr = 25 µs leads to Cr = 33. Therefore. 310 V ± 20% source voltage to 156Vdc ± 1% output voltage. DESIGN GUIDELINES Maximum achievable voltage gain Am versus r/π with loglog scale is plotted in Fig. 1(a)] is completely different from the operation of the conventional SEPIC converter. Always. 6.m ax . therefore.2 × 250). first Cr is charged completely and then its stored energy is pumped to the output. 11 to 13. In this design. The resonance voltage vr and diode current are presented in Fig. As a result.5 nF. Consider that at startup (A = 0). and L2 = 355 µH. less current stress. In both figures.683 is attained. Cr gets less charge with respect to the previous state and thus its voltage does not reach 2VS + VO .02 × 156 V.75 is chosen. The small spiky current created at Q2 turn on instant is due the reverse–recovery problem of the diode. However. Step 1) By substituting Am ax = 156/248 in (45). Zr = 119 Ω is achieved. In DCM. the received energy from VS charges Cr and simultaneously feeds the output. DESIGN PROCEDURE As an example. simulation shows that the value of the output capacitor should be C = 15. 10. In a certain design. then. 6 for α = 0.JABBARI AND FARZANEHFARD: NEW RESONANT STEP-DOWN/UP CONVERTERS 253 Fig. Maximum achievable voltage gain (A m ) versus r/π. Consequently. With 20% overdesign. Q1 is turned on. With these values. by decreasing TC . Am in CCM places between deep-CCM and DCM as shown in Fig. αm in = 0. the minimum of load resistance is R = 1562 /(1. Further decrease of load leads to DCM operation. EVALUATION According to the presented analysis. soft-switching performance of Q1 and Q2 are presented in Figs. Q2 is first turned on. zero-crossing instant of its current can be detected easily. the converter goes to CCM.6 µF. switching frequency. Step 4) In order to achieve peak-to-peak output voltage ripple equal to 0. In DCM with α < A/(1 + A). IV. . Thus. EXPERIMENTAL RESULTS Experimental results of the designed converter are presented in this section. which occurs at deep-CCM. Comparison of the designed converter with an ideal SEPIC converter is presented in Table I. voltage stress. and output voltage ripple is shown in Fig. Step 2) By applying Am = Am ax in (42). Then Zr 2 is obtained from Zr = Rm in /r where Rm in = VO /Pout. Step 3) On time durations of the switches is proportional to Tr . III. the converters can only operate as a step-down converter. consider a 250 W voltage regulator. L1 = 118 µH. then α = 0. the converter can operate as a step-down/up converter. Since the emitter of Q2 is grounded. V. Q2 = APT28GA60K and D = MUR860. the scenario of α > A/(1 + A) is performed. in DCM (left). For VS = 310 V and Pout = 200 W.75. and output voltage ripple is obtained for this state. To control the converter. waveforms of collector–emitter voltage and collector current of the switches are shown respectively from top.

13. and diode current: 2. it is assumed that its switching frequency is constant and equal to 78 kHz. 1. at the same operating conditions. 10. V C E : 200 V/div (top). 8. Voltage stress of Q1 in the proposed converter is always less . Fig. Output voltage ripple: 0. Maximum switching frequency of the proposed converter is 78 kHz that occurs at deep-CCM. the current stress of the semiconductor devices is lower.5 A/div (bottom) – (5 µs/div). IC : 2. JANUARY 2010 Fig.254 IEEE TRANSACTIONS ON POWER ELECTRONICS. Fig. Fig. 9. TABLE I COMPARISON OF THE SEPIC AND PROPOSED CONVERTER Fig. Efficiency versus output power (W). 25.5 A/div (bottom). Voltage regulation versus output power (W). Resonance voltage: 200 V/div (top). NO. 7. Switching frequency versus output power (W). Fig. VOL. The values of L1 and L2 are set the same as those of the proposed converter. Moreover. 12. the required Cr coupling (coupling capacitor) in an ideal SEPIC converter is 20 times larger than Cr (resonant capacitor) in the proposed converter. In the SEPIC converter.5 A/div (bottom). but Cr is designed such that voltage ripple of Cr to be less than 5%. IC : 2. 11. V C E : 200 V/div (top). Soft-switching operation of Q 1 (5 µs/div). Fig. Soft-switching operation of Q 2 (5 µs/div). As mentioned in Table I.5 V/div. 10 µs/div.

Undeland. R.. Treviso. [3]. Jr. However. “A modified SEPIC converter with soft-switching feature for power factor correction. the switching frequency is limited to 20 kHz.” in Proc.-H. 2001. In the recent method [26]. rectifiers exist at the secondary side. In all six quasi-resonant classes with two additional elements. In [28] two extra capacitors are used to create a resonant SEPIC converter. Jan. Spiazzi. pp. Lee. 451–456. S. 6. vol. and F. a laboratory prototype at the same conditions is implemented. New York: Wiley. Since ZCS turn-off is always attained. pp. 601– 606. efficiency of this converter is compared with the efficiency of the proposed converter in this paper.” in Proc. [2] K. CONCLUSION Two new resonant step-down/up converters were presented where all active elements operate under soft-switching condition independent of load and operating voltages. X. pp. Pomilio and G. [5] A. Power Electron. these assessments can be viewed as a comparison between the proposed converter and the best possible soft-switching SEPIC converter. Power Electron.” IEEE Trans. Their employed auxiliary circuit elements presented in Table II show that the proposed topologies in this paper have minimum number of additional element. pp. Trivedi and K. IECON 1994. 1. Devices. 3rd ed. The advantage of ZCS quasi-resonant converters [2]. In [27]. and F. Hefner.. “Internal dynamics of IGBT under zero-voltage and zero-current switching conditions.-E. pp. 2002. Lin and F. In this method. vol. Power Electronics: Converters. voltage and current stresses are high and operation at light-load is problematic [2]. no. 6. Bonato. Even though the advantages of current sharing are achieved. [6] C. no.. “An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT).” IEEE Trans. [11] R.. vol. and M.” IEEE Trans. pp. an additional transformer is employed to reduce voltage ripple (not to provide isolation) where the auxiliary network contains one switch. . and C.. Canesin. 1. According to the design considerations and tradeoffs presented in [29]. 1. Bonato. Canesin. Wu. Oct. “Novel zero-current-switching zero-voltageswitching converters.” in Proc. siliconcontrolled rectifier (SCR) can be employed for high-power/lowcost applications. VII. Sobrinho. Farias. Y. In Fig. Electron. Power Electron. Maksimovic and S. pp. 5. E.. Ind. in these converters. Yang.” IEEE Trans.. [13] F. “Novel zero-current-transition PWM converters. 9. 438–442. C. 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The operation of this converter is very simple and enjoys high efficiency among its rivals. 459–468. and C.. [12] L.” IEEE Trans. 13. 46.-L. “Novel high-powerfactor ZCS-PWM preregulators. a transformer ought to be used and the voltage stress of the auxiliary diode is very high. 1999. Mohan. but also the passive components size is small. REFERENCES [1] N. Jun. T. Moreover. Ind. M. Jan. 256–261. C.” in Proc. “A ZVS-ZCS-PWM self resonant DC-DC SEPIC converter. J. “A general approach to synthesis and analysis u of quasi-resonant converters. Wakabayashi. Certainly.” IEEE Trans. 1. Nov. [4] M. C. P. 717–722. R. 2008. unconstrained soft-switching condition is provided for all active elements. [6]–[29]. in a more realistic design for the hard-switching SEPIC converter with IGBT. one diode. In the most recent ZCT cell presented in [29] two switches operate out of phase and share the output current while providing soft-switching condition for each other. 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