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Microchip Technology Inc.

DS
Digital Signal Controller Digital Signal Controller
Introduction to the dsPIC33F Introduction to the dsPIC33F Architecture (Part 1 of 2) Architecture (Part 1 of 2)

© 2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

1

Welcome to Microchip’s dsPIC33F web seminar: Introduction to the dsPIC33F Architecture, Part 1. In this series of web seminars, we will discuss the features of the dsPIC33F family of devices, primarily from the standpoint of differences in the dsPIC33F family devices versus the dsPIC30F family devices. These seminars assume that the reader is familiar with the dsPIC30F product family features.

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What is dsPIC33F?
Second Generation Digital Signal Controller

Integration

dsPIC33F

dsPIC30F

Performance Performance
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 2

dsPIC33F is Microchip’s second generation digital signal controller. Very similar to its closest relative, the dsPIC30F family, the products offer DSP performance and MCU ease of use in devices integrating many fully featured peripherals. dsPIC33F is everything dsPIC30 is, plus more.

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What is dsPIC33 ? 2nd Generation DSC
Larger Flash: 64, 128 and 256K Larger RAM: 8K, 16K and 30KB DMA (Direct Memory Access) Controller Upward compatible with dsPIC30F Upward compatible with PIC24
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 3

More what? How about a lot more on board flash and data RAM. dsPIC33 devices integrate up to 256K bytes of program flash and up to 30K of on board data RAM. Another significant improvement is the addition of a direct memory access controller to the devices. To maximize your investment in Microchip products, all dsPIC33 devices are upwardly compatible with the dsPIC30F family of digital signal controllers as well as the PIC24F and PIC24H families of 16-bit microcontrollers.

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dsPIC33F Target Operating Parameters
Target Op Speed: Target Vdd: Target Temp: 40 MIPS * 3.0 to 3.6V -40º C to 85º C -40º 85º

* Op Speed over entire Vdd and Temp Range
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 4

dsPIC33 devices run applications at 40 MIPS. That’s 10 MIPS faster than the dsPIC30 family. The devices run at a lower Vdd range of three to three point six volts. dsPIC33 devices will operate at industrial temperatures from minus 40 degrees celcius to 85 degrees celcius.

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Feature Differences
So, what’s new then?

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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So, what’s new on dsPIC33 devices?

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Not the CORE!

dsPIC33F and dsPIC30F Instruction Sets are

identical
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 6

Not the core. In fact, the instruction sets are identical between dsPIC30 and dsPIC33. Software written for dsPIC30 will port with no translations onto the dsPIC33 devices. The MPLAB tools, including the integrated development environment and C-compiler are also identical.

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More Interrupts
Reset - GOTO Instruction Reset - GOTO Address 0x000000 0x000002 0x000004

Interrupt Vector Table

Double size of Interrupt Vector Table
User code starts at 0x000200

Reserved Oscillator Fail Trap Address Error Trap Stack Error Trap Arithmetic Error Trap

DMAC Fault Trap
Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 2 • • Interrupt Vector 117 Reserved Reserved 0x0000FE 0x000100 0x000102 0x000104

118 Total Interrupts
Alternate Interrupt Vector Table

Reserved Oscillator Fail Trap • • • • Interrupt Vector 117

0x0001FE

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The dsPIC33F family supports more interrupts. In fact, the size of the interrupt vector table is doubled, providing a total of 118 available interrupts. Like dsPIC30, all interrupts may be individually enabled and assigned to one of seven priority levels. Also like dsPIC30, interrupts can be directed to vector through an Alternate interrupt vector table. Because the interrupt vector tables are now twice as large, users should note that the first instruction of user code starts at program address hex 200 on dspic33 devices rather than hex 100 as on dsPIC30 devices.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

•New status bits for easier detection and recovery of math errors

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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On dsPIC33 devices, it is much easier to detect and recover from a mathematical error trap. There are six additional status bits within the INTCON1 register to provide details of a math error. These six new bits are highlighted in green in the slide.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The OVA and OVB bits indicate an overflow condition in either accumulator a or b, respectively. These bits differ subtly from the OA and OB bits within the SR status register. When an accumulator overflows, accumulator A for example, the OA and OVA bits will be set at the same time. However, the OA bit will be cleared if a subsequent accumulator instruction does not result in an overflow. The OVA bit will only be cleared when the user clears the MATHERR trap status flag.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The COVA and COVB bits indicate an catastrophic overflow condition in either accumulator a or b, respectively. Catastrophic overflow occurs when the accumulator bit 39 overflows.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The SFTERR bit indicates an error while executing a shift instruction. The DIVERR indicates an attempt to divide by 0.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

•User must (still) clear MATHERR to avoid re-vectoring re• New status bits auto-cleared when MATHERR cleared auto-

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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All of these 6 new bits as well as the OA,OB and SA,SB bits in the SR status register will cause a math error trap, which sets the MATHERR status bit. When the user clears the MATHERR bit, the 6 new bits will be auto cleared.

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dsPIC33F DMA Controller
Block Diagram
DMA Controller
0 1 2 3 4 5 6 7

SRAM

DPSRAM
Port1 Port2

DMA Control

DMA Channels

DMA-ready DMAPeripheral 1
CPU DMA

CPU X-bus X-

DMA Bus

CPU Peripheral Bus

CPU

DMA

CPU

DMA

CPU

Peripheral (non-DMA) (non-

DMA-ready DMAPeripheral 2

DMA-ready DMAPeripheral 3

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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dsPIC33 includes Direct Memory Access (DMA) controller for efficient data movement. The devices include eight DMA channels. Each of the eight channels can move data to/from eight different peripheral source or destinations. A simple arbitration scheme prioritizes each channel should more than one channel attempt transactions at the same time. The channel with the lower number wins.

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dsPIC33F DMA Controller
Block Diagram
DMA Controller
0 1 2 3 4 5 6 7

SRAM

DPSRAM
Port1 Port2

DMA Control

DMA Channels

DMA-ready DMAPeripheral 1
CPU DMA

CPU X-bus X-

DMA Bus

CPU Peripheral Bus

CPU

DMA

CPU

DMA

CPU

Peripheral (non-DMA) (non-

DMA-ready DMAPeripheral 2

DMA-ready DMAPeripheral 3

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Note that the DMA system has its own bus for DMA transactions. This “backside” bus means that DMA transactions can occur simultaneously with CPU transactions. It is not necessary to disrupt the CPU operation or wait for a “dead cycle” in the CPU operation.

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dsPIC33F DMA Controller
Block Diagram
DMA Controller
0 1 2 3 4 5 6 7

SRAM

DPSRAM
Port1 Port2

DMA Control

DMA Channels

DMA-ready DMAPeripheral 1
CPU DMA

CPU X-bus X-

DMA Bus

CPU Peripheral Bus

CPU

DMA

CPU

DMA

CPU

Peripheral (non-DMA) (non-

DMA-ready DMAPeripheral 2

DMA-ready DMAPeripheral 3

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Note also the dual port DMA SRAM. This allows both the DMA and CPU to access a portion of the total data RAM, simultaneously. dsPIC33 devices typically contain a 2K byte dual port RAM buffer area. Each DMA channel can select one of a number of peripheral interrupts to initiate a data transfer. Once a peripheral to memory transaction starts, the DMA controller can read from a peripheral on the DMA bus and then write that data to the DMA port of the daul port DMA SRAM. For a memory to peripheral transaction, the DMA controller will read from the dual port DMA SRAM and then write that data to the peripheral. A DMA channel can move words or bytes. I can mode blocks of up to 1024 data elements. When the channel completes moving a block, it can generate an interrupt to signal the software that the block is ready for processing.

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dsPIC33F DMA Controller
DMA-Ready Peripherals DMA-Ready

Input Capture 1
CPU DMA

Input Capture 2
CPU DMA

Timer 2
CPU DMA

Timer 3
CPU DMA

SPI 1
CPU DMA

SPI 2
CPU DMA

DCI
CPU DMA

CPU

DMA

CPU

DMA

CPU

DMA

CPU

DMA

CPU

DMA

CPU

DMA

CPU

DMA

CPU

DMA

Output Compare 1

Output Compare 2

UART 1

UART 2

ECAN 1

ECAN 2

A/D 1

A/D 2

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Most peripheral modules are capable of interfacing to the DMA channel. The Timer 2 and Time 3 modules can initiate a DMA transaction based on a time tick. Data can be streamed from either Input capture module 1 or 2 to capture a pulse stream. Data can be streamed to either output compare module 1 or 2. This can be used, for example, to automatically stream data to a PWM, generating a tone with no CPU overhead. All of the communication peripherals are DMA enabled, allowing large message buffers to be transmitted or received with no CPU overhead. Most of the communication peripherals have a small internal buffer to allow use of the peripheral without DMA, should the data rate be manageable by the CPU. The AD modules, as a source for much of the data passing through the system, has a very flexible interface to the DMA channel, allowing data to be sorted in time or sorted by analog input.

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dsPIC33F Traps
INTCON1 Status Register
INTCON1 (PIC30F)
NSTDIS

-

-

-

-

OVATE

OVBTE

COVTE

15
MATHERR ADDRERR STKERR OSCFAIL

8

0

7

INTCON1 (PIC33F)
NSTDIS OVA OVB COVA COVB OVATE OVBTE COVTE

15
SFTERR DIVERR DMAFLT MATHERR ADDRERR STKERR OSCFAIL

8

0

7

• New DMAC Fault trap status bit • User must (still) clear DMAFLT to avoid re-vectoring re•DMAC write collision flags auto-cleared when DMAFLT cleared auto© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 17

For the new DMA module, there is a new DMAFLT bit that indicates a data collision during a DMA transfer. The DMA module has write collision flags to determine why a collision occurred. Those bits are auto-cleared when the DMAFLT bit is cleared. For more information on the dsPIC33 DMA operation, see the dsPIC33 DMA webinar for more information.

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dsPIC33F Flash Memory
MORE FLASH – Up to 256K Bytes Program write/erase at nominal 3.3v Vdd

Three modes of programming are supported:
Standard Factory programming ICSP: In Circuit Serial Programming RTSP: Run Time Self Programming

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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dsPIC33 devices have much larger program flash memories, up to 256K bytes. The dsPIC33 flash programs and erases at the devices nominal 3.3 volts. Like the dsPIC30 family devices, the dsPIC33 devices can be programmed at the factory, or programmed with in circuit serial programming using MPLAB-PM3 programming tools and the device can program itself at boot time with run time self programming.

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dsPIC33F Flash Memory
But some differences exist between dsPIC30F and dsPIC33F Flash implementations:
Faster programming and erase operations Endurance now rated at ~1,000 write/erase cycles Different array organization Different Programming Operation Command codes

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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There are differences between the dsPIC33 flash and dsPIC30 flash. For one thing, the dsPIC33 flash programs and erases faster than the dsPIC30 flash. The endurance of the dsPIC30 flash is greater than the endurance of the dsPIC33 flash. The dsPIC33 flash is rated for 1000 program / erase cycles. When porting programming code from a dsPIC30 system to a dsPIC33 system, the array organization is slightly different and some of the programming command codes are different.

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dsPIC33F Flash Memory
Key Differences
Feature Endurance Instructions per: Program cycle Erase cycle Av. tprog per instruction Av. terase per instruction dsPIC30F 100,000 4 32 0.5ms 65us dsPIC33F 1,000 64 or 1* 512 25us 40us

* Subject to certain restrictions.
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 20

Looking at the differences in more detail, you see that the endurance is greater on dsPIC30 devices. Where the dsPIC30 device programs 4 instructions per programming cycle, the dsPIC33 can program either 64 instructions per cycle or 1 instruction per cycle. This ability to program 1 instruction word per cycle is very useful when storing parameter or constant data within the program space. The dsPIC30 device erases 32 instruction per erase cycle. The dsPIC33 erases 512 instructions per erase cycle. When programming the dsPIC33 is much faster. On average, the dsPIC30 programs an instruction every 0.5 milli seconds. The dsPIC33 programs an instruction every 25 micro seconds, nearly 20 times faster. The dsPIC33 erases an instruction every 40 micro seconds, somewhat faster than the dsPIC30’s 65 micro seconds.

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dsPIC33F Flash Memory Factory Programming
For “Production Programming” “Production Programming” Device in a Programmer or Tester Chip (bulk) erase ~ 200ms Programming time:
<1 sec for 64KB device <2 sec for 128KB device <4 sec for 256KB device
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 21

The faster programming of the dsPIC33 flash allows quick programming in a factory environment. When the device is on a bulk programmer or factory board tester, the devices are fully erased in 200 milli seconds. A large 256K byte flash device can be programmed in less than 4 seconds.

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dsPIC33F Flash Memory ICSP Programming
In Circuit Serial Programming:
Programming is done using:
2 data/clock pins + Reset pin

Useful to Combine Programming and Final Test at system level Ideal for field update of code through a small header Programming time is similar to factory programming

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Like most Microchip products, the dSPIC33 support in circuit serial programming, called ICSP. The interface to the device is done with 2 pins for clock and data and a reset pin. ICSP is ideal for programming and configuring the system at final test time. It also enables field upgrades to the system using a small connector. Programming times in ICSP is similar to those for factory programming.

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dsPIC33F Flash Memory RTSP Programming
Run Time Self Programming:
Run Time Self Programming OR Self Programming Device can program its own FLASH memory
CPU stalled during erase and program operations User code will: Page erase target Flash Row program target Flash

Ideal for “calibration” or “parameterization” in final test calibration” parameterization” “calibration” “parameterization” Ideal for “Remote code update” update” “Remote
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 23

Also, like many Microchip flash products, the dsPIC33 device can program themselves at run time. Under software control, the device will erase a page and program a row of the flash memory. This can be useful for calibrating the system or modifying parameters of the system. Self programming also enables remote code updates of the system as installed in the field. For example, the system might use the CAN bus to establish connection with a diagnostic port and receive code updates through that port. The device can then program the code update into its own flash, booting the new code into the system.

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Data EEPROM
dsPIC30F contains high endurance data EEPROM

dsPIC33F does not contain EEPROM, but:
Flash programmable during normal device operation at nominal Vdd (3.3V) - no high voltage needed Flash endurance is rated at ~1,000 cycles

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The dsPIC30 has on board high endurance data EEPROM memory. The dsPIC33 devices do not. However, the flash memory is useable as EEPROM memory. Programming the flash does not require any external high voltage or control. The flash can withstand 1000 write / erase cycles.

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dsPIC33F Data EEPROM Options

Program Flash may therefore be used as “Data “Data Flash” for applications requiring modest R/W cycles Flash”
Instruction Word size programming supported EEPROM emulation software increases effective endurance to ~ 10K cycles

For very high endurance requirements, external serial EEPROM offers a simple, cost effective solution
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 25

If the number of write erase cycles is modest, the program flash may be used for EEPROM functions. The flash can be programmed an instruction word at a time. And by using EEPROM emulation methodologies within your software, you can increase the effective endurance, up to 10K write erase cycles. Should the application require very high numbers of write erase cycles, Microchip can provide external serial EEPROM products to achieve a cost effective solution.

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dsPIC30 Power Supply

5.5V – 2.5V Source

5.5V – 2.5V Internal

30
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 26

dsPIC30 devices operate with power supplies ranging from 2.5 volts to 5.5 volts. The entire device uses the same supply, the internal core also runs from 2.5 volts to 5.5 volts.

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dsPIC33 Power Supply

3.3V +/- 10% Source REGULATOR

2.5V +/- 10% Internal

33
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 27

The dsPIC33 devices operate with an external supply of 3.3 volts plus or minus 10 percent. The internal core of the device operates at 2.5 volts plus or minus 10 percent. It is not necessary to provide an external regulator for the internal supply however.

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dsPIC33 Power Supply

3.3V +/- 10% Source
REGULATOR

2.5V +/- 10% Internal

33
© 2005 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC33F Architecture (Part 1) 28

Because the regulator is integrated within the device. So you only need to provide the 3.3 volts source.

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dsPIC30 I/O Levels
VDD=5.0V

30
Vi(max)=Vdd(max)+0.3=5.8V Vih(nom)=Vdd=5.0V Vih=0.8*Vdd=4.0V Vil=0.2 * Vdd = 1.0V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Let’s look at the I/O levels of the devices. On five volt dsPIC30 devices, the digital inputs can accept input voltages from zero to just over five volts.

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dsPIC30 I/O Levels
VDD=5.0V
Va(max)=5.0V

30
Vi(max)=Vdd(max)+0.3=5.8V Vih(nom)=Vdd=5.0V Vih=0.8*Vdd=4.0V Vil=0.2 * Vdd = 1.0V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The analog inputs can also span zero to five volts.

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dsPIC30 I/O Levels
VDD=5.0V
Va(max)=5.0V

30
Vi(max)=Vdd(max)+0.3=5.8V Vih(nom)=Vdd=5.0V Vih=0.8*Vdd=4.0V Vil=0.2 * Vdd = 1.0V Voh(nom)=Vdd=5.0V Voh=Vdd-0.7=4.3V Vol=0.6V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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And the outputs can also span zero to five volts.

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dsPIC33 I/O Levels
VDD=3.3V

33
Vi(max)=5.8V for digital pads Vi(max)=3.6V for analog pads Vih(nom)=Vdd=3.3V Vih=0.65*Vdd=2.2V Vil=0.2 * Vdd = 0.66V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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On a dsPIC33 device, with 3.3 volt power supply, the digital inputs nominally operate from zero to 3.3 volts.

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dsPIC33 I/O Levels
5V Tolerant Digital I/O

VDD=3.3V

33
Vi(max)=5.8V for digital pads Vi(max)=3.6V for analog pads Vih(nom)=Vdd=3.3V Vih=0.65*Vdd=2.2V Vil=0.2 * Vdd = 0.66V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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However, input pins that only have digital functions can sustain a 5 volt input. The levels at which the input pin detect a input high or input low stay the same and are set at values that work for 3.3 volt inputs. Input pins that have analog functions are not 5 volt tolerant, and cannot exceed the Vdd max specification of 3.6 volts.

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dsPIC33 I/O Levels
VDD=3.3V
Va(max)=3.3V

33
Vi(max)=5.8V for digital pads Vi(max)=3.6V for analog pads Vih(nom)=Vdd=3.3V Vih=0.65*Vdd=2.2V Vil=0.2 * Vdd = 0.66V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Analog inputs can span zero to 3.3 volts.

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dsPIC33 I/O Levels
VDD=3.3V
Va(max)=3.3V

33
Vi(max)=5.8V for digital pads Vi(max)=3.6V for analog pads Vih(nom)=Vdd=3.3V Vih=0.65*Vdd=2.2V Vil=0.2 * Vdd = 0.66V Voh(nom)=Vdd=3.3V Voh=2.4V Vol=0.4V

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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The digital outputs can span zero to 3.3 volts.

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Key Support Documents
Device Selection Reference dsPIC33F Family Data Sheet dsPIC33F Product Overview Base Design Reference dsPIC30F/33F Programmer's Reference Manual dsPIC33F Flash MCU Programming Specification Document # DS70165 DS70155 Document # DS70157 DS70152

Microchip Web Site: www.microchip.com

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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To continue your investigation into the dsPIC33 family devices, here are references to some important documents that contain a wealth of information about the dsPIC33F family of devices. For device-specific information such as pinout diagrams, packaging and electrical characteristics, the family data sheet and product overview listed here is the best source of information. The Programmer’s Reference Manual contains a thorough description of the instruction set. All these documents can be obtained from the Microchip web site shown, by clicking on the “dsPIC® Digital Signal Controllers” or “Technical Documentation” link.

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Thank you!

© 2005 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC33F Architecture (Part 1)

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Thank you for taking the time to investigate the dsPIC33 family of products. Be sure to continue your look at dsPIC33 devices by opening the second part of the introduction to dspic33f architecture. Please check the Microchip web site at www.microchip.com for other webinars on this product family as well as other Microchip products.

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