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IEEE Based 2009 - 2010 VLSI Projects VLSI (Very Large Scale Integration) VLSI - SIMULINK MODEL BASED

DESIGNS 1.FPGA Implementation of Edge Detection Algorithm using Model based Design on Si mulink. 2.Image Enhancement Algorithms on System on Chip 3.FPGA Implementation of Video Enhancement Algorithm using Model based Design on Simulink. 4.Design a Model based 2D Sharpening Finite Impulse Response (FIR) Filter for vi deoProcessing on FPGA. 5.Salt and Pepper Noise Removal Using 2D Median Filter for Video processing on F PGA. 6.Model based Image Frame Resizing Using Scaler design on FPGA. 7.Run-Time Reconfigurable Scaler Design 8.Model based design of Edge Detection Co-processor with Avalon Interface Implem entation in FPGA 9.FPGA Implementation of FIFO Controller using Model based Design 10.FPGA Implementation of Three Stage CIC Decimation Filter using Model based Des ign 11.FPGA Implementation of Three Stage CIC Interpolation Filter using Model based Design 12.Fixed-Coefficient 32 TAP Low Pass Filter using Model based Design 13.Adaptive Edge Detection for Real-Time Video Processing using FPGAs and Model based Design 14.Adaptive Edge Detection for Real-Time Image Processing using FPGAs 15.Model based Design for Reasembler using VLSI for Software Defined Radio 16.Model based Design for Convolution Interleaver, Deinterleaver using VLSI for Forward Error Correction. 17.Model based Polyphase Modulation with Aliasing for Data Up-Conversion on FPGA . SYNTHESIS 1.A Low Cost Advanced Encryption Standard (AES) Co-Processor Implementation 2.A Pipelined Implementation of 802.11a transmission on reconfigurable platforms for Wireless LAN. 3.High Speed FPGA Architectures for the Data Encryption Standard. 4.Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs 5.Estimating Power Consumption for FIR filter Implementation on FPGA. 6.Digital Signal Processor using FPGA. 7.Quantitative Analysis of Floating Point Arithmetic on FPGA based custom comp uting machines. 8.A Noise Reduction Algorithm Suitable for Hardware Implementation. 9.Digital Sampling Oscilloscope Implemented on an FPGA Chip. 10.A High-Level Implementation of a High Performance Pipeline FFT on FPGA 11.Implementation of Frequency Estimator using VHDL. 12.An FPGA Implementation of the LMS Adaptive Filter for Audio Processing. 13.An Area-Efficient Universal Cryptography Processor for Smart Cards. 14.Architecture for Dynamic Data Scaling in 2/4/8K pipeline FFT cores. 15.Parallel Synthesizable Implementation of 2D DCT in VHDL. 16.Implementation of CHIRP- Z Discrete Fourier Transform on FPGA. 17.A Detection algorithm for Zero-Quantized DCT Coefficients in JPEG. 18.A Low-cost and High Efficiency Architecture of AES Crypto-engine 19.Low Power FPGA-Based Implementation Of Decimating Filters For Multistandard R eceiver 20.Low Power Pipelined Radix-2 FFT Processor for Speech Recognition. . 21.Implementing and Optimizing a Direct Digital Frequency Synthesizer (DDFS) on FPGA 22.FPGA Implementation of Low Power Parallel Multiplier.

43.FPGA Realization of Lifting Based Forward Discrete Wavelet Transform for JPEG 2000. 3. 27. 24.Design of an FFT/IFFT Processor for MIMO OFDM Systems. 3. . CRYPTOGRAPHY 1. Lifting.A Design of New Infrared Data Broadcasting Protocol for Wireless Communication .RF Protocol Interface and Reconfigurable Logic Implementation for Low Power Wi reless Application. . 26. 3.A Low Cost Advanced Encryption Standard (AES) Co-Processor Implementation 2.High-Performance Designs for Linear Algebra Operations on Reconfigurable Hard ware.Performance Evaluation of VHDL Coding Techniques for Optimized Implementation of IEEE 802. 39.Hardware implementation of an Echo-Canceller for DVB-T On-Channel Repeaters.Design and Implementation of CDMA based Communication System in FPGA.Testing-Based Watermarking Techniques for Intellectual-Property Identificatio n in SOC Design 34. 28. 38.11a. 32.An Area Efficient High Performance DCT Distributed Architecture for Video Com pression.Based DWT with Folded an d Pipelined Schemes 37.VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application 40. 35.A Novel. 31.Implementation of Two fish cryptographic algorithm.On the design of an FPGA-Based OFDM modulator for IEEE 802. 4.Novel Hardware Implementation of Adaptive Median Filters.A Selective Trigger Scan Architecture for VLSI Testing. FPGA IMPLEMENTATION WIRELESS COMMUNICATION 1. 33.Design and Implementation of a High-Speed Matrix Multiplier Based on Word-Wid th Decomposition.High-Performance Designs for Linear Algebra Operations on Reconfigurable Hard ware 42. 25. 2.FPGA-based UDP/IP stacks parallelism for embedded Ethernet connectivity.3 Transmitters.Design and Verification of Inter IC (I2C) bus controller.Digital Design of DS-CDMA Transmitter and Receiver Using VHDL and FPGA 5. 4. 2. Efficient Architecture for the 2D.Implementation of Phase Shift Keying (QPSK.A BIST TPG for Low Power Dissipation and High Fault Coverage.Implémentations of Quadrature amplitude modulation technique..An Area-Efficient Universal Cryptography Processor for Smart Cards.Power analysis of spurious power suppression technique (SPST). NETWORKING 1.Application-Dependent Testing of FPGAs.High Speed FPGA Architectures for the Data Encryption Standard. COMMUNICATION 1.23.Implementation of Tiny Encryption Algorithm (TEA).JPEG Encoder for Low-Cost FPGAs. 30.A New Scan Architecture for Both Low Power Testing and Test Volume Compressio n under SOC Test Environment. BPSK).Area efficient FIR filters for high speed FPGA implementation. 36.A Noise Reduction Algorithm Suitable for Hardware Implementation. 29. 41.

Implementation of Frequency Shift Keying (BFSK. 5. 9. IMAGE PROCESSING 1.A New Scan Architecture for Both Low Power Testing and Test Volume Compression under SOC Test Environment.High speed Flash Audio Player for Multimedia Application.Implementation of high-performance infinite Impulse response filters on FPGA. 3.A Digit-Serial Multiplier for Finite Field GF (2m).Implementation of high-performance Finite Impulse response filters on FPGAs.FILTERS 1.Design a High Speed First-in First-out (FIFO) in FPGA 5.Design Variable Block Size Motion Estimation (VBSME). Area Efficient and Target Device Independent SRAM Controller.Design a Low Power Booth Multiplier in FPGA. 6. VIDEO PROCESSING 1.Speed. . 6.Design an Efficient Audio Processing Unit using WM8731Audio codec.DSP .A Noise Reduction Algorithm Suitable for Hardware Implementation.An FIR Notch Filter for Adaptive Filtering of a Sinusoidal signal (Synthesis).Bandwidth.Design a VGA Controller on FPGA. 4. 4.A BIST TPG for Low Power Dissipation and High Fault Coverage. 7. 4. 3. 3. COMPRESSION 1. 2. 2. 3. Area and Power Aspects of the Viterbi Decoder under Different ACS Struc ture CONTROLLER 1.Real-Time Audio Mixer. TESTING 1. 2. 2. 5. 2. 8.Speed and Direction control of Stepper Motor Using FPGA. 6.JPEG Encoder for Low-Cost FPGAs.Design and Implementation of PIC Microcontroller in FPGA 2.FPGA Implementation of Karaoke Machine. 8.FPGA Implementation of SDRAM memory Controller 4.UART Module for Real Time Application.Digital Frequency Synthesis implemented on a FPGA chip.FPGAs Enable Real-Time Data Recording for Audio Processing Applications. MFSK).A Selective Trigger Scan Architecture for VLSI Testing. Design and Implementation of a Lossless Parallel High-Speed Data Compression System. 3.An FPGA Implementation of the LMS Adaptive Filter for Audio Processing.Improving Area Efficiency of FIR Filters Implemented Using Distributed Arithme tic.4.An Efficient FPGA Implementation of a Pulse-Shaping IIR Filter.Design and Implementation of CORDIC core Algorithm in FPGA 2. AUDIO PROCESSING 1. 3.FPGAs for Prototyping and VGA Video Display Generation in Computer Architectur e Design.Design of High Speed Decimation and Interpolation Filter.An Efficient FPGA Implementation of a Pulse-Shaping IIR Filter.Low power FPGA Implementation of I2C interface with Audio Codec 7.Real-Time Video System Design Based on the Reprogrammable High Speed Devices. 5. ALGORITHM AND ARCHITECTURE 1.A Music Synthesizer on FPGA.High Speed Digital Data Amplification and Equalizer for Audio Signal on FPGA.

Designing a System-on-a-Chip for High Speed Application. .Shift inverter coding SOC 1.6.