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FINAL REPORT

Seminar Topic:

Multicore Processors

GUIDE NAME : Prof. Jitendra B. Bhatia NAME : Kaneriya Jigar M. (09bit039)

One process can launch many threads. This whitepaper discusses both multicore processor technologies and its limitation. has reached its technological limits. Single threaded applications will run on these newer processors just as if they were running on a single processor. Motorola had their 68000 and Intel the 8086 and 8088. the 4-bit 4004. The first dual core processor for home use was INTEL’s Pentium 840 released in 2005. CPU over clocking. this technology is only an advantage if applications are designed to work in such an environment. Abstract: Processor (or CPU) manufacturers. Shortly afterwards they developed the 8008 and 8080. The first commercial dual core processor was IBM’s Power 4 processor for it’s RISC servers in 2001. they execute threads. The operating system is responsible for allocating resources. 1. Over clocking has two primary undesirable side effects – more heat. 2. face an everincreasing demand for processing power. The heat can cause a server to fail. The companies then fabricated 16-bit microprocessors. and the generation of more electronic noise within the CPU. to those threads. and Motorola followed suit with their 6800 which was equivalent to Intel’s 8080. hence the advent of hyper-treading single processors and dual-core processors. 3. One can conclude that the more CPUs you have. Processors do not execute processes. the more threads can be handled at once. in the early 1970s which was basically just a number-crunching machine. like CPU and RAM. However. A Brief History of Microprocessors Intel manufactured the first microprocessor. the traditional method of increasing CPU performance. . both 8-bit. Less then two weeks AMD brought Sthlon 64x2 processor. the former would be the basis for Intel’s 80386 32-bit and later their popular Pentium line-up which were in the first consumer-based PCs. and the electronic noise can cause corruption within the data stream. such as Intel and AMD.

Intel Core Duo). AMD Phenom II X4.g. see i3. AMD Phenom II X2.g. one logical circuit . the Intel 2010 core line that includes three levels of quad-core processors. a quad-core processor contains four cores (e. Multiple processes can reside on same . Intel Core i7 Extreme Edition 980X) Why we need MULTI CORE processor?  Difficult to make single-core clock frequencies even higher  Deeply pipelined circuits: – – – – – heat problems speed of light problems difficult design and verification large design teams necessary server farms need expensive air-conditioning  Many new applications are multithreaded General trend in computer architecture (shift towards more parallelism) Difference between Unicore and multicore processor UNICORE Unicore – one core processor Having one arithmetic circuit. i5.What is Multi Core ? A multi core microprocessor is one which combines two or more independent processor into single package often a single integrated circuit. AMD Phenom II X6. and a hexa-core processor contains six cores (e. logical and shift circuit in single processor. Examples of Multi Core A dual-core processor has two cores (e. one shift logic circuit. MULTICORE Multicore – more than one core in single processor Having multiple arithmetic.g. One process can reside at a point of time. and i7 at Intel Core).

g. Thread safety Programming is much easy To get advantage programming must be in such way that creates multi threads at time. Heat problem is n time then single core. Heat problem is there but not serious. The cache coherence problem. Scheduling for multi core is much complex for high performance. . Real multi-tasking can take place. Single core can work on very high frequency. Easy to utilize at full efficient way.architecture. Multiple threads of same process can be executed at same time. Scheduling algorithms are simple. up to 30%) Fully utilization is much difficult. Enables better threading (e. Number of process depends on number of core. Each core can’t have higher frequency then single core. Processes can have more than one thread but they can’t execute at same time. Inter core communication. Virtual multi-tasking can be done using time sharing algo.

Difficulties at software level • • Special Algorithm and modification in operating system to manage multiple processors and cache at a time with high through-put. Emergent Game Technologies' Gamebryo engine includes their Floodgate technology which simplifies multicore development across game platforms. Apple Inc. Mac OS X Snow Leopard has a built-in multi-core facility called Grand Central Dispatch for Intel CPUs. Ex.'s second latest OS. Multi core processor need special support of software for improving performance with multiple threads of same process. In addition. Crysis. Hardware level Difficulties .

Frequency As we try to increase clock frequency to get high performance Leakage current value will increases by exponentially which make problem in case of architecture reliability.• • The number of transistors in a core determines basic power consumption Architectural efficiency matters a lot when designing new cores • • • More functional units means more transistors Deeper pipelines mean more transistors Larger caches mean more transistors • Current linkage vs. .

the average latency of memory accesses will be closer to the cache latency than to the latency of main memory. The cache is a smaller. faster memory which stores copies of the data from the most frequently used main memory locations.• Power vs. Shared cache . As long as most memory accesses are cached memory locations. Separated cache: 2. Frequency  The cache coherence problem:  What is cache? A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. 1. • Types of cache arrangement in processor.

shared caches: Advantages of private:  They are closer to core. Private vs. so faster access  Reduces contention Advantages of shared: – – Threads on different cores can share the same cache data More cache space available if a single (or a few) high-performance thread runs on the system .

Read – write conflict 3. Cache coherence problem: cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Write – read conflict . Simple occurrences are : 1. write – write conflict 2.

Distributed shared memory systems mimic these mechanisms in an attempt to maintain consistency between blocks of memory in loosely coupled systems.png solution to cache coherence problem  Directory-based coherence: In a directory-based system. the cache controller updates its own copy of the snarfed memory location with the new data.  Protocol based solution: A coherency protocol is a protocol which maintains the consistency between all the caches in a system of distributed shared memory.org/wiki/File:Cache_Coherency_Generic. Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory. release consistency model .wikipedia. When a write operation is observed to a location that a cache has a copy of. 1. Efficiency of protocol is decided on the average retrieval time for each instruction. 2. When an entry is changed the directory either updates or invalidates the other caches with that entry. the cache controller invalidates its own copy of the snooped memory location. The directory acts as a filter through which the processor must ask permission to load an entry from the primary memory to its cache. The protocol maintains memory coherence according to a specific consistency model.http://en. Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. Protocols are designed and verified using state diagram and then applied on the cache. sequential consistency model 2. 1. When a write operation is observed to a location that a cache has a copy of. the data being shared is placed in a common directory that maintains the coherence between caches. 3.

This whitepaper discussed both multi-core architecture and problems while preparing multicore platforms and its solutions. Libo Huang. such as hyper-threading and Multi-core. [2] “Multi-core Cache Hierarchies (Synthesis Lectures on Computer Architecture)” by morgan publication. are becoming much more common as processor manufacturers try to keep pace with the demands for more processing power.org http://www. References: [1] “Memory System Design for a Multi-core Processor” paper published by:.ieee. Fangyuan Chen.com/products/processor/ Sign Of Student: Remarks and further instruction by Guide: .wikipedia. Zhengyuan Pang. [3] Web references: http://en. Mingche Lai. Kui Dai. Zhiying Wang.org http://www.intel.Jianjun Guo.Summary : New CPU technologies.

Signature of Guide: Signature of seminar faculty: Submitted on : _____________ .