Clockless Chips

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INTRODUCTION
How fast is your personal computer? When people ask this question, they are typically referring to the frequency of a minuscule clock inside the computer, a crystal oscillator that sets the basic rhythm used throughout the machine. In a computer with a speed of one gigahertz, for example, the crystal "ticks" a billion times a second. Every action of the computer takes place in tiny steps, each a billionth of a second long. A simple transfer of data may take only one step; complex calculations may take many steps. All operations, however, must begin and end according to the clock's timing signals. The use of a central clock also creates problems. As speeds have increased, distributing the timing signals has become more and more difficult. Present-day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electrical power. Wouldn't it be nice to have an alternative? Clockless approach, which uses a technique known as asynchronous logic, differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison. It overcomes all the disadvantages of a clocked circuit such as slow speed, high power consumption, high electromagnetic noise etc. For these reasons the clockless technology is considered as the technology which is going to drive majority of electronic chips in the coming years.

Clockless Chips

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A BRIEF HISTORY

Computer chips of today are synchronous: they contain a main clock which controls the timing of the entire chips. Such crystals which tick up to 2 billion times each second in the fastest of today’s desktop personal computers. This functionality of the synchronous design makes designing the chip much easier. multiply and move the ones and zeros that are the basic stuff of the information age. Conventional chips (synchronous) operate under the control of a central clock. divide. signals barely have enough time to make it across the chip before the next clock tick. the clock signals to the devices of the chip when to input or output. speedup up the clock frequency could become disastrous. With a gigahertz clock powering a chip. The clock is what which sets the basic rhythm used throughout the machine. At this point. The clock orchestrates the synchronous dance of electrons that course through the hundreds of millions of wires and transistors of a modern computer. which samples data in the registers at precisely timed intervals. dictate the timing of every circuit in every one of the chips that add. Clock speeds are now in the gigahertz range and there is not much room for speedup before physical realities start to complicate things. This is when a chip that is not constricted by clock speeds could become very valuable.Clockless Chips 3 CONCEPT OF CLOCKS The clock is a tiny crystal oscillator that resides in the heart of every microprocessor chip. however. One advantage of a clock is that. There are problems that go along with the clock. . subtract.

all actions in this circuit take place only on the leading edge of the clock cycle. A synchronous circuit looks for a particular signal of the clock. . Then only the data will be transferred to the next register. The figure gives a clear idea of how conventional chips operate under the control of a central clock. The only thing the designers have to think about is how to complete one operation during a single tick of the clock. As we see in the figure. the circuit is looking for the leading edge of the clock pulse. which samples data in the registers at precisely timed intervals. In this case.Clockless Chips 4 WORKING OF A SYNCHRONOUS CIRCUIT This is the working model of a particular synchronous circuit. It is extremely important to design the circuits in such a fashion that all the computations must settle down and be ready for the next logical operation before the next clock tick. Especially when transferring the data on to the registers the computations settle down and wait for the next leading edge of the clock to occur.

as we design more complicated chips. The natural solution to the above problems. power consumption becomes an even more crucial topic. The clock consumes more power than another other component of the chip. The most disturbing thing about this is that the clock serves no direct computational use.Clockless Chips 5 PROBLEMS OF SYNCHRONOUS CIRCUITS One problem is speed. if one part of the chip is especially slow. It is also important to note that doubling the frequency of the clock does not double the chip speed. Mobile electronics are the target for many chips. we'll be forced to come up with a solution. . but this will incur overhead and power consumption. so does the power used by the clock. New problems with power consumption are arising. When we get to the point where the clock cannot drive the entire chip. A chip can only work as fast as its slowest component. Therefore. Therefore. A clock does not perform operations on information. New problems with speeding up a clocked chip are just around the corner. it simply orchestrates the computational parts of the computer. therefore blindly trying to increase chip speed by increasing frequency without considering other options is foolish. so this is a poor solution. Clock frequencies are getting so fast that signals can barely cross the chip on one clock cycle. as you may have guessed. One possible solution is a second clock. The other major problem with a clocked design is power consumption. These chips need to be even more conservative with power consumption in order to have a reasonable battery lifetime. is to eliminate the source of these headaches: the clock. As the number of transistors on a chip increases. the other parts of the chip are forced to sit idle. This wasted computing time is obviously detrimental to the speed of the chip.

runs almost twice as long as competitors' products. By throwing out the clock. an asynchronous-chip-based pager marketed by Philips Electronics. for example. a clocked chip can run no faster than its most slothful piece of logic. The clockless chips rely up on handshaking signals. The faster the clock. which use conventional clocked chips. it can run at the average speed of all components. this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. the transistors on an asynchronous chip can swap information independently. without needing to wait for everything else. That is. chip makers will be able to escape from the problems of the synchronous circuits. The result? Instead of the entire chip running at the speed of its slowest components. By contrast. enabling a huge savings in battery-driven devices. Like a team of horses that can only run as fast as its slowest member. . the answer isn't guaranteed until every part completes its work. the more difficult it is to prevent a device from interfering with other devices. Another advantage of clockless chips is that they give off very low levels of electromagnetic noise. At both Intel and Sun. So there must be some control mechanism which should synchronize the components inside a clockless chip to ensure correct working of the chip. dispensing with the clock all but eliminates this problem. they don’t have a global clock which synchronizes its actions. handoff signals & sometimes a local clock to synchronize the actions.Clockless Chips 6 CONCEPT OF CLOCKLESS CHIPS The main concept behind a clockless design is evident from the name itself. Clockless chips draw power only when there is useful work to do.

The figure below gives an idea of working of an asynchronous circuit.Clockless Chips 7 WORKING OF ASYNCHRONOUS CIRCUIT Clockless (also called asynchronous. The next part is about various types of implementation. So there is no separate control signal going across the circuit. self timed or event driven) chips dispense with the timepiece. data moves instead under the control of local "handshake" signals (lines below) that indicate when work has been completed and is ready for the next logic operation. The wires are used to transfer the data bits and the control bits together. The control signal is encoded within the data that is being transferred. As we can see above there is the usual logical circuitry and instead of a clock signal which controls the circuit. . In this particular scheme (which is called a duel rail circuit which will be discussed later). There are different ways to implement an asynchronous circuit. This control signals act as handshaking and handoff signals which indicates when the component is ready for the next logical operation. there are two lines on the top and bottom.

If a gate has any inputs that are NULL. that are all its inputs are DATA. This convention uses a NULL state when data is in the reset phase. BOUNDED DELAY METHOD 2. the gates do not need to be clocked because they do their computation as soon as possible. DELAY INSENSITIVE METHOD 3. as opposed to DATA in the set phase. The theory behind NCL is simple. Another way of implementing an asynchronous design is to use NULL Convention Logic (NCL). does not assume any bounds on time. Once the gate gets all its inputs. handshaking is needed between components. 1. NULL CONVENTIONAL LOGIC(NCL) The simplest implementation of asynchronous design is the Bounded-Delay method. They are the following.Clockless Chips 8 TYPES OF IMPLEMENTATIONS There are mainly three kinds of implementations of an asynchronous circuit. Knowing the bounds of the delay time allows for computations to be sped up. . This design is very similar to synchronous design. The Delay-Insensitive method. in Bounded-Delay design we assume that we know the largest amount of time for each component to perform its task. then the output of the gate is DATA. which is quite the opposite of Bounded-Delay. As a result. In this way. then this gate has an output which is NULL.

This is the actual logic which does all the calculation. . This completion detection unit indicates when the circuit has completed its action and when it is ready for the next action. When the combinational logic is done with the input signal.e. In some cases the “done” signal acts as the “go” signal to the completion detection circuit of the next stage.Clockless Chips 9 THE GENERAL MODEL G o C p u t o L m o g p l e t i o i c C n DD o en e t e c I n i O r cu t u p ui tt The general model of an asynchronous design implementation is shown above. In this circuit we can see a logic circuit which does the same operation as in the synchronous circuit. This signal is an indication given by the completion detection circuit for the signal to pass to the next step. without an error. The input signal in the combinational logic part and the “go” signal in the completion detection circuit reach the unit simultaneously. a “done” signal is produced by the completion detection circuit. Attached to this logic circuit is the completion detection unit which helps the circuit to proceed in a controlled fashion i.

In bounded delay method we assume that we know the maximum time a component takes to complete its working. In the circuit we can see that. the circuit which introduces the prototype delay acts as the completion detection circuit in bounded delay method. the circuit is designed in such a way that the control will be transferred to the next circuit only when the previous component completes its work.Clockless Chips 10 BOUNDED DELAY P r o t o E G o t y a r l y p ? e D d o e n el a y I n p u t C o m b O i un t p ua t t i o n The above circuit shows the working model of a bounded delay circuit. That is. Here we are assuming the maximum time taken and this is introduced as the delay. But this kind of implementation has a disadvantage. comparing with the general model. So it is not possible to do early completion even if the circuit doesn’t take the maximum time. To do this we introduce the maximum time which a circuit takes as the prototype delay.e. a component is considered to have finished its working when the introduced delay is over. So it is forced to wait until the delay is over. I. So this is kept in mind while designing an asynchronous circuit. . Bounded delay method is quite similar to the design of synchronous circuits.

The encoding scheme is shown below  XH=0 XL=0 -.Data not ready. In one method each signal X is encoded with two wires XH & XL. I.Not used. the delay-insensitive method doesn’t assume any bounds on time.  XH=0 XL=1 -. Thus special kind of gates would be required to implement the logics. So the input will consist of a total of four wires and the output will consist of two wires. CH=XL & CL=XH. Signals of both the channels together indicate the control and data signals.  XH=1 XL=0 -. 1 H1 L0 .Logical “0”. This is done with the help of handshake and hand off signals.e.  XH=1 XL=1 -. each wire in the logical circuit will now need two wires to implement a duel-rail circuit. Therefore communication between independent components is essential. The most popular and efficient method is the “duel-rail encoding” method. The AND.Clockless Chips 11 DELAY-INSENSITIVE METHOD Contrary to the bounded delay method which assumes bounds on time. OR & NOT gates are shown below. AH AL BH CH=AH*BH CL=AL+BL 0 L AH AL BH CH=AH+BH CL=AL*BL X X H C C NOT gate can be implemented simply as the only thing we need to do is to reverse the wires. There are many ways in which a delay insensitive method can be done.Logical “1”. As we see from the coding above. In this method separate channels are open for data and control signals. These signals indicate when the job of a component is over.

Once the gate reaches the DATA state. In addition. or system integration issues. Since these gates use two values. . but less than the threshold limit. This separation between control and data representations provides a self-synchronization throughout the design. No clock is needed. as traditional Boolean logic does.Clockless Chips 12 NULL CONVENTIONAL LOGIC NULL Convention Logic (NCL) is a logic that integrates data transformation and control into a single expression. NCL uses threshold gates with hysteresis: Threshold gates provide the basic building block of NCL designs. The hysteresis in the threshold gate provides the threshold needed to keep from switching during the intermediate state when the number of inputs in the DATA state is greater than zero. hysteresis provides the storage to remain at DATA until all of the inputs have returned to NULL. it remains in this state until all of the inputs return to the NULL state. they can be constructed with traditional CMOS (or Bipolar) processes. Threshold gate inputs and outputs can be in one of two states. “NCL” enables solutions for digital designs facing the critical power. The following NCL features enable the designer to solve these problems: NCL uses a combination of multiwire data representation and control/signaling protocol: NCL circuits switch between a voltage based data representation of DATA and a control representation of NULL. A threshold gate starting with its output in a NULL state will remain in the NULL state until the specified number of inputs is placed in the DATA state. DATA or NULL. noise. thus yielding inherently clockless or delay insensitive circuits and systems.

while a clocked circuit is always running. without needing to wait for everything else. At both Intel and Sun micro systems. . The reason for this is that asynchronous chips use power only during computations. Therefore the speed of an asynchronous design is not limited by the size of the chip.Clockless Chips 13 MERITS OF ASYNCHRONOUS CIRCUITS There are mainly three advantages of clockless design. The first of these advantages is speed. this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. They are  Increase in speed. as was the case with a clocked design. Chips can run at the average speed of all its components instead of the speed of the slowest component. The Intel Pentium referred above ran three times faster than clocked equivalent with half the power.  Less electromagnetic noise. An example of how much an asynchronous design can improve speed is the asynchronous Pentium designed by Intel in 1997 that runs three times as fast as the synchronous equivalent. The third advantage of the clockless design is that it produces less electromagnetic noise which interferes with the working frequencies of other signals.  Reduced power consumption. The transistors on an asynchronous chip can swap information independently. Another crucial advantage of clockless chips is the reduction in power consumption.

Clockless Chips 14 SPEED COMPARISON The above figure of the bucket brigade can be used to describe the flow of data in a computer. in contrast. When the clock ticks. each person pushes a bucket forward to the next person down the line (top). It is quite evident from the above metaphor. why the clockless chip is faster and effective. A synchronous computer system is like a bucket brigade in which each person follows the tick tock rhythm of a clock. An asynchronous system. . The clockless chips can run on the average speed of all of its components rather than adopting the speed of the slowest member. each person grasps the bucket pushed forward by the preceding person (middle). This is because of the fact that an action is not restricted by the rules like those in a clocked design. When the clock tocks. is like an ordinary bucket brigade: each person who holds a bucket can pass it down the line as soon as the next person’s hands are free.

Clockless Chips 15 POWER & NOISE CHARECTERISTICS POWER The above graphics is obtained from the Philips official website. Clearly synchronous chips consume more power than the asynchronous equivalent. The clock together with its timing circuits not only take up a good area of the chip. It is clear from the figure that the synchronous emit more heat as it has the more number of red spots on the light emission measurements. while a clocked chip always consumes power because the chip is always running. It is . It is clear that a chip which produces the more heat would consume more power. It illustrates the power saving character of the clockless chip. but also account for 30% of the total power consumed by the chip. The chip on the left side is a synchronous chip and the one to the right is its asynchronous equivalent. The red spots on the chip indicate the positions where heat is dissipated. This is an experiment to find out the heat emitted by a chip by placing it under special kind of light. The reason for this is that asynchronous chips use power only during computations. So removing this would surely give an increase in life of the battery.

Asynchronous systems produce less radio interference than synchronous machines. emitting less at any one frequency. The amount of power saved will depend on the machine’s pattern of activity. Because a clocked system uses a fixed rhythm. One would think that it is not much of an issue when we consider the case of a computer or other devices which can be plugged. . Systems with parts that act occasionally benefit more than systems that act continuously. The above said reason is more applicable in the case of mobile electronics where a battery is used to drive the chip. In order to avoid errors caused by these noise signals.Clockless Chips 16 also important to note that the idle parts of a clockless chip consume negligible amount of power. NOISE Now a day the demand for mobile devices is getting higher and higher. that often remain idle for long periods. designers would not be free to provide the scale of integration they wish. Everything around is becoming wireless. Asynchronous systems lack a fixed rhythm. such as the floating-point arithmetic unit. These devices work by sending and receiving radio signals. televisions and aircraft navigation systems that operate at the same frequencies. so they spread their radiated energy broadly across the radio spectrum. it broadcasts a strong radio signal at its operating frequency and at the harmonics of that frequency. air-conditioning and other cooling equipments in order to prevent overheating. When a clocked circuit is used in these types of devices the noise generated by the large frequency of the clock interferes with the working frequency of the mobile devices. Such signals can interfere with cellular phones. Most computers have components. But in this case the chip can cut the cost needed in the design of these equipments by reducing the need for cooling fans.

This is because there is no way for a hacker to track regularly timed signals. The hackers do not know what to look at. although asynchronous design can be challenging. . A final advantage of the clockless chip is the ability to provide superior encryption. Moreover. This becomes even more critical as computer all over the world become more closely connected and are sharing confidential material. electronic funds exchange and personal identification.Clockless Chips 17 OTHER BENEFITES Yet another benefit of asynchronous design is that it can be used to build bridges between clocked computers running at different speeds. increasing the speed of a clocked system usually requires upgrading every part. Many computing clusters. Moving data controlled by one clock to the control of another clock requires asynchronous bridges. Improved encryption makes asynchronous circuits an obvious choice for smart cards—the chip-endowed plastic cards beginning to be used for such security sensitive applications as storage of medical records. These clusters can tackle complex problems by dividing the computational tasks among the PCs. Because the circuits of an asynchronous system need not share a common rhythm. Finally. replacing any part with a faster version will improve the speed of the entire system. In contrast. Such a system is inherently asynchronous: different parts march to different beats. which are given away by the clock in a synchronous design. because the data may be "out of sync" with the receiving clock. designers have more freedom in choosing the system's parts and determining how they interact. it can also be wonderfully flexible. This has significant potential as security becomes an increasing priority. link fast PCs with slower machines. for instance.

The reason for this is there are no regularly timed signals for hackers to look for. . A final place that asynchronous design may be used is encryption devices. but where will we first see these designs in use? The first place we'll see. low levels of electromagnetic noise creates less interference. This is an ideal place to implement a clockless chip because of the minimal power consumption. They will be also used in smart cars as they provide excellent security. Clockless designs will occur here last because of the competitive PC market. as is the case with mobile electronics. Also. the manufacturing process must be improved to create a reasonably priced chip. It is essential in that market to create an efficient design that is reasonably priced. This becomes even more critical as computer all over the world become more closely connected and are sharing confidential material. Many prototypes will be necessary to create reliable designs. less interference is critical in designs with many components packed very tightly. The third place is in personal computers (PCs). Therefore. Manufacturing techniques must also be improved so the chips can be mass-produced.Clockless Chips 18 APPLICATIONS Clockless design is inevitable in the future of chip design because of the two major advantages of speed and power consumption. The second place we'll see these chips are in mobile electronics. clockless designs in the lab. A manufacturing cost increase of a couple cents per chip can cause an entire line of computers to fail because of the large cost increase passed onto the customer.

who have licensed their 32 bit Architecture to Fulcrum Microsystems. In the past few years.Clockless Chips 19 CLOCKLESS PRODUCTS IN THE MARKET Now of course. and used half the power. In 1997. actually. including Motorola. Intel developed a prototype of a Pentium style chip that ran 3 times as fast as a clocked equivalent. Sharp Corp. who have joined forces with Theseus Logic (one of the first companies founded on the principle of asynchronous design) to produce a 32 bit processor and an 8 bit microcontroller. the question is why aren't Intel. but lack of a perceived market convinced Intel to abandon the project (Intel's approach to asynchronous design seems to be slow integration-asynchronous circuitry is notoriously easy to integrate into clocked chips-and Intel has done so-including a few clockless elements in the Pentium IV series). and Philips has consistently given a hefty budget to its asynchronous design research department for many years. AMD. and MIPS. a competitor to Theseus. The latest company to step into this field is a Manchester based company called SELF-TIMED SOLUTIONS which has developed clockless chips for communication devices. and all the other chipmakers scrambling to put together research teams to design asynchronous prototypes? Well. . built an asynchronous chip for embedded applications in 1997. others have jumped on the bandwagon. some have.

and are therefore not typically taught in universities. most circuit simulation techniques are independent of synchrony. they would have to begin by training their engineering staff in the basics. • Lack of good tools. and the synthesis formalisms are unfamiliar. despite decades of attention. • Testing difficulties. LACK OF GOOD TOOLS The predominance of CAD tools oriented towards synchronous design is another chicken-and-egg problem. or a close variant (like burst mode). researchers have yet to make concurrent software design a turnkey affair. Also.Clockless Chips 20 LIMITATIONS OF ASYNCHRONOUS CIRCUITS • Design difficulties. If a microprocessor design company today wanted to use asynchronous logic. DESIGN DIFFICULTIES The primary drawback to asynchronous design is that it is hard. Control logic must operate in fundamental mode. And of course. previous . Architectural design has all the same challenges that concurrent software has. and existing tools can be adapted for asynchronous use. there is the basic obstacle that asynchronous design techniques have been out of favor since the 1980s. However.

Whereas the latter simply have to compute a valid result before the clock edge. . gating the request and/or acknowledge signals is a possibility. Asynchronous control circuitry must be designed to handle a variety of contingencies regarding timing. Additionally. unlike clock dividing). as in concurrent software. to allow the logic functions to be observed at human speeds. the prototype delay in a bounded-delay design is such a circuit. asynchronous circuits may have minimum delays too. related to the design difficulties.Clockless Chips 21 academic design efforts have produced the first sprinkling of a dedicated tool base. is the testing of the possible interleaving scenarios. and the testing harness must be able to cause at least most of these possibilities. For example. Finally. since some of the slow-transition effects are preserved. a common technique in synchronous testing is to slow or stop the clock. TESTING DIFFICULTIES Testing asynchronous circuits presents several new challenges. and it is at least conceivable that dropping Vdd to near the threshold could provide a useful slowing effect (and possibly more useful. However. asynchronous circuits have timing requirements that are more constrained than synchronous circuits.

the hardware community must move to incorporate asynchronous logic. industry has been getting by without asynchronous design. despite a number of academic (and industry) successes. skew-free clock for every (say) piece of clothing with a processing element. at least up to now. So far. and may even regard it with suspicion. tool development is likely seen as an obstacle. all of which complicates the global timing analysis necessary for a synchronous design. both of which make clock distribution harder. while chips are getting bigger. the clocked designs have been feasible (if occasionally expensive). Finally. Chips are also becoming more heterogeneous. especially at the university level. is given to asynchronous design. It’s just not practical to expect a clean. Should it be used? My conclusion is an emphatic yes! Clocks are getting faster. and this will require very low power designs. Most of today’s designers don’t understand it well enough to use it. any asynchronous design will incur additional cost in training engineers to use techniques they didn’t learn in school. . we are entering an age when processors will be just about everywhere. But this can only happen if more focus. Asynchronous design techniques are sometimes seen as unproven. but just as the software community is moving towards more concurrency.Clockless Chips 22 CONCLUSION Why isn’t it popular? Why doesn’t industry currently use asynchronous designs (with a handful of exceptions)? The main cause is risk. Moreover. It is certainly a challenge. with functions like memory and network interfaces being considered. Further. and low power does not yet dominate demand. Finally.

www.mdatechnology.theseus.nytimes.columbia. www. www. www. www.com . www.fulcrummicro.scientificamerican. www.com 3.com 6.Clockless Chips 23 REFERENCE 1. www.net 8.iht. www.com 5.com 7.cs.transentric.com 2.mips.edu/async 9.com 4.

CA INTEL Santa Clara. ASYNCHRONOUS DIGITAL DESIGN Pasadena. CA THESEUS LOGIC Maitland. Clockless prototype in 1997 ran three times faster than the conventional chip equivalent. FL PHILIPS ELECTRONICS Eindhoven. on half the power. .” a way of letting clockless chips know when an operation is Complete. England Patented “null convention logic. clockless chips for communications devices. Motorola is a current customer. License designs to manufacturers of smart cards and mobile devices. Produce chips for cell phones and other lowpower communications devices. GOALS Gradually integrate “islands” of clockless logic into future Generations of microprocessors.Clockless Chips 24 APPENDIX-1 CLOCKLESS COMPANIES AND THEIR ACHIEVEMENTS COMPANY SUN MICROSYSTEMS Palo Alto. Netherlands SELF-TIMED SOLUTIONS Manchester. CA ACHIEVEMENTS Prototypes have demonstrated two to three times the speed of Standard chips. Founded by students of Caltech’s Alain Martin. Stay current with clockless R&D. expected to announce plans by Year-end. who developed the First asynchronous microprocessor. Founded Steve Furber Clockless chips for smart who has developed cards. Markets a clockless chip that gives its pagers up to twice the battery life of competitors. Clockless chips for mobile devices and smart cards.

Clockless Chips 25 .

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