Department of Electrical Engineering

McGill University
ECSE 221 Introduction to Computer Engineering I
Final Examination

Friday, December 16th, 2005 9:00 am

Examiner: Prof. F.P. Ferrie

Associate Examiner: Prof. D.A. Lowther

Instructions:

Answer ALL questions in the examination booklet provided, showing all of your work.
Calculators are permitted, but they must be the Faculty standard. All questions are equally
weighted.

Question 1

a) A computer must sample an analog voltage in the range [-3.5v to 12.3v] to a precision of
0.5 mV. Assuming that the analog-to-digital converter used produces an output encoded
as a 2’s complement integer, how many bits would be required? [2 points]
b) Determine the range of decimal numbers that can be represented by a 5-digit, 8’s
complement number. [2 points]
c) Encode the number 2.62 x 1017 using IEEE-754 single precision floating-point format.
Express your answer as an 8-digit hexadecimal number. [2 points]
d) Identify the function FA,B ,C ,D implemented by the multiplexer circuit shown below. [2
points]

e) Determine the minimal canonical forms, ∑∏ and ∏∑, corresponding to the following
sum of products form: " (2,3,5,7,11,13) . [2 points]
A,B ,C ,D

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Question 2

Q2aPROM

Address Data Address Data

0 2 8 1
1 0 9 3
2 4 A 1
3 0 B 5
4 6 C 1
5 0 D 7
6 0 E 1
7 0 F 1

A finite state machine is implemented using a PROM and a 3-bit register as shown above. The
timing parameters for this circuit are: TA(PROM) = 15 nS, TPD(D-FF) = 5 nS, TSU(D-FF) = 5 nS,
and TH(D-FF) = 2 nS. The flip-flops are falling edge-triggered with identical parameters.

a) Using the information provided above, determine the state transition table for this circuit
and draw the corresponding state diagram. [2 points]
b) From the state transition table, determine the next state equations for Q2, Q1 and Q0.
[2 points]
c) From the timing information provided, determine the maximum frequency of operation of
the circuit (assuming the input is held constant) and plot the timing diagram
corresponding to 3 state transitions, starting from [0,0,0] with the input set to 0. Make
sure to show each of the critical delays. [2 points]
d) Suppose that the edge-triggered D flip-flops were replaced with their master-slave
counterparts. Explain what differences you would expect to see (if any) in the timing
diagram and clearly explain why (be brief, bullet points OK). [2 points]
e) List the PROM code (use the same format as pictured in the above figure) corresponding
to a 3-bit binary up/down counter. Assume that the counter counts up if I=0, and down
otherwise. [2 points]

Question 3

a) Translate the following “C” function into MIPS assembly language, strictly adhering to
context save/restore conventions discussed in class. [4 points]

long align2(long address)

{
while (address - ((address >> 2) << 2) != 0)
address++;
return(address);
}

The single function argument is to be passed in $4 with the function return in $6.

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b) Consider the following snippet of MIPS assembly code:
.text 0x400100

li $10, 5
lp10: sll $11, $11, 2
slt $12, $11, $0
bne $12, $0, lp20
addi $10, $10, -1
bne $10, $0, lp10
jr $31

lp20: li $6, -1
jr $31

Determine the memory address corresponding to the first bne instruction and the contents
of the lower 16-bits of this address. Do the same for the second bne instruction.
[2 points]

c) Consider the following data segment in MIPS assembly code:

.data 0x10010000

str1: .asciiz "Hello"

.align 2

var1: .word -23

str2: .asciiz "there"

.align 2

arr1: .word -4, 5, 12, -1, 16

str3: .asciiz "\n"

.align 2

arr2: .word 1024, 106425, -9963, 21, 22, 16

Determine the memory location of the second element of arr2. Explain in one sentence
precisely what the .align 1 pseudo-instruction does. [2 points]

d) List the MIPS code corresponding to the following pseudo-instructions:

i) li $10, 0xf7349601
ii) lw $11, 0x1001003f

In answering this question, you may assume that the assembler uses $1 as a scratch
register. [2 points]

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 Question 4

The LogicWorks circuit for the 4-bit unsigned binary multiplier discussed in Assignment 5 is
reproduced below.

a) Assume the full-adder is fabricated with full carry generation, and that each single-bit full
adder produces outputs pi = ai + bi and gi = ai · bi . Write down the expression for the CO line
in terms of the pi’s and gi’s. If each gate has a propagation delay of 1 nS, determine Tpd for
CO relative to inputs A and B. [2 points]
b) Draw the state diagram for the controller and list the contents of the CtrCtrl PROM.
[2 points]
c) Suppose the multiplier and multiplicand were set to F and F respectively (as shown in the
figure). List the contents of the Product High and Product Low registers for each of the 9
clock pulses required to compute the product. [2 points]
d) Show how to convert the 4-bit full-adder to an ALU capable of performing addition and
subtraction (2’s complement) – a diagram will suffice. Assume that the function selected is
controlled by a single line, SUB, that is set to 1 for subtract and 0 for add. [2 points]
e) Suppose the datapath is now modified (as in the assignment) to perform signed binary
multiplication using Booth’s algorithm. The multiplier is set to -4 and the multiplicand to 4.
List the contents of the Product High and Product Low registers for each of the 9 clock
pulses as in Part (c) above. [2 points]

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Question 5

The datapath for the multi-cycle implementation of the MIPS architecture is shown below.

Assume that the datapath has the following parameters:

For all registers: Tsu = 0.05 nS, Th = 0 nS, Tpd = 1.0 nS
For all multiplexers: Tpd = 0.5 nS
For the register file: Ta = 2 nS
For the ALU Tpd = 8 nS
For the Memory Ta = 8 nS (for both read and write operations)
All other delays may be neglected.

a) Write down the sequence of microinstructions corresponding to the BEQ instruction. List
them by name along with their corresponding register transfers and datapath settings.
Make sure to use register transfer notation (do not use micro-program notation).
[2 points]
b) The following microinstruction is added to the MIPS repertoire:
Register[31] = PC
PC = PC[31:28] || IR[25:0]<<2
Answer the following questions:
i) Assuming that this microinstruction is the final of a 3 microinstruction
sequence, what MIPS instruction would this correspond to?
ii) List all the changes to the datapath necessary to support this microinstruction.
iii) Explain why it is possible that both of the above register transfers can take
place concurrently.
iv) What is the range of the MIPS J instruction?
[2 points]

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c) Given the parameters listed above, determine Tcl for this datapath. Make sure to clearly
show how you arrived at this number. Determine the datapath’s maximum frequency of
operation. [2 points]
d) As discussed in class, the control for the multi-cycle datapath can be implemented using a
finite-state machine, FSM (e.g. ROM + register as in Assignment 5). Answer the
following questions:
i) How many input lies does the FSM have and where do they come from?
ii) How many state variables are needed to support the simplified version of the
MIPS architecture (the one in the diagram above)?
iii) Determine the parameters for the FSM ROM, i.e., # address lines, # data lines,
memory access time, Ta.
iv) Does the implementation of the controller make any difference with respect to
the performance of the MIPS processor. Explain your answer in no more than
two sentences.
[2 points]
e) Answer the following general questions about the MIPS architecture:
i) A MIPS implementation is clocked with a frequency of 1.2 Ghz. Estimate the
propagation delay of the switching elements employed assuming that Tcl for
the datapath is dominated by the ALU, and that the ALU uses two levels of
carry generation (all other delays are negligible).
ii) Explain in no more than two or three sentences how the undefined instruction
exception can be used to implement unsupported instructions.
[2 points]

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Appendix - MIPS Instruction Set

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Appendix – MIPS Machine Language