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Evolution, Challenge, and Outlook of TSV (Through-Silicon Via) and 3D IC/Si Integration

John H. Lau Electronics & Optoelectronics Laboratory Industrial Technology Research Institute 886-3591-3390, johnlau@itri.org.tw ABSTRACT 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed for high performance applications. 1. INTRODUCTION The Electronics Industry has been the largest industry since 1996 and may well reach 1.5 trillion dollars (i.e., $1.5x1012) by the end of 2011 [1, 2]. The most important invention of the Electronics Industry is, arguably the transistor (1947), which earned John Bardeen, Walter Brattain, and William Shockley the 1956 Nobel Prize in Physics. The invention of the integrated circuit (IC) by Jack Kilby in 1958 (which earned him the 2000 Nobel Prize in Physics), and six months later by Robert Noyce (who didn't share the Nobel Prize with Jack Kilby because he passed away in 1990) excited the generations of IC integrations [1]. The proposal of doubling the number of transistors on an IC chip (for minimum costs and innovations) every 24 months by Gordon Moore in 1965 (also called Moores law) [3] has been the most powerful driver for the development of the microelectronics industry in the past 45 years. This law emphasizes lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC) as schematically shown in the left-hand side of Figure 1. On the other hand, the integration of all these functions can be achieved through 3D integrations such as 3D IC packaging [1], 3D IC integration [1], [2], [4] [68], [92] [125] and 3D Si integration [1], [2], [69] [91], [92] [125] as shown in Figure 2. Since 3D IC packaging is a mature technology and does not use TSVs, it is not included in this study. The 3D IC integration and 3D Si integration are shown in the right-hand side of Figure 1 and are some of the more-than-Moore. TSV is the heart of 3D Si integration and 3D IC integration [124]. Though the 1956 Nobel Laureate in Physics, William Shockley (yes, the same William Shockley who co-invented the transistor) invented TSVs more than 50 years ago [125] (Figure 3), but it was not intended for 3D Si/IC integration.
Moores Law
2D SoC
MEMORY DISPLAY OPTO B DSP
MEMS

More-than-Moore
3D IC Integration
A Thin Chip DSP B DISPLAY TSV

3D Si Integration
Thin Wafers

PROCESSOR, ASIC, MCU, etc.

Long Wiring (from A to B) in 2D SoC MEMORY OPTO

For both cases, Thermal Management is a big issue!

TSV

MEMS

Micro Bumps

Wafer-to-wafer bonding (Bumpless) Very short wiring in 3D Si integration with very tiny TSVs, thin wafers, and bumpless (no bumps!) Thermal management is a huge problem!
TSV

PROCESSOR. AASIC, MCU, etc.

Chip #1

Solder Bump

Fig. 1 Moores law vs. more-than-Moore [1, 2] For commercial products, even HPs coplanar GaAs RF MMIC (monolithic microwave integrated circuit) has been using via hole grounding technology since 1975 (Figure 4), but it was not for 3D integration. Generally, the industry consider Toshibas CMOS image sensor with TCVs (through chip vias) [37] as the first high-volume 3D integration product (2008), Figure 5. Straightly speaking, however, it is not a 3D integration product neither; at most it is a 2.5D IC integration product [1].
3D IC Packaging 3D IC Integration 3D Si Integration
Full swing production for memories.

Mass Production
Commercialization
Die Stacking with wire bonds

Testing and yield challenges give way for package stacking

Maturity

Applied R&D Basic R&D

Package on Package Stacking (PoP)

Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the phase of industrialization.

Still in upstream research, technological challenges such as yield & device architecture are key issues.

C2C, C2W, W2W Stacking W2W Stacking

Technology

Fig. 2 Maturity of 3D integration technologies [1, 2]

Keynote at IEEE Japan ICEP, April 13-15, 2011

The origin of 3D Integration (1980)


3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years ago, when people thought Moores law could be hitting the wall by the 1990s.

The invention of TSV (1958)


Shockley's invention was not meant for 3D integration

3D Si Integration (was favored in 1980)


Stacking up wafers with TSVs for electrical feed through. Bumpless!

3D IC Integration (was rejected in 1980)


Stacking up the chips with TSVs and solder bumps

A boost (1985) by Richard Feynman


Go 3D instead of all on a surface of a chip!

3D IC Integration with microbumps and thin chips (has been favored since 2000)
Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

Long way to go!


Need Ecosystem, EDA, Technology

Fig. 3 TSV invented by William Shockley, US Patent #3,044,909, filed on October 23, 1958 and granted on July 17, 1962 In this study, TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the focus. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

No sight in Volume Production in the next 10 years


The right way to go and compete with Moores law

Memorychips Stacking
Cost issues and Competing technology

Active Interposers (Memory/Logic + CPU/Logic)


Need Ecosystem, EDA, and Business models

Passive Interposers (2.5D & 3D)


Will be used the most in the next 10 years

Via through IC chip

Co-planar GaAs RF MMIC (monolithic microwave IC)

Via through IC chip

Via-hole grounding Technology

Fig. 4 HPs high volume product (MMIC) with via through IC chip (1975)
Optical Lens

Fig. 6 The evolution of 3D integration (excluding 3D IC Packaging) [1] 2. THE ORIGIN OF 3D INTEGRATION Again, since the focus of this study is TSV, thus 3D IC packaging is out of the scope and will not be discussed. 3D integration is a very old idea [1] which consists of two or more layers of active electronic components that are integrated vertically through TSV (it used to be called vertical interconnection) into a single circuit. It was trigged by the advance of the silicon-on-insulator (SOI) technology first reported by Gat and his colleagues more than 30 years ago [126], when semiconductor people thought Moores law could be hitting the wall by the 1990s. Of course, the fact showed otherwise. Figure 6 shows the evolution of 3D integration. In the early 80s, there were two schools of thought [69, 70]. One is to stack up the chips with TSV and flip-chip [127, 128] solder bumps (3D IC integration), and the other is to stack up the wafers with TSV alone, i.e., bumpless (3D Si integration), as shown in Figure 1. The advantages of 3D Si integration over 3D IC integration are: (1) better electrical performance, (2) less power, (3) lower profile, (4) less weight, and (5) higher throughput. In general, industry favored the 3D Si integration. 3. OVERVIEW, CHANLLEGES, AND OUTLOOK OF 3D Si INTEGRATION
Japan 3D Si Integration Roadmap
Number of Elements X Function/Chip
1010

Through Chip Via (TCV)

Lens Holder IR Cut Filter Wire Bonds Board Sensor Chip

Volume Production

Development for Application

Optical Lens Lens Holder

IR Cut Filter

104

106

108

3D

Through Chip Via (TCV) Sensor Chip Solder Balls

102

Glass

2D VLSI Basic Research

100

Fig. 5 Toshibas CMOS image sensor with TCV (converted from wire bond to flip chip) (2008) [37, 38]

1970

1980

1990

2000

Year

Fig. 7 Japan 3D Si integration roadmap [69] In the early 80s, the Japan MITI (Ministry of International Trade and Industry) funded and directed

Keynote at IEEE Japan ICEP, April 13-15, 2011

(a)
(a) (b)

Fig. 8 3D Si integration: (a) IBM/RPIs Cu-to-Cu bonding; [71-73] (b) NIMS/AIST/Toshiba/ University of Tokyos Cu-to-Cu bonding [74-80] the 3D Research Committee of the 3D Si integration project. Their roadmap is shown in Figure 7 [69]. It was announced that: (1) functional models have been fabricated in stacked double or triple active layers demonstrating the concept of a future 3D structure; (2) the basic technology for stacking active layers will be developed before 1990; and (3) with this technology, various kinds of circuits such as high-packing density memory, high-speed logic or image processors are expected to be designed and realized in a 3D single chip between 1990 and 2000. History showed that the technology did not materialize within the timeframe stated by the Project. Basically, wafer-to-wafer (W2W) is the only way to perform the bonding operation for 3D Si integration and yield is a big issue (e.g., some bad chips are forced to bond on the good chips). In addition, the absence of (or an infinitesimal) gap between wafers and thermal management is a huge problem. Furthermore, the requirements of the bonding conditions, such as the surface cleanness, surface flatness, and the class of clean room for 3D Si integration are very high. There are at least two different W2W bonding methods for 3D Si integration, namely, Cu-to-Cu bonding and oxide-to-oxide bonding, as shown in Figures 8 and 9, respectively. Figure 8a shows a high-quality bonding interface by IBM and RPI [71 73]. Before bonding, the Cu interconnects (pads) are fabricated with the standard BEOL (back end of line) damascene process, followed by the oxide CMP (chemical mechanical polish) processed (oxide touch-up) to recess the oxide level to 40 nm lower than the Cu surface. The bonding temperature is ramped up to 400C. Figure 8b shows a cross-section of the interface between the bumpless Cu-to-Cu electrodes (pads) given by the NIMS/AIST/Toshiba/University of Tokyo [74] [80]. Figure 9a shows a cross section of MITs oxide-to-oxide bonding structure of three-layer 3D (ring oscillator) bonded at 275C [81] [87]. It can be seen that: (1) the layers are bonded and interconnected with W-plugs, (2) the conventional inter level connections are in the bottom two layers, and (3) the

(b)

Fig. 9 3D Si integration: (a) MITs oxide-to-oxide bonding; [81-87] (b) Leti/Freescale/ STMicroelectronics oxide-to-oxide bonding [88-90] 3D vias are located in the isolation (field) region between transistors. Figure 9b shows Leti/Freescale/ STMicroelectronics dielectric-to-dielectric bonding structure of two device layers bonded at ~400C [88] [90]. It can be seen that: (a) first, a metal level is formed on a 200 mm bulk wafer and SOI wafer; next, these wafers are bonded face to face, and then the bulk silicon of the SOI wafer is removed down to the BOX layer; (b) the ~1.5m interstrata vias (ISVs) are formed, which make contact from upper strata to lower strata; (c) a metal layer is formed at the top of the back side of the SOI wafer, and (d) this ISV makes contact with both the top and bottom metal layers. Tremendous of work still need to be done before products can be manufactured using the 3D Si integration technology. Besides thermal management, vias formation, thin-wafer handling, more research and development efforts should also be placed on areas such as: cost reduction, design and process parameter optimization, bonding environment, W2W bonding alignment, wafer distortion, wafer bow (warpage), inspection and testing, contact performance, contact integrality, contact reliability, and manufacturing yield issues. In addition, packaging the 3D Si integration module systematically and reliably to the next level of interconnect pose another great challenge. Besides technology issues, the EDA (electronic design automation), which is the soul of 3D Si integration [124] is far from ready. Urgently, the industry needs an ecosystem (e.g., standard and infrastructure) for 3D Si integration. Then, the EDA can write the design, simulation, analysis & verification, manufacturing preparation, and test software with the following guidelines. 1. Design automation from high level description to layout generation/optimization. 2. Verification all dedicated and tuned to 3D integration.

Keynote at IEEE Japan ICEP, April 13-15, 2011

3. Addressing the 3rd dimension not like a packaging bumping. 4. Addressing the true 3rd dimension, with partitioning, floor planning, automatic placing and routing. 5. Full extraction with the 3rd dimension, full 3D DRC (design rule checks), 3D LVS (layout vs. schematic) with all tiers together in a same database. 6. The 3D integrations have then to be seen as a whole system distributed in several tiers, and not just a stack of predefined chips. In the next 10 years, the industry will be hard-pressed for high volume products with the 3D Si integration technology, except for very niche applications (Figure 6). However, it should be noted and emphasized that 3D Si integration is the right way to go and compete with Moores law. The industry should stride to make this happens! 4. OVERVIEW, CHALLENGES, AND OUTLOOK OF 3D IC INTEGRATION Unlike 3D Si integration, 3D IC Integration (as shown in Figure 1) stacks up whatever Moore laws IC chips in the 3rd dimension with TSVs, thin chips and microbumps [1] to achieve performance, small form factor, and eventually low cost. Today, unlike 30 years ago, most people favor 3D IC integration. Basically, there are two groups of 3D IC integrations. One is memory-chip stacking and the other is interposers (active and passive) as shown in Figures 6 and 10.

Fig. 11 Samsungs 32-memory chips stacking with microbumps (each chip is 20m thick) [50] It should be pointed out that for this kind of high-volume products, 3D Si integration would be the perfect technology for its manufacturing. Hopefully, 10 years from now, when the ecosystem (e.g., standards and infrastructures), EDA, technology, testing, and the reliability of 3D Si integration are ready, then memory-chip stacking could be produced at higher throughputs and lower costs. 4B. Active Interposers (3D IC Integration)
Active Interposer Memory

Memory Si chip on top


CPU/ Logic

Microbumps between Memory and Logic

TSV

3D IC Integration
Memory-Chip Stacking (TSVs in active chips)
8@50m thick 2Gb Chips (16Gb) MEMORY B DISPLAY

Active Interposer (TSVs in active chips)

Passive Interposer (No TSVs in active chips)

PCB Logic Si chip at the bottom

Cu filled TSV

2.5D IC Integration with Passive Interposer

(a)

560m

TSV/RDL/IPD Passive Interposer Thin Chip DSP OPTO MEMS Micro Bump

3D IC Integration with Passive Interposer


Micro Bump

TSV

TSV A Micro bump

PROCESSOR. ASIC, MCU, etc. TSV/RDL/IPD Passive Interposer TSV

(b)
Active Interposer

Fig. 10 3D IC integration: Memory-chip stacking (L), Active Interposer (M), Passive Interposer (R) 4A. Memory-Chip Stacking (3D IC Integration) [1] The left-hand photo of Figure 10 (provided by Samsung) shows the simplest example of memory-chip stacking. It can be seen that even with eight chips, their total thickness (560m) is still less than the thickness of an ordinary chip. Figure 11 shows another example, a 32-chip stacked by Samsung. It can be seen that 32 memory chips, each 20 m thick, are stacked up with microbumps and communicated with Cu-filled TSVs. Unfortunately, due to cost issue and competing technologies, e.g., Au/Cu wire bonding, memory-chip stacking is not in volume production today.

(c) Fig. 12 Active interposers: (a) Wide I/O Memory/ Logic + CPU/Logic [14]; (b) Wide I/O DRAM by Samsung [50]; (c) Wide I/O DRAM by Micron.

Keynote at IEEE Japan ICEP, April 13-15, 2011

TSVs, in addition to being used for stacking just memory chips, they can also be used as an active interposers (the mid-schematic of Figure 10) such as logics, microprocessors, wide I/O memory [14], and wide I/O DRAM (dynamic random access memory) [50]. Figure 12(a) demonstrates the ultimate goal of a high power, pin-count and fine-pitch CPU/Logic and a maximum bandwidth with low power memory stacked together to address the memory bandwidth challenge [14, 129]. In this case, the CPU (or Logic) with TSVs acts like an active TSV interposer. Figure 12(b) shows a wide I/O DRAM (8X) proposed by Samsung [50]. In this case, the Master chip is the active interposer. Figure 12(c) shows a wide I/O DRAM (20X) proposed by Micron, where the Logic is the active interposer [http://news.cnet.com/8301-13924_3-20031380-64.ht ml (February 10, 2011 1:51 PM PST)]. Due to the very high device density and the complexity of the circuits (see Figure 13 for example) [130] on the CPU and memory, however, finding places/spaces to drill holes (TSVs) either by via-middle or via-last processes are very difficult.
Many tiny vias filled with W or Cu.

discussed in Sections (4C) and (4D). Thermal management is critical to 3D IC integration (with active interposer) because 3D circuits increase the total power generated per unit surface area; chips in the 3D stack may overheat if proper and adequate cooling is not provided; the space between the 3D stack may be too small for cooling channels; and thin chips may create extreme conditions for on-chip hot spots. For example, Figure 14 shows the temperature maps on a chip for various chip thicknesses. It can be seen that the heat on the chip surface is well dissipated for typical chip thicknesses of 200m subjected to a generated power of 0.2W. For the 200-m-thick chip, the temperature distribution is almost uniform and equal to 35C. However, the hot-spot temperature on the chip increases to 69C (0.2W power) if the chip thickness is reduced to 10m and the hot-spot area is clearly shown. Thus, low-cost and effective thermal management solutions are desperately needed for widespread use of 3D IC integration SiPs [1, 2, 4, 8, 15, 16, 19, 20, 24, 31]. Again, with a passive TSV interposer, the thermal
t=10m t=25m t=50m

Custructure

Low-k material Low-k layers, closest to chip surface

9 low-k layers
t=100m t=200m Chip Size: 5mmx5mm Chip Power: 0.2W/Chip Chip Heat Source Area: 0.2mmx0.2mm
65nm Cu/low-k Chip by Chartered Semiconductor (2006) to show the tiny vias.

Besides the tiny devices such as transistors (which cannot be seen in this SEM image), there are many tiny vias on a chip. They are connected to devices (e.g., 4 vias for each transistor) to build the first metal (M1) layer. Today, the number of these tiny vias, for many chips, already exceeds the world population of over 7 billion. One of the core competences and major businesses of foundries is to make these tiny vias. They are not the same TSV for 3D IC integration.

Fig. 13 The cross section of a 65nm Cu/low-k chip with 11,000 I/Os by Chartered Semiconductor (2006) [10] Additionally, the CPU and memory chip sizes and number of pin-outs may differ. Forcing them to attach reduces design freedom and could compromise functionality. Longer routings may be needed in the TSVed CPU and memory chip, which affects performance. Most importantly, the required TSV manufacturing yield is too high (>99.99%) for the CPU to bear additional costs due to yield loss [9]. Also, the yield lost due to front/back-side metallization, wafer temporary bonding and de-bonding, and wafer thinning of the CPU wafer increases the hidden costs [9]. Thus, a passive TSV interposer connecting the memory and CPU (without any TSVs) in certain 3D configurations could be cost-effective in resolving these issues, which will be

Fig. 14 Effect of chip thickness on temperature distribution: - hot spot temperature [8] management of memory/logic + CPU/logic is easier and more effective, which will be discussed in Sections (4C) and (4D). Why not dig holes on the active chips now? Besides the technology issues mentioned in Section (4B), the EDA and testing tools for 3D IC integration are not ready. Because the ecosystem such as standards and infrastructures of 3D IC integration does not yet exist, this area cannot be worked on seriously and with full-force. It should be noted that, besides they are different, the EDA for 3D IC integration is much simpler and easier to build and qualify than for 3D Si integration. However, it should be emphasized that the EDA for 3D Si integration (once it is ready) should be more attractive, useful, and acceptable because it is built for the true 3rd dimension right from the very beginning as shown in Section (3) and not from the predefined chips like 3D IC integration. Actually, the biggest issue for system houses on 3D IC integration with the active interposer is their

Keynote at IEEE Japan ICEP, April 13-15, 2011

business model. Most of these companies buy the chips from different sources and want them to be bullet-proved before they were shipped to SATS (semiconductor assembly and test services). Forcing two chips from different sources together into one chip is not acceptable to the system houses because if something wrong, they dont know who is responsible for finding the root causes and fixing the problem so they can continue shipping their products. By using a passive interposer to integrate a few bullet-proved chips together (like a multichip module) is what the system houses want and used to. Thus, passive interposer becomes the most effective 3D IC integrator! It could be very low cost because we dont have to dig and fill the holes on the active dies. Also, we dont have to thin and metalize the active dies. Furthermore, we dont have to temporary bonding and de-bonding of a supporting wafer to the active wafers. Let the passive interposer be the workhorse of our 3D IC integration SiP before the 3D Si integration time comes!
(a) Adhesive Heat spreader Chip BT substrate with RDL Thermal interface material (TIM)

FPGA Die Slices Silicon Interposer Package

Stiffener

Ordinary solder bumps

Ordinary underfill

Solder balls

PCB

(b)

Microbumps Adhesive

Heat Spreader Chip

TIM Stiffener ring Simple organic substrate

TSV Interposer with Redistribution layer (RDL) & integrated passive devices (IPD) Ordinary solder bumps

Ordinary underfill

Special underfill

Solder balls

PCB

Fig. 15 (a) Conventional face-down PBGA; (b) Face-down PBGA with a passive TSV interposer (2.5D IC integration) [10, 11] 4C. Passive Interposers (2.5D IC Integration) TSVs can also be used in a passive interposer to support ultra-fine pitch, high pin-count, wide bandwidth, and high-density Moores law IC chips as shown in the right-hand side of Figure 10. For example, Figure 15a shows a conventional face-down plastic ball grid array (PBGA) package, in which the chip is supported by a high-density organic-substrate with build-up layers connected through microvias [131]. As the chip gets bigger and its pitch gets smaller, the organic-substrate can no longer support the chip. Hence, an intermediate substrate is needed (e.g., the passive TSV interposer) to redistribute the array of fine-pitch pads on the chip to fewer and relatively larger pitch pads on a simpler and thinner organic substrate (Figure 15b) to achieve a smaller footprint with better performance. The packaging system in

Fig. 16 Xilinxs stacked silicon interconnection technology for Wide I/O Interface FPGA (2.5D IC integration with sample) [66] Figure 15b is called 2.5D IC integration SiPs. In the past few years, many significant 2.5D IC integration papers have been published by, e.g., IBM, IMEC, Fraunhofer IZM, Leti, AIST, KAIST, ALLVIA, Technical Univ. of Berlin, Nokia, ASE, NEC-Schott, STATSChipPAC, UTAC, IPDiA, DNP, Shinko, GIT, IME, Xilinx, etc. For example, Figure 16 [66] shows Xilinxs stacked silicon interconnection technology, which provides breakthrough field-programmable gate array (FPGA) capacity, bandwidth, and power efficiency. It can be seen that the four 28nm FPGA die slices are supported by a coarse-pitch TSV interposer with 4 redistribution layers (RDLs), which provides the connections between the package substrate and the FPGA for the parallel and serial I/O, power/ground, clocking, configuration signals, etc. According to Xilinx, this stacked silicon interconnect technology provides multi-Terabit-per-second die-to-die bandwidth through more than 10,000 device-scale connections. It should be emphasized that there are no TSVs in the active FPGA device chips! The passive TSV interposer is the workhorse of the system.
Signal Line

SiO2 Si Si
SW-CNT bundle

SiO2

Si

TSV

Signal Line

TSV

Fig. 17 TSV filled with carbon nanotube (CNT) [118, 119]

Keynote at IEEE Japan ICEP, April 13-15, 2011

Most passive interposers reported are made by silicon and filled with copper. However, glass interposers have been reported by IZM [61] and GIT [54, 55] for potential niche applications. Also, other filling materials such as tungsten, polymer, solder, and carbon nanotube (CNT) have been report. Figure 17 [118, 119] schematically shows TSVs filled with CNT. 4D. Passive Interposers (3D IC Integration) Most passive interposers reported in the literatures are 2.5D IC integration SiPs, i.e., the interposer supports chips (without TSVs) only on its top surface as schematically shown in the upper right-hand side of Figure 10. The 3D IC integration with passive interposer is shown in the lower right-hand side of Figure 10, which supports chips on its top and bottom surfaces. In this study, a few low-cost and thermal enhanced 3D IC integration SiPs with a passive TSV interposer are presented for high pin-count and/or high-performance applications. There are no TSVs in any of the active IC chips. 4D.1 Design Philosophy The present design philosophy addresses the electronic packaging of 3D IC integration with a passive TSV interposer with RDLs and/or IPDs (integrated passive devices) for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration SiP format. Rather than digging holes (TSVs) on active (devices) chips, existing Moores law chips are stacked with a passive TSV interposer to: a) Provide vertical (as well as horizontal) electrical feed through interconnections. b) Perform redistributions (to fan out high pin-out and ultra fine-pitch circuitries). c) Provide decoupling (to enhance the electrical performance). d) Connect to the next level of interconnects (e.g., the package substrate with fewer pin-outs and coarse pitches). e) Construct a cost-effective thermal management system (e.g., heat spreader/sink). 4D.2 Example No. 1 The 3D IC integration SiP shown in Figure 12 can be redesigned with a TSV/RDL/IPD passive interposer as shown in Figure 18. In this case; (1) no new EDA is needed; (2) there are no TSVs in the chips; and (3) the heat from the high power chips can be removed from their back sides. ; and (4) the solder joint reliability is not an issue because it is a standard package and has been used for more than 15 years. The outlook (package) of this proposed 3D IC integration SiP is very attractive to integrated device manufactures (IDMs), original equipment manufacturers (OEMs), and electronics manufacturing services (EMS) because

it is a standard face-down PBGA package and has been used by the electronic industry for more than 15 years.
TIM Microbumps Heat Spreader + Sink (if needed) Adhesive TSV Interposer with RDL & IPD Stiffener ring Simple organic substrate Microprocessor/ ASIC

PCB

Ordinary solder bumps

Memory

Solder balls

Special underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

Fig. 18 TSV passive interposer supporting high-power chips (e.g., microprocessor and logic) on its top side and low-power chips (e.g., memory) on its bottom side. Modified from [11, 34] 4D.3 Example No. 2 If the memory chips are too thick to fit in the space between the interposer and organic substrate and back-grinding is too expensive for active chips, then the design shown in Figure 19 could be a solution. The interposer consists of a cavity in its bottom-side, which can be easily fabricated by either lasers or wet anisotropic etches, for example the KOH (potassium hydroxide) solution as report in [7].
TIM Microbumps Adhesive Heat Spreader + Sink (if needed) Stiffener ring Microprocessor/ ASIC

TSV /RDL/IPD interposer with a cavity

Simple organic substrate

PCB

Ordinary solder bumps

Solder balls

Special underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

Fig. 19 TSV interposer supporting high-power chips on its top side and low-power chips on its bottom side with a cavity. Modified from [11, 34] 4D.4 Example No. 3 The 3D IC integration SiP as shown in Figure 20) features a silicon interposer with high-density TSVs, RDLs, and IPDs that connect various Moores chips with pads that have different pitches, sizes, and locations. A simple, organic substrate (either full or with cavity) with standard (in size and pitch) solder balls for PCB assembly supports the passive interposer. All the high-power chips such as the micro-processor unit (MPU), graphic processor unit (GPU), application specific IC (ASIC), digital signal processor (DSP), micro-controller unit (MCU), radio frequency (RF),

Keynote at IEEE Japan ICEP, April 13-15, 2011

high- and low-power IC chips. It should be noted that, recently, in order to eliminate thin-wafer handling (save manufacturing cost), interposer thicknesses 300m are used provided the electrical requirements are met.

Fig. 20 Passive TSV interposer with RDL and IPD supporting high-power chips on its top-side and low-power chips at its bottom-side. The organic substrate is with a cavity [11, 34] and high-power memory chips are on top of the TSV interposer in a flip-chip format [127, 128] so that the backside of these chips can be attached to a heat spreader via a thermal interface material (TIM). Just like Examples 1, 2, and 3, most of the heat from the high-power chips can be dissipated through the heat spreader (with a heat sink if it is necessary). All low-power chips MEMS, OMEMS, CMOS image sensors, and memory chips are at the bottom-side of the interposer with either flip-chip or wire-bond formats or both. Just like Examples 1, 2, and 3, a ring-stiffener connecting the organic substrate and the heat spreader provides adequate standoff for 3D IC integration with the passive interposer and to support the heat spreader with or without the heat sink. Underfill encapsulants are needed between the TSV interposer and the high- and low-power flip chips, and between the TSV interposer and the organic substrate. However, underfill is not needed between the 3D IC integration SiP and the PCB. For wire bonding chips, encapsulants may be needed. The outlook (package) of this proposed 3D IC integration SiP has been used by the electronic industry for more than 15 years [132]. Its not only effective in thermal management [133] [139], but its solder joints are very reliable [140] [143]. Therefore, in conjunction with the proper design of the high-power and low-power chips above/below the passive TSV/RDL/IPD interposer inside the package, a cost-effective, 3D IC integration SiP that displays high electrical and thermal performance can be achieved and manufactured. The thickness of the proposed TSV/RDL/IPD passive interposer should be 200m, however, the thinner the better. Thus thin-wafer handling methods, e.g., [22, 30, 104, 105, 107, 109] are required for the passivation, metallization and/or wafer bumping processes. Fortunately, by using the passive interposer, thin-wafer handling is not necessary for the TSV-less

TSV/RDL/IPD Interposer with embedded fluidic channels to support multiple Moores law chips without any TSVs Substrate

PCB

Fig. 21 3D IC integration SiP consists of a series of TSV/RDL/IPD interposers with embedded fluidic channels to support multiple Moores law chips without any TSVs 4D.5 Example No. 4 The 3D IC integration SiP shown in Figure 20 cannot be stacked into 3D because of the heat sink. Also, there may not be the luxury to separate all the high-power chips (on top) from the low-power chips (at the bottom) of the interposer. Figures 21 and 22 show a new 3D IC integration SiP design which is able to be stacked up in 3D and the chips can be randomly arranged on top or bottom of the interposer.
TSV/RDL/IPD interposer with embedded fluidic channels to support Moores law chips with no TSVs
IPD RDL Moores law chips

TSVs Micro-channels Microbumps Solder bumps

Fig. 22 TSV/RDL/IPD interposer with embedded fluidic channels supporting all kinds of chips on its top and bottom sides The basic unit is shown in Figure 21, which consists of the TSV/RDL/IPD interposer with embedded fluidic channels. This interposer is fabricated by bonding two silicon wafers together by wafer-to-wafer (W2W) bonding, and an optimized liquid cooling channel structure is embedded in between the chips, as shown in Figure 23. Silicon is chosen as interposer material because it is a suitable material for the integration of both electrical and fluidic structures in the same substrate with microfabrication process. The difference between these

Keynote at IEEE Japan ICEP, April 13-15, 2011

Fluidic inlet Fluidic outlet

Volume Production

TSV

3D IC integration (with TSV/RDL/IPD interposer), Multichip 2.5D IC integration (with TSV/RDL/IPD interposer), Multichip Chip on TSV/RDL/IPD interposer (2.5D) Memory/Logic + CPU/Logic with TSV

TSV

Fluidic channel

MEMS on ASIC with TSV CIS with TSV and DSP

CIS with TSV (2.5D)

Fluidic inlet

2008

2010

2012

2014

2016

2018

2020

Fluidic outlet

Fluidic Channel Top-side Bottom-side

Fig. 23 Interposer (carrier) with TSVs for electrical feed through and fluidic microchannels for thermal management [1, 2]

Fig. 24 Fabricated TSV and embedded fluidic microchannel carrier (interposer). The TSV, sealing ring for TSVs, sealing ring for micochannels. Au20Sn solder bumps and Ti/Cu/Ni/Au UBMs [1,2] two chips is that the bottom Si chip does not have any outlets. TSVs can be designed along the periphery of the carrier (interposer). After W2W bonding, electrical interconnection through the carrier is made by the TSV with on-wall metallization (in this case, the copper filling may not be necessary). The fluidic channels are connected out through the inlet and outlet. There are sealing rings (the solder is Au20Sn and the UBM is TiCuNiAu) around both the fluidic path and the individual TSV to isolate the fluid from the electrical interconnection as shown in Figure 24 [15, 16, 24]. 5. SUMMARY AND RECOMMENDATIONS A few generic, low-cost and thermal-enhanced 3D IC integration SiPs with various passive interposers have been presented for high performance applications. Also, the origin of 3D integration and the overview, challenges, and outlook of 3D Si/IC integrations have been presented and discussed. Some important results

Fig. 25 3D IC/Si integration roadmap (excluding memory chips stacking) modified from [11] and recommendation are summarized here. (1) A roadmap for the passive and active interposers is shown in Figure 25. In the next 10 years, most TSVs will be fabricated on passive interposers. For active interposers, we have to wait for the ecosystem and EDA, except for niche applications such as CMOS image sensor (CIS) [37], 3D MEMS [2, 6] and 3D LED [1, 7]. Even for these products, some (e.g., CIS) are going to be replaced by the passive interposer, e.g., [39, 40]. (2) Because of System Houses business model, it would be hard-pressed for them to use the active interposers, e.g., memory/logic + CPU/logic. An architect + broker system helps! (3) Passive interposer is the most cost-effective 3D IC integrator. It is not only for substrates, carriers, but also thermal management tools. Let the passive interposer be the workhorse of 3D IC integration SiPs! (4) With the passive interposer, it is not necessary to dig holes on the active chips. In fact, try to avoid making TSVs in the active chips. (5) The passive interposer provides flexible coupling for whatever Moores law chips are available and/or necessary, and enhances the functionality and possibly the routings. (6) With the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss. (7) For many products, their passive interposers can be 300m and still meet the electrical requirements. In these cases, thin wafer handling is not needed. (8) With the passive interposer, just about all the thermal problems of 3D IC integration can be managed. A few examples have been proposed in Section 4D. (9) With the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99%) for the active chips to bear additional costs due to TSV manufacturing yield loss. (10) With the passive interposer, large SoC dies can be replaced by a few smaller pieces of dies (like

Keynote at IEEE Japan ICEP, April 13-15, 2011

Memory stacking

Memory/Logic + CPU/Logic

Multi-LEDs on driver chip with TSV

Xilinxs FPGA) with much higher manufacturing yield and save cost! (11) With passive interposers, leaning from Xilinx: (a) the state-of-the-art technology (28nm) is only focused/applied on the device chips with billions of tiny vias, which Foundries can do best; (b) all the TSVs and RDLs are fabricated on a piece of dummy silicon with the most mature technology (65nm), which can be done by the backend (or a packaging assembly and test house) with much less expensive materials, processes, equipments and personals; and (c) these lead to substantial cost saving. (12) 3D Si integration is the right way to go and compete with Moores law. However, it is still a long way to go. Some technology R&D topics have been proposed in Section 3. Also, some guidelines on building the EDA have been recommended. The industry should immediately build an ecosystem incorporating standards and infrastructures so that EDA vendors can create and qualify the software for design, simulation, analysis & verification, manufacturing preparation, and test for 3D Si integration and stride to make it happens! Hopefully, (a) 10 years from now (Figure 25), at least the memory chips stacking could be manufactured at lower costs and higher throughputs by using the 3D Si integration technology, i.e., there are no bumps between the memory chips, and (b) 15 years from now, the wide I/O heterogeneous structures such as wide I/O DRAM, wide I/O interface, and wide I/O memory could be manufactured at high volume with the 3D Si integration technology. These will be performed by Foundries. The backend or packaging assembly and test houses receive the stacked wafers (without any bumps) and will go through the routine tasks such as dicing, packaging, and testing. In that case 100X is possible!. 6. ACKNOWLEDGEMENTS The author would like to thank Dr. Ian Yi-Jen Chan of Electronics & Optoelectronics Labs of ITRI for his strong supports and helps. REFERENCES
1. Lau, J. H., Reliability of RoHS Compliant 2D & 3D IC Interconnects, McGraw-Hill, NY, 2011. 2. Lau, J. H., C. K. Lee, C. S. Premachandran, A. Yu, Advanced MEMS Packaging, McGraw-Hill, NY, 2010. 3. Gordon Moore, Cramming More Components Onto Integrated Circuits, Electronics, Vol. 38, No. 8, April 19, 1965. 4. Lau, J. H., Critical Issues of 3D IC Integrations, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 35-43.

5. Tummula, R., and M. Swaminathan, System-On-Package: Miniaturization of the Entire System, McGraw-Hill, NY, 2008. 6. Lau, J. H., Design and Process of 3D MEMS Packaging, IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 10-15. 7. Lau, J. H., Lee, R., Yuen, M., and Chan, P., 3D LED and IC Wafer Level Packaging, Journal of Microelectronics International, Vol. 27, Issue 2, 2010, pp. 98-105. 8. Lau, J. H., and Tang, G., Thermal Management of 3D IC Integration with TSV (Through Silicon Via), IEEE Proceedings of ECTC, San Diego, May 2009, pp. 635-640. 9. Lau, J. H., TSV Manufacturing Yield and Hidden Costs for 3D IC Integration, IEEE Proceedings of ECTC, Las Vegas, NV, June 2010, pp. 1031-1041. 10. Lau, J. H., State-of-the-art and Trends in 3D Integration, Chip Scale Review, March/April, 2010, pp. 22-28. 11. Lau, J. H., Y. S. Chan, and R. S. W. Lee, 3D IC Integration with TSV Interposers for High-Performance Applications, Chip Scale Review, September/October, 2010, pp. 26-29. 12. Yu, A., J. H. Lau, Ho, S., Kumar, A., Wai, Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D., Kwong, D., Study of 15-m-pitch solder microbumps for 3D IC integration. IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 6 10. 13. Yu, A., J. H. Lau, Ho, S., Kumar, A., Yin, H., Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps. IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 350354. Also, accepted for publication in IEEE Transactions in Advanced Packaging. 14. Yu, A., A. Kumar, S. Ho, H. Yin, J. H. Lau, Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., Development of Fine Pitch Solder Microbumps for 3D Chip Stacking, IEEE EPTC Proceedings, Singapore, December 2008, pp. 387-392. Also, accepted for publication in IEEE Transactions in Advanced Packaging. 15. Yu, A., N. Khan, G. Archit, D. Pinjalal, K. Toh, V. Kripesh, S. Yoon, and J. H. Lau, Development of silicon carriers with embedded thermal solutions for high power 3-D package. IEEE Transactions on Components and Packaging Technology, Vol. 32, No. 3, September 2009, pp. 566-571. 16. Tang, G., O. Navas, D. Pinjala, J. H. Lau, A. Yu, and V. Kripesh, Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules, IEEE Transactions on Components and Packaging Technologies, Vol. 33, Issue 1, 2010, pp. 184-195. 17. Chen, K., C. Premachandran, K. Choi, C. Ong, X. Ling, A. Khairyanto, B. Ratmin, P. Myo, and J. H. Lau, C2W Bonding Method for MEMS Applications, IEEE Proceedings of ECTC, December 2008, pp. 1283-1287. 18. Premachandran, C. S., J. H. Lau, X. Ling, A. Khairyanto, K. Chen, and Myo Ei Pa Pa,, A Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform,

Keynote at IEEE Japan ICEP, April 13-15, 2011

19.

20.

21.

22.

23.

24.

25.

26.

27.

Chip-Size Wafers for MEMS and 3D SIP Applications, IEEE Proceedings of ECTC, Orlando, FL, May 27-30, 2008, pp. 314-318. Zhang, X., T. Chai, J. H. Lau, C. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, G. Tang, Y. Ong, S. Vempati, E. Wai, H. Li, B. Liao, N. Ranganathan, V. Kripesh, J. Sun, J. Doricko, and C. Vath, Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA Package, IEEE Proceedings of ECTC, May, 2009, pp. 305-312. Also, IEEE Transactions in Advanced Packaging (in press.) Hoe, G., G. Tang, P. Damaruganath, C. Chong, J. H. Lau, X. Zhang, and K. Vaidyanathan, Effect of TSV Interposer on the Thermal Performance of FCBGA Package, IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore, December 2009, pp. 778-786. Choi, W. O., C. S. Premachandran, S. Ong, Ling, X., E. Liao, K. Ahmad, B. Ratmin, K. Chen, P. Thaw, and J. H. Lau, Development of Novel Intermetallic Joints using Thin Film Indium Based Solder by Low Temperature Bonding Technology for 3D IC Stacking, IEEE Proceedings of ECTC, CA, May, 2009, pp. 333-338. Kumar, A., X. Zhang, Q. Zhang, M. Jong, G. Huang, V. Kripesh, C. Lee, J. H. Lau, D. Kwong, V. Sundaram, R. Tummula, and M. Georg (2008), Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor, IEEE Proceedings of EPTC, December, pp. 1270-1276, and IEEE Transactions in Components and Packaging Technologies, (in press.) Vempati1, S. R., S. Nandar, C. Khong, Y. Lim, K. Vaidyanathan, J. H. Lau, B. P. Liew, K. Y. Au, S. Tanary, A. Fenne, R. Erich, and J. Milla, Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects, IEEE Proceedings of ECTC San Diego, CA, May, 2009, pp. 980-987. Also, accepted for publication in IEEE Transactions in CPMT. Khan, N., L. Yu, P. Tan, S. Ho, N. Su, H. Wai, K. Vaidyanathan, D. Pinjala, J. H. Lau, T. Chuan, 3D Packaging with Through Silicon Via (TSV) for Electrical and Fluidic Interconnections, IEEE Proceedings of ECTC, San Diego, CA, May, 2009, pp. 1153-1158. Sekhar, V. N., S. Lu, A. Kumar, T. C. Chai, V. Lee, S. Wang, X. Zhang, C. S. Premchandran, V. Kripesh, and J. H. Lau, Effect of Wafer Back Grinding on the Mechanical Behavior of Multilayered Low-k for 3D-Stack Packaging Applications, IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1517-1524. Accepted for IEEE Transactions on Components and Packaging Technologies. Khan, N., V. Rao, S. Lim, S. Ho, V. Lee, X. Zhang, R. Yang, E. Liao, Ranganathan, T. Chai, V. Kripesh, and J. H. Lau, Development of 3D Silicon Module with TSV for System in Packaging, IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 550-555. Ho, S., S. Yoon, Q. Zhou, K. Pasad, V. Kripesh and J. H. Lau, High RF Performance TSV for Silicon Carrier for High Frequency Application, IEEE Proceedings of

28.

29.

30.

31.

32.

33. 34.

35.

36.

37.

38.

Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1956-1952. Lim, S., V. Rao, H. Yin, W. Ching, V. Kripesh, C. Lee, J. H. Lau, J. Milla and A. Fenner, Process Development and Reliability of Microbumps, IEEE Proceedings of Electronic Packaging Technology Conference, December 2008, pp. 367372. Also, accepted for the IEEE Transactions in Components and Packaging Technology. Selvanayagam, C., J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, Nonlinear Thermal Stress/Strain Analysis of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps, IEEE Transactions in Advanced Packaging, Vol. 32, No. 4, Nov. 2009, pp. 720-728. Zhang, X., A. Kumar, Q. X. Zhang, Y. Y. Ong, S. W. Ho, C. H. Khong, V. Kripesh, J. H. Lau, D.-L. Kwong, V. Sundaram, Rao R. Tummula, Georg Meyer-Berg, Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization, Journal of Sensors & Actuators: A. Physical, Vol. 156, Nov. 2009, pp. 2-7. Lau, J. H., Yue, T. G., Hoe, G. Y. Y., Zhang, X. W., Chong, C. T., Damaruganath, P., and Vaidyanathan, K. Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3-D IC Packaging. ASME Paper no. IPACK200989380. Lau, J. H., Lim, Y., Lim, T., Tang, G., Khong, C., Zhang, X., Ramana, P., Zhang, J., Tani, C., Chandrappan, J., Chai, J., Li, J., Tangdiongga, G., and Kwong, D. Design and analysis of 3-D stacked optoelectronics on optical printed circuit boards. In Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 1924, 2008, Vol. 6899, pp. 07.107.20 and accepted for IEEE Transactions in Advanced Packaging. Lau, J. H., State-of-the-art and Trends in Through-Silicon Via (TSV) and 3D Integrations, ASME Paper no. IMECE2010-37783. Lau, J. H., M. S. Zhang, and S. W. R. Lee, Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates, ASME Paper no. IMECE2010-40974. Carson, F., K. Ishibashi, S. Yoon, P. Marimuthu, and D. Shariff, Development of Super Thin TSV PoP, Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 7-10. Kohara, S., K. Sakuma, Y. Takahashi, T. Aoki, K. Sueoka, K. Matsumoto, P. Andry, C. Tsang, E. Sprogis, J. Knickerbocker, and Y. Orii, Thermal Stress Analysis of 3D Die Stacks with Low-Volume Interconnections, Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 165-168. Sekiguchi, M., Numata, H., Sato, N., Shirakawa, T., Matsuo, M., Yoshikawa, H., Yanagida, M., Nakayoshi, H., and Takahashi, K., Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor, IEEE Proceedings of ECTC, San Diego, CA, May 2006, pp. 1367-1374. Takahashi, K., and M. Sekiguchi, Through Silicon Via and 3-D Wafer/Chip Stacking Technology, IEEE

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39.

40.

41. 42.

43.

44.

45.

46.

47.

48. 49.

50.

51.

52.

Proceedings of Symposium on VLSI Circuits Digest of Technical Papers, 2006, pp. 89-92. Juergen, M., Wolf, K. Zoschke, A. Klumpp, R. Wieland, M. Klein, L. Nebrich, A. Heinig, I. Limansyah, W. Weber, O. Ehrmann, and H. Reichl, 3D Integration of Image Sensor SiP using TSV Silicon Interposer, IEEE Proceedings of EPTC, December 2009, pp. 795-800. Limansyah, I., M. J. Wolf, A. Klumpp, K.Zoschke, R. Wieland, M. Klein, H. Oppermann, L. Nebrich, A. Heinig, A. Pechlaner, H. Reichl, and W. Weber, 3D Image Sensor SiP with TSV Silicon Interposer, IEEE Proceedings of ECTC, May 2009, pp. 1430-1436. Garrou, P., C. Bower, and P. Ramm, 3D Integration: Technology and Applications, Wiley, John & Sons, 2009. Ramm, P., M. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel, and H. Reichl, Through Silicon Via Technology Processes and Reliability for Wafer-Level 3D System Integration, IEEE ECTC Proceedings, Orlando, FL, May 2008, pp. 847-852. Andry, P. S., Tsang, C. K., Webb, B. C., Sprogis E. J., Wright S. L., Bang, B., Manzer, D. G., Fabrication and characterization of robust through-silicon vias for silicon-carrier applications, IBM Journal of Research and Development,, Vol. 52, No. 6, 2008, pp. 571-581. Knickerbocker, J. U., P.S. Andry, B. Dang, R.R. Horton, C S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, and S.L. Wright 3-D silicon integration, IEEE Proceedings of ECTC, May 2008, pp. 538-543. Kumagai, K., Yoneda, Y, Izumino, H., Shimojo, H., Sunohara, M., Kurihara, T., A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection, IEEE Proceedings of ECTC, Orlando, FL, May 2008, pp. 571-576. Sunohara, M., Tokunaga, T., Kurihara, T., Higashi, M., Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring, IEEE Proceedings of ECTC, Orlando, FL, May 2008, pp. 847-852. Lee, H. S., Choi, Y-S., Song, E., Choi, K., Cho, T., Kang, S., Power delivery network design for 3D SIP integrated over silicon interposer platform, IEEE Proceedings of ECTC, Reno, NV, May 2007, pp. 1193-1198. Matsuo, M., Hayasaka, N., Okumura, K., Silicon interposer technology for high-density package, IEEE Proceedings of ECTC, May 2000, pp. 1455-1459. Eric Wong, Jacob Minz, and Sung Kyu Lim, Effective Thermal Via and Decoupling Capacitor Insertion for 3D System-On-Package, IEEE Proceedings of ECTC, San Diego, CA, May 2006, pp. 1795-1801. Kang, U., H. Chung, S. Heo, D. Park, H. Lee, J. Kim, S. Ahn, S. Cha, J. Ahn, D. Kwon, J. Lee, H. Joo, W. Kim, D. Jang, N. Kim, J. Choi, T. Chung, J. Yoo, J. Choi, C. Kim, and Y. Jun, 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology, IEEE Journal of Solid-State Circuits, VOL. 45, NO. 1, January 2010, pp. 111-119. Lau, J. H., Y. Chan, R. Lee, Thermal-Enhanced and Cost-Effective 3D IC Integration with TSV (Through-Silicon Via) Interposers for High-Performance Applications, ASME Paper no. IMECE2010-40975. Shi, X., P. Sun, Y. Tsui, P. Law, S. Yau, C. Leung, Y. Liu, C. Chung, S. Ma, M. Miao, and Y. Jin, Development of

53.

54.

55.

56.

57.

58.

59.

60.

61.

62.

63.

CMOS-Process-Compatible Interconnect Technology for 3D-Stacking of NAND Flash Memory Chips, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 74-78. Kikuchi, K., C. Ueda, K. Takemura, O. Shimada, T. Gomyo, Y. Takeuchi, T. Ookubo, K. Baba, M. Aoyagi, T. Sudo, and K. Otsuka, Low-Impedance Evaluation of Power Distribution Network for Decoupling Capacitor Embedded Interposers of 3-D Integrated LSI System, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1455-1460. Sridharan, V., S. Min, V. Sundaram, V. Sukumaran, S. Hwang, H. Chan, F. Liu, C. Nopper* and R. Tummala, Design and Fabrication of Bandpass Filters in Glass Interposer with Through-Package-Vias (TPV), IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 530-535. Sukumaran, V., Q. Chen, F. Liu, N. Kumbhat, T. Bandyopadhyay, H. Chan, S. Min, C. Nopper, V. Sundaram, and R. Tummala, Through-Package-Via Formation and Metallization of Glass Interposers, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 557-563. Sakuma, K., K. Sueoka1, S. Kohara, K. Matsumoto, H. Noma, T. Aoki, Y. Oyama, H. Nishiwaki, P.S. Andry, C.K. Tsang, J. Knickerbocker, and Y. Orii, IMC Bonding for 3D Interconnection, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 864-871. Doany, F., B. Lee, C. Schow, C. Tsang, C. Baks, Y. Kwark, R. John, J. Knickerbocker, J. Kash, Terabit/s-Class 24-Channel Bidirectional Optical Transceiver Module Based on TSV Si Carrier for Board-Level Interconnects, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 58-65. Khan, N., D. Wee, O. Chiew, C. Sharmani, L. Lim, H. Li, and S. Vasarala, Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 884-888. Trigg, A., L. Yu, X. Zhang, C. Chong, C. Kuo, N. Khan, and D. Yu, Design and Fabrication of a Reliability Test Chip for 3D-TSV, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 79-83. Agarwal, R., W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 858-863. Tpper, M., I. Ndip, R. Erxleben, L. Brusberg, N. Nissen, H. Schrder, H. Yamamoto, G. Todt, H. Reichl, 3-D Thin Film Interposer Based on TGV (Through Glass Vias): An Alternative to Si-Interposer, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 66-73. Bouchoucha, M., P. Chausse, D. Henry, N. Sillon, Process Solutions and Polymer Materials for 3D-WLP Through Silicon Via Filling, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1696-1698. Liu, H., K. Wang, K. Aasmundtveit, and N. Hoivik, Intermetallic Cu3Sn as Oxidation Barrier for Fluxless Cu-Sn Bonding, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 853-857.

Keynote at IEEE Japan ICEP, April 13-15, 2011

64. Kang, I., G. Jung, B. Jeon, J. Yoo, and S. Jeong, Wafer Level embedded System in Package (WL-eSiP) for Mobile Applications, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 309-315. 65. Reed, J., M. Lueck, C. Gregory, A. Huffman, J. Lannon, Jr., and D. Temple, High Density Interconnect at 10m Pitch with Mechanically Keyed Cu/Sn-Cu and Cu-Cu Bonding for 3-D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 846-852. 66. Dorsey, P., Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency, Xilinx White Paper: Virtex-7 FPGAs, WP380 (v1) October 27, 2010, pp. 1-10. 67. Wang, Y., and T. Suga, Influence of Bonding Atmosphere on Low-Temperature Wafer Bonding, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 435-439. 68. Au, K., S. Kriangsak, X. Zhang, W. Zhu, and C. Toh, 3D Chip Stacking & Reliability Using TSV-Micro C4 Solder Interconnection, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1376-1384. 69. Akasaka, Y., Three-dimensional IC Trends, Proceedings of the IEEE, Vol. 74, No. 12, December 1986, pp. 1703-1714. 70. Akasaka, Y., and Nishimura, T., Concept and Basic Technologies for 3-D IC Structure, IEEE Proceedings of International Electron Devices Meetings, Vo. 32, 1986, pp. 488-491. 71. Chen, K., S. Lee, P. Andry, C. Tsang, A. Topop, Y. Lin, Y., J. Lu, A. Young, M., Ieong, and W. Haensch, W., Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits, IEEE Proceedings of International Electron Devices Meeting, (IEDM 2006), San Francisco, CA, December 11-13, 2006, pp. 367-370. 72. Liu, F., Yu, R., Young, A., Doyle, J., Wang, X., Shi, L., Chen, K., Li, X., Dipaola, D., Brown, D., Ryan, C., Hagan, J., Wong, K., Lu, M., Gu, X., Klymko, N., Perfecto, E., Merryman, A., Kelly K., Purushothaman, S., Koester, S., Wisnieff, R., and Haensch, W., A 300Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hyprid Cu-Adhesive Bonding, IEEE Proceedings of IEDM, December 2008, pp. 1-4.. 73. Yu, R., Liu, F., Polastre, R., Chen, K., Liu, X., Shi, L., Perfecto, E., Klymko, N., Chace, M., Shaw, T., Dimilia, D., Kinser, E., Young, A., Purushothaman, S., Koester, S., and Haensch W., Reliability of a 300-mm-compatible 3DI Technology Base on Hybrid Cu-adhesive Wafer Bonding, Proceedings of Symposium on VLSI Technology Digest of Technical Papers, 2009, pp. 170-171. 74. Shigetou, A. Itoh, T., Sawada, K., and Suga, T., Bumpless Interconnect of 6-um pitch Cu Electrodes at Room Temperature, In IEEE Proceedings of ECTC, Lake Buena Vista, FL, May 27-30, 2008, pp. 1405-1409. 75. Tsukamoto, K., E. Higurashi, and T. Suga, Evaluation of Surface Microroughness for Surface Activated Bonding, Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 147-150. 76. Kondou, R., C. Wang, and T. Suga, Room-temperature Si-Si and Si-SiN wafer bonding, Proceedings of IEEE

CPMT Symposium Japan, August 2010, , pp. 161-164. 77. Shigetou, A. Itoh, T., Matsuo, M., Hayasaka, N., Okumura, K., and Suga, T., Bumpless Interconnect Through Ultrafine Cu Electrodes by Mans of Surface-Activated Bonding (SAB) Method, IEEE Transaction on Advanced Packaging, Vol. 29, No. 2, May 2006, pp. 226. 78. Wang, C., and Suga, T., A Novel Moire Fringe Assisted Method for Nanoprecision Alignment in Wafer Bonding, In IEEE Proceedings of ECTC, San Diego, CA, May 25-29, 2009, pp. 872-878. 79. Wang, C., and Suga, T., Moire Method for Nanoprecision Wafer-to-Wafer Alignment: Theory, Simulation and Application, IEEE Proceedings of Int. Conference on Electronic Packaging Technology & High Density Packaging, August 2009, pp. 219-224. 80. Higurashi, E., Chino, D., Suga, T., and Sawada, R., Au-Au Surface-Activated Bonding and Its Application to Optical Microsensors with 3-D Structure, IEEE Journal of Selected Topic in Quantum Electronics, Vol. 15, No. 5 September/October 2009, pp. 1500-1505. 81. Burns, J., Aull, B., Keast, C., Chen, C., Chen, C. Keast, C., Knecht, J., Suntharalingam, V., Warner, K., Wyatt, P., and Yost, D., A Wafer-Scale 3-D Circuit Integration Technology, IEEE Transactions on Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516. 82. Chen, C., Warner, K., Yost, D., Knecht, J., Suntharalingam, V., Chen, C., Burns, J., and Keast, C., Sealing Three-Dimensional SOI Integrated-Circuit Technology, IEEE Proceedings of Int. SOI Conference, 2007, pp. 87-88. 83. Chen, C., Chen, C., Yost, D., Knecht, J., Wyatt, P., Burns, J., Warner, K., Gouker, P., Healey, P., Wheeler, B., and Keast, C., Three-dimensional integration of silicon-on-insulator RF amplifier, Electronics Letters, Vol. 44, No. 12, June 2008, pp. 1-2. 84. Chen, C., Chen, C., Yost, D., Knecht, J., Wyatt, P., Burns, J., Warner, K., Gouker, P., Healey, P., Wheeler, B., and Keast, C., Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers, IEEE Proceedings of Silicon Monolithic IC in RF Systems, 2009, pp. 1-4. 85. Chen, C., Chen, C., Wyatt, P., Gouker, P., Burns, J., Knecht, J., Yost, D., Healey, P., and Keast, C, Effects of Through-BOX Vias on SOI MOSFETs, IEEE Proceedings of VLSI Technology, Systems and Applications, 2008, pp. 1-2. 86. Chen, C., Chen, C., Burns, J., Yost, D., Warner, K., Knecht, J., Shibles, D., and Keast, C, Thermal Effects of Three Dimensional Integrated Circuit Stacks, IEEE Proceedings of Int. SOI Conference, 2007, pp. 91-92. 87. Aull, B., Burns, J., Chen, C., Felton, B., Hanson, H., Keast, C., Knecht, J., Loomis, A., Renzi, M., Soares, A., Suntharalingam, V., Warner, K., Wolfson, D., Yost, D., and Young, D., Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers, IEEE Proceedings of Int. Solid-State Circuits Conference, 2006, pp. 16.9. 88. Chatterjee, R., Fayolle, M., Leduc, P., Pozder, S., Jones, B., Acosta, E., Charlet, B., Enot, T., Heitzmann, M., Zussy, M., Roman, A., Louveau, O., Maitreqean, S., Louis, D., Kernevez, N., Sillon, N., Passemard, G., Pol, V., Mathew, V., Garcia, S., Sparks, T., and Huang, Z.,

Keynote at IEEE Japan ICEP, April 13-15, 2011

Three dimensional chip stacking using a wafer-to-wfer integration, IEEE Proceedings of IITC, 2007, pp. 81-83. 89. Ledus, P., Crecy, F., Fayolle, M., Fayolle, M., Charlet, B., Enot, T., Zussy, M., Jones, B., Barbe, J., Kernevez, N., Sillon, N., Maitreqean, S., Louis, D., and Passemard, G., Challenges for 3D IC integration: bonding quality and thermal management, IEEE Proceedings of IITC, 2007, pp. 210-212. 90. Poupon, G., Sillon, N., Henry, D., Gillot, C., Mathewson, A., Cioccio, L., Charlet, B., Leduc, P., Vinet, M., and Batude, P., System on Wafer: A New Silicon Concept in Sip, Proceedings of the IEEE, Vol. 97, No. 1, January 2009, pp. 60-69. 91. Fujimoto, K., N. Maeda, H. Kitada, Y. Kim. A. Kawai, K. Arai, T. Nakamura, K. Suzuki, and T. Ohba, Development of Multi-Stack Process on Wafter-on-Wafer (WoW), Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 157-160. 92. Healy, M., and S. Lim, Power Delivery System Architecture for Many-Tier 3D Systems, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1682-1688. 93. Liu, F., X. Gu, K. A. Jenkins, E. A. Cartier, Y. Liu, P. Song, and S. J. Koester, Electrical Characterization of 3D Through-Silicon-Vias, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1100-1105. 94. Gu, X., B. Wu, M. Ritter, and L. Tsang, Efficient Full-wave Modeling of High Density TSVs for 3D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 663-666. 95. Okoro, C., R. Agarwal, P. Limaye, B. Vandevelde, D. Vandepitte, E. Beyne1, Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1370-1375. 96. Huyghebaert, C., J. Olmen, O. Chukwudi, J. Coenen, A. Jourdain, M. Cauwenberghe, R. Agarwahl, R., A. Phommahaxay, M. Stucchi and P. Soussan., Enabling 10m Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1083-1087. 97. Pak, J., J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, Slow Wave and Dielectric Quasi-TEM Modes of Metal-Insulator-Semiconductor (MIS) Structure Through Silicon Via (TSV) in Signal Propagation and Power Delivery in 3D Chip Package, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 667-672. 98. Cioccioa, L., P. Gueguena, E. Grouillera, L. Vandrouxa, V. Delayea, M. Rivoireb, J. Lugandb, L. Claveliera, Vertical Metal Interconnect Thanks to Tungsten Direct Bonding, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, 1359-1363. 99. Gueguena, P., L. Cioccioa, P. Morfoulib, M. Zussya, J. Dechampa, L. Ballya, L. Claveliera, Copper Direct Bonding: An Innovative 3D Interconnect, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 878-883. 100. Taibi, R., L. Ciocciob, C. Chappaz, L. Chapelon, P. Gueguenb, J. Dechampb, R. Fortunierc, L. Clavelierb, Full Characterization of Cu/Cu Direct Bonding for 3D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 219-225.

101. Lim, D., J. Wei, C. Ng, and C. Tan, Low Temperature Bump-less Cu-Cu Bonding Enhancement with Self Assembled Monolayer (SAM) Passivation for 3-D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1364-1369. 102. Onkaraiah, S., and C. Tan, Mitigating Heat Dissipation and Thermo-Mechanical Stress Challenges in 3-D IC Using Thermal Through Silicon Via (TTSV), IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 411-416. 103. Campbell, D., Process Characterization Vehicles for 3D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1112-1116. 104. Bieck, F. S. Spiller, F. Molina, M. Tpper, C. Lopper, I. Kuna, T. Seng, T. Tabuchi, Carrierless Design for Handling and Processing of Ultrathin Wafers, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 316-322. 105. Itabashi, T., M. Zussman, High Temperature Resistant Bonding Solutions Enabling Thin Wafer Processing (Characterization of Polyimide Base Temporary Bonding Adhesive for Thinned Wafer Handling), IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1877-1880. 106. Lee, G., H. Son, J. Hong, K. Byun, and D. Kwon, Quantification of Micropartial Residual Stress for Mechanical Characterization of TSV through Nanoinstrumented Indentation Testing, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 200-205. 107. Dang, B., P. Andry, C. Tsang, J. Maria, R. Polastre, R. Trzcinski, A. Prabhakar, and J. Knickerbocker, CMOS Compatible Thin Wafer Processing using Temporary Mechanical Wafer, Adhesive and Laser Release of Thin Chips/Wafers for 3D Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1393-1398. 108. Pang, X., T. T. Chua, H. Y. Li, E.B. Liao, W. S. Lee, and F. X. Che, Characterization and Management of Wafer Stress for Various Pattern Densities in 3D Integration Technology, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1866-1869. 109. Zoschke, K., M. Wegner, M. Wilke, N. Jrgensen, C. Lopper, I. Kuna, V. Glaw, J. Rder1, O. Wnsch1, M. J. Wolf, O. Ehrmann, and H. Reichl, Evaluation of Thin Wafer Processing using a Temporary Wafer Handling System as Key Technology for 3D System Integration, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1385-1392. 110. Charbonnier, J., R. Hida, , D. Henry, S. Cheramy, P. Chausse, M. Neyret, O. Hajji, G. Garnier, C. Brunet-Manquat, P. Haumesser, L. Vandroux, R. Anciant, N. Sillon, A. Farcy, M. Rousseau, J. Cuzzocrea, G. Druais, E. Saugier, Development and Characterisation of a 3D Technology Including TSV and Cu Pillars for High Frequency Applications, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1077-1082. 111. Sun, Y., X. Li, J. Gandhi, S. Luo, and T. Jiang, Adhesion Improvement for Polymer Dielectric to Electrolytic-Plated Copper, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1106-1111.

Keynote at IEEE Japan ICEP, April 13-15, 2011

112. Kawano, M., N. Takahashi, M. Komuro, and S. Matsui, Low-Cost TSV Process Using Electroless Ni Plating for 3D Stacked DRAM, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1094-1099. 113. Malta, D., C. Gregory, D. Temple, T. Knutson, C. Wang, T. Richardson, Y. Zhang, and R. Rhoades, Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1769-1775. 114. Campbell, D., Yield Modeling of 3D Integrated Wafer Scale Assemblies, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1935-1938. 115. Archard, D., K. Giles, A. Price, S. Burgess, and K. Buchanan, Low Temperature PECVD of Dielectric Films for TSV Applications, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 764-768. 116. Shigetou, A., and T. Suga, Modified Diffusion Bonding for Both Cu and SiO2 at 150 C in Ambient Air, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 872-877. 117. Amagai, M., and Y. Suzuki, TSV Stress Testing and Modeling, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1273-1280. 118. Gupta, A., S. Kannan, B. Kim, F. Mohammed, and B. Ahn, Development of Novel Carbon Nanotube TSV Technology, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 1699-1702. 119. Kannan, S., A. Gupta, B. Kim, F. Mohammed, and B. Ahn, Analysis of Carbon Nanotube Based Through Silicon Vias, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 51-57. 120. Lu, K., S. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. Ho, Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects, IEEE Proceedings of ECTC, June 2010, Las Vegas, NV, pp. 40-45. 121. Miyazaki, C., H. Shimamoto, T. Uematsu, Y. Abe, K. Kitaichi, T. Morifuji, and S. Yasunaga, Development of high accuracy wafer thinning and pickup technology for thin wafer (die), Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 139-142. 122. Cho, J., K. Yoon, J. Pak, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, Guard Ring Effect for Through Silicon Via (TSV) Noise Coupling Reduction, Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 151-154. 123. Nonake, T., K. Fujimaru, A. Shimada, N. Asahi, Y. Tatsuta, H. Niwa, and Y. Tachibana, Wafer and/or chip bonding adhesives for 3D package, Proceedings of IEEE CPMT Symposium Japan, August 2010, , pp. 169-172. 124. Lau, J. H., Heart and Soul of 3D IC Integration, posted at 3D InCites on June 29, 2010, http://www.semineedle.com/posting/34277. 125. Lau, J. H., Who Invented the TSV and When? posted at 3D InCites on April 24, 2010, http://www.semineedle.com/posting/31171. 126. Gat, A., L. Gerzberg, J. Gibbons, T. Mages, J. Peng, and J. Hong, CW Laser of Polyerystalline Silicon: Crystalline Structure and Electrical Properties, Applied Physics Letter, Vol. 33, Issue 8, October 1978,

pp. 775-778. 127. Lau, J. H., Flip Chip Technology, McGraw-Hill, New York, NY, 1996. 128. Lau, J. H., Low Cost Flip Chip Technologies, McGraw-Hill, New York, NY, 2000. 129. Hu, G., Kalyanam, H., Krishnamoorthy, S., and Polka, L. Package technology to address the memory bandwidth challenge for tera-scale computing. INTEL Technol. J. Vol. 11, 2007, pp: 197206. 130. Ong, Y., S. Ho, K. Vaidyanathan, V. Sekhar, M. Jong, S. Long, V. Lee, C. Leong, V. Rao, J. Ong, X. Ong, X. Zhang, Y. Seung, J. H. Lau, Y. Lim, D. Yeo, K. Chan, Z. Yanfeng, J. Tan, and D. Sohn. Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package, Journal of Microelectronics Reliability, Vol. 50, 2010, pp. 986994. 131. Lau, J. H., and R. S. W. Lee, Microvias for Low Cost, High Density Interconnects, McGraw-Hill, New York, NY, 2001. 132. Lau, J. H., Ball Grid Array Technology, McGraw-Hill, New York, NY, 1995. 133. Lau, J. H., T. Tseng, and D. Cheng, Heat Spreader with a Placement Recess and Bottom Saw-Teeth for Connection to Ground planes on a This Two-Side Single-Core BGA Substrate, US Patent No. 6,057,601, Granted: May 2, 2000, Filed: November 27, 1998. 134. Lau, J. H., and K. L. Chen, Thermal and Mechanical Evaluations of a Cost-Effective Plastic Ball Grid Array Package, ASME Transactions, Journal of Electronic Packaging, Vol. 119, September 1997, pp. 208-212. 135. Lau, J. H., and T. Chen, Cooling Assessment and Distribution of Heat Dissipation of A Cavity Down Plastic Ball Grid Array Package NuBGA, IMAPS Transactions, International Journal of Microelectronics & Electronic Packaging, Vol. 21, No. 1, 1998, pp. 20-28. 136. Lau, J. H., and T. Chou, Electrical Design of a Cost-Effective Thermal Enhanced Plastic Ball Grid Array Package - NuBGA, IEEE Transactions on CPMT, Part B, Vol. 21, No. 1, Feb. 1998, pp. 35-42. 137. Lau, J. H., T. Chen, and R. Lee, Effect of Heat Spreader Sizes on the Thermal Performance of Large Cavity-Down Plastic Ball Grid Array Packages, ASME Transactions, Journal of Electronic Packaging, Vol. 121, No. 4, 1999, pp. 242-248. 138. Lau, J. H., Design, Manufacturing, and Testing of a Novel Plastic Ball Grid Array Package, Journal of Electronics Manufacturing, Vol. 9, No. 4, December 1999, pp. 283-291. 139. Lau, J. H., and T. Chen, Low-Cost Thermal and Electrical Enhanced Plastic Ball Grid Array Package NuBGA, Microelectronics International, 1999. 140. Lau, J. H., Solder Joint Reliability of Flip Chip and Plastic Ball Grid Array Assemblies Under Thermal, Mechanical, and Vibration Conditions'', IEEE Transaction on CPMT, Part B, Vol. 19, No. 4, pp. 728-735, November 1996. 141. Lau, J. H., with R. Lee, Design for Plastic Ball Grid Array Solder Joint Reliability, Journal of the Institute of Interconnection Technology, Vol. 23, No. 2, January 1997, pp. 11-13.

Keynote at IEEE Japan ICEP, April 13-15, 2011

142. Lau, J. H., with W. Jung and Y. Pao, Nonlinear Analysis of Full-Matrix and Perimeter Plastic Ball Grid Array Solder Joints, ASME Transactions, Journal of Electronic Packaging, Vol. 119, September 1997, pp. 163-170.

143. Lau, J. H., with R. Lee, Solder Joint Reliability of Cavity-Down Plastic Ball Grid Array Assemblies, Journal of Soldering & Surface Mount Technology, Vol. 10, No. 1, February 1998, pp. 26-31.

Keynote at IEEE Japan ICEP, April 13-15, 2011