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by

Riad Samir Wahby

S.B., Massachusetts Institute of Technology (2002)

Submitted to the Department of Electrical Engineering and Computer Science

in partial fulﬁllment of the requirements for the degree of

Master of Engineering

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

May 2004

c Riad Samir Wahby, MMIV. All rights reserved.

The author hereby grants to MIT permission to reproduce and distribute publicly

paper and electronic copies of this thesis document in whole or in part.

Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Department of Electrical Engineering and Computer Science

May 20, 2004

Certiﬁed by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

David J. Perreault

Carl Richard Soderberg Assistant Professor of Power Engineering

Thesis Supervisor

Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Arthur C. Smith

Chairman, Department Committee on Graduate Students

Radio Frequency Rectiﬁers for DC-DC Power Conversion

by

Riad Samir Wahby

Submitted to the Department of Electrical Engineering and Computer Science

on May 20, 2004, in partial fulﬁllment of the

requirements for the degree of

Master of Engineering

Abstract

A signiﬁcant factor driving the development of power conversion technology is the need to

increase performance while reducing size and improving eﬃciency. In addition, there is a

desire to increase the level of integration of DC-DC converters in order to take advantage

of the cost and other beneﬁts of batch fabrication techniques. While advances in the power

density and integration of DC-DC converters have been realized through development of

better active device technologies, much room for improvement remains in the size and

fabrication of passive components.

To achieve these improvements, a substantial increase in operating frequency is needed,

since intermediate energy storage requirements are inversely proportional to frequency. Un-

fortunately, traditional power conversion techniques are ill-suited to handle this dramatic

escalation of switching frequency. New architectures have been proposed which promise to

deliver radical performance improvements while potentially reaching microwave frequencies.

These new architectures promise to enable substantial miniaturization of DC-DC converters

and to permit much a higher degree of integration.

The principal eﬀort of this thesis is the development of design and characterization

methods for rectiﬁer topologies amenable to use in the new architectures. A computational

design approach allowing fast and accurate circuit analysis and synthesis is developed and

applied, along with traditional analysis, to two demonstrative rectiﬁer topologies. In addi-

tion, the application of coupled magnetic structures for parasitic mitigation is considered.

Experimental implementations are investigated to verify analytic and computational results.

Thesis Supervisor: David J. Perreault

Title: Carl Richard Soderberg Assistant Professor of Power Engineering

Acknowledgments

Thanks ﬁrst and foremost to my parents. Their dedication to my education, unconditional

love, and unwavering support have been, simply put, astounding. To my sisters, too, I say

thanks for everything.

Not long ago, I was unsure of my career path. It was Professor Dave Perreault who

brought me ﬁrmly back into the electrical engineering fold, so to speak, and for that I am

in his debt. His incredible enthusiasm and unparalleled knowledge of seemingly everything

have made working for him the past year an awesome learning experience and a source of

constant intellectual stimulation.

I owe thanks to my friends as well. In no real order, thanks to Jack, Jim, Mar, Andrew,

Rob, Chris, Josh, Juan, Claudio, and everyone else in LEES; to Hippo, Ariel, Gautham,

Sherv, Ian, Rodin, Amrys, George, Max, Sam, Kurt, Petar, Woz, May, and the rest of the

Fort Awesome crew; and to Kevin, Dave, Lael, Perry, and the rest of Clam’s old guard. If

for some reason I didn’t list you here—thank you, too.

A long time ago, I used to consider myself a violinist (and what’s more, other people

did as well!). My musical training has proven an immeasurable help in many unexpected

ways; thus, special thanks go to Doris Preucil and to Claudia Johnson.

Finally, I would like to thank the Massachusetts Institute of Technology and the member

companies of the MIT/Industry Consortium on Advanced Automotive Electrical/Electronic

Components and Systems, whose sponsorship enabled this research.

To my parents, whose dedication has been without parallel.

Contents

1 Introduction 15

1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1.1 Problems With High-Frequency Power Conversion . . . . . . . . . . 16

1.1.2 Proposed Architectural Improvements . . . . . . . . . . . . . . . . . 18

1.2 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2 Useful Techniques for Resonant Circuit Analysis 23

2.1 Resonant Impedance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.1 Jacobi’s Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1.2 Series-Shunt Transformation . . . . . . . . . . . . . . . . . . . . . . 25

2.1.3 The L-Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2 Higher Order Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.1 The L-Match Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2.2 The T- and Π-Matches . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2.3 Tapped Capacitor Resonator . . . . . . . . . . . . . . . . . . . . . . 31

2.2.4 Tapped Inductor Resonator . . . . . . . . . . . . . . . . . . . . . . . 33

2.2.5 The Double-Tapped Resonator . . . . . . . . . . . . . . . . . . . . . 34

2.3 Active Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3 Computational Techniques for Nonlinear Circuits 37

—7—

CONTENTS

3.1 Motivations for Computational Analysis . . . . . . . . . . . . . . . . . . . . 37

3.2 Nonlinear Network Impedance Considerations . . . . . . . . . . . . . . . . . 38

3.3 The Iterated Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.1 Basic Iterated Matching . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.2 Improved Iterated Matching . . . . . . . . . . . . . . . . . . . . . . . 41

3.3.3 Convergence of the Iterated Matching Procedure . . . . . . . . . . . 43

3.4 SAMwIICh: An Automated Matching Implementation . . . . . . . . . . . . 44

4 The Series Resonant Rectiﬁer 47

4.1 Analysis of the Series Resonant Rectiﬁer . . . . . . . . . . . . . . . . . . . . 47

4.2 Fourier Analysis of Input Impedance . . . . . . . . . . . . . . . . . . . . . . 49

4.3 Comparison of Analytic Model with Simulation . . . . . . . . . . . . . . . . 52

4.4 Application of the Series Resonant Rectiﬁer . . . . . . . . . . . . . . . . . . 54

4.5 Experimental Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 The Shunt Resonant Rectiﬁer 57

5.1 Analysis of the Shunt Resonant Rectiﬁer . . . . . . . . . . . . . . . . . . . . 57

5.2 Comparison of Analytic Model with Simulation . . . . . . . . . . . . . . . . 60

5.3 Application of the Shunt Resonant Rectiﬁer . . . . . . . . . . . . . . . . . . 61

5.4 Experimental Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5 Parasitic Mitigation in the Shunt Rectiﬁer . . . . . . . . . . . . . . . . . . . 64

6 Conclusion 69

6.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2 Thesis Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.3 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . . . . . 71

Bibliography 71

A SAMwIICh Code Listings 77

A.1 Makefile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

—8—

CONTENTS

A.2 automatch.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

A.3 matching.sp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

A.4 Eﬃciency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A.4.1 effextract.sh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A.4.2 effcalc.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A.5 Impedance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A.5.1 impextract.sh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A.5.2 impcalc.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

B SPICE Netlists 87

B.1 Comparison of Analytic Model with Simulation, Series Rectiﬁer . . . . . . . 87

B.1.1 Ideal Diode, Linear Capacitor . . . . . . . . . . . . . . . . . . . . . . 87

B.1.2 Real Diode with Constant Junction Capacitance . . . . . . . . . . . 88

B.1.3 Real Diode, Constant C

j

, Conjugate Source Impedance . . . . . . . 89

B.2 Series Resonant Rectiﬁer Output Impedance . . . . . . . . . . . . . . . . . . 90

B.3 Comparison of Analytic Model with Simulation, Shunt Rectiﬁer . . . . . . . 91

B.3.1 Ideal Diode, Linear Capacitor . . . . . . . . . . . . . . . . . . . . . . 91

B.3.2 Real Diode with Constant Junction Capacitance . . . . . . . . . . . 92

B.4 Shunt Resonant Rectiﬁer, Experimental Implementation . . . . . . . . . . . 93

B.5 Shunt Resonant Rectiﬁer with Parasitic Mitigation . . . . . . . . . . . . . . 94

C Scripts for PCB Inductor Generation 97

C.1 mkcan.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

C.2 spiral.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

C.3 dat2fig.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

C.4 dat2ind.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

C.5 dat2scr.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

C.6 placescr.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

C.7 qcalc.pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

—9—

CONTENTS

C.8 Miscellaneous Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

C.8.1 placedat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

C.8.2 gpdat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

D Shunt Rectiﬁer PCB Layouts and Magnetic Structures 113

—10—

List of Figures

1-1 An illustration of switching loss in the boost converter. . . . . . . . . . . . . 17

1-2 The basic structure of the proposed architectures. . . . . . . . . . . . . . . . 19

2-1 A simple circuit for deriving Jacobi’s theorem. . . . . . . . . . . . . . . . . 24

2-2 The L-match is derived by series-shunt transformation of one element in a

series resonant circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2-3 The T- and Π-matches, composed of two L-matches, give the designer another

degree of freedom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2-4 The tapped capacitor match gives more freedom than the L-match and, in

some cases, more reasonable component values than the T- or Π-match. . . 32

2-5 The tapped inductor match is a close relative of the tapped capacitor match

of section 2.2.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2-6 The double-tapped resonator gives an additional degree of freedom beyond

the third-order matching networks. . . . . . . . . . . . . . . . . . . . . . . . 34

2-7 Diode junction capacitances can be used to obtain a controlled L-match. A

DC voltage V

c

applied as shown controls the shunt capacitance. . . . . . . . 36

3-1 Linearized input impedance models. . . . . . . . . . . . . . . . . . . . . . . 39

3-2 A demonstration of the iterated impedance matching approach. . . . . . . . 41

3-3 An improved matching network for the circuit of Fig. 3-2(a). . . . . . . . . 42

4-1 The series resonant rectiﬁer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

—11—

LIST OF FIGURES

4-2 A parallel RL model for series rectiﬁer input impedance. . . . . . . . . . . . 49

4-3 To provide a DC current path, all or part of L

s

can be transformed into L

shn

. 54

4-4 Experimental implementation of the series rectiﬁer. . . . . . . . . . . . . . . 55

5-1 The shunt resonant rectiﬁer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5-2 The computationally-assisted design process for the shunt resonant rectiﬁer. 62

5-3 Experimental implementation of the shunt rectiﬁer. . . . . . . . . . . . . . . 63

5-4 The shunt resonant rectiﬁer with coupled magnetics for parasitic mitigation. 65

5-5 Experimental implementation of the shunt rectiﬁer with parasitic mitigation. 65

D-1 Layout for shunt rectiﬁer without cancellation. . . . . . . . . . . . . . . . . 114

D-2 L

M

= 3.5 nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

D-3 L

M

= 4.0 nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

D-4 L

M

= 4.6 nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

D-5 L

M

= 6.3 nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

—12—

List of Tables

4.1 Input impedance, output power, and eﬃciency, calculated versus simulated. 53

4.2 Component values used in the series rectiﬁer experimental implementation. 56

5.1 Output power and eﬃciency, calculated versus simulated. . . . . . . . . . . 60

5.2 Component values used in the shunt rectiﬁer experimental implementation. 63

5.3 Component values used in the experimental implementation of the shunt

rectiﬁer with parasitic mitigation. . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4 Experimental results for shunt rectiﬁers with parasitic mitigation. . . . . . . 66

—13—

Chapter 1

Introduction

1.1 Background and Motivation

C

ONTEMPORARY research in DC-DC power conversion is strongly motivated by

the need to increase performance while reducing size and maintaining or improv-

ing eﬃciency. In addition, there is a desire to achieve a higher degree of integration of

DC-DC converters, allowing major portions of systems to be manufactured using batch

fabrication techniques. While some improvements in the power density and integration

of DC-DC converters can be realized through extensive miniaturization and integration of

active components, equal or greater beneﬁt can be achieved by reducing the size of the

passive components. Doing so requires in almost all cases an increase in the frequency at

which the converter operates, since intermediate energy storage requirements are inversely

proportional to operating frequency.

Unfortunately, this increase in operating frequency is not without costs. At higher fre-

quencies, non-idealities in circuit components become much more important. Moreover, loss

mechanisms that can generally be ignored at low frequencies become crucial design consid-

erations. Finally, control strategies commonly used at low frequencies become unwieldy

when used at high frequencies.

To combat these diﬃculties, new circuit topologies and system architectures can be used.

—15—

Introduction

Replacing hard-switched square-wave topologies with resonant, soft-switched converters al-

lows high frequency converter designs that take advantage of techniques employed in tuned

radio frequency power ampliﬁers. To solve the problem of controlling these high-frequency

DC-DC converters, a new architectural approach will be employed which partially decouples

the problems of eﬃcient power conversion and controlled power delivery.

This thesis will explore rectiﬁcation of power at high frequencies (100 MHz–1 GHz) and

its application to new architectures for DC-DC conversion. In particular, rectiﬁer topologies

suitable for parallel combination in a cellular converter architecture will be designed and

characterized. In addition, a new computational approach to circuit analysis and design

synthesis will be presented.

1.1.1 Problems With High-Frequency Power Conversion

Whereas at low frequencies conduction losses are generally dominant, at high frequencies two

other loss mechanisms, switching loss and gating loss, must also be considered. In addition,

traditional control strategies for low frequency converters are impractical at high frequencies.

Finally, implementing passive components compatible with eﬃcient power processing at

high frequency is often diﬃcult; inductors are of particular concern, as there exist few

permeable materials whose performance is acceptable for application in high frequency

power conversion.

Switching Loss

Switching loss arises from the fact that no practical active element can turn on or oﬀ

instantaneously: there is some interval during which the device must traverse the region

between the on and oﬀ states. During this time, the device both conducts current and drops

voltage, dissipating power. Figure 1-1 illustrates a boost converter (1-1(a)) and the on-to-

oﬀ transient of the MOSFET (1-1(b)). Assuming a large input inductor (i.e., continuous

conduction operation), the transistor must conduct current until its drain voltage rises to

one diode drop above the output voltage; only then is the diode forward biased and able

—16—

1.1 Background and Motivation

V

in

L

C R

load

v

D

i

D

D

D

+

+

−

−

(a) A boost converter circuit.

v

D

i

D

t

t

(b) Switching waveforms.

Figure 1-1: An illustration of switching loss in the boost converter.

to conduct current to the output. For a typical device such a transition takes about 15

nanoseconds—insigniﬁcant at 100 kHz, but untenable at 100 MHz [1].

To ameliorate switching losses, zero-voltage switching topologies are often employed [2].

In these topologies, a continuous resonating action is used to ensure that switches only

change state when supporting little or no voltage. While ZVS can be advantageous when

applied to DC-DC conversion at full load, it becomes a problem at light load: since the

losses accompanying resonant operation are present at all load conditions, eﬃciency when

delivering only a fraction of full power is severely reduced.

Gating Loss

Gating loss is a result of the fact that turning any active device on or oﬀ involves a transfer

of energy. In a MOSFET, for example, the gate capacitance must be charged to turn the

device on and discharged to turn it oﬀ. In a switching scheme where the gate terminal is

charged from the supply and discharged into ground, power loss proportional to frequency

results. By employing resonant structures in driving the gate, energy can be recovered and

reused in subsequent cycles. In the simplest of such circuits, the energy transferred onto the

gate capacitor is transferred oﬀ and stored on an external inductor until the next switching

cycle; in this way, energy is only lost in conduction [3–6]. In eﬀect, a resonant gate driver

—17—

Introduction

is itself an RF ampliﬁer; thus, the beneﬁts of resonant gate drive can often be most fully

developed by using a cascade of resonant converters, one driving the next.

Control Strategies

Control strategies employed at low frequencies are not easily adapted to eﬃcient high fre-

quency topologies. Since such strategies often require direct manipulation of the harmonic

content of operating waveforms, they are generally incompatible with ZVS and resonant

gate drive topologies. Regulation can be achieved by other techniques, such as frequency

control [7, 8]; even so, realizing regulation over a wide load range becomes increasingly diﬃ-

cult as frequencies increase, as do considerations of converter dynamics and the complexity

of implementing control circuitry. Moreover, cascaded resonant gate drive is often at odds

with such a strategy, forcing the designer to trade oﬀ ease of control for eﬃciency.

Magnetic Components

At low frequencies, passive component sizing is dominated by volumetric energy storage

limits. At higher frequencies, losses become the most important consideration in the sizing

of magnetic components. For most ferrite materials, core losses increase dramatically with

frequency; to mitigate these loss characteristics, ﬂux derating becomes necessary. As a

result, increasing frequency can cause inductor sizes to worsen instead of improving [9]. Air-

core magnetic passives, lacking a lossy permeable core material, do not suﬀer this limitation;

however, the consequently reduced inductance per turn squared requires very high frequency

operation to achieve reasonable component size and Q.

1.1.2 Proposed Architectural Improvements

To overcome the limitations of very high frequency operation while taking advantage of

its beneﬁts, new cellular architectures have been proposed [10]. These architectures utilize

high eﬃciency tuned RF power ampliﬁer circuits while partitioning the energy conversion

and control functions so as to avoid the limitations discussed in section 1.1.1.

—18—

1.1 Background and Motivation

R

load

+

−

V

r

R

r

I

u1

R

u1

I

u2

R

u2

I

un

R

un

(a) The proposed architectures employ one regulating cell (Vr, Rr) and several unregulated

cells (Iu1 . . . un, Ru1 . . . un).

V

in

R

load

+

−

Inverter Matching Network Rectiﬁer

(b) The basic structure of an unregulated cell comprises an inverter and a rectiﬁer connected by an

impedance matching network.

Figure 1-2: The basic structure of the proposed architectures.

The new architectures employ two types of cells. RF power converters comprising an

inverter and rectiﬁer operating at very high frequency are used as unregulated, on/oﬀ-

controlled parallel cells. Each unregulated cell operates only when required, and only over

a narrow range of conditions; this allows nearly maximum performance to be achieved at

all times. Control is provided by a regulating cell, which only provides a fraction of the

output power; this reduces the impact of regulating cell loss on total eﬃciency. Figure 1-2(a)

illustrates the proposed architecture; the basic structure of one unregulated cell is depicted

in Fig. 1-2(b).

The principal eﬀort of this thesis is the development of design and characterization

methods for rectiﬁer topologies amenable to use in the aforementioned architectures

1

. In

this application, eﬃciency is of paramount importance. In addition, a well-characterized

input impedance is crucial for optimizing the matching network that connects the inverter

and rectiﬁer. Finally, a rectiﬁer having high output impedance is desirable, since this

facilitates load sharing among a parallel combination of several unregulated cells; failure to

1

The design of a suitable inverter is the topic of a separate investigation.

—19—

Introduction

share the load equally could result in ineﬃcient operation or cell failure [11–13].

In radio frequency rectiﬁers employing diodes, both conduction losses and switching

losses are important considerations

2

. To achieve acceptable eﬃciency, a resonant zero-

voltage switching topology which minimizes peak diode currents is necessary [14–20]. More-

over, parasitics associated with the active device are very important at high frequencies;

thus, a topology that makes use of these parasitics will likely outperform one that does not.

Alternatively, undesirable parasitic inductances might be cancelled using coupled magnetic

structures [21, 22].

1.2 Thesis Objectives

This thesis explores the selection, characterization, design, and implementation of radio

frequency rectiﬁers with the aim of improving both the process and product of future

rectiﬁer designs. To this end, I have several objectives.

First, I will demonstrate general

3

methods for cocktail napkin-style analysis of linear

resonant circuits. As much as possible, I will attempt to employ intuition and reasonable

estimates, and will show the methods used for developing both. When necessary, arduous

mathematical derivations will be accompanied by ample verbiage, allowing the casual reader

to proceed quickly to the ﬁnal result.

Second, I will develop an approach for computational modeling of nonlinear resonant

circuits. In particular, I will show algorithms for fast and accurate computational circuit

synthesis, allowing the user to proceed from speciﬁcation to design very quickly. Though

some minimal programming skill will likely be useful, the reader will not be unduly taxed

with abstruse code listings

4

.

Third, I will apply these analytic and computational techniques to example rectiﬁer

topologies, and establish the groundwork for similar analysis of others. In addition to stan-

2

Synchronous rectiﬁcation, not considered in this thesis, incurs additional penalty in gating, but may

result in overall eﬃciency improvement, since diode drop and the resulting conduction loss are largely

avoided.

3

. . . though not necessarily original!

4

For those of true grit, full code is provided in the appendices.

—20—

1.3 Thesis Organization

dard topologies, I will explore the use of coupled magnetic structures (which can be, e.g.,

implemented on printed circuit boards), allowing device parasitic mitigation and reduced

manufacturing cost. These will be accompanied by both simulation and experimental eval-

uation.

1.3 Thesis Organization

This thesis is divided into six chapters, including this introduction.

Chapter 2 reviews analytic techniques useful in linear resonant circuit analysis, and

demonstrates the application of these techniques to the analysis and design of resonant

impedance transformers.

Chapter 3 introduces the use of computational modeling for nonlinear circuit analysis.

In this chapter, algorithms are developed that allow for extremely fast design of rectiﬁer

circuits and which pave the way for the analyses performed in the proceeding chapters.

Chapter 4 discusses the ﬁrst of two resonant rectiﬁer topologies, exploring the design and

implementation process of the series resonant rectiﬁer. Chapter 4 comprises a discussion

of analytic models including Fourier and describing function analysis of input impedance,

a comparison of the analytic models with simulation, and a discussion of the strengths and

weaknesses of the series resonant topology. Experimental results are also discussed.

Chapter 5 covers another topology, the shunt resonant rectiﬁer. In addition to a dis-

cussion of analytic models and simulated results, the exploration of the shunt topology is

extended by application of coupled magnetic structures which allow the mitigation of unde-

sired parasitic eﬀects. Implementations of rectiﬁers with and without parasitic mitigation

are presented.

Finally, Chapter 6 concludes the thesis with a summary of the results and suggestions

for continued work.

—21—

Chapter 2

Useful Techniques for Resonant

Circuit Analysis

T

HIS CHAPTER is intended to familiarize the reader with useful analytic tech-

niques for linear resonant circuits. Much of the material is available from other

sources [23–25]; this chapter has been included nevertheless, since analytic approaches to

the same problem diﬀer substantially from one book to another, and because the particular

techniques reviewed here are a key component of the insight leading to the algorithms pre-

sented in chapter 3. In addition, the last section discusses an active impedance matching

network which might be employed in a feedforward or feedback system to eﬀect a dynamic

match.

2.1 Resonant Impedance Analysis

A major challenge in designing RF rectiﬁers, and indeed almost any RF power circuit,

is ensuring that maximum power is transferred from input to output. Because many RF

circuits operate over only a very limited frequency band, the use of narrowband impedance

transformation circuits is exceedingly common. Before delving into the analysis of such

circuits, however, it’s useful to remember the reason for their use.

—23—

Useful Techniques for Resonant Circuit Analysis

+

−

V

s

Z

s

Z

ℓ

V

ℓ

Figure 2-1: A simple circuit for deriving Jacobi’s theorem.

2.1.1 Jacobi’s Theorem

In low frequency designs, there is no diﬃculty in obtaining power gain. At radio frequencies,

however, the scarcity of power gain necessitates the resurrection of an oft-forgotten theorem

taught in every basic circuits course: for a ﬁxed source impedance, maximum power is always

transferred into a conjugate matched load

1

. Figure 2-1 shows an example circuit from which

derivation of the maximum power transfer theorem is straightforward.

P

ℓ

=

V

ℓ

2

R

ℓ

=

V

s

2

· R

ℓ

(R

ℓ

+ R

s

)

2

(2.1)

∂P

ℓ

∂R

ℓ

= V

s

_

1

(R

ℓ

+ R

s

)

2

−

2R

ℓ

(R

ℓ

+ R

s

)

3

_

(2.2)

∴ R

ℓ

= R

s

(2.3)

P

ℓ

= V

ℓ

I

ℓ

cos (φ) (2.4)

φ = tan

−1

_

X

s

+ X

l

R

ℓ

_

(2.5)

∴ X

ℓ

= −X

s

(2.6)

1

This theorem is often referred to as the Maximum Power Transfer theorem to avoid confusion with a

mathematical theorem of the same name. Moritz Hermann Jacobi is responsible for the former; his younger

brother, Carl Richard, stated the latter. In the mid-19

th

century, engineers (including James Prescott Joule!)

misinterpreted this theorem to imply that an electrical machine could never be made more than 50% eﬃcient

while delivering substantial power. This is, of course, false—for a ﬁxed source impedance, maximum power

is transferred into a conjugate matched load. On the other hand, diﬀerentiating equation 2.1 with respect to

Rs quickly shows that if instead the load impedance is ﬁxed, maximum power is transferred from zero source

impedance. This fact was realized by Thomas Edison or his assistant, Francis Robbins Upton, whereupon

they designed their dynamos for minimal armature resistance and realized eﬃciencies near 90%.

—24—

2.1 Resonant Impedance Analysis

2.1.2 Series-Shunt Transformation

If we are interested in the impedance of a two-element passive network only over a narrow

frequency range, it is possible to replace a series-connected network with a shunt-connected

one; to derive the new component values, simply equate the shunt and series impedances

and solve. For example, to replace a series RL network with a shunt one,

Z = R

ser

+ jωL

ser

(2.7)

=

jωL

shn

R

shn

R

shn

+ jωL

shn

=

R

shn

(ωL

shn

)

2

+ jωL

shn

R

2

shn

R

2

shn

+ (ωL

shn

)

2

(2.8)

Recalling that

Q =

ωL

ser

R

ser

=

R

shn

ωL

shn

=

1

ωR

ser

C

ser

= ωR

shn

C

shn

(2.9)

we can quickly simplify 2.7 and 2.8 to

R

shn

= R

ser

_

Q

2

+ 1

_

(2.10)

L

shn

= L

ser

_

Q

2

+ 1

Q

2

_

(2.11)

Equation 2.11 can be expressed more generally in terms of reactance:

X

shn

= X

ser

_

Q

2

+ 1

Q

2

_

(2.12)

From this we surmise that

C

shn

= C

ser

_

Q

2

Q

2

+ 1

_

(2.13)

These series-shunt equivalence relations form the basis for all resonant impedance match-

ing circuits.

—25—

Useful Techniques for Resonant Circuit Analysis

L

ser

C

ser

R

load

R

load

=⇒

(a) A series resonant circuit. At res-

onance, the reactances cancel, leaving

only the resistance R

load

.

L

ser

C

shn

R

load

(= R

ser

) R

shn

=⇒

(b) The circuit from (a) after series-

shunt transformation. Note that the

input resistance is now R

shn

.

L

ser

C

shn

R

load

(= R

shn

) R

ser

=⇒

(c) As in (b), this circuit is produced

by a series-shunt transformation. In

this case, the resulting input resistance

is smaller than before transformation.

Figure 2-2: The L-match is derived by series-shunt transformation of one element in a series

resonant circuit.

2.1.3 The L-Match

In the circuit of Fig. 2-2(a), assuming that the inductor and capacitor are at resonance, the

resistance seen across the terminals is R

load

. Transforming the capacitance via equation 2.13

to the circuit of Fig. 2-2(b) also transforms the apparent input resistance; we now see R

shn

at the input. Since we know from equation 2.10 that R

shn

must always be larger than

R

ser

, the input impedance of Fig. 2-2(b) must always be larger than that of Fig. 2-2(a). To

transform a large impedance downward into a smaller one, it is necessary to instead look

into the series port of the network, as shown in Fig. 2-2(c).

When designing an L-match, the two parameters that are generally speciﬁed are the

transformation ratio

R

shn

Rser

and the operating frequency ω. Since there are only two en-

ergy storage modes in this circuit, selecting both the transformation ratio and operating

frequency completely speciﬁes the circuit parameters

2

.

2

In principle, one could choose any two circuit parameters—Q and Lser, for example—and design the

rest of the match. Of course, this is not terribly practical, since it is not usually the case that the operating

—26—

2.2 Higher Order Matching Networks

From equation 2.10, we know that

Q =

_

R

shn

R

ser

−1 (2.14)

Some minimal algebra and equation 2.9 then produce the rest of the network:

C

shn

=

Q

ωR

shn

(2.15)

L

ser

=

QR

ser

ω

(2.16)

It is also possible to interchange the inductor and capacitor, making a high-pass L-match

instead of the low-pass matches depicted in Fig. 2-2(b) and 2-2(c). Once again, using

equation 2.9:

C

ser

=

1

ωR

ser

Q

(2.17)

L

shn

=

R

shn

ωQ

(2.18)

2.2 Higher Order Matching Networks

While theoretically the L-match allows arbitrary impedance transformations, in many prac-

tical circumstances it produces a sub-optimal solution. Since the transformation ratio ﬁxes

Q, it is not possible to select the bandwidth of an L-match arbitrarily. Moreover, extreme

transformation ratios require impractically large network Q.

To get around this limitation, it is possible to combine several L-matches, stepping from

the source impedance to one or more intermediate values and then to the load. If a very

large transformation ratio is required, the intermediate impedance(s) serve to reduce the

loaded Q necessary at each stage. On the other hand, if a very narrow bandwidth is desired,

but with only a very small change in impedance, an image resistance can be selected to

produce the appropriate overall Q. In the former case, an L-match ladder results. In the

frequency is a free parameter to be speciﬁed when designing the matching network!

—27—

Useful Techniques for Resonant Circuit Analysis

latter, an upward step is followed by a downward one (or vice-versa); such networks are

known as T- or Π-matches.

Alternatively, the designer may choose to use a tapped resonator for a matching network.

In this conﬁguration, a parallel LC resonator is tapped by splitting the capacitor or the

inductor (or both) into two series elements, then connecting the load and source across the

appropriate ports. Like the T- and Π-matches, the tapped capacitor and tapped inductor

resonator provide three degrees of freedom, while tapping both yields four.

2.2.1 The L-Match Ladder

When a very large transformation is necessary, it is often not possible to use a single L-

match stage. If, for example, the required Q is comparable to the Q

L

of the inductor to

be used, circuit performance will be substantially impaired, since in this case the series

resistance of the inductor becomes signiﬁcant. In cases such as this, a series of L-match

stages, each doing a portion of the total transformation, can be used.

In designing large L-match ladders, the issue of loss may be of particular concern. On

the one hand, continually adding more stages will inevitably result in decreasing eﬃciency;

at the same time, using fewer stages increases the required loaded Q per stage, increasing the

resonant currents and consequently the conduction losses. While the optimal solution may

change substantially depending on other constraints (e.g., required size, available component

values, and so on), it is interesting to note that in the limiting case of an extremely large

L-match ladder, the optimal transformation ratio per stage approaches a constant value

3

.

Imagine that we want to match two impedances requiring a very large transformation

ratio G. To do this, we will use N stages, each with a transformation ratio K, loaded

Q = Q

I

, and unloaded Q (that is, due to loss in the passives) of Q

u

. So

G = K

N

(2.19)

3

A similar argument is often made for bandwidth optimization in a cascade of ampliﬁers, each with a

constant gain-bandwidth product. In that case, most arguments conclude that the optimum gain is either e

(based on open-circuit time constant analysis, as in [26]) or

√

e (based on bandwidth shrinkage arguments,

as in [24]). In reality,

√

e is somewhat more accurate.

—28—

2.2 Higher Order Matching Networks

N = log

K

(G) =

ln(G)

ln(K)

(2.20)

Q

I

=

√

K−1 (2.21)

Q

I

is the loaded Q of one stage, so we know

Q

I

=

Energy stored

(Energy passed to the next stage) + (Energy lost)

(2.22)

If we assume that we are transferring much more power than we are losing (i.e., the unloaded

Q is much greater than the loaded Q), then each stage delivers approximately the total

output energy to the next stage, stores E

I

, and loses E

I,diss

, where

E

I

= E

tot

Q

I

(2.23)

E

I,diss

=

E

I

Q

u

(2.24)

The total dissipation is therefore

E

diss

=

NE

I

Q

u

= NE

tot

_

Q

I

Q

u

_

(2.25)

= E

tot

_√

K−1

Q

u

·

ln(G)

ln(K)

_

(2.26)

To minimize the loss, we diﬀerentiate with respect to K

∂

∂K

_

E

diss

E

tot

_

= −

1

2

ln(G) [Kln(K) −2K + 2]

Q

u

Kln(2K)

√

K−1

(2.27)

The mathematically inclined reader will no doubt note that the solutions to this equation

are related to the Lambert W function [27]; choosing the principally valued branch,

K ≈ 4.92 (2.28)

Q

I

≈ 1.98 (2.29)

—29—

Useful Techniques for Resonant Circuit Analysis

C

ser1

C

ser2

L

shn1

L

shn2

R

img

⇐⇒

=⇒ R

in

R

load

(a) The T-match is formed by two L-matches with the

image resistance in the shunt position. Thus, R

load

is

transformed up to Rimg and then back down to Rin.

C

ser1

C

ser2

L

shn1

L

shn2

R

img

⇐⇒

=⇒ R

in

R

load

(b) In the Π-match, the image resistance is on the series

port. R

load

is transformed down to Rimg, which is trans-

formed up to Rin.

Figure 2-3: The T- and Π-matches, composed of two L-matches, give the designer another

degree of freedom.

While in many practical cases a transformation ratio of 5 per stage is inconvenient, even

in such cases this derivation can serve as a handy rule of thumb: transformation ratios

much greater than 25 in a single stage are likely less eﬃcient than an appropriately chosen

ladder conﬁguration.

2.2.2 The T- and Π-Matches

If the L-match is unacceptable not because of an impractical transformation ratio but

because of an over-speciﬁed design, the T- and Π-matches provide a solution. Both allow

the designer an additional degree of freedom by transforming up or down to an intermediate

or image resistance and then back the other way to the desired resistance.

The T- and Π-matches are synthesized by putting two L-matches either front to front

or back to back, as depicted in Fig. 2-3(a) and 2-3(b). Design proceeds in both cases by

ﬁrst choosing (or calculating based on the imposed constraints) the image resistance, then

calculating the two resulting L-matches independently.

—30—

2.2 Higher Order Matching Networks

The equations for determining the values for the two L-matches are identical to those

in section 2.1.3. A few additional equations relate overall network Q to R

img

and to the

component values adjacent to R

img

. If we call the Q of the L-matches to the left and right

of the image resistance Q

left

and Q

right

, respectively,

Q = Q

left

+ Q

right

(the overall network Q) (2.30)

=

R

img

ω

_

L

shn1

L

shn2

L

shn1

+L

shn2

_ (for the T-match) (2.31)

=

1

ωR

img

_

C

ser1

C

ser2

C

ser1

+C

ser2

_ (for the Π-match) (2.32)

If we were instead to make low-pass networks, i.e., swap the inductors and capacitors,

Q = ωR

img

(C

shn1

+ C

shn2

) (for the T-match) (2.33)

=

ω (L

ser1

+ L

ser2

)

R

img

(for the Π-match) (2.34)

Since there is an additional degree of freedom, the designer can choose, for example, the

total shunt inductance at the center of the T-match, the overall transformation ratio, and

the operating frequency. While it’s possible to then derive an analytic expression for R

img

,

the result is truly hideous; it is almost certainly better to employ an aid such as Matlab

or to guess at the overall Q and iterate to the ﬁnal solution.

2.2.3 Tapped Capacitor Resonator

A departure from transformers based on the L-match, tapped resonators give three degrees

of freedom while allowing in some cases more reasonable component values than the T-

or Π-match. Note that for all of the tapped resonator matches, I have arbitrarily chosen

the input and output ports; as with any linear network, we can freely interchange these as

appropriate to a particular design.

The analysis of the tapped capacitor match is straightforward: convert R

load

into its

—31—

Useful Techniques for Resonant Circuit Analysis

R

in

C

1

C

2

L

shn

=⇒ R

load

Figure 2-4: The tapped capacitor match gives more freedom than the L-match and, in some

cases, more reasonable component values than the T- or Π-match.

series equivalent, then convert that series equivalent to the shunt impedance across C

1

. Of

course, one must take care to remember which Q value is used for each of the transforma-

tions.

Clearly,

R

in

R

load

=

Q

left

2

+ 1

Q

2

+ 1

(2.35)

Q =

R

load

ωL

shn

(2.36)

Q

left

= ωR

in

C

1

(2.37)

We deﬁne

R

ser

=

R

load

Q

2

+ 1

=

R

in

Q

left

2

+ 1

(2.38)

C

1,ser

= C

1

_

Q

left

2

+ 1

Q

left

2

_

(2.39)

C

equiv

=

C

1,ser

C

2

C

1,ser

+ C

2

(2.40)

This gives us another expression for the overall network Q

Q =

1

ωR

ser

C

equiv

(2.41)

To design a tapped capacitor match, ﬁrst decide which parameters will be set. For

—32—

2.2 Higher Order Matching Networks

R

in

C

shn

L

1

L

2

=⇒ R

load

Figure 2-5: The tapped inductor match is a close relative of the tapped capacitor match of

section 2.2.3.

example, we can pick the transformation ratio, frequency, and overall network Q. This lets

us use equation 2.36 to determine L

shn

. Equation 2.35 then gives a value for Q

left

, from

which equation 2.37 gives us the value for C

1

. To get the value for C

2

, we use equation 2.41.

A similar process allows us to instead choose C

equiv

or L

shn

in addition to transformation

ratio and center frequency.

2.2.4 Tapped Inductor Resonator

The tapped inductor resonator is very similar to the tapped capacitor resonator in that it

allows an additional degree of freedom over the L-match. Once again, component values for

this circuit may in some cases be more reasonable than those for other third-order matching

networks.

Analysis and design of the tapped inductor match proceeds along the same lines as the

process for the tapped capacitor network.

R

in

R

load

=

Q

left

2

+ 1

Q

2

+ 1

(2.42)

Q = ωR

load

C

shn

(2.43)

Q

left

=

R

in

ωL

1

(2.44)

Again we make some useful deﬁnitions:

R

ser

=

R

load

Q

2

+ 1

=

R

in

Q

left

2

+ 1

(2.45)

—33—

Useful Techniques for Resonant Circuit Analysis

L

1

L

2

C

1

C

2

R

in

R

load

=⇒

Figure 2-6: The double-tapped resonator gives an additional degree of freedom beyond the

third-order matching networks.

L

1,ser

= L

1

_

Q

left

2

Q

left

2

+ 1

_

(2.46)

L

equiv

= L

1,ser

+ L

2

(2.47)

Which leads us to an expression for network Q in terms of the inductors:

Q =

ωL

equiv

R

ser

(2.48)

2.2.5 The Double-Tapped Resonator

If we can tap either the capacitor or the inductor in the resonator, why not tap both?

Doing so gives us two degrees of freedom beyond transformation ratio and center frequency,

allowing us to choose, for example, total inductance and network Q.

As in the other resonator matches, R

load

goes through two series-shunt transformations

to become R

in

; in this case, however, the overall network Q is present in neither transfor-

mation, a result of the addition of another energy storage mode.

R

in

R

load

=

Q

2

left

+ 1

Q

right

2

+ 1

(2.49)

Q

left

=

R

in

ωL

1

(2.50)

Q

right

= ωR

load

C

1

(2.51)

—34—

2.3 Active Impedance Matching

Deﬁne

R

ser

=

R

load

Q

right

2

+ 1

=

R

in

Q

left

2

+ 1

(2.52)

L

1,ser

= L

1

_

Q

left

2

Q

left

2

+ 1

_

(2.53)

C

1,ser

= C

1

_

Q

right

2

+ 1

Q

right

2

_

(2.54)

Q =

ω (L

1,ser

+ L

2

)

R

ser

=

1

ωR

ser

_

1

C

1,ser

+

1

C

2

_

(2.55)

Of course, we can also say

Q

left

=

ωL

1,ser

R

ser

(2.56)

Q

right

=

1

ωR

ser

C

1,ser

(2.57)

which lets us simplify equation 2.55 slightly:

Q = Q

left

+

ωL

2

R

ser

= Q

right

+

1

ωR

ser

C

2

(2.58)

It is useful to note that

Q

left

=

_

R

in

R

load

_

Q

right

2

+ 1

_

−1 (2.59)

Q

right

=

_

R

load

R

in

_

Q

left

2

+ 1

_

−1 (2.60)

2.3 Active Impedance Matching

A system involving a dynamically changing load or source impedance may not be amenable

to the static matching networks heretofore discussed. In these cases, a dynamically ad-

justable matching network with appropriate control might allow more optimal operation.

While the fabrication of an adjustable inductor might be possible by using core satu-

—35—

Useful Techniques for Resonant Circuit Analysis

R

in

L

ser

C

shn

D

1

D

2

=⇒

V

c

R

load

Figure 2-7: Diode junction capacitances can be used to obtain a controlled L-match. A DC

voltage V

c

applied as shown controls the shunt capacitance.

ration characteristics, as in [28], such a device would almost certainly suﬀer at very high

frequencies from the eﬀects discussed in section 1.1.1. On the other hand, adjustable ca-

pacitors are readily available: the junction capacitance of a reverse-biased diode varies as

a (very nonlinear) function of voltage. The use of diodes as nonlinear capacitors is a well-

known technique; so-called varactors (shortened from “variable reactor”) are often used in

the tuning circuits of, e.g., FM receivers [24, 29].

Junction capacitance as a function of reverse voltage V

r

can be modeled as

C

j

=

C

j0

_

1 +

Vr

V

φ

_

m

(2.61)

where C

j0

is the zero-bias junction capacitance, V

φ

is the built-in potential (generally around

.5 Volts), and m is a constant determimined by the doping gradient at the junction (for an

abrupt junction, m = .5) [29].

Figure 2-7 shows one possible active matching implementation. In this circuit, two

diodes are used to ensure that one always remains reverse biased, preventing the input from

shorting to V

c

. By changing the value of V

c

, the junction capacitance of the diodes can

be changed. Since V

c

is a DC value, it might easily be supplied by a simple feedforward

network (perhaps relating the matching network’s characteristics to supply voltage) or by

the error signal from a phase-locked loop [30, 31] or delay-locked loop [32].

—36—

Chapter 3

Computational Techniques for

Nonlinear Circuits

3.1 Motivations for Computational Analysis

T

ECHNIQUES were developed in chapter 2 for the matching of linear networks with

known input and output impedances. While this is extremely useful, e.g., when

matching a power ampliﬁer to an antenna, nonlinear resonant networks present an additional

challenge: their input impedance is dependent on the conditions under which they operate.

In order to match these networks, it is necessary to establish an operating point and design

a matching network at that operating point. In many cases, however, the operating point

changes with the addition of the matching network!

In chapter 4, Fourier analysis and describing function methods are used to derive an

expression for the input impedance of a rectiﬁer circuit under speciﬁed conditions. It is

certainly possible to design a matching network using such an expression; unfortunately, this

approach is of limited use in practical designs. First, to make the Fourier analysis tractable,

idealization of the nonlinear circuit elements is required (for example, a diode might be

treated as a switch in parallel with a linear capacitor). Unfortunately, doing so reduces the

accuracy of the expression (by a substantive amount in many cases) and simultaneously

—37—

Computational Techniques for Nonlinear Circuits

makes error analysis diﬃcult. Moreover, the time spent in deriving an analytic expression

may be considerably more than is warranted, especially given the inherent inaccuracies in

the analysis.

For these reasons, the development of a more accurate and much faster computational

approach is a signiﬁcant step forward in the design of nonlinear resonant networks such

as rectiﬁers. Some hesitation to abandon pencil-and-paper engineering in favor of a com-

putational crutch is understandable; thus, in cases where back-of-the-envelope designs are

desirable, the computational approaches developed in this chapter may still be of some use.

For example, given a particular topology, curves of constant impedance versus power might

be generated and used for fast initial estimates

1

.

3.2 Nonlinear Network Impedance Considerations

When driving a nonlinear circuit, the deﬁnition of input impedance is not altogether clear.

One might choose, for example, to deﬁne the input impedance as Z

in

=

V

in

I

in

instantaneously.

It is quite likely, however, that the value of this expression would ﬂuctuate with time, since

the particular nonlinear network under consideration could produce substantial harmonic

distortion.

Recalling that under sinusoidal excitation power can only be transferred at the funda-

mental frequency, a convenient solution to this problem presents itself: for a sinusoidal drive,

the input impedance should be considered in a describing function [24, 33, 34] sense—that

is, only components of the voltage and current at the fundamental frequency contribute to

the input impedance. This solution is of particular value because almost any circuit sim-

ulation package can measure node voltages and branch currents. Once these are obtained,

the fundamental magnitudes and phases can be computationally determined via a simple

fast Fourier transform (FFT) calculation [25, 35].

Given the FFT results for input voltage and current, a linearized model of the input

1

For those who feel this verges too closely on the Red Rubber Ball school of engineering, a quick com-

parison between the results produced with Fourier/describing function analysis and those produced by

computational methods should be suﬃciently convincing.

—38—

3.2 Nonlinear Network Impedance Considerations

R

in,ω0

L

in,ω0

Z

in,ω0

=⇒

(a) Input impedance

model for positive

reactance.

R

in,ω0

C

in,ω0

Z

in,ω0

=⇒

(b) Input impedance

model for negative

reactance.

Figure 3-1: Linearized input impedance models.

impedance is easily constructed. If we call the fundamental voltage and current V

in,ω

0

and

I

in,ω

0

, respectively, then

Z

in,ω

0

=

V

in,ω

0

I

in,ω

0

(3.1)

R

in,ω

0

= ℜ{Z

in,ω

0

} (3.2)

X

in,ω

0

= ℑ{Z

in,ω

0

} (3.3)

If the reactance X

in,ω

0

is positive, then the linearized model corresponds to Fig. 3-1(a) where

L

in,ω

0

=

X

in,ω

0

ω

0

(3.4)

Otherwise, the model is represented by Fig. 3-1(b) with

C

in,ω

0

=

1

ω

0

X

in,ω

0

(3.5)

Note that we can instead represent these input impedances

2

as parallel RL or RC networks

via the transformations discussed in section 2.1.2.

Even after we have computed the input impedance via the aforementioned method, care

2

For brevity’s sake, input impedances will be assumed to be in the describing function sense when

appropriate throughout the rest of this thesis. Thus, the Rin,ω

0

notation will be dropped in favor of simply

Rin; input impedances are assumed to be at the fundamental frequency unless otherwise speciﬁed.

—39—

Computational Techniques for Nonlinear Circuits

is necessary to ensure that our calculations remain valid: from the nonlinear network’s point

of view, nothing may change. Clearly the impedance viewed from the input of the nonlinear

circuit looking back towards the source must remain the same. In addition, ensuring that

the total power throughput remains constant guarantees that the input voltage and current

to the nonlinear network do not change.

This requirement presents a particular diﬃculty when attempting to design a matching

network: if we wish to make a conjugate match between source impedance and linearized

input impedance, we must insert an appropriate matching network and at the same time

keep constant the apparent source impedance. That is, we require that looking back into

the matching network from the nonlinear network’s input we see the same impedance that

was used to calculate the linearized input impedance. Due to the linear nature of the

resonant impedance transformers we are designing, the transformation ratio looking into

the network from one side is the reciprocal of the ratio looking into the other side; thus,

in order to achieve a conjugate match at the established operating point, the calculation of

the source impedance must have been from a conjugate match in the ﬁrst place—requiring

that we knew (or were extremely lucky in guessing) the input impedance before calculating

it!

3.3 The Iterated Approach

The problem of calculating input impedance from a conjugate match can be circumvented

by iterating the calculation procedure.

3.3.1 Basic Iterated Matching

Taking as an example Fig. 3-2(a), our goal is to choose R

s

= R

i

and X

s

= −X

i

(for this

example, we assume that the input impedance looks inductive; of course, this procedure

applies equally for a capacitive input impedance). To begin, we choose a source impedance

somewhat close to the conjugate of the expected input impedance value. After simulating

the circuit and calculating the input impedance value, we set R

s

= R

i

and

1

ωCs

= ωL

i

,

—40—

3.3 The Iterated Approach

V

s

R

s

R

i

C

s

L

i

Input Impedance

(a) A conjugate match is achieved by iter-

atively selecting Rs and Cs.

V

s R

i

C

s

L

i

Input Impedance L-Match

R

s2 C

ser

L

shn

(b) After Rs and Cs are conjugate matched with Ri

and Li, a matching network can be inserted without

changing the apparent source impedance

Figure 3-2: A demonstration of the iterated impedance matching approach.

then repeat the simulation. Neglecting issues of convergence for the moment (these will

be discussed in section 3.3.3), we will arrive after several iterations at a conjugate match

between Z

s

and Z

i

.

Once the appropriate R

s

and C

s

are chosen and R

i

and L

i

calculated, a matching network

can be inserted between R

s

and C

s

. From the point of view of the source, C

s

cancels L

i

and R

i

is transformed to R

s2

, the desired source impedance. Looking towards the source,

the nonlinear network sees C

s

in series with R

s2

transformed by the matching network—the

same values used to calculated L

i

and R

i

.

3.3.2 Improved Iterated Matching

While matching has now been achieved, this circuit is not optimal: instead of utilizing the

input reactance of the nonlinear circuit, we are cancelling it and matching only the input

resistance. Not only is this a waste of usable reactance, it is also likely an eﬃciency hazard:

the use of series resonant cancellation causes large resonant currents as energy passes back

and forth between inductance and capacitance, likely resulting in additional conduction

loss.

This situation is easily remedied with judicious application of series-shunt transfor-

mations. Figure 3-3(a) shows another possible matching conﬁguration for the circuit of

Fig. 3-2(a). This time, C

s

is not explicitly present; nevertheless, the choice of appropriate

values for L

ser

and C

shn

gives an equivalent C

s

looking back from the input port of the

—41—

Computational Techniques for Nonlinear Circuits

V

s R

i

L

i

Input Impedance L-Match

R

s2

C

shn

L

ser

(a) Utilizing the input reactance of the nonlinear cir-

cuit in the matching network results in improved ef-

ﬁciency.

V

s

R

s

R

i

L

i

Input Impedance L-Match

C

ser

L

ser

(b) Analysis of the new matching network is aided by

series-shunt transformation of C

shn

and Rs2 into Cser and

Rs

Figure 3-3: An improved matching network for the circuit of Fig. 3-2(a).

nonlinear network while creating a matching network that utilizes the reactance of L

i

. To

calculate these values for a chosen R

s2

, ﬁrst transform Fig. 3-3(a) into a series network as

pictured in Fig. 3-3(b).

R

s

= R

i

(3.6)

Q

m

=

_

R

s2

R

s

−1 =

1

ωR

s

C

ser

= ωR

s2

C

shn

(3.7)

C

shn

= C

ser

_

Q

m

2

Q

m

2

+ 1

_

(3.8)

L

ser

=

1

ω

2

C

ser

−L

i

(3.9)

Looking back from the input of the nonlinear network, we see a reactance

X

s

= ωL

ser

−

1

ωC

ser

(3.10)

—42—

3.3 The Iterated Approach

= −ωL

i

(3.11)

=

1

ωC

s

(3.12)

so the nonlinear network sees the same conditions as in Fig. 3-2(a). On the other hand,

viewed from the source, all the reactances cancel, leaving just R

i

series-shunt transformed by

the matching network. Thus, a conjugate match is achieved without unnecessary impedance

cancellation.

The same method can be used to design a third-order network by ﬁrst choosing the

constraints and calculating the image resistance (R

img

for the T- and Π-matches, or R

ser

in the case of the tapped resonators). Design then proceeds by determining the half of

the matching network that transforms R

i

to the image resistance and then computing the

remaining values to transform the image resistance to the desired source resistance.

3.3.3 Convergence of the Iterated Matching Procedure

A suﬃcient (though not necessary) condition for convergence is monotonicity of the variation

of input impedance magnitude and phase with source impedance. That is, the slopes of the

source and input impedances are directly or inversely related such that a change in source

impedance always produces a change in the same direction (though not necessarily of the

same magnitude) in the input impedance. The rectiﬁers explored in chapters 4 and 5 were

empirically determined to have this property.

A more general requirement is that input impedance be a ﬁxed, deterministic function

of source impedance and power throughput. Circuits where there are several switches with

independently-determined operation such that there are multiple switching conﬁgurations

that can lead to the same behavior (such as the polyphase rectiﬁers analyzed in [36]) are

likely to be problematic. Of course, many multi-switch circuits do not have this property: a

series diode rectiﬁer with a shunt ﬂyback diode enforces a well-known relationship between

the switching behavior of the two active devices.

On the whole, it is overwhelming likely that any network consisting of only one nonlinear

—43—

Computational Techniques for Nonlinear Circuits

element will converge when using this method. In circuits with multiple switches but where

state transitions depend on a common variable this method is also likely to succeed. For

more exotic cases, convergence may depend on the initial impedance guess; in such cases,

Fourier analysis as in chapter 4 could be used in conjunction with this technique to produce

an initial guess from which iteration would likely converge on an accurate value.

3.4 SAMwIICh: An Automated Matching Implementation

For the purposes of design in the proceeding chapters and to verify the usefulness of iter-

ated impedance matching, a fully automated matching system named Software for Auto-

mated Matching with Iterated Impedance Calculations

3

(SAMwIICh) was developed. Since

SAMwIICh was developed expressly for use on the circuits discussed later, it is not com-

pletely general: it assumes that the input impedance is inductive, since in all cases of

interest this happened to be true; this is, of course, easily generalized. Full code is provided

in appendix A.

SAMwIICh uses the HSPICE circuit analysis package to simulate circuits and do FFT

analysis [37]. First, it provides an initial guess at source impedance; it then performs

the initial simulation run. From FFT data, the input impedance and its conjugate are

calculated, and the appropriate circuit elements are modiﬁed. Iteration continues until the

input impedance is matched to within the speciﬁed tolerance.

For single-diode rectiﬁers and 0.1% tolerance, fewer than ten iterations were necessary in

almost all cases. In the circuits tested, no stable limit cycles were encountered; convergence

proceeded smoothly from the initial guess to the ﬁnal value.

One possible modiﬁcation to SAMwIICh to speed convergence would be slope extrap-

olation: given the values of one or more previous iterations, guess at the ﬁnal value. This

was not implemented because it makes the system more susceptible to the eﬀects of non-

monotonicity; correcting this would require code to detect oscillations and reduce step size

3

Thanks to Jim Paris for his help in deciding on a name and for suggestions on how not to reinvent the

wheel.

—44—

3.4 SAMwIICh: An Automated Matching Implementation

or even turn oﬀ prediction entirely. Moreover, the observed convergence behavior did not

seem to warrant this modiﬁcation.

—45—

Chapter 4

The Series Resonant Rectiﬁer

T

HE FIRST topology to be considered is the series resonant rectiﬁer [19, 20, 38],

pictured in Fig. 4-1. Discussion of an analytic model of rectiﬁer operation, including

Fourier analysis of input impedance, is followed by veriﬁcation of the model by simulation

of a demonstrative design. The strengths and weaknesses of this topology as a candidate

for employment in the DC-DC converter architecture described in section 1.1.2 are then

considered. Finally, an experimental implementation is examined.

Both of the rectiﬁers considered, in this chapter and in the next, employ only one

diode. While multi-diode rectiﬁers for RF operation have been proposed [14, 15, 19], the

performance of the rectiﬁers examined was high enough that the inclusion of additional

diodes seemed unnecessary and, indeed, would likely decrease eﬃciency. Moreover, analysis

of these circuits is simpler than those involving multiple diodes, and problems of convergence

when using SAMwIICh (section 3.4) for computational analysis are seemingly nonexistent

with single-diode rectiﬁers.

4.1 Analysis of the Series Resonant Rectiﬁer

A detailed derivation of the analytic model of the rectiﬁer would be voluminous and redun-

dant; those interested in such a derivation should consult [38]. However, it will be useful

for later discussion to note Kazimierczuk and Czarkowski’s results. For the purposes of

—47—

The Series Resonant Rectiﬁer

+ +

+

+

− −

−

−

V

i

i

L

v

L

L

s

C

d

i

C

v

C

D

i

D

v

D

V

o

Figure 4-1: The series resonant rectiﬁer.

the derivation, an ideal diode with a constant parallel capacitance is assumed. In addition,

output ripple is neglected, and the circuit is assumed to be driven at the resonant frequency

1

√

LsC

d

. For ease of derivation, the diode is assumed to be oﬀ 0 ≤ ω

0

t ≤ 2π (1 −D); φ deﬁnes

the phase relationship between the input voltage and the state of the diode.

v

I

= V

i

sin(ω

0

t + φ) (4.1)

It is useful to deﬁne

V

rms

=

V

i

√

2

(4.2)

M

VR

=

V

o

V

RMS

(4.3)

i

O

= i

D

+ i

C

(4.4)

R

L

=

V

o

i

O

(4.5)

Thus,

Q =

R

L

ω

0

L

s

= ω

0

C

d

R

L

(4.6)

—48—

4.2 Fourier Analysis of Input Impedance

Z

i

R

i

L

i

=⇒

Figure 4-2: A parallel RL model for series rectiﬁer input impedance.

For 0 ≤ ω

0

t ≤ 2π (1 −D),

i

L

= i

C

=

i

O

Q

√

2M

VR

_

ω

0

t sin(ω

0

t + φ) +

_

sin(φ) −M

VR

√

2

_

sin(ω

0

t)

_

(4.7)

v

C

= v

D

= V

o

_

cos(φ) sin(ω

0

t) −ω

0

t cos(ω

0

t + φ)

M

VR

√

2

+ cos(ω

0

t) −1

_

(4.8)

v

L

=

V

o

√

2

M

VR

_

ω

0

t cos(ω

0

t + φ)

2

+

cos(φ) sin(ω

0

t)

2

+

_

sin(φ) −

M

VR

√

2

_

cos(ω

0

t)

_

(4.9)

The diode conducts during the interval 2π (1 −D) < ω

0

t ≤ 2π. During this time,

v

L

= V

o

_

√

2 sin(ω

0

t + φ)

M

VR

−1

_

(4.10)

i

D

=

i

O

Q

√

2

M

VR

_

cos(φ) −cos(ω

0

t + φ) −

M

VR

(ω

0

t −2π)

√

2

_

(4.11)

4.2 Fourier Analysis of Input Impedance

As argued in section 3.2, the condition of sinusoidal drive means that power is only trans-

ferred at the fundamental drive frequency; this means that we can once again construct a

linearized input impedance model. To model the series resonant rectiﬁer’s input impedance,

we must ﬁnd the fundamental component of input current. We can do this by applying the

Fourier integral [25] to equations 4.7 and 4.11; once again, this derivation closely follows

that of [38].

Expressing the input impedance in terms of a parllel RL circuit as in Fig. 4-2 allows

us to quickly identify the resistive component of input current. If we assume the network

—49—

The Series Resonant Rectiﬁer

is lossless, then the resistance of the parallel RL model must be the output impedance

reﬂected through the ratio of input to output voltages. That is,

R

i

=

R

o

M

VR

2

(4.12)

If the input voltage v

IN

= V

i

sin(ω

0

t + φ), then

i

IN

=

V

i

R

i

sin(ω

0

t + φ) −I

Lin

cos(ω

0

t + φ) (4.13)

We can then ﬁnd the current through the inductor by computing

I

Lin

= −

1

π

_

2π

0

i

L

cos(ω

0

t + φ)d(ω

0

t) (4.14)

=

V

i

ω

0

L

i

=

1

ω

0

L

i

V

o

√

2

M

VR

=

R

o

ω

0

L

i

i

O

√

2

M

VR

= Q

L

s

L

i

i

O

√

2

M

VR

(4.15)

After a substantial amount of math, we arrive at the ratio

L

s

L

i

=

1

π

_

π(5D−1)

4

−a · sin

2

(φ) −b · cos

2

(φ)+

+ c · sin(φ) cos(φ) +

M

VR

√

2

[d · sin(φ) + e · cos(φ)]

_

(4.16)

where

a =

_

3

8

cos(2πD) −

π(1 −D)

2

sin(2πD)

_

sin(2πD) −

π(1 −D)

2

(4.17)

b = sin(2πD) −

5

16

sin(4πD) −

π(1 −D)

2

cos

2

(2πD) (4.18)

c = [1 −cos(2πD)] cos(2πD) +

π(1 −D)

2

sin(4πD) (4.19)

d = 2πDcos(2πD) −π(1 −D) −

_

1 +

cos(2πD)

2

_

sin(2πD) (4.20)

e = 1 −cos(2πD) +

_

sin(2πD)

2

−2πD

_

sin(2πD) (4.21)

—50—

4.2 Fourier Analysis of Input Impedance

As mentioned previously, this derivation makes two signiﬁcant assumptions: ﬁrst, that

the diode is ideal, and second, that the capacitance across the diode is constant over a cycle.

At radio frequencies, it is unlikely that we would put additional capacitance in parallel with

the diode, electing instead to use the junction capacitance of the diode to provide C

d

.

Recalling from section 2.3 that diode junction capacitance is a strong function of voltage,

it is clear that some care is needed in choosing the appropriate capacitance value.

In order to make use of our analysis with a nonlinear capacitance, we will assume that we

must replace the linear capacitor with a nonlinear capacitance that stores the same average

energy each cycle. Preserving the average stored energy keeps the resonant operation closest

to the behavior predicted by the model, since it preserves average inductor current, thus

preserving average output current. Since we have ﬁxed the output voltage of the circuit for

the purpose of analysis, preserving average output current keeps output power constant.

Moreover, as power is only transferred at the fundamental frequency, keeping output power

constant means that the input characteristics at the driving frequency are unchanged. Thus,

macroscopic operation of the circuit is preserved

1

.

To calculate a ﬁrst-order estimate of the equivalent linear capacitance for a given

diode, the voltage waveform from equation 4.8 is applied to the capacitance function in

equation 2.61. This produces capacitance as a function of time, from which energy is

quickly calculated:

E(t) =

C(t) [V(t)]

2

2

(4.22)

The equivalent capacitance is then easily found:

C

equiv

=

E(t)

[V(t)]

2

(4.23)

Note that this derivation assumes that the addition of a nonlinear capacitance does

not change the voltage waveform across the diode. While this assumption is not completely

1

Further discussion of the use of nonlinear capacitance in resonant radio frequency circuits can be found

in [39, 40].

—51—

The Series Resonant Rectiﬁer

accurate, it is nevertheless reasonable for a ﬁrst-order estimate. Precise derivation of voltage

waveforms can be found in [39–41].

4.3 Comparison of Analytic Model with Simulation

In order to determine the usefulness of the analytic model, a rectiﬁer circuit will be designed

by the process described in [38] and then simulated. Predicted input impedance and output

power will be compared to simulated results.

Since the circuit parameters are easiest to determine at D = .5, we will choose this

operating point for our test case. The rectiﬁer will run at 100 MHz and provide 5 W into

5 V, meaning that R

o

= 5 Ω. From [38] page 105, D = .5 gives

Q ≈ .3884 (4.24)

M

VR

≈ .3684 (4.25)

Thus,

V

i

=

V

o

√

2

M

VR

= 19.19 V (4.26)

The necessary inductance and capacitance are

L

s

=

R

o

ω

0

Q

= 20.5 nH (4.27)

C

d

=

Q

ω

0

R

o

= 123.6 pF (4.28)

The analytic model predicts that

L

i

= 16.42 nH (4.29)

R

i

= 36.83 Ω (4.30)

Q = 3.6 (4.31)

—52—

4.3 Comparison of Analytic Model with Simulation

Table 4.1: Input impedance, output power, and eﬃciency, calculated versus simulated.

Parameter Calculated

Simulated,

Ideal Diode

Simulated,

Real Diode

Simulated,

Conjugate Match

Po 5 W 4.99 W 4.95 W .66 W

Ri 36.83 Ω 38.86 Ω 33.5 Ω 3.78 Ω

Li 16.42 nH 15.72 nH 16.02 nH 6.6 nH

η 100% 100% 89.2% 91.3%

or, for the series RL model,

L

i,ser

= 15.12 nH (4.32)

R

i,ser

= 2.64 Ω (4.33)

Table 4.1 compares the computed results with those obtained in three HSPICE sim-

ulation runs (netlists for these simulations are available in appendix B.1). In the ﬁrst

simulation, an ideal diode in parallel with a linear capacitor was employed. In the second,

the ideal diode was replaced by a real diode model, though still with a linear capacitance.

Finally, in the third simulation, the rectiﬁer was driven from a conjugate match. As ex-

pected, the input impedance of the rectiﬁer changed substantially with the addition of

source impedance, resulting in severely reduced power throughput. The slight increase in

eﬃciency is a result of reduced conduction loss because of lower average output current;

this is an illusory improvement, since we have sacriﬁced almost a factor of ten in output

power in order to gain two percent “improvement” in eﬃciency.

The results of the third simulation highlight the need for a model including an arbitrary

source impedance, which would allow the input impedance to be calculated for a conju-

gate match as described in section 3.2. This idea is unattractive for two reasons: ﬁrst,

the precision of the calculations for a range of real diodes is likely to be poor, and second,

the eﬀort involved in this calculation would only be useful for a single topology—parasitics

would require explicit consideration and would complicate the model considerably. A more

—53—

The Series Resonant Rectiﬁer

+

−

V

i

L

s

L

shn

C

d

D

V

o

Figure 4-3: To provide a DC current path, all or part of L

s

can be transformed into L

shn

.

attractive alternative has already been suggested in section 3.3, to wit, the iterated com-

putational approach. Design can proceed much more quickly without the need for special

provisions for nonlinear capacitance, diode drop, and passive component loss, none of which

the analytic model considers. Moreover, a computational approach can take into account

additional parasitics (such as those present on a printed circuit board) with only the eﬀort

required to modify the circuit description ﬁle.

4.4 Application of the Series Resonant Rectiﬁer

As demonstrated in section 4.3, the performance of the series resonant rectiﬁer is good when

applied under appropriate conditions: eﬃciencies approaching 90% were obtained using a

realistic model of diode loss. As argued in section 4.2, the use of a nonlinear capacitor

should not change circuit operation substantially; thus, the series rectiﬁer is a design with

signiﬁcant practical potential.

One limitation of the resonant rectiﬁer not yet discussed is that it must be driven from

a low DC impedance. This may cause problems in some applications, e.g., when driven by

a class-E inverter topology employing a series resonant output tank; in such cases, there is

no path for DC current to ﬂow to the output. This limitation can easily be overcome in

practice by transforming all or part of L

s

to its shunt equivalent as illustrated in Fig. 4-3;

since there is now a path for DC output current through the shunt inductor, a source with

high DC impedance can be used.

—54—

4.5 Experimental Implementation

+

−

V

i

L

shn

L

pkg

C

d

C

out

V

out

D

Figure 4-4: Experimental implementation of the series rectiﬁer.

Since this topology involves resonant operation, the reverse voltage stress on the active

device is quite high, requiring the use of diodes with high reverse voltage ratings to withstand

the voltage developed on C

d

each cycle. Going from a low voltage diode to one with a higher

reverse voltage rating has some practical eﬀects worth considering: in most cases, high

reverse voltage rating is achieved with the addition of guard rings or with a metal-overlapped

laterally-diﬀused process (see [41] and references therein). Both of these processes have the

eﬀect of reducing junction capacitance, since the diode is eﬀectively placed in series with

its guard structure. Unfortunately, these structures also tend to increase forward drop,

reducing eﬃciency

2

.

As an alternative to using high-voltage devices, topologies might be derived from the

series resonant rectiﬁer which exploit the multi-resonant structures designed and imple-

mented in [42]. Using such techniques, resonant operation can be utilized with reduced

voltage stress, since higher harmonic content is used to achieve square switching wave-

forms. Topologies of this nature would allow greater device utilization and enjoy enhanced

eﬃciency, since lower voltage diodes (with lower forward drops) could be employed.

4.5 Experimental Implementation

The series resonant rectiﬁer was implemented in the DC-DC converter in [10]. Fig. 4-4

shows the rectiﬁer as implemented, with component values and part numbers listed in

2

In some designs, the selection of a high voltage diode to obtain the junction capacitance prescribed by

the analytic model could cause a reduction in eﬃciency. In this case, the computational model is of great

assistance, since it may be applied to designs which utilize the increased capacitance of a lower voltage diode.

—55—

The Series Resonant Rectiﬁer

Table 4.2: Component values used in the series rectiﬁer experimental implementation.

Circuit Element Nominal Value Part Number

D MBRS1540T3

L

pkg

1 nH Diode package parasitic

C

d

Cj0 = 318.5 pF Diode junction capacitance

L

shn

12.5 nH Coilcraft A04TJ

Cout 9 × 47 nF X7R Ceramic, 50 V

Table 4.2. Overall eﬃciency of the radio frequency power converter cell was greater than

75% from 16 V DC input to 5 V DC output. Rectiﬁcation eﬃciency was around 85%; the

discrepancy between experimental eﬃciency and that calculated in section 4.3 is likely a

result of ﬁnite inductor Q.

As discussed in section 1.1.2, in addition to high eﬃciency and well-characterized input

impedance, a high DC output impedance is extremely important to ensure proper current

sharing between parallel converters. Simulation results (netlist provided in appendix B.2)

suggests that output impedance ranges from 20 Ω at light load to 5 Ω at maximum load. In

the experimental implementation, the output current of eight parallel cells under maximum

load was matched to within ±6.5% of average.

—56—

Chapter 5

The Shunt Resonant Rectiﬁer

T

HE SECOND topology considered is the shunt resonant rectiﬁer [7, 18, 19]. This

rectiﬁer, pictured in Fig. 5-1, employs a diode in the shunt position; it is in essence

the dual of the traditional class-E architecture [16, 43].

This chapter proceeds in much the same fashion as the previous one: an analytic model

is developed and compared to simulation, practical concerns are discussed, and an experi-

mental implementation is presented. In addition, the use of the coupled magnetic structures

similar to those presented in [21, 22] is examined, accompanied by simulation and experi-

mental results.

5.1 Analysis of the Shunt Resonant Rectiﬁer

The shunt resonant rectiﬁer is essentially the dual of the traditional class-E inverter. Stated

more precisely, the shunt rectiﬁer as analyzed here is the bilateral inverse of the class-

V

i

C

ser

L

ser

L

choke

D C

d

C

out

V

o

v

D

i

O

+

+

−

−

Figure 5-1: The shunt resonant rectiﬁer.

—57—

The Shunt Resonant Rectiﬁer

E circuit [44]. Since this means that the rectiﬁer operating waveforms are exactly time-

reversed copies of the class-E waveforms, analysis of this circuit is easily obtained by slight

modiﬁcations to the standard class-E inverter analysis. A particularly good analysis of the

class-E inverter, and the one from which the following is derived, appears in [45].

As required by bilateral inversion, the rectiﬁer duty cycle D = (1 − D

inverter

). Hence,

following [45], we deﬁne

v

I

= V

i

sin(ω

0

t + φ) (5.1)

tan(φ) =

sin(y)

y

−cos(y)

ξy

π

cos(y) −

_

1 +

ξ

π

_

sin(y)

(5.2)

y = πD (5.3)

ξ =

1

V

o

dv

D

dθ

(5.4)

where the conduction angle y is centered at ω

0

t =

π

2

, and φ deﬁnes the phase between the

input voltage and the state of the diode. Assuming L

choke

is large, the output current is

approximately constant, so

I

o

= i

O

≈ i

O

(5.5)

P

o

= V

o

I

o

(5.6)

R

o

=

V

o

I

o

(5.7)

r =

2R

o

g

2

(5.8)

g =

y

cos(φ) sin(y)

(5.9)

V

i

≈ V

o

_

2

g

_

(5.10)

The susceptance of C

d

is given by

B = ω

0

C

d

=

2

_

y

2

+ yg sin(φ −y) −g sin(φ) sin(y)

_

πg

2

r

(5.11)

—58—

5.1 Analysis of the Shunt Resonant Rectiﬁer

The input tank components, C

ser

and L

ser

, are given by

C

ser

=

1

ω

0

Qr

(5.12)

L

ser

=

(Q + tan(ψ)) r

ω

0

(5.13)

ψ represents the additional reactance angle which eﬀectively cancels C

d

, and is given by

tan(ψ) =

ω

1

sin(φ) + ω

2

cos(φ) + ω

3

cos(2φ) + gy

ω

2

sin(φ) + ω

3

sin(2φ) −ω

1

cos(φ)

(5.14)

where

ω

1

= −2g sin(φ −y) sin(y) −2y sin(y) (5.15)

ω

2

= 2y cos(y) −2 sin(y) (5.16)

ω

3

= −g sin(y) cos(y) (5.17)

These equations allow the design of a shunt rectiﬁer for a given Q, ξ, D, V

o

, and

P

o

. Whereas in the design of RF ampliﬁers, Q might be chosen for, e.g., output spectral

purity, in this case Q is in practice generally chosen such that the input tank serves as the

impedance matching network after a suitable series-shunt transformation of one of the tank

elements.

The derivation of an analytic expression for input impedance is not presented, since it

was shown in the previous chapter that such an expression is of little practical value. Were

such an expression desirable, a procedure largely similar to the one in section 4.2 could be

used. It is unlikely, however, that such a model would fare well in the face of nonidealities

and unmodeled parasitics.

—59—

The Shunt Resonant Rectiﬁer

Table 5.1: Output power and eﬃciency, calculated versus simulated.

Parameter Calculated

Simulated,

Ideal Diode

Simulated,

Real Diode

Po 5 W 5 W 1.12 W

η 100% 100% 89.7%

5.2 Comparison of Analytic Model with Simulation

To verify that the analytic model derived in section 5.1 is valid, we will design a rectiﬁer to

the same speciﬁcations as in section 4.3: V

o

= 5 V, P

o

= 5 W, D = .5, f

0

= 100 MHz.

We choose ξ = 0, since in practice optimal eﬃciency is obtained at this point [45], and

arbitrarily select Q = 5. The design equations yield

φ = −0.5669 (5.18)

g = 1.862 (5.19)

r = 2.884 (5.20)

B = .06366 (5.21)

ψ = .8561 (5.22)

We then calculate

C

d

= 101.32 pF (5.23)

C

ser

= 110.4 pF (5.24)

L

ser

= 28.24 nH (5.25)

V

i

≈ 5.4 V (5.26)

Table 5.1 compares calculated values for output power and eﬃciency to simulation re-

sults with an ideal diode and with a diode model that accounts for forward drop but still has

—60—

5.3 Application of the Shunt Resonant Rectiﬁer

a constant junction capacitance (HSPICE netlists are provided in appendix B.3). While the

ideal diode gives reasonable results, the use of the more realistic diode model is problematic.

This likely results from the fact that the diode forward drop is considerable compared to

the diﬀerence between V

i

and V

o

. Once again, the value of a computational approach is

highlighted by the shortcomings of the analytic model.

5.3 Application of the Shunt Resonant Rectiﬁer

Unlike the series resonant rectiﬁer, the shunt resonant rectiﬁer provides its own DC cur-

rent path. Hence, it is tolerant of a range of input impedances without modiﬁcation. As

mentioned earlier, however, shunt transformation of one of the elements of the input tank

is likely still desirable, since the input tank can then be used to interface the source and

input impedances. When using the input tank elements in this way, the designer no longer

has a choice of Q, since it is ﬁxed by the ratio of source to load impedance.

The analysis of section 5.1 makes the assumption that a “large” choke inductor is used

and ignores the choke inductor thereafter. In practice, the size of the choke inductor is

dictated by ripple requirements, and it is generally desirable to make it as small as possible

for a given application. While the analytic model is tolerant of some amount of ripple, it is

unlikely that model accuracy will be good with a current ripple that is greater than 10% of

DC output current; in such cases, the computational approach is certain to be preferable.

Also neglected in the foregoing analysis is any package inductance appearing in series

with the diode. It is convenient when considering the package inductance to break the

circuit into two loops: the AC loop, including the input tank and C

d

, and the DC loop,

containing the diode, L

choke

, and the load. Practically, the addition of an inductance in

series with the diode has two eﬀects: ﬁrst, it appears in series with C

d

when the diode is

oﬀ, adding with L

ser

and resulting in a larger eﬀective tank inductance; second, since it

appears in both the AC and DC loops, it has the eﬀect of coupling additional ripple into

the output. Section 5.5 explores the latter eﬀect in detail, including its mitigation through

the use of coupled magnetic structures of the kind described in [21, 22].

—61—

The Shunt Resonant Rectiﬁer

+

−

V

s

R

m

C

c

L

ser

D C

d

C

out

L

choke

V

o

(a) First, the input tank is replaced by Lser ≈

2

ω

0

2

C

d

, and Rm and

Cc are determined by iterated computation.

+

−

V

s

R

m

C

m

L

m

L

ser

D C

d

C

out

L

choke

V

o

(b) Next, Cc is replaced with a series transformed L-match comprising Cm

and Lm.

+

−

V

s

R

s

C

shn

L

tot

D C

d

C

out

L

choke

V

o

(c) Finally, Rm and Cm are shunt transformed and Lm and

Lser are combined into Ltot.

Figure 5-2: The computationally-assisted design process for the shunt resonant rectiﬁer.

When using iterated computation to design the shunt resonant rectiﬁer, it is convenient

to replace the input tank with only an inductance having a reactance approximately twice

that of C

d

; after computing the matching parameters, the matching network serves as the

input tank. Figure 5-2 illustrates the procedure for computing the appropriate matching

network values. First, determine R

m

and C

c

by iteration such that they form a conjugate

match with the rectiﬁer circuit (Fig. 5-2(a)). Next, following the procedure outlined in

section 3.3.2, an L-match which has been series transformed can be inserted in the place of

C

c

(Fig. 5-2(b)). The ﬁnal design is reached by shunt transforming C

m

into C

shn

and R

m

into R

s

, and combining L

m

and L

ser

into L

tot

(Fig. 5-2(c)).

—62—

5.4 Experimental Implementation

+

−

V

i

R

s

19

40

λ

Z

0

C

shn

L

ser

L

pkg

D C

d

L

choke

C

out

V

o

Figure 5-3: Experimental implementation of the shunt rectiﬁer.

Table 5.2: Component values used in the shunt rectiﬁer experimental implementation.

Circuit Element Nominal Value Part Number

D 20CJQ060

L

pkg

2 nH Diode package parasitic

C

d

Cj0 = 145 pF Diode junction capacitance

C

shn

56 pF CDE MC12FA560J

Lser 39 nH Coilcraft 1812SMS-39NJ

L

choke

120 nH Coilcraft 1812SMS-R12J

Cout 9 × 47 nF X7R Ceramic, 50 V

Rs 50 Ω Ampliﬁer output impedance

Z0 51.5 Ω Belkin 8240 RG-58A/U coax, 95 cm

5.4 Experimental Implementation

To verify the results of section 5.1 and the application of iterative matching as described

in section 5.3, a test rectiﬁer was implemented. The rectiﬁer provides 3.3 W into 5 V from

a 100 MHz sinusoidal excitation. Radio frequency input was provided by a General Radio

Company Model 1363 VHF Oscillator with a Model 1264-B Modulating Power Supply

1

driving an Ampliﬁer Research Model 10W1000 power ampliﬁer [47], and the rectiﬁer was

loaded with ﬁfteen 1 W, 5.1 V Zener diodes in parallel with a bulk capacitance comprising

two 15 µF tantalum capacitors. Figure 5-3 illustrates the rectiﬁer implementation, with

component values listed in Table 5.2. The transmission line at the input of the rectiﬁer

1

Due to the age of the General Radio equipment and the circumstances under which this unit was

obtained (I found it abandoned in a hallway!), no manual or other reference is available. It is worth noting

that, in addition to producing all manner of RF signal and noise generators, the General Radio Company

invented the Variac variable autotransformer. More information on this very interesting company can be

found in [46].

—63—

The Shunt Resonant Rectiﬁer

models the coaxial cable used to connect it to the ampliﬁer.

An HSPICE netlist of the rectiﬁer circuit is provided in appendix B.4. Simulated and

experimental results are well matched: the rectiﬁer provided 3.32 W at 4.97 V with nearly

80% eﬃciency.

5.5 Parasitic Mitigation in the Shunt Rectiﬁer

In the series resonant rectiﬁer, both of the principal parasitics of the diode (C

j

and L

pkg

)

are employed by the topology. While the shunt rectiﬁer still uses C

d

, L

pkg

is not present in

the ideal circuit representation, and it is ignored by the analytic development in section 5.1.

As brieﬂy mentioned in section 5.3, L

pkg

has two main eﬀects: ﬁrst, it adds to L

ser

and

acts as part of the AC loop while the diode is oﬀ. When the diode is conducting, L

pkg

appears in the DC loop, which has the additional eﬀect of coupling additional AC current

into the output, increasing output voltage ripple. Techniques have been described in [21, 22]

that can be used to move inductance from one branch to two adjacent branches. This is

achieved by the use of coupled magnetic structures which produce an equivalent T network

having negative inductance in one branch.

For a design of the kind presented in section 5.4, a center tapped magnetic structure

is a good choice, since it produces more inductance cancellation for a given size than an

end tapped structure [21, 22]. Thus, we will consider exclusively the use of center tapped

magnetics. In a center tapped structure, the two physical inductances L

1

and L

2

appear in

the positive branches of the equivalent T network. The negative branch of the network has

a value equal to −L

M

, the negative mutual inductance between L

1

and L

2

.

Application of coupled structures to the shunt rectiﬁer results in the circuit depicted in

Fig. 5-4. The magnetic structure is designed such that the mutual inductance cancels all

or part of L

pkg

, while L

1

and L

2

add to L

ser

and L

choke

, respectively. In some designs, one

or both of the latter can be entirely contained in the transformer structure. The use of this

technique allows the designer to reverse the eﬀect of L

pkg

in coupling the AC and DC loops

and eliminate consequent increases in output ripple.

—64—

5.5 Parasitic Mitigation in the Shunt Rectiﬁer

+

−

V

i

R

s

C

shn

L

ser

L

1

−L

M

L

pkg

C

d

D

L

2

Coupled

Magnetic

Structure

L

choke

C

out

V

o

Figure 5-4: The shunt resonant rectiﬁer with coupled magnetics for parasitic mitigation.

PSfrag

+

−

V

i

R

s

19

40

λ

Z

0

C

shn

L

ser

L

pkg,eﬀ

D C

d

L

choke

C

out

V

o

Figure 5-5: Experimental implementation of the shunt rectiﬁer with parasitic mitigation.

While it seems that complete cancellation of L

pkg

should result in minimum ripple at the

output, simulation and experimentation both show that there is a particular (nonzero) value

for which output ripple is minimized. This minimization is a result of higher harmonics

generated by the interaction between the series combination L

pkg

− L

M

= L

pkg,eﬀ

and C

d

.

For the optimal value of L

pkg,eﬀ

, these harmonics are phased such that peak-to-peak AC

ripple is minimized.

To test the eﬀect of inductance cancellation, several rectiﬁers incorporating varying

amounts of cancellation were simulated, designed, and built. For comparison, a matching

rectiﬁer design without inductance cancellation was also built. All rectiﬁers were designed

to provide 8 W into 5 V from a 100 MHz RF source. The rectiﬁers were driven and loaded

in precisely the same manner as in section 5.4. Figure 5-5 shows the experimental rectiﬁer

circuit; component values are listed in Table 5.3. In all cases, coupled magnetic structures

—65—

The Shunt Resonant Rectiﬁer

Table 5.3: Component values used in the experimental implementation of the shunt rectiﬁer

with parasitic mitigation.

Element LM = 0 LM = 3.5 nH LM = 4.0 nH LM = 4.6 nH LM = 6.3 nH

D 1N5822

L

pkg,eﬀ

6.5 nH 3 nH 2.5 nH 1.9 nH 0.2 nH

C

d

Cj0 = 548 pF

C

shn

138 pF (82 pF and 56 pF)

CDE MC12FA560J and CDE MC12FA820J

Lser 12.5 nH 13.5 nH 16.1 nH

Coilcraft A04TJ L1 of coupled structure

L

choke

120 nH 135 nH 140 nH

Coilcraft 1812SMS-R12J Coilcraft 1812SMS-R12J and L2 of coupled structure

Cout 9 × 47 nF X7R Ceramic, 50V

Rs 50 Ω ampliﬁer output impedance

Z0 51.5 Ω Belkin 8240 RG-58A/U coax, 95 cm

Table 5.4: Experimental results for shunt rectiﬁers with parasitic mitigation.

Parameter No Cancellation LM = 3.5 nH LM = 4.0 nH LM = 4.6 nH LM = 6.3 nH

Po 8 W

L

pkg,eﬀ

6.5 nH 3 nH 2.5 nH 1.9 nH 0.2 nH

Vrip,pp, measured 38 mV 18 mV 16 mV 20 mV 27 mV

Vrip,pp, adjusted 38 mV 20 mV 18 mV 22 mV 32 mV

were implemented on printed circuit board traces as described in [22]. The scripts used to

generate the circuit board are available in appendix C.

Simulation results suggested that L

pkg,eﬀ

= 2.5 nH should give the greatest reduction

in output ripple (an HSPICE netlist for these simulations can be found in appendix B.5).

As evidenced by Table 5.4, experimental ﬁndings agree with the results of simulation. Note

that L

choke

was larger for the cases with inductance cancellation, since L

2

from the coupled

magnetic structure appeared in series with the Coilcraft 1812SMS-R12J. Thus, adjusted

ripple ﬁgures which account for the discrepancy in choke inductance are listed along with

measured values in Table 5.4.

In the best case, L

pkg,eﬀ

= 2.5 nH, L

choke

was reduced to a total of 54 nH (including L

2

)

while maintaining ripple performance comparable to the uncancelled case. This strongly

—66—

5.5 Parasitic Mitigation in the Shunt Rectiﬁer

suggests that the application of coupled magnetic structures may in many cases be of great

beneﬁt in terms of total required ﬁlter size.

An eﬀect of using coupled magnetic structures not considered before implementation

was an increase in EMI susceptibility. In particular, all three cases in which inductance

cancellation were employed displayed a marked increase in ripple when pointed broadside

to a strong source of EMI at ω

0

(in this case, the power ampliﬁer used to drive the test

circuits). Ripple ﬁgures in Table 5.4 were measured with the circuit raking the EMI source

(that is, the principal component of ﬂux linked by the PCB inductors was perpendicular to

the ﬂux emitted by the EMI source).

It is likely that this enhanced EMI susceptibility arises as a result of the much greater

enclosed area of the PCB inductors compared to the Coilcraft inductors employed in the

rectiﬁer without inductance cancellation. While the diameter of the Coilcraft A04TJ is

approximately 3.1 mm, the PCB inductors had diameters of 7.1 mm, 7.6 mm, and 8.1 mm

(L

M

= 3.5 nH, 4.0 nH, and 4.6 nH, respectively). Another likely factor is that the Coilcraft

inductor was located substantially closer to a ground plane than the inductors implemented

in PCB traces (appendix D gives detailed PCB layouts for both the cancelled and non-

cancelled cases). This eﬀect is by no means a fundamental problem with inductors fabricated

on a PCB. In fact, the implementation of multilayer toroidal PCB magnetics or self-shielded

components as in [42] would likely prove a substantial boon to those wishing to manufacture

integrated passive components using PCB fabrication techniques.

—67—

Chapter 6

Conclusion

6.1 Thesis Summary

T

HE PRINCIPAL eﬀort of this thesis is the development of design and character-

ization methods for rectiﬁer topologies amenable to use in the new architectures

proposed in [10]. A computational design approach allowing fast and accurate circuit anal-

ysis and synthesis is developed and applied, along with traditional analysis, to two demon-

strative rectiﬁer topologies. In addition, the application of coupled magnetic structures for

parasitic mitigation is considered. Experimental implementations are investigated to verify

analytic and computational results.

This thesis is divided into six chapters, including this conclusion.

Chapter 1 introduces background material and presents motivations for the development

of new architectures for DC-DC power conversion.

Chapter 2 reviews analytic techniques useful in linear resonant circuit analysis, and

demonstrates the application of these techniques to the analysis and design of resonant

impedance transformers.

Chapter 3 introduces the use of computational modeling for nonlinear circuit analysis.

In this chapter, algorithms are developed that allow for extremely fast design of rectiﬁer

circuits and which pave the way for the analyses performed in the proceeding chapters.

—69—

Conclusion

Chapter 4 discusses the ﬁrst of two resonant rectiﬁer topologies, exploring the design and

implementation process of the series resonant rectiﬁer. Chapter 4 comprises a discussion

of analytic models including Fourier and describing function analysis of input impedance,

a comparison of the analytic models with simulation, and a discussion of the strengths and

weaknesses of the series resonant topology. Experimental results are also discussed.

Chapter 5 covers another topology, the shunt resonant rectiﬁer. In addition to a dis-

cussion of analytic models and simulated results, the exploration of the shunt topology is

extended by application of coupled magnetic structures in the rectiﬁer, allowing the mitiga-

tion of undesired parasitic eﬀects. Implementations of rectiﬁers with and without parasitic

mitigation are presented.

6.2 Thesis Conclusions

There are two main conclusions that can be drawn from this thesis. First, while analytic

models of nonlinear resonant circuits are useful for developing an understanding of circuit

operation, the crude models generally discussed are wholly inadequate for practical designs.

Moreover, the eﬀort involved in extending these models to account for nonidealities is so

great as to motivate the search for an alternate approach. The computational design ap-

proach presented herein fulﬁlls all practical design requirements while allowing the designer

to proceed from speciﬁcation to synthesis in a fast and accurate manner. It is anticipated

that the development of more general computational approaches will allow even greater

speed and accuracy for large classes of nonlinear resonant circuits.

The second conclusion is that the application of integrated, batch fabricated passive

components, both to replace existing passives and to enhance circuit performance through,

e.g., parasitic mitigation, has great potential. Substantial cost reduction can be realized

through the elimination of discrete passives in favor of components integrated on printed cir-

cuit boards. In addition, circuit performance can be enhanced and passive size requirement

reduced through the judicious application of integrated magnetic and resonant structures.

—70—

6.3 Recommendations for Future Work

6.3 Recommendations for Future Work

Two principal improvements to the work here should be investigated. First, generalization of

the computational techniques presented in chapter 3 is needed. Armed with such techniques,

designers could realize a range of circuit topologies with great speed and accuracy. Moreover,

the development of these techniques in parallel with similar methods for the design of

integrated passive components will allow power converter technologies to take advantage of

the beneﬁts of batch fabrication.

In all simulated and experimental circuits presented, diode conduction loss was the domi-

nant mechanism contributing to degraded eﬃciency. To circumvent this loss, investigation of

synchronous rectiﬁcation techniques is necessary. Such techniques would likely resemble the

shunt rectiﬁer implementation of chapter 5, since this allows the use of a ground-referenced

switch. With the use of self-resonant gate drives of the type presented in [10], the gating

losses inherent in synchronous rectiﬁer designs could be made insigniﬁcant compared to the

conduction loss savings realized by the elimination of diode forward drop.

The new architectures presented in [10], combined with accurate computational model-

ing and highly integrated passive components, promise dramatic increases in performance

and, simultaneously, radical reductions in the cost of DC-DC power conversion systems.

—71—

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—76—

Appendix A

SAMwIICh Code Listings

This appendix consists of code listings for the SAMwIICh system. SAMwIICh uses a

combination of perl scripts [48], bash scripts [49], and Makeﬁles [50].

A.1 Makefile

Using a Makeﬁle makes everything easier (sorry, pun intended).

WORKDIR := $(shell basename $$PWD)

CALCOPTS = −V −C

all: lis imp pwr

5

lis: $(WORKDIR).lis

imp: $(WORKDIR).imp

10 pwr: $(WORKDIR).pwr

clean:

rm −f *.lis *.imp *.pwr *.st0 *.tr0 *.mt0 *.ipp

15 %.imp: %.lis . ./bin/impcalc.pl . ./bin/impextract.sh

. ./bin/impextract.sh $< $@ | perl . ./bin/impcalc.pl $(CALCOPTS) | tee $@

%.pwr: %.lis . ./bin/eﬀcalc.pl . ./bin/eﬀextract.sh

. ./bin/eﬀextract.sh $< $@ | perl . ./bin/eﬀcalc.pl | tee $@

20

%.lis: %.sp values.dat

hspice $< | tee $@

—77—

SAMwIICh Code Listings

A.2 automatch.pl

This is the heart of SAMwIICh; it dispatches all the simulation jobs and sets up component

values for the next iteration.

#!/usr/bin/perl

use Getopt::Std;

my %opts;

5 getopts(’r:c:v:l:d:m:’, \%opts);

# get the name of the directory. Everything else

# should have this name, too

$PWNAM = ‘basename $ENV{’PWD’}‘;

10 chomp $PWNAM;

# set up utility variables

$done = 0;

$maxiter = 15;

15 $TOLER = .002;

# the component values for the ﬁrst iteration

$nextr = $opts{’r’} | | 6;

$nextc = $opts{’c’} | | 2e−9;

20 $vin = $opts{’v’} | | 9;

$ℓser = $opts{’l’} | | 10e−9;

$ℓdio = $opts{’d’} | | 6e−9;

$ℓmut = $opts{’m’} | | 0;

25 # set the ﬁrst round of values

open(VALS,">values.dat") or die "Could not set R and C values: $!";

print VALS join(’ ’, ($nextr, $nextc, $vin, $ℓser, $ℓdio, $ℓmut)), "\n";

close(VALS);

30 # until $done is true or if we do too many iterations

while ((!$done) && ($maxiter−− > 0))

{

# clean up

‘make clean‘;

35 # do the body of calculations

# hspice is called from the makeﬁle

‘make CALCOPTS="-V -C" imp‘;

# read in the impedance values

open(IMP, "<".$PWNAM.".imp");

40 ($mag, $rvaℓ, $xvaℓ, $inx, $inxc) = split(’ ’, <IMP>);

close(IMP);

# we match assuming that we’re cancelling inductance with capacitance

# and then adding a high-pass L-match.

45 if ($inxc =˜ /H/)

{

# oops! the input looks capacitive for some reason. . .

—78—

A.3 matching.sp

$done = 1;

undef $nextc;

50 undef $vin;

undef $ℓser;

undef $ℓdio;

undef $ℓmut;

$nextr = "*ERROR: Input looks capacitive!*";

55 }

# OK, things are looking good

else

{

# how much have things changed from the last run?

60 $rtoℓer = abs((abs($nextr)−abs($rvaℓ))/$rvaℓ);

$ctoℓer = abs((abs($nextc)−abs($inxc))/$inxc);

# show the user what’s going on

print "$nextr => $rval ($rtoler); $nextc => $inxc ($ctoler)\n";

65

# if we’re within $TOLER, we’re done

($done = 1) if (($rtoℓer < $TOLER) && ($ctoℓer < $TOLER));

# set up the new values

70 $nextr = $rvaℓ + 0;

$nextc = $inxc + 0;

}

# write out the new component values for spice

75 open(VALS,">values.dat") or die "Could not set R and C values: $!";

print VALS join(’ ’, ($nextr, $nextc, $vin, $ℓser, $ℓdio, $ℓmut)), "\n";

close(VALS);

}

A.3 matching.sp

This is the HSPICE input ﬁle used for the analysis. Most of this ﬁle is setup commands

to make HSPICE produce appropriate output. Comments note the location of the circuit

under test.

SAMwIICh Circuit

.options post=1 nomod nopage INGOLD=1 accurate unwrap

5 * SPICE model for the diode

* courtesy of International Rectiﬁer

.MODEL d20cjq030 d

+IS=7.45927e−09 RS=0.0632601 N=0.89875 EG=1.3

+XTI=4 BV=30 IBV=0.0001 CJO=2.9346e−10

10 +VJ=0.4 M=0.427299 FC=0.5 TT=0

+KF=0 AF=1

—79—

SAMwIICh Code Listings

* simulation parameters

.PARAM FOSC = 100e6

15 .PARAM WOSC = ’6.283185 * FOSC’

.PARAM LMUT = 0

.PARAM LSER = 10e−9

.PARAM QLSER = 100

.PARAM LSHN = 47e−9

20 .PARAM QLSHN = 100

.PARAM LDs = 6n

.PARAM RSOURCE = 6.03

.PARAM CSOURCE = 2015e−12

.PARAM INV = 9

25

* the circuit under test

Vin rin 0 sin(0 INV FOSC 0 0)

Rin rin inc RSOURCE

30 Cin inc inm C=CSOURCE

Vinm inm in 0

Lser1 in 1 L=LSER R=’WOSC * LSER / QLSER’

35 Lshn1 1 nrfoo L=LSHN

Rfoo nrfoo 0 R=’WOSC * LSHN / QLSHN’

Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’

40 Ldio 1 3 LDs

Dtest 3 4 d20cjq030

Cout 4 0 30n

Vout 4 0 5

45 * some useful analysis options

.save all

.probe tran i(Vinm) V(in) V(1) v(3) v(4)

.probe tran p(Vin) p(Dtest) p(Vout) POWER

50 * these .measure statements allow us to examine input

* and output power, eﬃciency, and diode dissipation

.measure tran avgpin avg p(Vin) from=.5u to=1u

.measure tran avgprin avg p(Rin) from=.5u to=1u

.measure tran avgpd avg p(Dtest) from=.5u to=1u

55 .measure tran avgpout avg p(Vout) from=.5u to=1u

.measure tran avgptot avg POWER from=.5u to=1u

* the next line causes HSPICE to do the Fourier analysis

.four 100x v(in) i(vinm)

60

* this is data from automatch.pl

.DATA valdat MER

+FILE=’values.dat’ RSOURCE=1 CSOURCE=2 INV=3 LSER=4 LDs=5 LMUT=6

.ENDDATA

65

—80—

A.4 Eﬃciency Calculations

* perform a transient sweep, using the input data

.tran .01n 1u UIC SWEEP DATA=valdat

.end

A.4 Eﬃciency Calculations

The two ﬁles in here parse data out of the HSPICE listing and then do the crunching. I’ve

kept the two functions separate so that I can easily swap in a diﬀerent parser while keeping

the number crunching facilities the same, or vice-versa.

A.4.1 effextract.sh

This code extracts the data necessary for eﬃciency calculations from the HSPICE listing

in a format useful to effcalc.pl.

#!/bin/bash

# grab the power calculations out of the spice listing

5 grep avgpin= $1 | awk ’{print($2);}’ > $2.pin

grep avgprin= $1 | awk ’{print($2);}’ > $2.prin

grep avgpout= $1 | awk ’{print($2);}’ > $2.pout

paste $2.pin $2.prin $2.pout | tr ’\t’ , > $2.tmp

cat $2.tmp

10 rm $2.pin $2.prin $2.pout $2.tmp

A.4.2 effcalc.pl

This script calculates input and output power and conversion eﬃciency.

#!/usr/bin/perl

# reads in data from eﬀextract.sh

# subtracts power burned in the source resistance

5 # from total power in, then divides output/input

while(<>)

{

chomp;

10 ($pin, $prin, $pout) = split(/,/);

printf ("%s,%s,%s\n",

abs($pin)−abs($prin),

abs($pout),

abs($pout)/(abs($pin)−abs($prin)));

15 }

—81—

SAMwIICh Code Listings

A.5 Impedance Calculations

Like eﬃciency, impedance calculations are separated from parsing functionality.

A.5.1 impextract.sh

#!/bin/bash

# extract impedance parameters from input spice ﬁle

# this script grabs the fundamentals of the fourier series

5 # resulting from ’.four FREQ v(in) i(vinm)’

grep −A7 ’v(in)’ $1 | grep ’^[[:space:]]*1[[:space:]]’ | \

awk ’BEGIN {OFS=",";} {print($3,$5);}’ > $2.v

grep −A7 ’i(vinm)’ $1 | grep ’^[[:space:]]*1[[:space:]]’ | \

10 awk ’BEGIN {OFS=",";} {print($3,$5,$2);}’ > $2.i

paste $2.v $2.i | tr ’\t’ ,

rm $2.i $2.v

A.5.2 impcalc.pl

This is a slightly more complex script; its output is conﬁgurable via commandline parame-

ters.

#!/usr/bin/perl

# one of the workhorses of the SAMwIICh suite

5 use Getopt::Std;

my %opts;

# hooray for excessive precision

$pi = 3.14159265358979323846;

10

getopts(’CVhpm:’, \%opts);

if ($opts{’h’})

{

15 print "Usage: $0 [-C] [-V] [-p] [-m <res>] [-h]\n";

print " -V Print impedance magnitude, resistance, reactance, " .

"and equivalent component value\n";

print " -C Print complement of equivalent component value " .

"(i.e. component corresponding to -1*X)\n";

20 print " -p Print equivalent parallel input network\n";

print " -m <res> Print high pass L-match resulting in <res> input impedance\n";

exit(0);

}

25 sub engnot

—82—

A.5 Impedance Calculations

{

# change a number to engineering notation

# argument

30 my $num = shift @ ;

return undef unless $num;

# if it’s not in scientiﬁc notation,

# make it so

35 ($num = sprintf (’%4.4g’,$num)) unless ($num =˜ /e/);

my ($basen, $expnt) = split(’e’, sprintf (’%e’, $num));

my $adj = $expnt % 3;

$expnt −= $adj;

40 $basen *= 10**$adj;

return $basen . "e" . $expnt;

}

while (<>)

45 {

# main loop

# read in data from each line of stdin or ﬁlenames provided as arguments

chomp;

50 # read in the data

($vmag, $vph, $imag, $iph, $freq) = split(/,/);

$phase = $pi * ($vph − $iph) / 180;

$omega = 2 * $pi * $freq;

$zmag = abs($vmag) / abs($imag);

55 $R = $zmag * cos($phase);

$X = $zmag * sin($phase);

# print out impedance values

if ($opts{’V’})

60 {

printf ("%s %s %sj %s%s ",

engnot($zmag),

engnot($R),

engnot($X),

65 engnot((($X < 0) ? (−1 / ($X * $omega))

: ($X / $omega))),

(($X < 0) ? ’F’ : ’H’)

);

}

70

# print out conjugate element corresponding to X*

if ($opts{’C’})

{

printf ("%s%s ",

75 engnot((($X>0) ? (1 / ($X * $omega))

: (−1 * $X / $omega))),

(($X<0) ? ’H’ : ’F’)

);

—83—

SAMwIICh Code Listings

}

80

# convert series impedance to parallel impedance

if ($opts{’p’})

{

$q = abs($R/$X);

85 $Xp = $X * ($q**2+1)/($q**2);

$Rp = $R * ($q**2+1);

if ($X < 0)

{

90 $nmstring = ’F’;

$Ep = 1 / ($Xp * $omega);

}

else

{

95 $nmstring = ’H’;

$Ep = $Xp / $omega;

}

printf ("%s %s %s%s ", $q, engnot($Rp), engnot($Ep), $nmstring);

100 }

# matching with a high-pass L-match, cancelling

# input reactance as necessary

if ($opts{’m’})

105 {

# ﬁrst cancel the reactance

$ecanc = (($X > 0) ? (1 / ($X * $omega))

: (1 * ($X / $omega)));

110 $q = sqrt(abs(($opts{’m’}/$R) − 1));

$cm = 1 / ($omega * $q * $R);

$ℓm = $opts{’m’} / ($q * $omega);

115 if ($ecanc > 0)

{

$ctot = ($ecanc*$cm)/($ecanc+$cm);

printf ("%s %sF %sH",

$q,

120 engnot($ctot),

engnot($ℓm));

}

else

{

125 printf ("%sH %s %sF %sH",

engnot(−1*$ecanc),

$q,

engnot($cm),

engnot($ℓm));

130 }

}

—84—

A.5 Impedance Calculations

print "\n";

}

—85—

Appendix B

SPICE Netlists

This appendix contains all SPICE netlists used.

B.1 Comparison of Analytic Model with Simulation, Series

Rectiﬁer

The three netlists in this section are for the simulations performed in section 4.3.

B.1.1 Ideal Diode, Linear Capacitor

The diode is represented by a voltage-controlled resistor.

Series−resonant rectiﬁer, run #1

.options post=1 nomod nopage INGOLD=1 accurate unwrap

5 .PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM CDp = 123.6e−12

.PARAM LDs = 20.5e−9

.PARAM INV = 19.19

10

Vin rin 0 sin(0 INV FOSC 0 0)

Vinm rin in 0

15 Ldio in 3 LDs

Cdio 3 4 CDp

Gtest 3 4 VCR PWL(1) 3 4 0,1e24 1e−24,1e−24

Vout 4 0 5

20 .save all

.probe tran i(Vinm) V(in) v(3) v(4)

.probe tran p(Vin) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

—87—

SPICE Netlists

.measure tran avgpout avg p(Vout) from=.5u to=1u

25 .measure tran avgptot avg POWER from=.5u to=1u

.four 100x v(in) i(vinm)

.tran .01n 1u UIC

30

.end

B.1.2 Real Diode with Constant Junction Capacitance

This simulation uses a real diode model, but with the junction capacitance replaced by a

constant capacitor.

Series−resonant rectiﬁer, run #2

.options post=1 nomod nopage INGOLD=1 accurate unwrap

5 .MODEL d20cjqfoo d

+IS=7.45927e−09 RS=0.0632601 N=0.89875 EG=1.3

+XTI=4 BV=30 IBV=0.0001 CJO=1e−24

+VJ=0.4 M=0.427299 FC=0.5 TT=0

+KF=0 AF=1

10

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM CDp = 123.6e−12

.PARAM LDs = 20.5e−9

15 .PARAM INV = 19.19

Vin rin 0 sin(0 INV FOSC 0 0)

Vinm rin in 0

20

Ldio in 3 LDs

Cdio 3 4 CDp

Dtest 3 4 d20cjqfoo

Vout 4 0 5

25

.save all

.probe tran i(Vinm) V(in) v(3) v(4)

.probe tran p(Vin) p(Dtest) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

30 .measure tran avgpd avg p(Dtest) from=.5u to=1u

.measure tran avgpout avg p(Vout) from=.5u to=1u

.measure tran avgptot avg POWER from=.5u to=1u

.four 100x v(in) i(vinm)

35

.tran .01n 1u UIC

—88—

B.1 Comparison of Analytic Model with Simulation, Series Rectiﬁer

.end

B.1.3 Real Diode, Constant C

j

, Conjugate Source Impedance

As above, a “real” diode with constant junction capacitance was used. This time, the source

impedance is the conjugate of the calculated input impedance.

Series−resonant rectiﬁer, run #3

.options post=1 nomod nopage INGOLD=1 accurate unwrap

5 .MODEL d20cjqfoo d

+IS=7.45927e−09 RS=0.0632601 N=0.89875 EG=1.3

+XTI=4 BV=30 IBV=0.0001 CJO=1e−24

+VJ=0.4 M=0.427299 FC=0.5 TT=0

+KF=0 AF=1

10

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM CDp = 123.6e−12

.PARAM LDs = 20.5e−9

15 .PARAM INV = ’19.19 * 2’

.PARAM RSOURCE = 36.83

.PARAM CSOURCE = 154.26e−12

* since we are driving from a conjugate match,

* we have to double the voltage at the source

20 * to keep the input voltage the same

Vin rin 0 sin(0 INV FOSC 0 0)

* we must use a shunt capacitor

25 * because otherwise there is no

* path for DC current

Rin rin inm RSOURCE

Cin inm 0 CSOURCE

Vinm inm in 0

30

Ldio in 3 LDs

Cdio 3 4 CDp

Dtest 3 4 d20cjqfoo

Vout 4 0 5

35

.save all

.probe tran i(Vinm) V(in) v(3) v(4)

.probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

40 .measure tran avgprin avg p(Rin) from=.5u to=1u

.measure tran avgpd avg p(Dtest) from=.5u to=1u

.measure tran avgpout avg p(Vout) from=.5u to=1u

—89—

SPICE Netlists

.measure tran avgptot avg POWER from=.5u to=1u

45 .four 100x v(in) i(vinm)

.tran .01n 1u UIC

.end

B.2 Series Resonant Rectiﬁer Output Impedance

This rectiﬁer was implemented in [10]. The netlist uses a real diode model, including non-

linear output capacitance.

Series−resonant rectiﬁer, output impedance testing

.options post=1 nomod nopage INGOLD=1 accurate unwrap

5 .MODEL Dmbrs1540t3 d

+IS=3.54179e−05 RS=0.0306875 N=1.4038 EG=0.6

+XTI=1.97409 BV=40 IBV=0.0008 CJO=3.18451e−10

+VJ=0.4 M=0.428536 FC=0.5 TT=0

+KF=0 AF=1

10

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM LDs = 1e−9

.PARAM LSHN = 12.5e−9

15 .PARAM QLSHN= 150

.PARAM INV = 7.5

.PARAM VOUT = 5

Vin rin 0 sin(0 INV FOSC 0 0)

20

Vinm rin in 0

Lshn in nfoo LSHN

Rfoo nfoo 0 R=’WOSC * LSHN / QLSHN’

25 * we account for the ﬁnite Q of the

* inductor by calculating the appropriate

* series resistance

Ldio in 3 LDs

30 Dtest 3 4 Dmbrs1540t3

Vout 4 0 VOUT

.save all

.probe tran i(Vinm) V(in) v(3) v(4)

35 .probe tran p(Vin) p(Dtest) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

.measure tran avgpd avg p(Dtest) from=.5u to=1u

—90—

B.3 Comparison of Analytic Model with Simulation, Shunt Rectiﬁer

.measure tran avgpout avg p(Vout) from=.5u to=1u

.measure tran avgptot avg POWER from=.5u to=1u

40

.four 100x v(in) i(vinm)

.data vodat VOUT

+4.98 4.99 5.00 5.01 5.02

45 .enddata

.tran .01n 1u UIC SWEEP DATA=vodat

.end

B.3 Comparison of Analytic Model with Simulation, Shunt

Rectiﬁer

The netlists in this section are for the simulations performed in section 5.2.

B.3.1 Ideal Diode, Linear Capacitor

Shunt−resonant rectiﬁer, run #1

.options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100

5 .PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM CSER = 110.4e−12

.PARAM LSER = 28.24e−9

.PARAM CD = 101.32e−12

10 .PARAM LCHOKE = 2.5e−6

.PARAM INV = 5.6

.PARAM OUTV = 5

Vin in 0 sin(0 INV FOSC 0 0)

15

Cser1 in cin CSER

Lser1 cin lin LSER

Vinm lin 1 0

20 Cd 1 0 CD

Gtest 0 1 VCR PWL(1) 0 1 0,1e24 1e−24,1e−24

Lchk 1 4 LCHOKE

Voutm 4 out 0

25 Vout 4 0 OUTV

.save all

.probe tran i(Vinm) V(1) v(4) v(out) i(Voutm)

.probe tran p(Vin) p(Vout) p(Gtest) POWER

—91—

SPICE Netlists

30 .measure tran avgpin avg p(Vin) from=19u to=20u

.measure tran avgpd avg p(Gtest) from=19u to=20u

.measure tran avgpout avg p(Vout) from=19u to=20u

.measure tran avgptot avg POWER from=19u to=20u

35 .tran .1n 20u

.end

B.3.2 Real Diode with Constant Junction Capacitance

Shunt−resonant rectiﬁer, run #2

.options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100

5 .MODEL d20cjqfoo d

+IS=7.45927e−09 RS=0.0632601 N=0.89875 EG=1.3

+XTI=4 BV=30 IBV=0.0001 CJO=1e−24

+VJ=0.4 M=0.427299 FC=0.5 TT=0

+KF=0 AF=1

10

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM CSER = 110.4e−12

.PARAM LSER = 28.24e−9

15 .PARAM CD = 101.32e−12

.PARAM LCHOKE = 2.5e−6

.PARAM INV = 5.6

.PARAM OUTV = 5

20 Vin in 0 sin(0 INV FOSC 0 0)

Cser1 in cin CSER

Lser1 cin lin LSER

Vinm lin 1 0

25

Cd 1 0 CD

Dtest 0 1 d20cjqfoo

Lchk 1 4 LCHOKE

30 Voutm 4 out 0

Vout 4 0 OUTV

.save all

.probe tran i(Vinm) V(1) v(4) v(out) i(Voutm)

35 .probe tran p(Vin) p(Vout) p(Gtest) POWER

.measure tran avgpin avg p(Vin) from=19u to=20u

.measure tran avgpd avg p(Gtest) from=19u to=20u

.measure tran avgpout avg p(Vout) from=19u to=20u

.measure tran avgptot avg POWER from=19u to=20u

40

—92—

B.4 Shunt Resonant Rectiﬁer, Experimental Implementation

.tran .1n 20u

.end

B.4 Shunt Resonant Rectiﬁer, Experimental Implementation

This netlist corresponds to the experimental implementation of the rectiﬁer described in

section 5.4.

Shunt−resonant rectiﬁer, no inductance cancllation

.options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100

5 .MODEL d20cjq060 d

+IS=7.45927e−09 RS=0.0632601 N=0.89875 EG=1.3

+XTI=4 BV=30 IBV=0.0001 CJO=144.56e−12

+VJ=0.43217 M=0.47728 FC=0.5 TT=0

+KF=0 AF=1

10

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

.PARAM LMUT = 0

.PARAM LSER = 1e−9

15 .PARAM QLSER = 150

.PARAM LSHN = 120e−9

.PARAM QLSHN = 150

.PARAM LDs = 2e−9

.PARAM RSOURCE = 11.95

20 .PARAM CMAT = 74.6378e−12

.PARAM LMAT = 38e−9

.PARAM QLMAT = 150

.PARAM INV = 21

.PARAM FOOB = 0

25

Vin rin 0 sin(0 INV FOSC 0 0)

* note that the input capacitance is

* in the series path, not the shunt

30 * path. This is the reason for the

* discrepancy between the value used

* for experimentation and the value

* used in this simulation. Note that

* series-shunt conversion yields the

35 * correct value

Rin rin ino RSOURCE

Cm ino inm CMAT

Lm inm int L=LMAT R=’WOSC * LMAT / QLMAT’

40 Tin int 0 inmo 0 Z0=51.5 TD=5e−9 L=.95

Vinm inmo in 0

—93—

SPICE Netlists

Lser1 in 1 L=LSER R=’WOSC * LSER / QLSER’

45 Ldio 1 3 Lds

Dtest 0 3 d20cjq060

C3par 3 0 2e−12

50 Lshn1 1 4 L=LSHN R=’WOSC * LSHN / QLSHN’

Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’

Voutm 4 out 0

55

Cout out 0 100n

Vout out 0 5

.save all

60 .probe tran i(Vinm) V(inm) V(in) V(1) v(3) v(4) v(out) i(Voutm)

.probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

.measure tran avgprin avg p(Rin) from=.5u to=1u

.measure tran avgpd avg p(Dtest) from=.5u to=1u

65 .measure tran avgpout avg p(Vout) from=.5u to=1u

.measure tran avgptot avg POWER from=.5u to=1u

.measure tran ippout PP i(Voutm) from=.7u to=.72u

.four 100x v(in) i(vinm) i(voutm)

70

.tran .01n 1u UIC

.end

B.5 Shunt Resonant Rectiﬁer with Parasitic Mitigation

This netlist corresponds to the experimental implementation of the shunt rectiﬁer with

parasitic mitigation described in section 5.5.

Shunt−resonant rectiﬁer with inductance cancellation

.options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100

5 .model legd d is = 2.37487E−007 n = 1.98477 rs = 0.0171579

+ eg = 1.79999 xti = 3.99991

+ cjo = 5.47556E−010 vj = 1.64135 m = 0.603662 fc = 0.5

+ tt = 1.4427E−009 bv = 48.4 ibv = 3.5 af = 1 kf = 0

.model grd d is = 1.27781E−005 n = 1.2149 rs = 0.0250254

10 + eg = 0.55507 xti = 0.794212

.subckt d1n5822 1 2

—94—

B.5 Shunt Resonant Rectiﬁer with Parasitic Mitigation

ddio 1 2 legd

dgr 1 2 grd

15 .ends

.PARAM FOSC = 100e6

.PARAM WOSC = ’6.283185 * FOSC’

* set this parameter to the desired mutual inductance

20 .PARAM LMUT = 0

* dummy value; most of the inductance is in LMAT

.PARAM LSER = 1e−9

.PARAM QLSER = 150

.PARAM LSHN = 120e−9

25 .PARAM QLSHN = 150

.PARAM LDs = 6.5e−9

.PARAM RSOURCE = 2.56

* note that this is in series, not in shunt as in the actual implementation

.PARAM CMAT = 144e−12

30 .PARAM LMAT = 13.8e−9

.PARAM QLMAT = 150

.PARAM INV = 29.7

Vin rin 0 sin(0 INV FOSC 0 0)

35

Rin rin ino RSOURCE

Cm ino inm CMAT

Lm inm int L=LMAT R=’WOSC * LMAT / QLMAT’

Cm2 inm int C=CMAT2

40 Tin int 0 inmo 0 Z0=51.5 TD=5e−9 L=.95

Vinm inmo in 0

Lser1 in 1 L=LSER R=’WOSC * LSER / QLSER’

45 Ldio 1 3 Lds

Xtest 0 3 d1n5822

C3par 1 0 2e−12

50 Lshn1 1 4 L=LSHN R=’WOSC * LSHN / QLSHN’

Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’

Voutm 4 out 0

55

Cout out 0 100n

Vout out 0 5

.save all

60 .probe tran i(Vinm) V(inm) V(in) V(1) v(3) v(4) v(out) i(Voutm)

.probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER

.measure tran avgpin avg p(Vin) from=.5u to=1u

.measure tran avgprin avg p(Rin) from=.5u to=1u

.measure tran avgpd avg p(Dtest) from=.5u to=1u

65 .measure tran avgpout avg p(Vout) from=.5u to=1u

—95—

SPICE Netlists

.measure tran avgptot avg POWER from=.5u to=1u

.measure tran ippout PP i(Voutm) from=.7u to=.72u

.four 100x v(in) i(vinm) i(voutm)

70

.tran .01n 1u UIC

.end

—96—

Appendix C

Scripts for PCB Inductor

Generation

This appendix provides listings of the perl scripts [48] used to generate coupled magnetic

structures on PCBs.

C.1 mkcan.pl

mkcan.pl generates 20 coupled magnetic structures of increasing size and produces both

FastHenry simulations and scripts which produce a single PCB with the magnetic structures

laid out in a tiled pattern.

#!/usr/bin/perl -w

# the endpoints are always the same,

# allowing consistent via placement

5 $endpttop = "270,-90";

$endptbot = "440,250";

$viapt = "270,0";

# these deﬁne the base radius and increment

10 $baserad = 79;

$radmuℓ = 10;

for (my $i=0; $i<20; $i++)

{

15 # make a place to store the data

mkdir("p1r" . ($baserad+($radmuℓ*$i)));

chdir("p1r" . ($baserad+($radmuℓ*$i)));

# computer the new radius

20 $raditer = $baserad + ($radmuℓ * $i);

# generate the top spiral

—97—

Scripts for PCB Inductor Generation

$topcmd = ". ./bin/spiral.pl -t 1 -w 50 -c 35 -r "

. $raditer . " -C -e " . $endpttop

25 . " -b " . $viapt . ",0 > top.dat";

print ‘$topcmd‘;

# generate the bottom spiral

$botcmd = ". ./bin/spiral.pl -f -t 1 -w 50 -c 35 -r "

30 . $raditer . " -C -z -62 -e " . $endptbot

. " -b " . $viapt . "> bot.dat";

print ‘$botcmd‘;

# since we are tiling these on a PCB, give each

35 # one an appropriate oﬀset to make tiling simple

$xoﬀ = 1000 + ($i % 5)*2000;

$yoﬀ = 1000 + int($i/5)*2000;

# generate the Eagle script for the top

40 $topscr = ". ./bin/dat2scr.pl -f top.dat -p . ./gpdat -x "

. $xoﬀ . " -X " . $xoﬀ . " -y "

. $yoﬀ . " -Y " . $yoﬀ . " > top.scr";

print ‘$topscr‘;

45 # generate the Eagle script for the bottom

$botscr = ". ./bin/dat2scr.pl -f bot.dat -p . ./gpdat -x "

. $xoﬀ . " -X " . $xoﬀ . " -y "

. $yoﬀ . " -Y " . $yoﬀ . " > bot.scr";

print ‘$botscr‘;

50

# generate the part placement script

$pℓcmd = ". ./bin/placescr.pl -f . ./placedat -x $xoff "

. "-y $yoff > place.scr";

‘$pℓcmd‘;

55

# generate the data for FastHenry simulation

$indcmd = ". ./bin/dat2ind.pl -1 top.dat -2 bot.dat -F "

. "1e8,1e8,1 -b -H 3 -W 4 -p . ./gpdat > full.ind";

print ‘$indcmd‘;

60

# make the zbuf ﬁle

$fhzcmd = "fasthenry -f refined full.ind";

‘$fhzcmd &>/dev/null ‘;

‘zbuf zbuﬃle2 &>/dev/null ‘;

65 # fork oﬀ a new process to display the inductors

unless (fork())

{

# oooooh, pretty

print ‘gv −geometry +0−0 zbuﬃle2.ps‘;

70 exit;

}

# meanwhile, Rick James simulates them

‘fasthenry full.ind &>/dev/null‘;

75

—98—

C.2 spiral.pl

# extract the data from the FastHenry simulation

print ‘cat Zc.mat | . ./bin/qcalc.pl | tee Ldat‘;

# get ready to run another cycle

80 chdir(’. .’);

}

C.2 spiral.pl

spiral.pl generates spirals and circles in a generic format processed by dat2fig.pl,

dat2ind.pl, and dat2scr.pl.

#!/usr/bin/perl -w

use strict;

use Getopt::Std;

5

# ha ha

my $pi = 3.1415926535897932384626433832795;

my $maxtheta;

my $radrange;

10 my %opts;

getopts(’t:w:s:c:x:y:z:b:e:r:Cfph’, \%opts);

# show help if they don’t give -t foo

$opts{’h’}++ unless ($opts{’t’});

15 $opts{’h’}++ if ($opts{’C’} && !($opts{’r’}));

if ($opts{’h’})

{

print "Usage: $0 -t <turns> [opt [opt [opt]]]\n";

20 print " -t <turns> Number of turns (required)\n";

print " -w <width> Width of conductor in each turn (default 50)\n";

print " -s <space> Turn spacing multiplier (default 1.5)\n";

print " -c <chunks> Number of chunks (line segments) in output file\n";

print " -x <xoff> Offset in X-dimension (ignored in cylindrical mode)\n";

25 print " -y <yoff> Offset in Y-dimension (ignored in cylindrical mode)\n";

print " -z <zoff> Offset in Z-dimension\n";

print " -e <x1,y1[:x2,y2. . .]> Connects the outer end of the spiral to the given points\n";

print " -b <x1,y1[:x2,y2. . .]> Connects the inner end of the spiral to the given points\n";

print " (These points are referred to the center of the spiral,\n";

30 print " i.e. they are offset by <xoff> and <yoff>)\n";

print " -r <rad> Start with initial radius <rad> instead of zero\n";

print " -C Make a circle instead of a spiral. Must also specify -r.\n";

print " -f Flip spiral direction (default counterclockwise)\n";

print " -p Output points in cylindrical form (default Cartesian)\n";

35 print " -h Show this help screen\n";

exit(0);

}

—99—

Scripts for PCB Inductor Generation

$opts{’w’} | |= 50;

40 $opts{’s’} | |= 1.5;

$opts{’c’} | |= 100;

$opts{’x’} | |= 0;

$opts{’y’} | |= 0;

$opts{’z’} | |= 0;

45 $opts{’r’} | |= 0;

$opts{’C’} | |= 0;

if ($opts{’b’})

{

50 my @points = split(/:/, $opts{’b’});

foreach my $point (@points)

{

my ($xvaℓ, $yvaℓ) = split(/,/, $point);

55 $xvaℓ += $opts{’x’};

$yvaℓ += $opts{’y’};

if ($opts{’p’})

{

60 my $radius = sqrt($xvaℓ**2 + $yvaℓ**2);

my $theta = atan2($yvaℓ,$xvaℓ);

print join(",", ($radius, $theta, $opts{’z’}, $opts{’w’})) . "\n";

}

65 else

{

print join(",", ($xvaℓ, $yvaℓ, $opts{’z’}, $opts{’w’})) . "\n";

}

}

70 }

if ($opts{’C’})

{

unless ($opts{’t’} < 1)

75 {

# if it’s bigger than 1 turn, reduce it to 1 turn less

# 1.75 wire widths

$maxtheta = ((2 * $pi) − (1.75 * $opts{’w’} / $opts{’r’})) * (($opts{’f’}) ? −1 : 1);

}

80 else

{

# just calculate based on the number of turns

$maxtheta = $opts{’t’} * 2 * $pi * (($opts{’f’}) ? −1 : 1);

}

85 }

else

{

# spiral starts at 0, goes to 2*pi*#turns

$maxtheta = $opts{’t’} * 2 * $pi * (($opts{’f’}) ? −1 : 1);

90 # radrange is the distance we’ll be travelling

—100—

C.3 dat2fig.pl

$radrange = $opts{’w’} * $opts{’t’} * $opts{’s’};

}

for (my $i=0; $i<($opts{’c’}+1); $i++)

95 {

my $radius = ($opts{’C’}) ? $opts{’r’} : (($radrange * $i / $opts{’c’}) + $opts{’r’});

my $theta = $maxtheta * $i / $opts{’c’};

if ($opts{’p’})

100 {

print join(",", ($radius, $theta, $opts{’z’}, $opts{’w’})) . "\n";

}

else

{

105 my $xvaℓ = $radius * cos($theta);

my $yvaℓ = $radius * sin($theta);

print join(",", ($xvaℓ+$opts{’x’}, $yvaℓ+$opts{’y’}, $opts{’z’}, $opts{’w’})) . "\n";

}

}

110

if ($opts{’e’})

{

my @points = split(/:/, $opts{’e’});

115 foreach my $point (@points)

{

my ($xvaℓ, $yvaℓ) = split(/,/, $point);

$xvaℓ += $opts{’x’};

$yvaℓ += $opts{’y’};

120

if ($opts{’p’})

{

my $radius = sqrt($xvaℓ**2 + $yvaℓ**2);

my $theta = atan2($yvaℓ,$xvaℓ);

125

print join(",", ($radius, $theta, $opts{’z’}, $opts{’w’})) . "\n";

}

else

{

130 print join(",", ($xvaℓ, $yvaℓ, $opts{’z’}, $opts{’w’})) . "\n";

}

}

}

C.3 dat2fig.pl

dat2fig.pl generates a graphical representation of the output of spiral.pl suitable for

display with XFig [51] or translation to PostScript [52] using the transfig program [51].

#!/usr/bin/perl -w

—101—

Scripts for PCB Inductor Generation

use strict;

use Getopt::Std;

5

my %opts;

my @data;

getopts(’f:p:X:Y:h’, \%opts);

10

if ($opts{’h’})

{

print "Usage: $0 [opts]\n";

print " -f <filename> Read data from filename (stdin)\n";

15 print " -p <planefile> Ground plane data file\n";

print " -X <xpoff> Ground plane offset xpoff in x direction\n";

print " -Y <ypoff> Ground plane offset ypoff in y direction\n";

print " -h Show this help screen\n";

exit(0);

20 }

$opts{’f’} | |= ’-’;

open FILE, ’<’ . $opts{’f’} or

25 die "Couldn’t open file: $!";

while (<FILE>)

{

chomp;

30 my @tmp = split(/,/);

push @data, \@tmp;

}

close FILE;

35

# we assume that width is the same for all of the points

# maybe next time it would be good to use a diﬀerent width

# for each one, but this is good enough for my purposes

my $width = int((8/100 * $data[0][3]));

40 my $numpoints = $#data + 1;

print <<END;

\#FIG 3.2

Landscape

45 Center

Inches

Letter

100.00

Single

50 −2

1000 2

2 1 0 $width 0 7 50 −1 −1 0.000 1 0 −1 0 0 $numpoints

END

—102—

C.4 dat2ind.pl

55 # make the pretty XFig picture

for (my $i=0; $i<=$#data; $i++)

{

print int($data[$i][0]) . " ";

print int($data[$i][1]) . "\n";

60 }

@data = ();

# put in the ground planes if desired

65 if ($opts{’p’})

{

open FILE, ’<’ . $opts{’p’} or

die "Couldn’t open plane data file: $!";

70 while (<FILE>)

{

chomp;

my @tmp = split(/,/);

push @data, \@tmp;

75 }

for (my $i=0; $i<=$#data; $i++)

{

print "2 2 0 1 0 0 50 -1 20 0.000 0 0 -1 0 0 5\n";

80 printf ("%d %d %d %d %d %d %d %d %d %d\n",

int(${$data[$i]}[0] + $opts{’X’}),

int(${$data[$i]}[1] + $opts{’Y’}),

int(${$data[$i]}[3] + $opts{’X’}),

int(${$data[$i]}[4] + $opts{’Y’}),

85 int(${$data[$i]}[6] + $opts{’X’}),

int(${$data[$i]}[7] + $opts{’Y’}),

int(${$data[$i]}[0] + $opts{’X’}),

int(${$data[$i]}[7] + $opts{’Y’}),

int(${$data[$i]}[0] + $opts{’X’}),

90 int(${$data[$i]}[1] + $opts{’Y’}));

}

}

C.4 dat2ind.pl

dat2ind.pl generates a representation of data from spiral.pl suitable for simulation with

the FastHenry ﬁeld solver [53].

#!/usr/bin/perl -w

use strict;

use Getopt::Std;

5

my @planedata;

—103—

Scripts for PCB Inductor Generation

my $oneﬁℓe = 0;

my @data;

my %opts;

10 getopts(’f:1:2:F:p:bes:r:H:W:t:hX:Y:Z:’, \%opts);

$opts{’h’}++ unless ($opts{’f’} | | $opts{’1’} | | $opts{’2’});

if ($opts{’f’})

15 {

if ($opts{’1’} | | $opts{’2’})

{

print "Cannot specify both -f and -1/-2.\n";

$opts{’h’}++;

20 }

$oneﬁℓe = 1;

}

elsif (!($opts{’1’} && $opts{’2’}))

25 {

print "Must specify either -f or -1 and -2.\n";

$opts{’h’}++;

}

30 if ($opts{’s’} && $opts{’r’})

{

print "Cannot specify both sigma and rho.\n";

$opts{’h’}++;

}

35

unless ($opts{’r’})

{

$opts{’s’} | |= 1513.84;

}

40

if ($opts{’h’})

{

print "Usage: $0 (-f <file> | -1 <file1> -2 <file2>) [opt [opt [opt]]]\n";

print " **NOTE** Input units must be mils\n";

45 print " -f <file> Process a single file\n";

print " -1 <file1> -2 <file2> Process two files connected together\n";

print " -F <min,max,ndec> Simulate from min to max with ndec pts/dec (default DC)\n";

print " -p <planefile> Ground plane data file\n";

print " -b Connect two files at initial points\n";

50 print " -e Connect last point of <file1> to first point of <file2>\n";

print " -s <sigma> Set conductivity to sigma (1/(mil*Ohm)) (default Cu)\n";

print " -r <rho> Set resistivity to rho\n";

print " -H <nhinc> Number of height increments (default 5)\n";

print " -W <nwinc> Number of width increments (default 10)\n";

55 print " -t <thickness> Copper thickness (default 1.4 mils = 1 oz Cu)\n";

print " -X <pxoff> Ground planes offset by pxoff in x axis\n";

print " -Y <pyoff> Ground planes offset by pxoff in y axis\n";

print " -Z <pzoff> Ground planes offset by pxoff in z axis\n";

print " -h Show this help screen\n";

—104—

C.4 dat2ind.pl

60 exit(0);

}

$opts{’H’} | |= 5;

$opts{’W’} | |= 10;

65 $opts{’t’} | |= 1.4;

$opts{’F’} | |= "0,1,1";

$opts{’X’} | |= 0;

$opts{’Y’} | |= 0;

$opts{’Z’} | |= 0;

70

if ($oneﬁℓe)

{

open (FILE, "<" . $opts{’f’})

or die "Couldn’t open input file: $!";

75 @data = <FILE>;

close FILE;

chomp @data;

print "* Conversion of " . $opts{’f’} . "\n";

80 }

else

{

open (FILE, "<" . $opts{’1’})

or die "Couldn’t open first input file: $!";

85 @{$data[0]} = <FILE>;

close FILE;

open (FILE, "<" . $opts{’2’})

or die "Couldn’t open second input file: $!";

@{$data[1]} = <FILE>;

90 close FILE;

chomp @{$data[0]};

chomp @{$data[1]};

print "* Conversion of " . $opts{’1’} . " and " . $opts{’2’} . "\n";

95 }

print ".units mil\n";

print ".default " . ($opts{’r’} ? ("rho=" . $opts{’r’}) : ("sigma=" . $opts{’s’})) . "\n";

print ".default nhinc=" . $opts{’H’} . " nwinc=" . $opts{’W’} . "\n\n*NODES:\n";

100

if ($opts{’p’})

{

open FILE, ’<’ . $opts{’p’} or

die "Couldn’t open ground plane file: $!";

105

while (<FILE>)

{

chomp;

my @tmp = split(/,/);

110 push @planedata, \@tmp;

}

—105—

Scripts for PCB Inductor Generation

close FILE;

115 for (my $i=0; $i<=$#planedata; $i++)

{

printf ("G%d x1=%g y1=%g z1=%g

+ x2=%g y2=%g z2=%g

+ x3=%g y3=%g z3=%g

120 + thick=%g seg1=%g seg2=%g\n",

$i, ${$pℓanedata[$i]}[0] + $opts{’X’},

${$pℓanedata[$i]}[1] + $opts{’Y’}, ${$pℓanedata[$i]}[2]

+ $opts{’Z’}, ${$pℓanedata[$i]}[3] + $opts{’X’},

${$pℓanedata[$i]}[4] + $opts{’Y’}, ${$pℓanedata[$i]}[5]

125 + $opts{’Z’}, ${$pℓanedata[$i]}[6] + $opts{’X’},

${$pℓanedata[$i]}[7] + $opts{’Y’}, ${$pℓanedata[$i]}[8]

+ $opts{’Z’}, $opts{’t’}, ${$pℓanedata[$i]}[9] | | 10,

${$pℓanedata[$i]}[10] | | 10);

}

130 }

if ($oneﬁℓe)

{

for (my $i=0; $i<=$#data; $i++)

135 {

my @tmp = split(/,/, $data[$i]);

printf ("N%d x=%g y=%g z=%g\n", $i, $tmp[0], $tmp[1], $tmp[2]);

}

140 print "\n*EDGES\n";

for (my $i=0; $i<$#data; $i++)

{

my @tmp = split(/,/, $data[$i]);

145 printf ("E%d N%d N%d w=%g h=%g\n", $i, $i, $i+1, $tmp[3], $opts{’t’});

}

printf ("\n.external N1 N%d", $#data);

}

150 else

{

for (my $i=0; $i<2; $i++)

{

print "*file " . $opts{$i+1} . "\n";

155 for (my $j=0; $j<=$#{$data[$i]}; $j++)

{

my @tmp = split(/,/, ${$data[$i]}[$j]);

printf ("Nf%dn%d x=%g y=%g z=%g\n", $i, $j, $tmp[0], $tmp[1], $tmp[2]);

}

160 }

print "\n*EDGES\n";

for (my $i=0; $i<=$#data; $i++)

165 {

—106—

C.5 dat2scr.pl

print "*file " . $opts{$i+1} . "\n";

for (my $j=0; $j<$#{$data[$i]}; $j++)

{

my @tmp = split(/,/, ${$data[$i]}[$j]);

170 printf ("Ef%dn%d Nf%dn%d Nf%dn%d w=%g h=%g\n", $i, $j, $i, $j, $i, $j+1, $tmp[3], $opts{’t’});

}

}

if ($opts{’e’})

175 {

printf ("\n.equiv Nf0n%d Nf1n1\n", $#{$data[0]});

}

else

{

180 print "\n.equiv Nf0n1 Nf1n1\n";

}

printf (".external Nf0n1 Nf0n%d\n", $#{$data[0]});

printf (".external Nf1n1 Nf1n%d\n", $#{$data[1]});

185 }

my ($fmin, $fmax, $ndec) = split(/,/, $opts{’F’});

printf ("\n.freq fmin=%g fmax=%g ndec=%g\n", $fmin, $fmax, $ndec);

190

print "\n.end\n";

C.5 dat2scr.pl

dat2scr.pl generates placement scripts for the EAGLE CAD program [54] from data gen-

erated by spiral.pl.

#!/usr/bin/perl -w

use strict;

use Getopt::Std;

5 my %opts;

getopts(’f:p:x:y:X:Y:h’, \%opts);

if ($opts{’h’})

{

10 print "Usage: $0 -f <file> [opts]\n";

print " -f <file> Data file to read (stdin)\n";

print " -p <planefile> Ground plane datafile\n";

print " -x <xoff> Offset by xoff mils in x\n";

print " -y <yoff> Offset by yoff mils in y\n";

15 print " -X <xpoff> Offset ground plane by xpoff mils in x\n";

print " -Y <ypoff> Offset ground plane by ypoff mils in y\n";

print " -h Show this help screen\n";

exit(0);

—107—

Scripts for PCB Inductor Generation

}

20

my @data;

$opts{’f’} | |= ’-’;

$opts{’x’} | |= 0;

$opts{’y’} | |= 0;

25 $opts{’X’} | |= 0;

$opts{’Y’} | |= 0;

open FILE, ’<’ . $opts{’f’} or

die "Couldn’t open input file: $!";

30

while (<FILE>)

{

chomp;

my @tmp = split(/,/);

35 push @data, \@tmp;

}

close FILE;

40 # width should never change, so we just go with the ﬁrst one

my $width = $data[0][3] / 1000;

my $ℓayer = ($data[0][2] < 0) ? "bottom" : "top";

print "set wire_bend 2;\n";

45 print "change layer $layer;\n";

print "wire " . $width . " ";

for (my $i=0; $i<=$#data; $i++)

50 {

print("(" . (($data[$i][0] + $opts{’x’})/1000) . " ");

print((($data[$i][1]+$opts{’y’})/1000) . ")\n");

}

55 print ";\n";

@data = ();

if ($opts{’p’})

60 {

open FILE, ’<’ . $opts{’p’} or

die "Couldn’t open ground plane file: $!";

while (<FILE>)

65 {

chomp;

my @tmp = split(/,/);

push @data, \@tmp;

}

70

for (my $i=0; $i<=$#data; $i++)

—108—

C.6 placescr.pl

{

printf ("rect (%g %g) (%g %g);\n",

($data[$i][0] + $opts{’X’})/1000,

75 ($data[$i][1] + $opts{’Y’})/1000,

($data[$i][6] + $opts{’X’})/1000,

($data[$i][7] + $opts{’Y’})/1000);

}

}

C.6 placescr.pl

placescr.pl takes input from placedat and generates a script to place components on an

EAGLE layout.

#!/usr/bin/perl -w

use strict;

use Getopt::Std;

5 my %opts;

getopts(’f:x:y:h’, \%opts);

if ($opts{’h’})

{

10 print "Usage: $0 -f <file> [opts]\n";

print " -f <file> Data file to read (stdin)\n";

print " -x <xoff> Offset by xoff mils in x\n";

print " -y <yoff> Offset by yoff mils in y\n";

print " -h Show this help screen\n";

15 exit(0);

}

my @data;

$opts{’f’} | |= ’-’;

20 $opts{’x’} | |= 0;

$opts{’y’} | |= 0;

open FILE, ’<’ . $opts{’f’} or

die "Couldn’t open input file: $!";

25

while (<FILE>)

{

chomp;

my @tmp = split(/:/);

30 push @data, \@tmp;

}

for (my $i=0; $i<=$#data; $i++)

{

35 if (${$data[$i]}[0] eq "WIRE")

{

—109—

Scripts for PCB Inductor Generation

my ($part, $xstart, $ystart, $xend, $yend, $ℓayer, $width) = @{$data[$i]};

$width /= 1000;

40 $xstart = ($xstart+$opts{’x’})/1000;

$ystart = ($ystart+$opts{’y’})/1000;

$xend = ($xend+$opts{’x’})/1000;

$yend = ($yend+$opts{’y’})/1000;

45 print "change layer $layer;\n";

print "wire $width ($xstart $ystart) ($xend $yend);\n";

}

elsif (${$data[$i]}[0] eq "VIA")

{

50 my ($part, $xpos, $ypos, $diameter, $driℓℓ, $shape) = @{$data[$i]};

$diameter /= 1000;

$driℓℓ /= 1000;

$xpos = ($xpos+$opts{’x’})/1000;

55 $ypos = ($ypos+$opts{’y’})/1000;

print "change drill $drill;\nvia $diameter $shape ($xpos $ypos);\n";

}

else

60 {

my ($part, $xpos, $ypos, $rotation) = @{$data[$i]};

$xpos = ($xpos+$opts{’x’})/1000;

$ypos = ($ypos+$opts{’y’})/1000;

65

print "add $part $rotation ($xpos $ypos);\n";

}

}

C.7 qcalc.pl

qcalc.pl parses the Zc.mat ﬁle generated by FastHenry to provide self and mutual induc-

tance and Qdata.

#!/usr/bin/perl -w

use strict;

my ($L1, $L2);

5 # heh

my $pi = 3.1415926535897932384626433832795;

sub engnot

{

10 # argument

my $num = shift @ ;

return undef unless $num;

—110—

C.8 Miscellaneous Data Files

my ($basen, $expnt) = split(’e’, sprintf (’%e’, $num));

15 my $adj = $expnt % 3;

$expnt −= $adj;

$basen *= 10**$adj;

return $basen . "e" . $expnt;

}

20

while (<>)

{

if (/Impedance matrix for frequency = (\S*)/)

{

25 my $freq = $1;

my $ℓine1 = <>;

my $ℓine2 = <>;

my ($r11, $ℓ11, $r12, $ℓ12) = split(’ ’, $ℓine1);

30 my ($r21, $ℓ21, $r22, $ℓ22) = split(’ ’, $ℓine2);

# get rid of the ’j’ in the L terms

chop ($ℓ11, $ℓ12, $ℓ21, $ℓ22);

35 print "Frequency: ", &engnot($freq), " Hz\n";

print " L1: ", &engnot(($L1 = $ℓ11 / (2 * $pi * $freq))), "\n";

print " L2: ", &engnot(($L2 = $ℓ22 / (2 * $pi * $freq))), "\n";

print " Q1: ", 2 * $pi * $freq * $L1 / $r11, "\n";

print " Q2: ", 2 * $pi * $freq * $L2 / $r22, "\n";

40 print " Lm: ", &engnot(($ℓ12 + $ℓ21) / (4 * $pi * $freq)), "\n";

}

}

C.8 Miscellaneous Data Files

C.8.1 placedat

placedat contains input to placescr.pl which places components on the magnetic struc-

ture layouts.

b35n61:430:−480:R0

WIRE:430:−480:430:−100:top:50

C1812K:350:−130:R0

C1812K:510:−240:R0

5 C1812K:400:350:MR90

VIA:270:0:50:35:round

WIRE:270:0:400:0:top:50

403a−03:340:−5:R0

WIRE:400:430:0:430:bot:50

10 VIA:0:430:75:50:square

VIA:0:540:75:50:square

WIRE:300:−350:300:−600:top:100

—111—

Scripts for PCB Inductor Generation

WIRE:300:−350:300:−600:bot:100

C.8.2 gpdat

gpdat contains information on where to place the ground planes around the magnetic struc-

tures. It is processed by dat2scr.pl and dat2ind.pl.

−1000,1000,0,1000,1000,0,1000,500,0,10,5

−1000,500,0,−500,500,0,−500,−550,0,5,5

500,500,0,1000,500,0,1000,−550,0,5,5

−1000,−550,0,1000,−550,0,1000,−1000,0,10,5

5 −1000,1000,−62,1000,1000,−62,1000,500,−62,10,5

−1000,500,−62,−500,500,−62,−500,−550,−62,5,5

500,500,−62,1000,500,−62,1000,−550,−62,5,5

−1000,−550,−62,1000,−550,−62,1000,−1000,−62,10,5

—112—

Appendix D

Shunt Rectiﬁer PCB Layouts and

Magnetic Structures

Layouts for the shunt resonant rectiﬁers implemented in section 5.5 are provided in this

appendix. In the layouts, diagonal top left to bottom right hatching indicates copper on

the top layer of the board, whereas top right to bottom left indicates the bottom copper.

Crosshatching is used where both the top and bottom copper are present.

In all cases, the input signal comes from the BNC at the bottom right edge of the

picture. C

shn

connects from the input trace to ground directly adjacent to the connector.

L

ser

connects from the input node to the trace above and to the left of the BNC. Since L

ser

is provided entirely by the coupled magnetic structures when cancellation is employed, the

input node is simply shorted to the input of the magnetic structure in these cases.

In the layout without cancellation, the cathode of the diode D connects from ground to

the node adjoining L

ser

; in the cases where cancellation is used, D is located in the same

place, but is connected to the other end of L

1

. L

2

is on the bottom side of the board, and

connects to pads for L

choke

, also located on the bottom of the board. When no cancellation

is employed, the diode cathode is simply shorted to one of the L

choke

pads.

The output node is located at the top of the layout, and provides room for several bypass

capacitors and through-hole mounting for an output connector block.

—113—

Shunt Rectiﬁer PCB Layouts and Magnetic Structures

The magnetic structures that were implemented are also represented in 3-dimensional

renderings which give a more detailed structural view. The renderings were made using

the zbuf utility provided with the FastHenry software package [53]. In all cases, the top

winding is L

1

and the bottom winding is L

2

. While it is not explicitly represented in the

renderings, the connection between L

1

and L

2

is located on the short overlapping segments.

On the PCB, this connection is implemented as a via.

Figure D-1: Layout for shunt rectiﬁer without cancellation.

—114—

(a) 3D rendering of the magnetic structure.

(b) PCB layout.

Figure D-2: L

M

= 3.5 nH

—115—

Shunt Rectiﬁer PCB Layouts and Magnetic Structures

(a) 3D rendering of the magnetic structure.

(b) PCB layout.

Figure D-3: L

M

= 4.0 nH

—116—

(a) 3D rendering of the magnetic structure.

(b) PCB layout.

Figure D-4: L

M

= 4.6 nH

—117—

Shunt Rectiﬁer PCB Layouts and Magnetic Structures

(a) 3D rendering of the magnetic structure.

(b) PCB layout.

Figure D-5: L

M

= 6.3 nH

—118—

**Radio Frequency Rectiﬁers for DC-DC Power Conversion by Riad Samir Wahby
**

Submitted to the Department of Electrical Engineering and Computer Science on May 20, 2004, in partial fulﬁllment of the requirements for the degree of Master of Engineering

Abstract

A signiﬁcant factor driving the development of power conversion technology is the need to increase performance while reducing size and improving eﬃciency. In addition, there is a desire to increase the level of integration of DC-DC converters in order to take advantage of the cost and other beneﬁts of batch fabrication techniques. While advances in the power density and integration of DC-DC converters have been realized through development of better active device technologies, much room for improvement remains in the size and fabrication of passive components. To achieve these improvements, a substantial increase in operating frequency is needed, since intermediate energy storage requirements are inversely proportional to frequency. Unfortunately, traditional power conversion techniques are ill-suited to handle this dramatic escalation of switching frequency. New architectures have been proposed which promise to deliver radical performance improvements while potentially reaching microwave frequencies. These new architectures promise to enable substantial miniaturization of DC-DC converters and to permit much a higher degree of integration. The principal eﬀort of this thesis is the development of design and characterization methods for rectiﬁer topologies amenable to use in the new architectures. A computational design approach allowing fast and accurate circuit analysis and synthesis is developed and applied, along with traditional analysis, to two demonstrative rectiﬁer topologies. In addition, the application of coupled magnetic structures for parasitic mitigation is considered. Experimental implementations are investigated to verify analytic and computational results. Thesis Supervisor: David J. Perreault Title: Carl Richard Soderberg Assistant Professor of Power Engineering

Acknowledgments

Thanks ﬁrst and foremost to my parents. Their dedication to my education, unconditional love, and unwavering support have been, simply put, astounding. To my sisters, too, I say thanks for everything. Not long ago, I was unsure of my career path. It was Professor Dave Perreault who brought me ﬁrmly back into the electrical engineering fold, so to speak, and for that I am in his debt. His incredible enthusiasm and unparalleled knowledge of seemingly everything have made working for him the past year an awesome learning experience and a source of constant intellectual stimulation. I owe thanks to my friends as well. In no real order, thanks to Jack, Jim, Mar, Andrew, Rob, Chris, Josh, Juan, Claudio, and everyone else in LEES; to Hippo, Ariel, Gautham, Sherv, Ian, Rodin, Amrys, George, Max, Sam, Kurt, Petar, Woz, May, and the rest of the Fort Awesome crew; and to Kevin, Dave, Lael, Perry, and the rest of Clam’s old guard. If for some reason I didn’t list you here—thank you, too. A long time ago, I used to consider myself a violinist (and what’s more, other people did as well!). My musical training has proven an immeasurable help in many unexpected ways; thus, special thanks go to Doris Preucil and to Claudia Johnson. Finally, I would like to thank the Massachusetts Institute of Technology and the member companies of the MIT/Industry Consortium on Advanced Automotive Electrical/Electronic Components and Systems, whose sponsorship enabled this research.

To my parents, whose dedication has been without parallel.

. . . . . . . 2. . . . . . . 2. . . . . 15 15 16 18 20 21 23 23 24 25 26 27 28 30 31 33 34 35 37 Thesis Objectives . . . . . . . . . . . . . .2 Jacobi’s Theorem . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents 1 Introduction 1. . . . . . . . . . . . . . The Double-Tapped Resonator . .2. . . . . . . . . . . . . Tapped Capacitor Resonator . . . . . .2. . . . . . . . . . . . . .2 2. .2. . . . . . . . .2 1. . . . . . . . . 1. .1 1. . . . Series-Shunt Transformation . . . . . . . . . . . .1.5 The L-Match Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . .and Π-Matches . . . . . .1 2. . . . . . . . . . . . . . . . . .3 2. . . . . . . . . The L-Match . . . . Thesis Organization . .1 2. .2 1. Tapped Inductor Resonator . . . . . . .1. .2 2. . . . . . . . . Higher Order Matching Networks .3 Problems With High-Frequency Power Conversion . . . . . . .3 Active Impedance Matching . . . The T. .1 Resonant Impedance Analysis . . . . Proposed Architectural Improvements . .4 2. .1 Background and Motivation . . . . . . . . . . . . . . . 2 Useful Techniques for Resonant Circuit Analysis 2.2. . . . . . . . . .2. 3 Computational Techniques for Nonlinear Circuits —7— . . . . . . . .

5 Analysis of the Shunt Resonant Rectiﬁer . . . . . . . . .1 Makefile .2 3. . . . . . .2 5. . . .4 5.1 4. . . . . . . . . . . . Improved Iterated Matching . Comparison of Analytic Model with Simulation . . . . . . . . . . 4 The Series Resonant Rectiﬁer 4. . . . . . .5 Analysis of the Series Resonant Rectiﬁer . Application of the Series Resonant Rectiﬁer . . . . . . . . . . . . . . . . . Nonlinear Network Impedance Considerations . . .1 3. . . . . . . . . . . . . . . .3. Bibliography A SAMwIICh Code Listings A. . . . . . . . . . . . . . . . . . . 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5. . . . . . . . . . . . . . . . . . . . . . . .1 3. . . . . . . . . . . . . 5 The Shunt Resonant Rectiﬁer 5.3 Basic Iterated Matching . . . . . .CONTENTS 3. . . . . . . . . . . . . . . . . . . . . . Recommendations for Future Work . . . . . . . Thesis Conclusions . . . . . . . . . . Comparison of Analytic Model with Simulation . . . .2 6. . . . . . . . . . . .3 4.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental Implementation . . . . . . . . .1 6. Application of the Shunt Resonant Rectiﬁer . . .3. . . . . .2 4. . . . . . . . . . . . . . . . .3 Motivations for Computational Analysis . . . . . . . . . . . . . . . . . . . .3 5. . . . . . Convergence of the Iterated Matching Procedure . . . . . . . . . . . . . . . . .2 3. . . . . . . . . . . . . . . . . . .4 SAMwIICh: An Automated Matching Implementation . . . . . . . . . Parasitic Mitigation in the Shunt Rectiﬁer . . . . . . . 6 Conclusion 6. —8— . . . . . . . . . . . Experimental Implementation . . . . . . . . . . . . . . The Iterated Approach . . . . . . . . . . . . . . . . 37 38 40 40 41 43 44 47 47 49 52 54 55 57 57 60 61 63 64 69 69 70 71 71 77 77 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fourier Analysis of Input Impedance .4 4. . . . .3 Thesis Summary . . .

. . C.sh . . . . . . . . .4. . . . . . . .2 Series Resonant Rectiﬁer Output Impedance . . . . . . . . . . . . . . . . . . . . .pl . . . . . . . . . . . . . . . . . . . .1 mkcan. . .CONTENTS A. . . .6 placescr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. . . . . B. . . . . . . . . . . C. . . . . . A. .5. . . Experimental Implementation . . . . . . B. . A. . . . . . . . . . . . .1 Ideal Diode. . . . . B. . . . . . . B. . . . . . . . . . .2 spiral. B.sh . . . . .1 Ideal Diode. .2 effcalc. . . . . . . . . . .7 qcalc. . . . . . . . . . .2 automatch. . . . . .1 effextract. . . . . . Shunt Rectiﬁer . . . .pl . . . . . . . . . . . . . . . .pl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. A. . . . . . . . . . . . . .3 Comparison of Analytic Model with Simulation. . . . . . . .1. . . . B SPICE Netlists B. . . . . . . .pl .1. . . . . . . . . . . . . . . . . . . . . . . .2 impcalc. . . C. . . . . . .pl .4 dat2ind. . . . . . . . . . .pl . Linear Capacitor . . . . . . . . . . . . . . . . . . . . . . .3 Real Diode. . . . . . . . . . . . A. . . . . . .4 Shunt Resonant Rectiﬁer. . . . . . . . . . —9— 78 79 81 81 81 82 82 82 87 87 87 88 89 90 91 91 92 93 94 97 97 99 101 103 107 109 110 . . . . . . . . . . . . . . . . . . . . . . . . . .pl . . . . . C. . . . . . . . . . . . . . . . . . . . . . . . . Series Rectiﬁer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .pl . . . .2 Real Diode with Constant Junction Capacitance . . . . . . . . . . . . . . . . . . . . C Scripts for PCB Inductor Generation C. . A. .5 Shunt Resonant Rectiﬁer with Parasitic Mitigation . A.pl . . Conjugate Source Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . B. . . . . . .3 matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . B. C. . . . . . . .5. Linear Capacitor . . .1 impextract. . . . .4 Eﬃciency Calculations . . . . . . . .3. . . . .1 Comparison of Analytic Model with Simulation. . . . . A. . . .4. . . . . .pl . . . . . . .3 dat2fig. . . . . . . . . . . . . . . . . . .5 dat2scr.3.sp . . .5 Impedance Calculations . . . Constant Cj . . . . . . . . C. . . . . .2 Real Diode with Constant Junction Capacitance . . . . . . . . . .

. . . . . . . . . . . . . .CONTENTS C. . . . . . . . . . . . . . . . . . . . . . . . . . .2 gpdat . . . . . . . . .8. . . . . C. . . . . . . . . .8. . . . . . .1 placedat . . . . . . . D Shunt Rectiﬁer PCB Layouts and Magnetic Structures 111 111 112 113 —10— . . . . . . . . . . . . C.8 Miscellaneous Data Files . . . . . . . . . . .

.and Π-matches. . . . . . . . . . . . . . . . . . . . 2-7 Diode junction capacitances can be used to obtain a controlled L-match.3.List of Figures 1-1 An illustration of switching loss in the boost converter. . . . . . give the designer another degree of freedom. . . . . . . . . . . . . . 3-2(a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 A simple circuit for deriving Jacobi’s theorem. . . . . . . . . . . . . . . . . . . 2-6 The double-tapped resonator gives an additional degree of freedom beyond the third-order matching networks. . . . . . . . . . . 2-2 The L-match is derived by series-shunt transformation of one element in a series resonant circuit. . . . . . . . . . in some cases. . 2-5 The tapped inductor match is a close relative of the tapped capacitor match of section 2. . . . . . . . . . —11— 36 39 41 42 48 34 33 32 30 26 17 19 24 . . . . . . . . 3-1 Linearized input impedance models. . . . . . . . composed of two L-matches. .2. . 4-1 The series resonant rectiﬁer. . . more reasonable component values than the T. . . . . . . . . . . . . . . . . . . . . A DC voltage Vc applied as shown controls the shunt capacitance. . . . . . . . . . . . . . . 3-3 An improved matching network for the circuit of Fig. . . . . 1-2 The basic structure of the proposed architectures. . .or Π-match. . . . . . . 2-4 The tapped capacitor match gives more freedom than the L-match and. . . . . . . . . 3-2 A demonstration of the iterated impedance matching approach. . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 The T. . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . .5 nH . . . . . . . . . . . . . . . . . D-1 Layout for shunt rectiﬁer without cancellation. . D-4 LM = 4. . . . . D-3 LM = 4. . . . . .3 nH . . 5-5 Experimental implementation of the shunt rectiﬁer with parasitic mitigation. 5-2 The computationally-assisted design process for the shunt resonant rectiﬁer. . . . . . . . .0 nH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 LM = 3. . . . . . 49 4-3 To provide a DC current path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4-4 Experimental implementation of the series rectiﬁer.6 nH . . . . . . . . . . . . . . . . . . . . . D-5 LM = 6. . . . . . . .LIST OF FIGURES 4-2 A parallel RL model for series rectiﬁer input impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 The shunt resonant rectiﬁer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Experimental implementation of the shunt rectiﬁer. . . . . . . 5-4 The shunt resonant rectiﬁer with coupled magnetics for parasitic mitigation. . all or part of Ls can be transformed into Lshn . . . . . . . 55 57 62 63 65 65 114 115 116 117 118 —12— . . .

. . . .3 Input impedance. . . . 5. . Component values used in the series rectiﬁer experimental implementation. .2 5. calculated versus simulated. . . .1 4.List of Tables 4. . . . Component values used in the shunt rectiﬁer experimental implementation. . . .1 5. .4 Experimental results for shunt rectiﬁers with parasitic mitigation. Component values used in the experimental implementation of the shunt rectiﬁer with parasitic mitigation. . Output power and eﬃciency. . . . . . . 66 66 53 56 60 63 —13— . . and eﬃciency. . . . . . . calculated versus simulated. .2 5. . . output power. . . . .

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new circuit topologies and system architectures can be used. since intermediate energy storage requirements are inversely proportional to operating frequency. Moreover. At higher frequencies. loss mechanisms that can generally be ignored at low frequencies become crucial design considerations. —15— . Doing so requires in almost all cases an increase in the frequency at which the converter operates.1 Background and Motivation ONTEMPORARY research in DC-DC power conversion is strongly motivated by the need to increase performance while reducing size and maintaining or improv- C ing eﬃciency.Chapter 1 Introduction 1. allowing major portions of systems to be manufactured using batch fabrication techniques. In addition. To combat these diﬃculties. Finally. non-idealities in circuit components become much more important. Unfortunately. there is a desire to achieve a higher degree of integration of DC-DC converters. equal or greater beneﬁt can be achieved by reducing the size of the passive components. this increase in operating frequency is not without costs. control strategies commonly used at low frequencies become unwieldy when used at high frequencies. While some improvements in the power density and integration of DC-DC converters can be realized through extensive miniaturization and integration of active components.

. a new computational approach to circuit analysis and design synthesis will be presented.1.e. soft-switched converters allows high frequency converter designs that take advantage of techniques employed in tuned radio frequency power ampliﬁers. In addition. Assuming a large input inductor (i. This thesis will explore rectiﬁcation of power at high frequencies (100 MHz–1 GHz) and its application to new architectures for DC-DC conversion. the device both conducts current and drops voltage. 1. In particular. as there exist few permeable materials whose performance is acceptable for application in high frequency power conversion. rectiﬁer topologies suitable for parallel combination in a cellular converter architecture will be designed and characterized. the transistor must conduct current until its drain voltage rises to one diode drop above the output voltage. Figure 1-1 illustrates a boost converter (1-1(a)) and the on-tooﬀ transient of the MOSFET (1-1(b)). inductors are of particular concern. Switching Loss Switching loss arises from the fact that no practical active element can turn on or oﬀ instantaneously: there is some interval during which the device must traverse the region between the on and oﬀ states. implementing passive components compatible with eﬃcient power processing at high frequency is often diﬃcult. must also be considered. To solve the problem of controlling these high-frequency DC-DC converters. only then is the diode forward biased and able —16— . During this time. a new architectural approach will be employed which partially decouples the problems of eﬃcient power conversion and controlled power delivery. traditional control strategies for low frequency converters are impractical at high frequencies.Introduction Replacing hard-switched square-wave topologies with resonant. switching loss and gating loss. Finally. dissipating power. at high frequencies two other loss mechanisms.1 Problems With High-Frequency Power Conversion Whereas at low frequencies conduction losses are generally dominant. In addition. continuous conduction operation).

In a switching scheme where the gate terminal is charged from the supply and discharged into ground. to conduct current to the output. eﬃciency when delivering only a fraction of full power is severely reduced. In a MOSFET. power loss proportional to frequency results. energy is only lost in conduction [3–6]. In eﬀect. but untenable at 100 MHz [1].1 Background and Motivation vD t L iD Vin + − + D vD − C Rload t D iD (a) A boost converter circuit. the gate capacitance must be charged to turn the device on and discharged to turn it oﬀ. Gating Loss Gating loss is a result of the fact that turning any active device on or oﬀ involves a transfer of energy. energy can be recovered and reused in subsequent cycles. To ameliorate switching losses. In these topologies. For a typical device such a transition takes about 15 nanoseconds—insigniﬁcant at 100 kHz. in this way. for example. Figure 1-1: An illustration of switching loss in the boost converter. (b) Switching waveforms. By employing resonant structures in driving the gate. zero-voltage switching topologies are often employed [2]. a resonant gate driver —17— . While ZVS can be advantageous when applied to DC-DC conversion at full load.1. In the simplest of such circuits. the energy transferred onto the gate capacitor is transferred oﬀ and stored on an external inductor until the next switching cycle. it becomes a problem at light load: since the losses accompanying resonant operation are present at all load conditions. a continuous resonating action is used to ensure that switches only change state when supporting little or no voltage.

the beneﬁts of resonant gate drive can often be most fully developed by using a cascade of resonant converters. ﬂux derating becomes necessary. forcing the designer to trade oﬀ ease of control for eﬃciency. For most ferrite materials. Moreover.2 Proposed Architectural Improvements To overcome the limitations of very high frequency operation while taking advantage of its beneﬁts. Control Strategies Control strategies employed at low frequencies are not easily adapted to eﬃcient high frequency topologies. they are generally incompatible with ZVS and resonant gate drive topologies. even so.Introduction is itself an RF ampliﬁer. passive component sizing is dominated by volumetric energy storage limits. such as frequency control [7. as do considerations of converter dynamics and the complexity of implementing control circuitry. —18— . realizing regulation over a wide load range becomes increasingly diﬃcult as frequencies increase. do not suﬀer this limitation. These architectures utilize high eﬃciency tuned RF power ampliﬁer circuits while partitioning the energy conversion and control functions so as to avoid the limitations discussed in section 1. lacking a lossy permeable core material.1. 8]. the consequently reduced inductance per turn squared requires very high frequency operation to achieve reasonable component size and Q. to mitigate these loss characteristics. losses become the most important consideration in the sizing of magnetic components. however. Regulation can be achieved by other techniques. Magnetic Components At low frequencies. one driving the next. As a result.1. At higher frequencies. cascaded resonant gate drive is often at odds with such a strategy. Aircore magnetic passives. thus. increasing frequency can cause inductor sizes to worsen instead of improving [9]. Since such strategies often require direct manipulation of the harmonic content of operating waveforms. 1.1. core losses increase dramatically with frequency. new cellular architectures have been proposed [10].

eﬃciency is of paramount importance. a well-characterized input impedance is crucial for optimizing the matching network that connects the inverter and rectiﬁer. . since this facilitates load sharing among a parallel combination of several unregulated cells. . Ru1 . failure to 1 The design of a suitable inverter is the topic of a separate investigation. Figure 1-2: The basic structure of the proposed architectures. Rr ) and several unregulated cells (Iu1 .1 Background and Motivation Rr + − Vr Iu1 Ru1 Iu2 Ru2 Iun Run Rload (a) The proposed architectures employ one regulating cell (Vr . Each unregulated cell operates only when required. In this application. this allows nearly maximum performance to be achieved at all times. un ). un . Figure 1-2(a) illustrates the proposed architecture. —19— . The new architectures employ two types of cells. RF power converters comprising an inverter and rectiﬁer operating at very high frequency are used as unregulated.1. . In addition. a rectiﬁer having high output impedance is desirable. Vin + − Inverter Matching Network Rectiﬁer Rload (b) The basic structure of an unregulated cell comprises an inverter and a rectiﬁer connected by an impedance matching network. and only over a narrow range of conditions. the basic structure of one unregulated cell is depicted in Fig. The principal eﬀort of this thesis is the development of design and characterization methods for rectiﬁer topologies amenable to use in the aforementioned architectures1 . 1-2(b). this reduces the impact of regulating cell loss on total eﬃciency. Finally. on/oﬀcontrolled parallel cells. . Control is provided by a regulating cell. which only provides a fraction of the output power.

and implementation of radio frequency rectiﬁers with the aim of improving both the process and product of future rectiﬁer designs. not considered in this thesis. I will develop an approach for computational modeling of nonlinear resonant circuits. Though some minimal programming skill will likely be useful. In particular. full code is provided in the appendices. allowing the casual reader to proceed quickly to the ﬁnal result. and will show the methods used for developing both. the reader will not be unduly taxed with abstruse code listings4 . a topology that makes use of these parasitics will likely outperform one that does not. design. undesirable parasitic inductances might be cancelled using coupled magnetic structures [21. though not necessarily original! 4 For those of true grit. Third. a resonant zerovoltage switching topology which minimizes peak diode currents is necessary [14–20]. First. arduous mathematical derivations will be accompanied by ample verbiage. Moreover. I will demonstrate general3 methods for cocktail napkin-style analysis of linear resonant circuits. since diode drop and the resulting conduction loss are largely avoided. I have several objectives. parasitics associated with the active device are very important at high frequencies. and establish the groundwork for similar analysis of others. thus. —20— . To this end. 1. I will apply these analytic and computational techniques to example rectiﬁer topologies. . As much as possible. To achieve acceptable eﬃciency. incurs additional penalty in gating. Second. In radio frequency rectiﬁers employing diodes. 22]. In addition to stan2 Synchronous rectiﬁcation. allowing the user to proceed from speciﬁcation to design very quickly. I will attempt to employ intuition and reasonable estimates. characterization.Introduction share the load equally could result in ineﬃcient operation or cell failure [11–13].2 Thesis Objectives This thesis explores the selection. When necessary. . Alternatively. both conduction losses and switching losses are important considerations2 . 3 . I will show algorithms for fast and accurate computational circuit synthesis. but may result in overall eﬃciency improvement.

In this chapter. 1. e. exploring the design and implementation process of the series resonant rectiﬁer. Experimental results are also discussed. Chapter 5 covers another topology. Chapter 4 comprises a discussion of analytic models including Fourier and describing function analysis of input impedance..3 Thesis Organization dard topologies. allowing device parasitic mitigation and reduced manufacturing cost. the shunt resonant rectiﬁer. and demonstrates the application of these techniques to the analysis and design of resonant impedance transformers. Finally. including this introduction. a comparison of the analytic models with simulation. —21— . Chapter 3 introduces the use of computational modeling for nonlinear circuit analysis. implemented on printed circuit boards). and a discussion of the strengths and weaknesses of the series resonant topology.3 Thesis Organization This thesis is divided into six chapters. Implementations of rectiﬁers with and without parasitic mitigation are presented. the exploration of the shunt topology is extended by application of coupled magnetic structures which allow the mitigation of undesired parasitic eﬀects. Chapter 4 discusses the ﬁrst of two resonant rectiﬁer topologies. In addition to a discussion of analytic models and simulated results. These will be accompanied by both simulation and experimental evaluation. Chapter 6 concludes the thesis with a summary of the results and suggestions for continued work. algorithms are developed that allow for extremely fast design of rectiﬁer circuits and which pave the way for the analyses performed in the proceeding chapters. I will explore the use of coupled magnetic structures (which can be.g. Chapter 2 reviews analytic techniques useful in linear resonant circuit analysis.1.

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—23— . and because the particular techniques reviewed here are a key component of the insight leading to the algorithms presented in chapter 3. Much of the material is available from other sources [23–25]. since analytic approaches to the same problem diﬀer substantially from one book to another. Because many RF circuits operate over only a very limited frequency band. it’s useful to remember the reason for their use. the use of narrowband impedance transformation circuits is exceedingly common. this chapter has been included nevertheless. Before delving into the analysis of such circuits.1 Resonant Impedance Analysis A major challenge in designing RF rectiﬁers. is ensuring that maximum power is transferred from input to output. In addition. the last section discusses an active impedance matching network which might be employed in a feedforward or feedback system to eﬀect a dynamic 2. HIS CHAPTER is intended to familiarize the reader with useful analytic techniques for linear resonant circuits.Chapter 2 Useful Techniques for Resonant Circuit Analysis T match. and indeed almost any RF power circuit. however.

In the mid-19th century.1. the scarcity of power gain necessitates the resurrection of an oft-forgotten theorem taught in every basic circuits course: for a ﬁxed source impedance. his younger brother. of course. engineers (including James Prescott Joule!) misinterpreted this theorem to imply that an electrical machine could never be made more than 50% eﬃcient while delivering substantial power.1) (2. there is no diﬃculty in obtaining power gain. —24— .6) 1 This theorem is often referred to as the Maximum Power Transfer theorem to avoid confusion with a mathematical theorem of the same name. This is. 2. On the other hand. Moritz Hermann Jacobi is responsible for the former. however.Useful Techniques for Resonant Circuit Analysis Zs + Vs Zℓ Vℓ − Figure 2-1: A simple circuit for deriving Jacobi’s theorem.1 Jacobi’s Theorem In low frequency designs. false—for a ﬁxed source impedance. Vs 2 · Rℓ Vℓ 2 = Rℓ (Rℓ + Rs )2 ∂Pℓ 2Rℓ 1 = Vs 2 − ∂Rℓ (Rℓ + Rs ) (Rℓ + Rs )3 Pℓ = ∴ Rℓ = Rs Pℓ = Vℓ Iℓ cos (φ) φ = tan−1 ∴ Xℓ = −Xs Xs + Xl Rℓ (2. stated the latter. whereupon they designed their dynamos for minimal armature resistance and realized eﬃciencies near 90%.2) (2.3) (2.4) (2.1 with respect to Rs quickly shows that if instead the load impedance is ﬁxed. Carl Richard. Francis Robbins Upton. Figure 2-1 shows an example circuit from which derivation of the maximum power transfer theorem is straightforward. diﬀerentiating equation 2.5) (2. maximum power is transferred from zero source impedance. maximum power is transferred into a conjugate matched load. This fact was realized by Thomas Edison or his assistant. maximum power is always transferred into a conjugate matched load1 . At radio frequencies.

7 and 2.11 can be expressed more generally in terms of reactance: Q2 + 1 Q2 Xshn = Xser (2.8) Recalling that ωLser Rshn 1 = = ωRshn Cshn = Rser ωLshn ωRser Cser Q= (2. it is possible to replace a series-connected network with a shunt-connected one.9) we can quickly simplify 2.7) (2. to derive the new component values. —25— . Z = Rser + jωLser = Rshn (ωLshn )2 + jωLshn R2 jωLshn Rshn shn = Rshn + jωLshn R2 + (ωLshn )2 shn (2.1. to replace a series RL network with a shunt one. For example.1 Resonant Impedance Analysis 2.8 to Rshn = Rser Q2 + 1 Lshn = Lser Q2 + 1 Q2 (2.10) (2.11) Equation 2.12) From this we surmise that Q2 Q2 + 1 Cshn = Cser (2. simply equate the shunt and series impedances and solve.13) These series-shunt equivalence relations form the basis for all resonant impedance matching circuits.2 Series-Shunt Transformation If we are interested in the impedance of a two-element passive network only over a narrow frequency range.2.

input resistance is now Rshn . Note that the only the resistance Rload . In this case. it is necessary to instead look into the series port of the network. assuming that the inductor and capacitor are at resonance. the resistance seen across the terminals is Rload . as shown in Fig. leaving shunt transformation. this is not terribly practical. At res. 2-2(a). Figure 2-2: The L-match is derived by series-shunt transformation of one element in a series resonant circuit. 2.13 to the circuit of Fig. the reactances cancel. 2-2(b) also transforms the apparent input resistance. we now see Rshn at the input. 2-2(a). 2-2(c). Transforming the capacitance via equation 2. one could choose any two circuit parameters—Q and Lser . Lser Rser =⇒ Cshn Rload (= Rshn ) (c) As in (b).10 that Rshn must always be larger than Rser .3 The L-Match In the circuit of Fig. selecting both the transformation ratio and operating frequency completely speciﬁes the circuit parameters2 . 2 In principle. When designing an L-match. this circuit is produced by a series-shunt transformation. 2-2(b) must always be larger than that of Fig. Of course.(b) The circuit from (a) after seriesonance.1. Since there are only two en- ergy storage modes in this circuit. the two parameters that are generally speciﬁed are the transformation ratio Rshn Rser and the operating frequency ω. the resulting input resistance is smaller than before transformation. for example—and design the rest of the match. Since we know from equation 2. To transform a large impedance downward into a smaller one. since it is not usually the case that the operating —26— .Useful Techniques for Resonant Circuit Analysis Cser Lser Lser Rload =⇒ Rload Rshn =⇒ Cshn Rload (= Rser ) (a) A series resonant circuit. the input impedance of Fig.

Moreover.10. 2-2(b) and 2-2(c).17) (2. an image resistance can be selected to produce the appropriate overall Q. On the other hand. it is possible to combine several L-matches. an L-match ladder results.2 Higher Order Matching Networks From equation 2.9 then produce the rest of the network: Q ωRshn QRser = ω Cshn = Lser (2. the intermediate impedance(s) serve to reduce the loaded Q necessary at each stage. stepping from the source impedance to one or more intermediate values and then to the load. extreme transformation ratios require impractically large network Q.2 Higher Order Matching Networks While theoretically the L-match allows arbitrary impedance transformations. making a high-pass L-match instead of the low-pass matches depicted in Fig.2.9: 1 ωRser Q Rshn = ωQ Cser = Lshn (2. Since the transformation ratio ﬁxes Q.16) It is also possible to interchange the inductor and capacitor. Once again. To get around this limitation.18) 2. but with only a very small change in impedance. If a very large transformation ratio is required.15) (2. in many practical circumstances it produces a sub-optimal solution.14) Some minimal algebra and equation 2. it is not possible to select the bandwidth of an L-match arbitrarily. we know that Q= Rshn −1 Rser (2. In the frequency is a free parameter to be speciﬁed when designing the matching network! —27— . In the former case. if a very narrow bandwidth is desired. using equation 2.

2.1 The L-Match Ladder When a very large transformation is necessary. as in [26]) or e (based on bandwidth shrinkage arguments. If. at the same time. then connecting the load and source across the appropriate ports. continually adding more stages will inevitably result in decreasing eﬃciency. available component values. the issue of loss may be of particular concern. the required Q is comparable to the QL of the inductor to be used. can be used. each with a transformation ratio K. On the one hand. the tapped capacitor and tapped inductor resonator provide three degrees of freedom. In that case. an upward step is followed by a downward one (or vice-versa). √ as in [24]). it is often not possible to use a single Lmatch stage. the designer may choose to use a tapped resonator for a matching network. most arguments conclude that the optimum gain is either e √ (based on open-circuit time constant analysis. we will use N stages.or Π-matches. Alternatively. In this conﬁguration. for example. required size.and Π-matches. 2. a parallel LC resonator is tapped by splitting the capacitor or the inductor (or both) into two series elements. To do this. increasing the resonant currents and consequently the conduction losses. Like the T.19) A similar argument is often made for bandwidth optimization in a cascade of ampliﬁers. due to loss in the passives) of Qu . In reality.. the optimal transformation ratio per stage approaches a constant value3 . while tapping both yields four. In designing large L-match ladders. —28— . such networks are known as T. a series of L-match stages. and so on). circuit performance will be substantially impaired. it is interesting to note that in the limiting case of an extremely large L-match ladder. So G = KN 3 (2.Useful Techniques for Resonant Circuit Analysis latter. In cases such as this. each doing a portion of the total transformation. e is somewhat more accurate. and unloaded Q (that is. While the optimal solution may change substantially depending on other constraints (e. since in this case the series resistance of the inductor becomes signiﬁcant. each with a constant gain-bandwidth product.g. using fewer stages increases the required loaded Q per stage. Imagine that we want to match two impedances requiring a very large transformation ratio G. loaded Q = QI .

K ≈ 4.diss .20) (2.21) QI is the loaded Q of one stage.diss = EI Qu (2. choosing the principally valued branch.23) (2.24) The total dissipation is therefore NEI = NEtot Qu √ K−1 = Etot Qu QI Qu · ln(G) ln(K) Ediss = (2. stores EI .98 —29— (2.22) If we assume that we are transferring much more power than we are losing (i.2 Higher Order Matching Networks ln(G) ln(K) N = logK (G) = QI = √ K−1 (2.27) The mathematically inclined reader will no doubt note that the solutions to this equation are related to the Lambert W function [27]. the unloaded Q is much greater than the loaded Q).92 QI ≈ 1.2. so we know Energy stored (Energy passed to the next stage) + (Energy lost) QI = (2.28) (2.26) To minimize the loss.e.29) .25) (2.. where EI = Etot QI EI. then each stage delivers approximately the total output energy to the next stage. and loses EI. we diﬀerentiate with respect to K ∂ ∂K Ediss Etot 1 ln(G) [K ln(K) − 2K + 2] √ 2 Qu K ln(2K) K − 1 =− (2.

as depicted in Fig. 2-3(a) and 2-3(b). the image resistance is on the series port. 2. Design proceeds in both cases by ﬁrst choosing (or calculating based on the imposed constraints) the image resistance. The T. composed of two L-matches. While in many practical cases a transformation ratio of 5 per stage is inconvenient. Rload is transformed up to Rimg and then back down to Rin .Useful Techniques for Resonant Circuit Analysis Cser1 Cser2 Rin=⇒ Lshn1 Rimg ⇐⇒ Lshn2 Rload (a) The T-match is formed by two L-matches with the image resistance in the shunt position.2 The T.and Π-Matches If the L-match is unacceptable not because of an impractical transformation ratio but because of an over-speciﬁed design.and Π-matches. which is transformed up to Rin . give the designer another degree of freedom. —30— . then calculating the two resulting L-matches independently. Cser1 Cser2 Rin=⇒ Lshn1 Rimg ⇐⇒ Lshn2 Rload (b) In the Π-match. even in such cases this derivation can serve as a handy rule of thumb: transformation ratios much greater than 25 in a single stage are likely less eﬃcient than an appropriately chosen ladder conﬁguration. the T.and Π-matches are synthesized by putting two L-matches either front to front or back to back. Figure 2-3: The T.and Π-matches provide a solution. Thus. Both allow the designer an additional degree of freedom by transforming up or down to an intermediate or image resistance and then back the other way to the desired resistance.2. Rload is transformed down to Rimg .

i.e. the overall transformation ratio.3 Tapped Capacitor Resonator A departure from transformers based on the L-match. it is almost certainly better to employ an aid such as Matlab or to guess at the overall Q and iterate to the ﬁnal solution. as with any linear network.32) 1 Cser1 Cser2 Cser1 +Cser2 If we were instead to make low-pass networks.31) (2.2. we can freely interchange these as appropriate to a particular design. While it’s possible to then derive an analytic expression for Rimg . I have arbitrarily chosen the input and output ports.2. A few additional equations relate overall network Q to Rimg and to the component values adjacent to Rimg . The analysis of the tapped capacitor match is straightforward: convert Rload into its —31— . and the operating frequency. Q = Qleft + Qright = ω = ωRimg Rimg Lshn1 Lshn2 Lshn1 +Lshn2 (the overall network Q) (for the T-match) (for the Π-match) (2. for example. If we call the Q of the L-matches to the left and right of the image resistance Qleft and Qright .33) (2.30) (2. tapped resonators give three degrees of freedom while allowing in some cases more reasonable component values than the Tor Π-match. the total shunt inductance at the center of the T-match.1.3. the result is truly hideous.34) Since there is an additional degree of freedom. 2. Note that for all of the tapped resonator matches.2 Higher Order Matching Networks The equations for determining the values for the two L-matches are identical to those in section 2. Q = ωRimg (Cshn1 + Cshn2 ) = ω (Lser1 + Lser2 ) Rimg (for the T-match) (for the Π-match) (2. swap the inductors and capacitors. the designer can choose. respectively..

in some cases. then convert that series equivalent to the shunt impedance across C1 . one must take care to remember which Q value is used for each of the transformations.39) (2. more reasonable component values than the T.35) (2. For —32— . Clearly.37) We deﬁne Rload Rin = Q2 + 1 Qleft 2 + 1 Qleft 2 + 1 = C1 Qleft 2 C1.ser Cequiv (2. Of course.41) To design a tapped capacitor match.or Π-match.Useful Techniques for Resonant Circuit Analysis C2 Rin=⇒ C1 Lshn Rload Figure 2-4: The tapped capacitor match gives more freedom than the L-match and. series equivalent. ﬁrst decide which parameters will be set.40) This gives us another expression for the overall network Q 1 ωRser Cequiv Q= (2.36) (2. Qleft 2 + 1 Rin = Rload Q2 + 1 Rload Q= ωLshn Qleft = ωRin C1 (2.ser C2 = C1.38) (2.ser + C2 Rser = C1.

42) (2. Analysis and design of the tapped inductor match proceeds along the same lines as the process for the tapped capacitor network. Once again.45) . A similar process allows us to instead choose Cequiv or Lshn in addition to transformation ratio and center frequency.35 then gives a value for Qleft . To get the value for C2 . 2.43) (2. Qleft 2 + 1 Rin = Rload Q2 + 1 Q = ωRload Cshn Qleft = Rin ωL1 (2. and overall network Q. frequency.41. we can pick the transformation ratio.4 Tapped Inductor Resonator The tapped inductor resonator is very similar to the tapped capacitor resonator in that it allows an additional degree of freedom over the L-match.2 Higher Order Matching Networks L2 Rin=⇒ L1 Cshn Rload Figure 2-5: The tapped inductor match is a close relative of the tapped capacitor match of section 2. example. we use equation 2. This lets us use equation 2.2. Equation 2.2.37 gives us the value for C1 . from which equation 2.44) Again we make some useful deﬁnitions: Rload Rin = 2+1 Q Qleft 2 + 1 —33— Rser = (2.36 to determine Lshn . component values for this circuit may in some cases be more reasonable than those for other third-order matching networks.3.2.

ser + L2 Which leads us to an expression for network Q in terms of the inductors: ωLequiv Rser Q= (2.47) Lequiv = L1. a result of the addition of another energy storage mode.48) 2. in this case. why not tap both? Doing so gives us two degrees of freedom beyond transformation ratio and center frequency. total inductance and network Q. allowing us to choose.5 The Double-Tapped Resonator If we can tap either the capacitor or the inductor in the resonator.46) (2. As in the other resonator matches.51) . the overall network Q is present in neither transformation.2. Q2 + 1 Rin left = Rload Qright 2 + 1 Rin Qleft = ωL1 Qright = ωRload C1 —34— (2. L1.ser = L1 Qleft 2 Qleft 2 + 1 (2.Useful Techniques for Resonant Circuit Analysis L2 C2 Rin=⇒ L1 C1 Rload Figure 2-6: The double-tapped resonator gives an additional degree of freedom beyond the third-order matching networks. Rload goes through two series-shunt transformations to become Rin .49) (2. for example. however.50) (2.

ser = L1 Of course. a dynamically adjustable matching network with appropriate control might allow more optimal operation.57) which lets us simplify equation 2.60) 2.55) Qleft 2 Qleft 2 + 1 Qright 2 + 1 C1. While the fabrication of an adjustable inductor might be possible by using core satu—35— .ser = C1 Qright 2 ω (L1.53) (2.59) (2.54) 1 1 + C1.ser Rser 1 = ωRser C1.55 slightly: 1 ωL2 = Qright + Rser ωRser C2 Q = Qleft + (2.ser C2 (2.58) It is useful to note that Rin Qright 2 + 1 − 1 Rload Rload Qleft 2 + 1 − 1 Rin Qleft = Qright = (2. we can also say ωL1.52) (2.ser + L2 ) 1 = Q= Rser ωRser L1.56) (2.3 Active Impedance Matching A system involving a dynamically changing load or source impedance may not be amenable to the static matching networks heretofore discussed.ser Qleft = Qright (2.2. In these cases.3 Active Impedance Matching Deﬁne Rload Rin = 2 Qright + 1 Qleft 2 + 1 Rser = (2.

so-called varactors (shortened from “variable reactor”) are often used in the tuning circuits of. such a device would almost certainly suﬀer at very high frequencies from the eﬀects discussed in section 1. ration characteristics. it might easily be supplied by a simple feedforward network (perhaps relating the matching network’s characteristics to supply voltage) or by the error signal from a phase-locked loop [30. 29]. On the other hand.Useful Techniques for Resonant Circuit Analysis Lser D1 D2 Vc Cshn Rin=⇒ Rload Figure 2-7: Diode junction capacitances can be used to obtain a controlled L-match. The use of diodes as nonlinear capacitors is a wellknown technique. —36— . By changing the value of Vc .1. e. adjustable capacitors are readily available: the junction capacitance of a reverse-biased diode varies as a (very nonlinear) function of voltage. Figure 2-7 shows one possible active matching implementation.5) [29].61) where Cj0 is the zero-bias junction capacitance. In this circuit. as in [28]. Vφ is the built-in potential (generally around . preventing the input from shorting to Vc . 31] or delay-locked loop [32]. m = . the junction capacitance of the diodes can be changed.g. two diodes are used to ensure that one always remains reverse biased. A DC voltage Vc applied as shown controls the shunt capacitance..1. Junction capacitance as a function of reverse voltage Vr can be modeled as Cj = Cj0 1+ Vr Vφ m (2. Since Vc is a DC value. and m is a constant determimined by the doping gradient at the junction (for an abrupt junction. FM receivers [24.5 Volts).

it is necessary to establish an operating point and design a matching network at that operating point. however. doing so reduces the accuracy of the expression (by a substantive amount in many cases) and simultaneously —37— . unfortunately.Chapter 3 Computational Techniques for Nonlinear Circuits 3.1 Motivations for Computational Analysis ECHNIQUES were developed in chapter 2 for the matching of linear networks with known input and output impedances. the operating point changes with the addition of the matching network! In chapter 4. to make the Fourier analysis tractable. this approach is of limited use in practical designs. a diode might be treated as a switch in parallel with a linear capacitor). e.g.. In order to match these networks. idealization of the nonlinear circuit elements is required (for example. Fourier analysis and describing function methods are used to derive an expression for the input impedance of a rectiﬁer circuit under speciﬁed conditions. First. nonlinear resonant networks present an additional challenge: their input impedance is dependent on the conditions under which they operate. In many cases. While this is extremely useful. Unfortunately. It is certainly possible to design a matching network using such an expression. when T matching a power ampliﬁer to an antenna.

the computational approaches developed in this chapter may still be of some use. One might choose. however. Moreover. curves of constant impedance versus power might be generated and used for fast initial estimates1 . a linearized model of the input For those who feel this verges too closely on the Red Rubber Ball school of engineering. Given the FFT results for input voltage and current. 1 —38— . since the particular nonlinear network under consideration could produce substantial harmonic distortion. especially given the inherent inaccuracies in the analysis. the input impedance should be considered in a describing function [24. in cases where back-of-the-envelope designs are desirable. a convenient solution to this problem presents itself: for a sinusoidal drive. This solution is of particular value because almost any circuit simulation package can measure node voltages and branch currents. 34] sense—that is. given a particular topology. 3. the deﬁnition of input impedance is not altogether clear. For example. for example. only components of the voltage and current at the fundamental frequency contribute to the input impedance. Once these are obtained. the time spent in deriving an analytic expression may be considerably more than is warranted. to deﬁne the input impedance as Zin = Vin Iin instantaneously. that the value of this expression would ﬂuctuate with time. It is quite likely. thus.Computational Techniques for Nonlinear Circuits makes error analysis diﬃcult. Recalling that under sinusoidal excitation power can only be transferred at the fundamental frequency. the development of a more accurate and much faster computational approach is a signiﬁcant step forward in the design of nonlinear resonant networks such as rectiﬁers. For these reasons. 35].2 Nonlinear Network Impedance Considerations When driving a nonlinear circuit. the fundamental magnitudes and phases can be computationally determined via a simple fast Fourier transform (FFT) calculation [25. a quick comparison between the results produced with Fourier/describing function analysis and those produced by computational methods should be suﬃciently convincing. Some hesitation to abandon pencil-and-paper engineering in favor of a computational crutch is understandable. 33.

respectively.ω0 Iin. the model is represented by Fig.ω0 =⇒ Rin.ω0 (3. 2 —39— .4) Otherwise. input impedances will be assumed to be in the describing function sense when appropriate throughout the rest of this thesis.ω0 = (3.ω0 = (3.ω0 Cin.ω0 } If the reactance Xin.ω0 notation will be dropped in favor of simply Rin .3) Rin. Even after we have computed the input impedance via the aforementioned method.ω0 .2 Nonlinear Network Impedance Considerations Lin.ω0 = Vin.ω0 Zin.ω0 is positive. (b) Input impedance model for negative reactance. 3-1(b) with 1 ω0 Xin.5) Note that we can instead represent these input impedances2 as parallel RL or RC networks via the transformations discussed in section 2.ω0 } Xin. care For brevity’s sake.ω0 = ℑ {Zin. then the linearized model corresponds to Fig. then Zin. input impedances are assumed to be at the fundamental frequency unless otherwise speciﬁed.ω0 Zin.ω0 ω0 Lin.ω0 and Iin.3.1) (3. Thus. 3-1(a) where Xin. If we call the fundamental voltage and current Vin.ω0 (a) Input impedance model for positive reactance.1.2) (3. the Rin.ω0 Cin.2.ω0 = ℜ {Zin.ω0 =⇒ Rin. Figure 3-1: Linearized input impedance models. impedance is easily constructed.

This requirement presents a particular diﬃculty when attempting to design a matching network: if we wish to make a conjugate match between source impedance and linearized input impedance. Clearly the impedance viewed from the input of the nonlinear circuit looking back towards the source must remain the same. thus. nothing may change. of course.3 The Iterated Approach The problem of calculating input impedance from a conjugate match can be circumvented by iterating the calculation procedure. 3. Due to the linear nature of the resonant impedance transformers we are designing. To begin. That is.3. in order to achieve a conjugate match at the established operating point. we must insert an appropriate matching network and at the same time keep constant the apparent source impedance. . this procedure applies equally for a capacitive input impedance). we require that looking back into the matching network from the nonlinear network’s input we see the same impedance that was used to calculate the linearized input impedance. our goal is to choose Rs = Ri and Xs = −Xi (for this example.1 Basic Iterated Matching Taking as an example Fig. we choose a source impedance somewhat close to the conjugate of the expected input impedance value. In addition. we set Rs = Ri and —40— 1 ωCs = ωLi . we assume that the input impedance looks inductive. the transformation ratio looking into the network from one side is the reciprocal of the ratio looking into the other side. the calculation of the source impedance must have been from a conjugate match in the ﬁrst place—requiring that we knew (or were extremely lucky in guessing) the input impedance before calculating it! 3. After simulating the circuit and calculating the input impedance value. ensuring that the total power throughput remains constant guarantees that the input voltage and current to the nonlinear network do not change.Computational Techniques for Nonlinear Circuits is necessary to ensure that our calculations remain valid: from the nonlinear network’s point of view. 3-2(a).

3). we are cancelling it and matching only the input resistance.(b) After Rs and Cs are conjugate matched with Ri atively selecting Rs and Cs .3. then repeat the simulation. Cs cancels Li and Ri is transformed to Rs2 . This time. a matching network can be inserted without changing the apparent source impedance Figure 3-2: A demonstration of the iterated impedance matching approach. Not only is this a waste of usable reactance. the desired source impedance.3. Once the appropriate Rs and Cs are chosen and Ri and Li calculated. we will arrive after several iterations at a conjugate match between Zs and Zi . Figure 3-3(a) shows another possible matching conﬁguration for the circuit of Fig. 3. Looking towards the source. the choice of appropriate values for Lser and Cshn gives an equivalent Cs looking back from the input port of the —41— . nevertheless. This situation is easily remedied with judicious application of series-shunt transformations. it is also likely an eﬃciency hazard: the use of series resonant cancellation causes large resonant currents as energy passes back and forth between inductance and capacitance.3 The Iterated Approach Rs Cs Li Rs2 Cser Cs Li Vs Ri Vs Lshn Ri Input Impedance L-Match Input Impedance (a) A conjugate match is achieved by iter. this circuit is not optimal: instead of utilizing the input reactance of the nonlinear circuit. From the point of view of the source. a matching network can be inserted between Rs and Cs .2 Improved Iterated Matching While matching has now been achieved. Cs is not explicitly present. 3-2(a). Neglecting issues of convergence for the moment (these will be discussed in section 3. and Li . the nonlinear network sees Cs in series with Rs2 transformed by the matching network—the same values used to calculated Li and Ri . likely resulting in additional conduction loss.3.

Rs Cser Lser Li Vs Ri L-Match Input Impedance (b) Analysis of the new matching network is aided by series-shunt transformation of Cshn and Rs2 into Cser and Rs Figure 3-3: An improved matching network for the circuit of Fig.Computational Techniques for Nonlinear Circuits Rs2 Lser Li Vs Cshn Ri L-Match Input Impedance (a) Utilizing the input reactance of the nonlinear circuit in the matching network results in improved efﬁciency. 3-3(a) into a series network as pictured in Fig. 3-3(b). ﬁrst transform Fig.8) (3. 3-2(a). nonlinear network while creating a matching network that utilizes the reactance of Li . To calculate these values for a chosen Rs2 .6) (3.9) Looking back from the input of the nonlinear network.7) (3.10) . Rs = Ri Qm = Cshn Lser Rs2 1 −1= = ωRs2 Cshn Rs ωRs Cser Qm 2 = Cser Qm 2 + 1 1 = 2 − Li ω Cser (3. we see a reactance 1 ωCser —42— Xs = ωLser − (3.

The same method can be used to design a third-order network by ﬁrst choosing the constraints and calculating the image resistance (Rimg for the T. Circuits where there are several switches with independently-determined operation such that there are multiple switching conﬁgurations that can lead to the same behavior (such as the polyphase rectiﬁers analyzed in [36]) are likely to be problematic. all the reactances cancel. viewed from the source. The rectiﬁers explored in chapters 4 and 5 were empirically determined to have this property. 3.3 Convergence of the Iterated Matching Procedure A suﬃcient (though not necessary) condition for convergence is monotonicity of the variation of input impedance magnitude and phase with source impedance. many multi-switch circuits do not have this property: a series diode rectiﬁer with a shunt ﬂyback diode enforces a well-known relationship between the switching behavior of the two active devices. On the other hand. deterministic function of source impedance and power throughput. leaving just Ri series-shunt transformed by the matching network. Thus. On the whole.12) so the nonlinear network sees the same conditions as in Fig. Design then proceeds by determining the half of the matching network that transforms Ri to the image resistance and then computing the remaining values to transform the image resistance to the desired source resistance. a conjugate match is achieved without unnecessary impedance cancellation. Of course. A more general requirement is that input impedance be a ﬁxed. the slopes of the source and input impedances are directly or inversely related such that a change in source impedance always produces a change in the same direction (though not necessarily of the same magnitude) in the input impedance.3 The Iterated Approach = −ωLi = 1 ωCs (3. or Rser in the case of the tapped resonators).3.3.11) (3.and Π-matches. it is overwhelming likely that any network consisting of only one nonlinear —43— . That is. 3-2(a).

the input impedance and its conjugate are calculated. it is not completely general: it assumes that the input impedance is inductive. In the circuits tested. convergence may depend on the initial impedance guess. First.Computational Techniques for Nonlinear Circuits element will converge when using this method. it provides an initial guess at source impedance. —44— . easily generalized. In circuits with multiple switches but where state transitions depend on a common variable this method is also likely to succeed. of course. and the appropriate circuit elements are modiﬁed. 3. Full code is provided in appendix A. Iteration continues until the input impedance is matched to within the speciﬁed tolerance. For more exotic cases. SAMwIICh uses the HSPICE circuit analysis package to simulate circuits and do FFT analysis [37]. it then performs the initial simulation run. a fully automated matching system named Software for Automated Matching with Iterated Impedance Calculations 3 (SAMwIICh) was developed. since in all cases of interest this happened to be true. Since SAMwIICh was developed expressly for use on the circuits discussed later. no stable limit cycles were encountered. This was not implemented because it makes the system more susceptible to the eﬀects of nonmonotonicity. correcting this would require code to detect oscillations and reduce step size 3 Thanks to Jim Paris for his help in deciding on a name and for suggestions on how not to reinvent the wheel. this is.1% tolerance. guess at the ﬁnal value. Fourier analysis as in chapter 4 could be used in conjunction with this technique to produce an initial guess from which iteration would likely converge on an accurate value. fewer than ten iterations were necessary in almost all cases. From FFT data. convergence proceeded smoothly from the initial guess to the ﬁnal value. in such cases. For single-diode rectiﬁers and 0.4 SAMwIICh: An Automated Matching Implementation For the purposes of design in the proceeding chapters and to verify the usefulness of iterated impedance matching. One possible modiﬁcation to SAMwIICh to speed convergence would be slope extrapolation: given the values of one or more previous iterations.

4 SAMwIICh: An Automated Matching Implementation or even turn oﬀ prediction entirely.3. —45— . Moreover. the observed convergence behavior did not seem to warrant this modiﬁcation.

.

an experimental implementation is examined. However. Both of the rectiﬁers considered. and problems of convergence when using SAMwIICh (section 3. 15. Finally. 20. 38].Chapter 4 The Series Resonant Rectiﬁer T HE FIRST topology to be considered is the series resonant rectiﬁer [19. employ only one diode. is followed by veriﬁcation of the model by simulation of a demonstrative design. While multi-diode rectiﬁers for RF operation have been proposed [14. those interested in such a derivation should consult [38]. 4. 4-1. For the purposes of —47— . in this chapter and in the next. it will be useful for later discussion to note Kazimierczuk and Czarkowski’s results.1. would likely decrease eﬃciency.2 are then considered. Discussion of an analytic model of rectiﬁer operation. analysis of these circuits is simpler than those involving multiple diodes. including Fourier analysis of input impedance. pictured in Fig. 19]. the performance of the rectiﬁers examined was high enough that the inclusion of additional diodes seemed unnecessary and. Moreover.1 Analysis of the Series Resonant Rectiﬁer A detailed derivation of the analytic model of the rectiﬁer would be voluminous and redundant.4) for computational analysis are seemingly nonexistent with single-diode rectiﬁers. indeed. The strengths and weaknesses of this topology as a candidate for employment in the DC-DC converter architecture described in section 1.

an ideal diode with a constant parallel capacitance is assumed. the derivation.6) .1) It is useful to deﬁne Vi Vrms = √ 2 Vo MVR = VRMS iO = iD + iC RL = Vo iO (4.2) (4.3) (4. Ls C d For ease of derivation. In addition. the diode is assumed to be oﬀ 0 ≤ ω0 t ≤ 2π (1 − D). φ deﬁnes the phase relationship between the input voltage and the state of the diode.4) (4. output ripple is neglected.5) Thus. vI = Vi sin(ω0 t + φ) (4. RL = ω0 Cd RL ω0 L s —48— Q= (4. and the circuit is assumed to be driven at the resonant frequency √ 1 .The Series Resonant Rectiﬁer Cd iC iL Ls + vL − + vC − D iD + − Vo + vD − Vi Figure 4-1: The series resonant rectiﬁer.

4. If we assume the network —49— . For 0 ≤ ω0 t ≤ 2π (1 − D). this derivation closely follows that of [38].8) (4. this means that we can once again construct a linearized input impedance model.11. once again.11) (4. To model the series resonant rectiﬁer’s input impedance.7) (4.7 and 4. 4-2 allows us to quickly identify the resistive component of input current.10) (4. We can do this by applying the Fourier integral [25] to equations 4.2.2 Fourier Analysis of Input Impedance Zi =⇒ Ri Li Figure 4-2: A parallel RL model for series rectiﬁer input impedance. During this time.9) 4. we must ﬁnd the fundamental component of input current. vL = Vo 2 sin(ω0 t + φ) −1 MVR √ MVR (ω0 t − 2π) iO Q 2 √ cos(φ) − cos(ω0 t + φ) − iD = MVR 2 √ (4. √ iO Q ω0 t sin(ω0 t + φ) + sin(φ) − MVR 2 sin(ω0 t) 2MVR cos(φ) sin(ω0 t) − ω0 t cos(ω0 t + φ) √ + cos(ω0 t) − 1 vC = vD = Vo MVR 2 √ Vo 2 ω0 t cos(ω0 t + φ) cos(φ) sin(ω0 t) vL = + MVR 2 2 MVR cos(ω0 t) + sin(φ) − √ 2 iL = iC = √ The diode conducts during the interval 2π (1 − D) < ω0 t ≤ 2π. Expressing the input impedance in terms of a parllel RL circuit as in Fig. the condition of sinusoidal drive means that power is only transferred at the fundamental drive frequency.2 Fourier Analysis of Input Impedance As argued in section 3.

21) —50— . Ri = Ro MVR 2 (4.16) where 3 π(1 − D) π(1 − D) cos(2πD) − sin(2πD) sin(2πD) − 8 2 2 5 π(1 − D) b = sin(2πD) − sin(4πD) − cos2 (2πD) 16 2 π(1 − D) c = [1 − cos(2πD)] cos(2πD) + sin(4πD) 2 cos(2πD) d = 2πD cos(2πD) − π(1 − D) − 1 + sin(2πD) 2 sin(2πD) − 2πD sin(2πD) e = 1 − cos(2πD) + 2 a= (4.13) We can then ﬁnd the current through the inductor by computing 1 2π iL cos(ω0 t + φ)d(ω0 t) π 0 √ √ √ Vi 1 Vo 2 Ro iO 2 Ls iO 2 = = = =Q ω0 L i ω0 Li MVR ω0 Li MVR Li MVR ILin = − (4.14) (4.The Series Resonant Rectiﬁer is lossless. That is.18) (4.17) (4.15) After a substantial amount of math.20) (4. then the resistance of the parallel RL model must be the output impedance reﬂected through the ratio of input to output voltages.19) (4. then Vi sin(ω0 t + φ) − ILin cos(ω0 t + φ) Ri iIN = (4.12) If the input voltage vIN = Vi sin(ω0 t + φ). we arrive at the ratio 1 Ls = Li π π(5D − 1) − a · sin2 (φ) − b · cos2 (φ)+ 4 MVR + c · sin(φ) cos(φ) + √ [d · sin(φ) + e · cos(φ)] 2 (4.

4.2 Fourier Analysis of Input Impedance

As mentioned previously, this derivation makes two signiﬁcant assumptions: ﬁrst, that the diode is ideal, and second, that the capacitance across the diode is constant over a cycle. At radio frequencies, it is unlikely that we would put additional capacitance in parallel with the diode, electing instead to use the junction capacitance of the diode to provide Cd . Recalling from section 2.3 that diode junction capacitance is a strong function of voltage, it is clear that some care is needed in choosing the appropriate capacitance value. In order to make use of our analysis with a nonlinear capacitance, we will assume that we must replace the linear capacitor with a nonlinear capacitance that stores the same average energy each cycle. Preserving the average stored energy keeps the resonant operation closest to the behavior predicted by the model, since it preserves average inductor current, thus preserving average output current. Since we have ﬁxed the output voltage of the circuit for the purpose of analysis, preserving average output current keeps output power constant. Moreover, as power is only transferred at the fundamental frequency, keeping output power constant means that the input characteristics at the driving frequency are unchanged. Thus, macroscopic operation of the circuit is preserved1 . To calculate a ﬁrst-order estimate of the equivalent linear capacitance for a given diode, the voltage waveform from equation 4.8 is applied to the capacitance function in equation 2.61. This produces capacitance as a function of time, from which energy is quickly calculated: C(t) [V(t)]2 E(t) = 2 The equivalent capacitance is then easily found: E(t) [V(t)]2 (4.22)

Cequiv =

(4.23)

Note that this derivation assumes that the addition of a nonlinear capacitance does not change the voltage waveform across the diode. While this assumption is not completely

1 Further discussion of the use of nonlinear capacitance in resonant radio frequency circuits can be found in [39, 40].

—51—

The Series Resonant Rectiﬁer

accurate, it is nevertheless reasonable for a ﬁrst-order estimate. Precise derivation of voltage waveforms can be found in [39–41].

4.3

Comparison of Analytic Model with Simulation

In order to determine the usefulness of the analytic model, a rectiﬁer circuit will be designed by the process described in [38] and then simulated. Predicted input impedance and output power will be compared to simulated results. Since the circuit parameters are easiest to determine at D = .5, we will choose this operating point for our test case. The rectiﬁer will run at 100 MHz and provide 5 W into 5 V, meaning that Ro = 5 Ω. From [38] page 105, D = .5 gives Q ≈ .3884 MVR ≈ .3684 Thus, √ Vo 2 = 19.19 V Vi = MVR The necessary inductance and capacitance are Ro = 20.5 nH ω0 Q Q = 123.6 pF Cd = ω0 Ro Ls = The analytic model predicts that (4.24) (4.25)

(4.26)

(4.27) (4.28)

Li = 16.42 nH Ri = 36.83 Ω Q = 3.6 —52—

(4.29) (4.30) (4.31)

4.3 Comparison of Analytic Model with Simulation

**Table 4.1: Input impedance, output power, and eﬃciency, calculated versus simulated.
**

Parameter Po Ri Li η Calculated 5W 36.83 Ω 16.42 nH 100% Simulated, Ideal Diode 4.99 W 38.86 Ω 15.72 nH 100% Simulated, Real Diode 4.95 W 33.5 Ω 16.02 nH 89.2% Simulated, Conjugate Match .66 W 3.78 Ω 6.6 nH 91.3%

or, for the series RL model,

Li,ser = 15.12 nH Ri,ser = 2.64 Ω

(4.32) (4.33)

Table 4.1 compares the computed results with those obtained in three HSPICE simulation runs (netlists for these simulations are available in appendix B.1). In the ﬁrst simulation, an ideal diode in parallel with a linear capacitor was employed. In the second, the ideal diode was replaced by a real diode model, though still with a linear capacitance. Finally, in the third simulation, the rectiﬁer was driven from a conjugate match. As expected, the input impedance of the rectiﬁer changed substantially with the addition of source impedance, resulting in severely reduced power throughput. The slight increase in eﬃciency is a result of reduced conduction loss because of lower average output current; this is an illusory improvement, since we have sacriﬁced almost a factor of ten in output power in order to gain two percent “improvement” in eﬃciency. The results of the third simulation highlight the need for a model including an arbitrary source impedance, which would allow the input impedance to be calculated for a conjugate match as described in section 3.2. This idea is unattractive for two reasons: ﬁrst, the precision of the calculations for a range of real diodes is likely to be poor, and second, the eﬀort involved in this calculation would only be useful for a single topology—parasitics would require explicit consideration and would complicate the model considerably. A more —53—

the performance of the series resonant rectiﬁer is good when applied under appropriate conditions: eﬃciencies approaching 90% were obtained using a realistic model of diode loss. to wit. Design can proceed much more quickly without the need for special provisions for nonlinear capacitance. and passive component loss. all or part of Ls can be transformed into Lshn . in such cases. none of which the analytic model considers.2. This may cause problems in some applications.g. diode drop.The Series Resonant Rectiﬁer Cd Ls D + − Vo Vi Lshn Figure 4-3: To provide a DC current path. e.. since there is now a path for DC output current through the shunt inductor. the series rectiﬁer is a design with signiﬁcant practical potential. a computational approach can take into account additional parasitics (such as those present on a printed circuit board) with only the eﬀort required to modify the circuit description ﬁle. 4-3. Moreover.3.3.4 Application of the Series Resonant Rectiﬁer As demonstrated in section 4. there is no path for DC current to ﬂow to the output. 4. As argued in section 4. when driven by a class-E inverter topology employing a series resonant output tank. a source with high DC impedance can be used. the iterated computational approach. thus. the use of a nonlinear capacitor should not change circuit operation substantially. —54— . attractive alternative has already been suggested in section 3. This limitation can easily be overcome in practice by transforming all or part of Ls to its shunt equivalent as illustrated in Fig. One limitation of the resonant rectiﬁer not yet discussed is that it must be driven from a low DC impedance.

Using such techniques. Unfortunately. Fig.5 Experimental Implementation Cd Lpkg D Vi Lshn Cout + − Vout Figure 4-4: Experimental implementation of the series rectiﬁer. these structures also tend to increase forward drop. the reverse voltage stress on the active device is quite high. the computational model is of great assistance. 4. As an alternative to using high-voltage devices. Since this topology involves resonant operation.4. Going from a low voltage diode to one with a higher reverse voltage rating has some practical eﬀects worth considering: in most cases. 2 —55— . In this case. reducing eﬃciency2 . requiring the use of diodes with high reverse voltage ratings to withstand the voltage developed on Cd each cycle. the selection of a high voltage diode to obtain the junction capacitance prescribed by the analytic model could cause a reduction in eﬃciency. Topologies of this nature would allow greater device utilization and enjoy enhanced eﬃciency. since higher harmonic content is used to achieve square switching waveforms.5 Experimental Implementation The series resonant rectiﬁer was implemented in the DC-DC converter in [10]. 4-4 shows the rectiﬁer as implemented. with component values and part numbers listed in In some designs. since lower voltage diodes (with lower forward drops) could be employed. Both of these processes have the eﬀect of reducing junction capacitance. since the diode is eﬀectively placed in series with its guard structure. high reverse voltage rating is achieved with the addition of guard rings or with a metal-overlapped laterally-diﬀused process (see [41] and references therein). resonant operation can be utilized with reduced voltage stress. topologies might be derived from the series resonant rectiﬁer which exploit the multi-resonant structures designed and implemented in [42]. since it may be applied to designs which utilize the increased capacitance of a lower voltage diode.

—56— .5 pF 12. Circuit Element D Lpkg Cd Lshn Cout Nominal Value 1 nH Cj0 = 318.1.2. Overall eﬃciency of the radio frequency power converter cell was greater than 75% from 16 V DC input to 5 V DC output.The Series Resonant Rectiﬁer Table 4.2: Component values used in the series rectiﬁer experimental implementation. a high DC output impedance is extremely important to ensure proper current sharing between parallel converters.5% of average. in addition to high eﬃciency and well-characterized input impedance. In the experimental implementation. Simulation results (netlist provided in appendix B. the output current of eight parallel cells under maximum load was matched to within ±6. Rectiﬁcation eﬃciency was around 85%.2. 50 V Table 4.2) suggests that output impedance ranges from 20 Ω at light load to 5 Ω at maximum load.3 is likely a result of ﬁnite inductor Q. the discrepancy between experimental eﬃciency and that calculated in section 4. As discussed in section 1.5 nH 9 × 47 nF Part Number MBRS1540T3 Diode package parasitic Diode junction capacitance Coilcraft A04TJ X7R Ceramic.

In addition. 43]. the use of the coupled magnetic structures similar to those presented in [21.Chapter 5 The Shunt Resonant Rectiﬁer T HE SECOND topology considered is the shunt resonant rectiﬁer [7. 22] is examined. 5.1 Analysis of the Shunt Resonant Rectiﬁer The shunt resonant rectiﬁer is essentially the dual of the traditional class-E inverter. —57— . This chapter proceeds in much the same fashion as the previous one: an analytic model is developed and compared to simulation. Stated more precisely. 19]. accompanied by simulation and experimental results. 5-1. This rectiﬁer. employs a diode in the shunt position. the shunt rectiﬁer as analyzed here is the bilateral inverse of the classCser Lser + Vi D vD − Cd Cout Lchoke iO + − Vo Figure 5-1: The shunt resonant rectiﬁer. it is in essence the dual of the traditional class-E architecture [16. and an experimental implementation is presented. practical concerns are discussed. pictured in Fig. 18.

Hence. A particularly good analysis of the class-E inverter.6) (5.7) (5. − cos(y) ξ π cos(y) − 1 + y = πD ξ= 1 dvD Vo dθ where the conduction angle y is centered at ω0 t = and φ deﬁnes the phase between the input voltage and the state of the diode. following [45].1) (5.4) π 2. Since this means that the rectiﬁer operating waveforms are exactly timereversed copies of the class-E waveforms.8) (5. analysis of this circuit is easily obtained by slight modiﬁcations to the standard class-E inverter analysis.10) y cos(φ) sin(y) 2 Vi ≈ Vo g g= The susceptance of Cd is given by 2 y 2 + yg sin(φ − y) − g sin(φ) sin(y) πg 2 r —58— B = ω0 Cd = (5.9) (5.5) (5.11) .3) (5. appears in [45]. so Io = iO ≈ iO Po = Vo Io Ro = Vo Io 2Ro r= 2 g (5. the output current is approximately constant.2) sin(y) (5. Assuming Lchoke is large. As required by bilateral inversion. the rectiﬁer duty cycle D = (1 − Dinverter ). we deﬁne vI = Vi sin(ω0 t + φ) tan(φ) = sin(y) y ξy π (5.The Shunt Resonant Rectiﬁer E circuit [44]. and the one from which the following is derived.

16) (5. however. The derivation of an analytic expression for input impedance is not presented.14) where ω1 = −2g sin(φ − y) sin(y) − 2y sin(y) ω2 = 2y cos(y) − 2 sin(y) ω3 = −g sin(y) cos(y) (5.. a procedure largely similar to the one in section 4. Q might be chosen for.2 could be used. Whereas in the design of RF ampliﬁers. and Po .15) (5. and is given by ω1 sin(φ) + ω2 cos(φ) + ω3 cos(2φ) + gy ω2 sin(φ) + ω3 sin(2φ) − ω1 cos(φ) tan(ψ) = (5.12) (5.13) ψ represents the additional reactance angle which eﬀectively cancels Cd . —59— . Were such an expression desirable. D. Vo .1 Analysis of the Shunt Resonant Rectiﬁer The input tank components. that such a model would fare well in the face of nonidealities and unmodeled parasitics. ξ.17) These equations allow the design of a shunt rectiﬁer for a given Q. in this case Q is in practice generally chosen such that the input tank serves as the impedance matching network after a suitable series-shunt transformation of one of the tank elements. since it was shown in the previous chapter that such an expression is of little practical value. Cser and Lser . e.g. It is unlikely. output spectral purity. are given by 1 ω0 Qr (Q + tan(ψ)) r = ω0 Cser = Lser (5.5.

1: Output power and eﬃciency.4 V (5.20) (5. Parameter Po η Calculated 5W 100% Simulated.3: Vo = 5 V.862 r = 2. and arbitrarily select Q = 5.22) We then calculate Cd = 101.5669 g = 1.1 compares calculated values for output power and eﬃciency to simulation results with an ideal diode and with a diode model that accounts for forward drop but still has —60— . We choose ξ = 0. D = . since in practice optimal eﬃciency is obtained at this point [45].32 pF Cser = 110.2 Comparison of Analytic Model with Simulation To verify that the analytic model derived in section 5. The design equations yield φ = −0.26) Table 5.8561 (5.1 is valid.19) (5.24 nH Vi ≈ 5.06366 ψ = .884 B = . Ideal Diode 5W 100% Simulated.23) (5. we will design a rectiﬁer to the same speciﬁcations as in section 4.24) (5.The Shunt Resonant Rectiﬁer Table 5.5.7% 5.25) (5.21) (5. Real Diode 1. f0 = 100 MHz. calculated versus simulated. Po = 5 W.18) (5.4 pF Lser = 28.12 W 89.

This likely results from the fact that the diode forward drop is considerable compared to the diﬀerence between Vi and Vo . While the analytic model is tolerant of some amount of ripple. it is tolerant of a range of input impedances without modiﬁcation. In practice. in such cases.5 explores the latter eﬀect in detail. the computational approach is certain to be preferable. it appears in series with Cd when the diode is oﬀ. including its mitigation through the use of coupled magnetic structures of the kind described in [21. and it is generally desirable to make it as small as possible for a given application. and the DC loop. shunt transformation of one of the elements of the input tank is likely still desirable.5. the value of a computational approach is highlighted by the shortcomings of the analytic model. containing the diode. The analysis of section 5. adding with Lser and resulting in a larger eﬀective tank inductance. —61— .3). including the input tank and Cd .1 makes the assumption that a “large” choke inductor is used and ignores the choke inductor thereafter. Once again. it is unlikely that model accuracy will be good with a current ripple that is greater than 10% of DC output current. since the input tank can then be used to interface the source and input impedances. When using the input tank elements in this way. however. the addition of an inductance in series with the diode has two eﬀects: ﬁrst. second. Section 5. Hence. the use of the more realistic diode model is problematic. 5. Also neglected in the foregoing analysis is any package inductance appearing in series with the diode. since it is ﬁxed by the ratio of source to load impedance. and the load. Lchoke . the shunt resonant rectiﬁer provides its own DC current path. since it appears in both the AC and DC loops. the designer no longer has a choice of Q. While the ideal diode gives reasonable results. the size of the choke inductor is dictated by ripple requirements.3 Application of the Shunt Resonant Rectiﬁer a constant junction capacitance (HSPICE netlists are provided in appendix B. 22]. it has the eﬀect of coupling additional ripple into the output. As mentioned earlier. Practically.3 Application of the Shunt Resonant Rectiﬁer Unlike the series resonant rectiﬁer. It is convenient when considering the package inductance to break the circuit into two loops: the AC loop.

after computing the matching parameters. following the procedure outlined in section 3.The Shunt Resonant Rectiﬁer Rm Cc Lser Lchoke + − Vs D Cd Cout Vo (a) First. First. Figure 5-2 illustrates the procedure for computing the appropriate matching network values. the matching network serves as the input tank. and combining Lm and Lser into Ltot (Fig. it is convenient to replace the input tank with only an inductance having a reactance approximately twice that of Cd . 5-2(a)). Cc is replaced with a series transformed L-match comprising Cm and Lm . Figure 5-2: The computationally-assisted design process for the shunt resonant rectiﬁer. When using iterated computation to design the shunt resonant rectiﬁer.2. Rs Ltot Lchoke + − Vs Cshn D Cd Cout Vo (c) Finally. Rm and Cm are shunt transformed and Lm and Lser are combined into Ltot . 5-2(c)). an L-match which has been series transformed can be inserted in the place of Cc (Fig. ω0 2 Cd and Rm and Lchoke + − Vs D Cd Cout Vo (b) Next. Rm Cm Lm Lser 2 . determine Rm and Cc by iteration such that they form a conjugate match with the rectiﬁer circuit (Fig. —62— . Next. the input tank is replaced by Lser ≈ Cc are determined by iterated computation. 5-2(b)). The ﬁnal design is reached by shunt transforming Cm into Cshn and Rm into Rs .3.

a test rectiﬁer was implemented.4 Experimental Implementation 19 40 λ Lser Lchoke Rs Z0 Vi Cshn Cd Lpkg Cout D + Vo − Figure 5-3: Experimental implementation of the shunt rectiﬁer. no manual or other reference is available.3 W into 5 V from a 100 MHz sinusoidal excitation. The transmission line at the input of the rectiﬁer 1 Due to the age of the General Radio equipment and the circumstances under which this unit was obtained (I found it abandoned in a hallway!). with component values listed in Table 5.2: Component values used in the shunt rectiﬁer experimental implementation. It is worth noting that.5. 50 V Ampliﬁer output impedance Belkin 8240 RG-58A/U coax.2.5 Ω Part Number 20CJQ060 Diode package parasitic Diode junction capacitance CDE MC12FA560J Coilcraft 1812SMS-39NJ Coilcraft 1812SMS-R12J X7R Ceramic.4 Experimental Implementation To verify the results of section 5.1 V Zener diodes in parallel with a bulk capacitance comprising two 15 µF tantalum capacitors. Figure 5-3 illustrates the rectiﬁer implementation. and the rectiﬁer was loaded with ﬁfteen 1 W. in addition to producing all manner of RF signal and noise generators. The rectiﬁer provides 3. 95 cm 5. Table 5. 5. —63— .1 and the application of iterative matching as described in section 5. Circuit Element D Lpkg Cd Cshn Lser Lchoke Cout Rs Z0 Nominal Value 2 nH Cj0 = 145 pF 56 pF 39 nH 120 nH 9 × 47 nF 50 Ω 51.3. More information on this very interesting company can be found in [46]. the General Radio Company invented the Variac variable autotransformer. Radio frequency input was provided by a General Radio Company Model 1363 VHF Oscillator with a Model 1264-B Modulating Power Supply1 driving an Ampliﬁer Research Model 10W1000 power ampliﬁer [47].

a center tapped magnetic structure is a good choice. Lpkg has two main eﬀects: ﬁrst.3. 5-4. it adds to Lser and acts as part of the AC loop while the diode is oﬀ. As brieﬂy mentioned in section 5. which has the additional eﬀect of coupling additional AC current into the output. we will consider exclusively the use of center tapped magnetics. For a design of the kind presented in section 5. since it produces more inductance cancellation for a given size than an end tapped structure [21. Lpkg is not present in the ideal circuit representation. The use of this technique allows the designer to reverse the eﬀect of Lpkg in coupling the AC and DC loops and eliminate consequent increases in output ripple.5 Parasitic Mitigation in the Shunt Rectiﬁer In the series resonant rectiﬁer. Lpkg appears in the DC loop. one or both of the latter can be entirely contained in the transformer structure. In a center tapped structure. 5. An HSPICE netlist of the rectiﬁer circuit is provided in appendix B. This is achieved by the use of coupled magnetic structures which produce an equivalent T network having negative inductance in one branch. and it is ignored by the analytic development in section 5.The Shunt Resonant Rectiﬁer models the coaxial cable used to connect it to the ampliﬁer. While the shunt rectiﬁer still uses Cd .32 W at 4.4. while L1 and L2 add to Lser and Lchoke . 22] that can be used to move inductance from one branch to two adjacent branches. respectively. The magnetic structure is designed such that the mutual inductance cancels all or part of Lpkg . When the diode is conducting. In some designs. The negative branch of the network has a value equal to −LM .4. both of the principal parasitics of the diode (Cj and Lpkg ) are employed by the topology. Simulated and experimental results are well matched: the rectiﬁer provided 3. the two physical inductances L1 and L2 appear in the positive branches of the equivalent T network. Thus.97 V with nearly 80% eﬃciency. Application of coupled structures to the shunt rectiﬁer results in the circuit depicted in Fig. the negative mutual inductance between L1 and L2 .1. Techniques have been described in [21. 22]. —64— . increasing output voltage ripple.

The rectiﬁers were driven and loaded in precisely the same manner as in section 5.eﬀ Cout D + Vo − Figure 5-5: Experimental implementation of the shunt rectiﬁer with parasitic mitigation. a matching rectiﬁer design without inductance cancellation was also built. For the optimal value of Lpkg. While it seems that complete cancellation of Lpkg should result in minimum ripple at the output.5. designed. All rectiﬁers were designed to provide 8 W into 5 V from a 100 MHz RF source. simulation and experimentation both show that there is a particular (nonzero) value for which output ripple is minimized. coupled magnetic structures —65— . several rectiﬁers incorporating varying amounts of cancellation were simulated. In all cases.eﬀ .eﬀ and Cd . To test the eﬀect of inductance cancellation. component values are listed in Table 5.5 Parasitic Mitigation in the Shunt Rectiﬁer Lser L1 L2 Lchoke PSfrag Rs Cshn Vi Coupled Magnetic Structure −LM Cout + Vo − Lpkg Cd D Figure 5-4: The shunt resonant rectiﬁer with coupled magnetics for parasitic mitigation.4. 19 40 λ Lser Lchoke Rs Z0 Vi Cshn Cd Lpkg. Figure 5-5 shows the experimental rectiﬁer circuit. these harmonics are phased such that peak-to-peak AC ripple is minimized. This minimization is a result of higher harmonics generated by the interaction between the series combination Lpkg − LM = Lpkg. For comparison. and built.3.

As evidenced by Table 5. adjusted No Cancellation 6. 95 cm Table 5.6 nH 1. Simulation results suggested that Lpkg.5 nH 13. 50V 50 Ω ampliﬁer output impedance 51. experimental ﬁndings agree with the results of simulation. adjusted ripple ﬁgures which account for the discrepancy in choke inductance are listed along with measured values in Table 5.1 nH Coilcraft A04TJ L1 of coupled structure 120 nH 135 nH 140 nH Coilcraft 1812SMS-R12J Coilcraft 1812SMS-R12J and L2 of coupled structure 9 × 47 nF X7R Ceramic.3: Component values used in the experimental implementation of the shunt rectiﬁer with parasitic mitigation.eﬀ = 2.The Shunt Resonant Rectiﬁer Table 5.5 nH 3 nH 18 mV 20 mV LM = 4.5).5 Ω Belkin 8240 RG-58A/U coax.5 nH 16.9 nH 0. The scripts used to generate the circuit board are available in appendix C.pp .5 nH LM = 3.5 nH 16 mV 18 mV LM = 4.6 nH LM = 6. Parameter Po Lpkg.eﬀ Vrip.0 nH LM = 4. measured Vrip. Thus.5 nH should give the greatest reduction in output ripple (an HSPICE netlist for these simulations can be found in appendix B.2 nH 27 mV 32 mV were implemented on printed circuit board traces as described in [22].4.3 nH 0.5 nH.5 nH 3 nH LM = 4. This strongly —66— .2 nH Cj0 = 548 pF 138 pF (82 pF and 56 pF) CDE MC12FA560J and CDE MC12FA820J 12.eﬀ = 2.5 nH 38 mV 38 mV LM = 3.eﬀ Cd Cshn Lser Lchoke Cout Rs Z0 LM = 0 6. Lchoke was reduced to a total of 54 nH (including L2 ) while maintaining ripple performance comparable to the uncancelled case. Note that Lchoke was larger for the cases with inductance cancellation. Element D Lpkg.3 nH 1N5822 2.0 nH 8W 2. In the best case.pp .4: Experimental results for shunt rectiﬁers with parasitic mitigation.9 nH 20 mV 22 mV LM = 6.4. since L2 from the coupled magnetic structure appeared in series with the Coilcraft 1812SMS-R12J.5 nH 1. Lpkg.

Another likely factor is that the Coilcraft inductor was located substantially closer to a ground plane than the inductors implemented in PCB traces (appendix D gives detailed PCB layouts for both the cancelled and noncancelled cases).1 mm. the implementation of multilayer toroidal PCB magnetics or self-shielded components as in [42] would likely prove a substantial boon to those wishing to manufacture integrated passive components using PCB fabrication techniques. While the diameter of the Coilcraft A04TJ is approximately 3. respectively). the PCB inductors had diameters of 7. the principal component of ﬂux linked by the PCB inductors was perpendicular to the ﬂux emitted by the EMI source). all three cases in which inductance cancellation were employed displayed a marked increase in ripple when pointed broadside to a strong source of EMI at ω0 (in this case. An eﬀect of using coupled magnetic structures not considered before implementation was an increase in EMI susceptibility. Ripple ﬁgures in Table 5.4 were measured with the circuit raking the EMI source (that is. the power ampliﬁer used to drive the test circuits). 4.6 mm. It is likely that this enhanced EMI susceptibility arises as a result of the much greater enclosed area of the PCB inductors compared to the Coilcraft inductors employed in the rectiﬁer without inductance cancellation. In fact.0 nH.1 mm (LM = 3.5. In particular.6 nH. and 8. This eﬀect is by no means a fundamental problem with inductors fabricated on a PCB. 7. —67— .5 Parasitic Mitigation in the Shunt Rectiﬁer suggests that the application of coupled magnetic structures may in many cases be of great beneﬁt in terms of total required ﬁlter size.5 nH. and 4.1 mm.

.

Chapter 3 introduces the use of computational modeling for nonlinear circuit analysis. including this conclusion. and demonstrates the application of these techniques to the analysis and design of resonant impedance transformers. This thesis is divided into six chapters. A computational design approach allowing fast and accurate circuit analysis and synthesis is developed and applied. the application of coupled magnetic structures for parasitic mitigation is considered. In addition. Chapter 2 reviews analytic techniques useful in linear resonant circuit analysis. along with traditional analysis. Experimental implementations are investigated to verify analytic and computational results.Chapter 6 Conclusion 6. —69— . algorithms are developed that allow for extremely fast design of rectiﬁer circuits and which pave the way for the analyses performed in the proceeding chapters. In this chapter. Chapter 1 introduces background material and presents motivations for the development of new architectures for DC-DC power conversion.1 Thesis Summary HE PRINCIPAL eﬀort of this thesis is the development of design and characterization methods for rectiﬁer topologies amenable to use in the new architectures T proposed in [10]. to two demonstrative rectiﬁer topologies.

In addition. batch fabricated passive components. e..Conclusion Chapter 4 discusses the ﬁrst of two resonant rectiﬁer topologies. Implementations of rectiﬁers with and without parasitic mitigation are presented. the eﬀort involved in extending these models to account for nonidealities is so great as to motivate the search for an alternate approach. the crude models generally discussed are wholly inadequate for practical designs. In addition to a discussion of analytic models and simulated results. and a discussion of the strengths and weaknesses of the series resonant topology. a comparison of the analytic models with simulation. Chapter 5 covers another topology. exploring the design and implementation process of the series resonant rectiﬁer. while analytic models of nonlinear resonant circuits are useful for developing an understanding of circuit operation.g. Chapter 4 comprises a discussion of analytic models including Fourier and describing function analysis of input impedance. allowing the mitigation of undesired parasitic eﬀects. both to replace existing passives and to enhance circuit performance through. The second conclusion is that the application of integrated. parasitic mitigation. Moreover. has great potential.2 Thesis Conclusions There are two main conclusions that can be drawn from this thesis. the shunt resonant rectiﬁer. First. —70— . The computational design approach presented herein fulﬁlls all practical design requirements while allowing the designer to proceed from speciﬁcation to synthesis in a fast and accurate manner. circuit performance can be enhanced and passive size requirement reduced through the judicious application of integrated magnetic and resonant structures. Experimental results are also discussed. Substantial cost reduction can be realized through the elimination of discrete passives in favor of components integrated on printed circuit boards. It is anticipated that the development of more general computational approaches will allow even greater speed and accuracy for large classes of nonlinear resonant circuits. the exploration of the shunt topology is extended by application of coupled magnetic structures in the rectiﬁer. 6.

radical reductions in the cost of DC-DC power conversion systems. The new architectures presented in [10]. diode conduction loss was the dominant mechanism contributing to degraded eﬃciency. designers could realize a range of circuit topologies with great speed and accuracy. Moreover. the gating losses inherent in synchronous rectiﬁer designs could be made insigniﬁcant compared to the conduction loss savings realized by the elimination of diode forward drop. Such techniques would likely resemble the shunt rectiﬁer implementation of chapter 5. combined with accurate computational modeling and highly integrated passive components. Armed with such techniques. generalization of the computational techniques presented in chapter 3 is needed. simultaneously.6.3 Recommendations for Future Work Two principal improvements to the work here should be investigated. investigation of synchronous rectiﬁcation techniques is necessary. since this allows the use of a ground-referenced switch.3 Recommendations for Future Work 6. With the use of self-resonant gate drives of the type presented in [10]. In all simulated and experimental circuits presented. promise dramatic increases in performance and. First. the development of these techniques in parallel with similar methods for the design of integrated passive components will allow power converter technologies to take advantage of the beneﬁts of batch fabrication. To circumvent this loss. —71— .

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and D. Wall.” http://www. pp. P.gnu.cadsoft.edu/ ram/electro/gr/history. Perreault. L.” in 16th Annual IEEE Power Electronics Specialists Conference Proceedings. Albulet. “Exact analysis of class E tuned power ampliﬁer at any Q and switch duty cycle. and J. Feb. 1987.org/LDP/abs/html/. 1996. Bloom.” http://www. no.” http://www. “Advanced Bash-Scripting Guide. Silveira. 2nd ed. 2001. Kamon. E. [44] R. Christiansen. [51] “XFig Version 3.pdf.” http://www.htm. June 2004. W. A History of the General Radio Company. Kazimierczuk and K. J. Cambridge. 91–100. “The application of power MOSFETs at 100MHz.BIBLIOGRAPHY [41] A.. 1985. PDF available from http://www-2. Programming Perl. CA: O’Reilly Associates.cs. Severns and G. Sebastapol.” http://www. San Rafael. [47] Ampliﬁer Research. [43] M.org/userman/. 149–159. [49] M. Schwartz. [42] J. 34. —76— . Modern DC-to-DC Switchmode Power Converter Circuits. Smithhisler. [54] “EAGLE: The easily applicable graphical layout editor.adobe. 1985.tldp. Inc. Kassakian. Thiessen. CA: e/j BLOOM Associates. RF Power Ampliﬁers. Goldberg and J. pp. Cooper. Puczko. L. GA: Noble Publishing. [53] M.org/software/make/manual/. Phinney. H.xﬁg. 2.” IEEE transactions on Circuits and Systems. White. MA: General Radio Company. Ampliﬁer Research Model 10W1000C. Inc. [45] M. MA: MIT Research Laboratory of Electronics. Atlanta. T. 1996. [52] “Adobe PostScript 3. 1965. F. M. [46] A.2. J. C. G.com/products/postscript/. “Multi-resonant microfabricated inductors and transformers.cmu. West Concord.. vol..4 user manual.de/info. FastHenry User’s Guide.” in 35th Annual Power Electronics Specialists Conference Proceedings. [48] L. and R. [50] “GNU make. Lang.

A.mt0 *.dat hspice $< | tee $@ 20 —77— .pwr: %.sh . .imp *.pl .lis imp: $(WORKDIR). .imp 10 pwr: $(WORKDIR).tr0 *./bin/impextract.pwr *.pwr clean: rm −f *./bin/eﬀextract.Appendix A SAMwIICh Code Listings This appendix consists of code listings for the SAMwIICh system. . . .pl | tee $@ %. and Makeﬁles [50].lis: %. .sh $< $@ | perl ./bin/eﬀextract. SAMwIICh uses a combination of perl scripts [48].imp: %.sp values.pl . WORKDIR := $(shell basename $$PWD) CALCOPTS = −V −C all: lis imp pwr 5 lis: $(WORKDIR)./bin/eﬀcalc. pun intended)./bin/impextract. .pl $(CALCOPTS) | tee $@ %./bin/eﬀcalc./bin/impcalc.ipp 15 %.1 Makefile Using a Makeﬁle makes everything easier (sorry. bash scripts [49].sh . .sh $< $@ | perl .lis *./bin/impcalc.lis .st0 *.lis .

$ℓdio = $opts{’d’} | | 6e−9. $xvaℓ. $inxc) = split(’ ’. if ($inxc =˜ /H/) { # oops! the input looks capacitive for some reason. # the component values for the ﬁrst iteration $nextr = $opts{’r’} | | 6. close(VALS). $vin. 20 $vin = $opts{’v’} | | 9. it dispatches all the simulation jobs and sets up component values for the next iteration. $nextc. too $PWNAM = ‘basename $ENV{’PWD’}‘. 10 chomp $PWNAM. # set up utility variables $done = 0. —78— . #!/usr/bin/perl use Getopt::Std. 40 ($mag. # get the name of the directory.imp"). $rvaℓ. . print VALS join(’ ’. $ℓmut)). $nextc = $opts{’c’} | | 2e−9. <IMP>). $inx. 15 $TOLER = .">values.SAMwIICh Code Listings A.002. close(IMP).". $ℓser. "<". Everything else # should have this name. $ℓdio. ($nextr.dat") or die "Could not set R and C values: $!". # until $done is true or if we do too many iterations while ((!$done) && ($maxiter−− > 0)) { # clean up ‘make clean‘.2 automatch. 25 # set the ﬁrst round of values open(VALS. # read in the impedance values open(IMP. $maxiter = 15. "\n". 35 # do the body of calculations # hspice is called from the makeﬁle ‘make CALCOPTS="-V -C" imp‘. . 5 getopts(’r:c:v:l:d:m:’. my %opts. 30 45 # we match assuming that we’re cancelling inductance with capacitance # and then adding a high-pass L-match. $ℓser = $opts{’l’} | | 10e−9. $ℓmut = $opts{’m’} | | 0. \%opts).$PWNAM.pl This is the heart of SAMwIICh.

MODEL d20cjq030 d +IS=7. $nextc = $inxc + 0. } A. $ℓdio.5 TT=0 +KF=0 AF=1 5 —79— . $nextc. $ctoℓer = abs((abs($nextc)−abs($inxc))/$inxc). undef $nextc. $ℓser. undef $ℓmut.A. $nextc => $inxc ($ctoler)\n". undef $vin.3 matching.3 matching.45927e−09 RS=0. SAMwIICh Circuit .3 +XTI=4 BV=30 IBV=0.427299 FC=0.9346e−10 10 +VJ=0. $vin. we’re done ($done = 1) if (($rtoℓer < $TOLER) && ($ctoℓer < $TOLER)).0632601 N=0.4 M=0. undef $ℓdio. "\n".options post=1 nomod nopage INGOLD=1 accurate unwrap * SPICE model for the diode * courtesy of International Rectiﬁer . # show the user what’s going on print "$nextr => $rval ($rtoler).sp 50 $done = 1. undef $ℓser.dat") or die "Could not set R and C values: $!". things are looking good else { # how much have things changed from the last run? $rtoℓer = abs((abs($nextr)−abs($rvaℓ))/$rvaℓ). Comments note the location of the circuit under test. Most of this ﬁle is setup commands to make HSPICE produce appropriate output. } # OK.89875 EG=1. } 75 70 # write out the new component values for spice open(VALS.sp This is the HSPICE input ﬁle used for the analysis. # set up the new values $nextr = $rvaℓ + 0. ($nextr. close(VALS).">values. 55 60 65 # if we’re within $TOLER. $nextr = "*ERROR: Input looks capacitive!*". $ℓmut)).0001 CJO=2. print VALS join(’ ’.

and diode dissipation .probe tran i(Vinm) V(in) V(1) v(3) v(4) .pl .PARAM WOSC = ’6.PARAM QLSER = 100 .PARAM CSOURCE = 2015e−12 .measure tran avgprin avg p(Rin) from=.four 100x v(in) i(vinm) 60 * this is data from automatch.dat’ RSOURCE=1 CSOURCE=2 INV=3 LSER=4 LDs=5 LMUT=6 . eﬃciency.03 .PARAM LSHN = 47e−9 20 .PARAM FOSC = 100e6 15 .PARAM LSER = 10e−9 .PARAM RSOURCE = 6.probe tran p(Vin) p(Dtest) p(Vout) POWER * these .DATA valdat MER +FILE=’values.5u to=1u 55 .PARAM LDs = 6n .measure tran avgpd avg p(Dtest) from=.save all .PARAM QLSHN = 100 .measure tran avgptot avg POWER from=.5u to=1u .measure tran avgpout avg p(Vout) from=.measure statements allow us to examine input * and output power.5u to=1u 50 * the next line causes HSPICE to do the Fourier analysis .5u to=1u .SAMwIICh Code Listings * simulation parameters .283185 * FOSC’ .PARAM LMUT = 0 .ENDDATA 65 —80— .measure tran avgpin avg p(Vin) from=.5u to=1u .PARAM INV = 9 25 * the circuit under test Vin rin 0 sin(0 INV FOSC 0 0) Rin rin inc RSOURCE Cin inc inm C=CSOURCE Vinm inm in 0 Lser1 in 35 30 1 L=LSER R=’WOSC * LSER / QLSER’ Lshn1 1 nrfoo L=LSHN Rfoo nrfoo 0 R=’WOSC * LSHN / QLSHN’ Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’ 40 Ldio 1 Dtest 3 Cout 4 Vout 4 3 4 0 0 LDs d20cjq030 30n 5 45 * some useful analysis options .

}’ > $2.}’ > $2.prin $2. printf ("%s.tran .pin grep avgprin= $1 | awk ’{print($2). A.tmp 5 A.4.pin $2.tmp cat $2.pl.pout | tr ’\t’ .pout $2. abs($pin)−abs($prin).end A. abs($pout). or vice-versa. #!/usr/bin/perl # reads in data from eﬀextract. #!/bin/bash # grab the power calculations out of the spice listing grep avgpin= $1 | awk ’{print($2).2 effcalc.01n 1u UIC SWEEP DATA=valdat . using the input data .1 effextract.4.pl This script calculates input and output power and conversion eﬃciency.pin $2. then divides output/input while(<>) { chomp. $prin. abs($pout)/(abs($pin)−abs($prin))).pout paste $2.%s\n". $pout) = split(/. > $2. 15 } —81— . 10 ($pin.4 Eﬃciency Calculations * perform a transient sweep.}’ > $2.prin $2. I’ve kept the two functions separate so that I can easily swap in a diﬀerent parser while keeping the number crunching facilities the same.sh # subtracts power burned in the source resistance 5 # from total power in.4 Eﬃciency Calculations The two ﬁles in here parse data out of the HSPICE listing and then do the crunching.A./).sh This code extracts the data necessary for eﬃciency calculations from the HSPICE listing in a format useful to effcalc.prin grep avgpout= $1 | awk ’{print($2).%s.tmp 10 rm $2.

my %opts.v grep −A7 ’i(vinm)’ $1 | grep ’^[[:space:]]*1[[:space:]]’ | \ 10 awk ’BEGIN {OFS=". # hooray for excessive precision $pi = 3. component corresponding to -1*X)\n".$5). resistance.}’ > $2. rm $2. \%opts).} {print($3.5. 20 print " -p Print equivalent parallel input network\n". "and equivalent component value\n". } 25 sub engnot —82— .$5.i $2. print " -m <res> Print high pass L-match resulting in <res> input impedance\n".$2). A. "(i. 10 getopts(’CVhpm:’. " .1 impextract. #!/usr/bin/perl # one of the workhorses of the SAMwIICh suite 5 use Getopt::Std.14159265358979323846. exit(0).5.sh #!/bin/bash # extract impedance parameters from input spice ﬁle # this script grabs the fundamentals of the fourier series 5 # resulting from ’.v A.".i paste $2. reactance.SAMwIICh Code Listings A. if ($opts{’h’}) { 15 print "Usage: $0 [-C] [-V] [-p] [-m <res>] [-h]\n". print " -V Print impedance magnitude.}’ > $2.i | tr ’\t’ .".} {print($3.v $2. its output is conﬁgurable via commandline parameters.four FREQ v(in) i(vinm)’ grep −A7 ’v(in)’ $1 | grep ’^[[:space:]]*1[[:space:]]’ | \ awk ’BEGIN {OFS=".5 Impedance Calculations Like eﬃciency.e. print " -C Print complement of equivalent component value " .pl This is a slightly more complex script. impedance calculations are separated from parsing functionality.2 impcalc.

$basen *= 10**$adj. $phase = $pi * ($vph − $iph) / 180. my ($basen. } # print out conjugate element corresponding to X* if ($opts{’C’}) { printf ("%s%s ". $expnt. engnot((($X>0) ? (1 / ($X * $omega)) : (−1 * $X / $omega))). # read in the data ($vmag. my $adj = $expnt % 3. $expnt −= $adj. 50 55 60 65 70 75 —83— . return $basen . engnot($X). # print out impedance values if ($opts{’V’}) { printf ("%s %s %sj %s%s ". $freq) = split(/. return undef unless $num. (($X < 0) ? ’F’ : ’H’) ). engnot($R). engnot($zmag). (($X<0) ? ’H’ : ’F’) ). $expnt) = split(’e’. $X = $zmag * sin($phase). # if it’s not in scientiﬁc notation.$num)) unless ($num =˜ /e/)./). engnot((($X < 0) ? (−1 / ($X * $omega)) : ($X / $omega))). "e" . $omega = 2 * $pi * $freq. $num)). # make it so ($num = sprintf (’%4.5 Impedance Calculations { # change a number to engineering notation # argument my $num = shift @ . } 45 30 35 40 while (<>) { # main loop # read in data from each line of stdin or ﬁlenames provided as arguments chomp.A.4g’. $iph. $imag. $vph. $R = $zmag * cos($phase). sprintf (’%e’. $zmag = abs($vmag) / abs($imag).

$q. $cm = 1 / ($omega * $q * $R).SAMwIICh Code Listings 80 } # convert series impedance to parallel impedance if ($opts{’p’}) { $q = abs($R/$X). cancelling # input reactance as necessary if ($opts{’m’}) { # ﬁrst cancel the reactance $ecanc = (($X > 0) ? (1 / ($X * $omega)) : (1 * ($X / $omega))). engnot($Ep). engnot(−1*$ecanc). $Xp = $X * ($q**2+1)/($q**2). $Ep = 1 / ($Xp * $omega). engnot($ℓm)). $nmstring). engnot($ctot). } # matching with a high-pass L-match. } printf ("%s %s %s%s ". } else { printf ("%sH %s %sF %sH". } —84— . $q. printf ("%s %sF %sH". $q. $Ep = $Xp / $omega. engnot($ℓm)). 85 90 95 100 105 110 115 120 125 130 } if ($ecanc > 0) { $ctot = ($ecanc*$cm)/($ecanc+$cm). engnot($cm). if ($X < 0) { $nmstring = ’F’. } else { $nmstring = ’H’. engnot($Rp). $q = sqrt(abs(($opts{’m’}/$R) − 1)). $Rp = $R * ($q**2+1). $ℓm = $opts{’m’} / ($q * $omega).

A. } —85— .5 Impedance Calculations print "\n".

.

PARAM .5e−9 INV = 19.probe tran p(Vin) p(Vout) POWER .options post=1 nomod nopage INGOLD=1 accurate unwrap 5 .3.5u to=1u —87— .6e−12 LDs = 20. B.PARAM FOSC = 100e6 WOSC = ’6.Appendix B SPICE Netlists This appendix contains all SPICE netlists used.283185 * FOSC’ CDp = 123. Series Rectiﬁer The three netlists in this section are for the simulations performed in section 4.1e24 1e−24.1.measure tran avgpin avg p(Vin) from=.1e−24 5 Ldio in Cdio 3 Gtest 3 Vout 4 3 4 4 0 20 .19 10 Vin rin 0 sin(0 INV FOSC 0 0) Vinm rin in 15 0 LDs CDp VCR PWL(1) 3 4 0. Linear Capacitor The diode is represented by a voltage-controlled resistor.PARAM . B.1 Ideal Diode.PARAM .probe tran i(Vinm) V(in) v(3) v(4) . Series−resonant rectiﬁer.1 Comparison of Analytic Model with Simulation.save all . run #1 .PARAM .

run #2 .probe tran p(Vin) p(Dtest) p(Vout) POWER .5u to=1u .5u to=1u .measure tran avgpd avg p(Dtest) from=.PARAM .tran .save all .0632601 N=0.end B.19 10 .01n 1u UIC —88— .SPICE Netlists 25 .PARAM 15 .4 M=0.5e−9 INV = 19.5u to=1u 30 .45927e−09 RS=0.tran .5u to=1u .283185 * FOSC’ CDp = 123.four 100x v(in) i(vinm) .MODEL d20cjqfoo d +IS=7.427299 FC=0.89875 EG=1.6e−12 LDs = 20.measure tran avgpout avg p(Vout) from=.1.probe tran i(Vinm) V(in) v(3) v(4) .PARAM Vin rin 0 sin(0 INV FOSC 0 0) Vinm rin in 20 0 LDs CDp d20cjqfoo 5 Ldio in Cdio 3 Dtest 3 Vout 4 25 3 4 4 0 .measure tran avgptot avg POWER from=.2 Real Diode with Constant Junction Capacitance This simulation uses a real diode model.PARAM .01n 1u UIC 30 . Series−resonant rectiﬁer.0001 CJO=1e−24 +VJ=0.PARAM .four 100x v(in) i(vinm) 35 .3 +XTI=4 BV=30 IBV=0.5u to=1u .measure tran avgptot avg POWER from=.options post=1 nomod nopage INGOLD=1 accurate unwrap 5 .measure tran avgpout avg p(Vout) from=. but with the junction capacitance replaced by a constant capacitor.5 TT=0 +KF=0 AF=1 FOSC = 100e6 WOSC = ’6.measure tran avgpin avg p(Vin) from=.5u to=1u .

5e−9 15 .measure tran avgpd avg p(Dtest) from=.B.5u to=1u —89— .PARAM CSOURCE = 154.MODEL d20cjqfoo d +IS=7.26e−12 * since we are driving from a conjugate match.PARAM RSOURCE = 36.options post=1 nomod nopage INGOLD=1 accurate unwrap 5 .5u to=1u 40 .measure tran avgpout avg p(Vout) from=.89875 EG=1.427299 FC=0.PARAM WOSC = ’6. Constant Cj .1 Comparison of Analytic Model with Simulation. Series−resonant rectiﬁer.45927e−09 RS=0.283185 * FOSC’ .probe tran i(Vinm) V(in) v(3) v(4) .measure tran avgprin avg p(Rin) from=. This time.save all .end B.5u to=1u .PARAM INV = ’19.5 TT=0 +KF=0 AF=1 10 .0001 CJO=1e−24 +VJ=0. * we have to double the voltage at the source 20 * to keep the input voltage the same Vin rin 0 sin(0 INV FOSC 0 0) * we must use a shunt capacitor * because otherwise there is no * path for DC current Rin rin inm RSOURCE Cin inm 0 CSOURCE Vinm inm in 0 Ldio in Cdio 3 Dtest 3 Vout 4 35 25 30 3 4 4 0 LDs CDp d20cjqfoo 5 .PARAM FOSC = 100e6 .PARAM LDs = 20.19 * 2’ .probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER .measure tran avgpin avg p(Vin) from=. the source impedance is the conjugate of the calculated input impedance.6e−12 . Series Rectiﬁer . run #3 .83 .4 M=0.3 +XTI=4 BV=30 IBV=0.3 Real Diode.5u to=1u .PARAM CDp = 123. a “real” diode with constant junction capacitance was used.1.0632601 N=0. Conjugate Source Impedance As above.

5u to=1u —90— .tran .PARAM .PARAM Vin rin 0 sin(0 INV FOSC 0 0) 20 Vinm rin in 0 Lshn in nfoo LSHN Rfoo nfoo 0 R=’WOSC * LSHN / QLSHN’ 25 * we account for the ﬁnite Q of the * inductor by calculating the appropriate * series resistance Ldio in Dtest 3 Vout 4 3 4 0 LDs Dmbrs1540t3 VOUT 30 . including nonlinear output capacitance.5 VOUT = 5 10 .probe tran i(Vinm) V(in) v(3) v(4) 35 .0306875 N=1.283185 * FOSC’ LDs = 1e−9 LSHN = 12.428536 FC=0.18451e−10 +VJ=0.PARAM .options post=1 nomod nopage INGOLD=1 accurate unwrap 5 .54179e−05 RS=0.PARAM .PARAM 15 .4038 EG=0.5 TT=0 +KF=0 AF=1 FOSC = 100e6 WOSC = ’6.5u to=1u 45 .probe tran p(Vin) p(Dtest) p(Vout) POWER .5u to=1u .2 Series Resonant Rectiﬁer Output Impedance This rectiﬁer was implemented in [10].measure tran avgpd avg p(Dtest) from=.SPICE Netlists .01n 1u UIC .5e−9 QLSHN= 150 INV = 7.measure tran avgpin avg p(Vin) from=.4 M=0.0008 CJO=3.PARAM . output impedance testing . Series−resonant rectiﬁer.save all .MODEL Dmbrs1540t3 d +IS=3.four 100x v(in) i(vinm) . The netlist uses a real diode model.6 +XTI=1.PARAM .measure tran avgptot avg POWER from=.97409 BV=40 IBV=0.end B.

3 Comparison of Analytic Model with Simulation.measure tran avgpout avg p(Vout) from=.5e−6 INV = 5.end B.1 Ideal Diode. run #1 .6 OUTV = 5 Vin in 0 sin(0 INV FOSC 0 0) 15 Cser1 in cin Lser1 cin lin Vinm lin 1 20 CSER LSER 0 CD VCR PWL(1) 0 1 0.PARAM . B. Shunt Rectiﬁer .2.PARAM .PARAM .02 45 .data vodat VOUT +4.measure tran avgptot avg POWER from=.5u to=1u . Shunt Rectiﬁer The netlists in this section are for the simulations performed in section 5.32e−12 LCHOKE = 2.save all .3 Comparison of Analytic Model with Simulation.PARAM 5 FOSC = 100e6 WOSC = ’6.01 5.options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100 .00 5.enddata .PARAM .4e−12 LSER = 28.99 5.PARAM .1e−24 LCHOKE 0 OUTV Cd 1 Gtest 0 0 1 4 out 0 Lchk 1 Voutm 4 25 Vout 4 .98 4.PARAM 10 .B.24e−9 CD = 101.3.283185 * FOSC’ CSER = 110.four 100x v(in) i(vinm) . Linear Capacitor Shunt−resonant rectiﬁer.1e24 1e−24.probe tran p(Vin) p(Vout) p(Gtest) POWER —91— .probe tran i(Vinm) V(1) v(4) v(out) i(Voutm) .tran .5u to=1u 40 .01n 1u UIC SWEEP DATA=vodat .PARAM .

3 +XTI=4 BV=30 IBV=0.PARAM .5e−6 INV = 5.tran .measure .options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100 5 .MODEL d20cjqfoo d +IS=7.probe tran p(Vin) p(Vout) p(Gtest) POWER .measure tran avgpout avg p(Vout) from=19u to=20u .24e−9 CD = 101.32e−12 LCHOKE = 2.measure tran avgpin avg p(Vin) from=19u to=20u .measure tran avgpd avg p(Gtest) from=19u to=20u .4 M=0.PARAM .0001 CJO=1e−24 +VJ=0. run #2 .measure tran tran tran tran avgpin avg p(Vin) from=19u to=20u avgpd avg p(Gtest) from=19u to=20u avgpout avg p(Vout) from=19u to=20u avgptot avg POWER from=19u to=20u 35 .5 TT=0 +KF=0 AF=1 FOSC = 100e6 WOSC = ’6.2 Real Diode with Constant Junction Capacitance Shunt−resonant rectiﬁer.6 OUTV = 5 10 .PARAM .1n 20u .45927e−09 RS=0.427299 FC=0.end B.PARAM .measure .save all .89875 EG=1.0632601 N=0.SPICE Netlists 30 .PARAM 15 .PARAM .measure tran avgptot avg POWER from=19u to=20u 40 —92— .3.measure .283185 * FOSC’ CSER = 110.PARAM 20 Vin in 0 sin(0 INV FOSC 0 0) Cser1 in cin Lser1 cin lin Vinm lin 1 CSER LSER 0 CD d20cjqfoo LCHOKE 0 OUTV 25 Cd 1 Dtest 0 Lchk 1 Voutm 4 Vout 4 0 1 4 out 0 30 .probe tran i(Vinm) V(1) v(4) v(out) i(Voutm) 35 .PARAM .4e−12 LSER = 28.

PARAM .PARAM .3 +XTI=4 BV=30 IBV=0.PARAM 15 .PARAM .283185 * FOSC’ LMUT = 0 LSER = 1e−9 QLSER = 150 LSHN = 120e−9 QLSHN = 150 LDs = 2e−9 RSOURCE = 11.0001 CJO=144.95 CMAT = 74.5 TD=5e−9 L=.45927e−09 RS=0.4 Shunt Resonant Rectiﬁer.95 Vinm inmo in 0 —93— .5 TT=0 +KF=0 AF=1 FOSC = 100e6 WOSC = ’6. Note that series-shunt conversion yields the correct value Rin rin ino RSOURCE Cm ino inm CMAT Lm inm int L=LMAT R=’WOSC * LMAT / QLMAT’ 40 Tin int 0 inmo 0 Z0=51.4.PARAM . not the shunt path. no inductance cancllation .PARAM .options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100 5 . Experimental Implementation .B.PARAM .56e−12 +VJ=0.end B.tran . This is the reason for the discrepancy between the value used for experimentation and the value used in this simulation.47728 FC=0.MODEL d20cjq060 d +IS=7.0632601 N=0.PARAM 20 .1n 20u .PARAM .PARAM 25 Vin rin 0 sin(0 INV FOSC 0 0) * * 30 * * * * * 35 * note that the input capacitance is in the series path. Shunt−resonant rectiﬁer.PARAM .43217 M=0. Experimental Implementation This netlist corresponds to the experimental implementation of the rectiﬁer described in section 5.89875 EG=1.4 Shunt Resonant Rectiﬁer.PARAM .PARAM .6378e−12 LMAT = 38e−9 QLMAT = 150 INV = 21 FOOB = 0 10 .PARAM .

64135 m = 0.603662 fc = 0.4 ibv = 3.5u to=1u .99991 + cjo = 5.5u to=1u 65 .four 100x v(in) i(vinm) i(voutm) 70 .0250254 10 + eg = 0.79999 xti = 3.72u .98477 rs = 0.5.probe tran i(Vinm) V(inm) V(in) V(1) v(3) v(4) v(out) i(Voutm) .27781E−005 n = 1.01n 1u UIC .measure tran avgptot avg POWER from=.5u to=1u .0171579 + eg = 1.measure tran avgpd avg p(Dtest) from=.model grd d is = 1.4427E−009 bv = 48.measure tran avgprin avg p(Rin) from=. Shunt−resonant rectiﬁer with inductance cancellation .subckt d1n5822 1 2 —94— .tran .794212 5 .47556E−010 vj = 1.measure tran avgpin avg p(Vin) from=.55507 xti = 0.5 Shunt Resonant Rectiﬁer with Parasitic Mitigation This netlist corresponds to the experimental implementation of the shunt rectiﬁer with parasitic mitigation described in section 5.5u to=1u .measure tran avgpout avg p(Vout) from=.save all .options post=1 nomod nopage INGOLD=1 accurate unwrap itl4=100 .end B.measure tran ippout PP i(Voutm) from=.5 + tt = 1.5u to=1u .37487E−007 n = 1.model legd d is = 2.SPICE Netlists Lser1 in 45 1 3 3 0 4 L=LSER R=’WOSC * LSER / QLSER’ Lds d20cjq060 2e−12 L=LSHN R=’WOSC * LSHN / QLSHN’ Ldio 1 Dtest 0 C3par 3 50 Lshn1 1 Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’ Voutm 4 55 out 0 100n 5 Cout out 0 Vout out 0 60 .5 af = 1 kf = 0 .7u to=.probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER .2149 rs = 0.

5 Shunt Resonant Rectiﬁer with Parasitic Mitigation ddio 1 2 legd dgr 1 2 grd 15 .PARAM LMAT = 13.PARAM FOSC = 100e6 .8e−9 . most of the inductance is in LMAT .7 Vin rin 0 sin(0 INV FOSC 0 0) 35 Rin rin ino RSOURCE Cm ino inm CMAT Lm inm int L=LMAT R=’WOSC * LMAT / QLMAT’ Cm2 inm int C=CMAT2 40 Tin int 0 inmo 0 Z0=51.PARAM WOSC = ’6.PARAM CMAT = 144e−12 30 .95 Vinm inmo in 0 Lser1 in 45 1 3 3 0 4 L=LSER R=’WOSC * LSER / QLSER’ Lds d1n5822 2e−12 L=LSHN R=’WOSC * LSHN / QLSHN’ Ldio 1 Xtest 0 C3par 1 50 Lshn1 1 Ksershn Lser1 Lshn1 K=’LMUT / SQRT(LSER * LSHN)’ Voutm 4 55 out 0 100n 5 Cout out 0 Vout out 0 60 .PARAM LSHN = 120e−9 25 .measure tran avgpin avg p(Vin) from=.probe tran p(Vin) p(Rin) p(Dtest) p(Vout) POWER .5u to=1u 65 .save all .PARAM LMUT = 0 * dummy value.measure tran avgpout avg p(Vout) from=.PARAM QLMAT = 150 .PARAM RSOURCE = 2.5e−9 .PARAM INV = 29. not in shunt as in the actual implementation .probe tran i(Vinm) V(inm) V(in) V(1) v(3) v(4) v(out) i(Voutm) .B.5u to=1u .PARAM QLSER = 150 .measure tran avgprin avg p(Rin) from=.5 TD=5e−9 L=.PARAM LSER = 1e−9 .PARAM QLSHN = 150 .measure tran avgpd avg p(Dtest) from=.PARAM LDs = 6.283185 * FOSC’ * set this parameter to the desired mutual inductance 20 .5u to=1u —95— .5u to=1u .56 * note that this is in series.ends .

end —96— .measure tran ippout PP i(Voutm) from=.5u to=1u .measure tran avgptot avg POWER from=.72u .four 100x v(in) i(vinm) i(voutm) 70 .SPICE Netlists .tran .7u to=.01n 1u UIC .

($baserad+($radmuℓ*$i))).0". # these deﬁne the base radius and increment $baserad = 79. # computer the new radius $raditer = $baserad + ($radmuℓ * $i). #!/usr/bin/perl -w # the endpoints are always the same. chdir("p1r" .-90". $endptbot = "440.pl generates 20 coupled magnetic structures of increasing size and produces both FastHenry simulations and scripts which produce a single PCB with the magnetic structures laid out in a tiled pattern.1 mkcan. $i<20. $i++) { 15 # make a place to store the data mkdir("p1r" . # allowing consistent via placement 5 $endpttop = "270.Appendix C Scripts for PCB Inductor Generation This appendix provides listings of the perl scripts [48] used to generate coupled magnetic structures on PCBs. $viapt = "270. # generate the top spiral 20 —97— . C. ($baserad+($radmuℓ*$i))).pl mkcan. 10 for (my $i=0. $radmuℓ = 10.250".

. $xoﬀ .pl -f -t 1 -w 50 -c 35 -r " . $yoﬀ = 1000 + int($i/5)*2000.0 > top. " -b " . print ‘$topcmd‘./bin/dat2scr./gpdat -x " ./gpdat -x " . $yoﬀ . " -b " . # generate the Eagle script for the top $topscr = ".pl -f . Rick James simulates them ‘fasthenry full. " -y " . " -Y " . # generate the bottom spiral $botcmd = ". "-y $yoff > place.ind". 30 35 40 45 50 55 # generate the data for FastHenry simulation $indcmd = "./gpdat > full. ". "> bot. # fork oﬀ a new process to display the inductors unless (fork()) { # oooooh.pl -t 1 -w 50 -c 35 -r " . . $raditer . $yoﬀ . . . " -C -z -62 -e " ./bin/dat2ind.Scripts for PCB Inductor Generation 25 $topcmd = ". } # meanwhile. $xoﬀ . . $endptbot .ps‘.ind &>/dev/null‘. $viapt . . " -X " .scr". ./bin/spiral. $yoﬀ . " > bot. give each # one an appropriate oﬀset to make tiling simple $xoﬀ = 1000 + ($i % 5)*2000.pl -1 top. # generate the Eagle script for the bottom $botscr = ". "1e8. # generate the part placement script $pℓcmd = ". ./bin/dat2scr. " > top. pretty print ‘gv −geometry +0−0 zbuﬃle2. exit.dat -p . ‘$fhzcmd &>/dev/null ‘./bin/placescr. # since we are tiling these on a PCB. 75 —98— . " -y " . ‘$pℓcmd‘.dat -F " . ‘zbuf zbuﬃle2 &>/dev/null ‘.1 -b -H 3 -W 4 -p .scr".pl -f bot. " -Y " .dat"./bin/spiral. " -X " .dat". $xoﬀ . 60 65 70 # make the zbuf ﬁle $fhzcmd = "fasthenry -f refined full. $raditer .ind". print ‘$botcmd‘.pl -f top. $xoﬀ . $yoﬀ .dat -p . .1e8.dat -2 bot./placedat -x $xoff " . " -C -e " . print ‘$indcmd‘. print ‘$botscr‘.scr". print ‘$topscr‘. . $endpttop . $viapt .

if ($opts{’h’}) { print "Usage: $0 -t <turns> [opt [opt [opt]]]\n".y1[:x2.pl generates spirals and circles in a generic format processed by dat2fig. .1415926535897932384626433832795. } C. print " -z <zoff> Offset in Z-dimension\n".pl.5)\n".2 spiral. getopts(’t:w:s:c:x:y:z:b:e:r:Cfph’. 15 $opts{’h’}++ if ($opts{’C’} && !($opts{’r’})). print " -b <x1. print " -w <width> Width of conductor in each turn (default 50)\n". print " -t <turns> Number of turns (required)\n". print " -c <chunks> Number of chunks (line segments) in output file\n"./bin/qcalc. print " -s <space> Turn spacing multiplier (default 1.’). . . Must also specify -r. print " i.y2. my $maxtheta. print " -r <rad> Start with initial radius <rad> instead of zero\n". exit(0).2 spiral. print " -p Output points in cylindrical form (default Cartesian)\n". and dat2scr. .]> Connects the outer end of the spiral to the given points\n".C.y1[:x2. print " (These points are referred to the center of the spiral. use Getopt::Std. my $radrange. dat2ind.y2.pl.mat | . \%opts).pl | tee Ldat‘.pl. 10 my %opts.\n". #!/usr/bin/perl -w use strict. 80 # get ready to run another cycle chdir(’. print " -C Make a circle instead of a spiral. print " -f Flip spiral direction (default counterclockwise)\n". print " -h Show this help screen\n". # show help if they don’t give -t foo $opts{’h’}++ unless ($opts{’t’}).\n". print " -y <yoff> Offset in Y-dimension (ignored in cylindrical mode)\n". .]> Connects the inner end of the spiral to the given points\n".e. print " -e <x1.pl spiral. 5 # ha ha my $pi = 3. . } 20 25 30 35 —99— .pl # extract the data from the FastHenry simulation print ‘cat Zc. they are offset by <xoff> and <yoff>)\n". print " -x <xoff> Offset in X-dimension (ignored in cylindrical mode)\n".

my $theta = atan2($yvaℓ. $yvaℓ. $theta. "\n". $yvaℓ += $opts{’y’}.75 * $opts{’w’} / $opts{’r’})) * (($opts{’f’}) ? −1 : 1). ($xvaℓ. # radrange is the distance we’ll be travelling —100— . 0. } else { # just calculate based on the number of turns $maxtheta = $opts{’t’} * 2 * $pi * (($opts{’f’}) ? −1 : 1). if ($opts{’b’}) { 50 my @points = split(/:/. $opts{’z’}. 100. $opts{’b’}). $opts{’w’})) .$xvaℓ). foreach my $point (@points) { my ($xvaℓ. $xvaℓ += $opts{’x’}.75 wire widths $maxtheta = ((2 * $pi) − (1. 1. ($radius. } 55 60 65 70 } } 75 80 85 90 if ($opts{’C’}) { unless ($opts{’t’} < 1) { # if it’s bigger than 1 turn.5. 0. goes to 2*pi*#turns $maxtheta = $opts{’t’} * 2 * $pi * (($opts{’f’}) ? −1 : 1). $point).".Scripts for PCB Inductor Generation 40 $opts{’w’} $opts{’s’} $opts{’c’} $opts{’x’} $opts{’y’} $opts{’z’} 45 $opts{’r’} $opts{’C’} | |= | |= | |= | |= | |= | |= | |= | |= 50. 0. 0.". $opts{’w’})) ./. $opts{’z’}. } } else { # spiral starts at 0. } else { print join(". 0. reduce it to 1 turn less # 1. "\n". if ($opts{’p’}) { my $radius = sqrt($xvaℓ**2 + $yvaℓ**2). print join(". $yvaℓ) = split(/.

} 100 105 110 } if ($opts{’e’}) { my @points = split(/:/. print join(". ($radius. $opts{’z’}. if ($opts{’p’}) { my $radius = sqrt($xvaℓ**2 + $yvaℓ**2).$xvaℓ). $opts{’w’})) .3 dat2fig.pl suitable for display with XFig [51] or translation to PostScript [52] using the transfig program [51].pl $radrange = $opts{’w’} * $opts{’t’} * $opts{’s’}. $opts{’w’})) . $opts{’z’}. $opts{’w’})) . $point). #!/usr/bin/perl -w —101— .pl generates a graphical representation of the output of spiral. "\n". $opts{’z’}.". "\n". $xvaℓ += $opts{’x’}.pl dat2fig. 120 125 130 } } print join(".3 dat2fig. ($radius. my $theta = $maxtheta * $i / $opts{’c’}. $yvaℓ+$opts{’y’}. 115 foreach my $point (@points) { my ($xvaℓ. $theta. $opts{’e’}). "\n". $theta. } else { my $xvaℓ = $radius * cos($theta)./. my $yvaℓ = $radius * sin($theta). $yvaℓ. } else { print join(".". ($xvaℓ+$opts{’x’}.C. $opts{’z’}. if ($opts{’p’}) { print join(". "\n". $opts{’w’})) . $yvaℓ += $opts{’y’}. my $theta = atan2($yvaℓ. $i++) { my $radius = ($opts{’C’}) ? $opts{’r’} : (($radrange * $i / $opts{’c’}) + $opts{’r’}).". $i<($opts{’c’}+1). } 95 for (my $i=0. } C.". ($xvaℓ. $yvaℓ) = split(/.

2 Landscape 45 Center Inches Letter 100.00 Single 50 −2 1000 2 2 1 0 $width 0 7 50 −1 −1 0. 25 open FILE.Scripts for PCB Inductor Generation use strict. print " -X <xpoff> Ground plane offset xpoff in x direction\n". 10 if ($opts{’h’}) { print "Usage: $0 [opts]\n". \#FIG 3. while (<FILE>) { chomp. push @data. ’<’ . 15 print " -p <planefile> Ground plane data file\n". but this is good enough for my purposes my $width = int((8/100 * $data[0][3])). 5 my %opts. 30 my @tmp = split(/. print <<END. getopts(’f:p:X:Y:h’. print " -Y <ypoff> Ground plane offset ypoff in y direction\n". \@tmp. print " -f <filename> Read data from filename (stdin)\n"./). my @data. 35 # we assume that width is the same for all of the points # maybe next time it would be good to use a diﬀerent width # for each one. 20 } $opts{’f’} | |= ’-’. exit(0). 40 my $numpoints = $#data + 1.000 1 0 −1 0 0 $numpoints END —102— . use Getopt::Std. \%opts). $opts{’f’} or die "Couldn’t open file: $!". print " -h Show this help screen\n". } close FILE.

pl suitable for simulation with the FastHenry ﬁeld solver [53]. int(${$data[$i]}[0] + $opts{’X’}). } for (my $i=0. int(${$data[$i]}[4] + $opts{’Y’}). int(${$data[$i]}[1] + $opts{’Y’})). push @data. int(${$data[$i]}[1] + $opts{’Y’}).pl generates a representation of data from spiral. int(${$data[$i]}[6] + $opts{’X’})./). use Getopt::Std. my @tmp = split(/.pl # make the pretty XFig picture for (my $i=0. while (<FILE>) { chomp. print int($data[$i][1]) . ’<’ .C. "\n". printf ("%d %d %d %d %d %d %d %d %d %d\n". $i++) { print int($data[$i][0]) . " ". $i++) { print "2 2 0 1 0 0 50 -1 20 0. 5 my @planedata.pl dat2ind.4 dat2ind. } 65 70 75 80 85 90 } C. $opts{’p’} or die "Couldn’t open plane data file: $!". # put in the ground planes if desired if ($opts{’p’}) { open FILE. #!/usr/bin/perl -w use strict. int(${$data[$i]}[0] + $opts{’X’}). int(${$data[$i]}[7] + $opts{’Y’}). $i<=$#data. int(${$data[$i]}[0] + $opts{’X’}). 60 } 55 @data = (). int(${$data[$i]}[3] + $opts{’X’}).4 dat2ind. int(${$data[$i]}[7] + $opts{’Y’}). \@tmp. $i<=$#data. —103— .000 0 0 -1 0 0 5\n".

if ($opts{’f’}) { if ($opts{’1’} | | $opts{’2’}) { print "Cannot specify both -f and -1/-2.\n". 50 print " -e Connect last point of <file1> to first point of <file2>\n". print " -Y <pyoff> Ground planes offset by pxoff in y axis\n". print " -s <sigma> print " -r <rho> Set resistivity to rho\n".max. print " -H <nhinc> Number of height increments (default 5)\n". \%opts). } 40 if ($opts{’h’}) { print "Usage: $0 (-f <file> | -1 <file1> -2 <file2>) [opt [opt [opt]]]\n". $opts{’h’}++. print " **NOTE** Input units must be mils\n". print " -h Show this help screen\n".4 mils = 1 oz Cu)\n". 20 } 15 $oneﬁℓe = 1. } 30 35 if ($opts{’s’} && $opts{’r’}) { print "Cannot specify both sigma and rho. print " -1 <file1> -2 <file2> Process two files connected together\n". } unless ($opts{’r’}) { $opts{’s’} | |= 1513. } elsif (!($opts{’1’} && $opts{’2’})) 25 { print "Must specify either -f or -1 and -2. my @data.84.ndec> Simulate from min to max with ndec pts/dec (default DC)\n".Scripts for PCB Inductor Generation my $oneﬁℓe = 0. Set conductivity to sigma (1/(mil*Ohm)) (default Cu)\n". 45 print " -f <file> Process a single file\n". print " -W <nwinc> Number of width increments (default 10)\n". $opts{’h’}++.\n". Ground plane data file\n". —104— . print " -p <planefile> print " -b Connect two files at initial points\n". print " -X <pxoff> Ground planes offset by pxoff in x axis\n".\n". $opts{’h’}++ unless ($opts{’f’} | | $opts{’1’} | | $opts{’2’}). print " -Z <pzoff> Ground planes offset by pxoff in z axis\n". 10 getopts(’f:1:2:F:p:bes:r:H:W:t:hX:Y:Z:’. 55 print " -t <thickness> Copper thickness (default 1. my %opts. $opts{’h’}++. print " -F <min.

$opts{’1’}) or die "Couldn’t open first input file: $!". $opts{’2’} . \@tmp. print ". " and " . $opts{’f’}) or die "Couldn’t open input file: $!". close FILE. my @tmp = split(/. print ". $opts{’r’}) : ("sigma=" . if ($oneﬁℓe) { open (FILE. $opts{’p’} or die "Couldn’t open ground plane file: $!". "<" . 100 if ($opts{’p’}) { open FILE.C. chomp @data. $opts{’H’} .units mil\n". "\n". ($opts{’r’} ? ("rho=" ./). push @planedata. 0. 75 @data = <FILE>. } —105— .pl 60 exit(0). $opts{’f’} . 95 } print ". chomp @{$data[0]}. $opts{’W’} . 105 110 while (<FILE>) { chomp. "<" .default nhinc=" .default " . " nwinc=" . $opts{’1’} .4 dat2ind. "\n". 85 @{$data[0]} = <FILE>. "\n". 90 close FILE. close FILE. 0. open (FILE. "0. } else { open (FILE. } $opts{’H’} $opts{’W’} 65 $opts{’t’} $opts{’F’} $opts{’X’} $opts{’Y’} $opts{’Z’} 70 | |= | |= | |= | |= | |= | |= | |= 5. print "* Conversion of " . 1.1". "<" .4. $opts{’s’})) . ’<’ . chomp @{$data[1]}.1. 80 print "* Conversion of " . $opts{’2’}) or die "Couldn’t open second input file: $!". @{$data[1]} = <FILE>. 0. "\n\n*NODES:\n". 10.

$tmp[1]. ${$pℓanedata[$i]}[9] | | 10. $j++) { my @tmp = split(/. printf ("E%d N%d N%d w=%g h=%g\n". $i<=$#data. $i. $i<=$#planedata. $i. $data[$i]). } 140 print "\n*EDGES\n"./. $i++) { my @tmp = split(/. $i<=$#data. $tmp[2]). $i++) { print "*file " . } if ($oneﬁℓe) { for (my $i=0. ${$pℓanedata[$i]}[8] + $opts{’Z’}. ${$pℓanedata[$i]}[5] + $opts{’Z’}. "\n". printf ("N%d x=%g y=%g z=%g\n".external N1 N%d". $tmp[3]. ${$pℓanedata[$i]}[10] | | 10). $opts{’t’}). $j. printf ("Nf%dn%d x=%g y=%g z=%g\n". for (my $i=0. $data[$i]). $i<2. $i++) { printf ("G%d x1=%g y1=%g z1=%g + x2=%g y2=%g z2=%g + x3=%g y3=%g z3=%g + thick=%g seg1=%g seg2=%g\n". $i++) 135 { my @tmp = split(/. ${$pℓanedata[$i]}[1] + $opts{’Y’}. } 145 printf ("\n. ${$pℓanedata[$i]}[2] + $opts{’Z’}. 155 for (my $j=0. $i++) { 165 —106— . $opts{’t’}. $i. } 160 } print "\n*EDGES\n"./. $i<$#data. 115 120 125 130 } for (my $i=0. $i. $i. $tmp[1]. $i+1. ${$pℓanedata[$i]}[4] + $opts{’Y’}. $opts{$i+1} . ${$pℓanedata[$i]}[6] + $opts{’X’}. $#data)./. $tmp[2]). } 150 else { for (my $i=0. for (my $i=0.Scripts for PCB Inductor Generation close FILE. $j<=$#{$data[$i]}. $tmp[0]. ${$pℓanedata[$i]}[3] + $opts{’X’}. ${$pℓanedata[$i]}[7] + $opts{’Y’}. ${$pℓanedata[$i]}[0] + $opts{’X’}. ${$data[$i]}[$j]). $tmp[0].

$i. printf ("Ef%dn%d Nf%dn%d Nf%dn%d w=%g h=%g\n".freq fmin=%g fmax=%g ndec=%g\n". $#{$data[0]}). $fmax. print " -f <file> Data file to read (stdin)\n". $opts{’F’}). $j. $ndec).pl 170 } 175 print "*file " . $tmp[3]. C. print " -p <planefile> Ground plane datafile\n". $fmin. if ($opts{’h’}) { 10 print "Usage: $0 -f <file> [opts]\n". $fmax.equiv Nf0n%d Nf1n1\n".C. } printf (". #!/usr/bin/perl -w use strict. for (my $j=0.external Nf0n1 Nf0n%d\n". $#{$data[1]})./. printf ("\n. 15 print " -X <xpoff> Offset ground plane by xpoff mils in x\n".pl dat2scr.pl generates placement scripts for the EAGLE CAD program [54] from data generated by spiral. $j. } else { print "\n.end\n". 190 print "\n. print " -x <xoff> Offset by xoff mils in x\n". getopts(’f:p:x:y:X:Y:h’. $#{$data[0]}). $i.5 dat2scr. $j++) { my @tmp = split(/.equiv Nf0n1 Nf1n1\n". print " -y <yoff> Offset by yoff mils in y\n". $ndec) = split(/. —107— . use Getopt::Std.external Nf1n1 Nf1n%d\n". \%opts). $i.5 dat2scr. "\n". $opts{$i+1} .pl. printf (". print " -Y <ypoff> Offset ground plane by ypoff mils in y\n". $j+1. ${$data[$i]}[$j]). $opts{’t’})./. print " -h Show this help screen\n". } 180 if ($opts{’e’}) { printf ("\n. exit(0). $j<$#{$data[$i]}. 185 } my ($fmin. 5 my %opts.

0. ’<’ . print "wire " . so we just go with the ﬁrst one my $width = $data[0][3] / 1000. my @tmp = split(/. 0.\n". $width . print((($data[$i][1]+$opts{’y’})/1000) . $i++) 45 50 55 60 65 70 —108— .\n". } print ". my @data. for (my $i=0. 0. " ". $i++) { print("(" . ")\n"). 0. @data = (). (($data[$i][0] + $opts{’x’})/1000) .Scripts for PCB Inductor Generation 20 } | |= | |= | |= | |= | |= ’-’. my @tmp = split(/. " "). while (<FILE>) { chomp. $opts{’f’} or die "Couldn’t open input file: $!". 35 push @data./). $i<=$#data./). \@tmp. push @data. } close FILE. if ($opts{’p’}) { open FILE. 40 # width should never change. ’<’ .\n". $i<=$#data. 30 while (<FILE>) { chomp. print "change layer $layer. print "set wire_bend 2. $opts{’p’} or die "Couldn’t open ground plane file: $!". } for (my $i=0. my $ℓayer = ($data[0][2] < 0) ? "bottom" : "top". \@tmp. $opts{’f’} $opts{’x’} $opts{’y’} 25 $opts{’X’} $opts{’Y’} open FILE.

pl placescr. #!/usr/bin/perl -w use strict. $i++) { 35 if (${$data[$i]}[0] eq "WIRE") { —109— .pl { 75 printf ("rect (%g %g) (%g %g).C. \@tmp. 5 my %opts. ($data[$i][0] + $opts{’X’})/1000.6 placescr.pl takes input from placedat and generates a script to place components on an EAGLE layout. $opts{’y’} | |= 0. 25 while (<FILE>) { chomp. } for (my $i=0. ($data[$i][6] + $opts{’X’})/1000. print " -y <yoff> Show this help screen\n". getopts(’f:x:y:h’. 20 $opts{’x’} | |= 0. if ($opts{’h’}) { 10 print "Usage: $0 -f <file> [opts]\n".6 placescr. $opts{’f’} | |= ’-’. \%opts). ’<’ . $i<=$#data. } } C. Data file to read (stdin)\n". my @tmp = split(/:/). ($data[$i][7] + $opts{’Y’})/1000). Offset by yoff mils in y\n".\n". print " -h 15 exit(0). use Getopt::Std. $opts{’f’} or die "Couldn’t open input file: $!". } my @data. 30 push @data. open FILE. ($data[$i][1] + $opts{’Y’})/1000. print " -f <file> print " -x <xoff> Offset by xoff mils in x\n".

$ypos = ($ypos+$opts{’y’})/1000. $driℓℓ. $width /= 1000. $L2). } } C. $diameter /= 1000. my ($L1. $xend. $ystart = ($ystart+$opts{’y’})/1000. $ystart. $yend = ($yend+$opts{’y’})/1000. $xstart. print "wire $width ($xstart $ystart) ($xend $yend). $driℓℓ /= 1000.7 qcalc. $rotation) = @{$data[$i]}.Scripts for PCB Inductor Generation my ($part.\n". $xpos = ($xpos+$opts{’x’})/1000.1415926535897932384626433832795. 5 # heh my $pi = 3. $xend = ($xend+$opts{’x’})/1000.mat ﬁle generated by FastHenry to provide self and mutual inductance and Qdata. $ypos = ($ypos+$opts{’y’})/1000. sub engnot { 10 # argument my $num = shift @ .\n". $yend. print "change layer $layer. print "change drill $drill.\n". $diameter.\nvia $diameter $shape ($xpos $ypos). #!/usr/bin/perl -w use strict. $xpos. 65 40 45 50 55 60 print "add $part $rotation ($xpos $ypos). return undef unless $num. —110— . } elsif (${$data[$i]}[0] eq "VIA") { my ($part. $xstart = ($xstart+$opts{’x’})/1000. } else { my ($part. $xpos. $ℓayer. $ypos.\n". $shape) = @{$data[$i]}. $ypos. $width) = @{$data[$i]}. $xpos = ($xpos+$opts{’x’})/1000.pl qcalc.pl parses the Zc.

my $ℓine1 = <>. $ℓ21. $expnt) = split(’e’. "\n".C. $basen *= 10**$adj. 2 * $pi * $freq * $L2 / $r22.pl which places components on the magnetic structure layouts. $ℓ12. $ℓine2). &engnot(($ℓ12 + $ℓ21) / (4 * $pi * $freq)).1 Miscellaneous Data Files placedat placedat contains input to placescr. " L1: ". b35n61:430:−480:R0 WIRE:430:−480:430:−100:top:50 C1812K:350:−130:R0 C1812K:510:−240:R0 5 C1812K:400:350:MR90 VIA:270:0:50:35:round WIRE:270:0:400:0:top:50 403a−03:340:−5:R0 WIRE:400:430:0:430:bot:50 10 VIA:0:430:75:50:square VIA:0:540:75:50:square WIRE:300:−350:300:−600:top:100 —111— . "\n". } 20 while (<>) { if (/Impedance matrix for frequency = (\S*)/) { 25 my $freq = $1. C. &engnot(($L1 = $ℓ11 / (2 * $pi * $freq))). $ℓ11. $num)). # get rid of the ’j’ in the L terms chop ($ℓ11. " Hz\n". $ℓine1). "e" .8 Miscellaneous Data Files 15 my ($basen. &engnot($freq).8. " Lm: ". 2 * $pi * $freq * $L1 / $r11. "\n". "\n". $expnt −= $adj. $r12. my $adj = $expnt % 3. 35 30 40 print print print print print print } } "Frequency: ". $ℓ21. " Q2: ". "\n".8 C. my ($r21. $expnt. my ($r11. $ℓ22). &engnot(($L2 = $ℓ22 / (2 * $pi * $freq))). my $ℓine2 = <>. " Q1: ". $r22. sprintf (’%e’. $ℓ12) = split(’ ’. return $basen . $ℓ22) = split(’ ’. " L2: ".

0.−500.5 −1000.500.5 500.−500.5.1000.−550.−550.−62.0. −1000.5 5 −1000.−62.1000.−550.10.500.1000.Scripts for PCB Inductor Generation WIRE:300:−350:300:−600:bot:100 C.1000.1000.−500.5 500.0.1000.1000.1000.5 −1000.−62.−62.500.0.5.0.500.−550.5 −1000.0.−500.1000.1000.5.−62.−550.0.10.5.0.1000.500.−62.500.1000.10.1000.500.8.−550.0.2 gpdat gpdat contains information on where to place the ground planes around the magnetic structures.5 —112— .1000.500.0.−62.−62.−1000.pl.−62.10.0.500.−62.−550. It is processed by dat2scr.500.1000.0.1000.−1000.−62.−62.pl and dat2ind.5 −1000.−550.

L2 is on the bottom side of the board. In the layout without cancellation. in the cases where cancellation is used.Appendix D Shunt Rectiﬁer PCB Layouts and Magnetic Structures Layouts for the shunt resonant rectiﬁers implemented in section 5. Lser connects from the input node to the trace above and to the left of the BNC. diagonal top left to bottom right hatching indicates copper on the top layer of the board.5 are provided in this appendix. also located on the bottom of the board. When no cancellation is employed. In the layouts. Crosshatching is used where both the top and bottom copper are present. the input signal comes from the BNC at the bottom right edge of the picture. In all cases. —113— . the cathode of the diode D connects from ground to the node adjoining Lser . the input node is simply shorted to the input of the magnetic structure in these cases. and provides room for several bypass capacitors and through-hole mounting for an output connector block. Cshn connects from the input trace to ground directly adjacent to the connector. The output node is located at the top of the layout. the diode cathode is simply shorted to one of the Lchoke pads. and connects to pads for Lchoke . but is connected to the other end of L1 . whereas top right to bottom left indicates the bottom copper. Since Lser is provided entirely by the coupled magnetic structures when cancellation is employed. D is located in the same place.

While it is not explicitly represented in the renderings. In all cases. the connection between L1 and L2 is located on the short overlapping segments. On the PCB. The renderings were made using the zbuf utility provided with the FastHenry software package [53]. the top winding is L1 and the bottom winding is L2 . this connection is implemented as a via. —114— . Figure D-1: Layout for shunt rectiﬁer without cancellation.Shunt Rectiﬁer PCB Layouts and Magnetic Structures The magnetic structures that were implemented are also represented in 3-dimensional renderings which give a more detailed structural view.

(b) PCB layout. Figure D-2: LM = 3.5 nH —115— .(a) 3D rendering of the magnetic structure.

(b) PCB layout. Figure D-3: LM = 4.0 nH —116— .Shunt Rectiﬁer PCB Layouts and Magnetic Structures (a) 3D rendering of the magnetic structure.

6 nH —117— .(a) 3D rendering of the magnetic structure. Figure D-4: LM = 4. (b) PCB layout.

Shunt Rectiﬁer PCB Layouts and Magnetic Structures (a) 3D rendering of the magnetic structure. (b) PCB layout.3 nH —118— . Figure D-5: LM = 6.

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