AccuCell

Introduction to Cell Characterization

Overview

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Objective of Cell Characterization Digital Design Tools that Use Standard Cell Models Input Data Files Required by Digital Design Tools Types of Standard Cell Libraries Input Views of Circuits – Bridging Analog and Digital Cell Library Attributes Cell Library Model Quality Synopsys Liberty Format (.lib) Characterization of Gates Characterization of Sequential Circuits

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Summary Slide
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Objective of Cell Characterization Digital Design Tools That Use Standard Cell Models Input Data Files Required by Digital Design Tools (Generated by AccuCell) Input Data Files Required by Digital Design Tools (Generated by Other Tools) Types of Standard Cell Libraries Digital Circuit Representation – Inverter Analog Circuit Description - Inverter Input Views of Circuits Bridging Analog and Digital Static Timing Analysis Use of Liberty Format Cell Library Attributes Measurements Cell Library Model Quality Liberty .lib File Structure Operating Conditions Cell Attributes in .lib File Datasheet View of AND2 Pin Attributes Setting Output Load Limits Delay Modeling Concepts Total Delay Equation Slope Delay Slew Modeling Intrinsic and Transition Delays Connect Delay Interconnect Delay Timing Arcs 3

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Combinational Timing Arcs Sequential Timing Arcs Timing Arcs Between Single and Multiple Pins Three-State Timing Arcs Edge-Sensitive Timing Arcs Preset Arcs Clear Arcs Defining Delay Arcs With Lookup Tables Defining Lookup Table Templates Assigning Values to Lookup Tables Timing Constraints Setup and Hold Constraints Non Sequential Setup and Hold Constraints Recovery Timing Constraints Removal Timing Constraints .lib of State Table Flip Flop .lib of Type ff D Flip Flop Components of Power Dissipation Power Modeling State Dependent Leakage Power Modeling Internal Power Lookup Tables Internal Power Calculations Clock Pin Power Output Pin Power Power Lookup Tables Descriptions 1D, 2D, 3D Internal Power Table for Cell Output Calculating Switching Power Switching Power Calculations

This set of models are used by several different digital design tools for different purposes. 4 .Objective of Cell Characterization ß Create a set of high quality models of a standard cell library that accurately and efficiently model cell behavior.

Digital Design Tools That Use Standard Cell Models ß Synthesis Tools ß Place and Routing Systems ß High level Design Language (HDL) Simulators (Verilog and ß ß ß ß ß ß ß VHDL) Floorplanning Tools Physical Placement tools Static Timing Analysis (STA) tools Power Analysis tools Formal Verification tools Automatic Test Program Generation (ATPG) tools Library Compiler 5 .

Input Data Files Required by Digital Design Tools (Generated by AccuCell) ß ß ß ß ß .html Technology library source files Generated Verilog simulation libraries Generated VHDL simulation libraries ATPG library Verilog testbench to compare SPICE to Verilog with same stimulus HTML datasheet 6 .lib .lib .v .vhd atpg.tbench ß .

Input Data Files Required by Digital Design Tools (Generated by Other Tools) ß .Abstracts or Bounding Boxes Cadence Encounter Files .LEF .db Compiled technology libraries in Synopsys internal ß ß ß ß ß database format Synopsys Milkyway Files .DEF GDS 7 .Abstracts or Bounding Boxes .

# of metals. sets. IP Vendors. scans. antenna diodes ß Optimized for Addressing Tradeoffs Between ß High speed. Scan Flops. AOI. resets. thick metal. 8 Fabless and IDMs . Gated Flops ß I/O Cells – Input pads. Complex ß Process Options ß Mask layer options. multiple oxides ß Cell Options ß Drive strengths. OAI ß Flops – Flip flops (D. special diffusions. gate shrinks. NOR. substrate ties. Latches. JK). XOR. low leakage. Bidirectional Pads.Types of Standard Cell Libraries ß There are often several cell libraries per semi process that typically contain 100 to 1. Output pads. RS. high density.000 cells including: ß Functions ß Gates – inverter. low voltage. AND. low power. low noise ß Cell Libraries are Produced by Foundries. NAND.

3)i1 (out. // basic inverter not #(5. Fall=3ns 9 . // Rise=5ns. in). in).Digital Circuit Representation – Inverter IEEE-1164 Verilog Logic States Strength State Value U Uninitialized Driven X Unknown Driven 0 Low Driven 1 High Z High impedance Resistive W Weak X Resistive L Weak 0 Resistive H Weak 1 -Don’t care Inverter Rise/Fall Diagram Verilog Language Description of Inverter not i1 (out.

0u .sch M3 y a gnd gnd nmos L=0.35u W=4.END 10 .35u W=4.... C2 …. C3 ….0u C1 ….35u W=4.0u M2 y a vdd vdd pmos L=0.END Transistor Inverter Schematic Schematic Netlist with Parasitics *svc_inv.35u W=4.Analog Circuit Description .0u M2 y a vdd vdd pmos L=0. .Inverter Schematic Netlist *svc_inv.sch M3 y a gnd gnd nmos L=0.

NCsim. SILOS ß Methodology has limitations on accuracy (load based only) ß STA is preferred methodology 11 . Modelsim. VCS.Input Views of Circuits Bridging Analog and Digital ß Timing back annotation for Verilog simulator (gate. behavioral) Model must work in Verilog-XL.

STA operates independently of characterization reading both a Verilog netlist and multiple timing libraries in Liberty format.Static Timing Analysis Use of Liberty Format ß In a standalone flow. 12 . It can also read interconnect parasitic data in SPF or SDF formats.

1. 4.24").00. variable_2 : fanout_pin_capacitance.0.186 .0. 3.0.0 . fanout_length(1.21. 3.0. 1. } lu_table_template(trans_template) { variable_1 : total_output_net_capacitance.12").5"). 2.12. interconnect_delay(wire_delay_table_template) values("0. } ß Pin Types ß direction ß function ß Loads ß Capacitive ß Active ß Fanout and wire loads ß Stimulus ß PWL for slope ß Active drivers ß Indexes ß Load ß Input slope 13 .39) .41".0.57".0. } wire_load("05x05") { resistance : 0 . slope : 0. index_3 ("0.10 0.0").23. area : 0 . index_1 ("1.0. "0.7. \ "0. index_1 ("0.5.0.44.Cell Library Attributes pin (A) { direction : output .41"). } lu_table_template(wire_delay_table_template) { variable_1 : fanout_number.00. 2. function : "X + Y" .11. index_2 ("0. capacitance : 1 .3". "0.3. variable_3 : driver_slew. 2. 0.0.

dynamic. internal ) (i. power arcs) 14 .Measurements ß ß ß ß ß ß Capacitance Thresholds/switching points Rise Time Fall Time Delay (propagation + transition = cell) (i. timing arcs) Power ( static state dependent leakage.e. shortcircuit.e. hidden.

Cell Library Model Quality ß Accuracy to silicon over the required power supply voltage. input signal slope range Completeness of characterization (state. thresholds) Conformance with digital tool value constraints (monotonicity) and multi-tool timing engine correlation Model Efficiency .speed of execution of model in digital tool that runs many times on large circuits using generated models Characterization time efficiency – runs once but characterizing a single flop can take hours Minimum size of model file . types[rise/fall]. indexes. especially with noise data 15 .lib files can become huge. units. pins ) – all timing arcs are included Conformance with digital tool format requirements (syntax. ß ß ß ß ß ß load range..

Synopsys Liberty . and design layout. supply voltage variations. ß Functional information ß Describes the logical function of every output pin of every cell so that the digital design tools can map the logic of a design to the actual technology. bus. all of which directly affect the efficiency of every design. ß Environmental information ß Describes the manufacturing process. ß Timing information ß Describes the parameters for pin-topin timing relationships and delay calculation for each cell in the library. operating temperature. 16 .lib File Structure ß Structural information ß Describes each cell’s connectivity to the outside world. including cell. and pin descriptions.

Liberty .lib File Library Level Attributes library (name) { technology (name) . routing_layers(string). bus_naming_style : string .unit). Default Units Defines units for entire library 17 . time_unit : unit . pulling_resistance_unit : unit . voltage_unit : unit . current_unit : unit . capacitive_load_unit(value. leakage_power_unit : unit ./* library-level attributes */ delay_model : generic_cmos | table_lookup | cmos2 | piecewise_cmos | dcm | polynomial .

voltage ß The operating voltage of the design tree_type ß The definition for the environment interconnect model. This factor is typically 1. process ß The scaling factor accounts for variations in the outcome of the actual semiconductor manufacturing steps. power_rail ß The voltage value for a power supply. temperature ß The ambient temperature in which the design is to operate.Operating Conditions ß name ß The name (WCCOM in the example) identifies the set of operating conditions.0 for normal operating conditions. ß ß ß ß ß 18 .

such as the parameters for pin-to-pin timing relationships. and pin structure that describes each cell’s connection to the outside world. 19 .lib File ß Structure ß The cell. and timing constraints for sequential cells. ß Power ß Modeling for state-dependent and path-dependent power ß Other parameters ß These parameters describe area and design rules.Cell Attributes in . ß Function ß The logical function of every output pin of each cell that digital design tools use to map the logic of a design to the actual technology. ß Timing ß Timing analysis and design optimization information. delay calculations. bus.

Datasheet View of AND2 ß Correlation between datasheet and .lib representation of a 2 input AND gate 20 .

A timing constraint such as setup and hold ß In the example. ß capacitance ß Defines the input pin load (input capacitance) placed on the network. The timing groups describe the following: ß . ß function ß Defines the logic function of an output pin in terms of the cell’s input or inout pins.A pin-to-pin delay ß . A and B are defined as input pins and Z as an output pin.Pin Attributes ß direction ß Defines the direction of each pin. Typical units of measure for capacitance are picofarads and standardized loads. ß timing ß Describes timing groups. the timing group for pin Z describes the delays between pin Z and pins A and B. 21 . In the example on the previous page. Load units should be consistent with other capacitance specifications throughout the library. the function of pin Z is defined as the logical AND of pins A and B. In the example.

ß max_capacitance ß Specifies the maximum total capacitive load that an output pin can drive. ß max_transition ß Specifies the maximum rise or fall transition time on an output due to total capacitive load. ß min_capacitance ß Specifies the minimum total capacitive load that an output pin can drive. ß min_fanout ß Specifies the minimum number of loads that a pin can drive. ß max_fanout ß Specifies the maximum number of loads a pin can drive.Setting Output Load Limits ß fanout_load ß Specifies how much to add to the fanout on the net. 22 .

Delay Modeling Concepts ß ß ß ß ß ß ß ß Total Delay Equation Total Delay Scaling Slope Delay Intrinsic Delay Transition Delay Connect Delay Interconnect Delay Delay Calculation Example 23 .

ß DC ß Connect media delay to an input pin (wire delay). ß DT ß Transition delay caused by loading of the output pin. 24 .Total Delay Equation ß Dtotal = DI + DS + DC + DT ß DI ß Intrinsic delay inherent in the gate and independent of ß particular instantiation. ß DS ß Slope delay caused by the ramp time of the input signal.

and voltage.Total Delay Scaling ß When calculating total delay. temperature. *Total Delay is typically measured from 50% to 50%. the digital tool scales each parameter of Dtotal individually. ß Each component of the total delay has its own global parameters to model the effects on the nominal case of variations in process. regardless of where transition thresholds are set 25 .

The attributes that define it in the timing group of the driving pin are slope_rise and slope_fall. This factor accounts for the time during which the input voltage begins to rise but has not reached the threshold level at which channel conduction begins. D is calculated with the transition delay at the previous output pin. This is not used by AccuCell. as shown here: ß This equation calculates both the rise and fall delays. use the “rise” parameter to calculate the rise delay and the “fall” parameter to calculate the fall delay. the calculation of DS enforces a global order on local analysis. ß SS ß Slope sensitivity factor. ß DT(prevstage) ß The transition delay calculated at the previous output pin. In some technologies.Slope Delay ß ß ß The slope delay of an element (DS) is the incremental time delay caused by slowly changing input signals. this delay is a strong function of the ramp time. plus a slope sensitivity factor. ß DS ß Transition delay is calculated at the previous stage of logic. 26 . Therefore. Where applicable.

ß The designated threshold points must fall within a voltage falling from 1 to 0 or rising from 0 to 1. or a bidirectional port. 27 .Slew Modeling ß Slew is the time it takes for the voltage value to fall or rise between two designated threshold points on an input. an output.

ß This equation calculates the rise and fall delays. The transition time of the output pin on a net is a function of the capacitance of all pins on the net and the capacitance of the interconnect network that ties the pins together. ß Transition Delay ß The transition delay of a circuit element is the time it takes the driving pin to change state. This portion is the fixed (or zero load) delay from the input pin to the output pin of a circuit element. 28 .Intrinsic and Transition Delays ß Intrinsic Delay ß The intrinsic delay of a circuit element (DI) is the portion of the total delay that is independent of the circuit element’s usage.

ß This delay is also known as time-of-flight delay.Connect Delay ß The connect delay of an element (DC) is the time it takes the voltage at an input pin to charge after the driving output pin has made a transition. 29 . which is the time it takes a waveform to travel along a wire.

ß Include the capacitance attribute in the pin group of the input pin.Interconnect Delay ß Interconnect delay is defined as the delay caused by connect delay and fanout. ß Give zero capacitance to the pin group of the output pin. ß Resistance is attributed entirely to the output pin. It is calculated as the sum of DT and DC. 30 .

output. Each timing arc has a startpoint and an endpoint. recovery or removal constraint between two input pins. ß All delay information in a library refers to an input-to-output pin pair or an output-to-output pin pair defined as: ß intrinsic delay ß The fixed delay from input to output pins. ß related_pin ß This attribute defines the pin or pins representing the startpoint of a timing arc. The only exception is a constraint timing arc. such as a setup. ß slope sensitivity ß The incremental time delay due to slow change of input signals.Timing Arcs ß ß ß ß ß Timing arcs can be delay arcs or constraint arcs. 31 . hold. Transition delay attributes represent the resistance encountered in making logic transitions. The startpoint can be an input. The endpoint is always an output pin or an inout pin. or inout pin. ß transition delay ß The time it takes the driving pin to change state.

The timing arc is attached to an output pin. ß A combinational timing arc is of one of the following types: ß combinational AND Gate With Timing Arc ß combinational_rise ß combinational_fall ß three_state_disable ß three_state_disable_rise XOR Gate With State-Dependent Timing Arc ß three_state_disable_fall ß three_state_enable ß three_state_enable_rise ß three_state_enable_fall 32 . AccuCell does not use these. and the related pin is either an input or an output.Combinational Timing Arcs ß A combinational timing arc describes the timing characteristics of a combinational element.

or removal_falling) ß • No change (nochange_high_high. removal_rising. nochange_low_low) 33 .Sequential Timing Arcs ß A sequential timing arc is of one of the following types: ß Edge-sensitive (rising_edge or falling_edge) ß Preset or clear ß Setup or hold (setup_rising. or hold_falling) ß Nonsequential setup or hold (non_seq_setup_rising. recovery_falling. nochange_high_low. hold_rising. non_seq_hold_rising. setup_falling. non_seq_hold_falling) ß • Recovery or removal (recovery_rising. non_seq_setup_falling. nochange_low_high.

Timing Arcs Between Single and Multiple Pins Pin and a Single Related Pin Pin and Multiple Related Pins *Timing Arcs can also be between pins. and busses 34 . groups.

Three-State Timing Arcs ß Assign related_pin to the enable pin of the three-state function. 35 . ß Define the Z-to-0 propagation time with the intrinsic_fall statement. ß Define the Z-to-1 propagation time with the intrinsic_rise statement. ß Include the timing_type : three_state_enable statement.

the path tracer propagates only the active edge (rise or fall) path values along the timing arc. ß rising_edge ß Identifies a timing arc whose output pin is sensitive to a rising signal at the input pin. ß These arcs are path-traced. 36 . are identified by the following values of the timing_type attribute in the timing group. ß falling_edge ß Identifies a timing arc whose output pin is sensitive to a falling signal at the input pin. such as the arc from the clock on a flipflop.Edge-Sensitive Timing Arcs ß Edge-sensitive timing arcs.

37 . The source pin is active-high. This calculation produces the rise arrival time on the arc’s endpoint pin. ß non_unate ß Indicates that the maximum of the rise and fall arrival times of the arc’s source pin is used to calculate the arc’s delay. ß negative_unate ß Indicates that the fall arrival time of the arc’s source pin is used to calculate the arc’s delay. In the case of slope delays. In the case of slope delays.Preset Arcs ß Select ß timing_type : preset. The source pin is active-low. the source pin’s fall transition time is added to the arc’s delay. This calculation produces the maximum arrival time on the arc’s endpoint pin. ß timing_sense : ß positive_unate ß Indicates that the rise arrival time of the arc’s source pin is used to calculate the arc’s delay. the source pin’s rise transition time is added to the arc’s delay. In the case of slope delays. This calculation produces the rise arrival time on the arc’s endpoint pin. the maximum of the source pin’s rise and fall transition times is added to the arc’s delay.

In the case of slope delays. In the case of slope delays. This calculation produces the maximum fall arrival time on the arc’s endpoint pin. In the case of slope delays. the source pin’s rise transition time is added to the arc’s delay. This calculation produces the fall arrival time on the arc’s endpoint pin. ß Select ß timing_type : clear. The source pin is active-low. The source pin is active-high.Clear Arcs ß Clear arcs affect only the fall arrival time of the arc’s endpoint pin. This calculation produces the fall arrival time on the arc’s endpoint pin. ß non_unate ß Indicates that the maximum of the rise and fall arrival times of the arc’s source pin is used in calculating the arc’s delay. the maximum of the source pin’s rise and fall transition times is added to the arc’s delay. the source pin’s fall transition time is added to the arc’s delay. 38 . ß negative_unate ß Indicates that the rise arrival time of the arc’s source pin is used to calculate the arc’s delay. ß timing_sense : ß positive_unate ß Indicates that the fall arrival time of the arc’s source pin is used to calculate the arc’s delay. A clear arc means that you are asserting a logic 0 on the output pin when the designated related_pin is asserted.

Defining Delay Arcs With Lookup Tables

ß Transition time is the time it takes for an output signal to
make a transition between the high and low logic states. With nonlinear delay models, it is computed by table lookup and interpolation. Transition delay is a function of capacitance at the output pin and input transition time. ß Group attributes: To specify cell delay independently of transition delay, ß cell_rise use one of these timing group attributes as your lookup table: ß cell_fall ß rise_propagation To specify transition delay as a term in the total cell delay, use one of these timing group attributes as your lookup table ß fall_propagation ß retaining_rise ß retaining_fall ß retain_rise_slew ß retain_fall_slew
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Defining Lookup Table Templates

ß CMOS Nonlinear Delay Model is
specified by a one or two dimensional table of delay values dependent on input net transition and output capacitance

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Assigning Values to Lookup Tables

ß Referring to tables
defined in previous slide ß Pin a is two dimensional 4X4 ß Pin b is one dimensional X4 ß These timing values are the results of SmartSpice .MEASURE statements within AccuCell
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ß recovery and removal arcs ß Use the recovery timing arc and the removal timing arc for asynchronous control pins such as clear and preset. before latching its value.Timing Constraints ß setup and hold arcs ß Set these constraints to ensure that a data signal has stabilized. ß skew ß This is another constraint that the VHDL library generator uses for simulation. 42 . ß You can also set state-dependent and conditional constraints.

Setup and Hold Constraints Setup and Hold Constraints for Rising-Edge-Triggered Flip-Flop Setup and Hold Constraints for High-Enable Latch 43 .

the setup and hold timing constraints are specified on the data pin with a nonclock pin as the related pin. ß The signal of a pin must be stable for a specified period of time before and after another pin of the same cell range state for the cell to function as expected.Non Sequential Setup and Hold Constraints ß In some nonsequential cells. Nonsequential Setup and Hold Constraints 44 .

Recovery Timing Constraints Recovery Timing Constraint for a Rising-Edge-Triggered Flip-Flop Recovery Timing Constraint for a Low-Enable Latch 45 .

ß The removal constraint describes the minimum allowable time between the active edge of the clock pin while the asynchronous pin is active and the inactive edge of the same asynchronous control pin No-Change Timing Check ß No-Change Timing Constraints ß You can model no-change timing checks to use in static timing verification during synthesis. 46 . and during an established hold period. ß A no-change timing check checks a constrained signal against a levelsensitive related signal.Removal Timing Constraints Timing Diagram for Removal Constraint ß Removal Constraint ß This constraint is also known as the asynchronous control signal hold time. for the width of the related pulse. ß The constrained signal must remain stable during an established setup period.

.lib of State Table Flip Flop 47 .

In this example IQ is assigned the value of the D input. ß ß ß 48 . rather than the internal_node attribute. IQ and IQN The next_state equation determines the value of IQ after the next clocked_on transition.lib of Type ff D Flip Flop ß The ff group statement ß replaces the statetable group statement The function attribute.. defines the output pin’s function The D flip-flop defines two variables.

Components of Power Dissipation 49 .

This can be handled in two ways: ß Include the effect of the output capacitance in the internal_power group (defined in a pin group within a cell group). and model only the short-circuit power as the cell’s internal power (in the internal_power group) ß Switching Power ß Switching (or interconnect) power is the power dissipated in the circuit as a result of a logical transition of the capacitive load. ß Short-Circuit Power ß Short-circuit or internal power is the power dissipated whenever a pin makes a transition.Power Modeling ß Leakage Power ß Leakage power is the static (or quiescent) power dissipated when a gate is not switching. 50 . which gives the output pins zero capacitance ß Give the output pins a real capacitance. which causes them to be included in the switching power. Switching power (along with internal power) is used to compute the design’s total dynamic power dissipation.

State Dependent Leakage Power ß Leakage power is state dependent based on input pin state values 51 .

When you model the library. ß Because a table indexed by T input transition times and C output load capacitances has TxC entries. if internal power will be modeled by use of a 3x3 table at the output of the cell. ß For example. the design will have 9 input voltage transitions—output load combinations where energy dissipation must be measured. or three-dimensional internal power lookup table indexed by the total output load capacitances (best model). ß The library group supports a one-. the input transition time. the cell’s internal power must be characterized TxC times. 52 . or both.Modeling Internal Power Lookup Tables ß You should measure the energy dissipated by varying either input voltage transition or output load while holding the other constant. avoid double counting. ß NOTE: The input pin power is added to the output pin power. two-. once for each input transition time and output load capacitance combination.

Modeling Internal Power Lookup Tables Power is calculated by integrating energy 53 .

ß Accurate sequential modeling requires a separate table for the clock and for the output pin the clock controls. because a clock pin often toggles without causing any observable state change on the output pin. use the following equation: ß PInt ß Total internal power for the cell. ß E ß Internal energy for the pin. ß AF ß Activity factor. The two tables are used to ensure that clock pin power and output power are accounted for separately.Internal Power Calculations ß To calculate the internal power for cell U1. 54 .

55 . because the measurement is done for two transitions of the clock. the energy measured must be divided by 2 to get the energy dissipated by the clock pin transition. A onedimensional internal power table indexed by input transition time should be attached to the clock pin. ß Clk_Pin_Energy = Clk_Total / 2 ß Add Clk_Pin_Energy as an entry indexed by input transition time in the one-dimensional internal power table attached to the clock pin. Total energy dissipated in the cell during this simulation is measured.Clock Pin Power ß This energy is characterized by simulation of a single full cycle (one rise transition and one fall transition) of the clock. If separate rise and fall power modeling is not used. with no transition at the output and input pins.

because the measurement is done for two transitions.2*(Clk_Pin_Energy) 56 . A twodimensional internal power table should be attached to the output pin. with two rise and fall transitions at the output. ß Output_Pin_Energy = (Out_total)/2 . the energy measured must be divided by 2. Total energy dissipated in the cell during the two-full-cycle simulation (Out_total) is measured.Output Pin Power ß This power is characterized by simulation of two full cycles of the clock. If separate rise and fall power modeling is not used.

Power Lookup Tables Descriptions 1D. or three-dimensional templates. two-. 3D ß The example at left shows shows four power_lut_template groups that have one-. ß The index values are lists of floating-point numbers greater than or equal to 0.0. ß The number of floatingpoint numbers in the indexes determines the size of each dimension 57 . 2D. ß The values in the list must be in increasing order.

Internal Power Table for Cell Output 58 .

ß An explicit units attribute is not required for switching power. and capacitance attributes. switching power is used to compute the design’s total dynamic power dissipation.Calculating Switching Power ß Switching (or interconnect) power is the power dissipated in the circuit as a result of a logical transition of the capacitive load ß With internal power. ß Switching power information is a function of a net’s capacitive loading. 59 . associated clock frequency. and the supply voltage level of the design. time. because the units are implicitly determined by the units of the voltage.

a toggle rate of two transitions every 100 ns.Switching Power Calculations ß For a single net with a total load of 100 femtofarad. ß CLoad ß Capacitive load of each net. and a supply voltage of 5 volts. 60 . the calculation of the net’s power dissipation is: ß TR ß Toggle rate (number of toggles per unit of time).

Syllabus for Advanced Cell Characterization ß ß ß ß ß ß ß ß ß ß ß Review of Introduction to Cell Characterization Latches Scan Flop Gated Clocks Definition of I/O cell terms Example of I/O Cell Active Loads Active Drivers Derating factors. K factors Verilog Timing Checks Noise Considerations (CCS. ECSM) 61 .

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