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Static Timing Analysis

Introduction
Depending on the design methodologies used, three types of timing analysis methods are commonly used: Manual analysis, static timing analysis and dynamic timing analysis. Latch based designs are not common in large-scale integration, a separate section is attached at the end of the notes to cover latch based static timing analysis.

Manual analysis consists of taking a schematic or a netlist to determine the times

signals arrive or leave at the input and output ports of the design, and calculating the delay time for the path by adding up the delay times for each component in the path. The objective of the process is to ensure that all signals meet the circuit constraints. This method works well for simple circuits and it is undesirable for large or iterative design process.

Dynamic timing analysis verifies circuit timing by applying test vectors to the
circuit. This approach is an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths. The most common dynamic timing analysis is the so-called min-max analysis method. Under min-max timing analysis, both minimum and maximum delays of circuit components are used to generate outputs, which are ranges (the spread of earliest data and latest arrival data) instead of edges. Since outputs are in turn fed into inputs, managing the ranges (merging them) can become very complex. As can be seen, if both min version & max version of the delays must be used, the simulation speed will be extremely slow. Another major issue with dynamic timing analysis is the incomplete coverage. It may only check circuitry that is exercised by test stimulus, which may leave critical paths untested, and timing problems undiscovered. It is also not path oriented. Since dynamic timing analysis reports errors on a certain pin at a certain time, the user must trace through the schematic to locate the path that caused the problem (difficult for large designs). Finally this method requires development time for test vectors. Dynamic timing analysis tools often track more information than logic simulators, making their performance slower. Also each component must contain both timing information and a functional model before timing verification can proceed. This could prevent the use of new parts that do not have functional models. It should be noted that min-max simulation is not currently used in the industry. Instead, either functional simulation with timing (timing simulation) or formal verification method is typically used to verify complex IC designs. Typically people use the max version of delays to verify the circuit works under worst-case timing (no setup issues) and min version of the delays to verify best-case timing (no hold issues).

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Static timing analysis verifies circuit timing by adding up propagation delays

along paths between clocked elements in a circuit. It checks the delays along each path against the specified timing constraints for each circuit path and reports any existing timing violations. Static timing analysis tools can determine and report timing statistics such as the total number of paths, delays for each path and the circuits most critical paths. As design complexity increases, performing timing analysis manually becomes extremely difficult and sometimes even impossible. With increasing popularity of HDL based design methodologies, static timing analysis becomes increasingly popular among digital logic designers. To summarize, both static and dynamic timing analysis methods offer tradeoffs. One is not a replacement for the other. However, the static timing analysis method offers more complete coverage, little overhead, and the ability to report errors in terms of the design schematic.

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Commercially Available Static Timing Analysis Tools

The following Static timing analysis tools are the most popular ones by ASIC designers. Synopsys Inc: Cadence Design Systems: PrimeTime & DesignTime Pearl

Dynamic Timing Analysis Summary

Advantages: 1. Extends coverage of circuit simulation (edges to region). 2. Evaluates worst-case timing using both minimum and maximum delay values for components. 3. Uses the same test stimulus as logic simulation. 4. Does not report false errors. Disadvantages: 1. It is not complete. 2. It is not path oriented. 3. It is slower than logic simulation and may require additional test stimulus. 4. It requires functional behavioral models. Dynamic timing analysis extends logic simulation by reporting violations in terms of simulation times and states. To test circuit timing using worst-case conditions, dynamic timing analysis evaluates the circuit using minimum and maximum propagation delays for each component for each component in the design.

Since dynamic timing analysis performs a simulation, it can use the same stimulus as a logic simulation. Because the stimulus functionally exercises the design, false errors of unused or uninteresting paths are not tested. Note a timing simulation reports results differently than a logic simulation. A logic simulation reports results as edge times and a timing simulation reports results as regions of ambiguity. The results of a timing simulation do not specify exactly when an event occurs, they specify a range of time in which an event can occur.

Static Timing Analysis Summary

Advantages: 1.It resembles manual analysis methods. 2. It is path oriented and finds all setup and hold violations. 3. It does not require stimulus or functional models. 4. It is faster than simulation. (for the same amount of coverage)

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Disadvantages: 1. It can report false errors. 2. It cannot detect timing errors related to logical operation. Static timing analysis is similar to manual analysis process, except that it is automated. This allows the design to be analyzed much faster. This makes it possible for a designer to experiment with different synthesis options and constraints in a short time. This method is also complete because it traces and evaluates all paths in a design, not just those exercised by test stimulus. Because static timing analysis does not perform logic simulation, test stimulus and functional models are not required. This makes static analysis available earlier since development time for stimulus and models are not required. The modeling requirements for a static analysis tool are relatively simple. However, timing information for each component in the design is required and the designer must specify waveform information about the input data and clock signals the design uses. The component timing information can be found in parts libraries or data books. Such timing information typically include: pin-to-pin delays, setup, hold time specifications and signal inversion information, and clock frequency constraints. Clock and data waveforms are a normal requirement of the design process, and do not require additional development time. The major drawback of a static timing analysis tool is that it reports false errors. By checking all possible paths in a design, static timing analysis ensures that all possible setup and hold violations in the circuit have been found. However, the potential to detect some false errors exists since circuit behavior is not considered during the analysis. Static analysis tools cannot detect timing errors related to logical operation. Because static timing analysis does not perform functional testing, it cannot detect timing errors, such as race conditions, that are based on the logical operation of the circuit.

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Timing Models
Static timing analysis tools typically use timing models at the logic primitive level. The timing parameters are typically similar among different timing tools. The following are some of the common timing parameters for primitive logic gates, flip-flop and latch.

Timing Measurements for Primitive Gates

Transition time is the time between one specified voltage level and another voltage level for a given signal. Transition rise time is the time between a specified low voltage level and a specified high voltage level. Transition fall time is the time between a specified high voltage level and a specified low voltage level.

transition time measurement

rise time

fall time

Propagation delay time is the time between the specified reference points on the input and output voltage waveforms with the output changing from one defined level (high or low) to the other defined level. Propagation delay time up is the time between the specified transition reference points on the input and output voltage waveforms with the output changing from low level to the defined high level. Propagation delay time down is the time between the specified transition reference points on the input and output voltage waveforms with output changing from high level to the defined low level.
Propagation Delay Time Measurement A A B Z Z time up time down

Timing Measurements for Edge Triggered Flip-Flops

Setup time is the time interval between a specified transition reference point of the data input signal and a specified transition reference point of the clock input signal. Setup time

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is specified as the shortest interval for which correct operation of the flip-flop is guaranteed. Hold time is the time interval between a specified transition reference point of the clock input signal and a specified transition reference point of the data input signal. Hold time is specified as the shortest interval for which correct operation of the flip-flop is guaranteed. Propagation delay time is the time between the specified transition reference points on the clock input and data output voltage waveforms with the output changing from one defined level (high or low) to the other defined level.
Edge Triggered Flip-Flop Timing Measurements C D Q C D setup Q hold time C to Q

Timing Measurements for Level Sensitive Latches

The definition of setup time and hold time for a latch are the same for those for an edge triggered flop-flop. However, reference points are not the same as shown in the wavefom diagrams. In this case, the timing measurements are for the transparent mode. Note that the control to output measurement is not quite accurate in this case. Propagation delay time is the time between either the specified transition reference points on the control input or the data input and data output voltage waveforms with the output changing from one defined level (low or high) to the other defined level.

setup

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Common Features of Static Timing Analysis Tools

Static timing analysis tools are used for three major purposes: design characterization, design analysis & verification and design debugging (tracing). Characterization involves deriving a timing model for the design under analysis. The circuit critical paths are typically derived during the characterization mode. This model can be used for board level or system level timing analysis. In the analysis mode, the given design is analyzed under a given timing environment where clock frequency, data arrival times, data required times and other constraints are given. In additional to performance estimation, lower level modules can be characterized so that they can be used hierarchically to reduce overall analysis time.

Given a system performance requirement, often a maximum frequency, a designer would often want to know if the design would operate reliably under the given system timing environment. The environment includes the input signal arrival time as well as the required departure times (also referred to as stable time and required time) of the output signals. Most timing analysis tools also provide a tracing capability for debugging purposes. Typically a source and a destination are selected, and the timing analysis tool would trace all the paths or a subset of them based on some threshold delay value.

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Timing Environments
Most design modules are specified to meet certain performance goals. For synchronous digital circuits, the most common parameters used to describe the timing environments include the system clock frequencies, input arrival times, output required times, output loads, input loads and drive strengths on the input side. The following diagram shows typical design environments settings:

set drive

set operating conditions set wire load create clock definition set max area

set max capacitance set max transition set max fanout set output delay

set drive or set drive cell set Resistance set Capacitance set max capacitance set max transition set max fanout set input delay

set multicycle paths set false paths set max delay paths set min delay paths

set R C

The left hand side parameters specify timing environment parameters on inputs; the right hand side parameters specify timing environment parameters on outputs. The ones in the middle are typically the parameters for the design itself. Refer to notes on how to set design constraints using Synopsys design compiler.

Timing Paths Definitions

There are four types of timing paths in a synchronous design. They are primary input to register, register-to-register, register to primary output and primary input to primary output. For each type of paths, constraints can be applied so that a static timing analyzer can check the circuit for any potential violation: 1. Primary input to register paths This type of paths can be constrained by defining the clock for the register and setting the input delay for the input (arrival time) with respect to the clock.

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2. Register to register paths This type of paths can be constrained by defining the clock(s) for the registers. 3. Register to primary output paths This type of paths can be constrained by defining the clock for the register and setting an output delay relative to a clock on the output port (departure time). 4. Primary input to primary output paths This type of paths can be constrained by setting an input delay on the input port (arrival time), and minimum and/or maximum delays required at the output (departure time).

Path Analysis
Path analysis is the most fundamental type of analysis and is used as basis for slack analysis, critical path identification and timing model generation (e.g. extracting chip level timing models for board level timing analysis).

Ambiguity Region of a Design

Because the specifications for circuit devices have a tolerance range associated with them, signals that propagate through a device contains a region of ambiguity. This region is the range of time in which the signal arrives at or leaves the device and it is denoted by minimum and maximum signal edges. To perform a worst case analysis, the longest delay from the longest paths are used to make sure that the slow signals will still make it on time with enough setup time. To perform a best case analysis, the shorted delay from the shorted paths are used to make sure that the fast signals will be stable long enough to meet the hold time requirement.

When a static timing tool calculates a path delay, it propagates min and max delay values for both rise and fall transitions. After tracing, each path would have four values: output rise min (tRmin), output rise max (tRmax), output fall min (tFmin) and output fall max (tFmax). During path tracing, the output polarity causes the signal to change polarity as well. A path has a source and a destination. If the shortest paths are needed, both the rise and fall min paths (tRmin and tFmin) for each individual path is compared to others to find the ones with minimum delays. If the longest paths are needed, both the rise and fall max paths (tRmax and tFmax) for each individual path is compare to others to find the ones with max delays.

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Example: Determine the path delays for the following circuit segment:

rise=(8,10) fall=(3,5)

rise=(6,8) fall=(2,4)

rise=(7,9) fall=(4,6)

Path delays for the above path: tRmin = 8 + 2 + 7 = 17ns tRmax = 10 + 4 + 9 = 23ns tFmin = 3 + 6 + 4 = 13ns tFmax = 5 + 8 + 6 = 19 Example: Determine the path delay for the following circuit segment:

rise=(8,12) fall=(4,6)

rise=(6,8) fall=(2,4)

rise=(8,12) fall=(4,6)

For the above simple path A to Z: tRmin = 8+6+4 = 18 tRmax = 12+8+6=26 tFmin = 4+2+8 = 14 tFmax = 6+4+12=22

Longest and Shortest Paths Calculation

For each input pin to an output pin of a basic component, there are four or six numbers (in this case, these six numbers are made of minimum, typical and max for both delay up and delay down). In the following sections, if a single number is used, we assume that the delay rise and delay fall are the same. Also the minimum, typical and maximum delays are assumed to be the same. For simplicity, we may just use a single number for a component to represent its delays for all the paths in the logic component.

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A timing analyzer calculates the delay of a path by tracing from a starting point of the path to its ending point, cumulatively adding delays along the way. The longest path is the path that has the largest delay from start point to end point. The shortest path is the path which has the smallest delay from start point to end point. When calculating the longest and shortest paths, the clock to Q delay of a flip-flop are also included in the calculation. Example: Given that the inverter g1 has delay of 20ns, the AND gate g2 has delay of 40ns, the AND gate g3 has delay of 30ns and the OR gate g4 has delay 30ns, calculate the longest and shortest path from A to F:

B g2 A g1 20ns g3 C D 40ns

H F g4 30ns

E 30ns

After exhaustively trace all the paths from A to F: The longest path: Ag1Dg2Hg4F = 20+40+30=90ns The shortest path: Ag3Eg4F = 30+30 = 60ns

Timing Characterization
In the following scenarios, a design/module needs to be characterized: 1. Hierarchical timing analysis 2. For Reuse 3. Feasibility studies 4. A custom block A typical design/module can be fully characterized (timing wise for verification) with the following parameters: 1. Max internal frequency 2. Setup and hold time requirements for the first level flip-flop elements with respect to primary inputs 3. Clock to output delays for the last level flip-flop elements 4. Primary inputs to primary outputs delays The following sections show how these timing parameters can be calculated:

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Maximum Frequency Calculation

One way to calculate the frequency is to take the longest path in a circuit and use it as the basis for estimating a maximum frequency. The problem with this approach is that the longest path may not be a register to register path in which case the clock to register output and register setup time are not known. Also primary input to register delay and register to output delay may not be complete to calculate frequency. It is more often that the frequency calculation is performed for register to register paths. If a design does not have any registers or if a design has only one level of registers, frequency calculation is typically not performed, or the exact input arrival time and the output required time must be known. In another word, the timing environment must be complete. To get the maximum frequency, the minimum clock period is first estimated. This is done by adding up the maximum clock to output delay of the source register, the maximum path delay from source register Q output to destination register D input and the setup time of the destination register. That is: Max frequency = 1/(minimum clock period) = 1/(clkQ + max path + setup) Example: Given the following circuit, if the longest delay from Q1 to D2 is 90ns, the delay from C1 to Q1 of the source register is 10ns, and the setup time of the destination register is 5ns, calculate the maximum frequency.

IN3 IN1 D1 IN2 C1 CLK C2 Q1 D2 Q2

OUT2

OUT1

The minimum clock period would then be 10 + 90 + 5 = 105ns The maximum frequency is 1/(minimum clock period) = 1/105 = 9.5Mhz

Setup Time and Hold Time Evaluation at the Primary Inputs

Once a design is synthesized into gate level technology dependent network, a static timing analyzer can characterize the setup time and hold time at the chip primary inputs. The first task is to identify the clock and data signals at the primary inputs. This can be done by tracing back from all register data inputs and register clock inputs to the chip primary inputs.

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The following formula can be used to calculate the setup time and hold time at the chip level: setup time = (longest data path delay) (shortest clock path delay) + (setup time of register) hold time = (longest clock path delay) (shortest data path delay) + (hold time of register) Since both the data path and the clock path can be independent of each other, the setup and hold time of the chip level model can be either positive or negative. However, the sum of the setup time and hold time with respect to one pair of clock and data paths should be greater equal to zero. The setup and hold values on a sequential logic element such as a FF can be derived in a similar why using transistor level models with C and R. Example: In the circuit below calculate the setup and hold time for the circuit at the primary inputs with the following given information: The setup time for the registers are 10ns The hold time for the registers are 5ns The longest and shortest paths from clock to FF1 and FF2 are both 20ns The longest and shortest paths from in1 to D1 are both 100ns The longest and shortest paths from in2 to D1 are both 40ns

in1

FF1
D1 Q1

FF2
D1 Q1

out1

in2

clk

The setup and hold time calculations with respect to register FF1 are: The setup time of port in1 to port clk is: 100 20 + 10 = 90ns The hold time of port in1 to port clk is: 20 100 + 5 = -75ns The setup time of port in2 to port clk is: 40 20 + 10 = 30ns The hold time of port in2 to port clk is: 20 40 + 5 = -15ns

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Clock to output Delays

Clock to output delays can be calculated by adding up the following types of delays: Delay from primary clock port to the last level flip-flop clock pin delay (tcp) Clock to output delay of the flip-flop (tcq) Flip-flop output to primary output (tcom)

Clock to output delays (Tco) can be calculate using: Tco = (tcp) + (tcq) + (tcom)
Out1 Tcom Out2 Tcq Out3

Clk

Tcp

Not that in the above drawing, there will be three sets of clock to output delays one set for each of the output ports: Out1, Out2 and Out3. Each clock to output pair will consist of the following delays (assuming flip-flop is rising edge triggered): Max clock to output for data rising Min clock to output for data rising Max clock to output for data falling Min clock to output for data falling

Primary inputs to Primary outputs

If primary inputs to primary output paths exist (for a combinational circuit, there are only primary input to output paths), they need to be characterized. The longest and shorted paths calculation methods introduced earlier can be used for this purpose. For each input to output path, the following will be calculated:

Max input to output rise (using longest path, max component delay) Min input to output rise (using shortest path, min component delay) Max input to output fall (using longest path, max component delay) Min input to output fall (using shortest path, min component delay)

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Timing Verification and Slack Analysis

Slack analysis is a specialized type of timing analysis that applies specifically to synchronous logic designs. These designs require that data and clock signals are synchronized for circuitry to operate properly. Besides sequential elements in a circuit, slack analysis can be applied to any circuit element based on internal and external timing constrains. Slack analysis is only meaningful if the circuit is properly constrained with the correct timing environment. Slack time is defined as the difference between the required time and actual time: slack = required data arrival time actual data arrival time The following circuit shows how slack calculation is performed for a simple combinational circuit before the more complicated setup/hold slack analysis. Example: Assuming each component delay is 5 for both rise and fall. The data arrival time at the inputs are all 3 and the data required time at the function output L is 20. Calculate the slacks for each of the component inputs and outputs.
A 10-3=7
F

15-8=7

7 B 7 C D 2
5-3=2

7 H

K -3

7
I

20-23 = -3

J -3

10 13=-3

-3

15 18 = -3

-3

The required time at output L is propagated backward to derive the required time for each component and nets. The slack time is the difference between the required time and the actual data arrival time. The slack numbers are labelled on the nets and it can be seen that the path with worst slack is the critical path. Only two types of slack analysis are covered in detail here: setup slack and hold slack. Setup slack analysis determines whether or not data arrives and is valid at the input of a synchronous device before the input clock arrives. Hold slack analysis determines whether or not data remains at the input of a synchronous device long enough to be clocked into the device.

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Setup Slack Analysis (single cycle data transfer)

When performing a setup slack analysis, the maximum edge of the data signal and the minimum edge of the corresponding clock signal are used. This check determines if the devices (memory element) latest arriving data signal will meet the setup constraint for its earliest arriving clock signal. The setup slack can be calculated using the following equation: Setup slack = Clock Period + minimum clock path maximum data path setup

Hold Slack Analysis (single cycle data transfer)

When performing a hold slack analysis, the minimum edge of the data signal to the maximum edge of the corresponding clock signal is used. This check determines if the devices earliest changing data signal will meet the hold constraint for its earliest arriving clock signal. The hold slack can be can be calculated using the following equation: Hold slack = minimum data path maximum clock path hold Question: Why is the clock period is not part of this equation?

In case you have read static timing analysis in literature, you may wonder why some slack analysis relations include the clock period for the destination register, and others do not. In this note, the clock period is included. The reason for such difference is due to the selection of reference point. The following two drawings demonstrate the difference in selecting the reference points. Using absolute time reference for clock path:
max_data_path for setup data data launch here data capture here clock t=0 min_clock_path (includes T)

From the above diagram (assuming the clock is not gated), it can be seen that the clock edge of interest would include one clock period if absolute time scale is used. The longest data delay with respect to the clock edge is the third transition on the data for setup check. The data transition for hold check is the fourth transition on data which happens after the clock edge.

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If the data goes too fast, the fourth edge will be shifted to the left and this is why fast data causes hold violation.

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data stable reference for hold

data

clock data launch edge for setup t=0 data capture edge for setup

If the time reference point is chosen at the active clock edge of the destination register, it can be seen from the diagram that the clock delay must be compensated by a clock period for setup check. Otherwise the wrong edge will be compared. However, the transition for hold check happens after the clock edge, so that it is not necessary to include the clock period in this case. This also explains why the clock period is not included in either case for hold slack check. It can be seen that the reference of (t=0) only affects setup check, not hold check in single cycle based data transfer.

Single Clock Cycle based Setup and Hold Slack Analysis

Most digital circuits use single cycle timing, which means that it takes one clock cycle for data to propagate from source to destination. Static timing analysis tools usually do not know the exact number of cycles required for a signal to reach its destination. By default, most static timing analysis tools perform single cycle based analysis. There are only two cases for setup and hold slack analysis. Primary input or inout to register and register to register.

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Register to Register Slack Analysis

This is the most difficult case since the starting register and ending register may or may not have the same clock. The following three cases are investigated: Single-clock and single phase for both registers, single-clock and two-phase, and two-clocks and multiple frequencies.

Single Clock and Single phase

In this case, data is launched at the active-edge of the source register, and captured at the active edge (one cycle later) of the destination register. With respect to the active edge of the destination register, the latest data arrives with be that launched by the previous active clock edge at the source register. The hold time will be analyzed using the shortest data path with respect to the same active edge.

C.L.

source register

C.L.

destination register

clock

For setup analysis, the latest arrival data is used, such data is launched by the previous active edge of the clock. After the active edge at the destination register, the hold slack is calculated with respect to the same clock edge seen by the source register.
data launched by this edge is used for setup check data launched by this edge is used for hold check clock at source register

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Single Clock and multiple phases

Different registers may use either the non-inverted or inverted version of the same clock source. Between a source register and destination register, the phase difference can be anything between none and totally out of phase. If the phase difference is zero, then it degenerates to the previous case.

Comb .L. phase 1 phase 2

source reg

C.L.

dest. reg

When the source register and destination register do not have the same phase, there can be three cases: they are totally out of phase, the destination is ahead of the source register or the source register is ahead of the destination register.

T/2 - t

T/2 + t

differ by > T/2 differ by T/2

T/2

destination clock

The left pointing arrows point to the launching active clock edges from the source registers. The right pointing arrows point to the active clock edges for the hold time check edges. In each case, the setup and hold slack calculation need to be adjusted. When the source and destination registers are out of phase (the source is T/2 ahead of the destination clock edge), the following can be used to calculate the setup and hold slacks: setup slack = T/2 + minimum clock path maximum data path setup hold slack = minimum data path maximum clock path hold + T/2 When the active edge of the source register is (T/2 + t) ahead of the active edge of the destination clock, the following can be used to calculate the setup and hold slack:

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Setup slack = T/2 + t + minimum clock path maximum data path setup Hold slack = minimum data path maximum clock path hold + T/2 - t When the active edge of the source is (T/2 - t) ahead of the active edge of the destination clock, the following can be used to calculate the setup and hold slack: Setup slack = T/2 - t + minimum clock path maximum data path setup Hold slack = minimum data path maximum clock path hold + T/2 + t

Multiple Clocks and Multiple phases

Some designs have multiple clocks with different frequencies. The general method is to meet the most restrictive of all setup and hold relations. The multiplier used can be different depending on the source clock frequency and destination clock frequency. Given that the clocks are properly described, a static timing analyzer can usually detect the path properly. The following diagram shows a general case where the source and destination registers are controlled by either the same or different clocks. Also, it is assumed that the frequency of clkA is 3 times that of clkB in the following two diagrams.

C.L. clkA

R1A

R2A

C.L. C.L. clkB R1B R2B

The following diagram shows setup and hold relations for R1A to R2B and R1B to R2A:

clkA
setup hold

clkB

clkB

setup

hold

setup & hold relations for R1B to R2A

clkA

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All the above diagrams have assumed that a single clock cycle is used to launch and capture the data. If it is known that multiple clock cycles are needed to for data to reach from one register to another, the setup and hold relations will be different. The following two examples use the delta delay method so that the clock period is used in the setup slack analysis.

Example 1: This example shows setup margin calculation for a given simple circuit. The timing parameters are as following: The clock period is 40 For both flip flops, setup = 10, hold = 5, clock q rise and fall are: (4,15) and (3,12) The NOR gate has output rise and output fall (3,15) and (4,11) The buffers have output rise and output fall times (4,7) and (2,8)
Setup slack for data fall on the second register. din FF1 clk Q rise (4,15) fall (3,12) b4 b2 rise (4, 7) fall (2, 8) clock b1 rise (4, 7) fall (2, 8) b3 rise (4, 7) fall (2, 8)

FF2 clk Q rise (4,15) fall (3,12)

dout

In this case, both data path and clock path originate from the clock port. The first buffer b1 is common to both data path and clock path. Since the setup margin takes the difference of data path and clock path, we may choose either the maximum or the minimum data for the common gates in the two paths. We choose tRmin=4 for this case. First, calculate the paths for data fall transition at the input of the destination register: The minimum clock path = tRmin(b1) + tRmin(b3) =4+4=8 The maximum data path =

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tRmin(b1) + tRmax(b2) + CQ(FF1)Rmax + tFmax(b4) = 4 + 7 + 15 + 11 = 37 Setup slack (data fall) = T + minimum clock path maximum data path setup = 40 + 8 37 10 = 1ns When calculate the setup slack for data rise, the clock path is the same and the data path delay used will be different. Namely, we need different values for the register FF1 and the NOR gate b4. The minimum clock path = tRmin(b1) + tRmin(b3) =4+4=8 The maximum data path = tRmin(b1) + tRmax(b2) + CQ(FF1)Fmax + tRmax(b4) = 4 + 7 + 12 + 15 = 38 Setup slack (data rise) = T + minimum clock path maximum data path setup = 40 + 8 38 10 = 0 ns Example 2: This example shows hold margin (slack) calculation for the same circuit:
din Data Hold Slack (margin) for data fall R: 3, 15 FF1 F: 4, 11 R: 4, 7 F: 2, 8 b2 R:4,15 F:3,12 b4

FF2 R:4,15 F:3,12 dout

clock

R: 4, 7 F: 2, 8 b1

R: 4, 7 F: 2, 8 b3

For data fall on register FF2, we have the following numbers: The maximum clock path = tRmax(b1) + tRmax(b3) = 7 + 7 = 14 The minimum data path = tRmax(b1) + tRmin(b2) + CQ(FF1)Rmin + tFmin(b4) = 7 + 4 + 4 + 4 = 19 hold slack (data fall) = minimum data path maximum clock path hold = 19 14 5 = 0 ns

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For data rise on register FF2, the delay values for block b4 and register FF1 will have to be different. we have the following numbers: The maximum clock path = tRmax(b1) + tRmax(b3) = 7 + 7 = 14 The minimum data path = tRmax(b1) + tRmin(b2) + CQ(FF1)Fmin + tRmin(b4) = 7 + 4 + 3 + 3 = 17 hold slack (data rise) = minimum data path maximum clock path hold = 17 14 5 = -2 ns Obviously, there is a hold violation for the given circuit, and a static TA shall report such problem.

Multiple Clocks and Arbitrary Phases

If two clocks are totally unrelated for the launching and capture flip-flop, and they do not have a fixed relationship (if one is not multiple of the other one), timing analysis can be difficult. One approach is to have synchronization circuitry to make data transfer more reliable.

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Primary Input/Inout to Register Slack Analysis

This is very similar to the register to register paths. The minimum and maximum paths are calculated for both the clock and data starting from the primary inputs. Assuming single cycle data transfer, the amount of time it took the signals to arrive at the primary inputs must be known. This must be added to clock and data paths. The clock path and data path can then be used directly to calculate the setup and hold slacks.

data path

FF

clock path

The equations for setup and hold slacks are the same. However, The starting points of the paths are from the primary inputs (specified by set_input_delay in case of Synopsys tools). Setup slack = Clock Period + minimum clock path maximum data path setup Hold slack = minimum data path maximum clock path hold

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Performing Timing Analysis for PI to PO

Since the end point of the timing path is a non-register element, only slack analysis for combinational circuit needs to be performed.

Combinational gates

The following equation can be used: Slack = required data arrival time actual data arrival time On the input side, the time data arrival time is needed and on the output side, the data required time is needed.

Performing Timing Analysis for R to PO

Same as the preview case, only slack analysis for combinational circuit needs to be performed.

FF Combinational Data Path Clock path

The equation is: Slack = required data arrival time actual data arrival time When calculating the path delay, clock path, clock to Q for FF and the combinational path delay are all used to get the actual data arrival time.

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False Paths Elimination

Static timing tools tend to be overly pessimistic and they report timing paths or violations that do not exist. In case that the pessimistic results still meet the target performance requirement, the designers do not have to do anything. Otherwise, it is necessary to examine all the violation to determine if they are real violations. When tracing a circuit, a static timing analyzer assumes that the topological longest and shortest paths can be sensitized by setting other non-controlling inputs along the paths to appropriate logic values so that a transition can be propagated through the path. If the assumption turned out to be not true, then the paths are false paths. One type of false paths are those that can never happen such as the case shown below.

40 din

40

D 20 20

sel clk

In this case, the tool needs to know that the topological longest path (40 + 40) cannot happen by using a justification algorithm like the one discussed in the D-Algorithm for test vector generation. Another way is to de-select a path manually. Note that a minimum of two points is needed to specify the de-selection of the path. In other cases, the path is feasible, but it may take more than one clock cycle to complete the propagation of a signal. A multiple cycle path is typically characterized by a starting point, an ending point and a number of mid-points. The number of cycles is not limited to an integer, but most tools do not allow fraction of a cycle. Multiple cycle are typically cannot be detected by the tool automatically. The designer needs to specify all the multiple cycle paths before timing analysis. False paths and multiple cycle paths are also referred to as timing exceptions.

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Latch Based Static Timing Analysis

Latch based designs are harder to analysis, design & test. However, when properly done, the system can be extremely high performance. Some of the best-known high performance micro-processors are latch based. Cycle-stealing or time borrowing is one of the few features a static timing analysis tool must support for latch based design. Since latch based designs are not encouraged by educational institutions as well as the industry (EDA tools vendors specially), static timing analysis for latch-based design is not as well understood by designers as Flip-flop based designs. From the latch timing models, it can be seen that the setup/hold checks are performed at the edge the latch is closing (into the latch mode). When data arrives at the input of a latch, it can be in one of the three situations: Before the latch opens (going into transparent mode) The latch is already open (transparent mode) Just closed (just went into latch mode)

The following diagram shows the different scenarios:

Data launching from Stage 1 Assuming no time borrow from preview stage.
Stage 1 Latch Launch for Stage 2

If data from Stage 1 arrives at Ta, Slack = Tb Ta (no violation) If data from Stage 1 arrives at Tc, Slack = 0. Time Borrow (cycle stealing) occurs: Ta Time borrowed: Tc Tb If data from Stage 1 arrives at Td: Slack = Td Te (violation)

Stage 2 Latch Capture for Stage 1 Launch for Stage 3)

Tb

Tc

Td

Te

Data launching from Stage 2 Time is being borrowed here. Stage 3 Latch Capture for Stage 2

Describing Clock waveforms for Latch based Design

It should be noted that it is very important to describe the clock waveform for latch based designs since both the close and open edges of the clocks are used. This is not true for designs based on edge-triggered flip-flops with a single clock domain or with multiple domains but data do not run across the domains.

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Preventing Time Borrowing

Time borrowing occurs within the same clock cycle. This requires the launching and capturing latches be using the same phase of the same clock. When the clocks of the launching and capturing latches are out of phase, time borrowing is not to happen. Even both launching and capturing latches are the same, time borrowing can be typically disabled as a tools option.

Determining clock frequency and amount of time for borrowing

Latch based design allows designer to data path longer than the clock cycle time. This made possible by taking some available time from the subsequent shorter paths. The concept is simple, but in reality, determining what frequency the circuit can run at and how many stages timing borrowing are allowed is very difficult. In addition, the following items make the situation even worse: Multiple clocks used to launch and capture data. Multiple cycle paths False paths

The following first simple example shows timing borrowing concepts in some details. The second one shows the same example except the latches are replaced by edgetriggered flip-flops. Note: Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times. Since hold time slack calculation uses fastest data, time-borrowing typically does not affect hold slack calculation.

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Example 1 (zero cycle data transfer): Clock G Waveform & timing environments:
0 5 10

Data arrives at port D at 2 Data required at port Q at 8

D L1 1.15 L2 0.03 L3 Q

Latch Timing: G2Q = 0.18 D2Q = 0.16 setup = 0.08 hold = 0.07 Data Timing Diagram over one clock cycle: Time: 0 2 3 4 5
Valid data

10

D to L1: Data arrives at Latch (L1) at t = 2. Timing is met with Tborrow = 2 (slack = 0). L1 to L2: Next, the same data arrives at L1 output at (2 + 0.16 = 2.16). It continues to arrive at Latch (L2) at t = (2.16 + 1.15 = 3.31). Timing is met with Tborrow = 3.31 accumulative (slack = 0). L2 to L3: The same data arrives at L2 output at (3.31 + 0.16 = 3.47). It continues to arrive at Latch (L3) at t = (3.47 + 0.03 = 3.5). Timing is met with Tborrow = 3.50 accumulative (slack = 0). L3 to Q: Note that here, data is assumed to be needed for the next clock cycle. So that data needs to be available at Q at (T 2 = 8). Since time borrowing occurred, data arrives at Q at t = (3.5 + 0.16 = 3.66). The slack time at Q is: (8 3.66 = 4.34)

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Example 2 (single cycle data transfer): Clock G Waveform & timing environments:
0 5 10

Data arrives at port D at 2 Data required at port Q at 8

D F1 1.15 F2 0.03 F3 Q

D flip-flop Timing: G2Q = 0.16 setup = 0.11 hold = 0.05 Data Timing Diagram over one clock cycle: Time: 0 2 3 4 5
Valid data

10

D to F1: Data arrives at FF (F1) at t = 2. Add data setup time at F1: 2.0 + 0.11 = 2.11. Data is captured on the next cycle. Slack time = 10 2.11 = 7.89 F1 to F2: Data starts from G (clock) arriving F1 output at t = 0.16. Continues to arrive at F2 input at t = 0.16 + 1.15 = 1.31. Add the setup time of F2: 1.31 + 0.11 = 1.42. Data is captured on the next cycle when t = 10. Slack time = 10 1.42 = 8.58. F2 to F3: Data arrives from F2 at t = (0.16 + 0.03 = 0.19). Add the setup time of F3: 0.19 + 0.11 = 0.30. Data is captured on the next cycle when t = 10. Slack time = 10 0.3 = 9.7. F3 to Q: Data is captured at Q one clock cycle later. Since a percentage of the time is given to data transfer to off chip (2 in this case), data required time is 8. The only time data takes here is the G2Q delay (0.16). Slack Time = 8 0.16 = 7.84.

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Commonly Used Terms and Definitions

Divided Clock A clock divider circuit generates a new clock signal with a lower frequency than the original clock signal. Gated Clock A gated clock signal occurs when the clock network contains logic other than inverters and buffers. Clock Skew Clock skew is the difference in rise or fall edges at two register clock pins. The potential for skew can be modeled before layout by using plus and minus uncertainty values. False Path A timing path in the design that cannot propagate a signal is referred to as false path. Some tools can detect false paths automatically others allow users to mark them interactively. Multi-cycle Path A timing path in the design that is not expected to propagate a signal in one cycle is referred to as multicycle path. By default, all paths are assumed to be single cycle paths. Some tools allow fractional number of cycles others may require integer number of clock cycles for timing analysis. Slack The amount of margin by which maximum or minimum path delay requirement is met is referred to as slack time. Positive slack indicates that the requirement is met; negative slack time indicates a violation. Violation Timing violation is an indicator that a timing constraint is not met. A setup violation occurs when a timing path is longer than its maximum delay target. A hold violation occurs when a timing path is shorter than its minimum delay target. A violation is indicated by a negative slack value.

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